PCM66P

PCM66P BURR-BROWN | Alldatasheet

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Technical content

16-Bit CMOS Monolithic Audio DIGITAL-TO-ANALOG CONVERTER FPO PCM66P FPO International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Tel: (602) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (602) 889-1510 • Immediate Product Info: (800) 548-6132

FEATURES

l LOW COST 16-BIT 2-CHANNEL CMOS MONOLITHIC D/A CONVERTER l SINGLE SUPPLY +5V OPERATION l 50mW POWER DISSIPATION l GLITCH-FREE VOLTAGE OUTPUTS l LOW DISTORTION: –86dB max THD + N l COMPLETE WITH REFERENCE l SERIAL INPUT FORMAT l SINGLE OR DUAL DAC MODE OPERATION l PLASTIC 20-PIN SOIC PACKAGE Reference 16-Bit V DACOUT Integrate & Hold Amp Integrate & Hold AmpSerial-to-Parallel Shift Register Control Logic V A L CH Out V R CH Out D REF COM OUT COM CC V (+5V) DATA SDM SEL LRDAC LRCLK WDCLK CLK

DESCRIPTION

The PCM66P is a low cost, dual output 16-bit CMOS digital-to-analog converter. The PCM66P features true glitch-free voltage outputs, internal reference and re- quires only a single +5V supply. Total power dissipa- tion is less than 50mW max. Low maximum Total Harmonic Distortion + Noise (–86dB max; PCM66P- J) is 100% tested. Either one or two channel output modes are fully user selectable. The PCM66P comes in a space-saving 20-pin plastic SOIC package. PCM66P accepts a serial data input format and is compatible with other Burr-Brown PCM products such as the industry standard PCM56P. © 1990 Burr-Brown Corporation PDS-1051D Printed in U.S.A. October, 1993

NOTES: (1) Binary Two’s Complement coding. (2) Ratio of (DistortionRMS + NoiseRMS ) / SignalRMS . (3) D/A converter output frequency/signal level (on both left and right channels). (4) D/A converter sample frequency (4 x 44.1kHz; 4 times oversampling per channel). (5) Offset error at bipolar zero. (6) Ratio of output at BPZ (Bipolar Zero) to the full scale range using 20kHz low pass filter in addition to an A-weighted filter. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent right or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. SPECIFICATIONS ELECTRICAL All specifications at 25°C, and +VCC = +5V unless otherwise noted. PCM66P AND PCM66P, J PARAMETER CONDITIONS MIN TYP MAX UNITS RESOLUTION 16 Bits DYNAMIC RANGE 96 dB DIGITAL INPUT TTL Compatible CMOS Logic Family Logic Level: VIH IIH = +40µA max +2.4 +5.25 V VIL IIL = –40µA max 0 0.8 V Data Format Serial BTC(1) Input Clock Frequency 8.5 MHz DYNAMIC CHARACTERISTICS TOTAL HARMONIC DISTORTION + N (2) PCM60P/66P: f = 991Hz (0dB)(3) fS = 176.4kHz(4) –88 –82 dB f = 991Hz (–20dB) f S = 176.4kHz –68 dB f = 991Hz (–60dB) f S = 176.4kHz –28 dB PCM60P-J/66P-J: f = 991Hz (0dB) f S = 176.4kHz –92 –86 dB f = 991Hz (–20dB) f S = 176.4kHz –68 dB f = 99lHz (–60db) f S = 176.4kHz –28 dB CHANNEL SEPARATION +80 +85 dB TRANSFER CHARACTERISTICS ACCURACY Gain Error V OUT = 2.6 ±2 ±10 % Gain Mismatch Channel to Channel ±1% Bipolar Zero Error(5) ±30 mV Gain Drift 0 °C to 70°C 100 ppm/ °C Warm-up Time 1 minute IDLE CHANNEL SNR (6) 20-20kHz with A-weighted filter ±90 dB ANALOG OUTPUT Output Range 2.6 Vp-p Output Impedance 2 Ω Short Circuit Duration To Be Determined Settling Time Suffieicnt to Meet 176.4kHz THD + N Specs Glitch Energy Meets All THD + N Specs Without External Output Deglitching POWER SUPPLY REQUIREMENTS +VCC Supply Voltage +4.75 +5 +5.25 V Supply Current +9.5 mA Power Dissipation V CC = +5V 50 mW TEMPERATURE RANGE Specification 0 +70 °C Operating –30 +70 °C Storage –60 +100 °C

1 Left/Right Clock LRCLK

2 Word Clock WDCLK

3 Clock Input CLK

4 Data Input DATA

5 No Connection NC

6 Digital Common D COM

7 Analog Common A COM

8 Left Channel V OUT L CH Out

9 Output Common V COM

10 Right Channel V OUT R CH Out

11 Analog Supply +V CC

12 Analog Supply +V CC

13 Reference Decouple C REF

14 Reference Sense V REF SENSE

15 Reference Output V REF

16 Analog Supply +V CC

17 Analog Supply +V CC

18 Digital Supply +V CC

19 Single DAC Mode SDM SEL

20 Left/Right DAC Select LRDAC

MODEL 1–24 25-99 100+ PCM66P $11.80 $10.40 $9.15 PCM66P-J 13.30 11.70 10.30 USA OEM PRICESORDERING INFORMATION PCM66P -X Basic Model Number P: Plastic Performance Grade Code ABSOLUTE MAXIMUM RATINGS PACKAGE INFORMATION (1) PACKAGE DRAWING MODEL PACKAGE NUMBER PCM66P 20-Pin SOIC 248 PCM66P, J 20-Pin SOIC 248 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. SERIAL LEFT RIGHT DATA WORD CHANNEL CHANNEL SDM SEL LRDAC LRCLCK WDCLK INPUT OUTPUT OUTPUT

0 X 0 0 Right Hold Hold

0 X 0 1 Right Integrate Hold

0 X 1 0 Left Hold Hold

0 X 1 1 Left Hold Integrate

1 0 0 1 Inhibited V COM Hold 1 0 1 0 Left V COM Integrate 1 0 1 1 Left V COM Integrate 1 1 0 0 Right V COM Hold 1 1 0 1 Right V COM Hold 1 1 1 0 Inhibited V COM Integrate 1 1 1 1 Inhibited V COM Integrate TABLE I. PCM66P Logic Truth Table. NOTE: Positive edge of CLK (P3) latches LRCLK (P1), WDCLK (P2), and DATA (P4). PIN FUNCTIONS THEORY OF OPERATION The PCM66P is a dual output, 16-bit CMOS digital-to-analog audio converter. The PCM66P, complete with internal refer- ence, has two glitch-free voltage outputs and requires only a single +5V power supply. Output modes using either one or two channels per DAC are user selectable. The PCM66P accepts a serial data input format that is compatible with other Burr- Brown PCM products such as the industry standard PCM56P. ONE DAC TWO-CHANNEL OPERATION Normally, the PCM66P is operated with a continuous clock input in a two-channel output mode. This mode is selected when SDM SEL is held low (single DAC mode select). Refer to the truth table shown by Table I for exact control logic relation- ships. Data for left and right channel output is loaded alternately into the PCM66P while the control logic switches the left and right output amplifiers between the appropriate integrate and hold modes. Data word latch- ing is controlled by WDCLK (word clock) and channel selection is made by LRCLK (left/right clock). Figure 1 shows the timing for the single DAC two-channel mode of operation. The block diagram in Figure 2 shows how a single DAC output provides switched output to both integrate and hold amplifiers. Output between left and right channels in this mode is not in phase. See Figure 3 for proper connection of the PCM66P in the two-channel DAC mode.

FIGURE 1. PCM66P Timing Diagram. NOTES: Single DAC Mode Select = 1; L/R DAC Select = 0 (Left DAC) or 1 (Right DAC).

block diagram of the production THD + N test setup. THD + N specification without use of external deglitchers. gral linearity in the DAC depending on the grade specified. individual output code can be guaranteed. weighted filter is applied to make this measurement. bipolar zero offset error, and temperature gain drift. FIGURE 4. THD + N Test Setup Diagram. TABLE II. PCM66P Input/Output Relationships.

P3 (CLK) P4 (DATA) P2 (WDCLK) P1 (LRCLK) 60ns min 15ns min 15ns min WDCLK DUTY CYCLE WDCLK is the input signal that controls when data is loaded and how long each output is in the integrate mode. It is therefore recommended that a 50% (high) duty cycle be maintained on WDCLK. This will ensure that each output will have enough time to reach its final output value, and that the output level of each channel will be within the gain mismatch specification. Refer to Figure 1 for exact timing relationships of WDCLK to CLK and LRCLK and the outputs of the PCM66P. The WDCLK can be high longer than 50%, as long as setup and hold times shown in Figure 5 are observed and the time high is roughly equivalent for both left and right channels. SETUP AND HOLD TIME The individual serial data bit shifts, the serial to parallel data transfer, and left/right control are triggered on positive CLK edges. The setup time required for DATA, WDCLK, and LRCLK to be latched by the next positive going CLK is 15ns minimum. A minimum hold time of 15ns is also required after the positive going CLK edge for each data bit to be shifted into the serial input register. Refer to Figure 5 for the timing relationship of these signals. MAXIMUM CLOCK RATE The 100% tested maximum clock rate of 8.47MHz for the PCM66P is derived by multiplying the standard audio sample rate of 44.1kHz times eight (4X oversampling times two channels) times the standard audio word bit length of 24 (44.1kHz x 4 x 2 x 24 = 8.47MHz). Note that this clock rate accommodates a 24-bit word length, even though only 16 bits are actually being used. “STOPPED-CLOCK” OPERATION The PCM66P is normally operated with a continuous clock input signal. If the clock is to be stopped between input data words, the last 16 bits shifted in are not actually shifted from the serial register to the latched parallel DAC register until the first clock after the one used to input bit 16 (LSB). This means the data is not shifted into the DHC latch until the start of the next 16-bit data word input, unless at least one additional clock accompanies the 16 used to serially shift in data in the first place. In either case, the setup and hold times for DATA, WDCLK, and LRCLK must still be observed. INSTALLATION The PCM66P only requires a single +5V supply. The +5V supply, however, is used in deriving the internal reference. It is therefore very important that this supply be as “clean” as possible to reduce coupling of supply noise to the outputs. If a good analog supply is available at greater than +5V, a zener diode can be used to obtain a stable +5V supply. A FIGURE 5. PCM66P Setup and Hold Timing Diagram. the analog ground plane as close to the PCM66P as possible. to 1 is the important factor here for proper circuit operation. pickup from surrounding circuitry.

APPLICATIONS

Probably the most popular use of the PCM66P is in applica- tions requiring single power supply operation. For example, the PCM66P is ideal for automotive compact disk (CD) and digital audio tape (DAT) playback units. To use a more complex bipolar DAC requiring ±5V supplies in the +12V application, for example, would require driving a stable “floating” ground and regulating the +12V to +10V. The single supply CMOS PCM66P would only require a +5V zener diode to regulate its 50mW max supply. The outputs could be AC coupled to the rest of the circuit for perfectly acceptable high dynamic performance. The PCM66P is ideal in any application requiring a minimum of additional cir- cuitry as well as ultra-low-power CMOS performance. Of course, the PCM66P is the D/A converter of choice in any application requiring very low power dissipation. Por- table battery powered test and measurement equipment re- quiring very low distortion digital to analog converters would be an ideal application for the CMOS PCM66P with its 50mW max power dissipation.