PCM5141PW

PCM5141 TI1 | Alldatasheet

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32-bit ∆Σ Modulator Current Segment DAC I/V Analog Mute Zero Data Detector PLL Clock Charge Pump VCom POR Clock Halt Detection Advanced Mute Control MCK BCK LRCK CAPP CAPM VNEG UVP/XSMT LINE OUT DOUT (I2S) (through any GPIO) PCM514x Programmable miniDSP MODE1 MS/MODE2 MOSI/SDA/ATT2 MC/SCL/ATT1 GPIO6/FLT MISO/ADR1/FMT GPIO Power Supply CPVDD (3.3V) AVDD (3.3V) DVDD (1.8V or 3.3V) GND Program RAM Digital Volume Control DIN (I2S) I/VCurrent Segment DAC Analog Mute SPI/I2C GPIO5/ATT0 GPIO4/MAST GPIO3/AGNS GPIO2/ADR2/DOUT UVP/ Reset PCM5141,PCM5142 www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 2VRMSDirectPath™ ,112/106dBAudioStereoDACwith32-bit,384kHzPCM Interface Check forSamples: PCM5141 ,PCM5142 1FEATURES TypicalPerformance (3.3VPower Supply) 23• Programmable miniDSP Parameter PCM5142 PCM5141

• Market-LeadingLow Out-of-BandNoise SNR 112dB 106dB
• SelectableDigital-FilterLatency and Dynamic Range 112dB 106dB Performance THD+N @ -1dBFS –93dB –92dB
• No DC BlockingCapacitorsRequired FullScaleOutput 2.1VRMS (GND center)
• IntegratedNegativeCharge Pump Normal 8× Oversampling DigitalFilterLatency:20tS
• InternalPop-Free ControlFor Sample-Rate Low Latency 8× Oversampling DigitalFilterLatency:3.5tS Changes Or Clock Halts Sampling Frequency 8kHz to384kHz
• IntelligentMuting System; SoftUp or Down System Clock Multiples(fSCK ):64,128,192,256,384,512, 768,1024,1152,1536,2048,3072;up to50 MHzRamp and Analog Mute For 120dB Mute SNR With Popless Operation
• IntegratedHigh-PerformanceAudio PLL With BCK ReferenceTo Generate SCK Internally
• Accepts 16-,24-,And 32-BitAudio Data Figure1. PCM514x FunctionalBlock Diagram space Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2System Two Cascade,AudioPrecisionaretrademarksofAudioPrecision. 3DirectPathisa trademarkofTexas,Instruments,Inc.. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2012,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

PCM5141,PCM5142 SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 www.ti.com This integratedcircuitcan be damaged by ESD. Texas Instrumentsrecommends thatallintegratedcircuitsbe handled with appropriateprecautions.Failuretoobserveproperhandlingand installationprocedurescan cause damage. ESD damage can rangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmay be more susceptibletodamage because verysmallparametricchanges couldcause thedevicenottomeet itspublishedspecifications. OTHER KEY FEATURES The PCM514x provides2.1VRMS ground centered• PCM Data Formats:I2S,Left-Justified,Right- outputs,allowingdesignersto eliminateDC blockingJustified,TDM capacitorson the output,as wellas externalmuting circuitstraditionallyassociatedwithsinglesupplyline• SPI or I2C Control drivers.• Softwareor Hardware Configuration The integratedlinedriversurpassesallothercharge-• Automatic Power-Save Mode When LRCK And pump based linedriversby supportingloadsdown toBCK Are Deactivated 1kΩ.By supportingloadsdown to1kΩ,thePCM514x• 1.8Vor 3.3VFailsafeLVCMOS DigitalInputs can essentiallydriveup to 10 productsin parallel,

• SingleSupply Operation: such as LCD TV, DVDR, AV Receivers. – 3.3VAnalog,1.8Vor 3.3VDigital The integratedPLL on the device removes the
• IntegratedPower-On Reset requirementfora system clock(commonly known as master clock),allowinga 3-wireI2S connectionand• Small 28-pinTSSOP Package reducingsystemEMI. APPLICATIONS In addition,the PLL is completelyprogrammable, allowingthe deviceto become the I2S clockmaster• A/V Receivers and drivea DSP serialportas a slave.The PLL also• DVD, BD Players acceptsa non-standardclock(up to 50MHz) as a
• HDTV Receivers source to generate the audio relatedclock (for example 24.576MHz).• ApplicationsRequiring2VRMS Audio Output Intelligentclockerrorand PowerSense undervoltage DESCRIPTION protectionutilizesa two levelmute system forpop- freeperformance.Upon clockerroror system powerThe PCM514x devices are a familyof monolithic failure,thedevicedigitallyattenuatesthedata(orlastCMOS integratedcircuitsthatincludea stereodigital- known good data),thenmutes theanalogcircuit.to-analogconverterand additionalsupportcircuitryin a smallTSSOP package. The PCM514x uses the Compared with existingDAC technology,thelatestgenerationof TI’s advanced segment-DAC PCM514x familyoffersup to20dB lowerout-of-bandarchitecture to achieve excellent dynamic noise,reducingEMI and aliasingin downstreamperformanceand improvedtolerancetoclockjitter. amplifiers/ADCs.(from traditional100kHz OBN measurements alltheway to3MHz).Members of the PCM514x familyintegratea fully programmable miniDSP core,allowingdevelopersto The PCM514x acceptsindustry-standardaudiodataintegratefilters,dynamic range controls,custom formatswith16- to 32-bitdata.Sample ratesup tointerpolatorsand otherdifferentiatingfeaturestotheir 384kHz aresupported.products. Table1.DifferencesBetween PCM514x Devices PartNumber Dynamic Range SNR THD PCM5142 112dB 112dB –93dB PCM5141 106dB 106dB –92dB

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PCM5141,PCM5142 www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 spacer DEVICE INFORMATION PCM514x pinassignments-1MODE1 tiedDVDD :SPI mode PCM514x (topview) Table2.PCM514x SPI mode TerminalFunctions TERMINAL I/O DESCRIPTION NAME PIN CPVDD 1 - Charge pump power supply,3.3V CAPP 2 O Charge pump flyingcapacitorterminalforpositiverail CPGND 3 - Charge pump ground CAPM 4 O Charge pump flyingcapacitorterminalfornegativerail VNEG 5 O Negativechargepump railterminalfordecoupling,-3.3V OUTL 6 O AnalogoutputfromDAC leftchannel OUTR 7 O AnalogoutputfromDAC rightchannel AVDD 8 - Analogpower supply,3.3V AGND 9 - Analogground VCOM output(Optionalmode selectedby register;defaultsettingisVREF mode.)When in VCOM 10 O VREF mode (default),thispintiestoGND. When inVCOM mode, decouplingcapacitorto GND isrequired. MOSI 11 I InputdataforSPI(1) MC 12 I InputclockforSPI(1) GPIO5 13 I/O Generalpurposedigitalinputand outputport GPIO4 14 I/O Generalpurposedigitalinputand outputport GPIO3 15 I/O Generalpurposedigitalinputand outputport GPIO2 16 I/O Generalpurposedigitalinputand outputport MODE1 17 I Mode controlselectionpin(1)

• MODE1=Low, MODE2=Low :Hardwiredmode
• MODE1=Low, MODE2=High :I2C modeMS (MODE2) 18 I
• MODE1=High :SPI mode, MODE2 pinchanges MS pin(chipselectfor SPI) GPIO6 19 I/O Generalpurposedigitalinputand outputport SCK 20 I System clockinput(1) BCK 21 I/O Audiodatabitclockinput(slave)oroutput(master)(1) DIN 22 I Audiodatainput(1) LRCK 23 I/O Audiodataword clockinput(slave)oroutput(master)(1) PrimaryoutputdataforSPI readbackMISO (GPIO1) 24 I/O Secondary;generalpurposedigitalinput/outputportcontrolledby register XSMT 25 I Softmute control(1)Softmute (Low)/softun-mute(High) (1) FailsafeLVCMOS Schmitttriggerinput. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:PCM5141 PCM5142

PCM5141,PCM5142 SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 www.ti.com Table2.PCM514x SPI mode TerminalFunctions(continued) TERMINAL I/O DESCRIPTION NAME PIN LDOO 26 - Internallogicsupplyrailterminalfordecoupling,1.8V DGND 27 - Digitalground DVDD 28 - Digitalpower supply,3.3Vor1.8V

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PCM5141,PCM5142 www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 PCM514x pinassignments-2MODE1 tiedDGND and MODE2 tiedDVDD :I2C mode PCM514x (topview) Table3.PCM514x I2C mode TerminalFunctions TERMINAL I/O DESCRIPTIONS NAME PIN CPVDD 1 - Charge pump power supply,3.3V CAPP 2 O Charge pump flyingcapacitorterminalforpositiverail CPGND 3 - Charge pump ground CAPM 4 O Charge pump flyingcapacitorterminalfornegativerail VNEG 5 O Negativechargepump railterminalfordecoupling,-3.3V OUTL 6 O AnalogoutputfromDAC leftchannel OUTR 7 O AnalogoutputfromDAC rightchannel AVDD 8 - Analogpower supply,3.3V AGND 9 - Analogground VCOM output(Optionalmode selectedby register;defaultsettingisVREF mode.)When VCOM 10 I inVREF mode (default),thispintiestoGND. When inVCOM mode, decouplingcapacitor toGND isrequired. SDA 11 I/O InputdataforI2C (1)(2) SCL 12 I InputclockforI2C (2) GPIO5 13 I/O Generalpurposedigitalinputand outputport GPIO4 14 I/O Generalpurposedigitalinputand outputport GPIO3 15 I/O Generalpurposedigitalinputand outputport ADR2 16 I 2nd LSB addressselectbitforI2C MODE1 17 I Mode-controlselectionpins(2)

• MODE1=Low, MODE2=Low :Hardwiredmode
• MODE1=Low, MODE2=High :I2C modeMODE2 18 I
• MODE1=High :SPI mode, MODE2 pinchanges MS pin(chipselect forSPI) GPIO6 19 I/O Generalpurposedigitalinputand outputport SCK 20 I System clockinput(2) BCK 21 I/O Audiodatabitclockinput(slave)oroutput(master)(2) DIN 22 I Audiodatainput(2) LRCK 23 I/O Audiodataword clockinput(slave)oroutput(master)(2) ADR1 24 I LSB addressselectbitforI2C XSMT 25 I Softmute control:Softmute (Low)/softun-mute(High)(2) LDOO 26 - Internallogicsupplyrailterminalfordecoupling,1.8V DGND 27 - Digitalground DVDD 28 - Digitalpower supply,3.3Vor1.8V (1) Open-drainconfigurationinoutmode. (2) FailsafeLVCMOS Schmitttriggerinput. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:PCM5141 PCM5142

PCM5141,PCM5142 SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 www.ti.com PCM514x pinassignments-3MODE1 tiedDGND and MODE2 tiedDGND :Hardwired mode PCM514x (topview) The H/W mode has digitalgainand attenuationlevelcontrolby decodingexternalATT2 (11pin),ATT1 (12pin), and ATT0 (pin13).Table1 shows thepinsused tosetgainand attenuationlevels. Table4.Gain and AttenuationinHardware Mode ATT pincondition(ATT2 :ATT1 : Gain and AttenuationlevelATT0) (0 0 0 ) 0 dB (0 0 1 ) + 3 dB (0 1 0 ) + 6 dB (0 1 1 ) + 9 dB (1 0 0 ) + 12 dB (1 0 1 ) + 15 dB (1 1 0 ) -6 dB (1 1 1 ) -3 dB Table5.PCM514x Hardwired mode TerminalFunctions Terminal I/O Description Name Pin CPVDD 1 - Charge pump power supply,3.3V CAPP 2 O Charge pump flyingcapacitorterminalforpositiverail CPGND 3 - Charge pump ground CAPM 4 O Charge pump flyingcapacitorterminalfornegativerail VNEG 5 O Negativechargepump railterminalfordecoupling,-3.3V OUTL 6 O AnalogoutputfromDAC leftchannel OUTR 7 O AnalogoutputfromDAC rightchannel AVDD 8 - Analogpower supply,3.3V AGND 9 - Analogground DEMP 10 I De-emphasiscontrolfor44.1kHzsamplingrate(1):Off(Low)/On (High) ATT2 11 I Digitalgainand attenuationcontrolpin(1) ATT1 12 I Digitalgainand attenuationcontrolpin(1) ATT0 13 I Digitalgainand attenuationcontrolpin I2S Masterclockselectpin:Master(High)BCK/LRCK outputs,Slave(Low)BCK/LRCKMAST 14 I inputs AGNS 15 I Analoggainselector:0dB 2VRMS output(Low),-6dB 1VRMS output(High) GPO 16 O GeneralPurposeOutput(Low level) (1) FailsafeLVCMOS Schmitttriggerinput.

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PCM5141,PCM5142 www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 Table5.PCM514x Hardwired mode TerminalFunctions(continued) Terminal I/O Description Name Pin MODE1 17 I Mode-controlselectionpins(2)

• MODE1=Low, MODE2=Low :Hardwiredmode
• MODE1=Low, MODE2=High :I2C modeMODE2 18 I
• MODE1=High :SPI mode, MODE2 pinchanges MS pin(chipselect forSPI) FLT 19 I Filterselect:Normal latency(Low)/Low latency(High) SCK 20 I System clockinput(2) BCK 21 I/O Audiodatabitclockinput(2) DIN 22 I Audiodatainput(2) LRCK 23 I/O Audiodataword clockinput(2) FMT 24 I Audioformatselection:I2S (Low)/Leftjustified(High) XSMT 25 I Softmute control:Softmute (Low)/softun-mute(High)(2) LDOO 26 - Internallogicsupplyrailterminalfordecoupling,1.8V DGND 27 - Digitalground DVDD 28 - Digitalpower supply,3.3Vor1.8V (2) FailsafeLVCMOS Schmitttriggerinput. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:PCM5141 PCM5142

PCM5141,PCM5142 SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 www.ti.com ABSOLUTE MAXIMUM RATINGS overoperatingfree-airtemperaturerange(unlessotherwisenoted) VALUE UNIT AVDD, CPVDD, DVDD –0.3to3.9 SupplyVoltage LDOO wtihDVDD at1.8V(See TypicalApplicationsCircuits) –0.3to2.25 DVDD at1.8V –0.3to2.25 V DigitalInputVoltage DVDD at3.3V –0.3to3.9 AnalogInputVoltage –0.3to3.9 OperatingTemperatureRange –25 to85 StorageTemperatureRange –65 to150 THERMAL CHARACTERISTICS overoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT θJA ThetaJA HighK 72.2 θJC ThetaJC Top 17.5 θJB ThetaJB 35.0 ºC/W ψJT PsiJT 0.4 ψJB PsiJB 34.5

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PCM5141,PCM5142 www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012

ELECTRICAL CHARACTERISTICS

AllspecificationsatTA = 25°C, AV DD = CPV DD = DV DD = 3.3V,fS = 48kHz,systemclock= 512fS and 24-bitdataunless otherwisenoted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Resolution 16 24 32 Bits Data Format (PCM Mode) Audiodatainterfaceformat I2S,leftjustified,rightjustifiedand TDM Audiodatabitlength 16,24,32-bitacceptable Audiodataformat MSB First,2s Complement fS (1) Samplingfrequency 8 384 kHz Clocks System clockfrequency 64,128,192,256,384,512,768,1024,1152, 1536,2048,or3072 fSCK ,up to50Mhz Clockdivideruses fractionaldivide 6.7 20 MHzD > 0,P=1PLL InputFrequency (SCL ClockFrequency400 kHz) Clockdivideruses integerdivide 1 20 MHzD = 0,P=1 DigitalInput/Output LogicFamily:3.3VLVCMOS compatible VIH 0.7×DV DD Inputlogiclevel V VIL 0.3×DV DD IIH VIN = VDD 10 Inputlogiccurrent µA IIL VIN = 0V –10 VOH IOH = –4mA 0.8×DV DD Outputlogiclevel VVOL IOL = 4mA 0.22×DV D D LogicFamily1.8VLVCMOS compatible VIH 0.7×DV DD Inputlogiclevel V VIL 0.3×DV DD IIH VIN = VDD 10 Inputlogiccurrent µA IIL VIN = 0V –10 VOH IOH = –2mA 0.8×DV DD Outputlogiclevel VVOL IOL = 2mA 0.22×DV D D (1) One sample timesidefinedas thereciprocalofthesamplingfrequency.1tS = 1/fS Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:PCM5141 PCM5142

PCM5141,PCM5142 SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) AllspecificationsatTA = 25°C, AV DD = CPV DD = DV DD = 3.3V,fS = 48kHz,systemclock= 512fS and 24-bitdataunless otherwisenoted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Dynamic Performance (PCM Mode) (2)(3)(Valuesshown fortwo devicesPCM5142 /PCM5141) fS = 48kHz –93 /–92 –83 /–82 THD+N at-1dB (3) fS = 96kHz –93 /–92 fS = 192kHz –93 /–92 Dynamic range(3) EIAJ,A-weighted,fS = 48kHz 106 /100 112 /106 EIAJ,A-weighted,fS = 96kHz 112 /106 EIAJ,A-weighted,fS = 192kHz 112 /106 Signal-to-noiseratio(3) EIAJ,A-weighted,fS = 48kHz 112 /106 dB EIAJ,A-weighted,fS = 96kHz 112 /106 EIAJ,A-weighted,fS = 192kHz 112 /106 Signaltonoiseratiowithanalog EIAJ,A-weighted,fS = 48kHz 113 123 mute(3)(4) EIAJ,A-weighted,fS = 96kHz 113 123 EIAJ,A-weighted,fS = 192kHz 113 123 ChannelSeparation fS = 48kHz 100 /95 109 /103 fS = 96kHz 100 /95 109 /103 fS = 192kHz 100 /95 109 /103 (2) Filtercondition:THD+N: 20Hz HPF, 20kHz AES17 LPF Dynamic range:20Hz HPF, 20kHz AES17 LPF, A-weightedSignal-to-noise ratio:20Hz HPF, 20kHz AES17 LPF, A-weightedChannelseparation:20Hz HPF, 20kHz AES17 LPF Analogperformancespecifications aremeasured usingtheSystem Two Cascade™ audiomeasurement systemby AudioPrecision™ intheRMS mode. (3) Outputloadis10kΩ,with470Ω outputresistorand a 2.2nFshuntcapacitor(seerecommended outputfilter). (4) AssertXSMT orbothL-chand R-ch PCM dataareBPZ

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PCM5141,PCM5142 www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 ELECTRICAL CHARACTERISTICS (continued) AllspecificationsatTA = 25°C, AV DD = CPV DD = DV DD = 3.3V,fS = 48kHz,systemclock= 512fS and 24-bitdataunless otherwisenoted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Analog Output Outputvoltage 2.1 VRMS Gain error –6 ±2.0 6 % ofFSR Gain mismatch,channel-to- –6 ±0.5 6 % ofFSRchannel Bipolarzeroerror Atbipolarzero –5 ±1.0 5 mV Load impedance 1 kΩ FilterCharacteristics–1:Normal (8x) Pass band 0.45fS Stopband 0.55fS Stopband attenuation –60 dB Pass-bandripple ±0.02 Delaytime 20tS s FilterCharacteristics–2:Low Latency (8x) Pass band 0.47fS Stopband 0.55fS Stopband attenuation –52 dB Pass-bandripple ±0.0001 Delaytime 3.5tS s FilterCharacteristics–3:Asymmetric FIR (8x) Pass band 0.40fS Stopband 0.72fS Stopband attenuation –52 dB Pass-bandripple ±0.05 Delaytime 1.2tS s FilterCharacteristics–4:High-Attenuation(8x) Pass band 0.45fS Stopband 0.45fS Stopband attenuation –100 dB Pass-bandripple ±0.0005 Delaytime 33.7tS s Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:PCM5141 PCM5142

PCM5141,PCM5142 SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) AllspecificationsatTA = 25°C, AV DD = CPV DD = DV DD = 3.3V,fS = 48kHz,systemclock= 512fS and 24-bitdataunless otherwisenoted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Power Supply Requirements DV DD Digitalsupplyvoltage TargetDV DD = 1.8V 1.65 1.8 1.95 VDC DV DD Digitalsupplyvoltage TargetDV DD = 3.3V 3.0 3.3 3.6 AV DD Analogsupplyvoltage 3.0 3.3 3.6 VDC CPV DD Charge-pump suplyvoltage 3.0 3.3 3.6 fS = 48kHz,InputisBipolarZerodata 11 14 IDD DV DD supplycurrentat1.8V(5) fS = 96kHz,InputisBipolarZerodata 12 mA fS = 192kHz,InputisBipolarZerodata 14 fS = 48kHz,Inputis1kHz -1dBFS data 11 14 IDD DV DD supplycurrentat1.8V(6) fS = 96kHz,Inputis1kHz -1dBFS data 12 mA fS = 192kHz,Inputis1kHz -1dBFS data 14 IDD DV DD supplycurrentat1.8V(7) fS = N/A,Power Down Mode 0.3 0.6 mA fS = 48kHz,InputisBipolarZerodata 12 15 IDD DV DD supplycurrentat3.3V(5) fS = 96kHz,InputisBipolarZerodata 13 mA fS = 192kHz,InputisBipolarZerodata 15 fS = 48kHz,Inputis1kHz -1dBFS data 12 15 IDD DV DD supplycurrentat3.3V(6) fS = 96kHz,Inputis1kHz -1dBFS data 13 mA fS = 192kHz,Inputis1kHz -1dBFS data 15 IDD DV DD supplycurrentat3.3V(7) fS = N/A,Power Down Mode 0.5 0.8 mA fS = 48kHz,InputisBipolarZerodata 11 16 ICC AV DD /CPV DD SupplyCurrent(5) fS = 96kHz,InputisBipolarZerodata 11 mA fS = 192kHz,InputisBipolarZerodata 11 fS = 48kHz,Inputis1kHz -1dBFS data 24 32 ICC AV DD /CPV DD SupplyCurrent(6) fS = 96kHz,Inputis1kHz -1dBFS data 24 mA fS = 192kHz,Inputis1kHz -1dBFS data 24 ICC AV DD /CPV DD SupplyCurrent(7) fS = N/A,Power Down Mode 0.2 0.4 mA fS = 48kHz,InputisBipolarZerodata 59.4 78 Power Dissipation,DV DD = 1.8V(5) fS = 96kHz,InputisBipolarZerodata 61.2 mW fS = 192kHz,InputisBipolarZerodata 64.8 fS = 48kHz,Inputis1kHz -1dBFS data 99 130.8 Power Dissipation,DV DD = 1.8V(6) fS = 96kHz,Inputis1kHz -1dBFS data 100.8 mW fS = 192kHz,Inputis1kHz -1dBFS data 104.4 Power Dissipation,DV DD = 1.8V(7) fS = N/A,Power Down Mode 1.2 mW fS = 48kHz,InputisBipolarZerodata 79.2 103 Power Dissipation,DV DD = 3.3V(5) fS = 96kHz,InputisBipolarZerodata 82.5 mW fS = 192kHz,InputisBipolarZerodata 89.1 fS = 48kHz,Inputis1kHz -1dBFS data 118.8 155 Power Dissipation,DV DD = 3.3V(6) fS = 96kHz,Inputis1kHz -1dBFS data 122.1 mW fS = 192kHz,Inputis1kHz -1dBFS data 128.7 Power Dissipation,DV DD = 3.3V(7) fS = N/A,Power Down Mode 2.3 4.0 mW (5) InputisBipolarZerodata. (6) Inputis1kHz -1dBFS data (7) Power Down Mode, withLRCK, BCK, and SCK haltedatLow level.

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-160 -140 -120 -100 -80 -60 -40 -20 0 5 10 15 20 Frequency [kHz] Amplitude [dB] -160 -140 -120 -100 -80 -60 -40 -20 0 5 10 15 20 Frequency [kHz] Amplitude [dB] -110 -90 -70 -50 -30 -10 -100 -80 -60 -40 -20 0 Input Level [dBFS] THD+N [dB] -110 -90 -70 -50 -30 -10 -100 -80 -60 -40 -20 0 Input Level [dBFS] THD+N [dB] PCM5141,PCM5142 www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 TYPICAL CHARACTERISTICS AllspecificationsatTA = 25°C, AV DD = CPV DD = DV DD = 3.3V,fS = 48kHz,systemclock= 512 fS and 24-bitdataunless otherwisenoted. PCM5141 THD+N vs PCM5142 THD+N vs vs vs InputLevel InputLevel Figure2. Figure3. PCM5141 FFT Plotat-60dB Input PCM5142 FFT Plotat-60dB Input Figure4. Figure5. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:PCM5141 PCM5142

-180 -160 -140 -120 -100 -80 -60 -40 -20 0 5 10 15 20 Frequency [kHz] Amplitude [dB] -180 -160 -140 -120 -100 -80 -60 -40 -20 0 5 10 15 20 Frequency [kHz] Amplitude [dB] -180 -160 -140 -120 -100 -80 -60 -40 -20 0 5 10 15 20 Frequency [kHz] Amplitude [dB] -180 -160 -140 -120 -100 -80 -60 -40 -20 0 5 10 15 20 Frequency [kHz] Amplitude [dB] PCM5141,PCM5142 SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) AllspecificationsatTA = 25°C, AV DD = CPV DD = DV DD = 3.3V,fS = 48kHz,systemclock= 512 fS and 24-bitdataunless otherwisenoted. PCM5141 FFT PlotatBPZ PCM5142 FFT PlotatBPZ Figure6. Figure7. PCM5141 FFT PlotatBPZ With AMUTE PCM5142 FFT PlotatBPZ With AMUTE Figure8. Figure9.

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-160 -140 -120 -100 -80 -60 -40 -20 0 50 100 150 200 250 300 Frequency [kHz] Amplitude [dB] -160 -140 -120 -100 -80 -60 -40 -20 0 50 100 150 200 250 300 Frequency [kHz] Amplitude [dB] PCM5141,PCM5142 www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 TYPICAL CHARACTERISTICS (continued) AllspecificationsatTA = 25°C, AV DD = CPV DD = DV DD = 3.3V,fS = 48kHz,systemclock= 512 fS and 24-bitdataunless otherwisenoted. PCM5141 FFT Plotat-60dB To 300kHz PCM5142 FFT Plotat-60dB To 300kHz Figure10. Figure11. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:PCM5141 PCM5142

3.3V GPIO Soft mute SPI DOUT 3.3V 3.3V SPI GPIO GPIO GPIO Pull up to 3.3V Chip select for SPI GPIO DVDD DGND LDOO XSMT MISO LRCK DIN BCK SCK GPIO6 MS MODE1 GPIO2 GPIO3 CPVDD CAPP CPGND CAPM VNEG OUTL OUTR AVDD AGND VCOM MOSI MC GPIO5 GPIO4 0.1 F 0.1 F C1 , C 2 = 2.2nF 0.1 F 2.2 F 2.2 F

0.1 F10 F

R1, R2, = 470 3.3V GPIO Soft mute SPI DOUT 3.3V 3.3V SPI GPIO GPIO GPIO Pull up to 3.3V Chip select for SPI GPIO DVDD DGND LDOO XSMT MISO LRCK DIN BCK SCK GPIO6 MS MODE1 GPIO2 GPIO3 CPVDD CAPP CPGND CAPM VNEG OUTL OUTR AVDD AGND VCOM MOSI MC GPIO5 GPIO4 0.1 F 0.1 F C1 , C 2 = 2.2nF 0.1 F 2.2 F 2.2 F R1, R2, = 470 +10 F PCM Audio Source 3.3V 2Vrms /1Vrms level select Soft mute Format select 0.1 F 3.3V 3.3V Gain Attenuation I2S Master/Slave Filter select De-emphasis R1, R2, = 470 C1 , C 2 = 2.2nF 2.2 F 2.2 F 0.1 F 0.1 F 1.8V Soft mute Format select 3.3V 3.3V Gain Attenuation Filter select Digital audio data out C1 , C 2 = 2.2nF 0.1 F 2Vrms /1Vrms level select I2S Master/Slave De-emphasis R1, R2, = 470 0.1 F 2.2 F 2.2 F CPVDD CAPP CPGND CAPM VNEG OUTL OUTR AVDD AGND DEMP ATT2 ATT1 ATT0 MAST DVDD DGND LDOO XSMT FMT LRCK DIN BCK SCK FLT MODE2 MODE1 GPO AGNS PCM5141,PCM5142 SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 www.ti.com

APPLICATION INFORMATION

TypicalApplicationCircuits The PCM514x devicescan be operatedina varietyof configurationsto supporta wide range of applications. Figure12 throughFigure21 show differentcombinationsofpower supplies,controlmethods,and VCOM/VREF usage. Figure12.Hardwired ControlMode, DVDD=3.3V Figure13.Hardwired ControlMode, DVDD=1.8V Figure14.SPI Control,VREF Mode, DVDD=3.3V Figure15.SPI Control,VCOM Mode, DVDD=3.3V

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3.3V GPIO Soft mute 3.3V 3.3V I2C GPIO I2C Address 2 Pull down to GND Pull up to 3.3V C1 , C 2 = 2.2nF CPVDD CAPP CPGND CAPM VNEG OUTL OUTR AVDD AGND VCOM SDA SCL GPIO5 GPIO4 DVDD DGND LDOO XSMT ADR1 LRCK DIN BCK SCK GPIO6 MODE2 MODE1 ADR2 GPIO3 I 2C Address 1 0.1 F 0.1 F R1, R2, = 470 GPIO GPIO 0.1 F 2.2 F 2.2 F 3.3V 3.3V C1 , C 2 = 2.2nF PCM Audio Source 3.3V GPIO Soft mute GPIO I2C Address 2 Pull down to GND Pull up to 3.3V I2C Address 1 0.1 F 0.1 F I2C CPVDD CAPP CPGND CAPM VNEG OUTL OUTR AVDD AGND VCOM SDA SCL GPIO5 GPIO4 DVDD DGND LDOO XSMT ADR1 LRCK DIN BCK SCK GPIO6 MODE2 MODE1 ADR2 GPIO3 R1, R2, = 470 GPIO GPIO 0.1 F 2.2 F 2.2 F 3.3V 3.3V SPI C1 , C 2 = 2.2nF GPIO GPIO 0.1 F 2.2 F 2.2 F R1, R2, = 470 10 F PCM Audio Source 1.8V 0.1 F Soft mute SPI DOUT GPIO GPIO GPIO Pull up to 1.8V Chip select for SPI DVDD DGND LDOO XSMT MISO LRCK DIN BCK SCK GPIO6 MS MODE1 GPIO2 GPIO3 CPVDD CAPP CPGND CAPM VNEG OUTL OUTR AVDD AGND VCOM MOSI MC GPIO5 GPIO4 PCM Audio Source 1.8V 3.3V 3.3V SPI GPIO GPIO C1 , C 2 = 2.2nF DVDD DGND LDOO XSMT MISO LRCK DIN BCK SCK GPIO6 MS MODE1 GPIO2 GPIO3 CPVDD CAPP CPGND CAPM VNEG OUTL OUTR AVDD AGND VCOM MOSI MC GPIO5 GPIO4 R1, R2, = 470 0.1 F Soft mute SPI DOUT GPIO GPIO GPIO Pull up to 1.8V Chip select for SPI 0.1 F 2.2 F 2.2 F PCM5141,PCM5142 www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 Figure16.SPI Control,VREF Mode, DVDD=1.8V Figure17.SPI Control,VCOM Mode, DVDD=1.8V Figure18.I2C Control,VREF Mode, DVDD=3.3V Figure19.I2C Control,VCOM Mode, DVDD=3.3V Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:PCM5141 PCM5142

3.3V 3.3V I2C GPIO I2C Address 2 Pull down to GND Pull up to 1.8V C1 , C 2 = 2.2nF CPVDD CAPP CPGND CAPM VNEG OUTL OUTR AVDD AGND VCOM SDA SCL GPIO5 GPIO4 DVDD DGND LDOO XSMT ADR1 LRCK DIN BCK SCK GPIO6 MODE2 MODE1 ADR2 GPIO3 I 2C Address 1 0.1 F R1, R2, = 470 GPIO GPIO 0.1 F 2.2 F 2.2 F 1.8V PCM Audio Source GPIO Soft mute 3.3V 3.3V I2C GPIO I2C Address 2 Pull down to GND Pull up to 1.8V C1 , C 2 = 2.2nF CPVDD CAPP CPGND CAPM VNEG OUTL OUTR AVDD AGND VCOM SDA SCL GPIO5 GPIO4 DVDD DGND LDOO XSMT ADR1 LRCK DIN BCK SCK GPIO6 MODE2 MODE1 ADR2 GPIO3 I 2C Address 1 0.1 F R1, R2, = 470 GPIO GPIO 0.1 F 2.2 F 2.2 F 1.8V +10 F PCM5141,PCM5142 SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 www.ti.com Figure20.I2C Control,VREF Mode, DVDD=1.8V Figure21.I2C Control,VCOM Mode, DVDD=1.8V

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PCM5141,PCM5142 www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 Analog Outputs The PCM514x devicesincludea two-channelDAC, withsingle-endedoutputs.The full-scaleoutputvoltageis 2.1Vrms withground centeroutput.A dc-coupledloadissupportedinadditiontoan ac-coupledload,iftheload resistanceconformsto the specification.The PCM514x DAC outputson the OUTL and OUTR terminalshave market-leadinglow out-of-bandnoise,which offerup to 20dB lowerout-of-bandnoisecompared withexisting DAC technology. Most applicationsrequirean externallow-passRC filter(470Ω + 2.2nF)toprovidesufficientout-of-bandnoise rejection.This RC filterprovidesthe added advantage of improved protectionagainstESD damage. Further discussionofDAC post-filtercircuitsisprovidedinthePCM514x ApplicationReferenceGuide,SLAU345. VoltageReferenceand Ouptut Levels The PCM514x has an internal,fixedband-gap referencevoltage,withdefaultoperationin VREF mode. No externaldecouplingcapacitorisrequiredforthismode. VREF mode provides2.1Vrms full-scaleoutputat both AVDD levels. The PCM514x can be operatedwitha common-mode voltageoutput(VCOM mode) attheVCOM pinby setting Page 1,Register1,D(0)to1.Inthismode, an externaldecuplingcapacitorisrequired. When usingthisDAC inVREF mode, theoutput-signalvoltageisindependentofthepower-supplyvoltage:The D/A conversiongaininVREF mode yieldsa 2.1Vrms outputvoltagewitha digitalfull-scaleinput.However, in VREF mode, an outputwaveform may clipdue tothelimitationsthatmay be presentintheanalogpower supply voltage.On the otherhand, the full-scaleoutputvoltageinVCOM mode isproportionalto the analogpower supplyAVDD. Example,(2.1× AVDD /3.3)Vrms. Mode SwitchingSequence, From VREF Mode toVCOM Mode Followingregistersettingsequence isrecommended forchangingVREF mode toVCOM mode. 1. Page 0 /Register2 RQST = 1:Standbymode 2. Page 1 /Register8 RCMF = 1:Fastramp up → on 3. Page 1 /Register9 VCPD = 0:VCOM ispower on 4. Wait3ms withexternalcapacitor= 1µF 5. Page 1 /Register8 RCMF = 0:Fastramp up → off 6. Page 1 /Register1 OSEL = 1:VCOM mode 7. Page 0 /Register2 RQST = 0:Normal mode Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:PCM5141 PCM5142

SCK, BCK, LRCK Internal Reset 4 ms Reset Removal 2.8V 3.3V AVDD, DVDD, CPVDD PCM510x OUTL OUTR 470Ω 2.2nF LINE OUT 470Ω 2.2nF Output voltage is 2VRMS With a 10 kΩ Load PCM5141,PCM5142 SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 www.ti.com Recommended Output FilterforthePCM514x The diagram inFigure22 shows the recommended outputfilterforthe PCM514x. The new PCM514x next- generationcurrentsegment architectureoffersexcellentout-of-bandnoise,making a traditional20kHz low pass filtera thingofthepast. The RC settingsbelow offera -3dB filterpointat 153kHz (approx),givingthe DAC the abilityto reproduce virtuallyallfrequenciesthroughtoit’s maximum samplingrateof384kHz. Figure22. Recommended Output Lowpass Filterfor10kΩ Operation Reset and System Clock Functions Power-On Reset Function The PCM514x includesa power-on resetfunctionshown inFigure23. With VDD > 2.8V,the power-on reset functionisenabled.Aftertheinitializationperiod,thePCM514x issettoitsdefaultresetstate. Figure23. Power-On Reset Timing,DVDD = 3.3V The PCM514x includesa power-on resetfunctionshown inFigure24 operatingat DVDD=1.8V. With AVDD greaterthan approximately2.8V, and PVDD greaterthan approximately2.8V, and DVDD greaterthan approximately1.5V,thepower-onresetfunctionisenabled.Aftertheinitializationperiod,thePCM514x issetto itsdefaultresetstate.

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SCK, BCK, LRCK Internal Reset 4 ms Reset Removal 1.5V 1.8V DVDD, LDOO 2.8V 3.3V AVDD, CPVDD PCM5141,PCM5142 www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 Figure24. Power-On Reset Timing,DVDD = 1.8V Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:PCM5141 PCM5142

(SCK) tSCKL "L" "H" 0.3*DVDD 0.7*DVDD tSCY PCM5141,PCM5142 SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 www.ti.com System Clock Input The PCM514x requiresa system clockto operatethe digitalinterpolationfiltersand advanced segment DAC modulators.The system clockisappliedattheSCK input(pin20) and supportsup to50MHz. The PCM514x system-clockdetectioncircuitautomaticallysenses the system-clockfrequency.Common audio sampling frequenciesof8kHz, 16kHz, 32kHz - 44.1kHz - 48kHz, 88.2kHz - 96kHz, 176.4kHz -192kHz,and 384kHz with ±4% toleranceare supported.The samplingfrequencydetectorsetstheclockforthedigitalfilter,DeltaSigma Modulator(DSM) and theNegativeCharge Pump (NCP) automatically.Table6 shows examples ofsystem clock frequenciesforcommon audiosamplingrates. SCK ratesthatare not common to standardaudioclocks,between 1MHz and 50MHz, are onlysupportedin softwaremode by configuringvariousPLL and clock-dividerregisters.Thisprogrammabilityallowsthedeviceto become a clockmasterand drivethehostserialportwithLRCK and BCK, from a non-audiorelatedclock(for example,using12MHz togenerate44.1kHz(LRCK) and 2.8224MHz (BCK) ). Figure25 shows thetimingrequirementsforthesystemclockinput.Foroptimalperformance,use a clocksource withlowphase jitterand noise. Table6.System Master Clock InputsforAudio RelatedClocks System Clock Frequency (fSCK )(MHz)Sampling Frequency 64 fS 128 fS 192 fS 256 fS 384 fS 512 fS 768 fS 1024 fS 1152 fS 1536 fS 2048 fS 3072 fS (1) Thissystemclockrateisnotsupportedforthegivensamplingfrequency. (2) Thissystemclockrateissupportedby PLL mode. Figure25. Timing Requirements forSCK Input Table7.Timing Requirements forSCK Input Parameters Min Max Unit tSCY System clockpulsecycletime 20 1000 ns DVDD=1.8V 8 tSCKH System clockpulsewidth,High ns DVDD=3.3V 9 DVDD=1.8V 8 tSCKL System clockpulsewidth,Low ns DVDD=3.3V 9

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PCM5141,PCM5142 www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 System Clock PLL Mode The system clockPLL mode allowsdesignerstouse a simple3-wireI2S audiosourcewhen drivingtheDAC. The 3-wiresourcereducesthe need fora highfrequencySCK, making PCB layouteasier,and reduceshigh frequencyelectromagneticinterference. Inhardwiredmode, thedevicestartsup expectingan externalSCK input,butifBCK and LRCK startcorrectly whileSCK remainsatground levelfor16 successiveLRCK periods,thentheinternalPLL starts,automatically generatingan internalSCK from theBCK reference.The PCM514x disablestheinternalPLL when an external SCK issupplied;specificBCK ratesarerequiredtogeneratean appropriatemasterclock.Table8 describesthe minimum and maximum BCK perLRCK fortheintegratedPLL toautomaticallygeneratean internalSCK. Inhardwiredmode, theinternalPLL isdisabledas soon as an externalSCK issupplied;specificBCK ratesare requiredtogeneratean appropriatemasterclock.Table8 liststheminimum and maximum BCK per LRCK for theIntegratedPLL toautomaticallygeneratean internalSCK. Insoftwaremode, theusermust setallthePLL registersand clockdividerregistersforreferencingBCK. See ClockGenerationand PLL formore information. Table8.BCK Rates (MHz) by LRCK Sample Rate for PCM514x PLL Operation BCK (fS) Sample f(kHz) 32 64 8 - - 16 - 1.024 32 1.024 2.048 44.1 1.4112 2.8224 48 1.536 3.072 96 3.072 6.144 192 6.144 12.288 384 12.288 24.576 Clock Generationand PLL The PCM514x supportsa wide rangeofoptionstogeneratetherequiredclocksfortheDAC sectionas wellas interfaceand othercontrolblocksas shown inFigure26. The clocksforthePLL requirea sourcereferenceclock.Thisclockissourcedas theincomingBCK orSCK. The sourcereferenceclockforthePLL referenceclockisselectedby programmingtheSRCREF valueon Page 0,Register13,D(6:4).The PLL referenceclockcan thenbe routedthroughhighly-flexibleclockdividersshown in Figure26 to generatethe variousclocksrequiredforthe DAC, NegativeCharge Pump (NCP), Internal modulatorand miniDSP sections.The PCM514x providesseveralprogrammable clockdividersto achievea varietyofsamplingratesfortheDAC and clocksfortheNCP, OSR, and theminiDSP.OSRCK forOSR must be setat16fS frequencyby DOSR on Page0,Register30,D(6:0). IfPLL functionalityisn’t required,setthe PLLEN valueon Page 0, Register4, D(0) to 0. In thissituation,an externalSCK isrequired. Table9.PLL ConfigurationRegisters Clock multiplexer Function Bits SRCREF PLL Reference Page 0,Register13,D(6:4) Divider Function Bits DDSP miniDSP clockdivider Page 0,Register27,D(6:0) DDAC DAC clockdivider Page 0,Register28,D(6:0) DNCP NCP clockdivider Page 0,Register29,D(6:0) DOSR OSR clockdivider Page 0,Register30,D(6:0) DBCK ExternalBCK Div Page 0,Register32,D(6:0) Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:PCM5141 PCM5142

K * R / P K = J.D J = 1,2,3, ..,62,63 D= 0000 ,0001 , .,9998 ,9999 R= 1,2,3,4, .,15,16 P = 1,2, .,127,128 PLLCK MCK SCK BCK OSCCK PLLCK SRCDAC Q=1,2,3, ..,127,128 GPIO DIV Q DSPCK Q=1,2,3, ..,127,128 DIV Q SCK PLLEN Q=1,2,3, ..,127,128 DIV Q DACCK CPCK Q=1,2,3, ..,127,128 DIV Q OSRCK DIV Q OFSCCK OSCCK Q=1,2,3, ..,127,128 DIV Q BCKO SCK Q=1,2,3, ..,127,128 DIV Q LRCKO Q=1,2,3, ..,127,128 PLLCKIN PCM5141,PCM5142 SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 www.ti.com Table9.PLL ConfigurationRegisters(continued) DLRK ExternalLRCK Div Page 0,Register33,D(7:0) Figure26. PLL Clock Source and Clock Distribution

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PLLCKIN x R x J.D PLLCK = P PLLCKIN x R x K or PLLCK = P PCM5141,PCM5142 www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 PLL Calculation The PCM514x has an on-chipPLL withfractionalmultiplicationtogeneratetheclockfrequencyneeded by the audioDAC, NegativeCharge Pump, Modulatorand DigitalSignalProcessingblocks.The programmabilityofthe PLL allowsoperationfroma widevarietyofclocksthatmay be availableinthesystem.The PLL input(PLLCKIN) supportsclockfrequenciesfrom 512kHz to 50MHz and is registerprogrammable to enable generationof requiredsamplingrateswithfineprecision. The PLL isenabledby default.The PLL can be turnedon by writingtoPage 0,Register4,D(0).When thePLL isenabled,thePLL outputclockPLLCK isgivenby Equation1: (1) K = [Jvalue].[Dvalue] P = 1,2,3,...15 R, J,D, and P areprogrammable.J istheintegerportionofK (thenumbers totheleftofthedecimalpoint),while D isthefractionalportionofK (thenumbers totherightofthedecimalpoint,assumingfourdigitsofprecision). Examples:

• IfK = 8.5,thenJ = 8,D = 5000
• IfK = 7.12,thenJ = 7,D = 1200
• IfK = 14.03,thenJ = 14,D = 0300
• IfK = 6.0004,thenJ = 6,D = 0004 When thePLL isenabledand D = 0000,thefollowingconditionsmust be satisfied:
• 1MHz ≤ (PLLCKIN /P )≤20MHz
• 64MHz ≤ (PLLCKIN x K x R /P )≤ 100MHz (inVREF mode)
• 72MHz ≤ (PLLCKIN x K x R /P )≤ 86MHz (inVCOM mode)
• 1 ≤ J ≤ 63 When thePLL isenabledand D ≠ 0000,thefollowingconditionsmust be satisfied:
• 6.667MHz ≤ PLLCLKIN /P ≤ 20MHz
• 64MHz ≤ (PLLCKIN x K x R /P )≤ 100MHz (inVREF mode)
• 72MHz ≤ (PLLCK IN x K x R /P )≤ 86MHz (inVCOM mode)
• 4 ≤ J ≤ 11
• R = 1 When thePLL isenabled,
• fS = (PLLCLKIN × K × R) /(2048× P)
• The valueofN isselectedso thatfS × N = PLLCLKIN x K x R /P isintheallowablerange. Example: MCLK = 12MHz and fS = 44.1kHz,(N=2048) SelectP = 1,R = 1,K = 7.5264,whichresultsinJ = 7,D = 5264 Example: MCLK = 12MHz and fS = 48.0kHz,(N=2048) SelectP = 1,R = 1,K = 8.192,whichresultsinJ = 8,D = 1920 ValuesarewrittentotheregistersinTable10. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:PCM5141 PCM5142

PCM5141,PCM5142 SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 www.ti.com Table10.PLL Registers Divider Function Bits PLLE PLL enable Page 0,Register4,D(0) PPDV PLL P Page 0,Register20,D(3:0) PJDV PLL J Page 0,Register21,D(5:0) Page 0,Register22,D(5:0) PDDV PLL D Page 0,Register23,D(7:0) PRDV PLL R Page 0,Register24,D(3:0) Table11.PLL ConfigurationRecommendations Column Description fS (kHz) Samplingfrequency RSCK Ratiobetween samplingfrequencyand SCK frequency(SCK frequency= RSCK x samplingfrequency) SCK (MHz) System masterclockfrequencyatSCK input(pin20) PLL VCO (MHz) PLL VCO frequencyas PLLCK inFigure26 P One ofthePLL coefficientsinEquation1 PLL REF (MHz) Internalreferenceclockfrequencywhichisproducedby SCK /P M = K *R The finalPLL multiplicationfactorcomputed fromK and R as describedinEquation1 K = J.D One ofthePLL coefficientsinEquation1 R One ofthePLL coefficientsinEquation1 PLL fS Ratiobetween fS and PLL VCO frequency(PLL VCO /fS) DSP fS Ratiobetween miniDSP operatingclockrateand fS (PLL fS /NMAC) NMAC The miniDSP clockdividervalueinTable9 DSP CLK (MHz) The miniDSP operatingfrequencyas DSPCK inFigure26 MOD fS Ratiobetween DAC operatingclockfrequencyand fS (PLL fS /NDAC) MOD f(kHz) DAC operatingfrequencyas DACCK inFigure26 NDAC DAC clockdividervalueinTable9 OSR clockdividervalueinTable9 forgeneratingOSRCK inFigure26.DOSR must be chosen so thatMOD fS /DOSR =DOSR 16 forcorrectoperation. NCP NCP (negativechargepump) clockdividervalueinTable9 CP f Negativechargepump clockfrequency(fS *MOD fS /NCP) Percentageoferrorbetween PLL VCO /PLL fS and fS (mismatcherror).

• Thisnumber istypicallyzerobutcan be non-zeroespeciallywhen K isnotan integer(D is% Error notzero).
• Thisnumber may be non-zeroonlywhen thePCM514xacts as a master.

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PCM5141,PCM5142 www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 Table12.Recommended Clock DividerSettingsforPLL as Master Clock (VREF Mode) PLL VCO DSP CLKfS (kHz) RSCK SCK (MHz) P PLL REF (MHz) M = K*R K = J.D R PLL fS DSP fS NMAC MOD fS MOD f(kHz) NDAC DOSR % Error NCP CP f(kHz)(MHz) (MHz) 8 128 1.024 98.304 1 1.024 96 48 2 12288 1024 12 8.192 768 6144 16 48 0 4 1536 8 192 1.536 98.304 1 1.536 64 32 2 12288 1024 12 8.192 768 6144 16 48 0 4 1536 8 256 2.048 98.304 1 2.048 48 48 1 12288 1024 12 8.192 768 6144 16 48 0 4 1536 8 384 3.072 98.304 3 1.024 96 48 2 12288 1024 12 8.192 768 6144 16 48 0 4 1536 8 512 4.096 98.304 3 1.365 72 36 2 12288 1024 12 8.192 768 6144 16 48 0 4 1536 8 768 6.144 98.304 3 2.048 48 48 1 12288 1024 12 8.192 768 6144 16 48 0 4 1536 8 1024 8.192 98.304 3 2.731 36 36 1 12288 1024 12 8.192 768 6144 16 48 0 4 1536 8 1152 9.216 98.304 9 1.024 96 48 2 12288 1024 12 8.192 768 6144 16 48 0 4 1536 8 1536 12.288 98.304 9 1.365 72 36 2 12288 1024 12 8.192 768 6144 16 48 0 4 1536 8 2048 16.384 98.304 9 1.82 54 54 1 12288 1024 12 8.192 768 6144 16 48 0 4 1536 8 3072 24.576 98.304 9 2.731 36 36 1 12288 1024 12 8.192 768 6144 16 48 0 4 1536 16 64 1.024 98.304 1 1.024 96 48 2 6144 1024 6 16.384 384 6144 16 24 0 4 1536 16 128 2.048 98.304 1 2.048 48 48 1 6144 1024 6 16.384 384 6144 16 24 0 4 1536 16 192 3.072 98.304 1 3.072 32 32 1 6144 1024 6 16.384 384 6144 16 24 0 4 1536 16 256 4.096 98.304 1 4.096 24 24 1 6144 1024 6 16.384 384 6144 16 24 0 4 1536 16 384 6.144 98.304 3 2.048 48 48 1 6144 1024 6 16.384 384 6144 16 24 0 4 1536 16 512 8.192 98.304 3 2.731 36 36 1 6144 1024 6 16.384 384 6144 16 24 0 4 1536 16 768 12.288 98.304 3 4.096 24 24 1 6144 1024 6 16.384 384 6144 16 24 0 4 1536 16 1024 16.384 98.304 3 5.461 18 18 1 6144 1024 6 16.384 384 6144 16 24 0 4 1536 16 1152 18.432 98.304 3 6.144 16 16 1 6144 1024 6 16.384 384 6144 16 24 0 4 1536 16 1536 24.576 98.304 9 2.731 36 36 1 6144 1024 6 16.384 384 6144 16 24 0 4 1536 16 2048 32.768 98.304 9 3.641 27 27 1 6144 1024 6 16.384 384 6144 16 24 0 4 1536 16 3072 49.152 98.304 9 5.461 18 18 1 6144 1024 6 16.384 384 6144 16 24 0 4 1536 Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:PCM5141 PCM5142

PCM5141,PCM5142 SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 www.ti.com Table12.Recommended Clock DividerSettingsforPLL as Master Clock (VREF Mode) (continued) PLL VCO DSP CLKfS (kHz) RSCK SCK (MHz) P PLL REF (MHz) M = K*R K = J.D R PLL fS DSP fS NMAC MOD fS MOD f(kHz) NDAC DOSR % Error NCP CP f(kHz)(MHz) (MHz) 32 32 1.024 98.304 1 1.024 96 48 2 3072 1024 3 32.768 192 6144 16 12 0 4 1536 32 48 1.536 98.304 1 1.536 64 16 4 3072 1024 3 32.768 192 6144 16 12 0 4 1536 32 64 2.048 98.304 1 2.048 48 24 2 3072 1024 3 32.768 192 6144 16 12 0 4 1536 32 128 4.096 98.304 1 4.096 24 24 1 3072 1024 3 32.768 192 6144 16 12 0 4 1536 32 192 6.144 98.304 3 2.048 48 48 1 3072 1024 3 32.768 192 6144 16 12 0 4 1536 32 256 8.192 98.304 2 4.096 24 24 1 3072 1024 3 32.768 192 6144 16 12 0 4 1536 32 384 12.288 98.304 3 4.096 24 24 1 3072 1024 3 32.768 192 6144 16 12 0 4 1536 32 512 16.384 98.304 3 5.461 18 18 1 3072 1024 3 32.768 192 6144 16 12 0 4 1536 32 768 24.576 98.304 3 8.192 12 12 1 3072 1024 3 32.768 192 6144 16 12 0 4 1536 32 1024 32.768 98.304 3 10.923 9 9 1 3072 1024 3 32.768 192 6144 16 12 0 4 1536 32 1152 36.864 98.304 9 4.096 24 24 1 3072 1024 3 32.768 192 6144 16 12 0 4 1536 32 1536 49.152 98.304 6 8.192 12 12 1 3072 1024 3 32.768 192 6144 16 12 0 4 1536 48 32 1.536 98.304 1 1.536 64 32 2 2048 1024 2 49.152 128 6144 16 8 0 4 1536 48 64 3.072 98.304 1 3.072 32 16 2 2048 1024 2 49.152 128 6144 16 8 0 4 1536 48 128 6.144 98.304 1 6.144 16 16 1 2048 1024 2 49.152 128 6144 16 8 0 4 1536 48 192 9.216 98.304 3 3.072 32 32 1 2048 1024 2 49.152 128 6144 16 8 0 4 1536 48 256 12.288 98.304 2 6.144 16 16 1 2048 1024 2 49.152 128 6144 16 8 0 4 1536 48 384 18.432 98.304 3 6.144 16 16 1 2048 1024 2 49.152 128 6144 16 8 0 4 1536 48 512 24.576 98.304 3 8.192 12 12 1 2048 1024 2 49.152 128 6144 16 8 0 4 1536 48 768 36.864 98.304 3 12.288 8 8 1 2048 1024 2 49.152 128 6144 16 8 0 4 1536 48 1024 49.152 98.304 3 16.384 6 6 1 2048 1024 2 49.152 128 6144 16 8 0 4 1536 96 32 3.072 98.304 1 3.072 32 16 2 1024 512 2 49.152 64 6144 16 4 0 4 1536

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PCM5141,PCM5142 www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 Table12.Recommended Clock DividerSettingsforPLL as Master Clock (VREF Mode) (continued) PLL VCO DSP CLKfS (kHz) RSCK SCK (MHz) P PLL REF (MHz) M = K*R K = J.D R PLL fS DSP fS NMAC MOD fS MOD f(kHz) NDAC DOSR % Error NCP CP f(kHz)(MHz) (MHz) 96 48 4.608 98.304 3 1.536 64 32 2 1024 512 2 49.152 64 6144 16 4 0 4 1536 96 64 6.144 98.304 1 6.144 16 8 2 1024 512 2 49.152 64 6144 16 4 0 4 1536 96 128 12.288 98.304 2 6.144 16 16 1 1024 512 2 49.152 64 6144 16 4 0 4 1536 96 192 18.432 98.304 3 6.144 16 16 1 1024 512 2 49.152 64 6144 16 4 0 4 1536 96 256 24.576 98.304 4 6.144 16 16 1 1024 512 2 49.152 64 6144 16 4 0 4 1536 96 384 36.864 98.304 6 6.144 16 16 1 1024 512 2 49.152 64 6144 16 4 0 4 1536 96 512 49.152 98.304 8 6.144 16 16 1 1024 512 2 49.152 64 6144 16 4 0 4 1536 192 32 6.144 98.304 1 6.144 16 8 2 512 256 2 49.152 32 6144 16 2 0 4 1536 192 48 9.216 98.304 3 3.072 32 16 2 512 256 2 49.152 32 6144 16 2 0 4 1536 192 64 12.288 98.304 1 12.288 8 4 2 512 256 2 49.152 32 6144 16 2 0 4 1536 192 128 24.576 98.304 2 12.288 8 8 1 512 256 2 49.152 32 6144 16 2 0 4 1536 192 192 36.864 98.304 3 12.288 8 8 1 512 256 2 49.152 32 6144 16 2 0 4 1536 192 256 49.152 98.304 4 12.288 8 8 1 512 256 2 49.152 32 6144 16 2 0 4 1536 384 32 12.288 98.304 2 6.144 16 8 2 256 128 2 49.152 16 6144 16 1 0 4 1536 384 48 18.432 98.304 3 6.144 16 8 2 256 128 2 49.152 16 6144 16 1 0 4 1536 384 64 24.576 98.304 2 12.288 8 4 2 256 128 2 49.152 16 6144 16 1 0 4 1536 384 128 49.152 98.304 4 12.288 8 8 1 256 128 2 49.152 16 6144 16 1 0 4 1536 Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:PCM5141 PCM5142

PCM5141,PCM5142 SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 www.ti.com Table13.Recommended Clock DividerSettingsforPLL as Master Clock (VCOM Mode) SCK PLL VCO PLL REF DSP CLK MOD ffS (kHz) RSCK P M = K*R K = J.D R PLL FS DSP FS NMAC MOD fS NDAC DOSR % Error NCP CP f(kHz)(MHz) (MHz) (MHz) (MHz) (kHz) 8 128 1.024 73.728 1 1.024 72 36 2 9216 768 12 6.144 768 6144 12 48 0 4 1536 8 192 1.536 73.728 1 1.536 48 24 2 9216 768 12 6.144 768 6144 12 48 0 4 1536 8 256 2.048 73.728 1 2.048 36 36 1 9216 768 12 6.144 768 6144 12 48 0 4 1536 8 384 3.072 73.728 1 3.072 24 12 2 9216 768 12 6.144 768 6144 12 48 0 4 1536 8 512 4.096 73.728 2 2.048 36 36 1 9216 768 12 6.144 768 6144 12 48 0 4 1536 8 768 6.144 73.728 3 2.048 36 36 1 9216 768 12 6.144 768 6144 12 48 0 4 1536 8 1024 8.192 73.728 4 2.048 36 36 1 9216 768 12 6.144 768 6144 12 48 0 4 1536 8 1152 9.216 73.728 6 1.536 48 48 1 9216 768 12 6.144 768 6144 12 48 0 4 1536 8 1536 12.288 73.728 6 2.048 36 36 1 9216 768 12 6.144 768 6144 12 48 0 4 1536 8 2048 16.384 73.728 8 2.048 36 36 1 9216 768 12 6.144 768 6144 12 48 0 4 1536 8 3072 24.576 73.728 12 2.048 36 36 1 9216 768 12 6.144 768 6144 12 48 0 4 1536 16 64 1.024 73.728 1 1.024 72 36 2 4608 768 6 12.288 384 6144 12 24 0 4 1536 16 128 2.048 73.728 1 2.048 36 36 1 4608 768 6 12.288 384 6144 12 24 0 4 1536 16 192 3.072 73.728 1 3.072 24 24 1 4608 768 6 12.288 384 6144 12 24 0 4 1536 16 256 4.096 73.728 2 2.048 36 36 1 4608 768 6 12.288 384 6144 12 24 0 4 1536 16 384 6.144 73.728 3 2.048 36 36 1 4608 768 6 12.288 384 6144 12 24 0 4 1536 16 512 8.192 73.728 4 2.048 36 36 1 4608 768 6 12.288 384 6144 12 24 0 4 1536 16 768 12.288 73.728 6 2.048 36 36 1 4608 768 6 12.288 384 6144 12 24 0 4 1536 16 1024 16.384 73.728 8 2.048 36 36 1 4608 768 6 12.288 384 6144 12 24 0 4 1536 16 1152 18.432 73.728 9 2.048 36 36 1 4608 768 6 12.288 384 6144 12 24 0 4 1536 16 1536 24.576 73.728 8 3.072 24 24 1 4608 768 6 12.288 384 6144 12 24 0 4 1536 16 2048 32.768 73.728 8 4.096 18 18 1 4608 768 6 12.288 384 6144 12 24 0 4 1536 16 3072 49.152 73.728 8 6.144 12 12 1 4608 768 6 12.288 384 6144 12 24 0 4 1536

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PCM5141,PCM5142 www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 Table13.Recommended Clock DividerSettingsforPLL as Master Clock (VCOM Mode) (continued) SCK PLL VCO PLL REF DSP CLK MOD ffS (kHz) RSCK P M = K*R K = J.D R PLL FS DSP FS NMAC MOD fS NDAC DOSR % Error NCP CP f(kHz)(MHz) (MHz) (MHz) (MHz) (kHz) 32 32 1.024 73.728 1 1.024 72 36 2 2304 768 3 24.576 192 6144 12 12 0 4 1536 32 48 1.536 73.728 1 1.536 48 12 4 2304 768 3 24.576 192 6144 12 12 0 4 1536 32 64 2.048 73.728 1 2.048 36 18 2 2304 768 3 24.576 192 6144 12 12 0 4 1536 32 128 4.096 73.728 2 2.048 36 36 1 2304 768 3 24.576 192 6144 12 12 0 4 1536 32 192 6.144 73.728 3 2.048 36 36 1 2304 768 3 24.576 192 6144 12 12 0 4 1536 32 256 8.192 73.728 4 2.048 36 36 1 2304 768 3 24.576 192 6144 12 12 0 4 1536 32 384 12.288 73.728 6 2.048 36 36 1 2304 768 3 24.576 192 6144 12 12 0 4 1536 32 512 16.384 73.728 8 2.048 36 36 1 2304 768 3 24.576 192 6144 12 12 0 4 1536 32 768 24.576 73.728 6 4.096 18 18 1 2304 768 3 24.576 192 6144 12 12 0 4 1536 32 1024 32.768 73.728 8 4.096 18 18 1 2304 768 3 24.576 192 6144 12 12 0 4 1536 32 1152 36.864 73.728 9 4.096 18 18 1 2304 768 3 24.576 192 6144 12 12 0 4 1536 32 1536 49.152 73.728 12 4.096 18 18 1 2304 768 3 24.576 192 6144 12 12 0 4 1536 48 32 1.536 73.728 1 1.536 48 24 2 1536 768 2 36.864 128 6144 12 8 0 4 1536 48 48 2.304 73.728 1 2.304 32 8 4 1536 768 2 36.864 128 6144 12 8 0 4 1536 48 64 3.072 73.728 1 3.072 24 12 2 1536 768 2 36.864 128 6144 12 8 0 4 1536 48 128 6.144 73.728 2 3.072 24 24 1 1536 768 2 36.864 128 6144 12 8 0 4 1536 48 192 9.216 73.728 3 3.072 24 24 1 1536 768 2 36.864 128 6144 12 8 0 4 1536 48 256 12.288 73.728 4 3.072 24 24 1 1536 768 2 36.864 128 6144 12 8 0 4 1536 48 384 18.432 73.728 6 3.072 24 24 1 1536 768 2 36.864 128 6144 12 8 0 4 1536 48 512 24.576 73.728 4 6.144 12 12 1 1536 768 2 36.864 128 6144 12 8 0 4 1536 48 768 36.864 73.728 6 6.144 12 12 1 1536 768 2 36.864 128 6144 12 8 0 4 1536 Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLinks:PCM5141 PCM5142

PCM5141,PCM5142 SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 www.ti.com Table13.Recommended Clock DividerSettingsforPLL as Master Clock (VCOM Mode) (continued) SCK PLL VCO PLL REF DSP CLK MOD ffS (kHz) RSCK P M = K*R K = J.D R PLL FS DSP FS NMAC MOD fS NDAC DOSR % Error NCP CP f(kHz)(MHz) (MHz) (MHz) (MHz) (kHz) 48 1024 49.152 73.728 8 6.144 12 12 1 1536 768 2 36.864 128 6144 12 8 0 4 1536 96 32 3.072 73.728 2 1.536 48 24 2 768 384 2 36.864 64 6144 12 4 0 4 1536 96 48 4.608 73.728 3 1.536 48 24 2 768 384 2 36.864 64 6144 12 4 0 4 1536 96 64 6.144 73.728 2 3.072 24 12 2 768 384 2 36.864 64 6144 12 4 0 4 1536 96 128 12.288 73.728 4 3.072 24 24 1 768 384 2 36.864 64 6144 12 4 0 4 1536 96 192 18.432 73.728 6 3.072 24 24 1 768 384 2 36.864 64 6144 12 4 0 4 1536 96 256 24.576 73.728 8 3.072 24 24 1 768 384 2 36.864 64 6144 12 4 0 4 1536 96 384 36.864 73.728 6 6.144 12 12 1 768 384 2 36.864 64 6144 12 4 0 4 1536 96 512 49.152 73.728 8 6.144 12 12 1 768 384 2 36.864 64 6144 12 4 0 4 1536 192 32 6.144 73.728 2 3.072 24 12 2 384 192 2 36.864 32 6144 12 2 0 4 1536 192 48 9.216 73.728 3 3.072 24 12 2 384 192 2 36.864 32 6144 12 2 0 4 1536 192 64 12.288 73.728 4 3.072 24 12 2 384 192 2 36.864 32 6144 12 2 0 4 1536 192 128 24.576 73.728 8 3.072 24 24 1 384 192 2 36.864 32 6144 12 2 0 4 1536 192 192 36.864 73.728 6 6.144 12 12 1 384 192 2 36.864 32 6144 12 2 0 4 1536 192 256 49.152 73.728 8 6.144 12 12 1 384 192 2 36.864 32 6144 12 2 0 4 1536 384 32 12.288 73.728 2 6.144 12 6 2 192 96 2 36.864 16 6144 12 1 0 4 1536 384 48 18.432 73.728 3 6.144 12 6 2 192 96 2 36.864 16 6144 12 1 0 4 1536 384 64 24.576 73.728 4 6.144 12 6 2 192 96 2 36.864 16 6144 12 1 0 4 1536 384 128 49.152 73.728 8 6.144 12 12 1 192 96 2 36.864 16 6144 12 1 0 4 1536

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PCM5141,PCM5142 www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 Table14.Recommended Clock DividerSettingsforSCK as Master Clock fS (kHz) RSCK SCK (MHz) DSP fS NMAC DSP CLK MOD fS MOD f(kHz) NDAC DOSR NCP CP f(kHz) (MHz) 8 256 2.048 256 1 2.048 256 2048 1 16 2 1024 8 384 3.072 384 1 3.072 384 3072 1 24 2 1536 8 512 4.096 512 1 4.096 512 4096 1 32 2 2048 8 768 6.144 768 1 6.144 768 6144 1 48 4 1536 8 1024 8.192 1024 1 8.192 512 4096 2 32 2 2048 8 1152 9.216 1152 1 9.216 576 4608 2 36 4 1152 8 1536 12.288 1536 1 12.288 768 6144 2 48 4 1536 8 2048 16.384 2048 1 16.384 512 4096 4 32 2 2048 8 3072 24.576 3072 1 24.576 768 6144 4 48 4 1536 16 256 4.096 256 1 4.096 256 4096 1 16 2 2048 16 384 6.144 384 1 6.144 384 6144 1 24 4 1536 16 512 8.192 512 1 8.192 256 4096 2 16 2 2048 16 768 12.288 768 1 12.288 384 6144 2 24 4 1536 16 1152 18.432 1152 1 18.432 288 4608 4 18 4 1152 16 1536 24.576 1536 1 24.576 384 6144 4 24 4 1536 16 2048 32.768 2048 1 32.768 256 4096 8 16 2 2048 16 3072 49.152 3072 1 49.152 384 6144 8 24 4 1536 32 256 8.192 256 1 8.192 128 4096 2 8 2 2048 32 384 12.288 384 1 12.288 128 4096 3 8 2 2048 32 512 16.384 512 1 16.384 128 4096 4 8 2 2048 32 768 24.576 768 1 24.576 128 4096 6 8 2 2048 32 1024 32.768 1024 1 32.768 128 4096 8 8 2 2048 32 1152 36.864 1152 1 36.864 128 4096 9 8 4 1024 32 1536 49.152 1536 1 49.152 128 4096 12 8 4 1024 48 256 12.288 256 1 12.288 128 6144 2 8 4 1536 48 384 18.432 384 1 18.432 128 6144 3 8 4 1536 48 512 24.576 512 1 24.576 128 6144 4 8 4 1536 48 768 36.864 768 1 36.864 128 6144 6 8 4 1536 48 1024 49.152 1024 1 49.152 128 6144 8 8 4 1536 96 192 18.432 192 1 18.432 48 4608 4 3 6 768 96 256 24.576 256 1 24.576 64 6144 4 4 4 1536 96 384 36.864 384 1 36.864 64 6144 6 4 4 1536 96 512 49.152 512 1 49.152 64 6144 8 4 4 1536 Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLinks:PCM5141 PCM5142

PCM5141,PCM5142 SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 www.ti.com Table14.Recommended Clock DividerSettingsforSCK as Master Clock (continued) fS (kHz) RSCK SCK (MHz) DSP fS NMAC DSP CLK MOD fS MOD f(kHz) NDAC DOSR NCP CP f(kHz) (MHz) 192 128 24.576 128 1 24.576 32 6144 4 2 4 1536 192 192 36.864 192 1 36.864 32 6144 6 2 4 1536 192 256 49.152 256 1 49.152 32 6144 8 2 4 1536 384 64 24.576 64 1 24.576 16 6144 4 1 4 1536 384 128 49.152 128 1 49.152 16 6144 8 1 4 1536

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PCM5141,PCM5142 www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 Audio Data Interface Audio SerialInterface The audiointerfaceportisa 3-wireserialportwiththesignalsLRCK (pin15),BCK (pin13),and DIN (pin14). BCK istheserialaudiobitclock,used toclocktheserialdatapresenton DIN intotheserialshiftregisterofthe audiointerface.SerialdataisclockedintothePCM514x on therisingedge ofBCK. LRCK istheserialaudio left/rightword clock. Table15.PCM514x Audio Data Formats,BitDepths and Clock Rates MAX LRCKCONTROL MODE FORMAT DATA BITS SCK RATE [xfS] BCK RATE [xfS]FREQUENCY [fS] Up to192kHz 128 – 3072 64,48,32 I2S/LJ 32,24,20,16 384kHz 64,128 64,48,32 SoftwareControl Up to48kHz 128 – 3072 125,256(SPIorI2S) TDM 32,24,20,16 96kHz 128 – 512 125,256 192kHz 128,192,256 128 Up to192kHz 128 – 3072 64,48,32 Hardware Control I2S/LJ 32,24,20,16 384kHz 64,128 64,48,32 The PCM514x requiresthe synchronizationof LRCK and system clock,but does not need a specificphase relationbetween LRCK and systemclock. Iftherelationshipbetween LRCK and system clockchanges more than±5 SCK, internaloperationisinitialized withinone sample periodand analogoutputsareforcedtothebipolarzeroleveluntilresynchronizationbetween LRCK and systemclockiscompleted. Iftherelationshipbetween LRCK and BCK areinvalidmore than4 LRCK periods,internaloperationisinitialized withinone sample periodand analogoutputsareforcedtothebipolarzeroleveluntilresynchronizationbetween LRCK and BCK iscompleted. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 35 ProductFolderLinks:PCM5141 PCM5142

1. 5 * DVDD 0. 5 * DVDD 0. 5 * DVDD (Input) (Input) (Input) DATA 0. 5 * DVDD (Output ) tDOD PCM5141,PCM5142 SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 www.ti.com PCM Audio Data Formats and Timing The PCM514x supportsindustry-standardaudio data formats,includingstandardI2S and left-justified.Data formatsareselectedusingtheFMT (pin16),Low forI2S,and HighforLeft-justified.Allformatsrequirebinary2s- complement,MSB-firstaudiodata;up to32-bitaudiodataisaccepted. The PCM514x alsosupportsright-justifiedand TDM insoftwarecontrolmode. I2S, LJ,RJ, and TDM areselected usingRegister(Pg0Reg40).Allformatsrequirebinary2s complement,MSB-firstaudiodata.Up to32 bitsare accepted.DefaultsettingisI2S and 24 bitword length.The I2S slavetimingisshown inFigure27. Figure27. PCM514x SerialAudio Timing -Slave Table16.Audio InterfaceSlaveTiming Parameters Min Max Units tBCY BCK PulseCycleTime 40 ns tBCL BCK PulseWidthLOW 16 ns tBCH BCK PulseWidthHIGH 16 ns tBL BCK RisingEdge toLRCK Edge 8 ns tBCK BCK frequencyatDVDD = 3.3V 24.576 MHz tBCK(1.8V) BCK frequencyatDVDD = 1.8V 12.288 MHz tLB LRCK Edge toBCK RisingEdge 8 ns tDS DATA SetUp Time 8 ns tDH DATA HoldTime 8 ns tDOD DATA delaytimefromBCK fallingedge 15 ns Insoftwaremode, thePCM514x can actas an I2S master,generatingBCK and LRCK as outputsfromtheSCK input. Table17.I2S Master Mode Registers Register Function Page0,Register9,D(0),D(4),and D(5) I2S Mastermode select Register32,D(6:0) BCK dividerand LRCK divider Register33,D(7:0)

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1. 5 * DVDD 0. 5 * DVDD 0. 5 * DVDD ( Output ) ( Output ) ( Output ) tDOD DATA 0. 5 * DVDD (Input ) PCM5141,PCM5142 www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 The I2S mastertimingisshown inFigure28 and Table18. Figure28. PCM514x SerialAudio Timing -Master Table18. Audio InterfaceMaster Timing Parameters Min Max Units tBCY BCK PulseCycleTime 40 ns tBCL BCK PulseWidthLOW 16 ns tBCH BCK PulseWidthHIGH 16 ns tBCK BCK frequencyatDVDD = 3.3V 24.576 MHz tBCK(1.8V) BCK frequencyatDVDD = 1.8V 12.288 MHz tLRD LRCKx delaytimefromBCKx fallingedge –10 20 ns tDS DATA SetUp Time 8 ns tDH DATA HoldTime 8 ns DATA delaytimefromBCK fallingedge atDVDDtDOD 15 ns= 3.3V DATA delaytimefromBCK fallingedge atDVDDtDOD(1.8V) 20 ns= 1.8V Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 37 ProductFolderLinks:PCM5141 PCM5142

Audio data word = 16-bit, BCK = 32, 48, 64f S DATA MSB LSB MSB LSB BCK 16 15 21 16 15 21 24 23 2 24 23 21 32 31 21 32 31 21 Audio data word = 24-bit, BCK = 48, 64f S Audio data word = 32-bit, BCK = 64fS LRCK LSB L-channel R-channel BCK DATA MSB LSB MSB LSB 16 15 21 16 15 21 - , DATA MSB LSB MSB 21 24 2 21 24 23 DATA MSB LSB MSB LSB 21 32 31 21 32 31 1tS Audio data word = 16-bit, BCK = 32, 48, 64f S Audio data word = 24-bit, BCK = 48, 64f S Audio data word = 32-bit, BCK = 64fS PCM5141,PCM5142 SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 www.ti.com Figure29. LeftJustifiedAudio Data Format I2S Data Format;L-channel= LOW, R-channel= HIGH Figure30. I2S Audio Data Format

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PCM5141,PCM5142 www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 The followingdataformatsareonlyavailableinsoftwaremode. RightJustifiedData Format;L-channel= HIGH, R-channel= LOW Figure31. RightJustifiedAudio Data Format TDM Data Format;L-channel= FIRST,R-channel= LAST withOFFSET = 0 Figure32. TDM 1 Audio Data Format Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 39 ProductFolderLinks:PCM5141 PCM5142

PCM5141,PCM5142 SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 www.ti.com TDM Data Format;L-channel= FIRST,R-channel= LAST withOFFSET = 1 Figure33. TDM 2 Audio Data Format TDM Data Format;L-channel= FIRST,R-channel= LAST withOFFSET = N Figure34. TDM 3 Audio Data Format

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PCM5141,PCM5142 www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 FunctionDescriptions PCM514x Audio ProcessingOptions Overview The PCM514x featuresa fully-programmableminiDSP core.The algorithmsfortheminiDSP must be loadedinto the deviceafterpower up. The miniDSP has directaccess to the digitalstereoaudio stream,offeringthe possibilityforadvanced DSP algorithmswithverylow groupdelay.The miniDSP can runup to1024 instructions on everyaudiosample ata 48kHz sample rate. The PCM514x familysupportstwo differentcode sources.ROM based processflow(Program5 - FixedAudio ProcessingFlow (Program5)ofthisdatasheet)and RAM based processflow(Program31).Inprogram31 (RAM based),differentalgorithmscan be calledfrom ROM - such as EQ, DRC, Zero Crossingvolume controletc. Pleasesee thePurePathStudioDevelopmentEnvironmentformore details. miniDSP InstructionRegister miniDSP instructionregistersare only availablein PCM514x devices.Page 152-169 registersare 25-bit instructionsforthe miniDSP engine.For detailssee Table 58. 7 bitsof Instr(32:25)in Base register+0 are reservedbits.1 bitof Instr(24)- (LSB) inBase register+0 isMSB bitof 25 bitinstruction.These instructions controlminiDSP operation.When the fullyprogrammable miniDSP mode is enabled and DAC channel is powered up,thereadand writeaccesstotheseregistersisdisabled. Software SoftwaredevelopmentforthePCM514x issupportedthroughTI'scomprehensivePurePathStudioDevelopment Environment; a powerful,easy-to-usetooldesigned specificallyto simplifysoftwaredevelopment on the PCM514x miniDSP audioplatform.The GraphicalDevelopment Environmentconsistsof a libraryof common audiofunctionsthatcan be dragged-and-droppedintoan audiosignalflowand graphicallyconnectedtogether. The DSP code can thenbe assembledfromthegraphicalsignalflowwiththeclickofa mouse. Please visitthe PCM514x productfolderon www.ti.comto learnmore about PurePath Studioand the latest statuson available,ready-to-useDSP algorithms. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 41 ProductFolderLinks:PCM5141 PCM5142

PCM5141,PCM5142 SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 www.ti.com InterpolationFilter The PCM514x provides4 typesofinterpolationfilters,selectableby writingtoPage 0,Register43,D(4:0). Table19.ROM PresetPrograms Program number D(4:0) Description Minimum Cycles 0 0 0000 Reserved 1 0 0001 Normal x8/x4/x2/x1InterpolationFilter(1) 256 2 0 0010 Low Latencyx8/x4/x2/x1InterpolationFilter(1) 256 3 0 0011 HighAttenuationx8/x4/x2InterpolationFilter(1) 512 4 0 0100 Reserved 5 0 0101 PresetProcessFlow n/a 6 0 0110 Reserved 7 0 0111 AsymmetricFIR InterpolationFilter(1) 512 : : Reserved 31 1 1111 RAM program (1) fS 44.1kHzDe-emphasisfilterissupported. The PCM514xsupports foursamplingmodes (singlerate,dualrate,quad rate,and octalrate)which produce differentoversamplingrates(OSR) intheinterpolationdigitalfilteroperation.These areshown inTable20. Table20.Sampling Modes and Oversampling Rates Sampling Mode Sampling Frequency (fS)kHz Oversampling Rate (OSR) SingleRate 32 8 or16 44.1 88.2 DualRate 4 176.4 Quad Rate 2 192 OctalRate 384 1 (Bypass)

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−0.05 −0.04 −0.03 −0.02 −0.01 0.00 0.01 0.02 0.03 0.04 0.05 Frequency (x fS) Amplitude (dB) G034 −120 −100 −80 −60 −40 −20 0 1 2 3 4 Frequency (x fS) Amplitude (dB) G012 −0.4 −0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 50 100 150 200 250 300 350 400 Samples Amplitude (FFS) G023 PCM5141,PCM5142 www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 Table21.Normal x8 InterpolationFilter,SingleRate Parameter Condition Value (Typical) Value (Max) Units FilterGain Pass Band 0 … … .0.45fS ±0.01 dB FilterGain StopBand 0.55fS … ..7.455fS –60 dB FilterGroup Delay 20tS S Figure35.Normal x8 InterpolationFilterFrequency Figure36.Normal x8 InterpolationFilterImpulse Response Response Figure37.Normal x8 InterpolationFilterPassband Ripple Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 43 ProductFolderLinks:PCM5141 PCM5142

−0.05 −0.04 −0.03 −0.02 −0.01 0.00 0.01 0.02 0.03 0.04 0.05 0.0 0.5 1.0 Frequency (x fS) Amplitude (dB) G031 −120 −100 −80 −60 −40 −20 0 1 2 3 4 Frequency (x fS) Amplitude (dB) G009 −0.4 −0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 20 40 60 80 100 120 140 160 Samples Amplitude (FFS) G020 PCM5141,PCM5142 SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 www.ti.com Table22.Normal x4 InterpolationFilter,Dual Rate Parameter Condition Value (Typical) Value (Max) Units FilterGain Pass Band 0 … … .0.45fS ±0.01 dB FilterGain StopBand 0.55fS … ..3.455fS –60 dB FilterGroup Delay 20tS S Figure38.Normal x4 InterpolationFilterFrequency Figure39.Normal x4 InterpolationFilterImpulse Response Response Figure40.Normal x4 InterpolationFilterPassband Ripple

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−0.05 −0.04 −0.03 −0.02 −0.01 0.00 0.01 0.02 0.03 0.04 0.05 Frequency (x fS) Amplitude (dB) G028 −120 −100 −80 −60 −40 −20 0 1 2 3 4 Frequency (x fS) Amplitude (dB) G006 −0.4 −0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 10 20 30 40 50 60 70 80 90 100 Samples Amplitude (FFS) G017 PCM5141,PCM5142 www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 Table23.Normal x2 InterpolationFilter,Quad Rate Parameter Condition Value (Typical) Value (Max) Units FilterGain Pass Band 0 … … .0.45fS ±0.01 dB FilterGain StopBand 0.55fS … ..1.455fS –60 dB FilterGroup Delay 20tS S Figure41.Normal x2 InterpolationFilterFrequency Figure42.Normal x2 InterpolationFilterImpulse Response Response Figure43.Normal x2 InterpolationFilterPassband Ripple Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 45 ProductFolderLinks:PCM5141 PCM5142

−0.00010 −0.00008 −0.00006 −0.00004 −0.00002 0.00000 0.00002 0.00004 0.00006 0.00008 0.00010 Frequency (x fS) Amplitude (dB) G033 −120 −100 −80 −60 −40 −20 0 1 2 3 4 Frequency (x fS) Amplitude (dB) G011 −0.6 −0.4 −0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 50 100 150 200 250 300 350 400 Samples Amplitude (FFS) G022 PCM5141,PCM5142 SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 www.ti.com Table24.Low latencyx8 InterpolationFilter,SingleRate Parameter Condition Value (Typical) Value (Max) Units FilterGain Pass Band 0 … … .0.45fS ±0.001 dB FilterGain StopBand 0.55fS … ..7.455fS –52 dB FilterGroup Delay 3.5tS S Figure44.Low latencyx8 InterpolationFilter Figure45.Low latencyx8 InterpolationFilter Frequency Response Impulse Response Figure46.Low latencyx8 InterpolationFilterPassband Ripple

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−0.0001 −0.00008 −0.00006 −0.00004 −0.00002 0.00002 0.00004 0.00006 0.00008 0.0001 0.0 0.5 1.0 Frequency (x fS) Amplitude (dB) G030 −120 −100 −80 −60 −40 −20 0 1 2 3 4 Frequency (x fS) Amplitude (dB) G008 −0.6 −0.4 −0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 20 40 60 80 100 120 140 160 180 Samples Amplitude (FFS) G019 PCM5141,PCM5142 www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 Table25.Low latencyx4 InterpolationFilter,Dual Rate Parameter Condition Value (Typical) Value (Max) Units FilterGain Pass Band 0 … … .0.45fS ±0.001 dB FilterGain StopBand 0.55fS … ..3.455fS –52 dB FilterGroup Delay 3.5tS S Figure47.Low latencyx4 InterpolationFilter Figure48.Low latencyx4 InterpolationFilter Frequency Response Impulse Response Figure49.Low latencyx4 InterpolationFilterPassband Ripple Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 47 ProductFolderLinks:PCM5141 PCM5142

−0.0001 −0.00008 −0.00006 −0.00004 −0.00002 0.00002 0.00004 0.00006 0.00008 0.0001 0.0 0.5 1.0 Frequency (x fS) Amplitude (dB) G030 −120 −100 −80 −60 −40 −20 0 1 2 3 4 Frequency (x fS) Amplitude (dB) G005 −0.4 −0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 10 20 30 40 50 60 70 80 90 100 Samples Amplitude (FFS) G016 PCM5141,PCM5142 SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 www.ti.com Table26.Low latency×2 InterpolationFilter,Quad Rate Parameter Condition Value (Typical) Value (Max) Units FilterGain Pass Band 0 … … .0.45fS ±0.001 dB FilterGain StopBand 0.55fS … ..1.455fS –52 dB FilterGroup Delay 3.5tS S Figure50.Low latencyx2 InterpolationFilter Figure51.Low latencyx2 InterpolationFilter Frequency Response Impulse Response Figure52.Low latencyx2 InterpolationFilterPassband Ripple

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−0.2 −0.15 −0.1 −0.05 0.05 0.1 0.15 0.2 Frequency (× fS) Amplitude (dB) G009 −120 −100 −80 −60 −40 −20 0 1 2 3 4 Frequency (× fS) Amplitude (dB) G003 −0.4 −0.2 0.2 0.4 0.6 0.8 0 10 20 30 40 50 60 70 80 Samples Amplitude (FFS) G006 PCM5141,PCM5142 www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 Table27.Asymmetric FIR x8 InterpolationFilter,SingleRate Parameter Condition Value (Typical) Value (Max) Units FilterGain Pass Band 0 … … .0.40fS ±0.05 dB FilterGain StopBand 0.72fS … ..7.28fS –50 dB FilterGroup Delay 1.2tS S Figure53.Asymmetric FIR x8 InterpolationFilter Figure54.Asymmetric FIR x8 InterpolationFilter Frequency Response, SingleRate Impulse Response, SingleRate Figure55.Asymmetric FIR x8 InterpolationFilterPassband Ripple,SingleRate Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 49 ProductFolderLinks:PCM5141 PCM5142

−0.2 −0.15 −0.1 −0.05 0.05 0.1 0.15 0.2 0 0.5 1 Frequency (× fS) Amplitude (dB) G008 −120 −100 −80 −60 −40 −20 0 1 2 3 4 Frequency (× fS) Amplitude (dB) G002 −0.4 −0.2 0.2 0.4 0.6 0.8 0 10 20 30 40 50 60 Samples Amplitude (FFS) G005 PCM5141,PCM5142 SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 www.ti.com Table28.Asymmetric FIR x4 InterpolationFilter,Dual Rate Parameter Condition Value (Typical) Value (Max) Units FilterGain Pass Band 0 … … .0.40fS ±0.05 dB FilterGain StopBand 0.72fS … ..3.28fS –50 dB FilterGroup Delay 1.2tS S Figure56.Asymmetric FIR x4 InterpolationFilter Figure57.Asymmetric FIR x4 InterpolationFilter Frequency Response, Dual Rate Impulse Response, Dual Rate Figure58.Asymmetric x4 InterpolationFilterPassband Ripple,Dual Rate

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−0.2 −0.15 −0.1 −0.05 0.05 0.1 0.15 0.2 0 0.5 1 1.5 2 Frequency (× fS) Amplitude (dB) G007 −120 −100 −80 −60 −40 −20 0 1 2 3 4 Frequency (× fS) Amplitude (dB) G001 −0.4 −0.2 0.2 0.4 0.6 0.8 0 10 20 30 40 50 Samples Amplitude (FFS) G004 PCM5141,PCM5142 www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 Table29.Asymmetric FIR x2 InterpolationFilter,Quad Rate Parameter Condition Value (Typical) Value (Max) Units FilterGain Pass Band 0 … … .0.40fS ±0.05 dB FilterGain StopBand 0.72fS … ..1.28fS –50 dB FilterGroup Delay 1.2tS S Figure59.Asymmetric FIR x2 InterpolationFilter Figure60.Asymmetric FIR x2 InterpolationFilter Frequency Response, Quad Rate Impulse Response, Quad Rate Figure61.Asymmetric x2 InterpolationFilterPassband Ripple,Quad Rate Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 51 ProductFolderLinks:PCM5141 PCM5142

−0.002 −0.0015 −0.001 −0.0005 0.0005 0.001 0.0015 0.002 Frequency (× fS) Amplitude (dB) G009 −120 −100 −80 −60 −40 −20 0 1 2 3 4 Frequency (× fS) Amplitude (dB) G003 −0.4 −0.2 0.2 0.4 0.6 0.8 0 50 100 150 200 250 300 350 400 450 500 550 600 Samples Amplitude (FFS) G006 PCM5141,PCM5142 SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 www.ti.com Table30.High-Attentuationx8 InterpolationFilter,SingleRate Parameter Condition Value (Typical) Value (Max) Units FilterGain Pass Band 0 … … .0.45fS ±0.0005 dB FilterGain StopBand 0.55fS … ..7.455fS –100 dB FilterGroup Delay 33.7tS S Figure62.High-Attentuationx8 InterpolationFilter Figure63.High-Attentuationx8 InterpolationFilter Frequency Response, SingleRate Impulse Response, SingleRate Figure64.High-Attentuationx8 InterpolationFilterPassband Ripple,SingleRate

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−0.002 −0.0015 −0.001 −0.0005 0.0005 0.001 0.0015 0.002 0 0.5 1 Frequency (× fS) Amplitude (dB) G008 −120 −100 −80 −60 −40 −20 0 1 2 3 4 Frequency (× fS) Amplitude (dB) G002 −0.4 −0.2 0.2 0.4 0.6 0.8 0 50 100 150 200 250 300 Samples Amplitude (FFS) G005 PCM5141,PCM5142 www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 Table31.High-Attentuationx4 InterpolationFilter,Dual Rate Parameter Condition Value (Typical) Value (Max) Units FilterGain Pass Band 0 … … .0.45fS ±0.0005 dB FilterGain StopBand 0.55fS … ..3.455fS –100 dB FilterGroup Delay 33.7tS S Figure65.High-Attentuationx4 InterpolationFilter Figure66.High-Attentuationx4 InterpolationFilter Frequency Response, Dual Rate Impulse Response, Dual Rate Figure67.High-Attentuationx4 InterpolationFilterPassband Ripple,Dual Rate Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 53 ProductFolderLinks:PCM5141 PCM5142

−0.002 −0.0015 −0.001 −0.0005 0.0005 0.001 0.0015 0.002 0 0.5 1 1.5 2 Frequency (× fS) Amplitude (FFS) G007 −120 −100 −80 −60 −40 −20 0 1 2 3 4 Frequency (× fS) Amplitude (dB) G001 −0.4 −0.2 0.2 0.4 0.6 0.8 0 10 20 30 40 50 60 70 80 90 100 110 120 Samples Amplitude (FFS) G004 PCM5141,PCM5142 SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 www.ti.com Table32.High-Attentuationx2 InterpolationFilter,Quad Rate Parameter Condition Value (Typical) Value (Max) Units FilterGain Pass Band 0 … … .0.45fS ±0.0005 dB FilterGain StopBand 0.55fS … ..1.455fS –100 dB FilterGroup Delay 33.7tS S Figure68.High-Attentuationx2 InterpolationFilter Figure69.High-Attentuationx2 InterpolationFilter Frequency Response, Quad Rate Impulse Response, Quad Rate Figure70.High-Attentuationx2 InterpolationFilterPassband Ripple,Quad Rate

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(1) 6 BQ (2) 6 BQ Lch Rch (3) 2 BQ (5) 2 BQ (7) 2 BQ (8) 2 BQ (6) 2 BQ (4) 2 BQ

3 Band

PCM5141,PCM5142 www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 FixedAudio ProcessingFlow (Program 5) The PCM514x familyimplementssignalprocessingcapabilitiesand interpolationfilteringviaprocessingblocks. These fixedprocessingblocksgiveusersthechoiceofhow much and what typeofsignalprocessingtheymay use and whichinterpolationfilterisapplied. The signalprocessingblocksavailableare:

• Biquadfilters
• MultibandDRC
• Mono mixer
• Stereomixer
• Mastervolume The addresses of the coefficientsare fixedwhen selectingthe fixedprocessingflow,however, ifthese components areused intheRAM sourcemode (Program31)theregistersforcoefficientswillchange.Users can findmore detailsinPurepathStudio. ProcessingBlocks – DetailedDescriptions Figure71 shows thefixedprocessingflow. Figure71. PresetProcess Flow Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 55 ProductFolderLinks:PCM5141 PCM5142

D1*2 N1*2 /c40 /c41 2 2 3 zDzD 22 zNzN 2NzH /c45/c45 /c45/c45 /c45/c45 /c43/c43/c61 PCM5141,PCM5142 SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 www.ti.com Figure72 shows a screencaptureofPurePathStudio. Figure72. PurePath StudioScreen Capture Biquad Section The transferfunctionofeach ofthebiquadfiltersisgivenby (2) Figure73. Biquad Block Table33.Biquad FilterCoefficients Filter Channel Coefficient Register N0 C10 (Pg 44,Reg 48,49,50,51) N1 C11 (Pg 44,Reg 52,53,54,55) Lch,BIQUAD (1)-1 BIQUAD (2)-1 N2 C12 (Pg 44,Reg 56,57,58,59)Rch D1 C13 (Pg 44,Reg 60,61,62,63) D2 C14 (Pg 44,Reg 64,65,66,67) N0 C15 (Pg 44,Reg 68,69,70,71) N1 C16 (Pg 44,Reg 72,73,74,75) Lch,BIQUAD (1)-2 BIQUAD (2)-2 N2 C17 (Pg 44,Reg 76,77,78,79)Rch D1 C18 (Pg 44,Reg 80,81,82,83) D2 C19 (Pg 44,Reg 84,85,86,87)

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PCM5141,PCM5142 www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 Table33.Biquad FilterCoefficients(continued) Filter Channel Coefficient Register N0 C20 (Pg 44,Reg 88,89,90,91) N1 C21 (Pg 44,Reg 92,93,94,95) Lch,BIQUAD (1)-3 BIQUAD (2)-3 N2 C22 (Pg 44,Reg 96,97,98,99)Rch D1 C23 (Pg 44,Reg 100,101,102,103) D2 C24 (Pg 44,Reg 104,105,106,107) N0 C25 (Pg 44,Reg 108,109,110,111) N1 C26 (Pg 44,Reg 112,113,114,115) Lch,BIQUAD (1)-4 BIQUAD (2)-4 N2 C27 (Pg 44,Reg 116,117,118,119)Rch D1 C28 (Pg 44,Reg 120,121,122,123) D2 C29 (Pg 44,Reg 124,125,126,127) N0 C30 (Pg 45,Reg 8,9,10,11) N1 C31 (Pg 45,Reg 12,13,14,15) Lch,BIQUAD (1)-5 BIQUAD (2)-5 N2 C32 (Pg 45,Reg 16,17,18,19)Rch D1 C33 (Pg 45,Reg 20,21,22,23) D2 C34 (Pg 45,Reg 24,25,26,27) N0 C35 (Pg 45,Reg 28,29,30,31) N1 C36 (Pg 45,Reg 32,33,34,35) Lch,BIQUAD (1)-6 BIQUAD (2)-6 N2 C37 (Pg 45,Reg 36,37,38,39)Rch D1 C38 (Pg 45,Reg 40,41,42,43) D2 C39 (Pg 45,Reg 44,45,46,47) N0 C40 (Pg 45,Reg 48,49,50,51) N1 C41 (Pg 45,Reg 52,53,54,55) Lch,BIQUAD (3)-1 BIQUAD (4)-1 N2 C42 (Pg 45,Reg 56,57,58,59)Rch D1 C43 (Pg 45,Reg 60,61,62,63) D2 C44 (Pg 45,Reg 64,65,66,67) N0 C45 (Pg 45,Reg 68,69,70,71) N1 C46 (Pg 45,Reg 72,73,74,75) Lch,BIQUAD (3)-2 BIQUAD (4)-2 N2 C47 (Pg 45,Reg 76,77,78,79)Rch D1 C48 (Pg 45,Reg 80,81,82,83) D2 C49 (Pg 45,Reg 84,85,86,87) N0 C50 (Pg 45,Reg 88,89,90,91) N1 C51 (Pg 45,Reg 92,93,94,95) Lch,BIQUAD (5)-1 BIQUAD (6)-1 N2 C52 (Pg 45,Reg 96,97,98,99)Rch D1 C53 (Pg 45,Reg 100,101,102,103) D2 C54 (Pg 45,Reg 104,105,106,107) N0 C55 (Pg 45,Reg 108,109,110,111) N1 C56 (Pg 45,Reg 112,113,114,115) Lch,BIQUAD (5)-2 BIQUAD (6)-2 N2 C57 (Pg 45,Reg 116,117,118,119)Rch D1 C58 (Pg 45,Reg 120,121,122,123) D2 C59 (Pg 45,Reg 124,125,126,127) N0 C60 (Pg 46,Reg 8,9,10,11) N1 C61 (Pg 46,Reg 12,13,14,15) Lch,BIQUAD (7)-1 BIQUAD (8)-1 N2 C62 (Pg 46,Reg 16,17,18,19)Rch D1 C63 (Pg 46,Reg 20,21,22,23) D2 C64 (Pg 46,Reg 24,25,26,27) Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 57 ProductFolderLinks:PCM5141 PCM5142

PCM5141,PCM5142 SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 www.ti.com Table33.Biquad FilterCoefficients(continued) Filter Channel Coefficient Register N0 C65 (Pg 46,Reg 28,29,30,31) N1 C66 (Pg 46,Reg 32,33,34,35) Lch,BIQUAD (7)-2 BIQUAD (8)-2 N2 C67 (Pg 46,Reg 36,37,38,39)Rch D1 C68 (Pg 46,Reg 40,41,42,43) D2 C69 (Pg 46,Reg 44,45,46,47) Dynamic Range Compression Dynamic range compression (DRC) improves the overalllisteningexperience.Typicalmusic signalsare characterizedby crestfactors(theratioofpeak signalpower toaveragesignalpower)of12dB ormore.To avoid audibledistortiondue toclippingofpeak signals,thegainoftheDAC channelmust be adjustedso as notto cause hard clipping.As a result,the low appliedgainduringnominalperiodscauses the perceptionthatthe signalisnotloudenough.To overcome thisproblem,theDRC inthePCM514x continuouslymonitorstheoutput oftheDAC DigitalVolume controltodetectitspower levelwithrespectto0dB full-scale.When thepower levelis low,the DRC increasesthe inputsignalgainto make itsound louder,and reducesthe gainduringpeaks to avoid hard clipping.The DRC enables louderaudio duringnominal periodswitha clearer,more pleasant listeningexperience. The 3-band DRC functionappliesDRC to 3 differentmono/stereosignalswith3 differenttimeconstants.The same DRC curve is appliedon allthe signals,enablinga multi-bandDRC solution.The underlyingDRC algorithmisthesame as thatavailablewiththeDRC component inPurePathStudio.Inthisinstance,theDRC gainactson each signalintime-multiplexedorder,forexample,1-2-3,1-2-3,1-2-3. Table34.DRC Coefficients Coefficient Register Description DRC_MB_1_DRC_1_DRCAE C70 (Pg 46,Reg 48,49,50,51) DRC_MB_1_DRC_1_DRC1AE C71 (Pg 46,Reg 52,53,54,55) DRC_MB_1_DRC_1_DRCAA C72 (Pg 46,Reg 56,57,58,59) DRC_MB_1_DRC_1_DRC1AA C73 (Pg 46,Reg 60,61,62,63) DRC_MB_1_DRC_1_DRCAD C74 (Pg 46,Reg 64,65,66,67) DRC_MB_1_DRC_1_DRC1AD C75 (Pg 46,Reg 68,69,70,71) DRC_MB_1_DRC_2_DRCAE C76 (Pg 46,Reg 72,73,74,75) DRC_MB_1_DRC_2_DRC1AE C77 (Pg 46,Reg 76,77,78,79) DRC_MB_1_DRC_2_DRCAA C78 (Pg 46,Reg 80,81,82,83) DRC_MB_1_DRC_2_DRC1AA C79 (Pg 46,Reg 84,85,86,87) DRC_MB_1_DRC_2_DRCAD C80 (Pg 46,Reg 88,89,90,91) DRC_MB_1_DRC_2_DRC1AD C81 (Pg 46,Reg 92,93,94,95) DRC_MB_1_DRC_3_DRCAE C82 (Pg 46,Reg 96,97,98,99) DRC_MB_1_DRC_3_DRC1AE C83 (Pg 46,Reg 100,101,102,103) DRC_MB_1_DRC_3_DRCAA C84 (Pg 46,Reg 104,105,106,107) DRC_MB_1_DRC_3_DRC1AA C85 (Pg 46,Reg 108,109,119,111) DRC_MB_1_DRC_3_DRCAD C86 (Pg 46,Reg 112,113,114,115) DRC_MB_1_DRC_3_DRC1AD C87 (Pg 46,Reg 116,117,118,119) DRC_MB_1_DRC_DRCK0 C88 (Pg 46,Reg 120,121,122,123) DRC_MB_1_DRC_DRCK1 C89 (Pg 46,Reg 124,125,126,127) DRC_MB_1_DRC_DRCK2 C90 (Pg 47,Reg 8,9,10,11) DRC_MB_1_DRC_DRCMT1 C91 (Pg 47,Reg 12,13,14,15) DRC_MB_1_DRC_DRCMT2 C92 (Pg 47,Reg 16,17,18,19) DRC_MB_1_DRC_DRCOFF1 C93 (Pg 47,Reg 20,21,22,23) DRC_MB_1_DRC_DRCOFF2 C94 (Pg 47,Reg 24,25,26,27) DRC_MB_1_MinusOne_Q22 C95 (Pg 47,Reg 28,29,30,31)

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PCM5141,PCM5142 www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 Table34.DRC Coefficients(continued) Coefficient Register Description DRC_MB_1_MinusTwo_Q22 C96 (Pg 47,Reg 32,33,34,35) DRC_MB_1_One_M2 C97 (Pg 47,Reg 36,37,38,39) DRC_MB_1_Zero C98 (Pg 47,Reg 40,41,42,43) DRC_MB_1_En_dB C99 (Pg 47,Reg 44,45,46,47) DRC_MB_1_Minus__Zero_dB C100 (Pg 47,Reg 48,49,50,51) DRC_MB_1_60_dB C101 (Pg 47,Reg 52,53,54,55) DRC_MB_1_Minus_60_dB C102 (Pg 47,Reg 56,57,58,59) DRC_MB_1_12_dB C103 (Pg 47,Reg 60,61,62,63) DRC_MB_1_Offset C104 (Pg 47,Reg 64,65,66,67) DRC_MB_1_K C105 (Pg 47,Reg 68,69,70,71) DRC_MB_1_x /DRC_MB_1_DRC C106 (Pg 47,Reg 72,73,74,75) DRC_MB_1_48_dB C107 (Pg 47,Reg 76,77,78,79) DRC_MB_1_Minus_48_dB C108 (Pg 47,Reg 80,81,82,83) DRC_MB_1_c1_3 C109 (Pg 47,Reg 84,85,86,87) DRC_MB_1_c1_2 C110 (Pg 47,Reg 88,89,90,91) DRC_MB_1_c1_1 C111 (Pg 47,Reg 92,93,94,95) DRC_MB_1_c1_0 C112 (Pg 47,Reg 96,97,98,99) DRC_MB_1_O1_1 C113 (Pg 47,Reg 100,101,102,103) DRC_MB_1_S1_1 C114 (Pg 47,Reg 104,105,106,107) DRC_MB_1_O1_2 C115 (Pg 47,Reg 108,109,119,111) DRC_MB_1_S1_2 C116 (Pg 47,Reg 112,113,114,115) DRC_MB_1_O1_3 C117 (Pg 47,Reg 116,117,118,119) DRC_MB_1_S1_3 C118 (Pg 47,Reg 120,121,122,123) DRC_MB_1_One_1_Q17 C119 (Pg 47,Reg 124,125,126,127) DRC_MB_1_Scale1 C120 (Pg 48,Reg 8,9,10,11) DRC_MB_1_x1Coeff C121 (Pg 48,Reg 12,13,14,15) DRC_MB_1_c2_3 C122 (Pg 48,Reg 16,17,18,19) DRC_MB_1_c2_2 C123 (Pg 48,Reg 20,21,22,23) DRC_MB_1_c2_1 C124 (Pg 48,Reg 24,25,26,27) DRC_MB_1_c2_0 C125 (Pg 48,Reg 28,29,30,31) DRC_MB_1_O2_1 C126 (Pg 48,Reg 32,33,34,35) DRC_MB_1_S2_1 C127 (Pg 48,Reg 36,37,38,39) DRC_MB_1_O2_2 C128 (Pg 48,Reg 40,41,42,43) DRC_MB_1_S2_2 C129 (Pg 48,Reg 44,45,46,47) DRC_MB_1_O2_3 C130 (Pg 48,Reg 48,49,50,51) DRC_MB_1_S2_3 C131 (Pg 48,Reg 52,53,54,55) DRC_MB_1_One_2_Q17 C132 (Pg 48,Reg 56,57,58,59) DRC_MB_1_Scale2 C133 (Pg 48,Reg 60,61,62,63) DRC_MB_1_x2Coeff C134 (Pg 48,Reg 64,65,66,67) DRC_MB_1_R1_1 C135 (Pg 48,Reg 68,69,70,71) DRC_MB_1_R1_2 C136 (Pg 48,Reg 72,73,74,75) DRC_MB_1_R2_1 C137 (Pg 48,Reg 76,77,78,79) DRC_MB_1_R2_2 C138 (Pg 48,Reg 80,81,82,83) DRC_MB_1_Band1_GainC C139 (Pg 48,Reg 84,85,86,87) DRC_MB_1_Band2_GainC C140 (Pg 48,Reg 88,89,90,91) DRC_MB_1_Band3_GainC C141 (Pg 48,Reg 92,93,94,95) DRC_MB_1_MinusOne_M1 C142 (Pg 48,Reg 96,97,98,99) Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 59 ProductFolderLinks:PCM5141 PCM5142

x x x x x x Gain3 Gain2 Gain1 Lch Rch /c40 /c41 /c40 /c41 /c40 /c41 /c40 /c41/c229 /c183/c61 iG a inn , i L _In p u tnL _O u t PCM5141,PCM5142 SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 www.ti.com Table34.DRC Coefficients(continued) Coefficient Register Description DRC_MB_1_One_M1 C143 (Pg 48,Reg 100,101,102,103) DRC_MB_1_Band1_GainE C144 (Pg 48,Reg 104,105,106,107) DRC_MB_1_Band2_GainE C145 (Pg 48,Reg 108,109,110,111) DRC_MB_1_Band3_GainE C146 (Pg 48,Reg 112,113,114,115) DRC_MB_1_minus_One_M2 C147 (Pg 48,Reg 116,117,118,119) StereoMixer Threestereoinputsaremixed intoone stereooutputwithinputsignalgaingivenby Equation3. where

• i=1:2,3 (3) Figure74 and Table35 show thestrereomixeroperation. Figure74. Figure4.StereoMixerBlock Table35.StereoMixerCoefficients Coefficient Register Description Stereo_Mixer_1_MixGain1 C148 (Pg 48,Reg 120,121,122,123) Stereo_Mixer_1_MixGain2 C149 (Pg 48,Reg 124,125,126,127) Stereo_Mixer_1_MixGain3 C150 (Pg 49,Reg 8,9,10,11) StereoMultiplexer The StereoMultiplexerselectsone or2 from4 stereoinputchannels. Figure75. StereoMultiplexerBlock

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x x Mono output Gain1 Gain2 PCM5141,PCM5142 www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 Table36.StereoMultiplexerSelectCoefficient Coefficient Register Description Stereo_Mux_1_MuxSelect C152 (Pg 49,Reg 16,17,18,19) Table37.StereoMultiplexerInputCoefficient Coefficient Register Description C_to_D_1_Coefval C153 (Pg 49,Reg 20,21,22,23)C_to_D_2_Coefval Mono Mixer The Mono Mixercomputes a weightedsum of2 inputchannelsand producesan output. Figure76. Figure6.Mono MixerBlock Table38.Mono MixerCoefficients Coefficient Register Description Mono_Mixer_1_MixGain1 C154 (Pg 49,Reg 24,25,26,27) Mono_Mixer_1_MixGain2 C155 (Pg 49,Reg 28,29,30,31) Master Volume Control The MasterVolume controlsthevolume usinga linearramp and zerocrossingdetectionfortransitions. Table39.Mono MixerCoefficients Coefficient Register Description Volume_ZeroX_1_volcmd C158 (Pg 49,Reg 40,41,42,43) Volume_ZeroX_1_volout C159 (Pg 49,Reg 44,45,46,47) Volume_ZeroX_1_volout_loudne C160 (Pg 49,Reg 48,49,50,51)ss Volume_ZeroX_1_MinusOne_M2 C161 (Pg 49,Reg 52,53,54,55) Volume_ZeroX_1_workingval_1_ C162 (Pg 49,Reg 56,57,58,59)pre_CRAM Volume_ZeroX_1_volout_pre1 C163 (Pg 49,Reg 60,61,62,63) Volume_ZeroX_1_workingval_2_ C164 (Pg 49,Reg 64,65,66,67)pre_CRAM Volume_ZeroX_1_volout_pre2 C165 (Pg 49,Reg 68,69,70,71) Volume_ZeroX_1_workingval_3_ C166 (Pg 49,Reg 72,73,74,75)pre_CRAM Volume_ZeroX_1_volout_pre3 C167 (Pg 49,Reg 76,77,78,79) Volume_ZeroX_1_One_M2 C168 (Pg 49,Reg 80,81,82,83) Volume_ZeroX_1_Zero C169 (Pg 49,Reg 84,85,86,87) MinusOne_Int C170 (Pg 49,Reg 88,89,90,91) MinusOne_M1 C171 (Pg 49,Reg 92,93,94,95) One_M2 C172 (Pg 49,Reg 96,97,98,99) One_M1 C173 (Pg 49,Reg 100,101,102,103) Zero C174 (Pg 49,Reg 104,105,106,107) Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 61 ProductFolderLinks:PCM5141 PCM5142

PCM5141,PCM5142 SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 www.ti.com MiscellaneousCoefficients Table40.MiscellaneousCoefficients Coefficient Register Description DRC_MB_1_DataBlock C175 (Pg 49,Reg 108,109,110,111) DRC_MB_1_CoeffBlock C176 (Pg 49,Reg 112,113,114,115) Volume_ZeroX_1_DataBlock C177 (Pg 49,Reg 116,117,118,119) Volume_ZeroX_1_CoeffBlock C178 (Pg 49,Reg 120,121,122,123) plus_one C179 (Pg 49,Reg 124,125,126,127) ADD_OF_filter_in_L C180 (Pg 50,Reg 8,9,10,11) ADD_OF_filter_in_R C181 (Pg 50,Reg 12,13,14,15) Analog Gain Control Analoggaincontrolcan be selectedbetween 2Vrms FS (0dB)or1Vrms FS (-6dB).Gain iscontrolledviahardware by theAGNS pin,and viasoftware(SPI/I2C),Page 1,Register2,D4(L-ch)/D0(R-ch). DigitalVolume Control A basicdigitalvolume controlwithrangefrom24 dB to-103dB and mute isavailableon each channelsby Page 0, Resister61, D(7:0)forL-ch and Register62, D(7:0)forR-ch.These volume controlsallhave 0.5 dB step programmabilityover most gainand attenuationranges.Table 41 liststhe detailedgainversusprogrammed settingforthisbasicvolume control.Volume can be changed forboth L-ch and R-ch at the same time or independentlyby Page 0, Register60, D(1:0).When D(1:0)set00 (default),independentcontrolisselected. When D(1:0)set01,R-ch accordswithL-chvolume.When D(1:0)set10,L-chaccordswithR-ch volume.To set D(1:0)to11 isprohibited. Table41.DigitalVolume ControlSettings Gain GainBinaryData CommentsSetting (dB) 0 0000-0000 24.0 Positivemaximum 1 0000-0001 23.5 : : : 46 0010-1110 1.0 47 0010-1111 0.5 48 0011-0000 0.0 No attenuation(default) 49 0011-0001 -0.5 50 0011-0010 -1.0 51 0011-0011 -1.5 : : : 253 1111-1101 -102.5 254 1111-1110 -103 Negativemaximum 255 1111-1111 -∞ Negativeinfinite(Mute) Ramp-up frequencyand ramp-down frequencycan be controlledby Page 0,Register63,D(7:6)and D(3:2)as shown inTable42.AlsoRamp-up stepand ramp-down stepcan be controlledby Page 0,Register63 D(5:4)and D(1:0)as shown inTable43. Table42.Ramp Up or Down Frequency Ramp up Ramp downEvery N fS Comments Every N fS Commentsspeed frequency 00 1 Default 00 1 Default 01 2 01 2 10 4 10 4

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PCM5141,PCM5142 www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 Table42.Ramp Up or Down Frequency (continued)

11 Directchange 11 Directchange

Table43.Ramp Up or Down Step Ramp downRamp up step Step dB Comments Step dB Commentsstep 00 4.0 00 -4.0 01 2.0 01 -2.0 10 1.0 Default 10 -1.0 Default 11 0.5 11 -0.5 Emergency Ramp Down Digitalvolume emergency ramp down by isprovidedforsituationssuch as I2S clockerrorand power supply failure.Ramp-down speed iscontrolledby Page 0,Register64,D(7:6).Ramp-down stepcan be controlledby Page 0 Register64,D(5:4).Defaultisramp-down by everyfS cyclewith-4dB step. Zero Data Detect The PCM514x has a zero-detectfunction.When thedevicedetectsthecontinuouszerodataforbothL-chand R-cn,orseparateL-cnand R-ch,Analogmutes aresettobothOUTL and OUTR, orseparateOUTL and OUTR. These arecontrolledby Page0,Register65,D(2:1)as shown inTable44. ContinuousZero datacyclesarecountedby LRCK, and thethresholdofdecisionforanalogmute can be setby Page 0,Register59,D(6:4)forL-ch,and D(2:0)forRch as shown inTable45.Defaultvaluesare 0 forboth channels. InHardware mode, thedeviceuses defaultvalues. Table44.Zero DetectionMode ATMUTECTL Value Function

0 IndependentlyL-chorR-ch arezerodataforzerodetection

Bit:2 1 (Default) BothL-chand R-ch have tobe zerodataforzerodetection

0 Zerodetectionand analogmute aredisabledforR-ch

Bit:1 1 (Default) Zerodetectionanalogmute areenabledforR-ch

0 Zerodetectionanalogmute aredisabledforL-ch

Bit:0 1 (Default) Zerodetectionanalogmute areenabledforL-ch Table45.Zero Data DetectionTime ATMUTETIML / Number ofLRCKs Time @ 48kHzATMUTETIMR 0 0 0 1024 21 ms 0 0 1 5120 106 ms 0 1 0 10240 213 ms 0 1 1 25600 533 ms 1 0 0 51200 1.066sec 1 0 1 102400 2.133sec 1 1 0 256000 5.333sec 1 1 1 512000 10.66sec Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 63 ProductFolderLinks:PCM5141 PCM5142

PCM5141,PCM5142 SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 www.ti.com Power Save Modes The PCM514x offerstwo power-savemodes; standbyand power-down. When a clockerror(SCK, BCK, and LRCK) orclockhaltisdetected,thePCM514x automaticallyentersstandby mode. The DAC and linedriverare alsopowered down. The devicecan alsobe placedinstandbymode via softwarecommand. When BCK and LRCK remainata low levelformore than1 second,thePCM514x automaticallyenterspower- down mode. Power-down mode disablesthe negativecharge pump and bias/referencecircuit,in additionto thosedisabledinstandbymode. The devicecan alsobe placedinpower-down mode viasoftwarecommand. The detectiontimeofBCK and LRCK haltcan be controlledby Page 0,Register44,D(2:0). When expectedAudio clocks(SCK, BCK, LRCK) are appliedto the PCM514x, the devicestartsitspowerup sequence automatically.The detectiontimeforBCK and LRCK haltisprogrammable.

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0.9 * DV DD tr tf <20ns <20ns 0.1 * DV DD PCM5141,PCM5142 www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 Power Save Parameter Programming Register Description Page 0,Register2,D(4) Softwarestandbymode command Page 0,Register2,D(0) Softwarepower-down command Softwarepower-upsequence command (requiredaftersoftwarestandbyorpower-Page 0,Register2,D(4)and D(0) down) Page 0,Register44,D(2:0) DetectiontimeofBCK and LRCK halt XSMT Pin (SoftMute /SoftUn-Mute) For externaldigitalcontrolofthePCM514x, theXSMT pinneeds tobe drivenby an externaldigitalhostwitha specific/minimumrisingtime(tr) and fallingtime(tf) forsoftmute and softun-mute.The PCM514x expectstr/tf timesoflessthan20ns.Inthemajorityofapplications,thisshouldn’tbe a problem,however,traceswithhigh capacitancemay have issues. When the XSMT pinisshiftedfrom highto low (3.3Vto 0V),a softdigitalattenuationramp isstarted.-1dB attenuationwillbe appliedeverysample timefrom 0dBFS to- ∞.The softattenuationramp takes104 sample times. When theXSMT pinisshiftedfromlowtohigh(0V to3.3V),a softdigital“un-mute”isstarted.1dB gainstepsare appliedeverysample timefrom-∞ to0dBFS. The un-mutetakes104 sample times. Figure77. XSMT Timing forSoftMute and SoftUn-Mute Table46.XSMT Timing Parameters Parameters Min Max Unit Risetime(tr) 20 ns Falltime(tf) 20 ns Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 65 ProductFolderLinks:PCM5141 PCM5142

0.9 * DVDD 0.1 * DVDD 2.0 V 1.2 V XSMT tf Digital Attenuation Followed by Analog Mute Analog Mute System VDD XSMT 7.25k/c87 2.75k/c87 12V supply PCM5141,PCM5142 SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 www.ti.com ExternalPower Sense UndervoltageProtectionmode (supportedonlywhen DVDD = 3.3V) The XSMT pincan alsobe used tomonitora system voltage,such as the24VDC LCD TV backlight,or12VDC systemsupplyusinga voltagedividercreatedwithtwo resistors.(See Figure78 )

• IftheXSMT pinmakes a transitionfrom“1”to“0”over6ms ormore,thedeviceswitchesintoexternalunder- voltageprotectionmode. Thismode uses two triggerlevels.
• When theXSMT pinlevelreaches2V,softmute processbegins.
• When theXSMT pinlevelreaches1.2V,analogmute engages,regardlessofdigitalaudiolevel,and analog shutdownbegins.(DAC and relatedcircuitrypowers down). A timingdiagramtoshow thisisshown inFigure79. NOTE The XSMT inputpinvoltagerange isfrom -0.3Vto DVDD + 0.3V.Theratioof external resistorsmust produce a voltagewithinthisinputrange.Any increaseinpower supply (such as power supply positivenoise or ripple)can pullthe XSMT pin higherthan DVDD+0.3V. For example,ifthePCM514x ismonitoringa 12V input,and dividingthevoltageby 4,thenthevoltageatXSMT duringidealpower supplyconditionswillbe 3V. A voltagespikehigherthan14.4V causes a voltagegreaterthan 3.6V(DVDD+0.3) on theXSMT pin,potentiallydamaging thedevice. Providingthedividerissetappropriately,any DC voltagecan be monitored. Figure78. XSMT inExternalUVP Mode Figure79. XSMT Timing forUndervoltageProtection

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3.3V XSMT I2S Clocks SCK, BCK, LRCK 150t + 0.2msS VDD High Low High Low Time PCM5141,PCM5142 www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 Recommended Powerdown Sequence With inadequatesystem design,thePCM514x can exhibitsome pop on power down. Pops are caused by the devicenothavingenough timetodetectpower lossand startthemutingprocess. The PCM514x evaluationboard avoidsaudiblepop withan electrolyticdecouplingcapacitor.This capacitor providesenough timebetween datalossfrom USB or S/PDIF and power supplylossforthemutingprocessto takeplace. The PCM514x has two auto-mutefunctionstomute thedeviceupon power loss(intentionalorunintentional). XSMT = 0 When theXSMT pinispulledlow,theincomingPCM dataisattenuatedto0,closelyfollowedby a hardanalog mute.Thisprocesstakes150 sample times(ts)+ 0.2mS. As thismute timeismainlydominatedby thesamplingfrequency,systemssamplingat192kHz willmute much fasterthana 48kHz system. Clock ErrorDetect When clockerrorisdetectedon theincomingdataclock,thePCM514x familyswitchestoan internaloscillator, and continuestothedrivetheDAC, whileattenuatingthedatafrom thelastknown value.Once thisprocessis complete,thePCM514x outputswillbe hardmuted toground. Planned Shutdown These auto-mutingprocessescan be manipulatedby system designstomute beforepower lossinthefollowing ways: 1. AssertXSMT low150tS + 0.2mS beforepower isremoved. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 67 ProductFolderLinks:PCM5141 PCM5142

MCU GPIO “mute” signal 3.3V XSMT I2S Clocks SCK, BCK, LRCK 3msec VDD High Low High Low Time PCM5141,PCM5142 SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 www.ti.com 2. StopI2S clocks(SCK, BCK, LRCK) 3ms beforepowerdown as shown below: Unplanned Shutdown Many systemsuse a low-noiseregulatortoprovidean AVDD 3.3V supplyfortheDAC. The XSMT Pincan take advantageofsuch a featuretomeasure thepre-regulatedoutputfromthesystemSMPS tomute theDAC before theentireSMPS discharges.Figure80 shows how toconfiguresuch a system touse theXSMT pin.The XSMT pincan alsobe used inparallelwitha GPIO pinfromthesystemmicrocontroller/DSPorPower Supply. Figure80. Using theXSMT Pin SoftwareControl SPI Interface The SPI interfaceisa 4-wiresynchronousserialportwhichoperatesasynchronouslytotheserialaudiointerface and thesystemclock(SCK).The serialcontrolinterfaceisused toprogramand readtheon-chipmode registers. The controlinterfaceincludesMISO (pin24),MOSI (pin11),MC (pin12),and MS (pin18).MISO (MasterIn SlaveOut)istheserialdataoutput,used toreadback thevaluesofthemode registers;MOSI (MasterOut Slave In)istheserialdatainput,used toprogramthemode registers. MC istheserialbitclock,used toshiftdatainand outofthecontrolportby fallingedge ofMC, and MS isthe mode controlenablewithLOW active,used toenabletheinternalmode registeraccess.Iffeedbackfrom the deviceisnotrequired,theMISO pincan be assignedtoGPIO1 by registercontrol.

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W BYTE 4BYTE 3 BYTE 7BYTE 6BYTE 1 BYTE 2 A6 A5 A4 A3 A2 A1 A0 W D6 D5 D4 D3 D2 D1 D0D7 MS MC MOSI MISO HI-Z IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 D7 D6 D5 D4 D3 D2 D1 D0 Register Index (or Address) Register Data MSB LSB R/W PCM5141,PCM5142 www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 RegisterRead/WriteOperation Allread/writeoperationsfortheserialcontrolportuse 16-bitdatawords.Figure81 shows thecontroldataword format.The most significantbitisthe read/writebit.For writeoperations,the bitmust be setto 0. For read operations,the bitmust be set to 1. There are seven bits,labeledIDX[6:0],thathold the registerindex(or address)forthereadand writeoperations.The leastsignificanteightbits,D[7:0],containthedatatobe written to,orthedatathatwas readfrom,theregisterspecifiedby IDX[6:0]. Figure81 and Figure82 show thefunctionaltimingdiagramtowriteorreadthroughtheserialcontrolport.MS is heldata logic-1stateuntila registeraccess.To starttheregisterwriteorreadcycle,setMS tologic0.Sixteen clocksare thenprovidedon MC, correspondingtothe16 bitsofthecontroldataword on MOSI and read-back data on MISO. Afterthe eighthclockcyclehas completed,the data from the indexed-mode controlregister appearson MISO duringtheread operation.Afterthesixteenthclockcyclehas completed,thedataislatched intotheindexed-modecontrolregisterduringthewriteoperation.To writeorreadsubsequentdata,MS issetto logic1 once (See tMHH inFigure86). Figure81. ControlData Word Format;MDI NOTE B8 isused forselectionof “Write” or “Read ”. Setting= 0 indicatesa “Write”, while= 1 indicatesa ”Read ”.Bits15–9 areused forregisteraddress.Bits7–0 areused forregister data.Multiple-bytewriteor read (up to 8 bytes)issupportedwhileMS iskeptlow.The addressfieldbecomes theinitialaddress,automaticallyincrementingforeach byte. Figure82. SerialControlFormat;Write,SingleByte Figure83. SerialControlFormat;Write,MultipleByte Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 69 ProductFolderLinks:PCM5141 PCM5142

R BYTE 4BYTE 3 BYTE 7BYTE 6BYTE 1 BYTE 2 HI-Z BYTE 5BYTE 0 BYTE 4BYTE 3 BYTE 7BYTE 6BYTE 1 BYTE 2 A6 A5 A4 A3 A2 A1 A0 R D6 D5 D4 D3 D2 D1 D0D7 MS MC MOSI MISO D6 D5 D4 D3 D2 D1 D0D7HI-Z HI-Z PCM5141,PCM5142 SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 www.ti.com Figure84. SerialControlFormat;Read Figure85. SerialControlFormat;Read, MultipleByte Figure86. ControlInterfaceTiming

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PCM5141,PCM5142 www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 Table47.ControlInterfaceTiming Parameters Min Max Units tMCY MC PulseCycleTime 100 tMCL MC Low LevelTime 40 tMCH MC HighLevelTime 40 tMHH MS HighLevelTime 20 tMSS MS ↓ Edge toMC ↑ Edge 30 ns tMSH MS HoldTime(1) 30 tMDH MDI HoldTime 15 tMDS MDI Set-upTime 15 tMOS MC RiseEdge toMDO Stable 20 (1) MC fallingedge forLSB toMS risingedge. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 71 ProductFolderLinks:PCM5141 PCM5142

1–7 8 1–8 9 1–8 9 9 Sp Stop condition Slave address R/W ACK DATA ACK DATA ACK ACK R/W: Read operation if 1; otherwise, write operation ACK: Acknowledgement of a byte if 0 DATA: 8 bits (byte) MSB LSB INC A6 A5 A4 A3 A2 A1 A0 PCM5141,PCM5142 SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 www.ti.com I2C Interface The PCM514x supportstheI2C serialbus and thedatatransmissionprotocolforstandardand fastmode as a slavedevice.ThisprotocolisexplainedintheI2C specification2.0. InI2C mode, thecontrolterminalsarechanged as follows. Table48.I2C Pins and Functions Signal Pin I/O Description SDA 11 I/O I2C data SCL 12 I I2C clock ADR2 16 I I2C address2 ADR1 24 I I2C address1 SlaveAddress Table49.I2C SlaveAddress MSB LSB 1 0 0 1 1 ADR2 ADR1 R/ W The PCM514x has 7 bitsforitsown slaveaddress.The firstfivebits(MSBs) oftheslaveaddressare factory presetto10011.The nexttwo bitsoftheaddressbyteare thedeviceselectbitswhich can be user-definedby theADR1 and ADR0 terminals.A maximum offourPCM51xxs can be connectedon thesame bus atone time. Each PCM514x respondswhen itreceivesitsown slaveaddress. RegisterAddress Auto-IncrementMode Figure87. Auto IncrementMode Auto-incrementmode allowsmultiplesequentialregisterlocationsto be writtento or read back in a single operation,and isespeciallyusefulforblockwriteand readoperations. Packet Protocol A master devicemust controlpacketprotocol,which consistsof startcondition,slaveaddress,read/writebit, dataifwriteor acknowledgeifread,and stopcondition.The PCM514x supportsonlyslavereceiversand slave transmitters. Figure88. Packet Protocol

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PCM5141,PCM5142 www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 Table50.WriteOperation-Basic I2C Framework Transmitter M M M S M S M S S M Data Type St slaveaddress R/ ACK DATA ACK DATA ACK ACK Sp Table51.Read Operation-Basic I2C Framework Transmitter M M M S S M S M M M Data Type St slaveaddress R/ ACK DATA ACK DATA ACK NACK Sp M = MasterDevice;S = SlaveDevice;St= StartConditionSp = StopCondition WriteRegister A mastercan writetoany PCM514x registersusingsingleormultipleaccesses.The mastersends a PCM514x slaveaddress witha writebit,a registeraddress withauto-incrementbit,and the data.Ifauto-incrementis enabled,the addressisthatof the startingregister,followedby the data to be transferred.When the data is receivedproperly,theindexregisterisincrementedby 1 automatically.When theindexregisterreaches0x7F, thenextvalueis0x0.Table52 shows thewriteoperation. Table52.WriteOperation Transmitter M M M S M S M S M S S M reg write writeData Type St slaveaddr W ACK inc ACK ACK ACK ACK Spaddr data1 data2 M = MasterDevice;S = SlaveDevice;St= StartConditionSp = StopCondition;W = Write;ACK = Acknowledge Read Register A mastercan readthePCM514x register.The valueoftheregisteraddressisstoredinan indirectindexregister inadvance.The mastersends a PCM514x slaveaddresswitha readbitafterstoringtheregisteraddress.Then thePCM514x transfersthedatawhich theindexregisterpointsto.When auto-incrementisenabled,theindex registerisincrementedby 1 automatically.When theindexregisterreaches0x7F,thenextvalueis0x0.Table53 shows thereadoperation. Table53.Read Operation Transmitter M M M S M S M M M S S M M M slave reg slaveData Type St W ACK inc ACK Sr R ACK data ACK NACK Spaddr addr addr M = MasterDevice;S = SlaveDevice;St = StartCondition;Sr = Repeated startcondition;Sp = Stop Condition; W = Write;R = Read; NACK = Not acknowledge Timing Characteristics Figure89. RegisterAccess Timing Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 73 ProductFolderLinks:PCM5141 PCM5142

PCM5141,PCM5142 SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 www.ti.com Table54.I2C Bus Timing SYMBOL PARAMETER CONDITIONS MIN MAX UNIT Standard 100 kHz fSCL SCL clockfrequency Fast 400 kHz Standard 4.7Bus freetimebetween a STOP and STARTtBUF µscondition Fast 1.3 Standard 4.7 tLOW Low periodoftheSCL clock µs Fast 1.3 Standard 4.0 µs tHI HighperiodoftheSCL clock Fast 600 ns Standard 4.7 µs tRS-SU Setuptimefor(repeated)STARTcondition Fast 600 ns tS-HD Standard 4.0 µs Holdtimefor(repeated)STARTcondition tRS-HD Fast 600 ns Standard 250 tD-SU Data setuptime ns Fast 100 Standard 0 900 tD-HD Data holdtime ns Fast 0 900 Standard 20 + 0.1CB 1000 tSCL-R RisetimeofSCL signal ns Fast 20 + 0.1CB 300 Standard 20 + 0.1CB 1000RisetimeofSCL signalaftera repeatedSTARTtSCL-R1 nsconditionand afteran acknowledgebit Fast 20 + 0.1CB 300 Standard 20 + 0.1CB 1000 tSCL-F FalltimeofSCL signal ns Fast 20 + 0.1CB 300 Standard 20 + 0.1CB 1000 tSDA-R RisetimeofSDA signal ns Fast 20 + 0.1CB 300 Standard 20 + 0.1CB 1000 tSDA-F FalltimeofSDA signal ns Fast 20 + 0.1CB 300 Standard 4.0 µs tP-SU SetuptimeforSTOP condition Fast 600 ns C B CapacitiveloadforSDA and SCL line 400 pF tSP Pulsewidthofspikesuppressed Fast 50 ns NoisemarginatHighlevelforeach connectedVNH 0.2VDD Vdevice(includinghysteresis)

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PCM5141,PCM5142 www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 PCM514x RegisterMap Inany page,register0 isthePage SelectRegister.The registervalueselectstheRegisterPage from0 to255 fornextreadorwritecommand. Table55.RegisterMap Summary (continued) Table55.RegisterMap Summary 43 DSP programselection Register Description 44 Clockmissingdetectionperiod Number 59 Automute time Page 0 60 -64 Digitalvolume

0 Controlregister 65 Automute

1 Analogcontrolregister 75 -79 Reserved

2 Standby,Powerdown requests 80 -85 GPIOn outputselection

3 Mute 86,87 GPIO control

4 PLL Lock Flag,PLL enable

88,89 Reserved

5 Reserved 90 DSP overflow

6 SPI MISO functionselect 91 -94 Sample ratestatus

7 De-emphasisenable,SDOUT select

8 GPIO enables 108 Analogmute monitor

9 BCK, LRCLK configuration 109 -118 Reserved

10 DSP GPIO Input 119 GPIO input

11 Reserved

120 AutoMute flags

12 Mastermode BCK, LRCLK reset

13 PLL clocksourceselect 1 Outputamplitudetype

14 -19 Reserved 2 Analoggaincontrol 20 -24 PLL dividers 3,4 Reserved 25,26 Reserved

5 Undervoltageprotection

27 DSP clockdivider

6 Analogmute control

28 DAC clockdivider 7 Analoggainboost

29 NCP clockdivider 8,9 VCOM configuration

30 OSR clockdivider Page 44

31 Reserved

1 Coefficientmemory (CRAM) control

32,33 Mastermode dividers Pages 44 -52 Coefficientbuffer-A (256coeffsx 24 bits):See 34 fS speed mode Table56 35,36 IDAC (numberofDSP clockcyclesavailablein Pages 66 -74 Coefficientbuffer-B (256coeffsx 24 bits):See one audioframe) Table57

37 Ignorevariouserrors Pages 152 - Instructionbuffer(1024instructionx 25 bits),

186 I512-I1023arereserved.:See Table5838,39 Reserved Pages 187 - Reserved40,41 I2S configuration

25542 DAC datapath

Table56.CoefficientBuffer-AMap CoeffNO Page NO Base Register Base Register+0 Base Register+1 Base Register+2 Base Register+3 C0 44 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C1 44 12 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C29 44 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C30 45 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C59 45 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C60 46 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 75 ProductFolderLinks:PCM5141 PCM5142

PCM5141,PCM5142 SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 www.ti.com Table56.CoefficientBuffer-AMap (continued) C89 46 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C90 47 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C119 47 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C120 48 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C149 48 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C150 49 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C179 49 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C180 50 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C209 50 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C210 51 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C239 51 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C240 52 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C255 52 68 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. Table57.CoefficientBuffer-BMap CoeffNO Page NO Base Register Base Register+0 Base Register+1 Base Register+2 Base Register+3 C0 62 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C1 62 12 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C29 62 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C30 63 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C59 63 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C60 64 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C89 64 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C90 65 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C119 65 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C120 66 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C149 66 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C150 67 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C179 67 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C180 68 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C209 68 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C210 69 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C239 69 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C240 70 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved.

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PCM5141,PCM5142 www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 Table57.CoefficientBuffer-BMap (continued) C255 70 68 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. Table58.miniDSP InstructionMap CoeffNO Page NO Base Register Base Register+0 Base Register+1 Base Register+2 Base Register+3 I0 152 8 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0) I1 152 12 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0) I29 152 124 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0) I30 153 8 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0) I59 153 124 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0) I60 154 8 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0) I89 154 124 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0) I90 155 8 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0) I119 155 124 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0) I120 156 8 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0) I149 156 124 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0) I150 157 8 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0) I179 157 124 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0) I180 158 8 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0) I209 158 124 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0) I210 159 8 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0) I239 159 124 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0) I240 160 8 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0) I269 160 124 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0) I270 161 8 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0) I299 161 124 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0) I300 162 8 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0) I329 162 124 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0) I330 163 8 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0) I359 163 124 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0) I360 164 8 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0) I389 164 124 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0) I390 165 8 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0) I419 165 124 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0) Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 77 ProductFolderLinks:PCM5141 PCM5142

PCM5141,PCM5142 SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 www.ti.com Table58.miniDSP InstructionMap (continued) I420 166 8 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0) I449 166 124 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0) I450 167 8 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0) I479 167 124 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0) I480 168 8 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0) I509 168 124 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0) I510 169 8 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0) I511 169 12 Instr(31:24) Instr(23:16) Instr(15:8) Instr(7:0) I539 169 124 Reserved. Reserved. Reserved. Reserved. I540 170 8 Reserved. Reserved. Reserved. Reserved. I569 170 124 Reserved. Reserved. Reserved. Reserved. I570 171 8 Reserved. Reserved. Reserved. Reserved. I599 171 124 Reserved. Reserved. Reserved. Reserved. I600 172 8 Reserved. Reserved. Reserved. Reserved. I629 172 124 Reserved. Reserved. Reserved. Reserved. I630 173 8 Reserved. Reserved. Reserved. Reserved. I659 173 124 Reserved. Reserved. Reserved. Reserved. I660 174 8 Reserved. Reserved. Reserved. Reserved. I689 174 124 Reserved. Reserved. Reserved. Reserved. I690 175 8 Reserved. Reserved. Reserved. Reserved. I719 175 124 Reserved. Reserved. Reserved. Reserved. I720 176 8 Reserved. Reserved. Reserved. Reserved. I749 176 124 Reserved. Reserved. Reserved. Reserved. I750 177 8 Reserved. Reserved. Reserved. Reserved. I779 177 124 Reserved. Reserved. Reserved. Reserved. I780 178 8 Reserved. Reserved. Reserved. Reserved. I809 178 124 Reserved. Reserved. Reserved. Reserved. I810 179 8 Reserved. Reserved. Reserved. Reserved. I839 179 124 Reserved. Reserved. Reserved. Reserved. I840 180 8 Reserved. Reserved. Reserved. Reserved. I869 180 124 Reserved. Reserved. Reserved. Reserved. I870 181 8 Reserved. Reserved. Reserved. Reserved.

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PCM5141,PCM5142 www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 Table58.miniDSP InstructionMap (continued) I899 181 124 Reserved. Reserved. Reserved. Reserved. I900 182 8 Reserved. Reserved. Reserved. Reserved. I929 182 124 Reserved. Reserved. Reserved. Reserved. I930 183 8 Reserved. Reserved. Reserved. Reserved. I959 183 124 Reserved. Reserved. Reserved. Reserved. I960 184 8 Reserved. Reserved. Reserved. Reserved. I989 184 124 Reserved. Reserved. Reserved. Reserved. I990 185 8 Reserved. Reserved. Reserved. Reserved. I1019 185 124 Reserved. Reserved. Reserved. Reserved. I1020 186 8 Reserved. Reserved. Reserved. Reserved. I1023 186 20 Reserved. Reserved. Reserved. Reserved. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 79 ProductFolderLinks:PCM5141 PCM5142

PCM5141,PCM5142 SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 www.ti.com DetailedRegisterDescriptions Page 0 /Register1 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 1 01 RSV RSV RSV RSTM RSV RSV RSV RSTR ResetValue 0 0 RSV Reserved Reserved.Do notaccess. RSTM Reset Modules Thisbitresetstheinterpolationfilterand theDAC modules.SincetheDSP isalsoreset,thecoeffientRAM contentwillalsobe clearedby theDSP. Thisbitisautoclearedand can be setonlyinstandbymode. Defaultvalue:0 0:Normal 1:Resetmodules RSTR Reset Registers Thisbitresetsthemode registersback totheirinitialvalues.The RAM contentisnotcleared,buttheexecution sourcewillbe back toROM. Thisbitisautoclearedand must be setonlywhen theDAC isinstandbymode (resettingregisterswhen theDAC isrunningisprohibitedand notsupported). Defaultvalue:0 0:Normal 1:Resetmode registers Page 0 /Register2 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 2 02 RSV RSV RSV RQST RSV RSV RSV RQPD ResetValue 0 0 RSV Reserved Reserved.Do notaccess. RQST Standby Request When thisbitisset,theDAC isforcedintosystemstandbymode, whichisalsothemode thesystementersin case ofclockerrors.Inthismode, most subsystemsarepowered down exceptforthechargepump and digital power supply. Defaultvalue:0 0:Normal operation 1:Standbymode RQPD Powerdown Request SettingRQPD sends theDAC intopowerdown mode, reducingpower consumptiontoa minimum. The charge pump alsopowers down. However,ittakeslongertorestartfromthismode. Powerdown mode has higher precedencethanstandbymode; settingthisbitalongwithbit4 forstandbymode sends theDAC into powerdown mode. Defaultvalue:0 0:Normal operation 1:Powerdown mode Page 0 /Register3 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 3 03 RSV RSV RSV RQML RSV RSV RSV RQMR ResetValue 0 0

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PCM5141,PCM5142 www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 RSV Reserved Reserved.Do notaccess. RQML Mute LeftChannel Thisbitissuessoftmute requestfortheleftchannel.The volume willbe smoothlyramped down orup toavoid pop orclicknoise. Defaultvalue:0 0:Normal volume 1:Mute RQMR Mute RightChannel Thisbitissuessoftmute requestfortherightchannel.The volume willbe smoothlyramped down orup to avoidpop orclicknoise. Defaultvalue:0 0:Normal volume 1:Mute Page 0 /Register4 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 4 04 RSV RSV RSV PLCK RSV RSV RSV PLLE ResetValue 1 RSV Reserved Reserved.Do notaccess. PLCK PLL Lock Flag(Read Only) ThisbitindicateswhetherthePLL islockedornot.When thePLL isdisabledthisbitalwaysshows thatthe PLL isnotlocked.0:The PLL islocked 1:The PLL isnotlocked PLLE PLL Enable ThisbitenablesordisablestheinternalPLL.When PLL isdisabled,themasterclockwillbe switchedtothe SCK. Defaultvalue:1 0:DisablePLL 1:EnablePLL Page 0 /Register6 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 6 06 RSV RSV RSV RSV RSV RSV FSMI1 FSMI0 ResetValue 0 0 RSV Reserved Reserved.Do notaccess. FSMI[1:0] SPI MISO functionsel These bitsselectthefunctionoftheSPI_MISO pinwhen inSPI mode. Ifthepinissetas GPIO, register readoutviaSPI isnotpossible. Defaultvalue:00 00:SPI_MISO 01:GPIO1 Others:Reserved(Do notset) Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 81 ProductFolderLinks:PCM5141 PCM5142

PCM5141,PCM5142 SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 www.ti.com Page 0 /Register7 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 7 07 RSV RSV RSV DEMP RSV RSV RSV SDSL ResetValue 0 0 RSV Reserved Reserved.Do notaccess. DEMP De-Emphasis Enable Thisbitenablesordisablesthede-emphasisfilter.The defaultcoefficientsarefor44.1kHzsamplingrate,but can be changed by reprogrammingtheappropriatecoeffientsinRAM. Defaultvalue:0 0:De-emphasisfilterisdisabled 1:De-emphasisfilterisenabled SDSL SDOUT Select Thisbitselectswhat isbeingoutputas SDOUT viaGPIO pins. Defaultvalue:0 0:SDOUT istheDSP output(post-processing) 1:SDOUT istheDSP input(pre-processing) Page 0 /Register8 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 8 08 RSV RSV G6OE G5OE G4OE G3OE G2OE G1OE ResetValue 0 0 0 0 0 0 RSV Reserved Reserved.Do notaccess. G6OE GPIO6 Output Enable ThisbitsetsthedirectionoftheGPIO6 pin Defaultvalue:0 0:GPIO6 isinput 1:GPIO6 isoutput G5OE GPIO5 Output Enable ThisbitsetsthedirectionoftheGPIO5 pin Defaultvalue:0 0:GPIO5 isinput 1:GPIO5 isoutput G4OE GPIO4 Output Enable ThisbitsetsthedirectionoftheGPIO4 pin Defaultvalue:0 0:GPIO4 isinput 1:GPIO4 isoutput G3OE GPIO3 Output Enable ThisbitsetsthedirectionoftheGPIO3 pin Defaultvalue:0 0:GPIO3 isinput 1:GPIO3 isoutput G2OE GPIO2 Output Enable ThisbitsetsthedirectionoftheGPIO2 pin Defaultvalue:0

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PCM5141,PCM5142 www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 0:GPIO2 isinput 1:GPIO2 isoutput G1OE GPIO1 Output Enable ThisbitsetsthedirectionoftheGPIO1 pin Defaultvalue:0 0:GPIO1 isinput 1:GPIO1 isoutput Page 0 /Register9 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 9 09 RSV RSV BCKP BCKO RSV RSV RSV LRKO ResetValue 0 0 0 RSV Reserved Reserved.Do notaccess. BCKP BCK Polarity ThisbitsetstheinvertedBCK mode. IninvertedBCK mode, theDAC assumes thattheLRCK and DIN edges arealignedtotherisingedge oftheBCK. Normallytheyareassumed tobe alignedtothefallingedge ofthe BCK. Defaultvalue:0 0:Normal BCK mode 1:InvertedBCK mode BCKO BCK Output Enable ThisbitsetstheBCK pindirectiontooutputforI2S mastermode operation.InI2S mastermode thePCM51xx outputsthereferenceBCK and LRCK, and theexternalsourcedeviceprovidestheDIN accordingtothese clocks.Use Page 0 /Register32 toprogramthedivisionfactoroftheSCK toyieldthedesiredBCK rate (normally64fS) Defaultvalue:0 0:BCK isinput(I2S slavemode) 1:BCK isoutput(I2S mastermode) LRKO LRCLK Output Enable ThisbitsetstheLRCK pindirectiontooutputforI2S mastermode operation.InI2S mastermode thePCM51xx outputsthereferenceBCK and LRCK, and theexternalsourcedeviceprovidestheDIN accordingtothese clocks.Use Page 0 /Register33 toprogramthedivisionfactoroftheBCK toyield1fS forLRCK. Defaultvalue:0 0:LRCK isinput(I2S slavemode) 1:LRCK isoutput(I2S mastermode) Page 0 /Register10 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 10 0A DSPG7 DSPG6 DSPG5 DSPG4 DSPG3 DSPG2 DSPG1 DSPG0 ResetValue 0 0 0 0 0 0 0 0 DSPG[7:0] DSP GPIO Input The DSP acceptsa 24-bitexternalcontrolsignalsinput.The valuesetinthisregisterwillgo tobit16:8ofthis externalinput. Defaultvalue:00000000 Page 0 /Register12 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 12 0C RSV RSV RSV RSV RSV RSV RBCK RLRK ResetValue 0 0 Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 83 ProductFolderLinks:PCM5141 PCM5142

PCM5141,PCM5142 SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 www.ti.com RSV Reserved Reserved.Do notaccess. RBCK Master Mode BCK DividerReset Thisbit,when setto0,willresettheSCK dividertogenerateBCK clockforI2S mastermode. To use I2S mastermode, thedividermust be enabledand programmed properly. Defaultvalue:0 0:Mastermode BCK clockdividerisreset 1:Mastermode BCK clockdividerisfunctional RLRK Master Mode LRCK DividerReset Thisbit,when setto0,willresettheBCK dividertogenerateLRCK clockforI2S mastermode. To use I2S mastermode, thedividermust be enabledand programmed properly. Defaultvalue:0 0:Mastermode LRCK clockdividerisreset 1:Mastermode LRCK clockdividerisfunctional Page 0 /Register13 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 13 0D RSV RSV RSV SREF RSV RSV RSV RSV ResetValue 0 RSV Reserved Reserved.Do notaccess. SREF PLL Reference ThisbitselectthesourceclockforinternalPLL.Thisbitisignoredand overrideninclockautosetmode. Defaultvalue:0 0:The PLL referenceclockisSCK 1:The PLL referenceclockisBCK Page 0 /Register20 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 20 14 RSV RSV RSV RSV PPDV3 PPDV2 PPDV1 PPDV0 ResetValue 0 0 0 0 RSV Reserved Reserved.Do notaccess. PPDV[3:0] PLL P These bitssetthePLL dividerP factor.These bitsareignoredinclockautosetmode. Defaultvalue:0000 0000:P=1 0001:P=2 ... 1110:P=15 1111:Prohibited(donotsetthisvalue) Page 0 /Register21 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 21 15 RSV RSV PJDV5 PJDV4 PJDV3 PJDV2 PJDV1 PJDV0 ResetValue 0 0 0 0 0 0

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PCM5141,PCM5142 www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 RSV Reserved Reserved.Do notaccess. PJDV[5:0] PLL J These bitssettheJ partoftheoverallPLL multiplicationfactorJ.D*R.These bitsareignoredinclockautoset mode. Defaultvalue:000000 000000:Prohibited(donotsetthisvalue) 000001:J=1 000010:J=2 ... 111111:J=63 Page 0 /Register22 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 22 16 RSV RSV PDDV13 PDDV12 PDDV11 PDDV10 PDDV9 PDDV8 ResetValue 0 0 0 0 0 0 Page 0 /Register23 23 17 PDDV7 PDDV6 PDDV5 PDDV4 PDDV3 PDDV2 PDDV1 PDDV0 ResetValue 0 0 0 0 0 0 0 0 RSV Reserved Reserved.Do notaccess. PDDV[13:0] PLL D (MSB) These bitssettheD partoftheoverallPLL multiplicationfactorJ.D*R.These bitsareignoredinclockautoset mode. Defaultvalue:00000000000000 0 (indecimal):D=0000 1 (indecimal):D=0001 ... 9999 (indecimal):D=9999 others:Prohibited(donotset) Page 0 /Register24 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 24 18 RSV RSV RSV RSV PRDV3 PRDV2 PRDV1 PRDV0 ResetValue 0 0 0 0 RSV Reserved Reserved.Do notaccess. PRDV[3:0] PLL R These bitssettheR partoftheoverallPLL multiplicationfactorJ.D*R. These bitsareignoredinclockauto setmode. Defaultvalue:0000 0000:R=1 0001:R=2 ... 1111:R=16 Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 85 ProductFolderLinks:PCM5141 PCM5142

PCM5141,PCM5142 SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 www.ti.com Page 0 /Register27 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 27 1B RSV DDSP6 DDSP5 DDSP4 DDSP3 DDSP2 DDSP1 DDSP0 ResetValue 0 0 0 0 0 0 0 RSV Reserved Reserved.Do notaccess. DDSP[6:0] DSP Clock Divider These bitssetthesourceclockdividervaluefortheDSP clock.These bitsareignoredinclockautosetmode. Defaultvalue:0000000 0000000:Divideby 1 0000001:Divideby 2 ... 1111111:Divideby 128 Page 0 /Register28 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 28 1C RSV DDAC6 DDAC5 DDAC4 DDAC3 DDAC2 DDAC1 DDAC0 ResetValue 0 0 0 0 0 0 0 RSV Reserved Reserved.Do notaccess. DDAC[6:0] DAC Clock Divider These bitssetthesourceclockdividervaluefortheDAC clock.These bitsareignoredinclockautosetmode. Defaultvalue:0000000 0000000:Divideby 1 0000001:Divideby 2 ... 1111111:Divideby 128 Page 0 /Register29 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 29 1D RSV DNCP6 DNCP5 DNCP4 DNCP3 DNCP2 DNCP1 DNCP0 ResetValue 0 0 0 0 0 0 0 RSV Reserved Reserved.Do notaccess. DNCP[6:0] NCP Clock Divider These bitssetthesourceclockdividervaluefortheCP clock.These bitsareignoredinclockautosetmode. Defaultvalue:0000000 0000000:Divideby 1 0000001:Divideby 2 ... 1111111:Divideby 128 Page 0 /Register30 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 30 1E RSV DOSR6 DOSR5 DOSR4 DOSR3 DOSR2 DOSR1 DOSR0 ResetValue 0 0 0 0 0 0 0

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PCM5141,PCM5142 www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 RSV Reserved Reserved.Do notaccess. DOSR[6:0] OSR Clock Divider These bitssetthesourceclockdividervaluefortheOSR clock.These bitsareignoredinclockautosetmode. Defaultvalue:0000000 0000000:Divideby 1 0000001:Divideby 2 ... 1111111:Divideby 128 Page 0 /Register32 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 32 20 RSV DBCK6 DBCK5 DBCK4 DBCK3 DBCK2 DBCK1 DBCK0 ResetValue 0 0 0 0 0 0 0 RSV Reserved Reserved.Do notaccess. DBCK[6:0] Master Mode BCK Divider These bitssettheSCK dividervaluetogenerateI2S masterBCK clock. Defaultvalue:0000000 0000000:Divideby 1 0000001:Divideby 2 ... 1111111:Divideby 128 Page 0 /Register33 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 33 21 DLRK7 DLRK6 DLRK5 DLRK4 DLRK3 DLRK2 DLRK1 DLRK0 ResetValue 0 0 0 0 0 0 0 0 DLRK[7:0] Master Mode LRCK Divider These bitssettheI2S masterBCK clockdividervaluetogenerateI2S masterLRCK clock. Defaultvalue:00000000 00000000:Divideby 1 00000001:Divideby 2 ... 11111111:Divideby 256 Page 0 /Register34 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 34 22 RSV RSV RSV I16E RSV RSV FSSP1 FSSP0 ResetValue 0 0 0 RSV Reserved Reserved.Do notaccess. I16E 16x Interpolation Thisbitenablesordisablesthe16x interpolationmode Defaultvalue:0 0:8x interpolation 1:16x interpolation Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 87 ProductFolderLinks:PCM5141 PCM5142

PCM5141,PCM5142 SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 www.ti.com FSSP[1:0] fS Speed Mode These bitsselectthefS operationmode, whichmust be setaccordingtothecurrentaudiosamplingrate.These bitsareignoredinclockautosetmode. Defaultvalue:00 00:Singlespeed (fS = 48 kHz) 01:Doublespeed (48kHz < fS = 96 kHz) 10:Quad speed (96kHz < fS = 192 kHz) 11:Octalspeed (192kHz < fS = 384 kHz) Page 0 /Register35 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 35 23 IDAC15 IDAC14 IDAC13 IDAC12 IDAC11 IDAC10 IDAC9 IDAC8 ResetValue 0 0 0 0 0 0 0 1 Page 0 /Register36 36 24 IDAC7 IDAC6 IDAC5 IDAC4 IDAC3 IDAC2 IDAC1 IDAC0 ResetValue 0 0 0 0 0 0 0 0 IDAC[15:0] IDAC (MSB) These bitsspecifythenumber ofDSP clockcyclesavailableinone audioframe.The valueshouldmatch the DSP clockfS ratio.These bitsareignoredinclockautosetmode. Defaultvalue:0000000100000000 Page 0 /Register37 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 37 25 RSV IDFS IDBK IDSK IDCH IDCM DCAS IPLK ResetValue 0 0 0 0 0 0 0 RSV Reserved Reserved.Do notaccess. IDFS IgnorefS Detection ThisbitcontrolswhethertoignorethefS detection.When ignored,fS errorwillnotcause a clockerror. Defaultvalue:0 0:Regard fS detection 1:IgnorefS detection IDBK IgnoreBCK Detection ThisbitcontrolswhethertoignoretheBCK detectionagainstLRCK. The BCK must be stablebetween 32fS and 256fS inclusiveoran errorwillbe reported.When ignored,a BCK errorwillnotcause a clockerror. Defaultvalue:0 0:Regard BCK detection 1:IgnoreBCK detection IDSK IgnoreSCK Detection ThisbitcontrolswhethertoignoretheSCK detectionagainstLRCK. Onlysome certainSCK ratioswithinsome errormarginareallowed.When ignored,an SCK errorwillnotcause a clockerror. Defaultvalue:0 0:Regard SCK detection 1:IgnoreSCK detection IDCH IgnoreClock HaltDetection ThisbitcontrolswhethertoignoretheSCK halt(staticorfrequencyislowerthanacceptable)detection.When ignoredan SCK haltwillnotcause a clockerror. Defaultvalue:0

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PCM5141,PCM5142 www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 0:Regard SCK haltdetection 1:IgnoreSCK haltdetection IDCM IgnoreLRCK or BCK MissingDetection ThisbitcontrolswhethertoignoretheLRCK orBCK missingdetection.The LRCK orBCK need tobe inlow state(notonlystatic)tobe deemed missing.When ignoredan LRCK orBCK missingwillnotcause theDAC go intopowerdown mode. Defaultvalue:0 0:Regard LRCK orBCK missingdetection 1:IgnoreLRCK orBCK missingdetection DCAS DisableClock DividerAutoset Thisbitenablesordisablestheclockautosetmode. When dealingwithuncommon audioclockconfiguration, theautosetmode must be disabledand allclockdividersmust be setmanually.Addtionally,some clock detectorsmightalsoneed tobe disabled.The clockautosetfeaturewillnotwork withPLL enabledinVCOM mode. Inthiscase thisfeaturehas tobe disabledand theclockdividersmust be setmanually. Defaultvalue:0 0:Enableclockautoset 1:Disableclockautoset IPLK IgnorePLL Lock Detection ThisbitcontrolswhethertoignorethePLL lockdetection.When ignored,PLL unlockswillnotcause a clock error.The PLL lockflagatPage 0 /Register4,bit4 isalwayscorrectregardlessofthisbit. Defaultvalue:0 0:PLL unlocksraiseclockerror 1:PLL unlocksareignored Page 0 /Register40 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 40 28 RSV RSV AFMT1 AFMT0 RSV RSV ALEN1 ALEN0 ResetValue 0 0 1 0 RSV Reserved Reserved.Do notaccess. AFMT[1:0] I2S Data Format These bitscontrolbothinputand outputaudiointerfaceformatsforDAC operation. Defaultvalue:00 00:I2S 01:DSP 10:RTJ 11:LTJ ALEN[1:0] I2S Word Length These bitscontrolbothinputand outputaudiointerfacesample word lengthsforDAC operation. Defaultvalue:10 00:16 bits 01:20 bits 10:24 bits 11:32 bits Page 0 /Register41 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 41 29 AOFS7 AOFS6 AOFS5 AOFS4 AOFS3 AOFS2 AOFS1 AOFS0 ResetValue 0 0 0 0 0 0 0 0 Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 89 ProductFolderLinks:PCM5141 PCM5142

PCM5141,PCM5142 SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 www.ti.com AOFS[7:0] I2S Shift These bitscontroltheoffsetofaudiodataintheaudioframeforbothinputand output.The offsetisdefinedas thenumber ofBCK fromthestarting(MSB) ofaudioframetothestartingofthedesiredaudiosample. Defaultvalue:00000000 00000000:offset= 0 BCK (nooffset) 00000001:ofsset= 1 BCK 00000010:offset= 2 BCKs 11111111:offset= 256 BCKs Page 0 /Register42 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 42 2A RSV RSV AUPL1 AUPL0 RSV RSV AUPR1 AUPR0 ResetValue 0 1 0 1 RSV Reserved Reserved.Do notaccess. AUPL[1:0] LeftDAC Data Path These bitscontroltheleftchannelaudiodatapathconnection. Defaultvalue:01 00:Zerodata(mute) 01:Leftchanneldata 10:Rightchanneldata 11:Reserved(donotset) AUPR[1:0] RightDAC Data Path These bitscontroltherightchannelaudiodatapathconnection. Defaultvalue:01 00:Zerodata(mute) 01:Rightchanneldata 10:Leftchanneldata 11:Reserved(donotset) Page 0 /Register43 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 43 2B RSV RSV RSV PSEL4 PSEL3 PSEL2 PSEL1 PSEL0 ResetValue 0 0 0 0 1 RSV Reserved Reserved.Do notaccess. PSEL[4:0] DSP Program Selection These bitsselecttheDSP programtouse foraudioprocessing. Defaultvalue:00001 00000:Reserved(donotset) 00001:8x/4x/2xFIR interpolationfilterwithde-emphasis 00010:8x/4x/2xLow latencyIIRinterpolationfilterwithde-emphasis 00011:Highattenuationx8/x4/x2interpolationfilterwithde-emphasis 00100:Reserved 00101:Fixedprocessflowwithconfigurableparameters 00110:Reserved(donotset) 00111:8x Ringing-lesslowlatencyFIR interpolationfilterwithoutde-emphasis 11111:User programinRAM

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PCM5141,PCM5142 www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 others:Reserved(donotset) Page 0 /Register44 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 44 2C RSV RSV RSV RSV RSV CMDP2 CMDP1 CMDP0 ResetValue 0 0 0 RSV Reserved Reserved.Do notaccess. CMDP[2:0] Clock MissingDetectionPeriod These bitssethow longbothBCK and LRCK keep lowbeforetheaudioclocksdeemed missingand theDAC transitionstopowerdown mode. Defaultvalue:000 000:about1 second 001:about2 seconds 010:about3 seconds ... 111:about8 seconds Page 0 /Register59 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 59 3B RSV AMTL2 AMTL1 AMTL0 RSV AMTR2 AMTR1 AMTR0 ResetValue 0 0 0 0 0 0 RSV Reserved Reserved.Do notaccess. AMTL[2:0] Auto Mute Time forLeftChannel These bitsspecifythelengthofconsecutivezerosamplesatleftchannelbeforethechannelcan be auto muted.The timesshown arefor48 kHz samplingrateand willscalewithotherrates. Defaultvalue:000 000:21 ms 001:106 ms 010:213 ms 011:533 ms 100:1.07sec 101:2.13sec 110:5.33sec 111:10.66sec AMTR[2:0] Auto Mute Time forRightChannel These bitsspecifythelengthofconsecutivezerosamplesatrightchannelbeforethechannelcan be auto muted.The timesshown arefor48 kHz samplingrateand willscalewithotherrates. Defaultvalue:000 000:21 ms 001:106 ms 010:213 ms 011:533 ms 100:1.07sec 101:2.13sec 110:5.33sec 111:10.66sec Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 91 ProductFolderLinks:PCM5141 PCM5142

PCM5141,PCM5142 SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 www.ti.com Page 0 /Register60 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 60 3C RSV RSV RSV RSV RSV RSV PCTL1 PCTL0 ResetValue 0 0 RSV Reserved Reserved.Do notaccess. PCTL[1:0] DigitalVolume Control These bitscontrolthebehaviorofthedigitalvolume. Defaultvalue:00 00:The volume forLeftand rightchannelsareindependent 01:Rightchannelvolume followsleftchannelsetting 10:Leftchannelvolume followsrightchannelsetting 11:Reserved(Thevolume forLeftand rightchannelsareindependent) Page 0 /Register61 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 61 3D VOLL7 VOLL6 VOLL5 VOLL4 VOLL3 VOLL2 VOLL1 VOLL0 ResetValue 0 0 1 1 0 0 0 0 VOLL[7:0] LeftDigitalVolume These bitscontroltheleftchanneldigitalvolume.The digitalvolume is24 dB to-103dB in-0.5dB step. Defaultvalue:00110000 00000000:+24.0dB 00000001:+23.5dB 00101111:+0.5dB 00110000:0.0dB 00110001:-0.5dB ... 11111110:-103dB 11111111:Mute Page 0 /Register62 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 62 3E VOLR7 VOLR6 VOLR5 VOLR4 VOLR3 VOLR2 VOLR1 VOLR0 ResetValue 0 0 1 1 0 0 0 0 VOLR[7:0] RightDigitalVolume These bitscontroltherightchanneldigitalvolume.The digitalvolume is24 dB to-103dB in-0.5dB step. Defaultvalue:00110000 00000000:+24.0dB 00000001:+23.5dB 00101111:+0.5dB 00110000:0.0dB 00110001:-0.5dB ... 11111110:-103dB 11111111:Mute

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PCM5141,PCM5142 www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 Page 0 /Register63 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 63 3F VNDF1 VNDF0 VNDS1 VNDS0 VNUF1 VNUF0 VNUS1 VNUS0 ResetValue 0 0 1 0 0 0 1 0 VNDF[1:0] DigitalVolume Normal Ramp Down Frequency These bitscontrolthefrequencyofthedigitalvolume updateswhen thevolume isrampingdown.The setting hereisappliedtosoftmute request,assertedby XSMUTE pinorPage 0 /Register3. Defaultvalue:00 00:Update every1 sample period 01:Update every2 sample periods 10:Update every4 sample periods 11:Directlysetthevolume tozero(Instantmute) VNDS[1:0] DigitalVolume Normal Ramp Down Step These bitscontrolthestepofthedigitalvolume updateswhen thevolume isrampingdown.The settinghereis appliedtosoftmute request,assertedby XSMUTE pinorPage 0 /Register3. Defaultvalue:10 00:Decrement by 4 dB foreach update 01:Decrement by 2 dB foreach update 10:Decrement by 1 dB foreach update 11:Decrement by 0.5dB foreach update VNUF[1:0] DigitalVolume Normal Ramp Up Frequency These bitscontrolthefrequencyofthedigitalvolume updateswhen thevolume isrampingup.Thesettinghere isappliedtosoftunmute request,assertedby XSMUTE pinorPage 0 /Register3. Defaultvalue:00 00:Update every1 sample period 01:Update every2 sample periods 10:Update every4 sample periods 11:Directlyrestorethevolume (Instantunmute) VNUS[1:0] DigitalVolume Normal Ramp Up Step These bitscontrolthestepofthedigitalvolume updateswhen thevolume isrampingup.Thesettinghereis appliedtosoftunmute request,assertedby XSMUTE pinorPage 0 /Register3. Defaultvalue:10 00:Incrementby 4 dB foreach update 01:Incrementby 2 dB foreach update 10:Incrementby 1 dB foreach update 11:Incrementby 0.5dB foreach update Page 0 /Register64 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 64 40 VEDF1 VEDF0 VEDS1 VEDS0 RSV RSV RSV RSV ResetValue 0 0 0 0 RSV Reserved Reserved.Do notaccess. VEDF[1:0] DigitalVolume Emergency Ramp Down Frequency These bitscontrolthefrequencyofthedigitalvolume updateswhen thevolume isrampingdown due toclock errororpower outage,whichusuallyneeds fasterramp down compared tonormalsoftmute. Defaultvalue:00 00:Update every1 sample period 01:Update every2 sample periods Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 93 ProductFolderLinks:PCM5141 PCM5142

PCM5141,PCM5142 SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 www.ti.com 10:Update every4 sample periods 11:Directlysetthevolume tozero(Instantmute) VEDS[1:0] DigitalVolume Emergency Ramp Down Step These bitscontrolthestepofthedigitalvolume updateswhen thevolume isrampingdown due toclockerror orpower outage,whichusuallyneeds fasterramp down compared tonormalsoftmute. Defaultvalue:00 00:Decrement by 4 dB foreach update 01:Decrement by 2 dB foreach update 10:Decrement by 1 dB foreach update 11:Decrement by 0.5dB foreach update Page 0 /Register65 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 65 41 RSV RSV RSV RSV RSV ACTL AMLE AMRE ResetValue 1 1 1 RSV Reserved Reserved.Do notaccess. ACTL Auto Mute Control Thisbitcontrolsthebehavioroftheautomute upon zerosample detection.The timelengthforzerodetection issetwithPage 0 /Register59. Defaultvalue:1 0:Automute leftchanneland rightchannelindependently. 1:Automute leftand rightchannelsonlywhen bothchannelsareabouttobe automuted. AMLE Auto Mute LeftChannel Thisbitenablesordisablesautomute on rightchannel.Note thatwhen rightchannelautomute isdisabledand thePage 0 /Register65,bit2 issetto1,theleftchannelwillalsoneverbe automuted. Defaultvalue:1 0:Disablerightchannelautomute 1:Enablerightchannelautomute AMRE Auto Mute RightChannel Thisbitenablesordisablesautomute on leftchannel.Note thatwhen leftchannelautomute isdisabledand thePage 0 /Register65,bit2 issetto1,therightchannelwillalsoneverbe automuted. Defaultvalue:1 0:Disableleftchannelautomute 1:Enableleftchannelautomute Page 0 /Register80 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 80 50 RSV RSV RSV RSV G1SL3 G1SL2 G1SL1 G1SL0 ResetValue 0 0 0 0 RSV Reserved Reserved.Do notaccess. G1SL[3:0] GPIO1 Output Selection These bitsselectthesignaltooutputtoGPIO1. To actuallyoutputtheselectedsignal,theGPIO1 must be set tooutputmode atPage 0 /Register8. Defaultvalue:0000 0000:off(low) 0001:DSP GPIO1 output 0010:RegisterGPIO1 output(Page 0 /Register86,bit0)

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PCM5141,PCM5142 www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 0011:Automute flag(assertedwhen bothL and R channelsareautomuted) 0100:Automute flagforleftchannel 0101:Automute flagforrightchannel 0110:Clockinvalidflag(clockerrororclockchangingorclockmissing) 0111:Serialaudiointerfacedataoutput(SDOUT) 1000:Analogmute flagforleftchannel(lowactive) 1001:Analogmute flagforrightchannel(lowactive) 1010:PLL lockflag 1011:Charge pump clock 1100:Reserved 1101:Reserved 1110:Under voltageflag,assertedwhen XSMUTE voltageishigherthan0.7DVDD 1111:Under voltageflag,assertedwhen XSMUTE voltageishigherthan0.3DVDD Page 0 /Register81 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 81 51 RSV RSV RSV RSV G2SL3 G2SL2 G2SL1 G2SL0 ResetValue 0 0 0 0 RSV Reserved Reserved.Do notaccess. G2SL[3:0] GPIO2 Output Selection These bitsselectthesignaltooutputtoGPIO2. To actuallyoutputtheselectedsignal,theGPIO2 must be set tooutputmode atPage 0 /Register8. Defaultvalue:0000 0000:off(low) 0001:DSP GPIO2 output 0010:RegisterGPIO2 output(Page 0 /Register86,bit1) 0011:Automute flag(assertedwhen bothL and R channelsareautomuted) 0100:Automute flagforleftchannel 0101:Automute flagforrightchannel 0110:Clockinvalidflag(clockerrororclockchangingorclockmissing) 0111:Serialaudiointerfacedataoutput(SDOUT) 1000:Analogmute flagforleftchannel(lowactive) 1001:Analogmute flagforrightchannel(lowactive) 1010:PLL lockflag 1011:Charge pump clock 1100:Reserved 1101:Reserved 1110:Under voltageflag,assertedwhen XSMUTE voltageishigherthan0.7DVDD 1111:Under voltageflag,assertedwhen XSMUTE voltageishigherthan0.3DVDD Page 0 /Register82 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 82 52 RSV RSV RSV RSV G3SL3 G3SL2 G3SL1 G3SL0 ResetValue 0 0 0 0 Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 95 ProductFolderLinks:PCM5141 PCM5142

PCM5141,PCM5142 SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 www.ti.com RSV Reserved Reserved.Do notaccess. G3SL[3:0] GPIO3 Output Selection These bitsselectthesignaltooutputtoGPIO3. To actuallyoutputtheselectedsignal,theGPIO3 must be set tooutputmode atPage 0 /Register8. Defaultvalue:0000 0000:off(low) 0001:DSP GPIO3 output 0010:RegisterGPIO3 output(Page 0 /Register86,bit2) 0011:Automute flag(assertedwhen bothL and R channelsareautomuted) 0100:Automute flagforleftchannel 0101:Automute flagforrightchannel 0110:Clockinvalidflag(clockerrororclockchangingorclockmissing) 0111:Serialaudiointerfacedataoutput(SDOUT) 1000:Analogmute flagforleftchannel(lowactive) 1001:Analogmute flagforrightchannel(lowactive) 1010:PLL lockflag 1011:Charge pump clock 1100:Reserved 1101:Reserved 1110:Under voltageflag,assertedwhen XSMUTE voltageishigherthan0.7DVDD 1111:Under voltageflag,assertedwhen XSMUTE voltageishigherthan0.3DVDD Page 0 /Register83 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 83 53 RSV RSV RSV RSV G4SL3 G4SL2 G4SL1 G4SL0 ResetValue 0 0 0 0 RSV Reserved Reserved.Do notaccess. G4SL[3:0] GPIO4 Output Selection These bitsselectthesignaltooutputtoGPIO4. To actuallyoutputtheselectedsignal,theGPIO4 must be set tooutputmode atPage 0 /Register8. Defaultvalue:0000 0000:off(low) 0001:DSP GPIO4 output 0010:RegisterGPIO4 output(Page 0 /Register86,bit3) 0011:Automute flag(assertedwhen bothL and R channelsareautomuted) 0100:Automute flagforleftchannel 0101:Automute flagforrightchannel 0110:Clockinvalidflag(clockerrororclockchangingorclockmissing) 0111:Serialaudiointerfacedataoutput(SDOUT) 1000:Analogmute flagforleftchannel(lowactive) 1001:Analogmute flagforrightchannel(lowactive) 1010:PLL lockflag 1011:Charge pump clock 1100:Reserved 1101:Reserved 1110:Under voltageflag,assertedwhen XSMUTE voltageishigherthan0.7DVDD 1111:Under voltageflag,assertedwhen XSMUTE voltageishigherthan0.3DVDD

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PCM5141,PCM5142 www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 Page 0 /Register84 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 84 54 RSV RSV RSV RSV G5SL3 G5SL2 G5SL1 G5SL0 ResetValue 0 0 0 0 RSV Reserved Reserved.Do notaccess. G5SL[3:0] GPIO5 Output Selection These bitsselectthesignaltooutputtoGPIO5. To actuallyoutputtheselectedsignal,theGPIO5 must be set tooutputmode atPage 0 /Register8. Defaultvalue:0000 0000:off(low) 0001:DSP GPIO5 output 0010:RegisterGPIO5 output(Page 0 /Register86,bit4) 0011:Automute flag(assertedwhen bothL and R channelsareautomuted) 0100:Automute flagforleftchannel 0101:Automute flagforrightchannel 0110:Clockinvalidflag(clockerrororclockchangingorclockmissing) 0111:Serialaudiointerfacedataoutput(SDOUT) 1000:Analogmute flagforleftchannel(lowactive) 1001:Analogmute flagforrightchannel(lowactive) 1010:PLL lockflag 1011:Charge pump clock 1100:Reserved 1101:Reserved 1110:Under voltageflag,assertedwhen XSMUTE voltageishigherthan0.7DVDD 1111:Under voltageflag,assertedwhen XSMUTE voltageishigherthan0.3DVDD Page 0 /Register85 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 85 55 RSV RSV RSV RSV G6SL3 G6SL2 G6SL1 G6SL0 ResetValue 0 0 0 0 RSV Reserved Reserved.Do notaccess. G6SL[3:0] GPIO6 Output Selection These bitsselectthesignaltooutputtoGPIO6. To actuallyoutputtheselectedsignal,theGPIO6 must be set tooutputmode atPage 0 /Register8. Defaultvalue:0000 0000:off(low) 0001:DSP GPIO6 output 0010:RegisterGPIO6 output(Page 0 /Register86,bit5) 0011:Automute flag(assertedwhen bothL and R channelsareautomuted) 0100:Automute flagforleftchannel 0101:Automute flagforrightchannel 0110:Clockinvalidflag(clockerrororclockchangingorclockmissing) 0111:Serialaudiointerfacedataoutput(SDOUT) 1000:Analogmute flagforleftchannel(lowactive) 1001:Analogmute flagforrightchannel(lowactive) 1010:PLL lockflag Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 97 ProductFolderLinks:PCM5141 PCM5142

PCM5141,PCM5142 SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 www.ti.com 1011:Charge pump clock 1100:Reserved 1101:Reserved 1110:Under voltageflag,assertedwhen XSMUTE voltageishigherthan0.7DVDD 1111:Under voltageflag,assertedwhen XSMUTE voltageishigherthan0.3DVDD Page 0 /Register86 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 86 56 RSV RSV GOUT5 GOUT4 GOUT3 GOUT2 GOUT1 GOUT0 ResetValue 0 0 0 0 0 0 RSV Reserved Reserved.Do notaccess. GOUT[5:0] GPIO Output Control ThisbitcontrolstheGPIO6 outputwhen theselectionatPage 0 /Register85 issetto0010 (registeroutput) Defaultvalue:000000 0:Outputlow 1:Outputhigh Page 0 /Register87 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 87 57 RSV RSV GINV5 GINV4 GINV3 GINV2 GINV1 GINV0 ResetValue 0 0 0 0 0 0 RSV Reserved Reserved.Do notaccess. GINV[5:0] GPIO Output Inversion ThisbitcontrolsthepolarityofGPIO6 output.When setto1,theoutputwillbe invertedforany signalbeing selected. Defaultvalue:000000 0:Non-inverted 1:Inverted Page 0 /Register90 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 90 5A RSV RSV RSV L1OV R1OV L2OV R2OV SFOV ResetValue RSV Reserved Reserved.Do notaccess. L1OV Left1Overflow(Read Only) ThisbitindicateswhethertheleftchannelofDSP firstoutputporthas overflow.Thisbitisstickyand iscleared when read.0:No overflow 1:Overflowoccurred R1OV Right1Overflow(Read Only) The bitindicateswhethertherightchannelofDSP firstoutputporthas overflow.Thisbitisstickyand iscleared when read.0:No overflow 1:Overflowoccurred L2OV Left2Overflow(Read Only) ThisbitindicateswhethertheleftchannelofDSP second outputporthas overflow.Thisbitisstickyand is clearedwhen read.0:No overflow

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PCM5141,PCM5142 www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 1:Overflowoccurred R2OV Right2Overflow(Read Only) The bitindicateswhethertherightchannelofDSP second outputporthas overflow.Thisbitisstickyand is clearedwhen read.0:No overflow 1:Overflowoccurred SFOV ShifterOverflow(Read Only) ThisbitindicateswhetheroverflowoccurredintheDSP shifter(possiblesample corruption).Thisbitissticky and isclearedwhen read.0:No overflow 1:Overflowoccurred Page 0 /Register91 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 91 5B RSV DTFS2 DTFS1 DTFS0 DTSR3 DTSR2 DTSR1 DTSR0 ResetValue RSV Reserved Reserved.Do notaccess. DTFS[2:0] DetectedfS (Read Only) These bitsindicatethecurrentlydetectedaudiosamplingrate.000:Error(Outofvalidrange) 001:8 kHz 010:16 kHz 011:32-48kHz 100:88.2-96kHz 101:176.4-192kHz 110:384 kHz DTSR[3:0] DetectedSCK Ratio(Read Only) These bitsindicatethecurrentlydetectedSCK ratio.Note thateven iftheSCK ratioisnotindicatedas error, clockerrormightstillbe flaggeddue toincompatiblecombinationwiththesamplingrate.SpecificallytheSCK ratiomust be highenough toallowenough DSP cyclesforminimalaudioprocessingwhen PLL isdisabled.The absoluteSCK frequencymust alsobe lowerthan50 MHz. 0000:Ratioerror(TheSCK ratioisnotallowed) 0001:SCK = 32fS 0010:SCK = 48fS 0011:SCK = 64fS 0100:SCK = 128fS 0101:SCK = 192fS 0110:SCK = 256fS 0111:SCK = 384fS 1000:SCK = 512fS 1001:SCK = 768fS 1010:SCK = 1024fS 1011:SCK = 1152fS 1100:SCK = 1536fS 1101:SCK = 2048fS 1110:SCK = 3072fS Page 0 /Register92 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 92 5C RSV RSV RSV RSV RSV RSV RSV DTBR8 ResetValue Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 99 ProductFolderLinks:PCM5141 PCM5142

PCM5141,PCM5142 SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 www.ti.com Page 0 /Register93 93 5D DTBR7 DTBR6 DTBR5 DTBR4 DTBR3 DTBR2 DTBR1 DTBR0 ResetValue RSV Reserved Reserved.Do notaccess. DTBR[8:0] DetectedBCK Ratio(MSB) (Read Only) These bitsindicatethecurrentlydetectedBCK ratio,thatis,thenumber ofBCK clocksinone audioframe. Note thatfortheextremecase ofBCK = 1 fS (nota usablescenario),thedetectedratiowillbe unreliable. Page 0 /Register94 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 94 5E RSV CDST6 CDST5 CDST4 CDST3 CDST2 CDST1 CDST0 ResetValue RSV Reserved Reserved.Do notaccess. CDST[6:0] Clock DetectorStatus(Read Only) ThisbitindicateswhethertheSCK clockispresentornot.0:SCK ispresent 1:SCK ismissing(halted) Page 0 /Register108 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 108 6C RSV RSV RSV RSV RSV RSV AMLM AMRM ResetValue RSV Reserved Reserved.Do notaccess. AMLM LeftAnalog Mute Monitor(Read Only) Thisbitisa monitorforleftchannelanalogmute status.0:Mute 1:Unmute AMRM RightAnalog Mute Monitor(Read Only) Thisbitisa monitorforrightchannelanalogmute status.0:Mute 1:Unmute Page 0 /Register119 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 119 77 RSV RSV GPIN5 GPIN4 GPIN3 GPIN2 GPIN1 RSV ResetValue RSV Reserved Reserved.Do notaccess. GPIN[5:0] GPIO InputStates(Read Only) ThisbitindicatesthelogiclevelatGPIO6 pin.0:Low 1:High Page 0 /Register120 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 120 78 RSV RSV RSV AMFL RSV RSV RSV AMFR ResetValue

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PCM5141,PCM5142 www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 RSV Reserved Reserved.Do notaccess. AMFL Auto Mute FlagforLeftChannel (Read Only) Thisbitindicatestheautomute statusforleftchannel.0:Not automuted 1:Automuted AMFR Auto Mute FlagforRightChannel (Read Only) Thisbitindicatestheautomute statusforrightchannel.0:Not automuted 1:Automuted Page 1 /Register1 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 1 01 RSV RSV RSV RSV RSV RSV RSV OSEL ResetValue 0 RSV Reserved Reserved.Do notaccess. OSEL Output Amplitude Type Thisbitselectstheoutputamplitudetype.The clockautosetfeaturewillnotwork withPLL enabledinVCOM mode. Inthiscase thisfeaturehas tobe disabledviaPage 0 /Register37 and theclockdividersmust be set manually. Defaultvalue:0 0:VREF mode (ConstantoutputamplitudeagainstAVDD variation) 1:VCOM mode (OutputamplitudeisproportionaltoAVDD variation) Page 1 /Register2 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 2 02 RSV RSV RSV LAGN RSV RSV RSV RAGN ResetValue 0 0 RSV Reserved Reserved.Do notaccess. LAGN Analog Gain ControlforLeftChannel Thisbitcontrolstheleftchannelanaloggain. Defaultvalue:0 0:0 dB 1:-6dB RAGN Analog Gain ControlforRightChannel Thisbitcontrolstherightchannelanaloggain. Defaultvalue:0 0:0 dB 1:-6dB Page 1 /Register5 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 5 05 RSV RSV RSV RSV RSV RSV UEPD UIPD ResetValue 0 0 Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 101 ProductFolderLinks:PCM5141 PCM5142

PCM5141,PCM5142 SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 www.ti.com RSV Reserved Reserved.Do notaccess. UEPD ExternalUVP Control Thisbitenablesordisablesdetectionofpower supplydropviaXSMUTE pin(ExternalUnder Voltage Protection). Defaultvalue:0 0:Enabled 1:Disabled UIPD InternalUVP Control ThisbitenablesordisablesinternaldetectionofAVDD voltagedrop(InternalUnder VoltageProtection). Defaultvalue:0 0:Enabled 1:Disabled Page 1 /Register6 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 6 06 RSV RSV RSV RSV RSV RSV RSV AMCT ResetValue 0 RSV Reserved Reserved.Do notaccess. AMCT Analog Mute Control Thisbitenablesordisablesanalogmute followingdigitalmute. Defaultvalue:0 0:Enabled 1:Disabled Page 1 /Register7 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 7 07 RSV RSV RSV AGBL RSV RSV RSV AGBR ResetValue 0 0 RSV Reserved Reserved.Do notaccess. AGBL Analog +10% Gain forLeftChannel Thisbitenablesordisablesamplitudeboostmode forleftchannel. Defaultvalue:0 0:Normal amplitude 1:+10% (+0.8dB) boostedamplitude AGBR Analog +10% Gain forRightChannel Thisbitenablesordisablesamplitudeboostmode forrightchannel. Defaultvalue:0 0:Normal amplitude 1:+10% (+0.8dB) boostedamplitude Page 1 /Register8 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 8 08 RSV RSV RSV RSV RSV RSV RSV RCMF ResetValue 0

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PCM5141,PCM5142 www.ti.com SLAS759A –AUGUST 2012–REVISED SEPTEMBER 2012 RSV Reserved Reserved.Do notaccess. RCMF VCOM ReferenceRamp Up ThisbitcontrolstheVCOM voltageramp up speed. Defaultvalue:0 0:Normal ramp up,~600ms withexternalcapacitance= 1uF 1:Fastramp up,~3ms withexternalcapacitance= 1uF Page 1 /Register9 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 9 09 RSV RSV RSV RSV RSV RSV RSV VCPD ResetValue 1 RSV Reserved Reserved.Do notaccess. VCPD Power down controlforVCOM ThisbitcontrolsVCOM powerdown switch. Defaultvalue:1 0:VCOM ispowered on 1:VCOM ispowered down Page 44 /Register1 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 1 01 RSV RSV RSV RSV ACRM AMDC ACRS ACSW ResetValue 0 0 RSV Reserved Reserved.Do notaccess. ACRM ActiveCRAM Monitor(Read Only) ThisbitindicateswhichCRAM isbeingaccessedby theDSP when adaptivemode isdisabled.When adaptive mode isenabled,thisbithas no meaning.0:CRAM A isbeingused by theDSP 1:CRAM B isbeingused by theDSP AMDC AdaptiveMode Control ThisbitcontrolstheDSP adaptivemode. When inadaptivemode, onlyCRAM A isaccessibleviaserial interfacewhen theDSP isdisabled(DAC instandbystate),whilewhen theDSP isenabled(DAC isrunstate) theCRAM A can onlybe accessedby theDSP and theCRAM B can onlybe accessedby theserialinterface, orviceversadependingon thevalueofCRAMSTAT. When notinadaptivemode, bothCRAM A and B can be accessedby theserialinterfacewhen theDSP isdisabled,butwhen theDSP isenabled,no CRAM can be accessedby serialinterface.The DSP can accesseitherCRAM, whichcan be monitoredatSWPMON. Defaultvalue:0 0:Adaptivemode disabled 1:Adaptivemode enabled ACRS ActiveCRAM Selection(Read Only) ThisbitindicateswhichCRAM currentlyservesas theactiveone.The otherCRAM servesas an updatebuffer, and can accessedby serialinterface(SPIorI2C)0:CRAM A isactiveand beingused by theDSP 1:CRAM B isactiveand beingused by theDSP ACSW Switch ActiveCRAM Thisbitisa role-switchrequestbetween thetwo buffers,switchingtheactivebufferrolebetween CRAM A and CRAM B.Thisbitclearsautomaticallywhen theswitchingprocesscompleted. Defaultvalue:0 0:No switchingrequestedorswitchingcompleted 1:Switchingisbeingrequested Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 103 ProductFolderLinks:PCM5141 PCM5142

www.ti.com 10-Dec-2012 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Samples (Requires Login) PCM5141PW ACTIVE TSSOP PW 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCM5141PWR ACTIVE TSSOP PW 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCM5142PW ACTIVE TSSOP PW 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCM5142PWR ACTIVE TSSOP PW 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2012 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCM5141PWR TSSOP PW 28 2000 367.0 367.0 38.0 PCM5142PWR TSSOP PW 28 2000 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2012 Pack Materials-Page 2

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