PCM5100A TI | Alldatasheet
Document overview
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Technical content
- Integrated High-Performance Audio PLL with BCK blocking capacitors on the output, as well as external Reference to Generate SCK Internally muting circuits traditionally associated with single- supply line drivers.• Direct Line Level 2.1-VRMS Output
- No DC Blocking Capacitors Required The integrated line driver surpasses all other charge- pump based line drivers by supporting loads down to• Line Level Output Down to 1KΩ 1 kΩ per pin.• Intelligent Muting System; Soft Up or Down Ramp The integrated PLL on the device removes theand Analog Mute For 120-dB Mute SNR requirement for a system clock (commonly known as• Accepts 16-, 24-, and 32-Bit Audio Data master clock), allowing a 3-wire I2S connection and• PCM Data Formats: I2S, Left-Justified reducing system EMI.
- Automatic Power-Save Mode When LRCK And Intelligent clock error and PowerSense undervoltageBCK Are Deactivated protection utilizes a two-level mute system for pop-
- 1.8 V or 3.3 V Failsafe LVCMOS Digital Inputs free performance.
- Simple Configuration Using Hardware Pins Compared with many conventional switched capacitor
- Single-Supply Operation: 14 DAC architectures, the PCM510xA family offers up to 20 dB lower out-of-band noise, reducing EMI and– 3.3 V Analog, 1.8 V or 3.3 V Digital aliasing in downstream amplifiers/ADCs, measured• Qualified in Accordance with AEC-Q100 from the traditional 100-kHz OBN measurements to 3 MHz).2 Applications
Table 1. Device Information(1)
- A/V Receivers, DVD, BD Players PART NUMBER PACKAGE BODY SIZE (NOM)• Automotive Infotainment and Telematics PCM5102A• HDTV Receivers PCM5101A TSSOP (20) 5.50 mm × 4.40 mm• Aftermarket Automotive Amplifiers PCM5100A
3 Description (1) For all available packages, see the orderable addendum at
performance and improved tolerance to clock jitter.
4 Simplified System Diagram
intellectual property matters and other important disclaimers. PRODUCTION DATA.
PCM5100A,PCM5101A,PCM5102A PCM5100A-Q1,PCM5101A-Q1,PCM5102A-Q1 SLAS859C –MAY 2012–REVISED MAY 2015 www.ti.com Table of Contents
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (January 2015) to Revision C Page
- Changed the stereo line output load resistance MIN value in the Recommended Operating Conditions from "2 kΩ"
- Changed the operating junction temperature range in the Recommended Operating Conditions from "MIN = –25°C Changes from Revision A (September 2012) to Revision B Page
- Added ESD Rating table, Detailed Description section, Application and Implementation section, Power Supply Recommendations section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable
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Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1
PCM5100A,PCM5101A,PCM5102A PCM5100A-Q1,PCM5101A-Q1,PCM5102A-Q1 www.ti.com SLAS859C –MAY 2012–REVISED MAY 2015 Changes from Original (May 2012) to Revision A Page
- Changed "VOUT = –1 dB" to "THD+N at –1 dBFS" in in the Dymamic Performance section of the Electrical Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1
PCM5100A,PCM5101A,PCM5102A PCM5100A-Q1,PCM5101A-Q1,PCM5102A-Q1 SLAS859C –MAY 2012–REVISED MAY 2015 www.ti.com
6 Device Comparison
Differences Between PCM510xA Devices PART NUMBER DYNAMIC RANGE SNR THD PCM5102A 112dB 112dB –93 dB PCM5101A 106 dB 106 dB –92 dB PCM5100A 100 dB 100 dB –90 dB Typical Performance (3.3 V Power Supply) PARAMETER PCM5102 / PCM5101 / PCM5100 SNR 112 / 106 / 100 dB Dynamic range 112 /106 / 100 dB THD+N at –1 dBFS –93/ –92 / –90 dB Full-scale single-ended output 2.1 VRMS (GND center) Normal 8× oversampling digital filter latency 20tS Low latency 8× oversampling digital filter latency 3.5tS Sampling frequency 8 kHz to 384 kHz System clock multiples (fSCK): 64, 128, 192, 256, 384, Up to 50 MHz 512, 768, 1024, 1152, 1536, 2048, 3072
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Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1
PCM5100A,PCM5101A,PCM5102A PCM5100A-Q1,PCM5101A-Q1,PCM5102A-Q1 www.ti.com SLAS859C –MAY 2012–REVISED MAY 2015
7 Pin Configuration and Functions
(Top View) Pin Functions PIN TYPE DESCRIPTION NAME NO. AGND 9 — Analog ground AVDD 8 P Analog power supply, 3.3 V BCK 13 I Audio data bit clock input(1) CAPM 4 O Charge pump flying capacitor terminal for negative rail CAPP 2 O Charge pump flying capacitor terminal for positive rail CPGND 3 — Charge pump ground CPVDD 1 P Charge pump power supply, 3.3 V DEMP 10 I De-emphasis control for 44.1-kHz sampling rate(1): Off (Low) / On (High) DGND 19 — Digital ground DIN 14 I Audio data input(1) DVDD 20 P Digital power supply, 1.8 V or 3.3 V FLT 11 I Filter select : Normal latency (Low) / Low latency (High) FMT 16 I Audio format selection : I2S (Low) / Left-justified (High) LDOO 18 P Internal logic supply rail terminal for decoupling, or external 1.8 V supply terminal LRCK 15 I Audio data word clock input(1) OUTL 6 O Analog output from DAC left channel OUTR 7 O Analog output from DAC right channel SCK 12 I System clock input(1) VNEG 5 O Negative charge pump rail terminal for decoupling, –3.3 V XSMT 17 I Soft mute control(1): Soft mute (Low) / soft un-mute (High) (1) Failsafe LVCMOS Schmitt trigger input Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1
PCM5100A,PCM5101A,PCM5102A PCM5100A-Q1,PCM5101A-Q1,PCM5102A-Q1 SLAS859C –MAY 2012–REVISED MAY 2015 www.ti.com
8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT AVDD, CPVDD, DVDD –0.3 3.9 Supply voltage LDO with DVDD at 1.8 V –0.3 2.25 DVDD at 1.8 V –0.3 2.25 V Digital input voltage DVDD at 3.3 V –0.3 3.9 Analog input voltage –0.3 3.9 Operating junction temperature range –40 130 °C Storage temperature, Tstg –65 150 °C
8.2 ESD Ratings
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V(ESD) Electrostatic discharge VCharged-device model (CDM), per JEDEC specification JESD22- ±750C101(2) (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
VCOM mode 3 3.3 3.46Referenced toAVDD Analog power supply voltage range VAGND(1) VREF mode 3.2 3.3 3.46 1.8 V DVDD 1.65 1.8 1.95Referenced toDVDD Digital power supply voltage range VDGND(1) 3.3 V DVDD 3.1 3.3 3.46 CPVDD Charge pump supply voltage range Referenced to CPGND(1) 3.1 3.3 3.46 V MCLK Master clock frequency 50 MHz LOL, LOR Stereo line output load resistance 1 10 kΩ CLOUT Digital output load capacitance 10 pF TJ Operating junction temperature range –40 130 °C (1) All grounds on board are tied together; they must not differ in voltage by more than 0.2 V max, for any combination of ground signals.
8.4 Thermal Information
THERMAL METRIC(1) UNIT
20 PINS
RθJA Junction-to-ambient thermal resistance 91.2 RθJC(top) Junction-to-case (top) thermal resistance 25.3 RθJB Junction-to-board thermal resistance 42 °C/W ψJT Junction-to-top characterization parameter 1 ψJB Junction-to-board characterization parameter 41.5 RθJC(bot) Junction-to-case (bottom) thermal resistance — (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1
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8.5 Electrical Characteristics
Q1 Automotive grade devices are specified for TA = –40°C to 125°C. Consumer grade (non-Q1) devices are specified at TA = 25°C. All devices in the family are characterized with AVDD = CPVDD = DVD = 3.3 V, fS = 48 kHz, system clock = 512 fS and 24-bit data unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Resolution 16 24 32 Bits Data Format (PCM Mode) Audio data bit length 16 24 32 Bits fS (1) Sampling frequency 8 384 kHz Clock multiples: 64, 128, 192, 256, 384, fSCK System clock frequency 512, 768, 1024, 1152, 1536, 2048, or 50 MHz 3072 Digital Input/Output for non-Q1 Consumer Grade Devices Logic family: 3.3 V LVCMOS compatible VIH 0.7×DVDD Input logic level V VIL 0.3×DVDD IIH VIN = VDD 10 Input logic current µA IIL VIN = 0 V –10 VOH IOH = –4 mA 0.8×DVDD Output logic level V VOL IOL = 4 mA 0.22×DVDD Logic family 1.8 V LVCMOS compatible VIH 0.7×DVDD Input logic level V VIL 0.3×DVDD IIH VIN = VDD 10 Input logic current µA IIL VIN = 0 V –10 VOH IOH = –2 mA 0.8×DVDD Output logic level V VOL IOL = 2 mA 0.22×DVDD Digital Input/Output for Q1 Automotive Grade Devices Logic family: 3.3 V LVCMOS compatible VIH 0.7×DVDD Input logic level V VIL 0.3×DVDD IIH VIN = VDD 10 Input logic current µA IIL VIN = 0 V –10 VOH IOH = –4 mA 0.8×DVDD Output logic level V VOL IOL = 4 mA 0.22×DVDD Logic family 1.8 V LVCMOS compatible VIH 0.7×DVDD Input logic level V VIL 0.3×DVDD IIH VIN = VDD 10 Input logic current µA IIL VIN = 0 V –10 VOH IOH = –2 mA 0.8×DVDD Output logic level V VOL IOL = 2 mA 0.3×DVDD (1) One sample time is defined as the reciprocal of the sampling frequency. 1tS = 1/fS Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1
PCM5100A,PCM5101A,PCM5102A PCM5100A-Q1,PCM5101A-Q1,PCM5102A-Q1 SLAS859C –MAY 2012–REVISED MAY 2015 www.ti.com Electrical Characteristics (continued) Q1 Automotive grade devices are specified for TA = –40°C to 125°C. Consumer grade (non-Q1) devices are specified at TA = 25°C. All devices in the family are characterized with AVDD = CPVDD = DVD = 3.3 V, fS = 48 kHz, system clock = 512 fS and 24-bit data unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Dynamic Performance (PCM Mode)(2)(3) PCM5102A –93 –83 dB fS = 48 kHz PCM5101A –92 –82 PCM5100A –90 –80 THD+N at –1 dBFS(3) PCM5102A –93 fS = 96 kHz and 192 kHz PCM5101A –92 PCM5100A –90 PCM5102A 106 112 EIAJ, A-weighted, fS = 48 PCM5101A 100 106kHz PCM5100A 95 100 Dynamic range(3) PCM5102A 112 EIAJ, A-weighted, fS = 96 PCM5101A 106kHz and 192 kHz PCM5100A 100 PCM5102A 112 EIAJ, A-weighted, fS = 48 PCM5101A 106kHz PCM5100A 100 Signal-to-noise ratio(3) PCM5102A 112 EIAJ, A-weighted, fS = 96 PCM5101A 106kHz and 192 kHz PCM5100A 100 EIAJ, A-weighted, fS = 48 kHz 113 123 Signal to noise ratio with analog EIAJ, A-weighted, fS = 96 kHz and 192 123mute(3)(4) kHz PCM5102A 100 109 fS = 48 kHz PCM5101A 95 103 PCM5100A 90 97 PCM5102A 109 Channel separation fS = 96 kHz PCM5101A 103 PCM5100A 97 PCM5102A 109 fS = 192 kHz PCM5101A 103 PCM5100A 97 (2) Filter condition: THD+N: 20-Hz HPF, 20-kHz AES17 LPF; Dynamic range: 20-Hz HPF, 20-kHz AES17 LPF; A-weighted signal-to-noise ratio: 20-Hz HPF, 20-kHz AES17 LPF; A-weighted channel separation: 20-Hz HPF, 20-kHz AES17 LPF. Analog performance specifications are measured using the System Two Cascade™ audio measurement system by Audio Precision™ in the RMS mode. (3) Output load is 10 kΩ, with 470-Ω output resistor and a 2.2-nF shunt capacitor (see recommended output filter). (4) Assert XSMT or both L-ch and R-ch PCM data are Bipolar Zero.
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Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1
PCM5100A,PCM5101A,PCM5102A PCM5100A-Q1,PCM5101A-Q1,PCM5102A-Q1 www.ti.com SLAS859C –MAY 2012–REVISED MAY 2015 Electrical Characteristics (continued) Q1 Automotive grade devices are specified for TA = –40°C to 125°C. Consumer grade (non-Q1) devices are specified at TA = 25°C. All devices in the family are characterized with AVDD = CPVDD = DVD = 3.3 V, fS = 48 kHz, system clock = 512 fS and 24-bit data unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Analog Output Output voltage 2.1 VRMS Gain error –6 ±2 6 % of FSR Gain error on Q1 Automotive Grade –7 ±2 7 % of FSRDevices Gain mismatch, channel-to-channel –6 ±2 6 % of FSR Gain mismatch, channel-to-channel on –6 ±2 6 % of FSRQ1 Devices PCM5100/1 bipolar zero error At bipolar zero –5 ±1 5 mV PCM5102 Bipolar zero error At bipolar zero –2 ±1 2 mV Load impedance 1 kΩ Filter Characteristics–1: Normal Pass band 0.45fS Stop band 0.55fS Stop band attenuation –60 dB Pass-band ripple ±0.02 Delay time 20tS s Filter Characteristics–2: Low Latency Pass band 0.47fS Stop band 0.55fS Stop band attenuation –52 dB Pass-band ripple ±0.0001 Delay time 3.5tS s Power Supply Requirements DVDD Digital supply voltage Target DVDD = 1.8 V 1.65 1.8 1.95 VDC DVDD Digital supply voltage Target DVDD = 3.3 V 3 3.3 3.6 AVDD Analog supply voltage 3 3.3 3.6 VDC CPVDD Charge-pump supply voltage 3 3.3 3.6 fS = 48 kHz 7 IDD DVDD supply current at 1.8 V(5) fS = 96 kHz 8 mA fS = 192 kHz 9 fS = 48 kHz 7 IDD DVDD supply current at 1.8 V(6) fS = 96 kHz 8 mA fS = 192 kHz 9 IDD DVDD supply current at 1.8 V(7) Standby 0.3 mA fS = 48 kHz 7 12 IDD DVDD supply current at 3.3 V(5) fS = 96 kHz 8 mA fS = 192 kHz 9 fS = 48 kHz 8 13 IDD DVDD supply current at 3.3 V(6) fS = 96 kHz 9 mA fS = 192 kHz 10 IDD DVDD supply current at 3.3 V(7) Standby 0.5 0.8 mA fS = 48 kHz 11 16 IDD AVDD / CPVDD supply current(5) fS = 96 kHz 11 mA fS = 192 kHz 11 (5) Input is Bipolar Zero data. (6) Input is 1 kHz –1 dBFS data. (7) Power Down Mode Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1
PCM5100A,PCM5101A,PCM5102A PCM5100A-Q1,PCM5101A-Q1,PCM5102A-Q1 SLAS859C –MAY 2012–REVISED MAY 2015 www.ti.com Electrical Characteristics (continued) Q1 Automotive grade devices are specified for TA = –40°C to 125°C. Consumer grade (non-Q1) devices are specified at TA = 25°C. All devices in the family are characterized with AVDD = CPVDD = DVD = 3.3 V, fS = 48 kHz, system clock = 512 fS and 24-bit data unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fS = 48 kHz 22 32 IDD AVDD / CPVDD supply current(6) fS = 96 kHz 22 mA fS = 192 kHz 22 IDD AVDD / CPVDD supply current(7) fS = n/a 0.2 0.4 mA fS = 48 kHz 49 185 Power dissipation, DVDD = 1.8 V(5) fS = 96 kHz 51 mW fS = 192 kHz 53 fS = 48 kHz 85 187 Power dissipation, DVDD = 1.8 V(6) fS = 96 kHz 87 mW fS = 192 kHz 89 Power dissipation, DVDD = 1.8 V(7) fS = n/a (Power Down Mode) 1 mW fS = 48 kHz 60 92.4 Power dissipation, DVDD = 3.3 V(5) fS = 96 kHz 63 mW fS = 192 kHz 66 fS = 48 kHz 99 148.5 Power dissipation, DVDD = 3.3 V(6) fS = 96 kHz 102 mW fS = 192 kHz 106 Power dissipation, DVDD = 3.3 V(7) fS = n/a (Power Down Mode) 2 4 mW
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Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1
8.6 Timing Requirements
Figure 1. Timing Requirements for SCK Input
8.7 Timing Requirements, XSMT
Figure 2. XSMT Timing for Soft Mute and Soft Un-Mute
8.8 Typical Characteristics
25°C, AVDD = CPVDD = DVDD = 3.3 V, fS = 48 kHz, system clock = 512 fS and 24-bit data unless otherwise noted. Figure 3. PCM5101 THD+N versus Input Level Figure 4. PCM5102 THD+N versus Input Level Figure 6. PCM5102 FFT Plot using a 1-kHz tone (–60dBFS)Figure 5. PCM5101 FFT Plot using a 1-kHz tone (–60dBFS) Figure 8. PCM5102 FFT Plot at BPZFigure 7. PCM5101 FFT Plot At Bipolar Zero Data (BPZ)
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32bit /cfb/c08/c03Modulator Current Segment DAC Current Segment DAC I/VI/V Analog Mute Analog Mute Zero Data Detector UVP/Reset PLL Clock Power Supply Ch. PumpPOR Clock Halt Detection Advanced Mute Control SCK BCK LRCK CAPP CAPM VNEG LINE OUT DIN (i2s) PCM510xA CPVDD (3.3V) AVDD (3.3V) DVDD (1.8V or 3.3V) GND PCM5100A,PCM5101A,PCM5102A PCM5100A-Q1,PCM5101A-Q1,PCM5102A-Q1 SLAS859C –MAY 2012–REVISED MAY 2015 www.ti.com
9 Detailed Description
9.1 Overview
The integrated PLL on the device provided adds the flexibility to remove the system clock (commonly known as master clock), allowing a 3-wire I2S connection and reducing system EMI. Powersense undervoltage protection utilizes a two-level mute system. Upon clock error or system power failure, the device digitally attenuates the data (or last known good data) and then mutes the analog circuit. Compared with existing DAC technology, the PCM510xA devices offer up to 20 dB lower out-of-band noise, reducing EMI and aliasing in downstream amplifiers/ADCs. (from traditional 100-kHz OBN measurements to 3 MHz). The PCM510xA devices accept industry-standard audio data formats with 16- to 32-bit data. Sample rates up to 384 kHz are supported.
9.2 Functional Block Diagram
9.3 Feature Description
9.3.1 Terminology
Sampling frequency is symbolized by fS. Full scale is symbolized by FS. Sample time as a unit is symbolized by tS.
9.3.2 Audio Data Interface
9.3.2.1 Audio Serial Interface
The audio interface port is a 3-wire serial port with the signals LRCK, BCK, and DIN. BCK is the serial audio bit clock, used to clock the serial data present on DIN into the serial shift register of the audio interface. Serial data is clocked into the PCM510xA on the rising edge of BCK. LRCK is the serial audio left/right word clock. LRCK polarity for left/right is given by the format selected.
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Table 2. PCM510xA Audio Data Formats, Bit Depths and Clock Rates relation between LRCK and system clock. until resynchronization between LRCK and system clock is completed. until resynchronization between LRCK and BCK is completed.
9.3.2.2 PCM Audio Data Formats
twos-complement, MSB-first audio data; up to 32-bit audio data is accepted. Figure 13. Left Justified Audio Data Format
Figure 14. I2S Audio Data Format
9.3.2.3 Zero Data Detect
data detection to begin the muting process etc.
9.3.3 XSMT Pin (Soft Mute / Soft Un-Mute)
attenuation is then applied every sample time from 0 dBFS to –∞. The soft attenuation ramp takes 104 samples. are applied every sample time from –∞ to 0 dBFS. The un-mute takes 104 samples. In systems where XSMT is not required, it can be directly connected to AVDD.
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9.3.4 Audio Processing
9.3.4.1 Interpolation Filter
Table 3. Digital Interpolation Filter Options
0 FIR normal x8/x4/x2/x1 interpolation filters
1 IIR low-latency x8/x4/x2/x1 interpolation filters
The normal x8 / x4 / x2 / x1(bypass) interpolation filter is programmed for sample rates from 8 kHz to 384 kHz. Table 4. Normal x8 Interpolation Filter Figure 15. Normal x8 Interpolation Filter Frequency Figure 16. Normal x8 Interpolation Filter Impulse
Figure 17. Normal x8 Interpolation Filter Passband Ripple
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Table 6. Normal x2 Interpolation Filter Figure 21. Normal x2 Interpolation Filter Frequency Figure 22. Normal x2 Interpolation Filter Impulse Figure 23. Normal x2 Interpolation Filter Passband Ripple
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Table 8. Low Latency x4 Interpolation Filter Figure 27. Low Latency x4 Interpolation Filter Frequency Figure 28. Low Latency x4 Interpolation Filter Impulse Figure 29. Low Latency x4 Interpolation Filter Passband Ripple
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9.3.5 Reset and System Clock Functions
9.3.5.1 Clocking Overview
interface in one form or another. operate with or without an external SCK.
9.3.5.2 Clock Slave Mode With Master/System Clock (SCK) Input (4 Wire I2S)
96kHz are detected as "double rate," 32kHz, 44.1kHz and 48kHz will be detected as "single rate". Table 10. System Master Clock Inputs for Audio Related Clocks (1) This system clock rate is not supported for the given sampling frequency. (2) This system clock rate is supported by PLL mode.
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9.3.5.3 Clock Slave Mode with BCK PLL to Generate Internal Clocks (3-Wire PCM)
electromagnetic interference. The internal PLL is disabled as soon as an external SCK is supplied. Table 11. BCK Rates (MHz) by LRCK Sample Rate for
9.4 Device Functional Modes
9.4.1 External SCK and PLL Activation
a PCM510xA device supplies a SCK if an external SCK is not present at powerup.
9.4.1.1 Interpolation Filter Modes
Interpolation-filter options are controlled by the FLT pin. See Table 3. De-emphasis control for 44.1-kHz fS is controlled by the DEMP pin. See Pin Configuration and Functions.
9.4.1.3 Audio Format
Audio format is selected by the FMT pin. See Pin Configuration and Functions.
0.1 F/c109 10 F/c109
0.1 F/c109
10 F/c109
10 Applications and Implementation
validate and test their design implementation to confirm system functionality.
10.1 Application Information
10.1.1 Typical Applications
Figure 33. Simplified Schematic, Hardware-Controlled Subsystem
10.1.1.1 Example Design Requirements
- Device control method: hardware control – Normal filter latency – I2S digital audio interface – Power rail monitoring from the system 12-V rail to mute early on system power loss
- Single-ended 2.1-VRMS analog outputs
- 3-wire I2S interface (BCK PLL)
- Single 3.3-V supply
10.1.1.2 Detailed Design Procedure
- Device control method: See Pin Configuration and Functions and Audio Processing. – Normal filter latency: FLT pin tied low – Audio format selection: FMT pin tied low
- Clock and PLL setup (See Reset and System Clock Functions). Ensure incoming BCK meets minimum requirements.
- XSMT pin setup for 12-V monitoring (See External Power Sense Undervoltage Protection Mode).
- Single-supply 3.3-V operation (See Setting Digital Power Supplies and I/O Voltage Rails)
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10.1.1.3 Application Curve
Figure 34. PCM5101A FFT Plot, DC to 20 kHz with a 1 kHz, –60dBFS Input
11 Power Supply Recommendations
11.1 Power Supply Distribution and Requirements
Figure 35. Power Distribution Tree within PCM510xA Table 12. Power Supply Pin Descriptions AVDD Analog voltage supply; must be 3.3 V. This powers all analog circuitry that the DAC runs on. DVDD Digital voltage supply. This is used as the I/O voltage control and the input to the onchip LDO.
11.2 Recommended Powerdown Sequence
device not having enough time to detect power loss and start the muting process. mute. This process takes 150 sample times (ts) + 0.2 ms. much faster than a 48-kHz system. complete, the PCM510xA outputs are hard muted to ground.
11.2.1 Planned Shutdown
- Assert XSMT low 150 tS + 0.2 ms before power is removed.
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Figure 36. Assert XSMT
- Stop I2S clocks (SCK, BCK, LRCK) 3 ms before powerdown as shown in Figure 37.
Figure 37. Stop I2C Clocks
11.2.2 Unplanned Shutdown
XSMT pin can also be used in parallel with a GPIO pin from the system microcontroller/DSP or power supply.
Figure 38. Using the XSMT Pin
11.3 External Power Sense Undervoltage Protection Mode
- If the XSMT pin makes a transition from “1”to “0”over 6 ms or more, the device switches into external under- voltage protection mode. This mode uses two trigger levels: – When the XSMT pin level reaches 2 V, soft mute process begins. – When the XSMT pin level reaches 1.2 V, analog mute engages, regardless of digital audio level, and analog shutdown begins. (DAC and related circuitry powers down). If XSMT is moved from "1" to "0" in 20 ns or less, then the device will interpret it as a digital controlled request to mute. It will perform a soft mute, then move to standby. A timing diagram to show this is shown in Figure 40. NOTE The XSMT input pin voltage range is from –0.3 V to DVDD+0.3 V. The ratio of external resistors must produce a voltage within this input range. Any increase in power supply (such as power supply positive noise or ripple) can pull the XSMT pin higher than DVDD+0.3 V. For example, if the PCM510xA is monitoring a 12-V input, and dividing the voltage by 4, then the voltage at XSMT during ideal power supply conditions is 3.3 V. A voltage spike higher than 14.4 V causes a voltage greater than 3.6 V (DVDD+0.3) on the XSMT pin, potentially damaging the device. Providing the divider is set appropriately, any DC voltage can be monitored.
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11.4 Power-On Reset Function
digital interpolation filter selected. Figure 41. Power-On Reset Timing, DVDD = 3.3 V Figure 42. Power-On Reset Timing, DVDD = 1.8 V
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11.5 PCM510xA Power Modes
11.5.1 Setting Digital Power Supplies and I/O Voltage Rails
The internal digital core of the PCM510xA devices run from a 1.8-V supply. This can be generated by the internal LDO, or by an external 1.8-V supply. DVDD is used to set the I/O voltage, and to be used as the input to the onchip LDO that creates the 1.8 V required by the digital core. For systems that require 3.3 V I/O support, but lower power consumption, DVDD should be connected to 3.3 V and LDOO can be connected to an external 1.8-V source. Doing so will disable the onchip LDO. When setting I/O voltage to be 1.8 V, both DVDD and LDOO must be provided with an external 1.8-V supply.
11.5.2 Power Save Modes
The PCM510xA devices offer two power-save modes: standby and power-down. When a clock error (SCK, BCK, and LRCK) or clock halt is detected, the PCM510xA device automatically enters standby mode. The DAC and line driver are also powered down. When BCK and LRCK remain at a low level for more than 1 second, the PCM510xA device automatically enters powerdown mode. Power-down mode disables the negative charge pump and bias/reference circuit, in addition to those disabled in standby mode. When expected audio clocks (SCK, BCK, LRCK) are applied to the PCM510xA device, or if BCK and LRCK start correctly while SCK remains at ground level for 16 successive LRCK periods, the device starts its powerup sequence automatically. Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 33 Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1
1 CPVDD
2 CAPP
3 CPGND
4 CAPM
5 VNEG
6 OUTL
7 OUTR
8 AVDD
9 AGND
10 DEMP
12 Layout
12.1 Layout Guidelines
- The PCM510xA family of devices are simple to layout. Most engineers use a shared common ground for an entire device. GND can be consider AGND and DGND connected.
- Good system partitioning should keep digital clock and interface traces away from the analog outputs for highest analog performance. This reduces any high speed clock return currents influencing the analog outputs.
- Power supply and charge pump decoupling capacitors should be placed as close as possible to the device.
- The top layer should be used for routing signals, whilst the bottom layer can be used for GND.
Figure 43. PCM510x Layout Example
34 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated
13 Device and Documentation Support
13.1 Related Links
resources, tools and software, and quick access to sample or buy. Table 14. Related Links
13.2 Community Resources
13.3 Trademarks
Directpath is a trademark of Texas Instruments, Inc. System Two Cascade, Audio Precision are trademarks of Audio Precision.
13.4 Electrostatic Discharge Caution
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
14 Mechanical, Packaging, and Orderable Information
this document. For browser-based versions of this data sheet, see the left-hand navigation.
14.1 Mechanical Data
www.ti.com 7-Oct-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) PCM5100APW Active Production TSSOP (PW) | 20 70 | TUBE Yes NIPDAU Level-1-260C-UNLIM -25 to 85 PCM5100A PCM5100APW.A Active Production TSSOP (PW) | 20 70 | TUBE Yes NIPDAU Level-1-260C-UNLIM -25 to 85 PCM5100A PCM5100APWR Active Production TSSOP (PW) | 20 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -25 to 85 PCM5100A PCM5100APWR.A Active Production TSSOP (PW) | 20 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -25 to 85 PCM5100A PCM5100APWRG4 Active Production TSSOP (PW) | 20 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -25 to 85 PCM5100A PCM5100APWRG4.A Active Production TSSOP (PW) | 20 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -25 to 85 PCM5100A PCM5100AQPWRQ1 Active Production TSSOP (PW) | 20 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 P5100AQ1 PCM5100AQPWRQ1.A Active Production TSSOP (PW) | 20 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 P5100AQ1 PCM5101APW Active Production TSSOP (PW) | 20 70 | TUBE Yes NIPDAU Level-1-260C-UNLIM -25 to 85 PCM5101A PCM5101APW.A Active Production TSSOP (PW) | 20 70 | TUBE Yes NIPDAU Level-1-260C-UNLIM -25 to 85 PCM5101A PCM5101APWR Active Production TSSOP (PW) | 20 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -25 to 85 PCM5101A PCM5101APWR.A Active Production TSSOP (PW) | 20 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -25 to 85 PCM5101A PCM5101AQPWRQ1 Active Production TSSOP (PW) | 20 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 P5101AQ1 PCM5101AQPWRQ1.A Active Production TSSOP (PW) | 20 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 P5101AQ1 PCM5102APW Active Production TSSOP (PW) | 20 70 | TUBE Yes NIPDAU Level-1-260C-UNLIM -25 to 85 PCM5102A PCM5102APW.A Active Production TSSOP (PW) | 20 70 | TUBE Yes NIPDAU Level-1-260C-UNLIM -25 to 85 PCM5102A PCM5102APWG4 Active Production TSSOP (PW) | 20 70 | TUBE Yes NIPDAU Level-1-260C-UNLIM -25 to 85 PCM5102A PCM5102APWG4.A Active Production TSSOP (PW) | 20 70 | TUBE Yes NIPDAU Level-1-260C-UNLIM -25 to 85 PCM5102A PCM5102APWR Active Production TSSOP (PW) | 20 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -25 to 85 PCM5102A PCM5102APWR.A Active Production TSSOP (PW) | 20 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -25 to 85 PCM5102A PCM5102AQPWRQ1 Active Production TSSOP (PW) | 20 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 P5102AQ1 PCM5102AQPWRQ1.A Active Production TSSOP (PW) | 20 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 P5102AQ1 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. Addendum-Page 1
www.ti.com 7-Oct-2025 (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF PCM5100A, PCM5100A-Q1, PCM5101A, PCM5101A-Q1, PCM5102A, PCM5102A-Q1 :
- Catalog : PCM5100A , PCM5101A , PCM5102A
- Automotive : PCM5100A-Q1 , PCM5101A-Q1 , PCM5102A-Q1 NOTE: Qualified Version Definitions:
- Catalog - TI's standard catalog product
- Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 15-Jul-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 15-Jul-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCM5100APWR TSSOP PW 20 2000 350.0 350.0 43.0 PCM5100APWRG4 TSSOP PW 20 2000 350.0 350.0 43.0 PCM5100AQPWRQ1 TSSOP PW 20 2000 350.0 350.0 43.0 PCM5101APWR TSSOP PW 20 2000 350.0 350.0 43.0 PCM5101AQPWRQ1 TSSOP PW 20 2000 350.0 350.0 43.0 PCM5102APWR TSSOP PW 20 2000 350.0 350.0 43.0 PCM5102AQPWRQ1 TSSOP PW 20 2000 350.0 350.0 43.0 Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 15-Jul-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) PCM5100APW PW TSSOP 20 70 530 10.2 3600 3.5 PCM5100APW.A PW TSSOP 20 70 530 10.2 3600 3.5 PCM5101APW PW TSSOP 20 70 530 10.2 3600 3.5 PCM5101APW.A PW TSSOP 20 70 530 10.2 3600 3.5 PCM5102APW PW TSSOP 20 70 530 10.2 3600 3.5 PCM5102APW.A PW TSSOP 20 70 530 10.2 3600 3.5 PCM5102APWG4 PW TSSOP 20 70 530 10.2 3600 3.5 PCM5102APWG4.A PW TSSOP 20 70 530 10.2 3600 3.5 Pack Materials-Page 3
www.ti.com PACKAGE OUTLINE C 18X 0.65 5.85 20X 0.30 0.19 TYP6.6 6.2
1.2 MAX
0.15 0.05 0.25 GAGE PLANE -80 B NOTE 4 4.5 4.3 A NOTE 3 6.6 6.4 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightPW0020A SMALL OUTLINE PACKAGE 4220206/A 02/2017
0.1 C A B
0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 2.500
www.ti.com EXAMPLE BOARD LAYOUT
0.05 MAX
0.05 MIN
20X (1.5) 20X (0.45) 18X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0020A SMALL OUTLINE PACKAGE 4220206/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 10 11 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED
www.ti.com EXAMPLE STENCIL DESIGN 20X (1.5) 20X (0.45) 18X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0020A SMALL OUTLINE PACKAGE 4220206/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 10 11
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