PCM4220PFB

High-Performance, 2-Ch, 24-Bit, 216kHz Sampling Multi-Bit Delta-Sigma ADC (Rev. C)

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Manufacturer or author: Texas Instruments, Incorporated [SBAS407,C]
PDF pages: 37

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www.ti.com SBAS407C DECEMBER 2006 REVISED AUGUST 2009 High-Performance, Two-Channel, 24-Bit, 216kHz Sampling Multi-Bit Delta-Sigma Analog-to-Digital Converter Digital High-Pass Filtering Removes DC Offset Supports Linear PCM Output Data Left and Right Channel Filters May Be Disabled Independently Output Sampling Rates from 8kHz to 216kHz Audio Serial Port Interface Differential Voltage Inputs Master or Slave Mode Operation On-Chip Voltage Reference Improves Supports Left-Justified, I S and TDM Power-Supply Noise Rejection Data Formats Dynamic Performance (24-bit word length) Output Word Length Reduction Dynamic Range 60dB input, A-weighted): Overflow Indicators for the Left and Right 123dB typical Channels Dynamic Range 60dB input, 20kHz Analog Power Supply: bandwidth): 121dB typical +4.0V nominal Total Harmonic Distortion Noise Digital Power Supply: 1dB input, 20kHz bandwidth): +3.3V nominal 108dB typical Power-Down Mode: 4mW typical Channel Separation: 135dB Package: TQFP-48, RoHS compliant Low Power Dissipation: 305mW typical for 48kHz sampling rate Digital Audio Recorders and 330mW typical for 96kHz sampling rate Mixing Desks 340mW typical for 192kHz sampling rate Digital Live Sound Consoles Linear Phase Digital Decimation Filtering Digital Audio Effects Processors Select from Classic or Low Group Delay Surround Sound Encoders Filter Responses Broadcast Studio Equipment Low Passband Ripple Data Acquisition and Classic: 0.00015dB Measurement Systems Low Group Delay: 0.001dB Audio Test Systems blank Sonar blank Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. Windows is a registered trademark of Microsoft Corporation. I2S is a trademark of NXP Semiconductor. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright 2006 2009, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

DESCRIPTION

(1) PCM4220 SBAS407C DECEMBER 2006 REVISED AUGUST 2009 www.ti.com The PCM4220 is a high-performance, two-channel analog-to-digital (A/D) converter designed for use in professional audio applications. Offering outstanding dynamic performance, the PCM4220 provides 24-bit linear PCM output data, with support for output word length reduction to 20-, 18-, or 16-bits. The PCM4220 includes three sampling modes, supporting output sampling rates from 8kHz to 216kHz. The PCM4220 is ideal for a variety of digital audio recording and processing applications. A linear phase digital decimation filtering engine supports Classic and Low Group Delay filter responses, allowing optimization for either studio or live sound applications. In addition, digital high-pass filtering is provided for DC offset removal. The The PCM4220 is configured using dedicated control pins for selection of sampling modes, audio data formats and word length, decimation filter response, high-pass filter disable, and reset/power-down functions. While providing uncompromising performance, the PCM4220 addresses power concerns with just over 300mW typical total power dissipation, making the device suitable for multi-channel audio systems. The PCM4220 is typically powered from a +4.0V analog supply and a +3.3V digital supply. The digital I/O is logic-level compatible with common digital signal processors, digital interface transmitters, and programmable logic devices. The PCM4220 is available in a TQFP-48 package, which is RoHS-compliant. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI website at www.ti.com Over operating free-air temperature range, unless otherwise noted. VALUE Power supplies VCC1, VCC2 0.3V to +6.0V VDD 0.3V to +4.0V Digital input voltage All digital input and I/O pins 0.3V (VDD 0.3V) +4.0V Analog input voltage VINL+, VINL VINR+, VINR 0.3V (VCC 0.3V) +6.0V Input current (all pins except power and ground) 10mA Ambient operating temperature C to +85 C Storage temperature C to +150 C (1) These limits are stress ratings only. Stresses beyond these limits may result in permanent damage. Extended exposure to absolute maximum ratings may degrade device reliability. Normal operation or performance at or beyond these limits is not specified or ensured. Submit Documentation Feedback Copyright 2006 2009, Texas Instruments Incorporated Product Folder Link(s): PCM4220

CHARACTERISTICS: DIGITAL AND DYNAMIC PERFORMANCE PCM4220 www.ti.com SBAS407C DECEMBER 2006 REVISED AUGUST 2009 All specifications are at T A +25 VCC1 VCC2 +4.0V, and VDD +3.3V, unless otherwise noted. PCM4220 PARAMETER CONDITIONS MIN TYP MAX UNIT DIGITAL I/O CHARACTERISTICS (Applies to all digital pins) High-level input voltage, V IH 0.7 VDD VDD V Low-level input voltage, V IL 0.3 VDD V High-level input current, I IH µ A Low-level input current, I IL µ A High-level output voltage, V OH I O 2mA 0.8 VDD VDD V Low-level output voltage, V OL I O +2mA 0.2 VDD V Input capacitance, C IN pF PCM OUTPUT SAMPLING RATE, f S Normal mode kHz Double Speed mode 108 kHz Quad Speed mode 108 216 kHz MASTER CLOCK INPUT Normal mode, MCKI 256f S 2.048 13.824 MHz Double Speed mode, MCKI 128f S 6.912 13.824 MHz Quad Speed mode, MCKI 64f S 6.912 13.824 MHz DYNAMIC PERFORMANCE (1) PCM Output, Normal Mode, f S 48kHz BW 22Hz to 20kHz Total harmonic distortion noise (THD+N) f 997Hz, 1dB input 108 100 dB f 997Hz, 20dB input 100 dB f 997Hz, 60dB input dB Dynamic range, no weighting f 997Hz, 60dB input 121 dB Dynamic range, A-weighted f 997Hz, 60dB input 118 123 dB Channel separation f 10kHz, 1dB input 115 135 dB PCM Output, Double Speed Mode, f S 96kHz BW 22Hz to 40kHz Total harmonic distortion noise (THD+N) f 997Hz, 1dB input 108 dB f 997Hz, 20dB input dB f 997Hz, 60dB input dB Dynamic range, no weighting f 997Hz, 60dB input 118 dB Dynamic range, A-weighted f 997Hz, 60dB input 123 dB Channel separation f 10kHz, 1dB input 135 dB PCM Output, Quad Speed Mode, f S 192kHz BW 22Hz to 40kHz Total harmonic distortion noise (THD+N) f 997Hz, 1dB input 107 dB f 997Hz, 20dB input dB f 997Hz, 60dB input dB Dynamic range, no weighting f 997Hz, 60dB input 118 dB Dynamic range, A-weighted f 997Hz, 60dB input 123 dB Channel separation f 10kHz, 1dB input 135 dB PCM Output, Quad Speed Mode, f S 192kHz BW 22Hz to 80kHz Total harmonic distortion noise (THD+N) f 997Hz, 1dB input 106 dB f 997Hz, 20dB input dB f 997Hz, 60dB input dB Dynamic range, no weighting f 997Hz, 60dB input 112 dB Dynamic range, A-weighted f 997Hz, 60dB input 123 dB Channel separation f 10kHz, 1dB input 135 dB (1) Typical PCM output performance is measured and characterized with an Audio Precision SYS-2722 192kHz test system and a PCM4222EVM evaluation module modified for use with the PCM4220. Measurement bandwidth and weighting settings are noted in the Parameter and Conditions columns. THD+N is measured without the use of weighting filters. Master mode operation is utilized for all typical performance parameters, with the master clock input frequency (MCKI) set to 12.288MHz. Copyright 2006 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM4220

CHARACTERISTICS: ANALOG INPUTS, OUTPUTS, AND DC ERROR PCM4220 SBAS407C DECEMBER 2006 REVISED AUGUST 2009 www.ti.com ELECTRICAL CHARACTERISTICS: DIGITAL AND DYNAMIC PERFORMANCE (continued) All specifications are at T A +25 VCC1 VCC2 +4.0V, and VDD +3.3V, unless otherwise noted. PCM4220 PARAMETER CONDITIONS MIN TYP MAX UNIT Digital Decimation Filter Characteristics: Classic Response Passband 0.4535 f S Hz Passband ripple 0.00015 dB Stop band 0.5465 f S Hz Stop band attenuation 100 dB Group delay 39/f S Seconds Digital Decimation Filter Characteristics: Low Group Delay Response Passband 0.4167 f S Hz Passband ripple 0.001 dB Stop band 0.5833 f S Hz Stop band attenuation dB Group delay 21/f S Seconds Digital High-Pass Filter Characteristics 3dB corner frequency High-pass filter enabled f S /48000 Hz All specifications are at T A +25 VCC1 VCC2 +4.0V, and VDD +3.3V, unless otherwise noted. PCM4220 PARAMETER CONDITIONS MIN TYP MAX UNIT ANALOG INPUTS Full-scale input range Differential input Referenced from VINL+ to VINL or VINR+ to 5.6 V PP VINR Per input pin Applies to VINL+, VINL VINR+, or VINR 2.8 V PP Input impedance Applies to VINL+, VINL VINR+, or VINR 2.8 k Ω Common-mode rejection 100 dB ANALOG OUTPUTS Common-mode output voltage Left channel, VCOML Measured from VCOML to AGND 0.4875 VCC2 V Right channel, VCOMR Measured from VCOMR to AGND 0.4875 VCC1 V Common-mode output current Applies to VCOML or VCOMR 200 µ A DC ERROR Output offset error Digital high-pass filter disabled mV Offset drift Digital high-pass filter disabled 3.5 µ C Submit Documentation Feedback Copyright 2006 2009, Texas Instruments Incorporated Product Folder Link(s): PCM4220

CHARACTERISTICS: POWER SUPPLIES ELECTRICAL CHARACTERISTICS: AUDIO INTERFACE TIMING PCM4220 www.ti.com SBAS407C DECEMBER 2006 REVISED AUGUST 2009 All specifications are at T A +25 VCC1 VCC2 +4.0V, VDD +3.3V, and MCKI 12.288MHz, unless otherwise noted. PCM4220 PARAMETER CONDITIONS MIN TYP MAX UNIT POWER SUPPLIES Recommended supply voltage range VCC1, VCC2 C T A +85 C +3.8 +4.0 +4.2 V VCC1, VCC2 C T A C +3.9 +4.0 +4.2 V VDD C T A +85 C +2.4 +3.3 +3.6 V Supply current: power-down RST (pin 36) held low with no clocks applied ICC1 ICC2 VCC1 VCC2 +4.0V 600 µ A IDD VDD +3.3V 325 µ A Supply current: f S 48kHz ICC1 ICC2 VCC1 VCC2 +4.0V mA IDD VDD +3.3V mA Supply current: f S 96kHz ICC1 ICC2 VCC1 VCC2 +4.0V mA IDD VDD +3.3V mA Supply current: f S 192kHz ICC1 ICC2 VCC1 VCC2 +4.0V mA IDD VDD +3.3V mA Total power dissipation: power-down 3.5 mW Total power dissipation: f S 48kHz 305 360 mW Total power dissipation: f S 96kHz 330 mW Total power dissipation: f S 192kHz 340 mW All specifications are at T A +25 VCC1 VCC2 +4.0V, and VDD +3.3V, unless otherwise noted. PCM4220 PARAMETER CONDITIONS MIN TYP MAX UNIT AUDIO SERIAL PORT LRCK period, t LRCKP All data formats 4.62 125 µ s LRCK high/low time, t LRCKHL 0.45 t LRCKP 0.55 t LRCKP µ s Left-Justified, I and TDM Master mode formats TDM slave mode formats t BCKP 0.55 t LRCKP µ s BCK period, t BCKP Left-Justified and I S data formats Normal sampling mode t LRCKP /128 ns Double Speed sampling mode t LRCKP /64 ns Quad Speed sampling mode t LRCKP /64 ns BCK period, t BCKP TDM data formats Normal sampling mode t LRCKP /256 ns Double Speed sampling mode t LRCKP /128 ns Quad Speed sampling mode t LRCKP /64 ns BCK high/low time, t BCKHL All data formats 0.45 t BCKP 0.55 t BCKP ns Data output delay, t DO All data formats ns Copyright 2006 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM4220

www.ti.com Figure Audio Serial Port Timing: Left-Justified and I S Data Formats Figure Audio Serial Port Timing: TDM Data Formats Submit Documentation Feedback Copyright 2006 2009, Texas Instruments Incorporated Product Folder Link(s): PCM4220

VCOMR REFGNDR VREFR DGND FMT0 FMT1 OWL0 OWL1 DGND S/ M OVFR OVFL VCOML REFGNDL VREFLPCMENHPFDRHPFDL FS0 FS1 DF DGNDDGND DGND AGND VINR/c45 VINR+ VCC1 AGND AGND AGND AGND VCC2 VINL/c45 VINL+ AGND 48 47 46 45 44 43 42 41 40 39 38 13 14 15 16 17 18 19 20 21 22 23 PCM4220 PCM4220 www.ti.com SBAS407C DECEMBER 2006 REVISED AUGUST 2009 PFB PACKAGE TQFP-48 (TOP VIEW) TERMINAL FUNCTIONS PIN NAME NO. I/O inverting, 2.8V PP nominal full-scale VINR+ Input Right channel noninverting, 2.8V PP nominal full-scale VCC1 Power Analog supply, +4.0V nominal AGND Ground Analog ground AGND Ground Analog ground AGND Ground Analog ground AGND Ground Analog ground VCC2 Power Analog supply, +4.0V nominal VINL Input Left channel inverting, 2.8V PP nominal full-scale VINL+ Input Left channel noninverting, 2.8V PP nominal full-scale AGND Ground Analog ground VCOML Output Left channel common-mode voltage, (0.4875 VCC2) nominal REFGNDL Ground Left channel reference ground, connect to analog ground VREFL Output Left channel reference output for decoupling purposes only PCMEN Input PCM output enable (active high) HPFDR Input Right channel high-pass filter disable (active high) HPFDL Input Left channel high-pass filter disable (active high) Copyright 2006 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM4220

www.ti.com TERMINAL FUNCTIONS (continued) PIN NAME NO. I/O modes: FS0 and FS1 Normal mode FS0 Input FS0 and FS1 Double Speed mode FS1 FS0 and FS1 Quad Speed mode FS0 and FS1 Reserved Sampling mode Digital decimation filter response: DF Input DF Classic filter response DF Low Group Delay response DGND Ground Digital ground DGND Ground Digital ground DGND Ground Digital ground TDM active sub-frame: SUB0 and SUB1 Sub-frame SUB1 Input SUB0 and SUB1 Sub-frame SUB0 SUB0 and SUB1 Sub-frame SUB0 and SUB1 Sub-frame NC No external connection, internally bonded to ESD pad NC No external connection, internally bonded to ESD pad NC No external connection, internally bonded to ESD pad DGND Ground Digital ground VDD Power Digital supply, +3.3V nominal DATA Output Audio serial port data BCK I/O Audio serial port bit clock LRCK I/O Audio serial port left/right word clock MCKI Input Master clock RST Input Reset and power-down (active low) OVFL Output Left channel overflow flag (active high) OVFR Output Right channel overflow flag (active high) Audio serial port Slave/Master mode: M Input M Master mode M Slave mode DGND Output Digital ground Output word length: OWL0 and OWL1 24-bits OWL1 Input OWL0 and OWL1 18-bits OWL0 OWL0 and OWL1 20-bits OWL0 and OWL1 16-bits Audio data format: FMT0 and FMT1 Left-justified FMT1 Input FMT0 and FMT1 I S FMT0 FMT0 and FMT1 TDM FMT0 and FMT1 TDM with one BCK delay DGND Ground Digital ground VREFR Output Right channel reference output for decoupling purposes only REFGNDR Ground Right channel reference ground, connect to analog ground VCOMR Output Right channel common-mode voltage (0.4875 VCC1 nominal) Submit Documentation Feedback Copyright 2006 2009, Texas Instruments Incorporated Product Folder Link(s): PCM4220

Frequency□(Hz) Amplitude□(dB) /c4520 /c4540 /c4560 /c4580 /c45100 /c45120 /c45140 /c45160 /c45180 1k10020 10k 20k f =□48kHz f =□997kHz, 60dB S IN /c45 Frequency□(Hz) Amplitude□(dB) /c4520 /c4540 /c4560 /c4580 /c45100 /c45120 /c45140 /c45160 /c45180 1k10020 10k 20k f =□48kHz Idle□Channel□(no□input) S Input□Frequency□(Hz) THD+N□(dB) /c4560 /c4570 /c4580 /c4590 /c45100 /c45110 /c45120 /c45130 1k10020 10k 20k f =□48kHz Input□Amplitude□= 1dB BW□=□22Hz□to□20kHz S /c45 Input□Amplitude□(dB) THD+N□(dBFS) /c4560 /c4570 /c4580 /c4590 /c45100 /c45110 /c45120 /c45130 /c4540/c45120/c45140 /c4520 0/c45100 /c4580 /c4560 f =□48kHz f =□997Hz BW□=□22Hz□to□20kHz S IN Input□Frequency□(kHz) Channel□Separation□(dB) /c4520 /c45100 /c45120 /c45140 /c45160 /c45180 /c45200 1020 12 20 4 6 8 /c4580 /c4560 /c4540 14 16 18 f =□48kHzS Left□Channel Right□Channel Input□Amplitude□(dB) Linearity□(dBFS) /c4520 /c4540 /c4560 /c4580 /c45100 /c45120 /c45140 /c4540/c45120/c45140 /c4520 0/c45100 /c4580 /c4560 f =□48kHzS PCM4220 www.ti.com SBAS407C DECEMBER 2006 REVISED AUGUST 2009 At T A +25 VCC1 VCC2 +4.0V, and VDD +3.3V, unless otherwise noted. FFT PLOT FFT PLOT Figure Figure THD+N vs INPUT FREQUENCY THD+N vs INPUT AMPLITUDE Figure Figure CHANNEL SEPARATION vs INPUT FREQUENCY LINEARITY Figure Figure Copyright 2006 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM4220

Frequency□(Hz) Amplitude□(dB) /c4520 /c4540 /c4560 /c4580 /c45100 /c45120 /c45140 /c45160 /c45180 1k10020 10k 50k f =□96kHz f =□997Hz, 60dB S IN /c45 Frequency□(Hz) Amplitude□(dB) /c4520 /c4540 /c4560 /c4580 /c45100 /c45120 /c45140 /c45160 /c45180 1k10020 10k 50k f =□96kHz Idle□Channel□(no□input) S Input□Frequency□(Hz) THD+N□(dB) /c4560 /c4570 /c4580 /c4590 /c45110 /c45120 /c45130 1k10020 10k 40k /c45100 f =□96kHz Input□Amplitude□= 1dB BW□=□22Hz□to□40kHz S /c45 Input□Amplitude□(dB) THD+N□(dBFS) /c4560 /c4570 /c4580 /c4590 /c45100 /c45110 /c45120 /c45130 /c4540/c45120/c45140 /c4520 0/c45100 /c4580 /c4560 f =□96kHz f =□997Hz BW□=□22Hz□to□40kHz S IN Input□Frequency□(kHz) Channel□Separation□(dB) /c4580 /c45100 /c45120 /c45140 /c45160 /c45180 /c45200 2550 30 4010 15 20 35 /c4560 /c4540 /c4520 f =□96kHzS Left□Channel Right□Channel Input□Amplitude□(dB) Linearity□(dBFS) /c4520 /c4540 /c4560 /c4580 /c45100 /c45120 /c45140 /c4540/c45120/c45140 /c4520 0/c45100 /c4580 /c4560 f =□96kHzS PCM4220 SBAS407C DECEMBER 2006 REVISED AUGUST 2009 www.ti.com TYPICAL CHARACTERISTICS (continued) At T A +25 VCC1 VCC2 +4.0V, and VDD +3.3V, unless otherwise noted. FFT PLOT FFT PLOT Figure Figure 10. THD+N vs INPUT FREQUENCY THD+N vs INPUT AMPLITUDE Figure 11. Figure 12. CHANNEL SEPARATION vs INPUT FREQUENCY LINEARITY Figure 13. Figure 14. Submit Documentation Feedback Copyright 2006 2009, Texas Instruments Incorporated Product Folder Link(s): PCM4220

Frequency□(Hz) Amplitude□(dB) /c4520 /c4540 /c4560 /c4580 /c45100 /c45120 /c45140 /c45160 /c45180 1k10020 10k 100k f =□192kHz f =□997Hz, 60dB S IN /c45 Frequency□(Hz) Amplitude□(dB) /c4520 /c4540 /c4560 /c4580 /c45100 /c45120 /c45140 /c45160 /c45180 1k10020 10k 100k f =□192kHz Idle□Channel□(no□input) S Input□Frequency□(Hz) THD+N□(dB) /c4560 /c4570 /c4580 /c4590 /c45100 /c45110 /c45120 /c45130 1k10020 10k 80k f =□192kHz Input□Amplitude□= 1dB BW□=□22Hz□to□80kHz S /c45 Input□Amplitude□(dB) THD+N□(dBFS) /c4560 /c4570 /c4580 /c4590 /c45100 /c45110 /c45120 /c45130 /c4540/c45120/c45140 /c4520 0/c45100 /c4580 /c4560 f =□192kHz f =□997Hz BW□=□22Hz□to□80kHz S IN Input□Frequency□(kHz) Channel□Separation□(dB) /c4580 /c45100 /c45120 /c45140 /c45160 /c45180 /c45200 50100 60 8020 30 40 70 /c4560 /c4540 /c4520 f =□192kHzS Left□Channel Right□Channel Input□Amplitude□(dB) Linearity□(dBFS) /c4520 /c4540 /c4560 /c4580 /c45100 /c45120 /c45140 /c4540/c45120/c45140 /c4520 0/c45100 /c4580 /c4560 f =□192kHzS PCM4220 www.ti.com SBAS407C DECEMBER 2006 REVISED AUGUST 2009 TYPICAL CHARACTERISTICS (continued) At T A +25 VCC1 VCC2 +4.0V, and VDD +3.3V, unless otherwise noted. FFT PLOT FFT PLOT Figure 15. Figure 16. THD+N vs INPUT FREQUENCY THD+N vs INPUT AMPLITUDE Figure 17. Figure 18. CHANNEL SEPARATION vs INPUT FREQUENCY LINEARITY Figure 19. Figure 20. Copyright 2006 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM4220

Frequency□(Hz) Amplitude□(dB) /c450.4 /c450.6 /c450.8 /c451.0 /c451.2 /c451.4 /c451.6 /c451.8 /c452.0 1k10020 10k 20k /c450.2 f =□48kHz Classic□or□Low□Group□Delay□Response High-Pass□Filter□Enabled Input□Amplitude□= 1dB S /c45 Frequency□(Hz) Amplitude□(dB) /c450.4 /c450.6 /c450.8 /c451.0 /c451.2 /c451.4 /c451.6 /c451.8 /c452.0 1k10020 10k 40k /c450.2 f =□96kHz Classic□or□Low□Group□Delay□Response Enabled Input□Amplitude□= 1dB S High-Pass□Filter /c45 Frequency□(Hz) Amplitude□(dB) /c450.4 /c450.6 /c450.8 /c451.0 /c451.2 /c451.4 /c451.6 /c451.8 /c452.0 1k10020 10k 80k /c450.2 f =□192kHz High-Pass□Filter□Enabled Input□Amplitude□= 1dB S /c45 Normalized□Frequency□(f )S Amplitude□(dB) /c4550 /c45100 /c45150 /c45200 f =□48kHz Overall□Frequency□Response S Normalized□Frequency□(f )S Amplitude□(dB) /c45100 /c45150 /c4550 0.8 0.9 Normalized□Frequency□(f )S Amplitude□(dB/10,000) /c451 /c452 /c454 0.40 0.45 /c453 f =□48kHz Passband□Ripple□Detail S PCM4220 SBAS407C DECEMBER 2006 REVISED AUGUST 2009 www.ti.com TYPICAL CHARACTERISTICS (continued) At T A +25 VCC1 VCC2 +4.0V, and VDD +3.3V, unless otherwise noted. FREQUENCY RESPONSE FREQUENCY RESPONSE (Up to 20kHz) (Up to 40kHz) Figure 21. Figure 22. FREQUENCY RESPONSE DIGITAL DECIMATION FILTER, CLASSIC RESPONSE (Up to 80kHz) Overall Frequency Response Figure 23. Figure 24. DIGITAL DECIMATION FILTER, CLASSIC RESPONSE DIGITAL DECIMATION FILTER, CLASSIC RESPONSE Stop Band Detail Passband Ripple Detail Figure 25. Figure 26. Submit Documentation Feedback Copyright 2006 2009, Texas Instruments Incorporated Product Folder Link(s): PCM4220

Normalized□Frequency□(f )S Amplitude□(dB) /c453 /c454 /c456 /c452 /c451 0.49 0.50 /c455 f =□48kHz Transition□Band□Detail S Normalized□Frequency□(f )S Amplitude□(dB) /c45150 /c45200 /c45100 /c4550 3.0 3.5 f =□48kHz□(fast□mode) Overall□Frequency□Response S Normalized□Frequency□(f )S Amplitude□(dB) /c4510 /c4550 /c4560 /c4570 /c4580 /c4590 /c45100 /c4540 /c4530 /c4520 0.7 0.8 0.9 f =□48kHz□(fast□mode) Stop□Band□Detail S Normalized□Frequency□(f )S Amplitude□(dB/1000) 2.0 1.5 0.5 /c450.5 /c451.0 /c451.5 /c452.0 1.0 0.30 0.35 0.40 f =□48kHz□(fast□mode) Passband□Ripple□Detail S PCM4220 www.ti.com SBAS407C DECEMBER 2006 REVISED AUGUST 2009 TYPICAL CHARACTERISTICS (continued) At T A +25 VCC1 VCC2 +4.0V, and VDD +3.3V, unless otherwise noted. DIGITAL DECIMATION FILTER, LOW GROUP DELAY DIGITAL DECIMATION FILTER, CLASSIC RESPONSE RESPONSE Transition Band Detail Overall Frequency Response Figure 27. Figure 28. DIGITAL DECIMATION FILTER, LOW GROUP DELAY DIGITAL DECIMATION FILTER, LOW GROUP DELAY RESPONSE RESPONSE Stop Band Detail Passband Ripple Detail Figure 29. Figure 30. Copyright 2006 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM4220

Normalized□Frequency□(f )S Amplitude□(dB) /c450.5 /c451.5 /c452.0 /c452.5 /c453.0 /c454.0 /c451.0 0.50 0.55 /c453.5 f =□48kHz□(fast□mode) Transition□Band□Detail S Normalized□Frequency□(f )S/1000 Amplitude□(dB) 0.6 0.4 /c450.2 /c450.4 /c450.6 /c450.8 0.2 2.5 3.0 3.5 High-Pass□Filter Passband Normalized□Frequency□(f )S/1000 Amplitude□(dB) /c4540 /c4560 /c4580 /c45100 /c45140 0.100 0.15 0.300.05 /c4520 0.20 0.25 /c45120 High-Pass□Filter Stop□Band PCM4220 SBAS407C DECEMBER 2006 REVISED AUGUST 2009 www.ti.com TYPICAL CHARACTERISTICS (continued) At T A +25 VCC1 VCC2 +4.0V, and VDD +3.3V, unless otherwise noted. DIGITAL DECIMATION FILTER, LOW GROUP DELAY RESPONSE DIGITAL HIGH-PASS FILTER Transition Band Detail Passband Response Figure 31. Figure 32. DIGITAL HIGH-PASS FILTER Stop Band Response Figure 33. Submit Documentation Feedback Copyright 2006 2009, Texas Instruments Incorporated Product Folder Link(s): PCM4220

Master□Clock and□Timing VINL+ VCOML REFGNDL VREFL S/M FMT0 FMT1 OWL0 OWL1 SUB0 SUB1 PCMEN FS0 FS1 OVFL OVFR VCC1VCC2 AGND AGND AGND AGND AGND AGNDDGNDDGND VDD RST LRCK BCK DATA DF HPFDL HPFDR VREFR MCKI REFGNDR VCOMR VINL/c45 VINR+ VINR/c45 DGNDDGNDDGNDDGND PCM4220 www.ti.com SBAS407C DECEMBER 2006 REVISED AUGUST 2009 The PCM4220 is a two-channel, multi-bit delta-sigma Δ Σ A/D converter. The 6-bit output from the delta-sigma modulators is routed to the digital decimation filter, where the output of the filter provides linear PCM data. The linear PCM data are output at the audio serial port interface for connection to external processing and logic circuitry. Figure shows a simplified functional block diagram for the PCM4220, highlighting the interconnections between the various functional blocks. Figure 34. Functional Block Diagram Copyright 2006 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM4220

2.8V Full-ScalePP 2.8V Full-ScalePP VINL+ or VINR+ VINL/c45 or VINR/c45 +1.95V +1.95V VOLTAGE REFERENCE PCM4220 SBAS407C DECEMBER 2006 REVISED AUGUST 2009 www.ti.com The PCM4220 includes two analog inputs, referred to as the left and right channels. Each channel includes a pair of differential voltage input pins. The left channel inputs are named VINL (pin 10) and VINL+ (pin 11), respectively. The right channel inputs are named VINR (pin and VINR+ (pin 3), respectively. Each pin of an input pair has a nominal full-scale input of 2.8V PP The full-scale input for a given pair is specified as 5.6V PP differential in the Electrical Characteristics table. Figure shows the full-scale input range of the PCM4220, with the input signals centered on the nominal common-mode voltage of +1.95V. In a typical application, the front end is driven by a buffer amplifier or microphone/line level preamplifier. Examples are given in the Input Buffer Circuits section of this datasheet. The analog inputs of the PCM4220 may be driven up to the absolute maximum input rating without instability. If the analog input voltage is expected to exceed the absolute maximum input ratings in a given application, it is recommended that input clamping or limiting be added to the analog input circuitry prior to the PCM4220 in order to provide protection against damaging the device. Specifications for the analog inputs are given in the Electrical Characteristics and Absolute Maximum Ratings tables of this data sheet. Figure 35. Full-Scale Analog Input Range The PCM4220 includes an on-chip, band-gap voltage reference. The band-gap output voltage is buffered and then routed to the two delta-sigma modulators. The inclusion of an on-chip reference circuit enhances the power-supply noise rejection of the PCM4220. The buffered reference voltage for each channel is filtered using external capacitors. The capacitors are connected between VREFL (pin 15) and REFGNDL (pin 14) for the left channel, and VREFR (pin 46) and REFGNDR (pin 47) for the right channel. Figure illustrates the recommend reference decoupling capacitor values and connection scheme. The 10nF to 100nF capacitors in Figure may be metal film or X7R/C0G ceramic chip capacitors. The 100 µ F capacitors may be polymer tantalum chip (Kemet T520 series or equivalent) or aluminum electrolytic. The VREFL and VREFR pins are not designed for biasing external input circuitry. Two common-mode voltage outputs are provided for this purpose, and are discussed in the following section. Submit Documentation Feedback Copyright 2006 2009, Texas Instruments Incorporated Product Folder Link(s): PCM4220

Precision,□Low-Noise□Op□Amp (OPA227 or□equivalent) T o Bias□Nodes R (Optional) Direct□Connect□to High-Z□Bias□Node (Z >□10M )/c87L 100nF□to□1/c109F Close□to□IC□pins PCM4220 www.ti.com SBAS407C DECEMBER 2006 REVISED AUGUST 2009 Figure 36. Recommended Reference Capacitor Connections and Values The PCM4220 includes two dc common-mode voltage outputs, VCOML (pin 13) and VCOMR (pin 48), which correspond to the left and right input channels, respectively. The common-mode voltage is utilized to bias internal op amps within the modulator section of the PCM4220, and may be used to bias external input circuitry when proper design guidelines are followed. The common-mode voltages are derived from the VCC1 and VCC2 analog power supplies using internal voltage dividers. The voltage divider outputs are buffered and then routed to internal circuitry and the VCOML and VCOMR outputs. The common-mode output voltage is nominally equal to (0.4875 VCC1) for VCOMR and (0.4875 VCC2) for VCOML. Given an analog supply voltage of +4.0V connected to both VCC1 and VCC2, the resulting common-mode voltages are +1.95V. The common-mode voltage outputs have limited drive capability. If multiple bias points are to be driven, or the external bias nodes are not sufficiently high impedance, an external output buffer is recommended. Figure shows a typical buffer configuration using the OPA227 The op amp utilized in the buffer circuit should exhibit low dc offset and drift characteristics, as well as low output noise. Figure 37. Common-Mode Output Connections Copyright 2006 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM4220

40ns□minimum RST Internal Reset MCKI 1024□System□CLock□Periods Required□for□Initialization DISABLED STATES FOR THE PCM4220 AUDIO SERIAL PORT PCM4220 SBAS407C DECEMBER 2006 REVISED AUGUST 2009 www.ti.com The PCM4220 requires a master clock for operating the internal logic and modulator circuitry. The master clock is supplied from an external source, connected at the MCKI input (pin 35). Table summarizes the requirements for various operating modes of the PCM4220. Referring to Table the term f S refers to the PCM4220 PCM output sampling rate (that is, 48kHz, 96kHz, 192kHz, etc.). Refer to the Electrical Characteristics table for timing specifications related to the master clock input. For best performance, the master clock jitter should be maintained below 40ps peak amplitude. Table Master Clock Requirements OPERATING MODE REQUIRED MASTER CLOCK (MCKI) RATE PCM Normal 256f S PCM Double Speed 128f S PCM Quad Speed 64f S The PCM4220 includes an external reset input, RST (pin 36), which may be utilized to force an internal reset initialization or power-down sequence. The reset input is active low. Figure shows the required timing for an external forced reset. A power-down state for the PCM422 may be initiated by forcing and holding the reset input low for the duration of the desired power-down condition. Minimum power is consumed during this state when all clock inputs for the PCM4220 are forced low. Before releasing the reset input by forcing a high state, the master clock should be enabled so that the PCM4220 can execute a reset initialization sequence. While the RST pin is forced low, or during reset initialization, the audio serial port data and clock outputs are driven low. Figure 38. External Reset Sequence When PCMEN (pin 16) is driven low, the PCM output is disabled. The audio serial port data and clocks are driven low. Submit Documentation Feedback Copyright 2006 2009, Texas Instruments Incorporated Product Folder Link(s): PCM4220

www.ti.com SBAS407C DECEMBER 2006 REVISED AUGUST 2009 The PCM4220 supports 24-bit linear PCM output data when the PCMEN input (pin 16) is forced high. The PCM output is disabled when PCMEN is forced low. The 24-bit output data may be dithered to 20-, 18-, or 16-bits using internal word length reduction circuitry. Refer to the Output Word Length Reduction section of this data sheet for additional information. The PCM4220 supports three PCM sampling modes, referred to as Normal, Double Speed, and Quad Speed. The sampling mode is determined by the state of the FS0 and FS1 inputs (pins and 20, respectively). Table summarizes the sampling modes available for the PCM4220. Normal sampling mode supports output sampling rates from 8kHz to 54kHz. The Δ Σ modulator operates with 128x oversampling in this mode. Both the Classic and Low Group Delay decimation filter responses are available in Normal mode. The master clock (MCKI) rate must be 256x the desired output sampling rate for Normal operation. The Double Speed sampling mode supports output sampling rates from 54kHz to 108kHz. The delta-sigma modulator operates with 64x oversampling in this mode. Both the Classic and Low Group Delay decimation filter responses are available in Double Speed mode. The master clock (MCKI) rate must be 128x the desired output sampling rate for Double Speed operation. Quad Speed sampling mode supports output sampling rates from 108kHz to 216kHz. The delta-sigma modulator operates with 32x oversampling in this mode. Only the Low Group Delay decimation filter response is available in Quad Speed mode. The master clock (MCKI) rate must be 64x the desired output sampling rate for Quad Speed operation. Table PCM Sampling Mode Configuration FS1 (pin 20) FS0 (pin 19) SAMPLING MODE LO LO Normal, 8kHz f S 54kHz LO HI Double Speed, 54kHz f S 108kHz HI LO Quad Speed, 108kHz f S 216kHz HI HI Reserved The PCM output mode supports a three-wire synchronous serial interface. This interface includes a serial data output (DATA, pin 32), a serial bit or data clock (BCK, pin 33), and a left/right word clock (LRCK, pin 34). The BCK and LRCK clock pins may be inputs or outputs, depending on the Slave or Master mode configuration. Figure illustrates Slave and Master mode serial port connections to an external audio signal processor or host device. The audio serial port supports four data formats that are illustrated in Figure Figure and Figure The I S and Left-Justified formats support two channels of audio output data. The TDM data formats can support up to eight channels of audio output data on a single data line. The audio data format is selected using the FMT0 and FMT1 inputs (pins and 43, respectively). Table summarizes the audio data format options. For all formats, audio data are represented as two s complement binary data, with the MSB transmitted first. Regardless of the format selection, audio data are always clocked out of the port on the falling edge of the BCK clock. Table PCM Audio Data Format Selection FMT1 (pin 43) FMT0 (pin 44) AUDIO DATA FORMAT LO LO Left-Justified LO HI I S HI LO TDM HI HI TDM with data delayed one BCK cycle from LRCK rising edge The LRCK clock rate should always be operated at the desired output sampling rate, or f S In Slave mode, the LRCK clock is an input, with the rate set by an external audio bus master (that is, a clock generator, digital signal processor, etc.). In Master mode, the LRCK clock is an output, derived from the master clock input using on-chip clock dividers (as is the BCK clock). The clock divider is configured using the FS0 and FS1 pins, which are discussed in the PCM Output and Sampling Modes section of this datasheet. Copyright 2006 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM4220

Audio□DSP or Interface Audio□DSP or Interface BCK DATA LRCK BCK DATA MCKI MCLK MCKI MCLK Master Clock Master Clock (a)□Slave□Mode□(S/M□=□HI) (b)□Master□Mode□(S/M□=□LO) FSYNC SCLK DATA FSYNC SCLK DATA PCM4220 SBAS407C DECEMBER 2006 REVISED AUGUST 2009 www.ti.com For the I S and Left-Justified data formats, the BCK clock output rate is fixed in Master mode, with the Normal mode being 128f S and the Double and Quad Speed modes being 64f S In Slave Mode, a BCK clock input rate of 64f S or 128f S is recommended for Normal mode, while 64f S is recommended for Double and Quad Rate modes. For the TDM data formats, the BCK rate depends upon the sampling mode for either Slave or Master operation. For Normal sampling, the BCK must be 256f S Double Speed mode requires 128f S while Quad Speed mode requires 64f S This requirement limits the maximum number of channels carried by the TDM formats to eight for Normal mode, four for Double Rate mode, and two for Quad Rate mode. When using the TDM formats, the sub-frame assignment for the device must be selected using the SUB0 and SUB1 inputs (pins and 25, respectively). Table summarizes the sub-frame selection options. A sub-frame contains two 32-bit time slots, with each time slot carrying bits of audio data corresponding to either the left or right channel of the PCM4220. Refer to Figure through Figure for TDM interfacing connections and sub-frame formatting details. For the TDM format with one BCK delay, the serial data output is delayed by one BCK period after the rising edge of the LRCK clock. Table TDM Sub-frame Assignment SUB1 (pin 25) SUB0 (pin 26) SUB-FRAME ASSIGNMENT LO LO Sub-frame LO HI Sub-frame HI LO Sub-frame HI HI Sub-frame When using TDM formats with Double Speed sampling, it is recommended that the SUB1 pin be forced low. When using TDM formats with Quad Speed sampling, it is recommended that both the SUB0 and SUB1 pins be forced low. For all serial port modes and data formats, when driving capacitive loads greater than 30pF with the data and clock outputs, it is recommended that external buffers be utilized to ensure data and clock integrity at the receiving device(s). For specifications regarding audio serial port operation, the reader is referred to the Electrical Characteristics Audio Interface Timing table, as well as Figure and Figure in this data sheet. Figure 39. Slave and Master Mode Operation Submit Documentation Feedback Copyright 2006 2009, Texas Instruments Incorporated Product Folder Link(s): PCM4220

Left□Channel (a)□Left-Justified□Data□Format Right□Channel LRCK BCK DATA DATA MSB LSB LSBMSB (b)□I S□Data□Format 1/fS LRCK BCK MSB LSB MSB LSB LRCK BCK DATA LRCK BCK DATA LRCK BCK LRCK BCK LRCK BCK LRCK BCK LRCK BCK LRCK BCK LRCK BCK LRCK BCK DATA DATA DATA DATA DATA DATA DATA DATA SUB0 SUB1 SUB0 SUB1 SUB0 SUB1 SUB0 SUB1 SUB0 SUB1 SUB0 SUB1 SUB0 SUB1 SUB0 SUB1 (sub-frame 0) Slave PCM4220 (sub-frame 1) Slave PCM4220 (sub-frame 2) Slave PCM4220 (sub-frame 3) Slave PCM4220 (sub-frame 0) Master PCM4220 (sub-frame 1) Slave PCM4220 (sub-frame 2) Slave PCM4220 (sub-frame 3) Slave LO LO HI LO LO HI HI HI LO LO HI LO LO HI LRCK BCK DATA LRCK BCK DATA LRCK BCK LRCK BCK LRCK BCK LRCK BCK LRCK BCK LRCK BCK LRCK BCK LRCK BCK DATA DATA DATA DATA DATA DATA DATA DATA SUB0 SUB1 SUB0 SUB1 SUB0 SUB1 SUB0 SUB1 SUB0 SUB1 SUB0 SUB1 SUB0 SUB1 SUB0 SUB1 PCM4220 (sub-frame 0) Slave (sub-frame 1) Slave (sub-frame 2) Slave (sub-frame 3) Slave (sub-frame 0) Master (sub-frame 1) Slave (sub-frame 2) Slave (sub-frame 3) Slave LO LO HI LO LO HI HI HI HI HI HI HI LO LO HI LO LO HI (a)□All□devices□are□Slaves. (b)□One□device□is□the□Master□while□all□other□devices□are□Slaves. PCM4220 www.ti.com SBAS407C DECEMBER 2006 REVISED AUGUST 2009 Figure 40. Left-Justified and I S Data Formats Figure 41. TDM Mode Interface Connections (PCM Normal Mode Shown) Copyright 2006 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM4220

Normal□Mode LRCK L Sub-frame□0 Sub-frame□1 One□Frame,□1/fS Sub-frame□2 Sub-frame□3 R L R L R L R L Sub-frame□0 Sub-frame□1 One□Frame,□1/fS One□Frame,□1/fS Sub-frame□0 Sub-frame□1 R L R L R L R L One□Frame One□Frame 1/fS 1/fS 1/fS 1/fS One□Frame One□Frame R L R L R L R DATA LRCK DATA LRCK DATA Double□Speed□Mode Quad□Speed□Mode Normal□Mode LRCK L Sub-frame□0 Sub-frame□1 One□Frame,□1/fS Sub-frame□2 Sub-frame□3 R L R L R L R L Sub-frame□0 Sub-frame□1 One□Frame,□1/fS One□Frame,□1/fS Sub-frame□0 Sub-frame□1 R L R L R L R L One□Frame One□Frame 1/fS 1/fS 1/fS 1/fS One□Frame One□Frame R L R L R L R DATA LRCK DATA LRCK DATA Double□Speed□Mode Quad□Speed□Mode DIGITAL DECIMATION FILTER PCM4220 SBAS407C DECEMBER 2006 REVISED AUGUST 2009 www.ti.com NOTE: Each L or R channel time slot is bits long, with 24-bit data Left-Justified in the time slot. Audio data is MSB first. Sub-frame assignments for each PCM4220 device are selected by the corresponding SUB0 and SUB1 pin settings. Figure 42. TDM Data Formats: Slave Mode NOTE: Each L or R channel time slot is bits long, with 24-bit data Left-Justified in the time slot. Audio data is MSB first. Sub-frame assignments for each PCM4220 device are selected by the corresponding SUB0 and SUB1 pin settings. Figure 43. TDM Data Formats: Master Mode The PCM4220 digital decimation filter is a linear phase, multistage finite impulse response (FIR) design with two user-selectable filter responses. The decimation filter provides the digital downsampling and low-pass anti-alias filter functions for the PCM4220. The Classic filter response is typical of traditional audio data converters, with Figure through Figure detailing the frequency response, and the related specifications given in the Electrical Characteristics table. The group delay for the Classic filter is 39/f S or 812.5 µ s for f S 48kHz and 406.25 µ s for f S 96kHz. The Classic filter response is not available for the Quad Speed sampling mode. Submit Documentation Feedback Copyright 2006 2009, Texas Instruments Incorporated Product Folder Link(s): PCM4220

www.ti.com SBAS407C DECEMBER 2006 REVISED AUGUST 2009 The Low Group Delay response provides a lower latency option for the decimation filter, and is detailed in Figure through Figure with the relevant specifications given in the Electrical Characteristics table. The Low Group Delay filter response is available for all sampling modes. The group delay for this filter is 21/f S or 437.5 µ s for f S 48kHz, 218.75 µ s for f S 96kHz, and 109.375 µ s for f S 192kHz. The decimation filter response is selected using the DF input (pin 21), with the settings summarized in Table For Quad Speed sampling mode operation, the Low Group Delay filter is always selected, regardless of the DF pin setting. Table Decimation Filter Response Selection DF (pin 21) DECIMATION FILTER RESPONSE LO Classic response, with group delay 39/f S HI Low Group Delay response, with group delay 21/f S The PCM4220 incorporates digital high-pass filters for both the left and right audio channels, with the purpose of removing the Δ Σ modulator dc offset from the audio output data. Figure and Figure detail the frequency response for the digital high-pass filter. The f 3dB frequency is approximately f S /48000, where f S is the PCM output sampling rate. Two inputs, HPFDR (pin 17) and HPFDL (pin 18), allow the digital high-pass filter to be enabled or disabled individually for the right and left channels, respectively. Table summarizes the operation of the high-pass filter disable pins. Table Digital High-Pass Filter Configuration HPFDR (pin 17) or HPFDL (pin 18) HIGH-PASS FILTER STATE LO Enabled for the corresponding channel HI Disabled for the corresponding channel The PCM4220 is typically configured to output 24-bit linear PCM audio data. However, internal word length reduction circuitry may be utilized to reduce the 24-bit data to 20-, 18-, or 16-bit data. This reduction is accomplished by using a Triangular PDF dithering function. The OWL0 (pin 42) and OWL1 (pin 41) inputs are utilized to select the output data word length. Table summarizes the output word length configuration options. Table PCM Audio Data Word Length Selection OWL1 (pin 41) OWL0 (pin 42) OUTPUT WORD LENGTH LO LO bits LO HI bits HI LO bits HI HI bits The PCM4220 includes two active-high digital overflow outputs, OVFL (pin 37) and OVFR (pin 38), corresponding to the left and right channels, respectively. These outputs are functional when the PCM output mode is enabled, as the overflow detection circuitry is incorporated into the digital filter engine. The overflow indicators are forced high whenever a digital overflow is detected for a given channel. The overflow indicators may be utilized as clipping flags, and monitored using a host processor or light-emitting diode (LED) indicators. When driving a LED, the overflow output may be buffered to ensure adequate drive for the LED. A recommended buffer is Texas Instruments' SN74LVC1G125 Equivalent buffers may be substituted Copyright 2006 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM4220

100nF□to□1 F/c109 Left□Channel Analog□Input +4.0V 100nF

100 F/c109

From□Host,□Logic, or□Manual□Controls AGND VCOML REFGNDL VREFL PCMEN HPFDR HPFDL FS0 FS1 DF DGND DGND DGND Right□Channel Analog□Input VCOMR REFGNDR VREFR DGND FMT0 FMT1 OWL0 OWL1 DGND S/M OVFR From□Host,□Logic, or□Manual□Controls T o□Host□and/or□Clipping□Indicators From□Host□or□Master□Reset From□Audio□Master□Clock□Source Audio DSP□or□Host OVFL RST MCKI LRCK BCK DATA VDD DGND NC NC NC SUB0 SUB1 100nF +3.3V 100nF□to□1 F/c109 Required□only□for□TDM□data□formats. These□pins□are□ignored□for□all□other□formats. INPUT BUFFER CIRCUITS PCM4220 SBAS407C DECEMBER 2006 REVISED AUGUST 2009 www.ti.com Figure provides a typical connection diagram for the PCM4220. Recommended power-supply bypass and reference filter capacitors are shown. These components should be located as close to the corresponding PCM4220 package pins as physically possible. Larger power-supply bypass capacitors may be placed on the bottom side of the printed circuit board (PCB). However, reference decoupling capacitors should be located on the top side of the PCB to avoid issues with added via inductance. As Figure illustrates, the audio host device may be a digital signal processor (DSP), digital audio interface transmitter (DIT), or a programmable logic device. Figure 44. Typical Connections for PCM and DSD Output Modes The PCM4220 is typically preceded in an application by an input buffer or preamplifier circuit. The input circuit is required to perform anti-aliasing filtering, in addition to application-specific analog gain scaling, limiting, or processing that may be needed. At a minimum, first-order, low-pass anti-aliasing filtering is necessary. The input buffer must be able to perform the input filtering requirement, in addition to driving the switched-capacitor inputs of the PCM4220 device. The buffer must have adequate bandwidth, slew rate, settling time, and output drive capability to perform these tasks. Figure illustrates the input buffer/filter circuit utilized on the PCM4222EVM evaluation module where the PCM4222 analog input section is identical to the PCM4220. This circuit has been optimized for measurement purposes, so that it does not degrade the dynamic characteristics of the PCM4220. The resistors are primarily 0.1% metal film. The 40.2 Ω resistor is tolerance thick film. The 1nF and 2.7nF capacitors may be either PPS Submit Documentation Feedback Copyright 2006 2009, Texas Instruments Incorporated Product Folder Link(s): PCM4220

560 (0.1%)/c87 G R T S 40.2 (1%)/c87 40.2 (1%)/c87 270 (0.1%)/c87 270 (0.1%)/c87 OPA1632DGN Analog□Input Full-Scale:□11.76V DifferentialPP T ypical□with□R =□40/c87S 1nF 1nF 560 (0.1%)/c87 Ground Lift□Switch 2.7nF 10nF 100nF/c45 /c45 15V EN VOCM VINL or□VINR/c45 /c45 VINL or□VINR+/c43 From Buffered□V COM 10nF 100nF/c45 +15V 100nF PCM4220 www.ti.com SBAS407C DECEMBER 2006 REVISED AUGUST 2009 film or C0G ceramic capacitors; both types perform with equivalent results in this application. Surface-mount devices are utilized throughout because they provide superior performance when combined with a wideband amplifier such as the OPA1632 The DGN package version of the OPA1632 is utilized; this package includes a thermal pad on the bottom side. The thermal pad must be soldered to the PCB ground plane for heat sink and mechanical support purposes. Figure 45. Differential Input Buffer Circuit Utilizing the OPA1632 Figure demonstrates the same circuit topology of Figure while using standard single or dual op amps. The noise level of this circuit is adequate for obtaining the typical A-weighted dynamic range performance for the PCM4220. However, unweighted performance may suffer, depending upon the op amp noise specifications. Near-typical THD+N can be achieved with this configuration, although this performance also depends on the op amps used for the application. The NE5534A and OPA227 (the lower cost 'A' version) are good candidates from a noise and distortion perspective, and are reasonably priced. More expensive lower-noise models, such as the OPA211 should also work well for this configuration. Feedback and input resistor values may be changed to alter circuit gain. However, it is recommended that all circuit changes be simulated and then tested on the bench using a working prototype to verify performance. Figure illustrates a differential input circuit that employs a noninverting architecture. The total noise and distortion is expected to be higher than that measured for Figure and Figure As with Figure the NE5534A and OPA227 are good candidates for this circuit, although similar op amps should yield equivalent results. A useful tool for simulating the circuits shown here is TINA-TI a free schematic capture and SPICE-based simulator program available from the Texas Instruments web site This tool includes macro models for many TI and Burr-Brown branded amplifiers and analog integrated circuits. TINA-TI runs on personal computers using Microsoft Windows operating systems (Windows 2000 or newer). Copyright 2006 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM4220

40.2/c87 40.2/c87 270/c87 270/c87 1nF 1nF 100nF VINL or□VINR/c45 /c45 VINL or□VINR+/c43 560/c87C2 U2 2.7nF VCOML or VCOMR INPUT+ INPUT/c45 U1,□U2□=□NE5534A,□OPA227,□or□similar R /c871 10k/c87 10k/c87 40.2/c87 40.2/c87 1.5k/c87 1.5k/c87 1nF 1nF VINL /c43/c43 or□VINR VINL /c45/c45 or□VINR R /c872C2 2.7nF INPUT+ INPUT/c45 VCOML or VCOMR U1,□U2□=□NE5534A,□OPA227,□or□similar. U3□=□OPA227□or□equivalent. PCM4220 SBAS407C DECEMBER 2006 REVISED AUGUST 2009 www.ti.com NOTE: C and C provide ac coupling. They may be removed if the dc offset from the circuit is negligible. Figure 46. Alternative Buffer Circuit Using Standard Op Amps NOTE: R and R are optional. When used, values may be selected for the desired attenuation. NOTE: C and C provide ac coupling. They may be removed if the dc offset from the circuit is negligible. Figure 47. Noninverting Differential Input Buffer Utilizing Standard Op Amps Submit Documentation Feedback Copyright 2006 2009, Texas Instruments Incorporated Product Folder Link(s): PCM4220

(AES3, IEC60958-3, and S/PDIF) PCM4220 Divided□by□2 FS1 LO LO HI HI FS0 LO HI LO HI Mode Normal Double□Speed Quad□Speed Reserved MCKI BCK LRCK FS1 FS0 MCLK CLK0 CLK1 512f (Normal) S 256f (Double□Speed)S 128f (Quad□Speed)S DIT4192 Master Clock DATA S/M SCLK SYNC SDATA M/S LO□= ADC□Master HI□= ADC□Slave CLK1 LO LO HI HI CLK0 LO HI LO HI Mode Quad□Speed Double□Speed Reserved Normal PCM4220 www.ti.com SBAS407C DECEMBER 2006 REVISED AUGUST 2009 The serial output of audio analog-to-digital converters is oftentimes interfaced to transmitter devices that encode the serial output data to either the AES3 or IEC60958-3 (or S/PDIF) interface formats. Texas Instruments manufactures several devices that perform this encoding, including the DIT4192 DIX4192 SRC4382 and SRC4392 This section describes and illustrates the audio serial port interface connections required for communications between the PCM4220 and these devices. Register programming details for the DIX4192 and SRC4382/4392 are also provided. Figure shows the interface between a PCM4220 and a DIT4192 transmitter. This configuration supports sampling frequencies and encoded frame rates from 8kHz to 216kHz. For this example, the audio data format must be either Left-Justified or I TDM formats are not supported by the DIT4192. In addition, the PCM4220 VDD supply and DIT4192 VIO supply must be the same voltage, to ensure logic level compatibility. Figure illustrates the audio serial port interface between the PCM4220 and either a DIX4192 transceiver or SRC4382/SRC4392 combo sample rate converter/transceiver device. Port A of the DIX4192 or SRC4382/SRC4392 is utilized for this example. Data acquired by Port A are sent on to the DIT function block within the interface device for AES3 encoding and transmission. The DIX4192 and SRC4382/SRC4392 are software-configurable, with control register and data buffer settings that determine the operation of internal function blocks. Table and Table summarize the control register settings for the Port A and the DIT function blocks for both A/D Converter Master and Slave modes, respectively. Input sampling and encoded frame rates from 8kHz to 216kHz are supported with the appropriate register settings. Figure 48. Interfacing the PCM4220 to a DIT4192 Copyright 2006 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM4220

Divided□by□2 MCKI BCK LRCK DIX4192 or SRC4392 512f (Normal)S 256f (Double□Speed)S 128f (Quad□Speed)S Master Clock MCLK DATA BCKA LRCKA SDINA PCM4220 SBAS407C DECEMBER 2006 REVISED AUGUST 2009 www.ti.com NOTE: VDDPCM4220 VIODIX4192 or SRC4392. Audio data format if I S or Left Justified. Interface supports ADC Slave or Master configurations, depending on DIX4192, SRC4382, or SRC4392 register setup. Figure 49. Interfacing the PCM4220 to a DIX4192 SRC4382 or SRC4392 Table Register Configuration Sequence for an ADC Master Mode Interface REGISTER ADDRESS (hex) REGISTER DATA (hex) COMMENTS Select Register Page Port A is Slave mode with Left-Justified audio data format, or Port A is Slave mode with I S Data format Default for Port A Slave mode operation Divide MCLK by 512 for Normal sampling, or Divide MCLK by 256 for Double Speed Sampling, or Divide MCLK by 128 for Quad Speed sampling Line Driver and AESOUT buffer enabled Data buffers on Register Page are the source for the DIT channel status (C) and user (U) data Power up Port A and the DIT Table Register Configuration Sequence for an ADC Slave Mode Interface REGISTER ADDRESS (hex) REGISTER DATA (hex) COMMENTS Select Register Page Port A is Master mode with Left-Justified audio data format, or Port A is Master mode with I S Data format Divide MCLK by 512 for Normal sampling, or Divide MCLK by 256 for Double Speed sampling, or Divide MCLK by 128 for Quad Speed sampling Divide MCLK by 512 for Normal sampling, or Divide MCLK by 256 for Double Speed Sampling, or Divide MCLK by 128 for Quad Speed sampling Line Driver and AESOUT buffer enabled Data buffers on Register Page are the source for the DIT channel status (C) and user (U) data Power up Port A and the DIT Submit Documentation Feedback Copyright 2006 2009, Texas Instruments Incorporated Product Folder Link(s): PCM4220

www.ti.com SBAS407C DECEMBER 2006 REVISED AUGUST 2009 The DIT channel status (C) and user (U) data bits in register page may be programmed after the DIT block has powered up. To program these bits, disable buffer transfers by setting the BTD bit in control register 0x08 to '1'. Then, select register page using register address 0x7F. You can now load the necessary C and U data registers for the intended application by writing the corresponding data buffer addresses. When you have finished writing the C and U data, select register page using register address 0x7F. Re-enable buffer transfers by setting the BTD bit in control register 0x08 to '0'. Copyright 2006 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM4220

www.ti.com Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (October 2007) to Revision C Page Corrected statement concerning direction to drive PCMEN (pin 16) to disable PCM output Changes from Revision A (May 2007) to Revision B Page Changed Figure y-axis value from (dB) to (db/10,000) Changed Figure y-axis value from (dB) to (db/1000) Submit Documentation Feedback Copyright 2006 2009, Texas Instruments Incorporated Product Folder Link(s): PCM4220

www.ti.com 24-Apr-2015 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PCM4220PFB ACTIVE TQFP PFB 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 PCM4220 PCM4220PFBG4 ACTIVE TQFP PFB 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 PCM4220 PCM4220PFBR ACTIVE TQFP PFB 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 PCM4220 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

www.ti.com 24-Apr-2015 Addendum-Page 2 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCM4220PFBR TQFP PFB 48 1000 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 2

MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 4073176/B 10/96 Gage Plane 0,13 NOM 0,25 0,45 0,75 Seating Plane 0,05 MIN 0,17 0,27 SQ 7,20 6,80 5,50 TYP SQ8,80 9,20 1,05 0,95 1,20 MAX 0,08 0,50 M0,08 0°–7° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026

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Summary

High-Performance, Two-Channel, 24-Bit, 216kHz Sampling Multi-Bit Delta-Sigma Analog-to-Digital Converter REVISED AUGUST 2009

Description

High-Performance, Two-Channel, 24-Bit, 216kHz Sampling Multi-Bit Delta-Sigma Analog-to-Digital Converter REVISED AUGUST 2009

Source title PCM4220PFB Datasheet(PDF) - Texas Instruments

Read PCM4220PFB online.