PCM4104PFBR

PCM4104 TI | Alldatasheet

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Technical content

SBAS291C − AUGUST 2003 − REVISED DECEMBER 2004 /C0072/C0105/C0103/C0104/C0262/C0080/C0101/C0114/C0102/C0111/C0114/C0109/C0097/C0110/C0099/C0101/C0044 /C0050/C0052/C0262/C0066/C0105/C0116/C0044 /C0050/C0049/C0054/C0107/C0072/C0122 /C0083/C0097/C0109/C0112/C0108/C0105/C0110/C0103/C0044 /C0070/C0111/C0117/C0114/C0262/C0067/C0104/C0097/C0110/C0110/C0101/C0108 /C0065/C0117/C0100/C0105/C0111 /C0068/C0105/C0103/C0105/C0116/C0097/C0108/C0262/C0116/C0111/C0262/C0065/C0110/C0097/C0108/C0111/C0103/C0032/C0067/C0111/C0110/C0118/C0101/C0114/C0116/C0101/C0114 /C0080/C0067/C0077/C0052/C0049/C0048/C0052

FEATURES

/C0068Four High-Performance, Multi-Level, Delta-Sigma Digital-to-Analog Converters /C0068Differential Voltage Outputs − Full-Scale Output (Differential): 6.15VPP /C0068Supports Sampling Frequencies up to 216kHz /C0068Typical Dynamic Performance (24-Bit Data) − Dynamic Range (A-Weighted): 118dB − THD+N: −100dB /C0068Linear Phase, 8x Oversampling Digital Interpolation Filter /C0068Digital De-Emphasis Filters for 32kHz, 44.1kHz, and 48kHz Sampling Rates /C0068Soft Mute Function − All-Channel Mute via the MUTE Input Pin − Per-Channel Mute Available in Software Mode /C0068Digital Attenuation (Software Mode Only) − Attenuation Range: 0dB to −119.5dB − 256 Steps with 0.5dB per Step /C0068Output Phase Inversion (Software Mode Only) /C0068Zero Data Mute (Software Mode Only) /C0068Audio Serial Port − Supports Left-Justified, Right-Justified, I 2S/C0069, and TDM Data Formats − Accepts 16-, 18-, 20, and 24-Bit Two’s Complement PCM Audio Data /C0068Standalone or Software-Controlled Configuration Modes /C0068Four-Wire Serial Peripheral Interface (SPI/C0069) Port Provides Control Register Access in Software Mode /C0068Power Supplies: +5V Analog, +3.3V Digital /C0068Power Dissipation − 203mW typical with fS = 48kHz − 220mW typical with fS = 96kHz − 236mW typical with fS = 192kHz /C0068Power-Down Modes /C0068Small 48-Lead TQFP Package

APPLICATIONS

/C0068Digital Mixing Consoles /C0068Digital Audio Workstations /C0068Digital Audio Effects Processors /C0068Broadcast Studio Equipment /C0068Surround-Sound Processors /C0068High-End A/V Receivers

DESCRIPTION

The PCM4104 is a high-performance, four-channel digital-to-analog (D/A) converter designed for use in professional audio applications. The PCM4104 supports 16- to 24-bit linear PCM input data, with sampling frequencies up to 216kHz. The PCM4104 features lower power consumption than most comparable stereo audio D/A converters, making it ideal for use in high channel count applications by lowering the overall power budget required for the D/A conversion sub-system. The PCM4104 features delta-sigma architecture, employing a high-performance multi-level modulator combined with a switched capacitor output filter. This architecture yields lower out-of-band noise and a high tolerance to system clock phase jitter. Differential voltage outputs are provided for each channel and are well-suited to high-performance audio applications. The differential outputs are easily converted to a single-ended output using an external op amp IC. The PCM4104 includes a flexible audio serial port interface, which supports standard and time division multiplexed (TDM) formats. Support for TDM formats simplifies interfacing to DSP serial ports, while supporting a cascade connection for two PCM4104 devices. In addition, the PCM4104 offers two configuration modes: Standalone and Software-Controlled. The Standalone mode provides dedicated control pins for configuring a subset of the available PCM4104 functions, while Software mode utilizes a serial peripheral interface (SPI) port for accessing the complete feature set via internal control registers. The PCM4104 operates from a +5V analog power supply and a +3.3V digital power supply. The digital I/O is compatible with +3.3V logic families. The PCM4104 is available in a TQFP-48 package. All trademarks are the property of their respective owners. www.ti.com Copyright  2003−2004, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046

/C0080/C0067/C0077/C0052/C0049/C0048/C0052 SBAS291C − AUGUST 2003 − REVISED DECEMBER 2004 www.ti.com ORDERING INFORMATION (1) PRODUCT PACKAGE−LEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY PCM4104 TQFP-48 PFB −10°C to +70°C PCM4104PFB PCM4104PFBT Tape and Reel, 250 PCM4104 TQFP-48 PFB −10°C to +70°C PCM4104PFB PCM4104PFBR Tape and Reel, 2000 (1)For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or refer to our web site at www.ti.com. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) PCM4104 UNIT Supply voltage VCC +6.0 V Supply voltage VDD +3.6 V Ground voltage difference Any AGND-to-AGND and AGND-to-DGND ±0.1 V Digital input voltage FS0, FS1, FMT0, FMT1, FMT2, CDOUT, CDIN, CCLK, CS, DATA0, DATA1, BCK, LRCK, SCKI, SUB, DEM0, DEM1, MUTE, RST , MODE −0.3 to (VDD + 0.3) V Input current (any pin except supplies) ±10 mA Operating temperature range −10 to +70 °C Storage temperature range, TSTG −65 to +150 °C (1)Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.

/C0080/C0067/C0077/C0052/C0049/C0048/C0052 SBAS291C − AUGUST 2003 − REVISED DECEMBER 2004 www.ti.com

ELECTRICAL CHARACTERISTICS

All parameters are specified at TA = +25°C with VCC = +5V, VDD = +3.3V, and a measurement bandwidth from 10Hz to 20kHz, unless otherwise noted. System clock frequency is equal to 256fS for Single and Dual Rate sampling modes, and 128fS for Quad Rate sampling mode. PCM4104 PARAMETER CONDITIONS MIN TYP MAX UNITS RESOLUTION 24 Bits DATA FORMAT Audio data formats Left or Right Justified, I2S, and TDM Audio data word length 16 24 Bits Binary data format Two’s Complement Binary, MSB First CLOCK RATES AND TIMING Single rate sampling mode 6.144 36.864 MHz System clock frequency fSCKI Dual rate sampling mode 13.824 36.864 MHzSystem clock frequency fSCKI Quad rate sampling mode 13.824 36.864 MHz Single rate sampling mode 24 54 kHz Sampling frequency fS Dual rate sampling mode 54 108 kHzSampling frequency fS Quad rate sampling mode 108 216 kHz SPI port data clock fCCLK 24 MHz SPI port data clock high time tCCLKH 15 ns SPI port data clock low time tCCLKL 15 ns DIGITAL INPUT/OUTPUT Input logic level VIH 2.0 V Input logic level VIL 0.8 V Input logic current IIH VIN = VDD 1 10 µA Input logic current IIL VIN = 0V 1 −10 µA Output logic level VOH IOH = −2mA 2.4 V Output logic level VOL IOH = +2mA 0.4 V ANALOG OUTPUTS Full-scale output voltage, differential R L = 600Ω 6.15 VPP Bipolar zero voltage 2.5 V Output impedance 5 Ohms Switched capacitor filter frequency responsef = 20kHz, all sampling modes −0.2 dB Gain error 0.5 % FSR Gain mismatch, channel-to-channel 0.6 % FSR Bipolar zero error 1 mV VCOM 1 and VCOM 2 output voltage VCC = +5V 2.5 V VCOM 1 and VCOM 2 output current 200 µA

/C0080/C0067/C0077/C0052/C0049/C0048/C0052 SBAS291C − AUGUST 2003 − REVISED DECEMBER 2004 www.ti.com ELECTRICAL CHARACTERISTICS (continued) All parameters are specified at TA = +25°C with VCC = +5V, VDD = +3.3V, and a measurement bandwidth from 10Hz to 20kHz, unless otherwise noted. System clock frequency is equal to 256fS for Single and Dual Rate sampling modes, and 128fS for Quad Rate sampling mode. PCM4104 PARAMETER UNITSMAXTYPMINCONDITIONS DYNAMIC PERFORMANCE WITH 24-BIT DATA (1) fS = 48kHz Total harmonic distortion + noiseTHD+N f = 1kHz at 0dBFS −100 −94 dB Total harmonic distortion + noiseTHD+N f = 1kHz at −60dBFS −56 dB Dynamic range, A-weighted f = 1kHz at −60dBFS 112 118 dB Idle channel SNR, A-weighted All zero input data 119 dB Idle channel SNR, unweighted All zero input data 116 dB Channel separation f = 1kHz at 0dBFS for active channel 100 110 dB fS = 96kHz Total harmonic distortion + noise THD+N f = 1kHz at 0dBFS, BW = 10Hz to 40kHz −100 dB Total harmonic distortion + noise THD+N f = 1kHz at −60dBFS, BW = 10Hz to 40kHz −53 dB Dynamic range, A-weighted f = 1kHz at −60dBFS 118 dB Idle channel SNR, A-weighted All zero input data 119 dB Idle channel SNR, unweighted All zero input data, BW = 10Hz to 40kHz 113 dB Channel separation f = 1kHz at 0dBFS for active channel 110 dB fs = 192kHz Total harmonic distortion + noiseTHD+N f = 1kHz at 0dBFS, BW = 10Hz to 40kHz −97 dB Total harmonic distortion + noiseTHD+N f = 1kHz at −60dBFS, BW = 10Hz to 40kHz −53 dB Dynamic range, A-weighted f = 1kHz at −60dBFS 118 dB Idle channel SNR, A-weighted All zero input data 118 dB Idle channel SNR, unweighted All zero input data, BW = 10Hz to 40kHz 113 dB Channel separation f = 1kHz at 0dBFS for active channel 110 dB DYNAMIC PERFORMANCE WITH 16-BIT DATA fs = 44.1kHz Total harmonic distortion + noiseTHD+N f = 1kHz at 0dBFS −92 dB Total harmonic distortion + noiseTHD+N f = 1kHz at −60dBFS −33 dB Dynamic Range, A-weighted f = 1kHz at −60dBFS 96 dB Idle channel SNR, A-weighted(2) All zero input data 118 dB Idle channel SNR, unweighted(2) All zero input data 115 dB (1)Dynamic performance parameters are measured using an Audio Precision System Two Cascade or Cascade Plus test system. Input data word length is 24 bits with triangular PDF dither added for dynamic range and THD+N tests. Idle channel SNR is measured with both the soft and zero data mute functions disabled and 0% full-scale input data with no dither applied. The measurement bandwidth is limited by using the Audio Precision 10Hz high-pass filter in combination with either the AES17 20kHz low-pass filter or AES17 40kHz low-pass filter. All A-weighted measurements are performed using the Audio Precision A-weighting filter in combination with either the 22kHz or 80kHz low-pass filter. Measurement mode is set to RMS for all parameters. The AVERAGE measurement mode will yield better typical performance numbers. (2)Idle Channel SNR is not limited by word length.

/C0080/C0067/C0077/C0052/C0049/C0048/C0052 SBAS291C − AUGUST 2003 − REVISED DECEMBER 2004 www.ti.com ELECTRICAL CHARACTERISTICS (continued) All parameters are specified at TA = +25°C with VCC = +5V, VDD = +3.3V, and a measurement bandwidth from 10Hz to 20kHz, unless otherwise noted. System clock frequency is equal to 256fS for Single and Dual Rate sampling modes, and 128fS for Quad Rate sampling mode. PCM4104 PARAMETER UNITSMAXTYPMINCONDITIONS DIGITAL FILTERS Passband ±0.002dB 0.454fS Hz Passband −3dB 0.487fS Hz Stop Band 0.546fs Hz Passband ripple ±0.002 dB Stopband attenuation 0.546fs −75 dB Stopband attenuation 0.567fs −82 dB Group delay 29/fS sec De-emphasis filter error 0.1 dB POWER SUPPLY Supply Range Analog supply, VCC +4.75 +5.0 +5.25 V Digital supply, VDD +3.0 +3.3 +3.6 V Power down current VCC = +5V, VDD = +3.3V Power-down supply current, ICC + IDD RST = low, system and audio clocks off 1 mA Quiescent current System and audio clocks applied, all 0s data VCC = +5V, fS =48kHz 32 40 mA Analog supply, ICC VCC = +5V, fS =96kHz 32 mAAnalog supply, ICC VCC = +5V, fS =192kHz 32 mA VDD = +3.3V, fS =48kHz 13 17 mA Digital supply, IDD VDD = +3.3V, fS =96kHz 18 mADigital supply, IDD VDD = +3.3V, fS =192kHz 23 mA VCC = +5V, VDD = +3.3V Total power dissipation fS = 48kHz 203 256 mW Total power dissipation fS = 96kHz 220 mW fS = 192kHz 236 mW

/C0080/C0067/C0077/C0052/C0049/C0048/C0052 SBAS291C − AUGUST 2003 − REVISED DECEMBER 2004 www.ti.com PIN ASSIGNMENTS TQFP PACKAGE (TOP VIEW) VOUT 4+ VOUT 4− AGND2 V REF 4− VREF 4+ NC NC FS1 FS0 FMT2 FMT1 FMT0 VCOM 1 VOUT 2+ VOUT 2− VCC 1 VREF 2+ VREF 2− VREF 3− VREF 3+ VCC 2 VOUT 3− VOUT 3+ VCOM 2 SUB SCKI BCK LRCK DATA0 DATA1 V DD DGND CS CCLK CDIN CDOUT VOUT 1+ VOUT 1− AGND1 VREF 1− VREF 1+ NC NC MODE RST MUTE DEM1 DEM0 48 47 46 45 44 43 42 41 40 39 38 13 14 15 16 17 18 19 20 21 22 23 PCM4104 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION VOUT 1+ 1 Output Channel 1 Analog Output, Noninverted VOUT 1− 2 Output Channel 1 Analog Output, Inverted AGND1 3 Ground Analog Ground VREF 1− 4 Input Channel 1 Low Reference Voltage; Connect to AGND VREF 1+ 5 Input Channel 1 High Reference Voltage; Connect to VCC NC 6 No Internal Connection NC 7 No Internal Connection MODE 8 Input Operating Mode (0 = Standalone, 1= Software Controlled) RST 9 Input Reset/Power Down (Active Low) MUTE 10 Input All−Channel Soft Mute (Active High) DEM1 11 Input Digital De-Emphasis Filter Configuration DEM0 12 Input Digital De-Emphasis Filter Configuration SUB 13 Input Sub-Frame Assignment (TDM Formats Only) SCKI 14 Input System Clock

/C0080/C0067/C0077/C0052/C0049/C0048/C0052 SBAS291C − AUGUST 2003 − REVISED DECEMBER 2004 www.ti.com Terminal Functions (continued) TERMINAL NAME DESCRIPTIONI/ONO. BCK 15 Input Audio Bit (or Data) Clock LRCK 16 Input Audio Left/Right (or Word) Clock DATA0 17 Input Audio Data for Channels 1 and 2 (I2S, Left/Right Justified formats) or Audio Data for Channels 1 Through 4 for TDM Formats DATA1 18 Input Audio Data for Channels 3 and 4 (I2S, Left/Right Justified formats) VDD 19 Power Digital Power Supply, +3.3V DGND 20 Ground Digital Ground CS 21 Input Serial Peripheral Interface (SPI) Chip Select (Active Low) CCLK 22 Input Serial Peripheral Interface (SPI) Data Clock CDIN 23 Input Serial Peripheral Interface (SPI) Data Input CDOUT 24 Output Serial Peripheral Interface (SPI) Data Output FMT0 25 Input Audio Data Format Configuration FMT1 26 Input Audio Data Format Configuration FMT2 27 Input Audio Data Format Configuration FS0 28 Input Sampling Mode Configuration FS1 29 Input Sampling Mode Configuration NC 30 No Internal Connection NC 31 No Internal Connection VREF 4+ 32 Input Channel 4 High Reference Voltage; Connect to VCC VREF 4− 33 Input Channel 4 Low Reference Voltage; Connect to AGND AGND2 34 Ground Analog Ground VOUT 4− 35 Output Channel 4 Analog Output, Inverted VOUT 4+ 36 Output Channel 4 Analog Output, Noninverted VCOM 2 37 Output DC Common-Mode Voltage for Channels 3 and 4, +2.5V nominal VOUT 3+ 38 Output Channel 3 Analog Output, Noninverted VOUT 3− 39 Output Channel 3 Analog Output, Inverted VCC 2 40 Power Analog Power Supply, +5V VREF 3+ 41 Input Channel 3 High Reference Voltage; Connect to VCC VREF 3− 42 Input Channel 3 Low Reference Voltage,; Connect to AGND VREF 2− 43 Input Channel 2 Low Reference Voltage; Connect to AGND VREF 2+ 44 Input Channel 2 High Reference Voltage; Connect to VCC VCC 1 45 Power Analog Power Supply, +5V VOUT 2− 46 Output Channel 2 Analog Output, Inverted VOUT 2+ 47 Output Channel 2 Analog Output, Noninverted VCOM 1 48 Output DC Common-Mode Voltage for Channels 1 and 2, +2.5V nominal

/C0080/C0067/C0077/C0052/C0049/C0048/C0052 SBAS291C − AUGUST 2003 − REVISED DECEMBER 2004 www.ti.com TYPICAL CHARACTERISTICS All parameters are specified at TA = +25°C with VCC = +5V, VDD = +3.3V, and a measurement bandwidth from 10Hz to 20kHz, unless otherwise noted. System clock frequency is equal to 256fS for Single and Dual Rate sampling modes, and 128fS for Quad Rate sampling mode. FFT PLOT Frequency (Hz) Amplitude (dB) −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 1k10020 10k 20k fS =4 8 k H z fIN =1 k H z 0dBFS Amplitude 24−Bit Data FFT PLOT Frequency (Hz) Amplitude (dB) −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 1k10020 10k 20k fS = 48kHz fIN =1 k H z −20dBFS Amplitude 24−Bit Data FFT PLOT Frequency (Hz) Amplitude (dB) −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 1k10020 10k 20k fS = 48kHz fIN =1 k H z −60dBFS Amplitude 24−Bit Data FFT PLOT Frequency (Hz) Amplitude (dB) −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 1k10020 10k 20k fS =4 8 k H z Idle Channel Input 24−Bit Data FFT PLOT Frequency (Hz) Amplitude (dB) −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 1k10020 10k 40k fS =9 6 k H z fIN =1 k H z 0dBFS Amplitude 24−Bit Data FFT PLOT Frequency (Hz) Amplitude (dB) −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 1k10020 10k 40k fS = 96kHz fIN =1 k H z −20dBFS Amplitude 24−Bit Data

/C0080/C0067/C0077/C0052/C0049/C0048/C0052 SBAS291C − AUGUST 2003 − REVISED DECEMBER 2004 www.ti.com TYPICAL CHARACTERISTICS (continued) All parameters are specified at TA = +25°C with VCC = +5V, VDD = +3.3V, and a measurement bandwidth from 10Hz to 20kHz, unless otherwise noted. System clock frequency is equal to 256fS for Single and Dual Rate sampling modes, and 128fS for Quad Rate sampling mode. FFT PLOT Frequency (Hz) Amplitude (dB) −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 1k10020 10k 40k fS =9 6 k H z fIN =1 k H z −60dBFS Amplitude 24−Bit Data FFT PLOT Frequency (Hz) Amplitude (dB) −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 1k10020 10k 40k fS =9 6 k H z Idle Channel Input 24−Bit Data FFT PLOT Frequency (Hz) Amplitude (dB) −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 1k10020 10k 40k fS = 192kHz fIN =1 k H z 0dBFS Amplitude 24−Bit Data FFT PLOT Frequency (Hz) Amplitude (dB) −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 1k10020 10k 40k fS = 192kHz fIN =1 k H z −20dBFS Amplitude 24−Bit Data FFT PLOT Frequency (Hz) Amplitude (dB) −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 1k10020 10k 40k fS = 192kHz fIN =1 k H z −60dBFS Amplitude 24−Bit Data FFT PLOT Frequency (Hz) Amplitude (dB) −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 1k10020 10k 40k fS = 192kHz Idle Channel Input 24−Bit Data

/C0080/C0067/C0077/C0052/C0049/C0048/C0052 SBAS291C − AUGUST 2003 − REVISED DECEMBER 2004 www.ti.com TYPICAL CHARACTERISTICS (continued) All parameters are specified at TA = +25°C with VCC = +5V, VDD = +3.3V, and a measurement bandwidth from 10Hz to 20kHz, unless otherwise noted. System clock frequency is equal to 256fS for Single and Dual Rate sampling modes, and 128fS for Quad Rate sampling mode. FFT PLOT Frequency (Hz) Amplitude (dB) −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 1k10020 10k 20k fS = 44.1kHz fIN =1 k H z 0dBFS Amplitude 16−Bit Data FFT PLOT Frequency (Hz) Amplitude (dB) −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 1k10020 10k 20k fS = 44.1kHz fIN =1 k H z −20dBFS Amplitude 16−Bit Data FFT PLOT Frequency (Hz) Amplitude (dB) −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 1k10020 10k 20k fS = 44.1kHz fIN =1 k H z −60dBFS Amplitude 16−Bit Data FFT PLOT Frequency (Hz) Amplitude (dB) −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 −160 1k10020 10k 20k fS = 44.1kHz Idle Channel Input 16−Bit Data THD+N vs AMPLITUDE Amplitude (dBFS) THD+N (dB) −80 −85 −90 −95 −100 −105 −110 −115 −120 −150 −140 −130 −120 −110 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 fS = 48kHz fIN =1 k H z 24−Bit Data THD+N vs AMPLITUDE Amplitude (dBFS) THD+N (dB) −80 −85 −90 −95 −100 −105 −110 −115 −120 −150 −140 −130 −120 −110 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 fS =9 6 k H z fIN =1 k H z 24−Bit Data

/C0080/C0067/C0077/C0052/C0049/C0048/C0052 SBAS291C − AUGUST 2003 − REVISED DECEMBER 2004 www.ti.com TYPICAL CHARACTERISTICS (continued) All parameters are specified at TA = +25°C with VCC = +5V, VDD = +3.3V, and a measurement bandwidth from 10Hz to 20kHz, unless otherwise noted. System clock frequency is equal to 256fS for Single and Dual Rate sampling modes, and 128fS for Quad Rate sampling mode. THD+N vs AMPLITUDE Amplitude (dBFS) THD+N (dB) −80 −85 −90 −95 −100 −105 −110 −115 −120 −150 −140 −130 −120 −110 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 fS = 192kHz fIN =1 k H z 24−Bit Data THD+N vs AMPLITUDE Amplitude (dBFS) THD+N (dB) −80 −85 −90 −95 −100 −105 −110 −115 −120 −150 −140 −130 −120 −110 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 fS = 44.1kHz fIN =1 k H z 16−Bit Data −20 −40 −60 −80 −100 −120 −140 −160 FREQUENCY RESPONSE 01234 Frequency (x fS) Amplitude (dB) 0.003 0.002 0.001 −0.001 −0.002 −0.003 PASSBAND RIPPLE Frequency (x fS) Amplitude (dB) 0.0 −1.0 −2.0 −3.0 −4.0 −5.0 −6.0 −7.0 −8.0 −9.0 −10.0 DE−EMPHASIS FILTER RESPONSE (f S = 32kHz) 02468 1 0 1 2 1 4 Frequency (kHz) Level (dB) 0.5 0.4 0.3 0.2 0.1 0.0 −0.1 −0.2 −0.3 −0.4 −0.5 DE−EMPHASIS ERROR (f S = 32kHz) 02468 1 0 1 2 1 4 Frequency (kHz) Error (dB)

/C0080/C0067/C0077/C0052/C0049/C0048/C0052 SBAS291C − AUGUST 2003 − REVISED DECEMBER 2004 www.ti.com TYPICAL CHARACTERISTICS (continued) All parameters are specified at TA = +25°C with VCC = +5V, VDD = +3.3V, and a measurement bandwidth from 10Hz to 20kHz, unless otherwise noted. System clock frequency is equal to 256fS for Single and Dual Rate sampling modes, and 128fS for Quad Rate sampling mode. 0.0 −1.0 −2.0 −3.0 −4.0 −5.0 −6.0 −7.0 −8.0 −9.0 −10.0 DE−EMPHASIS FILTER RESPONSE (f S =4 4 . 1 k H z ) 0 2 4 6 8 1 01 21 41 61 82 0 Frequency (kHz) Level (dB) 0.5 0.4 0.3 0.2 0.1 0.0 −0.1 −0.2 −0.3 −0.4 −0.5 DE−EMPHASIS ERROR (f S = 44.1kHz) 0 2 4 6 8 1 01 21 41 61 82 0 Frequency (kHz) Error (dB) 0.0 −1.0 −2.0 −3.0 −4.0 −5.0 −6.0 −7.0 −8.0 −9.0 −10.0 DE− EMPHASIS FILTER RESPONSE (f S =4 8 k H z ) 0 2 4 6 8 1 01 21 41 61 82 2 Frequency (kHz) Level (dB) 0.5 0.4 0.3 0.2 0.1 0.0 −0.1 −0.2 −0.3 −0.4 −0.5 DE− EMPHASIS ERROR (f S =4 8 k H z ) 0 2 4 6 8 1 01 21 41 61 82 2 Frequency (kHz) Error (dB)

allowing configuration of the full PCM4104 feature set. simplified pin-programmed configuration mode. Figure 1. Functional Block Diagram for Standalone Mode

Figure 2. PCM4104 Functional Block Diagram for Software Mode (pin 47) and VOUT 2− (pin 46) correspond to Channel 2. recommended output filter circuits. VREF 4− (pin 33) correspond to Channel 4.

between the corresponding high and low reference pins. low-frequency power-supply noise present in the system. connections for the reference pins. (1) Capacitor(s) required for each of the four reference pairs. Figure 3. Recommended Connections for Voltage and FS1 (pin 29) inputs in Standalone mode. oversampling of the input data in Single Rate mode. requirements for common sampling frequencies. Table 1. Sampling Modes and System Clock Frequencies for Common Audio Sampling Rates

1024 System Clock Periods

Figure 5. Power-Up Reset Timing Figure 6. External Reset Timing Figure 7. Analog Output State for Reset Operations

and 2, and PDN34 corresponding to channels 3 and 4. Figure 8. Analog Output State for Power-Down Operations

providing an option for a simplified control model. configuration for Standalone mode. Table 2. Sampling Mode Configuration is always sampled on the rising edge of the BCK clock. Table 3. Audio Data Format Configuration mute level, minimizing or eliminating audible artifacts. Table 4 summarizes MUTE function operation. Table 4. Mute Function Configuration

0 On (mute disabled)

1 Muted

frequency content within the 20kHz audio band. filter configuration for Standalone mode. Table 5. Digital De-Emphasis Configuration

/C0080/C0067/C0077/C0052/C0049/C0048/C0052 SBAS291C − AUGUST 2003 − REVISED DECEMBER 2004 www.ti.com SOFTWARE MODE CONFIGURATION Software mode is selected by forcing the MODE input (pin 8) high. Software mode operation provides full access to the features of the PCM4104 by allowing the writing and reading of on-chip control registers. This is accomplished using the four-wire SPI port. The following paragraphs provide a brief description of each function available when using Software mode. Digital Attenuation The audio signal for each channel can be attenuated in the digital domain using this function. Attenuation settings from 0dB (unity gain) to −119.5dB are provided in 0.5dB steps. In addition, the attenuation level may be set to the mute state. The rate of change for the digital attenuation function is one 0.5dB step for every eight LRCK periods. Each channel has its own independent attenuation control, accessed using control registers 1 through 4. The reset default setting for all channels is 0dB, or unity gain (no attenuation applied). Digital De-Emphasis The de-emphasis function is accessed through Control Register 5 using the DEM[1:0] bits. The reset default setting is that the de-emphasis is disabled for all four channels. De-emphasis filter operation is described in the Standalone Mode Configuration section of this data sheet. Soft Mute Each of the four D/A converter channels has its own independent soft mute control, located in Control Register The reset default is normal output for all four channels with the soft mute function disabled. The MUTE input (pin 10) also functions in Software mode, with a high input forcing soft mute on all four channels. Zero Data Mute The PCM4104 includes a zero data detection and mute function in Software mode. This function automatically mutes a given channel when 1024 consecutive LRCK periods of all zero data are detected for that channel. The zero data mute function is enabled and disabled using the ZDM bit in Control Register 5. The zero data mute function is disabled by default on power up or reset. Output Phase Reversal The PCM4104 includes an output phase reversal function, which provides the ability to invert the output phase for all four channels, either for testing or for matching various output circuit configurations. This function is controlled using the PHASE bit, located within Control Register 5. The output phase is set to noninverted by default on power up or reset. Sampling Mode Sampling mode configuration was discussed earlier in this data sheet, with Table 1 providing a reference for common sampling and system clock frequencies. The FS0 and FS1 bits located in Control Register 6 are used to set the sampling mode. The sampling mode defaults to Single Rate on power up or reset. Power-Down Modes The power-down control bits are located in Control Register 6. These bits are used to power down pairs of D/A converters within the PCM4104. The PDN12 bit is used to power down channels 1 and 2, while the PDN34 bit is used to power down channels 3 and 4. When a channel pair is powered down, it ignores the audio data inputs and sets its outputs to a high-impedance state. By default, the power-down bits are disabled on power up or reset. Software Reset This reset function allows a reset sequence to be initiated under software control. All control registers are reset to their default state. The reset bit, RST, is located in Control Register 6. Setting this bit to 1 initiates a one-time reset sequence. The RST bit is cleared by the initialization sequence. Audio Data Formats, LRCK Polarity, and BCK Sampling Edge Control Register 7 is used to configure the PCM4104 audio serial port. Audio serial port operation was discussed previously in this data sheet; refer to that section for more details regarding the functions controlled by this register. The control register definitions provide additional information regarding the register functions and their default settings.

the PCM4104 is configured for Software mode operation. port: Single Register, Continuous, and Auto-Increment. a new address for the next write or read operation. succession, as shown in Figure 16. byte, as shown in Figure 17. write operation, or set to 1 for a register read operation. in the port ignoring the write or read request. Figure 16. Single Register and Continuous Write or Read Operation

for normal operation. Register 0 defaults to all zero data on power up or reset. Table 6. Control Register Map

1 AT17 AT16 AT15 AT14 AT13 AT12 AT11 AT10

2 AT27 AT26 AT25 AT24 AT23 AT22 AT21 AT20

3 AT37 AT36 AT35 AT34 AT33 AT32 AT31 AT30

4 AT47 AT46 AT45 AT44 AT43 AT42 AT41 AT40

5 MUT4 MUT3 MUT2 MUT1 ZDM PHASE DEM1 DEM0

6 RST 0 0 0 PDN34 PDN12 FS1 FS0

This register controls the digital output attenuation for Channel 1. This register controls the digital output attenuation for Channel 2. This register controls the digital output attenuation for Channel 3.

/C0080/C0067/C0077/C0052/C0049/C0048/C0052 SBAS291C − AUGUST 2003 − REVISED DECEMBER 2004 www.ti.com Register 4: Attenuation Control Register – Channel 4 BIT 7 (MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (LSB) AT47 AT46 AT45 AT44 AT43 AT42 AT41 AT40 This register controls the digital output attenuation for Channel 4. Default: AT4[7:0] = 255, or 0dB Let N = AT4[7:0]. For N = 16 to 255, Attenuation (dB) = 0.5 x (255 – N) For N = 0 to 15, Attenuation (dB) = Infinite (Muted) Register 5: Function Control Register BIT 7 (MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (LSB) MUT4 MUT3 MUT2 MUT1 ZDM PHASE DEM1 DEM0 This register controls various D/A converter functions, including de-emphasis filtering, output phase reversal, zero data mute, and per-channel soft muting. DEM[1:0] Digital De-Emphasis De-emphasis is available for Single Rate mode only. De-emphasis is disabled for Dual and Quad Rate modes. DEM1 DEM0 De-Emphasis Selection 0 0 De-emphasis disabled (default) 0 1 De-emphasis for f S = 48kHz 1 0 De-emphasis for f S = 44.1kHz 1 1 De-emphasis for f S = 32kHz PHASE Output Phase PHASE Output Phase

0 Noninverted (default)

1 Inverted

0 Disabled (default)

1 Enabled

MUT[4:1] Soft Mute MUTx D/A Converter Output

0 On (default)

NOTE: x = channel number.

/C0080/C0067/C0077/C0052/C0049/C0048/C0052 SBAS291C − AUGUST 2003 − REVISED DECEMBER 2004 www.ti.com Register 6: System Control Register BIT 7 (MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (LSB) RST 0 0 0 PDN34 PDN12 FS1 FS0 This register controls various system level functions of the PCM4104, including sampling mode, power down, and soft reset. FS[1:0] Sampling Mode FS1 FS0 Sampling Mode 0 0 Single Rate (default) 0 1 Dual Rate 1 0 Quad Rate 1 1 − Not Used − PDN12 Power-Down for Channels 1 and 2 PDN12 Power Down for Channels 1 and 2 PDN34 Power Down for Channels 3 and 4 PDN34 Power Down for Channels 3 and 4 RST Software Reset (value defaults to 0) Setting this bit to 1 will initiate a logic reset of the PCM4104. This bit functions the same as an external reset applied at the RST input (pin 9). Register 7: Audio Serial Port Control Register BIT 7 (MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (LSB) 0 0 BCKE LRCKP 0 FMT2 FMT1 FMT0 This register is used to control the data format and clock polarity for the PCM4104 audio serial port. FMT[2:0] Audio Data Format FMT2 FMT1 DEM0 Data Format 0 0 0 24-bit left justified (default) 0 0 1 24-bit I 2S 0 1 0 TDM with zero BCK delay 0 1 1 TDM with one BCK delay 1 0 0 24-bit right justified 1 0 1 20-bit right justified 1 1 0 18-bit right justified 1 1 1 16-bit right justified LRCKP LRCK Polarity (0 = Normal, 1 = Inverted). Defaults to 0. BCKE BCK Sampling Edge (0 = Rising Edge, 1 = Falling Edge), Defaults to 0.

www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) PCM4104PFBR Active Production TQFP (PFB) | 48 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -10 to 70 PCM4104 PCM4104PFBR.B Active Production TQFP (PFB) | 48 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -10 to 70 PCM4104 PCM4104PFBT Active Production TQFP (PFB) | 48 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -10 to 70 PCM4104 PCM4104PFBT.B Active Production TQFP (PFB) | 48 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -10 to 70 PCM4104 PCM4104PFBTG4 Active Production TQFP (PFB) | 48 250 | SMALL T&R Yes NIPDAU Level-2-260C-1 YEAR -10 to 70 PCM4104 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 26-Jun-2023 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 26-Jun-2023 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCM4104PFBR TQFP PFB 48 2000 350.0 350.0 43.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C 48X 0.27 0.1744X 0.5 PIN 1 ID (0.13) TYP

0.05 MIN0 -7

4X 5.5 9.2

8.8 TYP

0.75 0.45 B7.2 6.8 NOTE 3 A 7.2 6.8 NOTE 3 0.25 GAGE PLANE

1.2 MAX

(1) PLASTIC QUAD FLATPACK TQFP - 1.2 mm max heightPFB0048A PLASTIC QUAD FLATPACK 4215157/A 03/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Reference JEDEC registration MS-026. 13 24 3748

0.08 C A B

0.08 A 16 DETAIL A TYPICAL SCALE 1.900

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

(8.5) (8.5) 44X (0.5) 48X (1.35) 48X (0.25) (R0.05) TYP TQFP - 1.2 mm max heightPFB0048A PLASTIC QUAD FLATPACK 4215157/A 03/2024 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM SYMM 48 37 13 24 SEE DETAILS METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN 44X (0.5) 48X (1.35) 48X (0.25) (R0.05) TYP (8.5) (8.5) TQFP - 1.2 mm max heightPFB0048A PLASTIC QUAD FLATPACK 4215157/A 03/2024 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE SCALE:8X SYMM SYMM 48 37 13 24

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