PCM3168ATPAPRQ1

PCM3168A TI | Alldatasheet

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Burr-Brown□Audio

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www.ti.com SBAS452 SEPTEMBER 2008 24-Bit, 96-kHz/192-kHz, 6-In/8-Out Audio Codec with Differential Input/Output FLEXIBLE MODE CONTROL: 24-BIT Δ Σ ADC AND DAC Four-Wire SPI Two-Wire I C Compatible Serial Control Interface or SIX-CHANNEL ADC: Hardware Control High Performance: Differential and MULTIPLE FUNCTIONS VIA SPI OR I C I/F: Single-Ended, f S kHz Audio I/F Mode/Format Select for ADC and THD+N: dB (Differential), dB DAC (Single-Ended) Digital Attenuation and Soft Mute for ADC SNR: 107 dB (Differential), 104 dB and DAC (Single-Ended) Digital De-Emphasis: kHz, 44.1 kHz, Dynamic Range: 107 dB (Differential), kHz for DAC 104 dB (Single-Ended) Data Polarity Control for ADC and DAC Sampling Rate: kHz to kHz Power Down ADC/DAC Independently System Clock: 256 f S 384 f S 512 f S 768 f S MULTI FUNCTIONS VIA H/W CONTROL: Differential Voltage Input: V RMS Audio I/F Mode/Format Select Single-Ended Voltage Input: V RMS Digital De-Emphasis Filter: Decimation Filter: 44.1 kHz for DAC Passband Ripple: 0.035 dB EXTERNAL RESET PIN: Stop Band Attenuation: dB ADC/DAC Simultaneous On-Chip, High-Pass Filter: AUDIO INTERFACE MODE: 0.96 Hz at f S kHz ADC/DAC Independent Master/Slave Overflow Flag AUDIO DATA FORMAT: EIGHT-CHANNEL DAC: ADC/DAC Independent I S Left-Justified, High Performance: Differential, f S kHz Right-Justified, DSP, TDM THD+N: dB POWER SUPPLIES: V for Analog and SNR: 112 dB 3.3 V for Digital Dynamic Range: 112 dB PACKAGE: HTQFP-64 Sampling Rate: kHz to 192 kHz OPERATING TEMPERATURE RANGE: System Clock: 128 f S 192 f S 256 f S 384 f S Consumer Grade: C to +85 C 512 f S 768 f S Automotive Audio Grade: C to +105 C Differential Voltage Output: V PP Analog Low-Pass Filter Included 4x/8x Oversampling Digital Filter: CAR AUDIO EXTERNAL AMPLIFIERS Passband Ripple: 0.0018 dB CAR AUDIO AVN Attenuation: dB HOME THEATERS Zero Flag AV RECEIVERS Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. PowerPAD is a trademark of Texas Instruments Incorporated. SPI is a trademark of Motorola. I2C, I2S are trademarks of NXP Semiconductors. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright 2008, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

DESCRIPTION

www.ti.com The PCM3168A and PCM3168A-Q1 are high-performance, single-chip, 24-bit, 6-in/8-out, audio coders/decoders (codecs) with single-ended and differential selectable analog inputs and differential outputs. The six-channel, 24-bit analog-to-digital converter (ADC) employs a delta-sigma Δ Σ modulator and supports 8-kHz to 96-kHz sampling rates and a 16-bit/24-bit width digital audio output word on the audio interface. The eight-channel, 24-bit digital-to-analog converter (DAC) employs a Δ Σ modulator and supports 8-kHz to 192-kHz sampling rates and a 16-bit/24-bit width digital audio input word on the audio interface. Each audio interface supports I left-justified, right-justified, and DSP formats with 16-bit/24-bit word width. In addition, the PCM3168A and PCM3168A-Q1 support the time-division-multiplexed (TDM) format. The PCM3168A and PCM3168A-Q1 can be controlled through a four-wire, SPI-compatible interface, or two-wire, I C-compatible serial interface in software, which provides access to all functions including digital attenuation, soft mute, de-emphasis, and so forth. Also, hardware control mode provides a subset of user-programmable functions through four control pins. The PCM3168A and PCM3168A-Q1 are available in a 12-mm 12-mm (10-mm 10-mm body) HTQFP-64 PowerPAD package. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): PCM3168A PCM3168A-Q1

(1) RECOMMENDED OPERATING CONDITIONS PCM3168A PCM3168A-Q1 www.ti.com SBAS452 SEPTEMBER 2008 Over operating free-air temperature range (unless otherwise noted). PCM3168A, PCM3168A-Q1 UNIT Supply voltage: VCCAD1, VCCAD2, VCCDA1, VCCDA2 0.3 to +6.5 V Supply voltage: VDD1, VDD2 0.3 to +4.0 V Ground voltage differences: 0.1 V AGNDAD1, AGNDAD2, AGNDDA1, AGNDDA2, DGND1, DGND2 Supply voltage differences: VCCAD1, VCCAD2, VCCDA1, VCCDA2 0.1 V Supply voltage differences: VDD1, VDD2 0.1 V Digital input voltage: RST, MS, MC, MDI, SCK 0.3 to +6.5 V Digital input voltage: 0.3 to (VDD 0.3) +4.0 V BCKAD/DA, LRCKAD/DA, DIN1/2/3/4, DOUT1/2/3, MODE, OVF, ZERO, MDO Analog input voltage: VIN1-6 VCOMAD/DA, VOUT1-8 VREFAD1/2 0.3 to (VCC 0.3) +6.5 V Input current (all pins except supplies) mA Ambient temperature range (under bias) to +125 C Storage temperature to +150 C Junction temperature +150 C Lead temperature (soldering, 5s) +260 C Package temperature (IR reflow, peak) +260 C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Over operating free-air temperature range (unless otherwise noted). PCM3168A, PCM3168A-Q1 PARAMETER MIN TYP MAX UNIT Analog supply voltage, VCC 4.5 5.0 5.5 V Digital supply voltage, VDD 3.0 3.3 3.6 V Digital Interface LVTTL compatible Sampling frequency, (1) kHz LRCKAD/LRCKDA (1) Digital input clock frequency System clock frequency, SCKI 2.048 36.864 MHz Single-ended V RMS Analog input level Differential V RMS Analog output voltage Differential V PP To ac-coupled GND k Ω Analog output load resistance To dc-coupled GND k Ω Analog output load capacitance pF Digital output load capacitance pF PCM3168A Consumer grade +25 +85 C Operating free-air temperature PCM3168A-Q1 Automotive audio grade +25 +105 C (1) 192 kHz is supported only for DAC. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM3168A PCM3168A-Q1

CHARACTERISTICS: Digital Input/Output PCM3168A PCM3168A-Q1 SBAS452 SEPTEMBER 2008 www.ti.com All specifications at T A +25 VCCAD1 VCCAD2 VCCDA1 VCCDA2 VDD1 VDD2 3.3 f S kHz, SCKI 512 f S 24-bit data, Sampling Mode Auto for ADC and DAC, and Interface Mode Slave for ADC and DAC, unless otherwise noted. PCM3168A, PCM3168A-Q1 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DATA FORMAT Audio data interface format I LJ, RJ, DSP, TDM Audio data word length 16, Bits Audio data format MSB first, twos complement Sampling frequency, ADC kHz f S Sampling frequency, DAC 192 kHz 128 f S 192 f S 256 f S System clock frequency 2.048 36.864 MHz 384 f S 512 f S 768 f S INPUT LOGIC V IH (1) (2) 2.0 VDD VDC Input logic level V IL (1) (2) 0.8 VDC V IH (3) (4) 2.0 5.5 VDC Input logic level V IL (3) (4) 0.8 VDC I IH (2) (3) V IN VDD µ A Input logic level I IL (2) (3) V IN V µ A I IH (1) (4) V IN VDD +65 +100 µ A Input logic level I IL (1) (4) V IN V µ A OUTPUT LOGIC V OH (5) I OUT mA 2.4 VDC Output logic level V OL (5) (6) I OUT mA 0.4 VDC REFERENCE INPUT/OUTPUT VREFAD1 output voltage VCCAD1 V VREFAD2 output voltage AGNDAD1 V 0.5 VCOMAD output voltage V VCCAD1 VCOMAD output impedance k Ω Allowable VCOMAD output source/sink current µ A 0.5 VCOMDA output voltage V VCCDA1 VCOMDA output impedance 7.5 k Ω Allowable VCOMDA output source/sink current µ A (1) BCKAD, BCKDA, LRCKAD, and LRCKDA (in slave mode, Schmitt trigger input with 50-k Ω typical internal pull-down resistor). (2) DIN1/2/3/4 and MDO/ADR1/MD1. (Except SPI mode, Schmitt trigger input). (3) SCKI, MDI/SDA/DEMP, and MC/SCL/FMT (Schmitt trigger input, 5-V tolerant). (4) RST and MS/ADR0/MD0 (Schmitt trigger input with 50-k Ω typical internal pull-down resistor, 5-V tolerant). (5) BCKAD, BCKDA, LRCKAD, and LRCKDA (in master mode), DOUT1/2/3, ZERO, OVF, and MDO/ADR1/MD1 (in SPI mode). (6) SDA (in I C mode, open-drain low output). Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): PCM3168A PCM3168A-Q1

CHARACTERISTICS: ADC Characteristics PCM3168A PCM3168A-Q1 www.ti.com SBAS452 SEPTEMBER 2008 All specifications at T A +25 VCCAD1 VCCAD2 VCCDA1 VCCDA2 VDD1 VDD2 3.3 f S kHz, SCKI 512 f S 24-bit data, Sampling Mode Auto for ADC and DAC, and Interface Mode Slave for ADC and DAC, unless otherwise noted. PCM3168A, PCM3168A-Q1 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ADC CHARACTERISTICS Resolution Bits 0.2 V IN dB, Single-ended V RMS VCCAD1 Full-scale input voltage 0.4 V IN dB, Differential V RMS VCCAD1 0.5 Center voltage V VCCAD1 Input impedance k Ω Common-mode rejection ratio dB DC ACCURACY Gain mismatch channel-to-channel Full-scale input, V IN 2.0 of FSR Gain error Full-scale input, V IN 2.0 of FSR Bipolar zero error High-pass filter bypass, V IN 1.0 of FSR DYNAMIC PERFORMANCE (1) (2) f S kHz, Differential dB f S kHz, Differential dB THD+N, V IN dB f S kHz, Single-ended dB f S kHz, Single-ended dB f S kHz, A-weighted, differential 100 107 dB f S kHz, A-weighted, differential 107 dB f S kHz, A-weighted, Dynamic range 104 dB single-ended f S kHz, A-weighted, 104 dB single-ended f S kHz, A-weighted, differential 100 107 dB f S kHz, A-weighted, differential 107 dB f S kHz, A-weighted, S/N ratio 104 dB single-ended f S kHz, A-weighted, 104 dB single-ended f S kHz, Differential 104 dB f S kHz, Differential 104 dB Channel separation (between one channel and others) f S kHz, Single-ended 101 dB f S kHz, Single-ended 101 dB (1) In differential mode at VINx pin, f IN kHz, using Audio Precision System II, RMS mode with 20-kHz low-pass filter and 400-Hz high-pass filter. (2) f S kHz SCKI 512 f S (single), f S kHz SCKI 256 f S (dual), f S 192 kHz SCKI 128 f S (quad). Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM3168A PCM3168A-Q1

CHARACTERISTICS: DAC Characteristics PCM3168A PCM3168A-Q1 SBAS452 SEPTEMBER 2008 www.ti.com ELECTRICAL CHARACTERISTICS: ADC Characteristics (continued) All specifications at T A +25 VCCAD1 VCCAD2 VCCDA1 VCCDA2 VDD1 VDD2 3.3 f S kHz, SCKI 512 f S 24-bit data, Sampling Mode Auto for ADC and DAC, and Interface Mode Slave for ADC and DAC, unless otherwise noted. PCM3168A, PCM3168A-Q1 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL FILTER PERFORMANCE Passband (single) 0.454 f S Hz Passband (dual) 0.454 f S Hz Stop band (single) 0.555 f S Hz Stop band (dual) 0.597 f S Hz Passband ripple 0.454 f S 0.454 f S 0.035 dB Stop band attenuation 0.555 f S 0.597 f S dB Group delay time (single) 27/f S sec Group delay time (dual) 17/f S sec 0.02 High-pass filter frequency response dB Hz f S /1000 All specifications at T A +25 VCCAD1 VCCAD2 VCCDA1 VCCDA2 VDD1 VDD2 3.3 f S kHz, SCKI 512 f S 24-bit data, Sampling Mode Auto for ADC and DAC, and Interface Mode Slave for ADC and DAC, unless otherwise noted. PCM3168A, PCM3168A-Q1 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DAC CHARACTERISTICS Resolution Bits DC ACCURACY Gain mismatch channel-to-channel 2.0 of FSR Gain error 2.0 of FSR Bipolar zero error 1.0 of FSR DYNAMIC PERFORMANCE (1) (2) f S kHz dB THD+N, V OUT dB f S kHz dB f S 192 kHz dB f S kHz, EIAJ, A-weighted 105 112 dB Dynamic range f S kHz, EIAJ, A-weighted 112 dB f S 192 kHz, EIAJ, A-weighted 112 dB f S kHz, EIAJ, A-weighted 105 112 dB S/N ratio f S kHz, EIAJ, A-weighted 112 dB f S 192 kHz, EIAJ, A-weighted 112 dB f S kHz 102 108 dB Channel separation f S kHz 108 dB (between one channel and others) f S 192 kHz 108 dB (1) In differential mode at VOUTx pin, f OUT kHz, using Audio Precision System II, RMS mode with 20-kHz low-pass filter and 400-Hz high-pass filter. (2) f S kHz SCKI 512 f S (single), f S kHz SCKI 256 f S (dual), f S 192 kHz SCKI 128 f S (quad). Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): PCM3168A PCM3168A-Q1

www.ti.com SBAS452 SEPTEMBER 2008 ELECTRICAL CHARACTERISTICS: DAC Characteristics (continued) All specifications at T A +25 VCCAD1 VCCAD2 VCCDA1 VCCDA2 VDD1 VDD2 3.3 f S kHz, SCKI 512 f S 24-bit data, Sampling Mode Auto for ADC and DAC, and Interface Mode Slave for ADC and DAC, unless otherwise noted. PCM3168A, PCM3168A-Q1 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG OUTPUT 1.6 Output voltage Differential V PP VCCDA1 0.5 Center voltage V VCCDA1 To ac-coupled GND (3) k Ω Load impedance To dc-coupled GND (3) k Ω f kHz 0.04 dB Low-pass filter frequency response f kHz 0.18 dB DIGITAL FILTER PERFORMANCE (4) Sharp roll-off Passband (single, dual) 0.454 f S Hz Passband (quad) 0.432 f S Hz Stop band (single, dual) 0.546 f S Hz Stop band (quad) 0.569 f S Hz Passband ripple 0.454 f S 0.432 f S 0.0018 dB Stop band attenuation 0.546 f S 0.569 f S dB DIGITAL FILTER PERFORMANCE Slow roll-off Passband 0.328 f S Hz Stop band 0.673 f S Hz Passband ripple 0.328 f S 0.0013 dB Stop band attenuation 0.673 f S dB DIGITAL FILTER PERFORMANCE (4) Group delay time (single, dual) 28/f S sec Group delay time (quad) 19/f S sec De-emphasis error 0.1 dB POWER-SUPPLY REQUIREMENTS VCCxx1/2 4.5 5.0 5.5 VDC Voltage range VDD1/2 3.0 3.3 3.6 VDC f S kHz/ADC, f S kHz/DAC 162 210 mA I CC f S kHz/ADC, f S 192 kHz/DAC 162 mA Full power-down (5) 300 µ A Supply current f S kHz/ADC, f S kHz/DAC 106 130 mA I DD f S kHz/ADC, f S 192 kHz/DAC 127 mA Full power-down (5) µ A f S kHz/ADC, f S kHz/DAC 1160 1480 mW f S kHz/ADC, f S 192 kHz/DAC 1230 mW Power dissipation f S kHz/ADC, Power-down/DAC 660 mW Power-down/ADC, f S kHz/DAC 633 mW Full power-down (5) 1.67 mW (3) Allowable minimum input resistance of differential to single-ended converter with D to S Gain G is calculated as 2G)/(1 for ac-coupled and (1+ 0.9G)/(1 15k for dc-coupled connection, refer to Figure and Figure of the Application Information section. (4) Exclude single and dual at 128 f S 192 f S system clock and quad at 256 f S to 768 f S system clock, and specifications for quad, single, and dual are respectively applied in reverse for them. (5) Halt SCKI, BCKAD, BCKDA, LRCKAD, and LRCKDA. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM3168A PCM3168A-Q1

/c45 VOUT8 /c45 VIN5+ VOUT7+ VIN5 /c45 VOUT7 /c45 VREFAD2 VOUT6+ AREFAD1 VOUT6 /c45 VIN4+ VOUT5+ VIN4 /c45 VOUT5 /c45 VIN3+ VOUT4+ VIN3 /c45 VOUT4 /c45 VIN2+ VOUT3+ VIN2 /c45 VOUT3 /c45 VIN1+ VOUT2+ VIN1 /c45 VOUT2 /c45 AGNDAD1 VOUT1+ VCCAD1 VOUT1 /c45 64 63 62 61 60 59 58 57 56 55 54 17 18 19 20 21 22 23 24 25 26 27 53 52 51 50 49 28 29 30 31 32 PCM3168A PCM3168A-Q1 PowerPAD (Connected□to□Analog□Ground) AGNDDA2 PCM3168A PCM3168A-Q1 SBAS452 SEPTEMBER 2008 www.ti.com ELECTRICAL CHARACTERISTICS: DAC Characteristics (continued) All specifications at T A +25 VCCAD1 VCCAD2 VCCDA1 VCCDA2 VDD1 VDD2 3.3 f S kHz, SCKI 512 f S 24-bit data, Sampling Mode Auto for ADC and DAC, and Interface Mode Slave for ADC and DAC, unless otherwise noted. PCM3168A, PCM3168A-Q1 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEMPERATURE RANGE PCM3168A Consumer grade +85 C Operating temperature PCM3168A-Q1 Automotive audio +105 C grade Thermal resistance θ JA HTQFP-64 +21 C/W HTQFP-64 (12 mm x mm) (10-mm x 10-mm body, 0.5-mm pitch) (TOP VIEW) Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): PCM3168A PCM3168A-Q1

www.ti.com SBAS452 SEPTEMBER 2008 TERMINAL FUNCTIONS TERMINAL PULL- 5-V NAME PIN I/O DOWN TOLERANT V RST I Yes Yes Reset and power-down control input with active low OVF O No No Overflow flag output for ADC LRCKAD I/O Yes No Audio data word clock input/output for ADC BCKAD I/O Yes No Audio data bit clock input/output for ADC DOUT1 O No No Audio data digital output for ADC1 and ADC2 DOUT2 O No No Audio data digital output for ADC3 and ADC4 DOUT3 O No No Audio data digital output for ADC5 and ADC6 DGND2 No No Digital ground VDD2 No No Digital power supply +3.3 V ZERO O No No Zero detect flag output for DAC VCCDA1 No No DAC analog power supply V VCOMDA No No DAC voltage common decoupling AGNDDA1 No No Analog ground for DAC VOUT8+ O No No Positive analog output from DAC8 VOUT8 O No No Negative analog output from DAC8 VOUT7+ O No No Positive analog output from DAC7 VOUT7 O No No Negative analog output from DAC7 VOUT6+ O No No Positive analog output from DAC6 VOUT6 O No No Negative analog output from DAC6 VOUT5+ O No No Positive analog output from DAC5 VOUT5 O No No Negative analog output from DAC5 VOUT4+ O No No Positive analog output from DAC4 VOUT4 O No No Negative analog output from DAC4 VOUT3+ O No No Positive analog output from DAC3 VOUT3 O No No Negative analog output from DAC3 VOUT2+ O No No Positive analog output from DAC2 VOUT2 O No No Negative analog output from DAC2 VOUT1+ O No No Positive analog output from DAC1 VOUT1 O No No Negative analog output from DAC1 AGNDDA2 No No Analog ground for DAC VCCDA2 No No DAC analog power supply V LRCKDA I/O Yes No Audio data word clock input/output for DAC BCKDA I/O Yes No Audio data bit clock input/output for DAC DIN1 I No No Audio data input for DAC1 and DAC2 DIN2 I No No Audio data input for DAC3 and DAC4 DIN3 I No No Audio data input for DAC5 and DAC6 DIN4 I No No Audio data Input for DAC7 and DAC8 SCKI I No Yes System clock input MC/SCL/FMT I No Yes Clock for SPI, clock for I format select for hardware control mode Input data for SPI, data for I C (1) de-emphasis control for hardware MDI/SDA/DEMP I/O No Yes control mode (1) Open-drain configuration in I Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM3168A PCM3168A-Q1

www.ti.com TERMINAL FUNCTIONS (continued) TERMINAL PULL- 5-V NAME PIN I/O DOWN TOLERANT (2) address select for I mode select for MDO/ADR1/MD1 I/O No No hardware control mode Chip select for SPI, address select for I mode select for MS/ADR0/MD0 I Yes Yes hardware control mode VDD1 No No Digital power supply +3.3 V DGND1 No No Digital ground Control port mode selection. Tied to VDD: SPI, pull-up: H/W MODE I No No single-ended input, pull-down: H/W and differential input, tied to DGND: I C VCCAD1 No No ADC analog power supply V AGNDAD1 No No Analog ground for ADC VIN1 I No No Negative analog input to ADC1 VIN1+ I No No Positive analog input to ADC1 VIN2 I No No Negative analog input to ADC2 VIN2+ I No No Positive analog input to ADC2 VIN3 I No No Negative analog input to ADC3 VIN3+ I No No Positive analog input to ADC3 VIN4 I No No Negative analog input to ADC4 VIN4+ I No No Positive analog input to ADC4 VREFAD1 No No ADC analog reference voltage decoupling VREFAD2 No No ADC analog reference voltage decoupling VIN5 I No No Negative analog input to ADC5 VIN5+ I No No Positive analog input to ADC5 VIN6 I No No Negative analog input to ADC6 VIN6+ I No No Positive analog input to ADC6 (2) 3-state (Hi-Z) operation in SPI. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): PCM3168A PCM3168A-Q1

LRCKADBCKADDOUT1DOUT2DOUT3SCKIDIN1DIN2DIN3DIN4LRCKDABCKDA VOUT1/c45 DAC VOUT2+ VOUT2/c45 DAC VOUT3+ VOUT3/c45 DAC VOUT4+ VOUT4/c45 DAC VOUT5+ VOUT5/c45 DAC VOUT6+ VOUT6/c45 ADC VIN1+ VIN1/c45 ADC VIN2+ VIN2/c45 ADC VIN3+ VIN3/c45 ADC VIN4+ VIN4/c45 ADC VIN5+ VIN5/c45 ADC VIN6+ VIN6/c45 VCCAD1/2 VCCDA1/2 AGNDAD1/2 AGNDDA1/2 VDD1 VDD2 DGND1 DGND2 DAC VOUT7+ VOUT7/c45 DAC VOUT8+ VOUT8/c45 VREFAD1VREFAD2VCOMADVCOMDA OVFRST MODE MS/ADR0/MD0MDO/ADR1/MD1MDI/SDA/DEMP MC/SCL/FMT ZERO Audio□Serial□Interface□and□Clock□Control Digital Filter and Volume Digital Filter and Volume Mode□Control□Port (SPI/I C) Common□and Reference PCM3168A PCM3168A-Q1 www.ti.com SBAS452 SEPTEMBER 2008 Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM3168A PCM3168A-Q1

/c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 Amplitude□(dB) Normalized□Frequency□(f )S 0 642 0.20 0.15 0.10 0.05 0.05 0.10 0.15 0.20 /c45 /c45 /c45 /c45 0.5 Amplitude□(dB) Normalized□Frequency□(f )S 0 0.3 0.20.1 0.4 100 120 140 160 180 200 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 Amplitude□(dB) Normalized□Frequency□(f )S 0 321 0.20 0.15 0.10 0.05 0.05 0.10 0.15 0.20 /c45 /c45 /c45 /c45 0.5 Amplitude□(dB) Normalized□Frequency□(f )S 0 0.3 0.20.1 0.4 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 0.0010 Amplitude□(dB) Normalized□Frequency□(f )S 0 0.0006 0.00040.0002 0.0008 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 0.0 0.010 Amplitude□(dB) Normalized□Frequency□(f )S 0 0.006 0.0040.002 0.008 PCM3168A PCM3168A-Q1 SBAS452 SEPTEMBER 2008 www.ti.com ADC Digital Filter All specifications at T A +25 VCCAD1 VCCAD2 VCCDA1 VCCDA2 VDD1 VDD2 3.3 f S kHz, SCKI 512 f S 24-bit data, Sampling Mode Auto for ADC and DAC, and Interface Mode Slave for ADC and DAC, unless otherwise noted. FREQUENCY RESPONSE FREQUENCY RESPONSE PASSBAND (Single Rate) (Single Rate) Figure Figure FREQUENCY RESPONSE FREQUENCY RESPONSE PASSBAND (Dual Rate) (Dual Rate) Figure Figure HPF FREQUENCY RESPONSE HPF FREQUENCY RESPONSE PASSBAND Figure Figure Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): PCM3168A PCM3168A-Q1

/c45 /c45 /c45 /c45 /c45 /c45 /c45 Amplitude□(dB) Normalized□Frequency□(f )S 0 321 Sharp Slow 0.010 0.008 0.006 0.004 0.002 0.002 0.004 0.006 0.008 0.010 /c45 /c45 /c45 /c45 /c45 0.5 Amplitude□(dB) Normalized□Frequency□(f )S 0 0.3 0.20.1 0.4 Sharp Slow 100 120 140 /c45 /c45 /c45 /c45 /c45 /c45 /c45 Amplitude□(dB) Normalized□Frequency□(f )S 0 321 Sharp Slow 0.010 0.008 0.006 0.004 0.002 0.002 0.004 0.006 0.008 0.010 /c45 /c45 /c45 /c45 /c45 0.5 Amplitude□(dB) Normalized□Frequency□(f )S 0 0.3 0.20.1 0.4 Sharp Slow 100 120 140 /c45 /c45 /c45 /c45 /c45 /c45 /c45 2.0 Amplitude□(dB) Normalized□Frequency□(f )S 0 1.51.00.5 Sharp Slow 0.010 0.008 0.006 0.004 0.002 0.002 0.004 0.006 0.008 0.010 /c45 /c45 /c45 /c45 /c45 0.5 Amplitude□(dB) Normalized□Frequency□(f )S 0 0.3 0.20.1 0.4 Sharp Slow PCM3168A PCM3168A-Q1 www.ti.com SBAS452 SEPTEMBER 2008 All specifications at T A +25 VCCAD1 VCCAD2 VCCDA1 VCCDA2 VDD1 VDD2 3.3 f S kHz, SCKI 512 f S 24-bit data, Sampling Mode Auto for ADC and DAC, and Interface Mode Slave for ADC and DAC, unless otherwise noted. FREQUENCY RESPONSE FREQUENCY RESPONSE PASSBAND (Single Rate) (Single Rate) Figure Figure FREQUENCY RESPONSE FREQUENCY RESPONSE PASSBAND (Dual Rate) (Dual Rate) Figure Figure 10. FREQUENCY RESPONSE FREQUENCY RESPONSE PASSBAND (Quad Rate) (Quad Rate) Figure 11. Figure 12. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM3168A PCM3168A-Q1

/c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 Amplitude□(dB) Frequency□(kHz) 0 6 42 8 10 12 14 16 18 20 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 Amplitude□(dB) Frequency□(kHz) 0 6 42 8 10 12 14 16 18 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 Amplitude□(dB) Frequency□(kHz) 0 6 42 8 10 12 /c45 /c45 /c45 /c45 /c45 10M Amplitude□(dB) Frequency□(Hz) 1k 10k 100k 1M PCM3168A PCM3168A-Q1 SBAS452 SEPTEMBER 2008 www.ti.com DAC Digital Filter (continued) All specifications at T A +25 VCCAD1 VCCAD2 VCCDA1 VCCDA2 VDD1 VDD2 3.3 f S kHz, SCKI 512 f S 24-bit data, Sampling Mode Auto for ADC and DAC, and Interface Mode Slave for ADC and DAC, unless otherwise noted. DE-EMPHASIS CHARACTERISTIC DE-EMPHASIS CHARACTERISTIC S kHz) S kHz) Figure 13. Figure 14. DE-EMPHASIS CHARACTERISTIC S kHz) ANALOG FILTER CHARACTERISTIC Figure 15. Figure 16. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): PCM3168A PCM3168A-Q1

/c45 /c45 /c45 /c45 /c45 /c45 /c45 100 125 THD+N□(dB) T emperature□( C)/c176 /c45 50 /c45 25 0 25 50 75 100 112 110 108 106 104 102 100 125 Dynamic□Range□and□SNR□(dB) T emperature□( C)/c176 /c45 50 /c45 25 0 25 50 75 SNR Dynamic□Range 100 /c45 /c45 /c45 /c45 /c45 /c45 100/c45 5.50 THD+N□(dB) Supply□Voltage□(V) 4.50 4.75 5.00 5.25 112 110 108 106 104 102 100 5.50 Dynamic□Range□and□SNR□(dB) Supply□Voltage□(V) 4.50 4.75 5.00 5.25 SNR Dynamic□Range PCM3168A PCM3168A-Q1 www.ti.com SBAS452 SEPTEMBER 2008 All specifications at T A +25 VCCAD1 VCCAD2 VCCDA1 VCCDA2 VDD1 VDD2 3.3 f S kHz, SCKI 512 f S 24-bit data, Sampling Mode Auto for ADC and DAC, and Interface Mode Slave for ADC and DAC, unless otherwise noted. THD+N AT dB DYNAMIC RANGE AND SNR vs TEMPERATURE vs TEMPERATURE Figure 17. Figure 18. THD+N AT dB DYNAMIC RANGE AND SNR vs SUPPLY VOLTAGE vs SUPPLY VOLTAGE Figure 19. Figure 20. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM3168A PCM3168A-Q1

/c45 /c45 /c45 /c45 /c45 /c45 100 102/c45 125 THD+N□(dB) T emperature□( C)/c176 /c45 50 /c45 25 0 25 50 75 100 116 114 112 110 108 106 104 125 Dynamic□Range□and□SNR□(dB) T emperature□( C)/c176 /c45 50 /c45 25 0 25 50 75 SNR Dynamic□Range 100 100 102 /c45 /c45 /c45 /c45 /c45 /c45 /c45 5.50 THD+N□(dB) Supply□Voltage□(V) 4.50 4.75 5.00 5.25 116 114 112 110 108 106 104 5.50 Dynamic□Range□and□SNR□(dB) Supply□Voltage□(V) 4.50 4.75 5.00 5.25 SNR Dynamic□Range PCM3168A PCM3168A-Q1 SBAS452 SEPTEMBER 2008 www.ti.com All specifications at T A +25 VCCAD1 VCCAD2 VCCDA1 VCCDA2 VDD1 VDD2 3.3 f S kHz, SCKI 512 f S 24-bit data, Sampling Mode Auto for ADC and DAC, and Interface Mode Slave for ADC and DAC, unless otherwise noted. DYNAMIC RANGE AND SNR THD+N vs TEMPERATURE vs TEMPERATURE Figure 21. Figure 22. DYNAMIC RANGE AND SNR THD+N vs SUPPLY VOLTAGE vs SUPPLY VOLTAGE Figure 23. Figure 24. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): PCM3168A PCM3168A-Q1

/c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 Amplitude□(dB) Frequency□(kHz) 0 5 10 15 100 120 140 160 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 Amplitude□(dB) Frequency□(kHz) 0 5 10 15 100 120 140 160 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 Amplitude□(dB) Frequency□(kHz) 0 5 10 15 100 120 140 160 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 Amplitude□(dB) Frequency□(kHz) 0 5 10 15 PCM3168A PCM3168A-Q1 www.ti.com SBAS452 SEPTEMBER 2008 All specifications at T A +25 VCCAD1 VCCAD2 VCCDA1 VCCDA2 VDD1 VDD2 3.3 f S kHz, SCKI 512 f S 24-bit data, Sampling Mode Auto for ADC and DAC, and Interface Mode Slave for ADC and DAC, unless otherwise noted. ADC OUTPUT SPECTRUM ADC OUTPUT SPECTRUM dB, N 32,768) dB, N 32,768) Figure 25. Figure 26. DAC OUTPUT SPECTRUM DAC OUTPUT SPECTRUM dB, N 32,768) dB, N 32,768) Figure 27. Figure 28. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM3168A PCM3168A-Q1

-Supply□Current□(mA) Power-Save□Condition Operation ADC□OffDAC□Off Clock□Off ICC IDD PCM3168A PCM3168A-Q1 SBAS452 SEPTEMBER 2008 www.ti.com All specifications at T A +25 VCCAD1 VCCAD2 VCCDA1 VCCDA2 VDD1 VDD2 3.3 f S kHz, SCKI 512 f S 24-bit data, Sampling Mode Auto for ADC and DAC, and Interface Mode Slave for ADC and DAC, unless otherwise noted. POWER-SUPPLY CURRENT vs POWER-SAVE CONDITION Figure 29. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): PCM3168A PCM3168A-Q1

www.ti.com SBAS452 SEPTEMBER 2008 The PCM3168A and PCM3168A-Q1 are high-performance, multi-channel codecs targeted for automotive audio amplifiers, as well as home multi-channel audio (for example, home theaters and A/V receivers). The PCM3168A and PCM3168A-Q1 consist of six-channel analog-to-digital converters (ADCs) and eight-channel digital-to-analog converters (DACs). The ADC input is selectable between single-ended and differential inputs. The DAC output type is fixed with a differential configuration. The PCM3168A and PCM3168A-Q1 support 24-bit linear PCM input and output data in standard audio formats (left-justified, right-justified, and I S), DSP and TDM formats, and various sample frequencies from kHz to 192 kHz (the ADC configuration supports only up to kHz). The TDM format is useful to save interface bus line numbers for multi-channel audio data communication between the codec and digital audio processor. The PCM3168A and PCM3168A-Q1 offer three modes for device control: two-wire I C software, four-wire SPI software, and hardware modes. The PCM3168A and PCM3168A-Q1 include six ADCs, each with individual pairs of differential voltage input pins, as shown in Table Additionally, the PCM3168A and PCM3168A-Q1 have the capability of single-ended inputs. The full-scale input voltage is (0.2 VCCAD1) V RMS at the single-ended input mode and (0.4 VCCAD1) V RMS at the differential input mode. The input mode is selected by the MODE pin in hardware control mode or by register settings in the software control mode. In single-ended mode, VINx+ pins are used and VINx pins must be terminated with AGNDAD1/2 via a capacitor or terminated with VCOMAD. Table Pin Assignments in Differential and Single-Ended Input Modes CHANNEL DIFFERENTIAL INPUT MODE SINGLE-ENDED INPUT MODE (ADC1) VIN1+, VIN1 VIN1+ (ADC2) VIN2+, VIN2 VIN2+ (ADC3) VIN3+, VIN3 VIN3+ (ADC4) VIN4+, VIN4 VIN4+ (ADC5) VIN5+, VIN5 VIN5+ (ADC6) VIN6+, VIN6 VIN6+ The PCM3168A and PCM3168A-Q1 include eight DACs, each with individual pairs of differential voltage inputs pins, as shown in Table The full-scale output voltage is (1.6 VCCDA1) V PP in differential mode. DC-coupled loads are allowed in addition to ac-coupled loads if the load resistance conforms to the specification. Table Pin Assignments for Differential Output CHANNEL DIFFERENTIAL OUTPUT (DAC1) VOUT1+, VOUT1 (DAC2) VOUT2+, VOUT2 (DAC3) VOUT3+, VOUT3 (DAC4) VOUT4+, VOUT4 (DAC5) VOUT5+, VOUT5 (DAC6) VOUT6+, VOUT6 (DAC7) VOUT7+, VOUT7 (DAC8) VOUT8+, VOUT8 Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM3168A PCM3168A-Q1

System□Clock (SCKI) High Low tSCL tSCH tSCY 2.0□V 0.8□V SAMPLING MODE PCM3168A PCM3168A-Q1 SBAS452 SEPTEMBER 2008 www.ti.com The PCM3168A and PCM3168A-Q1 include two internal references for the six-channel ADCs; these references correspond to the outputs VREFAD1 and VREFAD2. Both reference pins should be connected with an analog ground via decoupling capacitors. In addition, the PCM3168A and PCM3168A-Q1 include two pins for common-mode voltage output (VCOMDA for DACs and VCOMAD for ADCs). These pins should be also connected with an analog ground via decoupling capacitors. Furthermore, both common pins can be used to bias external high-impedance circuits, if they are required. The PCM3168A and PCM3168A-Q1 require an external system clock input applied at the SCKI input for ADC and DAC operation. The system clock operates at an integer multiple of the sampling frequency, or f S The multiples supported in ADC operation include 256 f S 384 f S 512 f S and 768 f S the multiples supported in DAC operation include 128 f S 192 f S 256 f S 384 f S 512 f S and 768 f S Details for these system clock multiples are shown in Table Figure and Table show the SCKI timing requirements. Table System Clock Frequencies for Common Audio Sampling Rates SAMPLING DEFAULT FREQUENCY SYSTEM CLOCK FREQUENCY (MHz) SAMPLING MODE f S (kHz) 128 f S (1) 192 f S (1) 256 f S 384 f S 512 f S 768 f S N/A N/A 2.0480 3.0720 (2) 4.0960 6.1440 2.0480 (1) 3.0720 (1) 4.0960 6.1440 (2) 8.1920 12.2880 Single rate 4.0960 (1) 6.1440 (1) 8.1920 12.2880 (2) 16.3840 24.5760 44.1 5.6488 (1) 8.4672 (1) 11.2896 16.9344 (2) 22.5792 33.8688 6.1440 (1) 9.2160 (1) 12.2880 18.4320 (2) 24.5760 36.8640 88.2 11.2896 (3) 16.9344 (3) 22.5792 33.8688 N/A N/A Dual rate 12.2880 (3) 18.4320 (3) 24.5760 36.8640 N/A N/A 176.4 (3) 22.5792 (3) 33.8688 (3) N/A N/A N/A N/A Quad rate (3) 192 (3) 24.5760 (3) 36.8640 (3) N/A N/A N/A N/A (1) Supported only by DAC operation (2) Requires 50% duty cycle for stable ADC performance. (3) Supported only by DAC operation Figure 30. System Clock Timing Requirements Table Timing Requirements for Figure SYMBOL PARAMETER MIN MAX UNIT t SCY System clock pulse cycle time ns t SCH System clock pulse width high ns t SCL System clock pulse width low ns t DTY System clock pulse duty cycle The PCM3168A and PCM3168A-Q1 support two sampling modes (single rate and dual rate) in ADC operation, and three sampling modes (single rate, dual rate, and quad rate) in DAC operation. In single rate mode, the ADC and DAC operate at an oversampling frequency of x128 (except when SCKI 128 f S and 192 f S This mode is supported for sampling frequencies less than kHz. In dual rate mode, the ADC and DAC operate at an Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): PCM3168A PCM3168A-Q1

/c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 2.0 Amplitude□(dB) Normalized□Frequency□(f )S 0 0.5 1.0 1.5 DSM_Dual DSM_Single DF_Single DF_Dual 100 120 140 160 180 200 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 2.0 Amplitude□(dB) Normalized□Frequency□(f )S 0 0.5 1.0 1.5 DSM_Dual DSM_Single DSM_Quad DF_Dual DF_Single DF_Quad PCM3168A PCM3168A-Q1 www.ti.com SBAS452 SEPTEMBER 2008 oversampling frequency of x64; this mode is supported for sampling frequencies less than 100 kHz. In quad rate mode, the DAC operates at an oversampling frequency of x32. The sampling mode is automatically selected according to the ratio of system clock frequency and sampling frequency by default (for example, single rate for 512 f S and 768 f S dual rate for 256 f S and 384 f S and quad rate for 128 f S and 192 f S but manual selection is also possible for specified combinations through the serial mode control resistor. Table and Figure show the relation between the oversampling rate (OSR) of the Δ Σ modulator, noise-free shaped bandwidth, and each sampling mode setting for ADC operation. Table and Figure describe the relation between the oversampling rate of the digital filter and Δ Σ modulator, noise-free shaped bandwidth, and each sampling mode setting for DAC operation. Table ADC Modulator OSR and Noise-Free Shaped Bandwidthfor Each Sampling Mode NOISE-FREE SHAPED BANDWIDTH (kHz) SAMPLING MODE SYSTEM CLOCK RATE REGISTER SETTING S f S kHz f S kHz MODULATOR OSR 512, 768 N/A x128 Auto 256, 384 x64 512, 768 N/A x128 Single 256, 384 N/A x128 Dual 256, 384 x64 Table DAC Digital Filter OSR, Modulator OSR, and Noise-Free Shaped Bandwidth for Each Sampling Mode NOISE-FREE SHAPED BANDWIDTH SAMPLING MODE SYSTEM CLOCK f S f S f S 192 REGISTER SETTING RATE S kHz kHz kHz DIGITAL FILTER OSR MODULATOR OSR 512, 768 N/A N/A x128 Auto 256, 384 N/A x64 128, 192 (1) (2) x32 512, 768 N/A N/A x128 Single 256, 384 N/A N/A x128 128, 192 (1) (2) N/A N/A x64 256, 384 N/A x64 Dual 128, 192 (1) (2) N/A x64 Quad 128, 192 (1) (2) x32 (1) Supported only by DAC operation. (2) Quad mode filter characteristic is applied. Figure 31. ADC Δ Σ Modulator and Digital Filter Figure 32. DAC Δ Σ Modulator and Digital Filter Characteristic Characteristic Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM3168A PCM3168A-Q1

VDD 0□V

0.5 VCC/c180

(VDD□=□3.3□V,□typ) tADCDL Y2 tDACDL Y2 Fade-InZERO VCOMDA (0.5 VCCDA1)/c180

3846 SCKI/c180

Normal□Operation Synchronous□Clocks (VDD□=□2.2□V,□typ) RST Internal□Reset VOUT1 to VOUT8 /c177 /c177 DOUT1/2/3 SCKI, BCKAD/DA, LRCKAD/DA tADCDL Y1 tDACDL Y1 PCM3168A PCM3168A-Q1 SBAS452 SEPTEMBER 2008 www.ti.com The PCM3168A and PCM3168A-Q1 have both an internal power-on reset circuit and an external reset circuit. The sequences for both reset circuits are illustrated in Figure Table and Figure Figure and Table describe the timing chart at the internal power-on reset. Initialization is triggered automatically at the point where VDD exceeds 2.2 V typical, and the internal reset is released after 3846 SCKI clock cycles from power-on if RST is kept high and SCKI is provided. VOUT from the DACs are forced to the VCOMDA level initially 0.5 VCCDA1) and settles at a specified level according to the rising VCC. If synchronization among SCKI, BCKAD/DA, and LRCKAD/DA is maintained, VOUT starts to output with a fade-in sequence after t DACDLY1 from the internal reset release; VOUT then provides an output that corresponds to DIN after (3846 SCKI t DACDLY1 t DACDLY2 from power-on. Meanwhile, DOUT from the ADCs begins to output with a fade-in sequence after t ADCDLY1 from the internal reset release; DOUT then provides output corresponding to VIN after (3846 SCKI t ADCDLY1 t ADCDLY2 from power-on. If the synchronization is not held, the internal reset is not released and both operating modes are maintained at reset and power-down states; after the synchronization forms again, both the DAC and ADC return to normal operation with the above sequences. Figure illustrates a timing chart at the external reset. RST accepts an external forced reset by RST low, and provides a device reset and power-down state that makes the lowest power dissipation state available in the PCM3168A and PCM3168A-Q1. If RST goes from high to low under synchronization among SCKI, BCKAD/DA, and LRCKAD/DA, the internal reset is asserted, all registers and memory are reset, and finally the PCM3168A and PCM3168A-Q1 enter into all power-down states. At the same time, VOUT is immediately forced into the AGNDDA1 level and DOUT becomes '0'. To begin normal operation again, toggle RST high; the same power-up sequence as power-on reset shown in Figure is performed. The PCM3168A and PCM3168A-Q1 do not require particular power-on sequences for VCC and VDD; it allows VDD on and then VCC on, or VCC on and then VDD on. From the viewpoint of the Absolute Maximum Ratings however, simultaneous power-on is recommended for avoiding unexpected responses on VOUTx and DOUTx. Figure illustrates the response for VCC on with VDD on. Figure 33. Power-On-Reset Timing Requirements Table Timing Requirements for Figure SYMBOL t DACDLY1 3600 7200 14400 Period of LRCKDA VOUT start t DACDLY2 DAC fade-in/fade-out time 2048 4096 8192 Period of LRCKDA ADC delay time internal reset release to t ADCDLY1 4800 9600 N/A Period of LRCKAD DOUT start t ADCDLY2 ADC fade-in/fade-out time 2048 4096 N/A Period of LRCKAD Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): PCM3168A PCM3168A-Q1

Synchronous□Clocks ZERO Power-Down Normal□OperationNormal□Operation Synchronous□Clocks 0□V SCKI, BCKAD/DA, LRCKAD/DA RST Internal□Reset VOUT1 to VOUT8 /c177 /c177 DOUT1/2/3 tADCDL Y2 tDACDL Y1 tDACDL Y2 (VDD□=□3.3□V,□typ) 100□ns□(min) tADCDL Y1 AUDIO SERIAL PORT OPERATION AUDIO DATA INTERFACE FORMATS AND TIMING PCM3168A PCM3168A-Q1 www.ti.com SBAS452 SEPTEMBER 2008 Figure 34. External Reset Timing Requirements The PCM3168A and PCM3168A-Q1 audio serial ports consist of signals: BCKDA, BCKAD, LRCKDA, LRCKAD, DIN1, DIN2, DIN3, DIN4, DOUT1, DOUT2, and DOUT3. The PCM3168A and PCM3168A-Q1 also support audio interface mode, slave mode, and master mode. The BCKAD/DA is a bit clock input at the slave mode and an output at the master mode. The LRCKAD/DA is a left/right word clock or frame synchronization clock input at slave mode and output at master mode. The DIN1/2/3/4 are the audio data inputs for the DAC. The DOUT1/2/3 are the audio data outputs from the ADC. BCKAD, LRCKAD and DOUT1/2/3 are used for the ADC, and BCKDA, LRCKDA and DIN1/2/3/4 are used for the DAC. The PCM3168A and PCM3168A-Q1 support eight audio data interface formats for the ADC and DAC separately in both master and slave modes: 24-bit I 24-bit left-justified, 24-bit right-justified, 16-bit right-justified, 24-bit left-justified mode DSP, 24-bit I S mode DSP, 24-bit left-justified mode TDM, and 24-bit I S mode TDM format. The PCM3168A and PCM3168A-Q1 also support two audio data interface formats for the DAC and slave mode: 24-bit left-justified mode high-speed TDM and 24-bit I S mode high-speed TDM format. In the case of I left-justified, and right-justified data formats, BCKs, BCKs, and BCKs per LRCK period are supported, but BCKs are limited in slave mode and BCKs are limited in slave mode 16-bit right-justified only. In the case of TDM data format in single rate, BCKAD/DA, LRCKAD/DA, DOUT1, and DIN1 are used. In the case of TDM data format in dual rate, BCKAD/DA, LRCKAD/DA, DOUT1/2, and DIN1/2 are used. In the case of high-speed TDM format in dual rate, BCKDA, LRCKDA, and DIN1 are used. In the case of high-speed TDM format in quad rate, BCKDA, LRCKDA, and DIN1/2 are used. TDM format and high-speed TDM format are supported only at SCKI 512 f S 256 f S 128 f S and f BCK f SCKI The audio data formats are selected by MC/SCL/FMT in hardware control mode and registers and in software control mode. All data must be in binary twos complement, MSB first. Figure through Figure show audio interface data formats. Table summarizes the applicable formats and describes the relationships among them and the respective restrictions with mode control. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM3168A PCM3168A-Q1

www.ti.com Table Audio Data Interface Formats and Sampling Rate, Bit Clock, and System Clock Restrictions CONTROL MAX LRCK MODE FORMAT I/F MODE DATA BITS FREQUENCY S SCKI RATE (xf S BCK RATE (xf S APPLICABLE PINS 64, (slave) (1) I S/Left-Justified 64, (slave) (1) Right-Justified 24, kHz (ADC) 256 to 768 (ADC) DOUT1/2/3 (slave, bit) (1) 192 kHz (DAC) 128 to 768 (DAC) DIN1/2/3/4 Master/Slave I S/Left-Justified DSP Software control kHz 256, 512 256 DOUT1, DIN1 I Left-Justified TDM kHz 128 (DAC) (2) 256 128 DOUT1/2, DIN1/2 High-Speed kHz 256 256 DIN1 Slave and I S/Left-Justified DAC Only (3) 192 kHz 128 128 DIN1/2 TDM kHz (ADC) 256 to 768 (ADC) DOUT1/2/3 64, (slave) (1) I S 192 kHz (DAC) 128 to 768 (DAC) DIN1/2/3/4 Hardware Master control (ADC), Slave kHz 512 256 DOUT1, DIN1 I S TDM kHz 256 128 DOUT1/2, DIN1/2 (1) BCK f S f S is supported only in slave mode; BCK f S is supported only for 16-bit data length. (2) SCKI 128 f S is supported only for DAC. (3) High-Speed I S/Left-Justified TDM format is supported only for DAC operation in slave mode. Figure 35. Audio Data Format: 24-Bit I S Figure 36. Audio Data Format: 24-Bit Left-Justified Figure 37. Audio Data Format: 24-Bit Right-Justified Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): PCM3168A PCM3168A-Q1

1/f (64□BCKs)S LRCKAD/DA BCKAD/DA I S□Mode DIN1/2/3/4 DOUT1/2/3 Left-Justified□Mode DIN1/2/3/4 DOUT1/2/3 23 22 21 2 1 0 23 22 21 2 1 0 23 22 21 2 1 0 23 22 23 22 21 23 2221 2 1 0 LRCKAD/DA (Master) LRCKAD/DA (Slave) BCKAD/DA Left-Justified□Mode DIN1,□DOUT1 (Single) I S□Mode DIN1,□DOUT1 (Single) Left-Justified□Mode DIN1/2,□DOUT1/2 (Dual) I S□Mode2 DIN1/2,□DOUT1/2 (Dual) 1/f (256□BCKs□at□Single□Rate,□128□BCKs□at□Dual□Rate)S 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 23 22 0 23 22 1 0 23 22 1 0 23 22 1 0 23 22 23 22 1 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 23 22 0 23 22 1 0 1 0 1 0 23 22 23 22 1 023 22 23 22 Ch□1 32□BCKs Ch□2 32□BCKs Ch□3 32□BCKs Ch□4 32□BCKs Ch□5 32□BCKs Ch□6 32□BCKs Ch□7 32□BCKs Ch□8 32□BCKs Ch□1/Ch□5 32□BCKs Ch□2/Ch□6 32□BCKs Ch□3/Ch□7 32□BCKs Ch□4/Ch□8 32□BCKs PCM3168A PCM3168A-Q1 www.ti.com SBAS452 SEPTEMBER 2008 Figure 38. Audio Data Format: 16-Bit Right-Justified Figure 39. Audio Data Format: 24-Bit DSP Format Figure 40. Audio Data Format: 24-Bit TDM Format (SCKI 128 f S 256 f S and 512 f S Only) Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM3168A PCM3168A-Q1

(Slave) BCKDA Left-Justified□Mode DIN1 (Dual) I S□Mode DIN1 (Dual) Left-Justified□Mode DIN1/2 (Quad) I S□Mode2 DIN1/2 (Quad) 1/f (256□BCKs□at□Dual□Rate,□128□BCKs□at□Quad□Rate)S 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 23 22 0 23 22 1 0 23 22 1 0 23 22 1 0 23 22 23 22 1 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 23 22 0 23 22 1 0 1 0 1 0 23 22 23 22 1 023 22 23 22 Ch□1 32□BCKs Ch□2 32□BCKs Ch□3 32□BCKs Ch□4 32□BCKs Ch□5 32□BCKs Ch□6 32□BCKs Ch□7 32□BCKs Ch□8 32□BCKs Ch□1/Ch□5 32□BCKs Ch□2/Ch□6 32□BCKs Ch□3/Ch□7 32□BCKs Ch□4/Ch□8 32□BCKs AUDIO INTERFACE TIMING BCKAD/DA (Input) 1.4□V 1.4□V 1.4□V

0.5 VDD/c180

t LRS tDOD LRCKAD/DA (Input) DOUT1/2/3 DIN1/2/3/4 tDIH tLRH tDIS tBCH tBCL tBCY PCM3168A PCM3168A-Q1 SBAS452 SEPTEMBER 2008 www.ti.com Figure 41. Audio Data Format: 24-Bit High-Speed TDM Format (SCKI 128 f S 256 f S DAC, and Slave Mode Only) Figure through Figure describe the detailed interface timing specifications. Figure 42. Audio Interface Timing Requirements for Left-Justified, Right-Justified, and I S Data Formats (Slave Mode) Table Timing Requirements for Figure (1) SYMBOL t BCY BCKAD/DA cycle time ns t BCH BCKAD/DA pulse width high ns t BCL BCKAD/DA pulse width low ns t LRS LRCKAD/DA setup time to BCKAD/DA rising edge ns t LRH LRCKAD/DA hold time to BCKAD/DA rising edge ns t DIS DIN1/2/3/4 setup time to BCKDA rising edge ns t DIH DIN1/2/3/4 hold time to BCKDA rising edge ns t DOD DOUT1/2/3 delay time from BCKAD falling edge ns (1) Load capacitance of output is pF. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): PCM3168A PCM3168A-Q1

(Output) tLRD tDOD 1.4□V LRCKAD/DA (Output) DOUT1/2/3 DIN1/2/3/4 tBCH tBCL tBCY tDIS tDIH tDOD tLRS 1.4□V 1.4□V 1.4□VBCKAD/DA (Input) LRCKAD/DA (Input) DOUT1/2/3 DIN1/2/3/4 tBCH tBCL tBCY tLRH tDIS tDIH tLRW PCM3168A PCM3168A-Q1 www.ti.com SBAS452 SEPTEMBER 2008 Figure 43. Audio Interface Timing Requirements for Left-Justified, Right-Justified, and I S Data Formats (Master Mode) Timing Requirements for Figure (1) SYMBOL t BCY BCKAD/DA cycle time 1/(64 f S t BCH BCKAD/DA pulse width high 0.4 t BCY 0.5 t BCY 0.6 t BCY t BCL BCKAD/DA pulse width low 0.4 t BCY 0.5 t BCY 0.6 t BCY t LRD LRCKAD/DA delay time from BCKAD/DA falling edge ns t DIS DIN1/2/3/4 setup time to BCKDA rising edge ns t DIH DIN1/2/3/4 hold time to BCKDA rising edge ns t DOD DOUT1/2/3 delay time from BCKAD falling edge ns (1) Load capacitance of output is pF. Figure 44. Audio Interface Timing Requirements for DSP and TDM Data Formats (Slave Mode) Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM3168A PCM3168A-Q1

(Output) LRCKAD/DA (Output) DOUT1/2/3 DIN1/2/3/4 tDOD tLRD 1.4□V www.ti.com Timing Requirements for Figure (1) SYMBOL t BCY BCKDA cycle time ns BCKAD pulse width high ns t BCH BCKDA pulse width high ns BCKAD pulse width low ns t BCL BCKDA pulse width low ns LRCKAD/DA pulse width high (DSP format) t BCY t LRW LRCKAD/DA pulse width high (TDM format) t BCY 1/f S t BCY t LRS LRCKAD/DA setup time to BCKAD/DA rising edge ns t LRH LRCKAD/DA hold time to BCKAD/DA rising edge ns t DIS DIN1/2/3/4 setup time to BCKDA rising edge ns t DIH DIN1/2/3/4 hold time to BCKDA rising edge ns t DOD DOUT1/2/3 delay time from BCKAD falling edge ns (1) Load capacitance of output is pF. Figure 45. Audio Interface Timing Requirements for DSP and TDM Data Formats (Master Mode) Timing Requirements for Figure (1) SYMBOL (DSP format) 1/(64 f S t BCY BCKAD/DA cycle time (TDM format, single rate) 1/(256 f S BCKAD/DA cycle time (TDM format, dual rate) 1/(128 f S t BCH BCKAD/DA pulse width high 0.4 t BCY 0.5 t BCY 0.6 t BCY t BCL BCKAD/DA pulse width low 0.4 t BCY 0.5 t BCY 0.6 t BCY LRCKAD/DA pulse width high (DSP format) t BCY t LRW LRCKAD/DA pulse width high (TDM format) 1/(2 f S t LRD LRCKAD/DA delay time from BCKAD/DA falling edge ns t DIS DIN1/2/3/4 setup time to BCKDA rising edge ns t DIH DIN1/2/3/4 hold time to BCKDA rising edge ns t DOD DOUT1/2/3 delay time from BCKAD falling edge ns (1) Load capacitance of output is pF. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): PCM3168A PCM3168A-Q1

State□of Synchronization Synchronous Normal Normal ZERO Normal Normal SynchronousAsynchronous DAC VOUTX/c177 ADC DOUTX VCOMDA (0.5VCCDA1) Within□1/f S tADCDL Y3 tDACDL Y3 Undefined□Data Undefined□Data HIGH-PASS FILTER (HPF) PCM3168A PCM3168A-Q1 www.ti.com SBAS452 SEPTEMBER 2008 The PCM3168A and PCM3168A-Q1 operate under the system clock (SCKI) and the audio sampling rate (LRCKAD/DA). Therefore, SCKI and LRCKAD/DA must have a specific relationship in slave mode. The PCM3168A and PCM3168A-Q1 do not need a specific phase relationship between the audio interface clocks (LRCKAD/DA, BCKAD/DA) and the system clock (SCKI), but does require a specific frequency relationship (ratiometric) between LRCKAD/DA, BCKAD/DA, and SCKI. If the relationship between SCKI and LRCKDA changes more than BCKDA clocks because of jitter, sampling frequency change, etc., the DAC internal operation halts within 1/f S and the analog output is forced into VCOMDA (0.5 VCCDA1) until re-synchronization between SCKI, LRCKDA, and BCKDA is completed and then t DACDLY3 passes. If the relationship between SCKI and LRCKAD changes more than BCKADs because of jitter, sampling frequency change, etc., the ADC internal operation halts within 1/f S and the digital output is forced into a '0' code until re-synchronization between SCKI, LRCKAD, and BCKAD is completed and then t ADCDLY3 passes. In the event the change is less than BCKAD/DAs, re-synchronization does not occur, and this analog/digital output control and discontinuity do not occur. Figure shows the DAC analog output and ADC digital output for loss of synchronization. During undefined data periods, some noise may be generated in the audio signal. Also, the transition of normal to undefined data and undefined (or zero) data to normal data creates a discontinuity of data on the analog and digital outputs, which then may generate some noise in the audio signal. Both ADC outputs (DOUTx) and DAC outputs (VOUTx) hold the previous state if the system clock halts, but the asynchronous and re-synchronization processes would occur after the system clock resumes. Figure shows DAC outputs and ADC outputs for loss of synchronization. Figure 46. DAC Outputs and ADC Outputs for Loss of Synchronization Timing Requirements for Figure SYMBOL t DACDLY3 DAC delay synchronization detect to normal data LRCKDA Period of t ADCDLY3 ADC delay synchronization detect to normal data N/A LRCKAD The PCM3168A and PCM3168A-Q1 include a high-pass filter (HPF) for all ADC channels in order to remove the dc component of the digitized input signal. The filter is located at the output of the digital decimation filter. The dB corner frequency for the HPF scales with the output sampling rate, where f dB 0.020 f S /1000. When f S kHz, f dB is 0.96 Hz. The HPF function can be disabled (bypassed) by the BYP bits in two channels. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM3168A PCM3168A-Q1

www.ti.com The PCM3168A and PCM3168A-Q1 include an overflow flag output for all ADC channels. As soon as any of the six-channel ADC digital outputs exceed the full-scale range, an overflow flag is forced high on the OVF pin. The overflow flag is held high for 1024 LRCKAD clock cycles. In parallel, overflow flag information is stored in the OVF bits of the mode control register, and the OVF bit is held until the mode control register is read. The overflow flag polarity can be changed by the OVFP bit. The OVF pin also indicates internal reset completion by transmitting a 4096 SCKI width pulse. The PCM3168A and PCM3168A-Q1 include a zero flag output for all DAC channels. When all of the eight-channel DACs digital inputs have continued as zero data for 1024 LRCKDA clock cycles, the zero flag is forced high on ZERO. In parallel, zero flag information is stored in the ZERO bits according to channel. The zero flag polarity can be changed by the ZREV bit. Also, the zero flag function can be selected by the AZRO bits. AND or OR logic for stereo, six channels, and eight channels can be selected. The PCM3168A and PCM3168A-Q1 include four-way mode control selectable by MODE pin, as shown in Table The pull-up and pull-down resistors must be 220 k Ω 5%. This mode control selection is sampled only when the internal reset is released by a power-on reset or by a low-to-high transition of the external reset (RST pin); a system clock is also required. Table 10. Mode Control Selection MODE MODE CONTROL INTERFACE Tied to DGND Two-wire serial control, selectable analog input configuration Tied to DGND via pull-down resistor H/W (hardware control), differential analog input Tied to VDD via pull-up resistor H/W (hardware control), single-ended analog input Tied to VDD Four-wire (SPI) serial control, selectable analog input configuration From the mode control selection described in Table the functions of four pins are changed, as shown in Table Table 11. Pin Functions PIN ASSIGNMENTS PIN SPI I C H/W MS/ADR0/MD0 MS ADR0 MD0 MDO/ADR1/MD1 MDO ADR1 MD1 MDI/SDA/DEMP MDI SDA DEMP MC/SCL/FMT MC SCL FMT Both serial controls are available while RST high and after internal reset completion, which is indicated as a negative transition (high low) of a 4096 SCKI width pulse on the OVF pin. The data format is selected by the MC/SCL/FMT pin between I S format and I S mode in TDM format, as shown in Table Table 12. Data Format Selection FMT MODE CONTROL INTERFACE Low I S audio data format High I S mode, TDM audio data format (supported only for SCKI 128 f S 256 f S or 512 f S Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): PCM3168A PCM3168A-Q1

(SPI) SERIAL CONTROL CONTROL DATA WORD FORMAT ADR6R/W Register□Address Register□Data ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 D7 D6 D5 D4 D3 D2 D1 D0 MSB LSB PCM3168A PCM3168A-Q1 www.ti.com SBAS452 SEPTEMBER 2008 The de-emphasis filter is enabled by the MDI/SDA/DEMP pin. The de-emphasis frequency is fixed at 44.1 kHz in hardware control mode, as shown in Table The software mode provides full selections of kHz, 44.1 kHz, and kHz. Table 13. Hardware Control Mode DEMP (DE-EMPHASIS FILTER ENABLE) 44.1 kHz, de-emphasis disabled High 44.1 kHz, de-emphasis enabled The audio interface and the sampling mode are selected by the MS/ADR0/MD0 and MDO/ADR1/MD1 pins. The selectable multiple of the master mode audio interface is limited between 256 f S 384 f S and 512 f S the selectable sampling mode is limited as shown in Table The software mode provides full selections. Table 14. Selectable Sampling Mode (1) Slave (1) Auto (2) Auto (2) Low High Master, 512 f S Slave (1) Single rate Auto (2) High Low Master, 384 f S Slave (1) Dual rate Auto (2) High High Master, 256 f S Slave (1) Dual rate Auto (2) (1) The multiples between system clock and sampling frequency are automatically detected; 256 f S 384 f S 512 f S and 768 f S are acceptable for ADC operation, and 128 f S 192 f S 256 f S 384 f S 512 f S and 768 f S are acceptable for DAC operation. (2) The sampling mode is automatically set as single rate for 512 f S and 768 f S dual rate for 256 f S and 384 f S and quad rate for 128 f S and 198 f S according to the detected multiples between the system clock and sampling clock. The PCM3168A and PCM3168A-Q1 include an SPI-compatible serial port that operates asynchronously with the audio serial interface. The control interface consists of MDI/SDA/DEMP, MDO/ADR1/MD1, MC/SCL/FMT, and MS/ADR0/MD0. MDI is the serial data input to program the mode control registers. MDO is the serial data output to read back register settings and some flags. MDO is inactive (Hi-Z, high impedance) during MS high. MC is the serial bit clock that shifts the data into the control port. MS is the select input to enable the mode control port. All single write/read operations via the serial control port use 16-bit data words. Figure shows the control data word format. The first bit is for read/write controls; '0' indicates a write operation and '1' indicates a read operation. Following the first bit are seven other bits, labeled ADR[6:0] that set the register address for the write/read operation. The eight least significant bits (LSBs), D[7:0] on MDI or MDO, contain the data to be written to the register specified by ADR[6:0], or the data read from the register specified by ADR[6:0]. Figure 47. Control Data Word Format for MDI Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM3168A PCM3168A-Q1

(1) '0' ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 D7 D6 D5 D4 D3 D2 D1 D0 X X R/W ADR6 REGISTER READ OPERATION MS MC MDI X(1) '1' ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 Don't□Care□(X) R/W ADR6 MDO Hi-Z Hi-ZD7 D6 D5 D4 D3 D2 D1 D0 PCM3168A PCM3168A-Q1 SBAS452 SEPTEMBER 2008 www.ti.com Figure shows the functional timing diagram for single write operations on the serial control port. MS is held at a high state until a register must be written. To start the register write cycle, MS is set to a low state. clocks are then provided on MC, corresponding to the bits of the control data word on MDI. After the 16th clock cycle has been completed, MS is set high to latch the data into the indexed mode control register. Also, the PCM3168A and PCM3168A-Q1 support multiple write operations in addition to single write operations, which can be performed by sending the following N-times of the 8-bit register data after the first 16-bit register address and register data while keeping the MC clocks and MS at a low state. Closing a multiple write operation can be accomplished by setting MS to a high state. (1) X Don't care. Figure 48. Register Write Operation Figure shows the functional timing diagram for single read operations on the serial control port. MS is held at a high state until a register must be read. To start the register read cycle, MS is set to a low state. clocks are then provided on MC, corresponding to the first eight bits of the control data word on MDI and the second eight bits of the read-back data word from MDO. After the 16th clock cycle has been completed, MS is held high for the next write or read operation. MDO remains in a high impedance state except during the eight MC clock periods of the actual data transfer. (1) X Don't care. Figure 49. Register Read Operation Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): PCM3168A PCM3168A-Q1

CHARACTERISTICS: FOUR-WIRE MS 1.4□V 1.4□V 1.4□V 0.5 /c180VDD t MSH tMDD tMDR LSB□(D0) LSB□(D0) Hi-Z tMSS tMCH tMCL tMDD tMDS ADR0MSB□(R/ )W MSB□(D7)Hi-Z MC MDI MDO tMDH tMCY tMHH MSB□(D7) TWO-WIRE SERIAL CONTROL MSB LSB 1 0 0 0 1 ADR1 ADR0 R/W PCM3168A PCM3168A-Q1 www.ti.com SBAS452 SEPTEMBER 2008 (1) These timing parameters are critical for proper control port operation. Figure 50. Four-Wire Serial Control Interface Timing (1) Timing Requirements for Figure (1) PCM3168A, PCM3168A-Q1 SYMBOL PARAMETER MIN MAX UNIT t MCY MC pulse cycle time 100 ns t MCL MC low-level time ns t MCH MC high-level time ns t MHH MS high-level time t MCY ns t MSS MS falling edge to MC rising edge ns t MSH MS rising edge from MC rising edge for LSB ns t MDH MDI hold time ns t MDS MDI setup time ns t MDD MDO enable or delay time from MC falling edge ns t MDR MDO disable time from MS rising edge ns (1) These timing parameters are critical for proper control port operation. The PCM3168A and PCM3168A-Q1 support an I C-compatible serial bus and data transmission protocol for fast mode configured as a slave device. This protocol is explained in the I C specification, version 2.0. The PCM3168A and PCM3168A-Q1 have a 7-bit slave address, as shown in Figure The first five bits are the most significant bits (MSB) of the slave address and are factory-preset to 10001 The next two bits of the address byte are selectable bits that can be set by MS/ADR0/MD0 and MDO/ADR1/MD1. A maximum of four PCM3168A and PCM3168A-Q1s can be connected on the same bus at any one time. Each PCM3168A and PCM3168A-Q1 respond when it receives its own slave address. Figure 51. Slave Address Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM3168A PCM3168A-Q1

Slave□Address R/W (1) ACK(2) DATA(3) ACK DATA ACK ACK 9St Start Condition Sp Stop Condition WRITE OPERATION Transmitter Data□T ype St M Slave□Address M W M ACK S Reg□Address M ACK S Write□Data□1 M ACK S Write□Data□2 M ACK S ACK S Sp M READ OPERATION Transmitter M St M Slave□Address M W S ACK M Reg□Address S ACK M Sr M Slave□Address M R S ACK S Read□Data M NACK M SpData□T ype PCM3168A PCM3168A-Q1 SBAS452 SEPTEMBER 2008 www.ti.com A master device must control the packet protocol, which consists of the start condition, slave address with the read/write bit, data if a write operation is required, acknowledgement if a read operation is required, and stop condition. The PCM3168A and PCM3168A-Q1 support both slave receiver and transmitter functions. Details about DATA for both write and read operations are described in Figure (1) W Read operation if '1'; write operation otherwise. (2) ACK: Acknowledgement of a byte if '0', not Acknowledgement of a byite if '1'. (3) DATA: Eight bits (byte); details are described in the Write Operation and Read Operation sections. Figure 52. DATA Operation The PCM3168A and PCM3168A-Q1 support a receiver function. A master device can write to any PCM3168A and PCM3168A-Q1 register using single or multiple accesses. The master sends a PCM3168A and PCM3168A-Q1 slave address with a write bit, a register address, and the data. If multiple access is required, the address is that of the starting register, followed by the data to be transferred. When the data are received properly, the index register is incremented by one automatically. When the index register reaches h5E the next value is h40 When undefined registers are accessed, the PCM3168A and PCM3168A-Q1 do not send an acknowledgement. Figure illustrates a diagram of the write operation. The register address and write data are in 8-bit, MSB-first format. (1) M Master device, S Slave device, St Start condition, W Write, ACK Acknowledge, and Sp Stop condition. Figure 53. Framework for Write Operation A master device can read the registers from h40 to h5E of the PCM3168A and PCM3168A-Q1. The value of the register address is stored in an indirect index register in advance. The master sends the PCM3168A and PCM3168A-Q1 slave address with a read bit after storing the register address. Then the PCM3168A and PCM3168A-Q1 transfer the data that the index register points to. Figure shows a diagram of the read operation. (1) M Master device, S Slave device, St Start condition, Sr Repeated start condition, W Write, R Read, ACK Acknowledge, NACK Not acknowledge, and Sp Stop condition. NOTE: The slave address after the repeated start condition must be the same as the previous address. Figure 54. Framework for Read Operation Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): PCM3168A PCM3168A-Q1

REQUIREMENTS: SCL AND SDA tBUF tD-SU tD-HD tSDA-R tSDA-F tP -SU tSCL -F tS-HD tLOW tSCL -R tHI tS-SU tS-HD ST ART Repeated ST ART STOP SDA SCL PCM3168A PCM3168A-Q1 www.ti.com SBAS452 SEPTEMBER 2008 Figure 55. SCL and SDA Control Interface Timing Timing Requirements for Figure PCM3168A, PCM3168A-Q1 STANDARD MODE FAST MODE SYMBOL PARAMETER MIN MAX MIN MAX UNIT f SCL SCL clock frequency 100 400 kHz t BUF Bus free time between STOP and START condition 4.7 1.3 µ s t LOW Low period of the SCL clock 4.7 1.3 µ s t HI High period of the SCL clock 4.0 0.6 µ s t S-SU Setup time for START/Repeated START condition 4.7 0.6 µ s t S-HD Hold time for START/Repeated START condition 4.0 0.6 µ s t D-SU Data setup time 250 100 ns t D-HD Data hold time 3450 900 ns t SCL-R Rise time of SCL signal 1000 0.1 C B 300 ns t SCL-F Fall time of SCL signal 1000 0.1 C B 300 ns t SDA-R Rise time of SDA signal 1000 0.1 C B 300 ns t SDA-F Fall time of SDA signal 1000 0.1 C B 300 ns t P-SU Setup time for STOP condition 4.0 0.6 µ s t GW Allowable glitch width N/A C B Capacitive load for SDA and SCL line 400 100 pF Noise margin at high level for each connected device V NH 0.2 VDD 0.2 VDD V (including hysteresis) Noise margin at low level for each connected device V NL 0.1 VDD 0.1 VDD V (including hysteresis) V HYS Hysteresis of Schmitt-trigger input N/A 0.05 VDD V Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM3168A PCM3168A-Q1

(SOFTWARE MODE ONLY) PCM3168A PCM3168A-Q1 SBAS452 SEPTEMBER 2008 www.ti.com The PCM3168A and PCM3168A-Q1 have many user-programmable functions that are accessed via control registers, and are programmed through the SPI or I C serial control port. Table shows the available mode control functions along with reset default conditions and associated register address. Table lists the register map. Table 15. User-Programmable Mode Control Functions FUNCTION RESET DEFAULT REGISTER LABEL Mode control register reset for ADC and DAC operation Normal operation MRST System reset for ADC and DAC operation Normal operation SRST DAC sampling mode selection Auto SRDA[1:0] DAC power-save mode selection Power save PSMDA DAC master/slave mode selection Slave MSDA[2:0] DAC audio interface format selection I S FMTDA[3:0] DAC operation control Normal operation OPEDA[3:0] DAC digital filter roll-off control Sharp roll-off FLT[3:0] DAC output phase selection Normal REVDA[8:1] DAC soft mute control Mute disabled MUTDA[8:1] DAC zero flag Not detected ZERO[8:1] DAC digital attenuation mode Channel independent ATMDDA DAC digital attenuation speed N 2048/f S ATSPDA DAC digital de-emphasis function control Disabled DEMP[1:0] DAC zero flag function selection Independent AZRO[2:0] DAC zero flag polarity selection High for detection ZREV DAC digital attenuation level shifting dB, no attenuation ATDAx[7:0] ADC sampling mode selection Auto SRAD[1:0] ADC master/slave mode selection Slave MSAD[2:0] ADC audio interface format selection I S FMTAD[2:0] ADC power-save control Normal operation PSVAD[2:0] ADC HPF bypass control Normal output, HPF enabled BYP[2:0] ADC input configuration control Differential SEAD[6:1] ADC input phase selection Normal REVAD[6:1] ADC soft mute control Mute disabled MUTAD[6:1] ADC overflow flag Not detected OVF[6:1] ADC digital attenuation mode Channel independent ATMDAD ADC digital attenuation speed N 2048/f S ATSPAD ADC overflow flag polarity selection High for detection OVFP ADC digital attenuation level setting dB, no gain or attenuation ATADx[7:0] Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): PCM3168A PCM3168A-Q1

www.ti.com SBAS452 SEPTEMBER 2008 Table 16. Register Map ADDRESS DATA DAC HEX MRST SRST SRDA1 SRDA0 PSMDA MSDA2 MSDA1 MSDA0 FMTDA3 FMTDA2 FMTDA1 FMTDA0 OPEDA3 OPEDA2 OPEDA1 OPEDA0 FLT3 FLT2 FLT1 FLT0 REVDA8 REVDA7 REVDA6 REVDA5 REVDA4 REVDA3 REVDA2 REVDA1 MUTDA8 MUTDA7 MUTDA6 MUTDA5 MUTDA4 MUTDA3 MUTDA2 MUTDA1 ZERO8 ZERO7 ZERO6 ZERO5 ZERO4 ZERO3 ZERO2 ZERO1 ATMDDA ATSPDA DEMP1 DEMP0 AZRO2 AZRO1 AZRO0 ZREV ATDA07 ATDA06 ATDA05 ATDA04 ATDA03 ATDA02 ATDA01 ATDA00 ATDA17 ATDA16 ATDA15 ATDA14 ATDA13 ATDA12 ATDA11 ATDA10 ATDA27 ATDA26 ATDA25 ATDA24 ATDA23 ATDA22 ATDA21 ATDA20 ATDA37 ATDA36 ATDA35 ATDA34 ATDA33 ATDA32 ATDA31 ATDA30 ATDA47 ATDA46 ATDA45 ATDA44 ATDA43 ATDA42 ATDA41 ATDA40 ATDA57 ATDA56 ATDA55 ATDA54 ATDA53 ATDA52 ATDA51 ATDA50 ATDA67 ATDA66 ATDA65 ATDA64 ATDA63 ATDA62 ATDA61 ATDA60 ATDA77 ATDA76 ATDA75 ATDA74 ATDA73 ATDA72 ATDA71 ATDA70 ATDA87 ATDA86 ATDA85 ATDA84 ATDA83 ATDA82 ATDA81 ATDA80 SRAD1 SRAD0 MSAD2 MSAD1 MSAD0 FMTAD2 FMTAD1 FMTAD0 PSVAD2 PSVAD1 PSVAD0 BYP2 BYP1 BYP0 SEAD6 SEAD5 SEAD4 SEAD3 SEAD2 SEAD1 REVAD6 REVAD5 REVAD4 REVAD3 REVAD2 REVAD1 MUTAD6 MUTAD5 MUTAD4 MUTAD3 MUTAD2 MUTAD1 OVF6 OVF5 OVF4 OVF3 OVF2 OVF1 ATMDAD ATSPAD OVFP ATAD07 ATAD06 ATAD05 ATAD04 ATAD03 ATAD02 ATAD01 ATAD00 ATAD17 ATAD16 ATAD15 ATAD14 ATAD13 ATAD12 ATAD11 ATAD10 ATAD27 ATAD26 ATAD25 ATAD24 ATAD23 ATAD22 ATAD21 ATAD20 ATAD37 ATAD36 ATAD35 ATAD34 ATAD33 ATAD32 ATAD31 ATAD30 ATAD47 ATAD46 ATAD45 ATAD44 ATAD43 ATAD42 ATAD41 ATAD40 ATAD57 ATAD56 ATAD55 ATAD54 ATAD53 ATAD52 ATAD51 ATAD50 ATAD67 ATAD66 ATAD65 ATAD64 ATAD63 ATAD62 ATAD61 ATAD60 Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM3168A PCM3168A-Q1

www.ti.com DEC HEX MRST SRST SRDA1 SRDA0 MRST Mode control register reset for the ADC and DAC This bit sets the mode control register reset to the default value. Pop-noise may be generated. Returning the MRST bit to '1' is unneccesary, because it is automatically set to '1' after the mode control register is reset. Default value MRST Mode control register reset Set default value Normal operation (default) SRST System reset for the ADC and DAC This bit controls system reset, the relation between system clock and sampling clock re-synchronization, and ADC operation and DAC operation restart. The mode control register is not reset and the PCM3168A and PCM3168A-Q1 do not go into a power-down state. The fade-in sequence is supported in the resume process, but pop-noise may be generated. Returning the SRST bit to '1' is unneccesary; it is automatically set to '1' after triggering a system reset. Default value SRST System reset Resynchronization Normal operation (default) SRDA[1:0] DAC Sampling mode select These bits control the sampling mode of DAC operation. In Auto mode, the sampling mode is automatically set according to multiples between the system clock and sampling clock, single rate for 512 f S and 768 f S dual rate for 256 f S or 384 f S and quad rate for 128 f S and 192 f S Default value 00. SRDA DAC Sampling mode select Auto (default) Single rate Dual rate Quad rate Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): PCM3168A PCM3168A-Q1

www.ti.com SBAS452 SEPTEMBER 2008 DEC HEX PSMDA MSDA2 MSDA1 MSDA0 FMTDA3 FMTDA2 FMTDA1 FMTDA0 PSMDA DAC Power-save mode select This bit selects the power-save mode for the OPEDA[3:0] function. OPEDA[3:0] is the control of power-save mode and normal operation for PSMDA or OPEDA[3:0] works as the control of DAC disable (not power-save mode) and normal operation for PSMDA Default value: PSMDA DAC Power-save mode select Power-save enable mode (default) Power-save disable mode MSDA[2:0] DAC Master/slave mode select These bits control the audio interface mode for DAC operation. Default value: 000 (slave mode). MSDA DAC Master/slave mode select 000 Slave mode (default) 001 Master mode, 768 f S 010 Master mode, 512 f S 011 Master mode, 384 f S 100 Master mode, 256 f S 101 Master mode, 192 f S 110 Master mode, 128 f S 111 Reserved FMTDA[3:0] DAC Audio interface format select These bits control the audio interface format for DAC operation. Details of the format, and any related restrictions with the system clock and master/slave mode, are described in the Audio Data Interface Formats and Timing section. Default value: 0000 (24-bit I S format). FMTDA DAC Audio interface format select 0000 24-bit I S format (default) 0001 24-bit left-justified format 0010 24-bit right-justified format 0011 16-bit right-justified format 0100 24-bit I S mode DSP format 0101 24-bit left-justified mode DSP format 0110 24-bit I S mode TDM format 0111 24-bit left-justified mode TDM format 1000 24-bit high-speed I S mode TDM format 1001 24-bit high-speed left-justified mode TDM format 101x Reserved 11xx Reserved Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM3168A PCM3168A-Q1

www.ti.com DEC HEX OPEDA3 OPEDA2 OPEDA1 OPEDA0 FLT3 FLT2 FLT1 FLT0 OPEDA[3:0] DAC Operation control These bits control the DAC operation mode. In operation disable mode, the DAC output is cut off from DIN with a fade-out sequence, and the internal DAC data is reset. DAC output is forced into VCOMDA if PSMDA or DAC output is forced into AGNDDA and goes into a power-down state if PSMDA For normal operating mode, a fade-in sequence is applied on the DAC output in resume process. The serial mode control is effective during operation disable mode. A wait time greater than t DACDLY2 is required for the status change because of power-save control turning on/off. Default value: 0000. OPEDA DAC Operation control xxx0 DAC1/2 normal operation xxx1 DAC1/2 operation disable with or without power save xx0x DAC3/4 normal operation xx1x DAC3/4 operation disable with or without power save x0xx DAC5/6 normal operation x1xx DAC5/6 operation disable with or without power save 0xxx DAC7/8 normal operation 1xxx DAC7/8 operation disable with or without power save FLT[3:0] DAC Digital filter roll-off control The FLT[3:0] bits allow users to select the digital filter roll-off that is best suited to their applications. Sharp and Slow filter roll-off selections are available. The filter responses for these selections are shown in the Typical Characteristics section of this data sheet. Default value: 0000. FLT DAC Digital filter roll-off control xxx0 DAC1/2 sharp roll-off xxx1 DAC1/2 slow roll-off xx0x DAC3/4 sharp roll-off xx1x DAC3/4 slow roll-off x0xx DAC5/6 sharp roll-off x1xx DAC5/6 slow roll-off 0xxx DAC7/8 sharp roll-off 1xxx DAC7/8 slow roll-off Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): PCM3168A PCM3168A-Q1

www.ti.com SBAS452 SEPTEMBER 2008 DEC HEX REVDA8 REVDA7 REVDA6 REVDA5 REVDA4 REVDA3 REVDA2 REVDA1 REVDA[8:1] DAC Output phase select The REVDA[8:1] bits are used to control the phase of DAC analog signal outputs. Default value: 0000 0000. REVDA DAC Output phase select xxxx xxx0 DAC1 normal output xxxx xxx1 DAC1 inverted output xxxx xx0x DAC2 normal output xxxx xx1x DAC2 inverted output xxxx x0xx DAC3 normal output xxxx x1xx DAC3 inverted output xxxx 0xxx DAC4 normal output xxxx 1xxx DAC4 inverted output xxx0 xxxx DAC5 normal output xxx1 xxxx DAC5 inverted output xx0x xxxx DAC6 normal output xx1x xxxx DAC6 inverted output x0xx xxxx DAC7 normal output x1xx xxxx DAC7 inverted output 0xxx xxxx DAC8 normal output 1xxx xxxx DAC8 inverted output Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM3168A PCM3168A-Q1

www.ti.com DEC HEX MUTDA8 MUTDA7 MUTDA6 MUTDA5 MUTDA4 MUTDA3 MUTDA2 MUTDA1 MUTDA[8:1] DAC Soft Mute control These bits are used to enable or disable the Soft Mute function for the corresponding DAC outputs, VOUT. The Soft Mute function is incorporated into the digital attenuators. When Mute is disabled (MUTDA[8:1] 0), the attenuator and DAC operate normally. When Mute is enabled by setting MUTDA[8:1] the digital attenuator for the corresponding output decreases from the current setting to infinite attenuation with an s-curve response and time set by ATSPDA. By setting MUTDA[8:1] the attenuator increases to the last attenuation level with s-curve response in the same manner as it is for decreasing levels. This configuration provides pop and zipper noise-free muting of the DAC output. The Soft Mute control uses the same digital attenuation level resource setting as the DAC. Mute control has priority over the digital attenuation level setting. Default value: 0000 0000. MUTDA DAC Soft Mute control xxxx xxx0 DAC1 Mute disabled xxxx xxx1 DAC1 Mute enabled xxxx xx0x DAC2 Mute disabled xxxx xx1x DAC2 Mute enabled xxxx x0xx DAC3 Mute disabled xxxx x1xx DAC3 Mute enabled xxxx 0xxx DAC4 Mute disabled xxxx 1xxx DAC4 Mute enabled xxx0 xxxx DAC5 Mute disabled xxx1 xxxx DAC5 Mute enabled xx0x xxxx DAC6 Mute disabled xx1x xxxx DAC6 Mute enabled x0xx xxxx DAC7 Mute disabled x1xx xxxx DAC7 Mute enabled 0xxx xxxx DAC8 Mute disabled 1xxx xxxx DAC8 Mute enabled Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): PCM3168A PCM3168A-Q1

www.ti.com SBAS452 SEPTEMBER 2008 DEC HEX ZERO8 ZERO7 ZERO6 ZERO5 ZERO4 ZERO3 ZERO2 ZERO1 ZERO[8:1] DAC Zero flag (read-only) These bits indicate the present status of the zero detect circuit for each DAC channel; these bits are read-only. ZERO DAC Zero flag xxxx xxx0 DAC1 zero input not detected xxxx xxx1 DAC1 zero input detected xxxx xx0x DAC2 zero input not detected xxxx xx1x DAC2 zero input detected xxxx x0xx DAC3 zero input not detected xxxx x1xx DAC3 zero input detected xxxx 0xxx DAC4 zero input not detected xxxx 1xxx DAC4 zero input detected xxx0 xxxx DAC5 zero input not detected xxx1 xxxx DAC5 zero input detected xx0x xxxx DAC6 zero input not detected xx1x xxxx DAC6 zero input detected x0xx xxxx DAC7 zero input not detected x1xx xxxx DAC7 zero input detected 0xxx xxxx DAC8 zero input not detected 1xxx xxxx DAC8 zero input detected Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM3168A PCM3168A-Q1

www.ti.com DEC HEX ATMDDA ATSPDA DEMP1 DEMP0 AZRO2 AZRO1 AZRO0 ZREV ATMDDA DAC Attenuation mode This bit controls the DAC attenuation mode. ATDA1[7:0] to ATDA8[7:0] are simply used for ATMDDA and ATDA0[7:0] ATDA1[7:0] to ATDA0[7:0] ATDA8[7:0] in decibel number are used for ATMDDA Default value: ATMDDA DAC Attenuation mode Each channel with independent data (default) All channels with preset (independent) data master (common) data in decibel number ATSPDA DAC Attenuation speed This bit controls the DAC attenuation speed. N 2048/f S for ATSPDA and N 4096/f S for ATSPDA N is automatically selected according to the DAC sampling mode, SRDA, N for single rate, N for dual rate, and N for quad rate. Default value: ATSPDA DAC Attenuation speed N 2048/f S (default) N 4096/f S DEMP[1:0] DAC Digital de-emphasis function/sampling rate control These bits are used to control the enable/disable and sampling frequency of the digital de-emphasis function. Default value: 00. DEMP DAC Digital de-emphasis function/sampling rate control Disable (default) kHz enable 44.1 kHz enable kHz enable AZRO[2:0] DAC Zero flag function select The AZRO[2:0] bits are used to select the function of the zero flag pin. Default value: 000. AZRO DAC Zero flag function select 000 DAC1/2/3/4/5/6/7/8 channel) zero input detect with AND logic (default) 001 DAC1/2/3/4/5/6/7/8 channel) zero input detect with OR logic 010 DAC1/2/3/4/5/6 channel) zero input detect with AND logic 011 DAC1/2/3/4/5/6 channel) zero input detect with OR logic 100 DAC7/8 channel) zero input detect with AND logic 101 DAC7/8 channel) zero input detect with OR logic 11x Reserved Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): PCM3168A PCM3168A-Q1

www.ti.com SBAS452 SEPTEMBER 2008 ZREV DAC Zero flag polarity select This bit controls the polarity of the zero flag pin. Default value: ZREV DAC Zero flag polarity select High for zero detect (default) Low for zero detect DEC HEX ATDA07 ATDA06 ATDA05 ATDA04 ATDA03 ATDA02 ATDA01 ATDA00 ATDA17 ATDA16 ATDA15 ATDA14 ATDA13 ATDA12 ATDA11 ATDA10 ATDA27 ATDA26 ATDA25 ATDA24 ATDA23 ATDA22 ATDA21 ATDA20 ATDA37 ATDA36 ATDA35 ATDA34 ATDA33 ATDA32 ATDA31 ATDA30 ATDA47 ATDA46 ATDA45 ATDA44 ATDA43 ATDA42 ATDA41 ATDA40 ATDA57 ATDA56 ATDA55 ATDA54 ATDA53 ATDA52 ATDA51 ATDA50 ATDA67 ATDA66 ATDA65 ATDA64 ATDA63 ATDA62 ATDA61 ATDA60 ATDA77 ATDA76 ATDA75 ATDA74 ATDA73 ATDA72 ATDA71 ATDA70 ATDA87 ATDA86 ATDA85 ATDA84 ATDA83 ATDA82 ATDA81 ATDA80 ATDAx[7:0] DAC Digital attenuation level setting Where x and to corresponding to the DAC channel, DACx to 8). Each DAC channel (VOUTx) has a digital attenuator function. The attenuation level can be set from dB to 100 dB in 0.5-dB steps, and also can be set to infinite attenuation (mute). The attenuation level change from current value to target value is performed by incrementing or decrementing with s-curve responses and a time set by ATSPDA. While an attenuation level change sequence is in progress, new processing of the attenuation level change for new commands are ignored; any new commands are overwritten into the command buffer. The last command for the attenuation level change is performed after the present attenuation level change sequence is finished. The attenuation level for each channel can be set individually using the following formula; the table below shows attenuation levels for various settings. Attenuation level (dB) 0.5 (ATDAx[7:0]DEC 255), where ATDAx[7:0]DEC through 255 for ATDAx[7:0]DEC through 54, attenuation is set to infinite attenuation (Mute). ATDA0[7:0] are used to control all channels at the same time with attenuation data of ATDA0[7:0] ATDAx[7:0] in decibel number, when ATMDDA is set to '1'. This scheme provides preset and master volume operation. Default value: 1111 1111. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM3168A PCM3168A-Q1

www.ti.com ATDAx Decimal Attenuation level setting value 1111 1111 255 dB, no attenuation (default) 1111 1110 254 0.5 dB 1111 1101 253 1.0 dB ... ... ... 1000 0001 129 63.0 dB 1000 0000 128 63.5 dB 0111 1111 127 dB ... ... ... 0011 1000 99.5 dB 0011 0111 100 dB 0011 0110 Mute ... ... ... 0000 0000 Mute DEC HEX SRAD1 SRAD0 SRAD[1:0] ADC Sampling mode select These bits control the sampling mode of ADC operation. In Auto mode, the sampling mode is automatically set according to multiples between system clock and sampling clock, single rate for 512 f S and 768 f S and dual rate for 256 f S and 384 fS Default value: 00. SRAD ADC Sampling mode select Auto (default) Single rate Dual rate Reserved Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): PCM3168A PCM3168A-Q1

www.ti.com SBAS452 SEPTEMBER 2008 DEC HEX MSAD2 MSAD1 MSAD0 FMTAD2 FMTAD1 FMTAD0 MSAD[2:0] ADC Master/slave mode select These bits control the audio interface mode for ADC operation. Default value: 000 (slave mode). MSAD ADC Master/slave mode select 000 Slave mode (default) 001 Master mode, 768 f S 010 Master mode, 512 f S 011 Master mode, 384 f S 100 Master mode, 256 f S 101 Reserved 110 Reserved 111 Reserved FMTAD[2:0] ADC Audio interface format select These bits control the audio interface format for ADC operation. The format details and restrictions related to the system clock and master/slave mode are described in the Audio Data Interface Formats and Timing section. Default value: 000 (24-bit I S format). FMTAD ADC Audio interface format select 000 24-bit I S format (default) 001 24-bit left-justified format 010 24-bit right-justified format 011 16-bit right-justified format 100 24-bit I S mode DSP format 101 24-bit left-justified mode DSP format 110 24-bit I S mode TDM format 111 24-bit left-justified mode TDM format Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM3168A PCM3168A-Q1

www.ti.com DEC HEX PSVAD2 PSVAD1 PSVAD0 BYP2 BYP1 BYP0 PSVAD[2:0] ADC Power-save control These bits control the ADC power-save mode. In power-save mode, DOUT is forced into ZERO with a fade-out sequence, the internal ADC data are reset, and the ADC goes into a power-down state. For power-save mode release, a fade-in sequence is applied on DOUT in resume process. The serial mode control is enabled during this mode. Wait times greater than t ADCDLY2 are required for the status change because of the power-save control turning on/off. Default value: 000. PSVAD ADC Power-save control xx0 ADC1/2 normal operation xx1 ADC1/2 power-save mode x0x ADC3/4 normal operation x1x ADC3/4 power-save mode 0xx ADC5/6 normal operation 1xx ADC5/6 power-save mode BYP[2:0] ADC HPF bypass control These bits control the HPF function and dc components of the input signal; internal dc offset is converted in bypass mode. Default value: 000. BYP ADC HPF bypass control xx0 ADC1/2 normal output, HPF enabled xx1 ADC1/2 bypassed output, HPF disabled x0x ADC3/4 normal output, HPF enabled x1x ADC3/4 bypassed output, HPF disabled 0xx ADC5/6 normal output, HPF enabled 1xx ADC5/6 bypassed output, HPF disabled Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): PCM3168A PCM3168A-Q1

www.ti.com SBAS452 SEPTEMBER 2008 DEC HEX SEAD6 SEAD5 SEAD4 SEAD3 SEAD2 SEAD1 SEAD[6:1] ADC Input configuration control These bits control the input configuration of each ADC channel, differential or single-ended. Default value: 0000 (all ADC channels have differential inputs). SEAD ADC Input configuration xx xxx0 ADC1 differential input xx xxx1 ADC1 single-ended input xx xx0x ADC2 differential input xx xx1x ADC2 single-ended input xx x0xx ADC3 differential input xx x1xx ADC3 single-ended input xx 0xxx ADC4 differential input xx 1xxx ADC4 single-ended input xxxx ADC5 differential input xxxx ADC5 single-ended input xxxx ADC6 differential input xxxx ADC6 single-ended input Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM3168A PCM3168A-Q1

www.ti.com DEC HEX REVAD6 REVAD5 REVAD4 REVAD3 REVAD2 REVAD1 REVAD[6:1] ADC Input phase select These bits are used to control the phase of analog signal inputs. Default value: 0000. REVAD ADC Input phase select xx xxx0 ADC1 normal input xx xxx1 ADC1 inverted input xx xx0x ADC2 normal input xx xx1x ADC2 inverted input xx x0xx ADC3 normal input xx x1xx ADC3 inverted input xx 0xxx ADC4 normal input xx 1xxx ADC4 inverted input xxxx ADC5 normal input xxxx ADC5 inverted input xxxx ADC6 normal input xxxx ADC6 inverted input Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): PCM3168A PCM3168A-Q1

www.ti.com SBAS452 SEPTEMBER 2008 DEC HEX MUTAD6 MUTAD5 MUTAD4 MUTAD3 MUTAD2 MUTAD1 MUTAD[6:1] ADC Soft Mute control These bits are used to enable or disable the Soft Mute function for the corresponding ADC outputs, DOUT. The Soft Mute function is incorporated into the digital attenuators. When Mute is disabled (MUTAD[6:1] 0), the attenuator and ADC operate normally. When Mute is enabled by setting MUTAD[6:1] the digital attenuator for the corresponding output decreases from the current setting to infinite attenuation with an s-curve responses and time set by ATSPAD. By setting MUTAD[6:1] the attenuator increases to the last attenuation level with the s-curve response in same manner as for decreasing levels. This provides pop and zipper noise-free muting for the ADC input. The Soft Mute control uses the same digital attenuation level resource setting as the ADC. Mute control has priority over the digital attenuation level setting. Default value: 0000. MUTAD ADC Soft Mute control xx xxx0 ADC1 Mute disabled xx xxx1 ADC1 Mute enabled xx xx0x ADC2 Mute disabled xx xx1x ADC2 Mute enabled xx x0xx ADC3 Mute disabled xx x1xx ADC3 Mute enabled xx 0xxx ADC4 Mute disabled xx 1xxx ADC4 Mute enabled xxxx ADC5 Mute disabled xxxx ADC5 Mute enabled xxxx ADC6 Mute disabled xxxx ADC6 Mute enabled Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM3168A PCM3168A-Q1

www.ti.com DEC HEX OVF6 OVF5 OVF4 OVF3 OVF2 OVF1 OVF[6:1] ADC Overflow flag (read-only) These bits indicate the status information of an overflow detect circuit for each ADC channel; these bits are read only. '1' means an overflow has been detected in the past, and reading this register resets all OVF bits. OVF ADC Overflow flag xx xxx0 ADC1 overflow input not detected xx xxx1 ADC1 overflow input detected xx xx0x ADC2 overflow input not detected xx xx1x ADC2 overflow input detected xx x0xx ADC3 overflow input not detected xx x1xx ADC3 overflow input detected xx 0xxx ADC4 overflow input not detected xx 1xxx ADC4 overflow input detected xxxx ADC5 overflow input not detected xxxx ADC5 overflow input detected xxxx ADC6 overflow input not detected xxxx ADC6 overflow input detected Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): PCM3168A PCM3168A-Q1

www.ti.com SBAS452 SEPTEMBER 2008 DEC HEX ATMDAD ATSPAD OVFP ATMDAD ADC Attenuation mode This bit controls the ADC attenuation mode. ATAD1[7:0] to ATAD6[7:0] are simply used for ATMDAD and ATAD0[7:0] ATAD1[7:0] to ATAD0[7:0] ATAD6[7:0] in decibel number are used for ATMDAD Default value: ATMDAD ADC Attenuation mode Each channel with independent data (default) All channels with preset (independent) data master (common) data in decibel number ATSPAD ADC Attenuation speed This bit controls the ADC attenuation Speed, N 2048/f S for ATSPAD and N 4096/f S for ATSPAD N is automatically selected according to the ADC sampling mode, SRAD: N for single and N for dual rate. Default value: ATSPAD ADC Attenuation speed N 2048/f S (default) N 4096/f S OVFP ADC Overflow flag polarity select This bit controls the polarity of the overflow flag pin. Default value: OVFP ADC Overflow flag polarity select High for overflow detect (default) Low for overflow detect DEC HEX ATAD07 ATAD06 ATAD05 ATAD04 ATAD03 ATAD02 ATAD01 ATAD00 ATAD17 ATAD16 ATAD15 ATAD14 ATAD13 ATAD12 ATAD11 ATAD10 ATAD27 ATAD26 ATAD25 ATAD24 ATAD23 ATAD22 ATAD21 ATAD20 ATAD37 ATAD36 ATAD35 ATAD34 ATAD33 ATAD32 ATAD31 ATAD30 ATAD47 ATAD46 ATAD45 ATAD44 ATAD43 ATAD42 ATAD41 ATAD40 ATAD57 ATAD56 ATAD55 ATAD54 ATAD53 ATAD52 ATAD51 ATAD50 ATAD67 ATAD66 ATAD65 ATAD64 ATAD63 ATAD62 ATAD61 ATAD60 Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM3168A PCM3168A-Q1

www.ti.com ATADx[7:0] ADC Digital attenuation level setting Where x and to corresponding to the ADC channel, ADCx to 6). Each ADC channel has a digital attenuator function with 20-dB gain. The attenuation level can be set from dB to 100 dB in 0.5-dB steps, and also can be set to infinite attenuation (mute). The attenuation level change from current value to target value is performed by increment or decrement with s-curve response and time set by ATSPAD. While the attenuation level change sequence is in progress, new processing of an attenuation level change for a new command is ignored; the new command is overwritten into the command buffer. The last command for an attenuation level change is performed after the present attenuation level change sequence is finished. The attenuation level for each channel can be set individually using the following formula, and the above table shows attenuation levels for various settings. Attenuation level (dB) 0.5 (ATADx[7:0]DEC 215), where ATADx[7:0]DEC through 255 for ATADx[7:0]DEC through 14, attenuation is set to infinite attenuation (Mute). ATAD0[7:0] is used to control all channels at the same time with attenuation data of ATAD0[7:0] ATADx[7:0] in decibel number, though maximum level is limited within +20 dB, when ATMDAD is set to '1'. This scheme provides preset and master volume operation. Default value: 1101 0111. ATADx Decimal Attenuation level setting value 1111 1111 255 +20.0 dB 1111 1110 254 +19.5 dB 1111 1101 253 +19.0 dB ... ... ... 1101 1000 216 +0.5 dB 1101 0111 215 dB, no attenuation (default) 1101 0110 214 0.5 dB ... ... ... 0001 0000 99.5 dB 0000 1111 100.0 dB 0000 1110 Mute ... ... ... 0000 0000 Mute Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): PCM3168A PCM3168A-Q1

LRCKADBCKADDOUT1DOUT2DOUT3 SCKI DIN1 DIN2 DIN3 DIN4 LRCKDABCKDA MODE T ermination OVF RST MS/ADR0/MD0MDO/ADR1/MD1MDI/SDA/DEMPMC/SCL/FMTZERO VIN1+ VIN1/c45 VIN2+ VIN2/c45 VIN3+ VIN3/c45 VIN4+ VIN4/c45 VIN5+ VIN5/c45 VIN6+ VIN6/c45 VDD1 DGND1 VDD2 DGND2 VCCAD1 AGNDA1 VCCAD2 AGNDAD2 VCOMAD VREFAD1 VREFAD2 VOUT1+ VOUT1/c45 VOUT2+ VOUT2/c45 VOUT3+ VOUT3/c45 VOUT4+ VOUT4/c45 VOUT5+ VOUT5/c45 VOUT6+ VOUT6/c45 VOUT7+ VOUT7/c45 VOUT8+ VOUT8/c45 VCCDA1 AGNDDA1 VCCDA2 AGNDDA2 VCOMDA PCM3168A PCM3168A-Q1 C1C7 C11 C10 C12 Control□MCU Analog□Output LPF□and□Buffer Analog□Input Digital□Audio□Processor R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 0□V 5□V 0□V 3.3□V Analog□Input Analog□Input Analog□Input Analog□Input Analog□Input Analog□Output LPF□and□Buffer Analog□Output LPF□and□Buffer Analog□Output LPF□and□Buffer Analog□Output LPF□and□Buffer Analog□Output LPF□and□Buffer Analog□Output LPF□and□Buffer Analog□Output LPF□and□Buffer 3.3□V 3.3□V 0□V 0□V (1) (2) (3) (4) PCM3168A PCM3168A-Q1 www.ti.com SBAS452 SEPTEMBER 2008 A typical circuit connection for six-channel analog in and eight-channel analog out is shown in Figure C through C are µ F ceramic capacitors dependent on power-supply quality. C and C are 10- µ F electrolytic capacitors dependent on power-supply quality. C and C are 10- µ F electrolytic capacitors. C and C are 10- µ F electrolytic capacitors. R through R are 22- Ω to 100- Ω resistors. Figure 56. Example Board Layout Termination for mode control: any one of the circuits shown in Figure must be applied according to the necessary mode/configuration. Resistor value must be 220 k Ω tolerant. The PowerPAD must be tied to the ground plane with enough electrical and thermal conductivity; see the example board layout in Figure Figure 57. Typical Circuit Connections Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM3168A PCM3168A-Q1

R11 F/c109 +Analog□Input/c45 (1□V )RMS VIN/c45 (1□V )RMS R11 F/c109 +Analog□Input+ (1□V )RMS VIN+ (1□V )RMS 1.5□k/c87 1.5□k/c87 470□pF

10 F/c109

0.1 F/c109

4.7□k/c87 4.7□k/c87 470□pF VIN/c45 (1□V )RMS VIN+ (1□V )RMS VCOMAD Analog□Input (2□V )RMS PCM3168A PCM3168A-Q1 SBAS452 SEPTEMBER 2008 www.ti.com Typical interface circuits for analog input and analog output are shown in Figure through Figure R 47- Ω to 470- Ω resistor, C 0.01-pF to 0.001- µ F capacitor; f dB 160 kHz. NOTE: The signal source impedance must be low enough to apply this configuration. Figure 58. Basic Differential Input Circuit with Anti-Aliasing LPF for Differential ADC Input Amplifier is an NE5532A or OPA2134 x2; R 1.5-k Ω resistor; R 750- Ω resistor; R 47- Ω resistor; C 3300-pF capacitor; C 0.01- µ F capacitor; Gain f dB kHz. Figure 59. Single-Ended to Differential Buffer and Anti-Aliasing LPF for Differential ADC Input Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): PCM3168A PCM3168A-Q1

22□pF VIN+ (1□V )RMS VIN/c45 (1□V )RMS VCOMAD Analog□Input (2□V )RMS (1□V )RMS VCOMAD Analog□Input (2□V )RMS VIN/c45 PCM3168A PCM3168A-Q1 www.ti.com SBAS452 SEPTEMBER 2008 Amplifier is an NE5532A or OPA2134 x1; R 3-k Ω resistor; R 1.5-k Ω resistor; R 47- Ω resistor; C 2200-pF capacitor; C 0.01- µ F capacitor; Gain f dB kHz. Figure 60. Single-Ended to Differential Buffer and Anti-Aliasing LPF for Differential ADC Input Amplifier is an NE5532A or OPA2134 x1; R 3-k Ω resistor; R 1.5-k Ω resistor; R 47- Ω resistor; C 2200-pF capacitor; C 0.022- µ F capacitor; Gain 0.5; f dB kHz. Figure 61. Buffer and Anti-Aliasing LPF for Single-Ended ADC Input Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM3168A PCM3168A-Q1

Analog□Output (2□V )RMS VOUT/c45 (4□V )PP

10 F/c109 R1 R3

(4□V )PP C2R2 47/c87 R1 R3 Analog□Output (2□V )RMS VOUT/c45 (4□V )PP R1 R3 VOUT+ (4□V )PP C2R2 PCM3168A PCM3168A-Q1 SBAS452 SEPTEMBER 2008 www.ti.com Amplifier is an NE5532A x1/2 or OPA2134 x1/2; R 7.5-k Ω resistor; R 5.6-k Ω resistor; R 360- Ω resistor; C 3300-pF capacitor; C 680-pF capacitor; Gain 0.747; f dB kHz. Figure 62. Post-LPF and Differential to Single-Ended Buffer for DAC Output (AC-Coupled) Amplifier is an NE5532A x1/2 or OPA2134 x1/2; R 15-k Ω resistor; R 11-k Ω resistor; R 820- Ω resistor; C 1500-pF capacitor; C 330-pF capacitor; Gain 0.733; f dB kHz. Figure 63. Post-LPF and Differential to Single-Ended Buffer for DAC Output (DC-Coupled) Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): PCM3168A PCM3168A-Q1

(VCCAD1/2, VCCDA1/2, and VDD1/2) Grounding (AGNDAD1/2, AGNDDA1/2, and DGND1/2) VIN1 VIN2 VIN3 VIN4 VIN5 and VIN6 Pins VCOMAD and VCOMDA Pins VREFAD1/2 Pins VOUT1 VOU2 VOUT3 VOUT4 VOUT5 VOUT6 VOU7 and VOUT8 Pins PCM3168A PCM3168A-Q1 www.ti.com SBAS452 SEPTEMBER 2008 The digital and analog power-supply pins of the PCM3168A and PCM3168A-Q1 should be bypassed to the corresponding ground pins with µ F ceramic capacitors placed as close to the pins as possible. Each power-supply line (VCC, VDD) to the PCM3168A and PCM3168A-Q1 should be bypassed to the corresponding ground pins with 10- µ F electrolytic capacitors to maximize the dynamic performance of the ADC and DAC. Although the PCM3168A and PCM3168A-Q1 have two power lines to maximize the potential of dynamic performance, using one common source (for instance, a +5-V power supply for VCC and a +3.3-V power supply for VDD generated from one common source) is recommended to avoid unexpected power-supply trouble such as latch-up or incorrect power-supply conditions. Also, simultaneous power-on/off of VCC and VDD is recommended to avoid unexpected transient responses in outputs, though the power-supply sequence of VCC and VDD is not specified in the operation and absolute maximum ratings point of view. To maximize the dynamic performance of the PCM3168A and PCM3168A-Q1, the analog and digital grounds are not connected internally. These pins should have very low impedances to avoid digital noise and signal components feeding back into the analog ground. All ground pins should be connected directly to each other under the part, and the device should be connected to the analog ground of the application, as with acceptable analog layout practices; this layout reduces the potential of noise problems. In case of direct interface to VINx µ F electrolytic capacitors are recommended because the ac-coupling capacitor (which gives a 2-Hz HPF corner frequency and Ω and 0.1 µ F to 470 Ω and 0.001 µ F differential LPF) is recommended as the anti-aliasing filter that gives a 160-kHz LPF corner frequency. If signal source impedance is not enough (too low) or input line length to the VINx is not enough (too short), insertion of an analog front-end buffer (see Figure to Figure is recommended to maximize the dynamic performance. The voltage coefficient of the capacitor for an anti-aliasing filter should be considered to maximize the THD performance. A film-type capacitor is recommended; if a ceramic capacitor is used, a relatively higher voltage type is recommended. There are three ways to terminate any unused input pins. First, terminate these pins to AGNDAD with 0.001- µ F to µ F capacitors. This termination is applied on unused pins whose channels are configured in single-ended mode. The second form of termination is to connect the positive (+) pin and negative pins together and terminating these to AGNDAD with 0.001- µ F to µ F capacitors. This option applies to unused pins with channels that are configured in differential mode. The last termination method is to terminat the pins directly to VCOMAD; this option can be applied on unused pins with unused channels combined into two channels that are then configured in power-save mode. 10- µ F electrolytic capacitors are recommended between VCOMAD and AGNDAD, and VCOMDA and AGNDDA to ensure a low source impedance of ADC and DAC common voltages. These capacitors should be located as close to each pin as possible to reduce dynamic errors on the ADC and DAC common voltages. 10- µ F electrolytic capacitors are recommended between VREFAD1/2 and AGNDAD to ensure low source impedances of ADC references. These capacitors should be located as close to each pin as possible to reduce dynamic errors on ADC references. The differential to single-ended buffer with post LPF can be directly connected (without capacitors) to these output pins (see Figure thereby minimizing the use of coupling capacitors for the 2-V RMS outputs. The op amp and resistors should be determined with consideration of degrading some performance through this differential to single-ended and LPF buffer; there is about 1.5-dB degradation seen in the examples of Figure and Figure Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM3168A PCM3168A-Q1

www.ti.com This pin is a logic input with quad-state input capability. The MODE pin is high when connected to VDD, low when connected to DGND, and pulled up or pulled down through an external resistor and for the two mid-states in order to distinguish the four input states. The pull-up or pull-down resistor must be 220 k Ω in tolerance. Note that the state of the MODE pin is only sampled by a power-on or a low-to-high transition of the RST pin. When the MODE pin setting changes to change the operating mode, the new mode setting does not take effect immediately; a RST pin toggle is required to make the new mode setting valid, and for the new mode to take effect. The OVF pin has two functions. It is primarily the flag for ADC overflow occurrence detection. It is also used to indicate that the internal reset sequence is complete and that the device is ready to enter serial mode control. The quality of SCKI may influence dynamic performance, because the PCM3168A and PCM3168A-Q1 (both the ADC and DAC) operate based on SCKI. Therefore, it may be required to consider the jitter, duty, and rise/fall time of the system clock. In slave mode, the PCM3168A and PCM3168A-Q1 do not require a specific timing relationship between BCKAD/LRCKAD and SCKI, and BCKDA/LRCKDA and SCKI; however, there is a possibility of performance degradation with a certain timing relationship between them. In that case, specific timing relationship control might resolve this performance degradation. In master mode, there is a possibility of performance degradation because of heavy loads on BCKAD/LRCKAD, BCKDA/LRCKDA, and DOUT1/2/3. It is recommended to load these pins as lightly as possible. Note that all output clocks and signals go low; they do not go into a high-impedance state during power-save mode. The PowerPAD of the PCM3168A and PCM3168A-Q1 is internally connected to the substrate of the silicon. It should be connected to the ground plane with sufficient low conductance in electrical and thermal; see Figure The PowerPAD size is 7,25 mm x 7,00 mm (0,725 cm 0.7 cm). For power-down ON/OFF control without the pop-noise that is generated by a dc level change on the DAC output, the external mute control is generally required. Use of the following control sequence is recommended: external mute ON, codec power-down ON, SCKI stop and resume if necessary, codec power-down OFF, and external mute OFF control. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): PCM3168A PCM3168A-Q1

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) PCM3168APAP ACTIVE HTQFP PAP 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR PCM3168APAPR ACTIVE HTQFP PAP 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR PCM3168APAPRG4 ACTIVE HTQFP PAP 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR PCM3168ATPAPQ1 ACTIVE HTQFP PAP 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR PCM3168ATPAPRQ1 ACTIVE HTQFP PAP 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR PCM3168ATPAPRQ1G4 ACTIVE HTQFP PAP 64 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 13-Nov-2008 Addendum-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 27-Nov-2008 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCM3168APAPR HTQFP PAP 64 1000 346.0 346.0 41.0 PCM3168ATPAPRQ1 HTQFP PAP 64 1000 346.0 346.0 41.0 PACKAGE MATERIALS INFORMATION www.ti.com 27-Nov-2008 Pack Materials-Page 2

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