PCM3070 TI | Alldatasheet
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SPI_Select IN1_R IN2_R IN3_R IN3_L IN2_L IN1_L SCL/SSZ Left ADC DRC tpl Left DAC AGC /c43 /c43 /c43 /c43 ADC Signal Proc. DAC Signal Proc. Right ADC DRC tpr Right DAC AGC ADC Signal Proc. DAC Signal Proc./c43 /c43 /c43 /c43 Vol. Ctrl Vol. Ctrl Data Interface Gain Adj. Gain Adj. +47.5 dB 0.5 dB steps 0…+47.5 dB 0.5 dB steps -6...+29dB 1dB steps -6...+29dB 1dB steps -6...+29dB 1dB steps -6...+29dB 1dB steps SPI / I2C Control Block Pin Muxing/ Clock Routing Secondary I2S IF Primary I2S Interface Interrupt Ctrl ALDO DLDO PLL RefRef LDO Select Supplies LDO in HPVdd DVddAVdd IOVddAVssDVssIOVss SDA/MOSIMISOSCLK MCLK GPIO DOUTDIN BCLKWCLK miniDSP miniDSP HPL LOL HPR LOR Reset -30...0 dB -30...0 dB -72...0dB -72...0dB /c180 /c180 /c180/c180 Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community PCM3070 SLAS724A –SEPTEMBER 2008–REVISED NOVEMBER 2014 PCM3070StereoAudioCodecWithEmbeddedminiDSP
1 Features 2 Applications
1• Stereo Audio DAC with 100dB SNR • Soundbar
- Stereo Audio ADC with 93dB SNR • Flat Panel Television
- Extensive Signal Processing Options • MP3 Docking stations
- Embedded miniDSP • Cell Phone Docking Stations
- Six Single-Ended or 3 Fully-Differential Analog • Other Stereo or 2.1 Home Audio systems Inputs
3 Description• Stereo Headphone Outputs
The PCM3070 is a flexible stereo audio codec with• Stereo Line Outputs programmable inputs and outputs, fully-• Very Low-Noise PGA programmable miniDSP, fixed predefined and
- Analog Bypass Mode parameterizable signal processing blocks, integrated PLL, integrated LDOs and flexible digital interfaces.• Programmable PLL
- Integrated LDO Device Information(1)
- 5 mm x 5 mm 32-Pin QFN Package PART NUMBER PACKAGE BODY SIZE (NOM) PCM3070 VQFN (32) 5.00 mm x 5.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet.
4 Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
SLAS724A –SEPTEMBER 2008–REVISED NOVEMBER 2014 www.ti.com Table of Contents
5 Revision History
Changes from Original (February 2011) to Revision A Page
- Added Pin Configuration and Functions section, Handling Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
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6 Device Comparison Table
PCM3070 Stereo audio codec with embedded miniDSP Copyright © 2008–2014, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: PCM3070
LDO_SELECT GPIO/MFP5 (32) SDA/MOSI MISO/MFP4 SPI_SELECT IN1_L IN1_R IN2_L IN2_R IOV SS OVI DD DOUT/MFP2DIN/MFP1WCLKBCLKMCLK (1) LORLOLIN3_RIN3_LNC REFAV SS RESET SCLK/MFP3 SCL/SSZ AV DD HPL 1 8 1724 PCM3070 SLAS724A –SEPTEMBER 2008–REVISED NOVEMBER 2014 www.ti.com
7 Pin Configuration and Functions
This document describes signals that take on different names depending on how they are configured. In such cases, the different names are placed together and separated by slash (/) characters. For example, "SCL/SS". Active low signals are represented by overbars. (Bottom View) Pin Functions PIN NAME TYPE(1) DESCRIPTION
1 MCLK DI Master Clock Input
2 BCLK DIO Audio serial data bus (primary) bit clock
3 WCLK DIO Audio serial data bus (primary) word clock
4 DIN DI Primary function:
Audio serial data bus data input MFP1 Secondary function: General Purpose Clock Input General Purpose Input
5 DOUT DO Primary function:
Audio serial data bus data output MFP2 Secondary function: General Purpose Output Clock Output INT1 Output INT2 Output Audio serial data bus (secondary) bit clock output Audio serial data bus (secondary) word clock output 6 IOVDD Power IO voltage supply 1.1V – 3.6V
7 IOVSS Ground IO ground supply
(1) DI (Digital Input), DO (Digital Output), DIO (Digital Input/Output), AI (Analog Input), AO (Analog Output), AIO (Analog Input/Output)
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www.ti.com SLAS724A –SEPTEMBER 2008–REVISED NOVEMBER 2014 Pin Functions (continued) PIN NAME TYPE(1) DESCRIPTION
8 SCLK DI Primary function: (SPI_Select = 1)
/ SPI serial clock MFP3 Secondary function: (SPI_Select = 0) Audio serial data bus (secondary) bit clock input Audio serial data bus (secondary) DAC or common word clock input Audio serial data bus (secondary) ADC word clock input Audio serial data bus (secondary) data input General Purpose Input
9 SCL/SS DI I2C interface serial clock (SPI_Select = 0)
SPI interface mode chip-select signal (SPI_Select = 1)
10 SDA/MOSI DI I2C interface mode serial data input (SPI_Select = 0)
SPI interface mode serial data input (SPI_Select = 1)
11 MISO DO Primary function: (SPI_Select = 1)
/ Serial data output MFP4 Secondary function: (SPI_Select = 0) General purpose output CLKOUT output INT1 output INT2 output Audio serial data bus (primary) ADC word clock output Audio serial data bus (secondary) data output Audio serial data bus (secondary) bit clock output Audio serial data bus (secondary) word clock output
12 SPI_ SELECT DI Control mode select pin ( 1 = SPI, 0 = I2C )
13 IN1_L AI Multifunction Analog Input,
or Single-ended configuration: Line 1 left or Differential configuration: Line right, negative
14 IN1_R AI Multifunction Analog Input,
or Single-ended configuration: or Line 1 right or Differential configuration: Line right, positive
15 IN2_L AI Multifunction Analog Input,
or Single-ended configuration: Line 2 left or Differential configuration: Line left, positive
16 IN2_R AI Multifunction Analog Input,
or Single-ended configuration: Line 2 right or Differential configuration: Line left, negative
17 AVSS Ground Analog ground supply
18 REF AO Reference voltage output for filtering
19 NC -- NC, do not connect
20 IN3_L AI Multifunction Analog Input,
or Single-ended configuration: Line 3 left, or Differential configuration: Line left, positive, or Differential configuration: Line right, negative
21 IN3_R AI Multifunction Analog Input,
or Single-ended configuration: Line 3 right, or Differential configuration: Line left, negative, or Differential configuration: Line right, positive
22 LOL AO Left line output
23 LOR AO Right line output
24 AVDD Power Analog voltage supply 1.5V–1.95V Input when A-LDO disabled, Filtering output when A-LDO enabled
25 HPL AO Left high power output driver
26 LDOIN/HPVDD Power LDO Input supply and Headphone Power supply 1.9V– 3.6V Copyright © 2008–2014, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: PCM3070
SLAS724A –SEPTEMBER 2008–REVISED NOVEMBER 2014 www.ti.com Pin Functions (continued) PIN NAME TYPE(1) DESCRIPTION
27 HPR AO Right high power output driver
28 DVSS Ground Digital Ground and Chip-substrate
29 DVDD Power If LDO_SELECT Pin = 0 (D-LDO disabled)
Digital voltage supply 1.26V – 1.95V If LDO_SELECT Pin = 1 (D-LDO enabled) Digital voltage supply filtering output
30 LDO_ SELECT DI D-LDO enable signal (1 = D-LDO enable, 0 = D-LDO disabled)
31 RESET DI Reset (active low)
32 GPIO DI Primary function:
General Purpose digital IO MFP5 Secondary function: CLKOUT Output INT1 Output INT2 Output Audio serial data bus ADC word clock output Audio serial data bus (secondary) bit clock output Audio serial data bus (secondary) word clock output Thermal Pad Thermal Pad N/A Connect to PCB ground plane. Not internally connected.
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8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT AVDD to AVSS –0.3 2.2 V DVDD to DVSS –0.3 2.2 V Input voltage IOVDD to IOVSS –0.3 3.9 V LDOIN to AVSS –0.3 3.9 V Digital Input voltage IOVDD + 0.3 V Analog input voltage AVDD + 0.3 V Operating temperature range –40 85 °C Junction temperature (TJ Max) 105 °C (1) Stresses beyond those listed under “absolute maximum ratings”may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions”is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
8.2 Handling Ratings
Tstg Storage temperature range –55 125 °C Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) –2 2 kV ElectrostaticV(ESD) Charged device model (CDM), per JEDEC specification JESD22-C101, alldischarge –750 750 Vpins(2) (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
8.3 Recommended Operating Conditions
LDOIN 1.9 3.6 Referenced to AVSS (1) AVDD 1.5 1.8 1.95 Power Supply Voltage Range V IOVDD Referenced to IOVSS (1) 1.5 3.6 DVDD (2) Referenced to DVSS (1) 1.8 1.95 Clock divider uses fractional divide 10 20 MHz(D > 0), P = 1, DVDD ≥ 1.65V PLL Input Frequency Clock divider uses integer divide 0.512 20 MHz(D = 0), P = 1, DVDD ≥ 1.65V MCLK; Master Clock Frequency; DVDD ≥ 1.65V 50 MCLK Master Clock Frequency MHz MCLK; Master Clock Frequency; DVDD ≥ 1.26V 25 SCL SCL Clock Frequency 400 kHz 0.75 orCM = 0.75 V 0 0.530 VpeakAudio input max ac signal swing AVDD-0.75(3) (IN1_L, IN1_R, IN2_L, IN2_R, IN3_L, 0.9 orIN3_R) CM = 0.9 V 0 0.707 VpeakAVDD-0.9(3) CLout Digital output load capacitance 10 pF TOPR Operating Temperature Range –40 85 °C (1) All grounds on board are tied together to prevent voltage differences of more than 0.2V maximum for any combination of ground signals. (2) At DVDD values lower than 1.65V, the PLL does not function. Refer to the Maximum PCM3070 Clock Frequencies table in the PCM3070 (3) Whichever is smaller. Copyright © 2008–2014, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: PCM3070
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8.4 Thermal Information
THERMAL METRIC(1) RHB (QFN) UNIT
32 PINS
RθJA Junction-to-ambient thermal resistance 31.4 RθJCtop Junction-to-case (top) thermal resistance 21.4 RθJB Junction-to-board thermal resistance 5.4 °C/W ψJT Junction-to-top characterization parameter 0.2 ψJB Junction-to-board characterization parameter 5.4 RθJCbot Junction-to-case (bottom) thermal resistance 0.9 (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
8.5 Electrical Characteristics, ADC
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AUDIO ADC (1) (2) Input signal level (0dB) Single-ended, CM = 0.9V 0.5 VRMS 1kHz sine wave input , Single-ended Configuration IN1_R to Right ADC and IN1_L to Left ADC, Rin = 20K, fs = 48kHz,Device Setup AOSR = 128, MCLK = 256 x fs, PLL Disabled; AGC = OFF, Channel Gain = 0dB, Processing Block = PRB_R1, Inputs ac-shorted to ground 80 93 SNR Signal-to-noise ratio, A-weighted(1)(2) dBIN2_R, IN3_R routed to Right ADC and ac-shorted to ground 93IN2_L, IN3_L routed to Left ADC and ac-shorted to ground DR Dynamic range A-weighted(1)(2) –60dB full-scale, 1-kHz input signal 92 dB –3 dB full-scale, 1-kHz input signal –85 –70 IN2_R, IN3_R routed to Right ADCTHD+N Total Harmonic Distortion plus Noise dB IN2_L, IN3_L routed to Left ADC –85 –3dB full-scale, 1-kHz input signal AUDIO ADC Input signal level (0dB) Single-ended, CM = 0.75V, AVDD = 1.5V 0.375 VRMS 1kHz sine wave input, Single-ended Configuration IN1_R, IN2_R, IN3_R routed to Right ADC IN1_L, IN2_L, IN3_L routed to Left ADC Device Setup Rin = 20kΩ, fs = 48kHz, AOSR = 128, MCLK = 256 x fs, PLL Disabled, AGC = OFF, Channel Gain = 0dB, Processing Block = PRB_R1 SNR Signal-to-noise ratio, A-weighted (1)(2) Inputs ac-shorted to ground 91 dB DR Dynamic range A-weighted(1)(2) –60dB full-scale, 1-kHz input signal 90 dB THD+N Total Harmonic Distortion plus Noise –3dB full-scale, 1-kHz input signal –80 dB (1) Ratio of output level with 1kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a 20Hz to 20kHz bandwidth using an audio analyzer. (2) All performance measured with 20kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of- band noise, which, although not audible, may affect dynamic specification values.
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www.ti.com SLAS724A –SEPTEMBER 2008–REVISED NOVEMBER 2014 Electrical Characteristics, ADC (continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AUDIO ADC Input signal level (0dB) Differential Input, CM = 0.9V 10 mV 1kHz sine wave input, Differential configuration IN1_L and IN1_R routed to Right ADC IN2_L and IN2_R routed to Left ADCDevice Setup Rin = 10K, fs = 48kHz, AOSR = 128 MCLK = 256* fs PLL Disabled AGC = OFF, Channel Gain = 40dB Processing Block = PRB_R1, ICN Idle-Channel Noise, A-weighted(1)(2) Inputs ac-shorted to ground, input referred noise 2 μVRMS AUDIO ADC 1kHz sine wave input , Single-ended configuration Rin = 20kΩ fs = 48kHz, AOSR = 128, Gain Error MCLK = 256 x fs, PLL Disabled –0.05 dB AGC = OFF, Channel Gain = 0dB Processing Block = PRB_R1, 1kHz sine wave input at -3dBFS Single-ended configuration IN1_L routed to Left ADCInput Channel Separation 108 dBIN1_R routed to Right ADC, Rin = 20kΩ AGC = OFF, AOSR = 128, Channel Gain = 0dB, CM = 0.9V 1kHz sine wave input at –3dBFS on IN2_L, IN2_L internally not routed. IN1_L routed to Left ADC ac-coupled to ground 1kHz sine wave input at –3dBFS on IN2_R,Input Pin Crosstalk 115 dBIN2_R internally not routed. IN1_R routed to Right ADC ac-coupled to ground Single-ended configuration Rin = 20kΩ, AOSR = 128 Channel, Gain = 0dB, CM = 0.9V 217Hz, 100mVpp signal on AVDD, PSRR Single-ended configuration, Rin = 20kΩ, 55 dB Channel Gain = 0dB; CM = 0.9V Single-Ended, Rin = 10kΩ, PGA gain set to 0dB 0 dB Single-Ended, Rin = 10kΩ, PGA gain set to 47.5dB 47.5 dB Single-Ended, Rin = 20kΩ, PGA gain set to 0dB –6 dBADC programmable gain amplifier gain Single-Ended, Rin = 20kΩ, PGA gain set to 47.5dB 41.5 dB Single-Ended, Rin = 40kΩ, PGA gain set to 0dB –12 dB Single-Ended, Rin = 40kΩ, PGA gain set to 47.5dB 35.5 dB ADC programmable gain amplifier 1-kHz tone 0.5 dB step size Copyright © 2008–2014, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: PCM3070
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8.6 Electrical Characteristics, Bypass Outputs
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG BYPASS TO HEADPHONE AMPLIFIER, DIRECT MODE Load = 16Ω (single-ended), 50pF; Input and Output CM = 0.9V; Headphone Output on LDOIN Supply;Device Setup IN1_L routed to HPL and IN1_R routed to HPR; Channel Gain = 0dB Gain Error –0.8 dB Idle Channel, IN1_L and IN1_R ac-shorted toNoise, A-weighted(1) 3 μVRMSground THD Total Harmonic Distortion 446mVrms, 1kHz input signal –89 dB ANALOG BYPASS TO LINE-OUT AMPLIFIER, PGA MODE Load = 10kΩ (single-ended), 56pF; Input and Output CM = 0.9V; LINE Output on LDOIN Supply; Device Setup IN1_L routed to ADCPGA_L and IN1_R routed to ADCPGA_R; Rin = 20kΩ ADCPGA_L routed to LOL and ADCPGA_R routed to LOR; Channel Gain = 0dB Gain Error 0.6 dB Idle Channel, 7 μVRMSIN1_L and IN1_R ac-shorted to ground Noise, A-weighted(1) Channel Gain = 40dB, Input Signal (0dB) = 5mVrms 3.4 μVRMS Inputs ac-shorted to ground, Input Referred (1) All performance measured with 20kHz low-pass filter and, where noted, A-weighted filter. Testing without such a filter may result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values.
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8.7 Electrical Characteristics, Audio DAC Outputs
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AUDIO DAC – STEREO SINGLE-ENDED LINE OUTPUT Load = 10kΩ (single-ended), 56pF Line Output on AVDD Supply Input and Output CM = 0.9VDevice Setup DOSR = 128, MCLK = 256 x fs, Channel Gain = 0dB, word length = 16 bits, Processing Block = PRB_P1, Full scale output voltage (0dB) 0.5 VRMS SNR Signal-to-noise ratio A-weighted(1)(2) All zeros fed to DAC input 87 100 dB –60dB 1kHz input full-scale signal, WordDR Dynamic range, A-weighted(1)(2) 100 dBlength = 20 bits THD+N Total Harmonic Distortion plus Noise –3dB full-scale, 1kHz input signal –83 –70 dB DAC Gain Error 0 dB, 1kHz input full scale signal 0.3 dB DAC Mute Attenuation Mute 119 dB DAC channel separation –1 dB, 1kHz signal, between left and right HP 113 dB out 100mVpp, 1kHz signal applied to AVDD 73 dB DAC PSRR 100mVpp, 217Hz signal applied to AVDD 77 dB AUDIO DAC – STEREO SINGLE-ENDED LINE OUTPUT Load = 10kΩ (single-ended), 56pF Line Output on AVDD Supply Input and Output CM = 0.75V; AVDD = 1.5V DOSR = 128Device Setup MCLK = 256 * fs Channel Gain = –2dB word length = 20 bits Processing Block = PRB_P1 Full scale output voltage (0dB) 0.375 VRMS SNR Signal-to-noise ratio, A-weighted(1)(2) All zeros fed to DAC input 99 dB DR Dynamic range, A-weighted(1)(2) –60dB 1 kHz input full-scale signal 97 dB THD+N Total Harmonic Distortion plus Noise –1 dB full-scale, 1-kHz input signal –85 dB AUDIO DAC – STEREO SINGLE-ENDED HEADPHONE OUTPUT Load = 16Ω (single-ended), 50pF Headphone Output on AVDD Supply, Input and Output CM = 0.9V, DOSR = 128,Device Setup MCLK = 256 * fs, Channel Gain = 0dB word length = 16 bits; Processing Block = PRB_P1 Full scale output voltage (0dB) 0.5 VRMS SNR Signal-to-noise ratio, A-weighted(1)(2) All zeros fed to DAC input 87 100 dB –60dB 1kHz input full-scale signal, WordDR Dynamic range, A-weighted(1)(2) 99 dBLength = 20 bits THD+N Total Harmonic Distortion plus Noise –3dB full-scale, 1kHz input signal –83 –70 dB DAC Gain Error 0dB, 1kHz input full scale signal –0.3 dB DAC Mute Attenuation Mute 122 dB DAC channel separation –1dB, 1kHz signal, between left and right HP 110 dB out 100mVpp, 1kHz signal applied to AVDD 73 dB DAC PSRR 100mVpp, 217Hz signal applied to AVDD 78 dB (1) Ratio of output level with 1kHz full-scale sine wave input, to the output level with the inputs short circuited, measured A-weighted over a 20Hz to 20kHz bandwidth using an audio analyzer. (2) All performance measured with 20kHz low-pass filter and, where noted, A-weighted filter. Testing without such a filter may result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values Copyright © 2008–2014, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: PCM3070
SLAS724A –SEPTEMBER 2008–REVISED NOVEMBER 2014 www.ti.com Electrical Characteristics, Audio DAC Outputs (continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RL = 16Ω, Output Stage on AVDD = 1.8V THDN < 1%, Input CM = 0.9V, 15 Output CM = 0.9V Power Delivered mW RL = 16Ω Output Stage on LDOIN = 3.3V, THDN < 1% Input CM = 0.9V, 64 Output CM = 1.65V AUDIO DAC – STEREO SINGLE-ENDED HEADPHONE OUTPUT Load = 16Ω (single-ended), 50pF, Headphone Output on AVDD Supply, Input and Output CM = 0.75V; AVDD = 1.5V,Device Setup DOSR = 128, MCLK = 256 * fs, Channel Gain = –2dB, word length = 20-bits; Processing Block = PRB_P1, Full scale output voltage (0dB) 0.375 VRMS SNR Signal-to-noise ratio, A-weighted(1)(2) All zeros fed to DAC input 99 dB DR Dynamic range, A-weighted(1)(2) -60dB 1kHz input full-scale signal 98 dB THD+N Total Harmonic Distortion plus Noise –1dB full-scale, 1kHz input signal –83 dB AUDIO DAC – MONO DIFFERENTIAL HEADPHONE OUTPUT Load = 32Ω (differential), 50pF, Headphone Output on LDOIN Supply Input CM = 0.75V, Output CM = 1.5V, AVDD = 1.8V, LDOIN = 3.0V, DOSR = 128Device Setup MCLK = 256 * fs, Channel (headphone driver) Gain = 5dB for full scale output signal, word length = 16 bits, Processing Block = PRB_P1, Full scale output voltage (0dB) 1778 mVRMS SNR Signal-to-noise ratio, A-weighted(1)(2) All zeros fed to DAC input 98 dB DR Dynamic range, A-weighted(1)(2) –60dB 1kHz input full-scale signal 96 dB THD Total Harmonic Distortion –3dB full-scale, 1kHz input signal –82 dB RL = 32Ω, Output Stage on LDOIN = 3.3V, THDN < 1%, Input CM = 0.9V, 136 mW Output CM = 1.65V Power Delivered RL = 32Ω Output Stage on LDOIN = 3.0V, THDN < 1% Input CM = 0.9V, 114 mW Output CM = 1.5V
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8.8 Electrical Characteristics, LDO
over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LOW DROPOUT REGULATOR (AVdd) LDOMode = 1, LDOIN > 1.95V 1.67 Output Voltage LDOMode = 0, LDOIN > 2.0V 1.72 V LDOMode = 2, LDOIN > 2.05V 1.77 Output Voltage Accuracy ±2% Load Regulation Load current range 0 to 50mA 15 mV Line Regulation Input Supply Range 1.9V to 3.6V 5 mV Decoupling Capacitor 1 μF Bias Current 60 μA 8.9 Electrical Characteristics, Misc. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT REFERENCE CMMode = 0 (0.9V) 0.9 Reference Voltage Settings V CMMode = 1 (0.75V) 0.75 Reference Noise CM = 0.9V, A-weighted, 20Hz to 20kHz bandwidth, 1 μVRfcMS Cref = 10μF Decoupling Capacitor 1 10 μF miniDSP(1) Maximum miniDSP clock frequency - ADC DVDD = 1.65V 55.3 MHz Maximum miniDSP clock frequency - DAC DVDD = 1.65V 55.3 MHz Shutdown Current Coarse AVdd supply turned off, LDO_select held atDevice Setup ground, No external digital input is toggled I(DVDD) 0.9 μA I(IOVDD) 13 nA (1) miniDSP clock speed is specified by design and not tested in production.
8.10 Electrical Characteristics, Logic Levels(1)
At 25°C, AVDD, DVDD, IOVDD = 1.8V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LOGIC FAMILY CMOS IIH = 5 μA, IOVDD > 1.6V 0.7 × IOVDD V VIH Logic Level IIH = 5μA, 1.2V ≤ IOVDD < 1.6V 0.9 × IOVDD V IIH = 5μA, IOVDD < 1.2V IOVDD V IIL = 5 μA, IOVDD > 1.6V –0.3 0.3 × IOVDD V VIL IIL = 5μA, 1.2V ≤ IOVDD < 1.6V 0.1 × IOVDD V IIL = 5μA, IOVDD < 1.2V 0 V VOH IOH = 2 TTL loads 0.8 × IOVDD V VOL IOL = 2 TTL loads 0.1 × IOVDD V Capacitive Load 10 pF (1) Applies to all DI, DO, and DIO pins shown in Pin Configuration and Functions. Copyright © 2008–2014, Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Links: PCM3070
8.11 I2S LJF and RJF Timing in Master Mode (see Figure 1)
Figure 1. I2S LJF and RJF Timing in Master Mode
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8.12 I2S LJF and RJF Timing in Slave Mode (see Figure 2)
Figure 2. I2S LJF and RJF Timing in Slave Mode
8.13 DSP Timing in Master Mode (see Figure 3)
Figure 3. DSP Timing in Master Mode
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8.14 DSP Timing in Slave Mode (see Figure 4)
Figure 4. DSP Timing in Slave Mode
8.15 I2C Interface Timing
tHD;STA Hold time (repeated) START condition. After this 4.0 0.8 μsperiod, the first clock pulse is generated. Figure 5. I2C Interface Timing
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8.16 SPI Interface Timing (See Figure 6)
(1) These parameters are based on characterization and are not tested in production. Figure 6. SPI Interface Timing Diagram
8.17 Typical Characteristics
8.17.1 Typical Performance
Figure 7. ADC SNR vs Channel Gain Figure 8. Total Harmonic Distortion vs Headphone Output Figure 9. Total Harmonic Distortion vs Headphone Output Figure 10. Headphone SNR and Output Power vs Output Figure 11. LDO Dropout Voltage vs Load Current Figure 12. LDO Load Response
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8.17.2 Typical Characteristics, FFT
Figure 14. Playback to Headphone FFT at -1dBFS vsFigure 13. Single Ended Line Input to ADC FFT at -1dBr vs Figure 16. Line Input to Headphone FFT at 446mVrms vsFigure 15. DAC Playback to Line-out FFT at -1dBFS vs Figure 17. Line Input to Line-out FFT at 446mVrms vs Frequency
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9 Parameter Measurement Information
All parameters are measured according to the conditions described in the Specifications section.
10 Detailed Description
10.1 Overview
The PCM3070 features two fully-programmable miniDSP cores that support application-specific algorithms in the record and/or the playback path of the device. The miniDSP cores are fully software controlled. Target algorithms, like speaker EQ, Crossovers, Dynamic Range Controls, Intelligent volume controls and other post- processing algorithms are loaded into the device after power-up. Extensive register-based control of input/output channel configuration, gains, effects, pin-multiplexing and clocks is included, allowing the device to be precisely targeted to its application. The record path of the PCM3070 covers operations from 8kHz mono to 192kHz stereo recording, and contains programmable input channel configurations covering single-ended and differential setups, as well as floating or mixed input signals. The playback path offers signal-processing blocks for filtering and effects, and supports flexible mixing of DAC and analog input signals as well as programmable volume controls. The playback path contains two high-power output drivers as well as two fully-differential outputs. The high-power outputs can be configured in multiple ways, including stereo and mono BTL. system-level design, LDOs are integrated to generate the appropriate analog or digital supply from input voltages The required internal clock of the PCM3070 can be derived from multiple sources, including the MCLK pin, the BCLK pin, the GPIO pin or the output of the internal PLL, where the input to the PLL again can be derived from the MCLK pin, the BCLK or GPIO pins. The PLL is highly programmable and can accept available input clocks in the range of 512kHz to 50MHz.
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Product Folder Links: PCM3070
10.2 Functional Block Diagram
Figure 18 shows the basic functional blocks of the device. Figure 18. Block Diagram
10.3 Feature Description
10.3.1 Device Connections
10.3.1.1 Digital Pins
default function, and also can be reprogrammed to cover alternative functions for various applications. SPI_Select, the two control-bus pins SCL/SS and SDA/MOSI are configured for either I2C or SPI protocol. functionality is given in Multifunction Pins.
10.3.1.1.1 Multifunction Pins
programmed to be any of 4 pins (MCLK, BCLK, DIN, GPIO). Table 1. Multifunction Pin Assignments (1) S(1): The MCLK pin can drive the PLL and Codec Clock inputs simultaneously. (2) S(2): The BCLK pin can drive the PLL and Codec Clock and audio interface bit clock inputs simultaneously. (3) S(3): The GPIO/MFP5 pin can drive the PLL and Codec Clock inputs simultaneously.
10.3.1.2 Analog Pins
blocks can be powered up with fine granularity according to the application needs.
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10.3.2 Analog Audio I/O
The analog IO path of the PCM3070 features a large set of options for signal conditioning as well as signal routing:
- 6 analog inputs which can be mixed and-or multiplexed in single-ended and-or differential configuration
- 2 programmable gain amplifiers (PGA) with a range of 0 to +47.5dB
- 2 mixer amplifiers for analog bypass
- 2 low power analog bypass channels
- Mute function
- Automatic gain control (AGC)
- Channel-to-channel phase adjustment
- Fast charge of ac-coupling capacitors
- Anti thump
10.3.2.1 Analog Bypass
The PCM3070 offers two analog-bypass modes. In either of the modes, an analog input signal can be routed from an analog input pin to an amplifier driving an analog output pin. Neither the ADC nor the DAC resources are required for such operation. In analog low-power bypass mode, line-level signals can be routed directly from the analog inputs INL to the left headphone amplifier (HPL) and INR to HPR.
10.3.2.2 ADC Bypass Using Mixer Amplifiers
In addition to the analog bypass mode, another bypass mode uses the programmable gain amplifiers of the input stage in conjunction with a mixer amplifier. With this mode, low-level signals can be amplified and routed to the line or headphone outputs, fully bypassing the ADC and DAC. To enable this mode, the mixer amplifiers are powered on via software command.
10.3.2.3 Headphone Output
The stereo headphone drivers on pins HPL and HPR can drive loads with impedances down to 16Ω in single- ended AC-coupled headphone configurations, or loads down to 32Ω in differential mode, where a speaker is connected between HPL and HPR. In single-ended drive configuration these drivers can drive up to 15mW power into each headphone channel while operating from 1.8V analog supplies. While running from the AVdd supply, the output common-mode of the headphone driver is set by the common-mode setting of analog inputs in Page 1 / Register 10, Bit D6, to allow maximum utilization of the analog supply range while simultaneously providing a higher output-voltage swing. In cases when higher output-voltage swing is required, the headphone amplifiers can run directly from the higher supply voltage on LDOIN input (up to 3.6V). To use the higher supply voltage for higher output signal swing, the output common-mode can be adjusted to either 1.25V, 1.5V or 1.65V by configuring Page 1 / Register 10, Bits D5-D4. When the common-mode voltage is configured at 1.65V and LDOIN supply is 3.3V, the headphones can each deliver up to 40mW power into a 16Ω load. The headphone drivers are capable of driving a mixed combination of DAC signal and bypass from analog input INL and INR by configuring Page 1 / Register 12 and Page 1 / Register 13 respectively. The analog input signals can be attenuated up to 72dB before routing by configuring Page 1 / Register 22 and 23. The level of the DAC signal can be controlled using the digital volume control of the DAC in Page 0, Reg 65 and 66. To control the output-voltage swing of headphone drivers, the digital volume control provides a range of –6.0dB to +29.0dB(6) in steps of 1dB. These can be configured by programming Page 1 / Register 16 and 17. These level controls are not meant to be used as dynamic volume control, but more to set output levels during initial device configuration.
10.3.2.4 Line Outputs
The stereo line level drivers on LOL and LOR pins can drive a wide range of line level resistive impedances in the range of 600Ω to 10kΩ. The output common modes of line level drivers can be configured to equal either the analog input common-mode setting, or 1.65V. With output common-mode setting of 1.65V and DRVdd_HP supply at 3.3V the line-level drivers can drive up to 1Vrms output signal. The line-level drivers can drive out a mixed combination of DAC signal and attenuated ADC PGA signal. Signal mixing is register-programmable. Copyright © 2008–2014, Texas Instruments Incorporated Submit Documentation Feedback 25 Product Folder Links: PCM3070
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10.3.3 ADC
The PCM3070 includes a stereo audio ADC, which uses a delta-sigma modulator with a programmable oversampling ratio, followed by a digital decimation filter. The stereo recording path can be powered up one channel at a time, to support the case where only mono record capability is required. The ADC path of the PCM3070 features a large set of options for signal conditioning as well as signal routing:
- Two ADCs
- Six analog inputs which can be mixed and-or multiplexed in single-ended and-or differential configuration
- Two programmable gain amplifiers (PGA) with a range of 0 to +47.5dB
- Two mixer amplifiers for analog bypass
- Two analog bypass channels
- Fine gain adjustment of digital channels with 0.1dB step size
- Digital volume control with a range of -12 to +20dB
- Mute function
- Automatic gain control (AGC) In addition to the standard set of ADC features the PCM3070 also offers the following special functions:
- Channel-to-channel phase adjustment
- Fast charge of ac-coupling capacitors
- Anti thump
- Adaptive filter mode
10.3.3.1 ADC Processing
The PCM3070 offers a range of processing blocks which implement various signal processing capabilities along with decimation filtering. These processing blocks give users the choice of how much and what type of signal processing they may use and which decimation filter is applied.
10.3.3.1.1 ADC Processing Blocks
The PCM3070 offers a range of processing blocks which implement various signal processing capabilities along with decimation filtering. These processing blocks give users the choice of how much and what type of signal processing they may use and which decimation filter is applied. Table 2 gives an overview of the available processing blocks and their properties. The signal processing blocks available are:
- First-order IIR
- Scalable number of biquad filters
- Variable-tap FIR filter
- AGC The processing blocks are tuned for common cases and can achieve high anti-alias filtering or low group delay in combination with various signal processing effects such as audio effects and frequency shaping. The available first order IIR, BiQuad and FIR filters have fully user-programmable coefficients. The Resource Class Column (RC) gives an approximate indication of power consumption.
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Table 2. ADC Processing Blocks For more detailed information see the PCM3070 Application Reference Guide, SLAU332.
10.3.4 DAC
oversampling ratios for higher input data rates. frequency response, group delay and sampling rate.
- 2 headphone amplifiers – Usable in single-ended or differential mode – Analog volume setting with a range of -6 to +29dB
- 2 line-out amplifiers – Usable in single-ended or differential mode – Analog volume setting with a range of -6 to +29dB
- Digital volume control with a range of -63.5 to +24dB
- Mute function
- Dynamic range compression (DRC) Copyright © 2008–2014, Texas Instruments Incorporated Submit Documentation Feedback 27 Product Folder Links: PCM3070
- Built in sine wave generation (beep generator)
- Digital auto mute
- Adaptive filter mode
10.3.4.1 DAC Processing Blocks — Overview
which interpolation filter is applied. Resource Class Column (RC) gives an approximate indication of power consumption.
- First-order IIR
- Scalable number of biquad filters
- 3D – Effect
- Beep Generator The processing blocks are tuned for typical cases and can achieve high image rejection or low group delay in combination with various signal processing effects such as audio effects and frequency shaping. The available first-order IIR and biquad filters have fully user-programmable coefficients. The Resource Class Column (RC) gives an approximate indication of power consumption.
Table 3. Overview – DAC Predefined Processing Blocks
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10.3.5 Digital Audio IO Interface
Audio data is transferred between the host processor and the PCM3070 via the digital audio data serial interface, or audio bus. The audio bus on this device is very flexible, including left or right-justified data options, support for I2S or PCM protocols, programmable data length options, a TDM mode for multichannel operation, very flexible master/slave configurability for each bus clock line, and the ability to communicate with multiple devices within a system directly. The audio bus of the PCM3070 can be configured for left or right-justified, I2S, DSP, or TDM modes of operation, where communication with standard PCM interfaces is supported within the TDM mode. These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits by configuring Page 0, Register 27, D(5:4). In addition, the word clock and bit clock can be independently configured in either Master or Slave mode, for flexible connectivity to a wide variety of processors. The word clock is used to define the beginning of a frame, and may be programmed as either a pulse or a square-wave signal. The frequency of this clock corresponds to the maximum of the selected ADC and DAC sampling frequencies. The bit clock is used to clock in and clock out the digital audio data across the serial bus. When in Master mode, this signal can be programmed to generate variable clock pulses by controlling the bit-clock divider in Page 0, Register 30. The number of bit-clock pulses in a frame may need adjustment to accommodate various word- lengths as well as to support the case when multiple PCM3070s may share the same audio bus. The PCM3070 also includes a feature to offset the position of start of data transfer with respect to the word- clock. This offset can be controlled in terms of number of bit-clocks and can be programmed in Page 0, Register 28. The PCM3070 also has the feature of inverting the polarity of the bit-clock used for transferring the audio data as compared to the default clock polarity used. This feature can be used independently of the mode of audio interface chosen. This can be configured via Page 0, Register 29, D(3). The PCM3070 further includes programmability (Page 0, Register 27, D0) to place the DOUT line into a hi-Z (3- state) condition during all bit clocks when valid data is not being sent. By combining this capability with the ability to program at what bit clock in a frame the audio data begins, time-division multiplexing (TDM) can be accomplished, enabling the use of multiple codecs on a single audio serial data bus. When the audio serial data bus is powered down while configured in master mode, the pins associated with the interface are put into a hi-Z output condition. By default when the word-clocks and bit-clocks are generated by the PCM3070, these clocks are active only when the codec (ADC, DAC or both) are powered up within the device. This is done to save power. However, it also supports a feature when both the word clocks and bit-clocks can be active even when the codec in the device is powered down. This is useful when using the TDM mode with multiple codecs on the same bus, or when word-clock or bit-clocks are used in the system as general-purpose clocks.
10.3.6 Clock Generation and PLL
The PCM3070 supports a wide range of options for generating clocks for the ADC and DAC sections as well as interface and other control blocks. The clocks for ADC and DAC require a source reference clock. This clock can be provided on variety of device pins such as MCLK, BCLK or GPI pins. The CODEC_CLKIN can then be routed through highly-flexible clock dividers to generate the various clocks required for ADC, DAC and the miniDSP sections. In the event that the desired audio or miniDSP clocks cannot be generated from the reference clocks on MCLK BCLK or GPIO, the PCM3070 also provides the option of using the on-chip PLL which supports a wide range of fractional multiplication values to generate the required clocks. Starting from CODEC_CLKIN the PCM3070 provides several programmable clock dividers to help achieve a variety of sampling rates for ADC, DAC and clocks for the miniDSP. For more detailed information see the PCM3070 Application Reference Guide, SLAU332.
10.3.7 Control Interfaces
The PCM3070 control interface supports SPI or I2C communication protocols, with the protocol selectable using the SPI_SELECT pin. For SPI, SPI_SELECT should be tied high; for I2C, SPI_SELECT should be tied low. Changing the state of SPI_SELECT during device operation is not recommended. Copyright © 2008–2014, Texas Instruments Incorporated Submit Documentation Feedback 29 Product Folder Links: PCM3070
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10.3.7.1 I2C Control
The PCM3070 supports the I2C control protocol, and will respond to the I2C address of 0011000. I2C is a two- wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the I2C bus only drive the bus lines LOW by connecting them to ground; they never drive the bus lines HIGH. Instead, the bus wires are pulled HIGH by pullup resistors, so the bus wires are HIGH when no device is driving them LOW. This circuit prevents two devices from conflicting; if two devices drive the bus simultaneously, there is no driver contention.
10.3.7.2 SPI Control
In the SPI control mode, the PCM3070 uses the pins SCL/SS as SS, SCLK as SCLK, MISO as MISO, SDA/MOSI as MOSI; a standard SPI port with clock polarity setting of 0 (typical microprocessor SPI control bit CPOL = 0). The SPI port allows full-duplex, synchronous, serial communication between a host processor (the master) and peripheral devices (slaves). The SPI master (in this case, the host processor) generates the synchronizing clock (driven onto SCLK) and initiates transmissions. The SPI slave devices (such as the PCM3070) depend on a master to start and synchronize transmissions. A transmission begins when initiated by an SPI master. The byte from the SPI master begins shifting in on the slave MOSI pin under the control of the master serial clock (driven onto SCLK). As the byte shifts in on the MOSI pin, a byte shifts out on the MISO pin to the master shift register. For more detailed information see the PCM3070 Application Reference Guide, SLAU332.
10.4 Device Functional Modes
The following special functions are available to support advanced system requirements:
- Interrupt generation
- Flexible pin multiplexing For more detailed information see the PCM3070 Application Reference Guide, SLAU332.
10.4.1 MiniDSP
The PCM3070 features two miniDSP cores. The first miniDSP core is tightly coupled to the ADC, the second miniDSP core is tightly coupled to the DAC. The fully programmable algorithms for the miniDSP must be loaded into the device after power up. The miniDSPs have direct access to the digital stereo audio stream on the ADC and on the DAC side, offering the possibility for advanced, very-low group delay DSP algorithms. Each miniDSP can run up to 1152 instructions on every audio sample at a 48kHz sample rate. The two cores can run fully synchronized and can exchange data.
10.4.2 Software
Software development for the PCM3070 is supported through TI's comprehensive PurePath Studio Development Environment; a powerful, easy-to-use tool designed specifically to simplify software development on the PCM3070 miniDSP audio platform. The Graphical Development Environment consists of a library of common audio functions that can be dragged-and-dropped into an audio signal flow and graphically connected together. The DSP code can then be assembled from the graphical signal flow with the click of a mouse. Please visit the PCM3070 product folder on www.ti.com to learn more about PurePath Studio and the latest status on available, ready-to-use DSP algorithms.
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10.5 Register Map
10.5.1 Register Map Summary
Table 4. Summary of Register Map
Table 4. Summary of Register Map (continued)
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0.047 F/c109
47 F/c109
1 F/c109100/c87
0.47 F/c109
validate and test their design implementation to confirm system functionality.
11.1 Application Information
playback and needing to interface with other devices in the system over a digital audio interface.
11.2 Typical Application
Figure 19 shows a typical circuit configuration for a system using the PCM3070. Figure 19. Typical Circuit Configuration
11.2.1 Design Requirements
11.2.1.1 Reference Filtering Capacitor
11.2.2 Detailed Design Procedures
11.2.2.1 Analog Input Connection
combination with the selected input impedance of PCM3070 forms a high-pass filter. where g is the analog PGA gain calculated in linear terms. programmed in P1_R52-R57 and assumes Rin = Rcm (as defined in P1_R52-R57). where Rin is the value of the resistor programmed in P1_R52-R57, assuming symmetrical inputs. Figure 20. Analog Input Connection With Pull-down Resistor resistor value should be chosen large enough to avoid loading of signal source. resistor values of the network should be chosen to provide desired attenuation as well as Equation 6.
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Figure 21. Analog Input Connection With Resistor Divider Network ground using a small capacitor (example 0.1 µF).
11.2.2.2 Analog Output Connection
coupling capacitor. The ac-coupling capacitor in combination with the load impedance forms a high pass filter. with RL of 10 kΩ, using 1-µF coupling capacitor results in a cut-off frequency of 8 Hz. be left open or not connected.
11.2.3 Application Curves
Figure 23 shows the distortion performance of the PCM3070 in a system over the input amplitude range. Figure 22. Total Harmonic Distortion + Noise vs Figure 23. Total Harmonic Distortion + Noise vs
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12 Power Supply Recommendations
To power up the device, a 3.3V system rail (1.9V to 3.6V) can be used. The IOVDD voltage can be in the range of 1.1V – 3.6V. Internal LDOs can generate the appropriate digital and analog core voltages when configured to do so. For maximum flexibility, the respective voltages can also be supplied externally, bypassing the built-in LDOs. To support high-output drive capabilities, the output stages of the output amplifiers can be driven from the analog core voltage or the 1.9… 3.6V rail used for the LDO inputs (LDO_in). The AVDD and LDOIN power inputs are used to power the analog circuits including analog to digital converters, digital to analog converters, programmable gain amplifiers, headphone amplifiers, etc. The analog blocks in PCM3070 have high power supply rejection ratio, however it is recommended that these supplies be powered by well regulated power supplies like low dropout regulators (LDO) for optimal performance. When these power terminals are driven from a common power source, the current drawn from the source will depend upon blocks enabled inside the device. However as an example when all the internal blocks powered are enabled the source should be able to deliver 150mA of current. The DVDD powers the digital core of PCM3070, including the miniDSP, the audio serial interface, control interfaces (SPI or I2C), clock generation and PLL. The DVDD power can be driven by high efficiency switching regulators or low drop out regulators. When the miniDSP_A and miniDSP_D are enabled in programmable mode and operated at peak frequencies, the supply source should be able to able to deliver approx 100mA of current. When the PRB modes are used instead of programmable miniDSP mode, then the peak current load on DVDD supply source could be approximately 20 mA. The IOVDD powers the digital input and digital output buffers of PCM3070. The current consumption of this power depends on configuration of digital terminals as inputs or outputs. When the digital terminals are configured as outputs, the current consumption would depend on switching frequency of the signal and the load on the output terminal, which depends on board design and input capacitance of other devices connected to the signal. Refer to Figure 19 for recommendations on decoupling capacitors. For more detailed information see the PCM3070 Application Reference Guide, SLAU332.
13 Layout
13.1 Layout Guidelines
Each system design and PCB layout is unique. The layout should be carefully reviewed in the context of a specific PCB design. However, the following guidelines can optimize PCM3070 performance:
- Connect the thermal pad to ground.
- The decoupling capacitors for the power supplies should be placed close to the device terminals. Figure 19 shows the recommended decoupling capacitors for the PCM3070.
- The PCM3070 internal voltage references must be filtered using external capacitors. Place the filter capacitors on REF near the device terminals for optimal performance.
- For analog differential audio signals, the signals should be routed differentially on the PCB for better noise immunity. Avoid crossing of digital and analog signals to avoid undesirable crosstalk. Copyright © 2008–2014, Texas Instruments Incorporated Submit Documentation Feedback 39 Product Folder Links: PCM3070
1 MCLK
- Use differential signaling.
common mode rejection of external noise. clocks and high current traces.
13.2 Layout Example
Figure 24. Layout
- http://www.ti.com/tool/PCM3070RHBEVM-K
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14 Device and Documentation Support
14.1 Documentation Support
14.1.1 Related Documentation
14.2 Trademarks
All trademarks are the property of their respective owners.
14.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
14.4 Glossary
SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.
15 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2008–2014, Texas Instruments Incorporated Submit Documentation Feedback 41 Product Folder Links: PCM3070
www.ti.com 17-Jun-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) PCM3070IRHBR Active Production VQFN (RHB) | 32 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 PCM3070 I PCM3070IRHBR.A Active Production VQFN (RHB) | 32 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 PCM3070 I PCM3070IRHBT Active Production VQFN (RHB) | 32 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 PCM3070 I PCM3070IRHBT.A Active Production VQFN (RHB) | 32 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 PCM3070 I PCM3070IRHBTG4 Active Production VQFN (RHB) | 32 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 PCM3070 I PCM3070IRHBTG4.A Active Production VQFN (RHB) | 32 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 PCM3070 I (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Addendum-Page 1
www.ti.com 17-Jun-2025 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCM3070IRHBR VQFN RHB 32 3000 346.0 346.0 33.0 PCM3070IRHBT VQFN RHB 32 250 210.0 185.0 35.0 PCM3070IRHBTG4 VQFN RHB 32 250 210.0 185.0 35.0 Pack Materials-Page 2
www.ti.com GENERIC PACKAGE VIEW Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. VQFN - 1 mm max heightRHB 32 PLASTIC QUAD FLATPACK - NO LEAD5 x 5, 0.5 mm pitch 4224745/A
www.ti.com PACKAGE OUTLINE C 32X 0.3 0.2 3.45 0.1 32X 0.5 0.3
1 MAX
(0.2) TYP 0.05 0.00 28X 0.5 3.5 2X 3.5 A 5.1 4.9 B 5.1 4.9 (0.1) VQFN - 1 mm max heightRHB0032E PLASTIC QUAD FLATPACK - NO LEAD 4223442/B 08/2019 PIN 1 INDEX AREA 0.08 C SEATING PLANE 8 17 9 16 32 25 (OPTIONAL) PIN 1 ID
0.1 C A B
0.05 C EXPOSED THERMAL PAD
33 SYMM
NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 3.000 SEE SIDE WALL DETAIL 20.000 SIDE WALL DETAIL OPTIONAL METAL THICKNESS
www.ti.com EXAMPLE BOARD LAYOUT (1.475)
0.07 MIN
0.07 MAX
32X (0.25) 32X (0.6) ( 0.2) TYP VIA 28X (0.5) (4.8) (4.8) (1.475) ( 3.45) (R0.05) TYP VQFN - 1 mm max heightRHB0032E PLASTIC QUAD FLATPACK - NO LEAD 4223442/B 08/2019 SYMM 9 16 2532 SYMM LAND PATTERN EXAMPLE SCALE:18X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED METAL SOLDER MASK OPENINGSOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED)
www.ti.com EXAMPLE STENCIL DESIGN 32X (0.6) 32X (0.25) 28X (0.5) (4.8) (4.8) 4X ( 1.49) (0.845) (0.845)(R0.05) TYP VQFN - 1 mm max heightRHB0032E PLASTIC QUAD FLATPACK - NO LEAD 4223442/B 08/2019 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM METAL TYP SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 33: 75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:20X SYMM 9 16 2532
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