PCM3060

PCM3060 BURR-BROWN | Alldatasheet

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/C0066/C0117/C0114/C0114/C0262/C0066/C0114/C0111/C0119/C0110 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0102/C0114/C0111/C0109 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115

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24-BIT, 96/192-kHz ASYNCHRONOUS STEREO AUDIO CODEC Digital De-Emphasis: 32, 44.1, kHz for DAC 24-Bit Delta-Sigma ADC and DAC Power Down: ADC/DAC Independently ADC, DAC Asynchronous Operation Asynchronous/Synchronous Control for Stereo ADC: ADC/DAC Operation High Performance: (Typical, kHz) External Reset and Power-Down Pin: THD+N: dB ADC/DAC Simultaneously SNR: dB Audio Interface Mode: Dynamic Range: dB ADC/DAC Independent Master/Slave Sampling Rate: kHz Audio Data Format: System Clock: 256, 384, 512, 768 f S ADC/DAC Independent Full Scale Input: Vp-p I Left-Justified, Right-Justified Antialiasing Filter Included Dual Power Supplies: Decimation Filter: 5-V for Analog and 3.3-V for Digital Pass-Band Ripple: 0.05 dB Package: TSSOP-28 Stop-Band Attenuation: dB On-Chip High-Pass Filter: 0.91 Hz at f S kHz DVD-RW Stereo DAC: Digital TV High Performance: (Typical, Differential, Digital Set-Top Box kHz) Audio-Visual THD+N: dB SNR: 105 dB Dynamic Range: 104 dB The PCM3060 is a low-cost, high-performance, Sampling Rate: 192 kHz single-chip, 24-bit stereo audio codec with single-ended analog inputs and differential analog System Clock: 128, 192, 256, 384, outputs. 512, 768 f S The stereo 24-bit ADC employs a 64-times Differential Voltage Output: Vp-p delta-sigma modulator. It supports kHz Single-Ended Voltage Output: Vp-p sampling rates and a 16/24-bit digital audio output Analog Low-Pass Filter Included word on the audio interface. Oversampling Digital Filter: The stereo 24-bit DAC employs a 64- or 128-times Pass-Band Ripple: 0.04 dB delta-sigma modulator. It supports 192 kHz sampling rates and a 16/24-bit digital audio input Stop-Band Attenuation: dB word on the audio interface. Zero Flags The PCM3060 supports fully independent operation Flexible Mode Control of the sampling rate and audio interface for the ADC 3-Wire SPI, 2-Wire I C Compatible Serial and DAC. Control Interface Each audio interface supports I left-justified, and Hardware Control Mode right-justified formats with 16/24-bit words. Multiple Functions via SPI or I C Interface: Digital Attenuation and Soft Mute for ADC and DAC Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. PRODUCTION DATA information is current as of publication date. Copyright 2007, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com (CONTINUED) ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS PCM3060 SLAS533 MARCH 2007 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. The PCM3060 can be software-controlled through a 3-wire SPI-compatible or 2-wire I C-compatible serial interface, which provides access to all functions including digital attenuation, soft mute, de-emphasis etc. The PCM3060 can be also used in hardware mode, which provides three basic functions. The PCM3060 is fabricated using a highly advanced CMOS process and is available in a small 28-pin TSSOP package. The PCM3060 is suitable for various sound processing DVD-RW, digital TV, STB, and other AV equipment. over operating free-air temperature range (unless otherwise noted) (1) VALUE UNIT V CC 0.3 to 6.5 Supply voltage V V DD 0.3 to Ground voltage differences AGND1, AGND2, DGND, SGND 0.1 V RST MS MC, MD, SCKI1, SCKI2, DIN 0.3 to 6.5 V Digital input voltage BCK1, BCK2, LRCK1, LRCK2, DOUT 0.3 to DD 0.3 V ZEROL, ZEROR, MODE 0.3 to DD 0.3 V Analog input voltage V IN V IN V COM V OUT L+, V OUT L V OUT R+, V OUT R 0.3 to CC 0.3 6.5 V Input current (any pins except supplies) mA T A Ambient temperature under bias to 125 C T stg Storage temperature to 150 C T J Junction temperature 150 C Lead temperature (soldering) 260, s C Package temperature (IR reflow, peak) 260 C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT V CC Analog supply voltage 4.5 5.5 V V DD Digital supply voltage 2.7 3.3 3.6 V Digital input interface level TTL compatible Sampling frequency, LRCK1, LRCK2 kHz Digital input clock frequency System clock frequency, SCKI1, SCKI2 2.048 36.864 MHz Analog input level Vpp AC-coupled k Ω Analog output load resistance DC-coupled k Ω Analog output load capacitance pF Digital output load capacitance pF Operating free-air temperature C Submit Documentation Feedback

www.ti.com ELECTRICAL CHARACTERISTICS PCM3060 SLAS533 MARCH 2007 All specifications at T A V CC V DD 3.3 f S kHz, SCKI1 SCKI2 512 f S 24-bit data (unless otherwise noted). PCM3060PW PARAMETER TEST CONDITIONS UNIT MIN TYP MAX DIGITAL INPUT/OUTPUT DATA FORMAT Audio data interface format I LJ, RJ Audio data word length 16, Bits Audio data format MSB-first, 2s-complement Sampling frequency, ADC f S kHz Sampling frequency, DAC 192 System clock frequency 128, 192, 256, 384, 512, 768 f S 2.048 36.864 MHz INPUT LOGIC V IH (1) V DD V IL (1) 0.8 Input logic level VDC V IH (2) (3) 5.5 V IL (2) (3) 0.8 I IH (2) V IN V DD I IL (2) V IN V Input logic current µ A I IH (1) (3) V IN V DD 100 I IL (1) (3) V IN V OUTPUT LOGIC V OH (4) I OUT mA 2.8 Output logic level VDC V OL (4) (5) I OUT mA 0.5 REFERENCE OUTPUT V COM output voltage 0.5 V CC V V COM output impedance 12.5 k Ω Allowable V COM output µ A source/sink current ADC CHARACTERISTICS Resolution Bits ANALOG INPUT Full scale input voltage V IN V IN R dB 0.6 V CC Vp-p Center voltage 0.5 V CC V Input impedance k Ω Antialiasing filter response dB 300 kHz DC ACCURACY Gain mismatch, Full-scale input, V IN V IN R of FSR channel-to-channel Gain error Full-scale input, V IN V IN R of FSR Bipolar zero error HPF bypass, V IN V IN R 0.5 of FSR (1) BCK1, BCK2, LRCK1, LRCK2 (in slave mode, Schmitt-trigger input with 50-k Ω typical internal pulldown resistor) (2) SCKI1, SCKI2, DIN, MS /ADR/IFMD, MC/SCL/FMT, MD/SDA/IFMD (Schmitt-trigger input, 5-V tolerant). (3) RST (Schmitt-trigger input with 50-k Ω typical internal pulldown resistor, 5-V tolerant). (4) BCK1, BCK2, LRCK1, LRCK2 (in master mode), DOUT, ZEROL, ZEROR (5) MD/SDA/IFMD (in I C mode, open drain LOW output) Submit Documentation Feedback

www.ti.com PCM3060 SLAS533 MARCH 2007 ELECTRICAL CHARACTERISTICS (continued) All specifications at T A V CC V DD 3.3 f S kHz, SCKI1 SCKI2 512 f S 24-bit data (unless otherwise noted). PCM3060PW PARAMETER TEST CONDITIONS UNIT MIN TYP MAX DYNAMIC PERFORMANCE (6) (7) V IN dB, f S kHz THD+N Total harmonic distortion noise dB V IN dB, f S kHz f S kHz, A-weighted Dynamic range dB f S kHz, A-weighted 101 f S kHz, A-weighted SNR Signal-to-noise ratio dB f S kHz, A-weighted 101 f S kHz Channel separation dB (between L-ch and R-ch) f S kHz f S kHz, f S 44.1 kHz Crosstalk from DAC dB f S kHz, f S 44.1 kHz DIGITAL FILTER PERFORMANCE 0.454 Pass band Hz f S 0.583 Stop band Hz f S Pass-band ripple 0.454 f S 0.05 dB Stop-band attenuation 0.583 f S dB Group delay time 17.4/f S s 0.019 f S HPF frequency response dB Hz /1000 DAC CHARACTERISTICS Resolution Bits ANALOG OUTPUT Single-ended 0.8 V CC Output voltage Vp-p Differential 1.6 V CC Single-ended 0.5 V CC Center voltage V Differential 0.48 V CC AC-coupled Load impedance k Ω DC-coupled f kHz 0.02 dB LPF frequency response f kHz 0.07 dB 300 kHz DC ACCURACY Gain mismatch, of FSR channel-to-channel Gain error of FSR Single-ended Bipolar zero error of FSR Differential OUT V OUT X (6) f IN kHz, using System Two audio measurement system by Audio Precision, RMS mode with 20-kHz LPF and 400-Hz HPF. (7) f S kHz: SCKI1 SCKI2 256 f S f S 192 kHz: SCKI1 512 f S at f S kHz and SCKI2 128 f S at f S 192 kHz. Submit Documentation Feedback

www.ti.com PCM3060 SLAS533 MARCH 2007 ELECTRICAL CHARACTERISTICS (continued) All specifications at T A V CC V DD 3.3 f S kHz, SCKI1 SCKI2 512 f S 24-bit data (unless otherwise noted). PCM3060PW PARAMETER TEST CONDITIONS UNIT MIN TYP MAX DYNAMIC PERFORMANCE (SINGLE-ENDED) (8) (9) (10) V OUT dB, f S kHz THD+N Total harmonic distortion noise V OUT dB, f S kHz dB V OUT dB, f S 192 kHz f S kHz, EIAJ, A-weighted 103 Dynamic range f S kHz, EIAJ, A-weighted 103 dB fS 192 kHz, EIAJ, A-weighted 103 f S kHz, EIAJ, A-weighted 100 104 SNR Signal-to-noise ratio f S kHz, EIAJ, A-weighted 104 dB f S 192 kHz, EIAJ, A-weighted 104 f S kHz 101 Channel separation f S kHz 101 dB f S 192 kHz 101 f S kHz, f S 44.1 kHz 101 Crosstalk from ADC f S kHz, f S 88.2 kHz 101 dB f S kHz, f S 176.4 kHz 101 DYNAMIC PERFORMANCE (DIFFERENTIAL) (8) (9) (11) V OUT dB, f S kHz THD+N Total harmonic distortion noise V OUT dB, f S kHz dB V OUT dB, f S 192 kHz f S kHz, EIAJ, A-weighted 104 Dynamic range f S kHz, EIAJ, A-weighted 104 dB f S 192 kHz, EIAJ, A-weighted 104 f S kHz, EIAJ, A-weighted 105 SNR Signal-to-noise ratio f S kHz, EIAJ, A-weighted 105 dB f S 192 kHz, EIAJ, A-weighted 105 f S kHz 103 Channel separation f S kHz 103 dB f S 192 kHz 103 f S kHz, f S 44.1 kHz 103 Crosstalk from ADC f S kHz, f S 88.2 kHz 103 dB f S kHz, f S 176.4 kHz 103 DIGITAL FILTER PERFORMANCE SHARP ROLLOFF 0.454 Pass band Hz f S 0.546 Stop band Hz f S Pass-band ripple 0.454 f S 0.04 dB Stop-band attenuation 0.546 f S dB (8) f S kHz: SCKI1 SCKI2 256 f S f S 192 kHz: SCKI1 512 f S at f S kHz and SCKI2 128 f S at f S 192 kHz. (9) f OUT kHz, using System Two audio measurement system by Audio Precision, RMS mode with 20-kHz LPF and 400-Hz HPF. (10) Assumed 5-k Ω AC-coupled second-order LPF and 115-dB or higher- performance buffer. (11) Assumed 10-k Ω DC-coupled second-order LPF and 115- dB or higher-performance differential to single-ended converter. Submit Documentation Feedback

www.ti.com PCM3060 SLAS533 MARCH 2007 ELECTRICAL CHARACTERISTICS (continued) All specifications at T A V CC V DD 3.3 f S kHz, SCKI1 SCKI2 512 f S 24-bit data (unless otherwise noted). PCM3060PW PARAMETER TEST CONDITIONS UNIT MIN TYP MAX DIGITAL FILTER PERFORMANCE SLOW ROLLOFF 0.308 Pass band Hz f S Stop band 0.73 f S Hz Pass-band ripple 0.308 f S 0.5 dB Stop-band attenuation 0.73 f S dB DIGITAL FILTER PERFORMANCE Group delay time 20/f S s De-emphasis error 0.1 dB POWER SUPPLY REQUIREMENTS V CC 4.5 5.5 Voltage range VDC V DD 2.7 3.3 3.6 f S kHz/ADC, f S kHz/DAC mA f S kHz/ADC, f S kHz/DAC mA f S kHz/ADC, f S 192 kHz/DAC mA I CC f S kHz/ADC, power down/DAC mA Power down/ADC, f S kHz/DAC mA Full power down (12) (13) 780 µ A Supply current f S kHz/ADC, f S kHz/DAC mA f S kHz/ADC, f S kHz/DAC mA f S kHz/ADC, f S 192 kHz/DAC mA I DD f S kHz/ADC, power down/DAC mA Power down/ADC, f S kHz/DAC mA Full power down (12) 150 µ A f S kHz/ADC, f S kHz/DAC 160 190 f S kHz/ADC, f S kHz/DAC 180 f S kHz/ADC, f S 192 kHz/DAC 170 Power dissipation mW f S kHz/ADC, power down/DAC Power down/ADC, f S kHz/DAC Full power down (12) (13) 4.4 TEMPERATURE RANGE Operation temperature C θ JA Thermal resistance 105 C/W (12) Halt SCKI1, SCKI2, BCK1, BCK2, LRCK1, LRCK2 (13) AC-coupled configuration. If DC-coupled configuration is used, DC current flow to external load is added and it depends on external load resistance. Submit Documentation Feedback

www.ti.com PIN ASSIGNMENTS 1 1 MC/SCL/FMT MD/SDA/DEMP DOUT LRCK1 BCK1 SCKI1 VDD LRCK2 DGND DIN SCKI2 ZEROR BCK2 ZEROL MODE MS/ADR/IFMD V RIN V LIN VCC AGND1 AGND2 V R+ OUT VCOM V R–OUT V L+OUT SGND V L–OUT RST PCM3060 PW□(TSSOP)□PACKAGE (TOP VIEW) P0043-03 PCM3060 SLAS533 MARCH 2007 Submit Documentation Feedback

www.ti.com PCM3060 SLAS533 MARCH 2007 Table TERMINAL FUNCTIONS TERMINAL I/O (1) Audio data bit clock input/output for ADC BCK2 I/O (1) Audio data bit clock input/output for DAC DGND Digital ground DIN I (2) Audio data digital input for DAC DOUT O Audio data digital output for ADC LRCK1 I/O (1) Audio data left/right clock input/output for ADC LRCK2 I/O (1) Audio data left/right clock input/output for DAC MC/SCL/FMT I (2) Mode control, clock for SPI, clock for I format for H/W mode (5) MD/SDA/DEMP I/O (3) Mode control, data for SPI, data for I de-emphasis for H/W mode This pin provides four operation modes according to its input connection. Connected directly to V DD SPI mode. Connected to VDD through 220-k Ω pullup resistor: H/W mode, single-ended MODE I (4) V OUT Connected to DGND through 220-k Ω pulldown resistor: H/W mode, differential V OUT Connected directly to DGND I C mode. MS /ADR/IFMD I (2) Mode control, select for SPI with low active, address for I I/F mode for H/W mode RST I (5) Reset and power-down control input, active-low SCKI1 I (2) System clock input for ADC SCKI2 I (2) System clock input for DAC SGND Shield analog ground V CC ADC, DAC analog power supply, 5-V V COM ADC, DAC voltage common decoupling V DD Digital power supply, 3.3-V V IN L I Analog input to ADC, L-channel V IN R I Analog input to ADC, R-channel V OUT L O Analog output from DAC, L-channel in differential mode, must be open in single-ended mode V OUT O Analog output from DAC, L-channel in differential mode, L-channel in single-ended mode ZEROL O Zero flag, L-channel ZEROR O Zero flag, R-channel V OUT R O Analog output from DAC, R-channel in differential mode, must be open in single-ended mode V OUT O Analog output from DAC, R-channel in differential mode, R-channel in single-ended mode (1) Schmitt-trigger input/output with 50-k Ω typical internal pulldown resistor (2) Schmitt-trigger input, 5-V tolerant (3) Schmitt-trigger input, V tolerant for SPI, H/W mode and Schmitt-trigger input/open drain LOW output, 5-V tolerant for I C (4) V DD biased, quad-state input (5) Schmitt-trigger input with 50-k Ω typical internal pulldown resistor, 5-V tolerant Submit Documentation Feedback

www.ti.com VOUTL– VOUTR+ VOUTL+ VOUTR– VINR VINL VCOM VCC ZEROR SCK2 LRCK2 BCK1 BCK2 SGND AGND2 V DD DGND LRCK1 DOUT DIN SCK1 AGND1 MD/SDA/DEMP MS/ADR/IFMD RST MC/SCL/FMT MODE ZEROL Voltage Common and Reference Interpolation Filter with Digital Function Multi-Level Delta-Sigma Modulator Multi-Level Delta-Sigma Modulator Delta-Sigma Modulator Delta-Sigma Modulator LPF and Buffer LPF and Buffer SE to Diff. Converter SE to Diff. Converter Common and Reference Decimation Filter with HPF Audio Interface and Clock Control Mode Control B0229-01 PCM3060 SLAS533 MARCH 2007 BLOCK DIAGRAM Submit Documentation Feedback

www.ti.com TYPICAL PERFORMANCE CURVES OF ADC INTERNAL FILTER DIGITAL FILTER Normalized Frequency [×fS] −160 −140 −120 −100 −80 −60 −40 −20 0 8 16 24 32 Amplitude − dB G001 Normalized Frequency [×fS] −0.5 −0.4 −0.3 −0.2 −0.1 0.0 0.1 Amplitude − dB G002 ANALOG FILTER −50 −45 −40 −35 −30 −25 −20 −15 −10 f − Frequency − kHz Amplitude − dB 1 10 100 10k 1k G004 Normalized Frequency [×fS/1000] −50 −45 −40 −35 −30 −25 −20 −15 −10 Amplitude − dB G003 PCM3060 SLAS533 MARCH 2007 All specifications at T A V CC V DD 3.3 f S kHz, SCKI1 SCKI2 512 f S 24-bit data, unless otherwise noted. DECIMATION FILTER, STOP-BAND CHARACTERISTICS DECIMATION FILTER, PASS-BAND CHARACTERISTICS Figure Figure HIGH-PASS FILTER CHARACTERISTICS ANTIALIASING FILTER CHARACTERISTICS Figure Figure Submit Documentation Feedback

www.ti.com TYPICAL PERFORMANCE CURVES OF DAC INTERNAL FILTER DIGITAL FILTER −160 −140 −120 −100 −80 −60 −40 −20 0 1 2 3 4 Amplitude − dB Normalized Frequency [×fS] G005 −0.5 −0.4 −0.3 −0.2 −0.1 0.0 0.1 Amplitude − dB Normalized Frequency [×fS] G006 ANALOG FILTER −10 0 2 4 6 8 10 12 14 16 18 20 Amplitude − dB f − Frequency − kHz G007 −50 −40 −30 −20 −10 f − Frequency − kHz Amplitude − dB 1 10 100 10k 1k G008 PCM3060 SLAS533 MARCH 2007 All specifications at T A V CC V DD 3.3 f S kHz, SCKI1 SCKI2 512 f S 24-bit data, unless otherwise noted. INTERPOLATION FILTER, STOP BAND INTERPOLATION FILTER, PASS BAND (SHARP-ROLL OFF) (SHARP-ROLL OFF) Figure Figure DE-EMPHASIS FILTER CHARACTERISTICS S 44.1 kHz) LOW-PASS FILTER CHARACTERISTICS Figure Figure Submit Documentation Feedback

www.ti.com TYPICAL ADC PERFORMANCE CURVES −100 −98 −96 −94 −92 −90 −88 −25 0 25 50 75 100 THD+N − Total Harmonic Distortion + Noise − dB TA − Free-Air Temperature − °C G009 VIN = –0.5 dB 100 102 104 −25 0 25 50 75 100 Dynamic Range and SNR − dB TA − Free-Air Temperature − °C G010 SNR Dynamic Range −100 −98 −96 −94 −92 −90 −88 VCC − Supply Voltage − V G011 THD+N − Total Harmonic Distortion + Noise − dB VIN = –1 dB 100 102 104 Dynamic Range and SNR − dB VCC − Supply Voltage − V G012 SNR Dynamic Range PCM3060 SLAS533 MARCH 2007 All specifications at T A V CC V DD 3.3 f S kHz, SCKI1 SCKI2 512 f S 24-bit data, unless otherwise noted. THD+N at dB vs TEMPERATURE DYNAMIC RANGE and SNR vs TEMPERATURE Figure Figure 10. THD+N at dB vs SUPPLY VOLTAGE DYNAMIC RANGE and SNR vs SUPPLY VOLTAGE Figure 11. Figure 12. Submit Documentation Feedback

www.ti.com TYPICAL DAC PERFORMANCE CURVES −102 −100 −98 −96 −94 −92 −90 −25 0 25 50 75 100 TA − Free-Air Temperature − °C G013 THD+N − Total Harmonic Distortion + Noise − dB 100 102 104 106 108 110 −25 0 25 50 75 100 Dynamic Range and SNR − dB TA − Free-Air Temperature − °C G014 SNR Dynamic Range −102 −100 −98 −96 −94 −92 −90 VCC − Supply Voltage − V G015 THD+N − Total Harmonic Distortion + Noise − dB 100 102 104 106 108 110 Dynamic Range and SNR − dB VCC − Supply Voltage − V G016 SNR Dynamic Range PCM3060 SLAS533 MARCH 2007 All specifications at T A V CC V DD 3.3 f S kHz, SCKI1 SCKI2 512 f S 24-bit data, unless otherwise noted. THD+N vs TEMPERATURE DYNAMIC RANGE and SNR vs TEMPERATURE Figure 13. Figure 14. THD+N vs SUPPLY VOLTAGE DYNAMIC RANGE and SNR vs SUPPLY VOLTAGE Figure 15. Figure 16. Submit Documentation Feedback

www.ti.com TYPICAL PERFORMANCE CURVES ADCs OUTPUT SPECTRUM f − Frequency − kHz −140 −120 −100 −80 −60 −40 −20 0 5 10 15 20 Amplitude − dB G017 f − Frequency − kHz −140 −120 −100 −80 −60 −40 −20 0 5 10 15 20 Amplitude − dB G018 DAC OUTPUT SPECTRUM f − Frequency − kHz −140 −120 −100 −80 −60 −40 −20 0 5 10 15 20 Amplitude − dB G019 f − Frequency − kHz −140 −120 −100 −80 −60 −40 −20 0 5 10 15 20 Amplitude − dB G020 PCM3060 SLAS533 MARCH 2007 All specifications at T A V CC V DD 3.3 f S kHz, SCKI1 SCKI2 512 f S 24-bit data, unless otherwise noted. OUTPUT SPECTRUM dB, N=32768) OUTPUT SPECTRUM dB, N=32768) Figure 17. Figure 18. OUTPUT SPECTRUM dB, N=32768) OUTPUT SPECTRUM dB, N=32768) Figure 19. Figure 20. Submit Documentation Feedback

www.ti.com DEVICE tw(SCH) tw(SCL) 2 V 0.8 V H L T0005-14 t(SCY) System Clock (SCK1,□SCK2) PCM3060 SLAS533 MARCH 2007 The PCM3060 supports complete asynchronous operation between the ADC and DAC by receiving two independent system clocks on SCKI1 and SCKI2. Also, the PCM3060 supports synchronous operation between ADC and DAC by receiving one common system clock on either SCKI1 or SCKI2 and controlling the system clock configuration through register or in serial mode control. The PCM3060 requires two system clocks for operating the ADC and DAC blocks independently, or it requires one common clock for synchronous ADC and DAC operation. The system clock for the ADC of the PCM3060 must be 256, 384, 512, or 768 f S where f S is the audio sampling rate for the ADC, to kHz. The system clock for the DAC of the PCM3060 must be 128, 192, 256, 384, 512, or 768 f S where f S is the audio sampling rate for the DAC, to 192 kHz. Table lists the typical system clock frequencies, f SCKI1 and f SCKI2 for common audio sampling rates, and Figure shows the timing requirements for the system clock inputs. Table System Clock Frequencies for Common Audio Sampling Clock Frequencies SAMPLING SYSTEM CLOCK FREQUENCY, f SCKI1 f SCKI2 [MHz] FREQUENCY 128 f S (1) 192 f S (1) 256 f S 384 f S 512 f S 768 f S (kHz) 2.048 3.072 4.096 6.144 8.192 12.288 4.096 6.144 8.192 12.288 16.384 24.576 44.1 5.6488 8.4672 11.2896 16.9344 22.5792 33.8688 6.144 9.216 12.288 18.432 24.576 36.864 88.2 11.2896 16.9344 22.5792 33.8688 See (2) See (2) 12.288 18.432 24.576 36.864 See (2) See (2) 176.4 (1) 22.5792 33.8688 See (2) See (2) See (2) See (2) 192 (1) 24.576 36.864 See (2) See (2) See (2) See (2) (1) This combination of sampling clock frequency and system clock frequency is supported only for the DAC. (2) This system clock frequency is not supported for the given sampling clock frequency. SYMBOL PARAMETERS MIN MAX UNIT t (SCY) System clock cycle time ns t w(SCH) System clock high time 0.4 t (SCY) ns t w(SCL) System clock low time 0.4 t (SCY) ns System clock duty cycle 40% 60% Figure 21. System Clock Input Timing Submit Documentation Feedback

www.ti.com POWER-ON RESET AND EXTERNAL RESET SEQUENCE PCM3060 SLAS533 MARCH 2007 The PCM3060 has both an internal power-on reset circuit and an external reset circuit. The sequences for both resets are shown in the following. Figure illustrates the timing of the internal power-on reset. Initialization (reset) is done automatically at the time when V DD exceeds 2.2 V typical. Internal reset is released 1024 SCKIx after power on if the H/W control mode is selected and RST is kept HIGH; then the PCM3060 begins normal operation. If the S/W control mode is selected and RST is kept HIGH, internal reset is released 1024 SCKIx after the reset of ADPSV and DAPSV through serial control port; then the PCM3060 begins normal operation. If RST is kept LOW, internal reset is held and the reset sequence is frozen until RST is changed from LOW to HIGH. V OUT L and V OUT R from the DAC are forced to the V COM 0.5 V CC level as V CC rises. If synchronization is maintained among SCKIx, BCKx, and LRCKx, V OUT L and V OUT R go into the fade-in sequence after t DACDLY1 2048/f S from internal reset release. Then V OUT L and V OUT R provide outputs corresponding to DIN after t DACDLY2 1616/f S from the start of fade-in. Similarly, DOUT from the ADC is enabled and goes into the fade-in sequence after t ADCDLY1 2048/f S from internal reset release, and then DOUT provides an output corresponding to V IN L and V IN R after t ADCDLY2 1936/f S from the start of fade-in. If synchronization is not held, the internal reset is not released and operation mode is kept on reset and power-down state. After resynchronization, the DAC begins its fade-in sequence, and the ADC also begins fade-in operation after internal initialization and an initial delay. Figure is the timing chart of the external reset. The RST pin initiates external forced reset when RST is held LOW for at least t RST 2048/f S it resets the device places it in the power-down state, which is the lowest-power dissipation state in the PCM3060. When RST transitions from HIGH to LOW while SCKIx, BCKx, and LRCKx are synchronized, V OUT L and V OUT R are forced to the V COM 0.5V CC level after the fade-out sequence lasting t DACDLY2 1616/f S and DOUT is forced to ZERO after t ADCDLY2 1936/f S fade-out sequence. After that, the internal reset becomes LOW, the PCM3060 resets and enters into the power-down state, finally all registers and memory except mode control registers are reset. To resume into normal operation, changing RST to HIGH again is required, and the sequence shown in Figure is performed. It is possible to halt SCKIx, BCKx and LRCKx during the power-down state, but all clocks must be resumed prior to starting the power-up sequence. The same fade-in/-out sequence of V OUT L/R and DOUT can be obtained by setting the ADPSV and DAPSV bits through serial mode control port. Submit Documentation Feedback

www.ti.com POWER-ON RESET AND EXTERNAL RESET SEQUENCE (Continued)

1024 SCKIx

VDD 0 V (V = 2.2 V typ.)DD Synchronous Clocks RST Normal OperationPower Down

0.5 VCC

(1) SCKIx, BCKx, LRCKx ADPSV DAPSV Internal Reset V L+/– V R+/– OUT OUT (V =DD VDD 3.3□V typ.) ( = 2.7□V min) t 2048/f (DACDLY1) S t 2048/f (ADCDLY1) S t 1616/f (DACDLY2) S t 1936/f (ADCDLY2) S VCOM CC(0.5 V ) T0097-02 PCM3060 SLAS533 MARCH 2007 NOTE: Release from the power-save mode is required if the software control mode is selected. Figure 22. DAC Output and ADC Output for Power-On Reset Submit Documentation Feedback

www.ti.com VDD 0 V RST Normal OperationNormal Operation Power Down (1) SCKIx, BCKx, LRCKx ADPSV DAPSV Internal Reset V L+/– V R+/– OUT OUT (V =DD 3.3□V typ.) t 1936/f (ADCDLY2) S t 1936/f (ADCDLY2) S T0098-02 t 2048/f (DACDLY1) S t 1616/f (DACDLY2) S t 1616/f (DACDLY2) S VCOM CC(0.5 V ) 2048/fS min. t 2048/f min. RST S Synchronous Clocks Synchronous Clocks t 2048/f (ADCDLY1) S PCM3060 SLAS533 MARCH 2007 (1) ADPSV and DAPSV control V OUT L/R and DOUT, respectively, with fade-in/out the same as for RST Figure 23. DAC Output and ADC Output for External Reset Submit Documentation Feedback

www.ti.com PCM AUDIO INTERFACE Audio Interface Mode and Timing DOUT 0.5 VDD 1.4 V 1.4 V DIN 1.4 V BCK1 /2 (Input ) LRCK1/2 (Input ) t(BCY) t(DIH) t(BCH) t(BCL) t(LRS) t(DIS) t(DOD) T0247-01 t(LRH) PCM3060 SLAS533 MARCH 2007 The digital audio data can be interfaced in either slave or master mode, and this interface mode is selectable using the serial mode control described in the Mode Control section. The interface mode is also selectable independently for the ADC and the DAC. DIN is always input to the PCM3060 and DOUT is always an output from the PCM3060. Slave mode is the default mode for both the ADC and the DAC. In slave mode, BCK1/2 and LRCK1/2 are inputs to the PCM3060, and BCK1/2 must be either f S or f S DIN is sampled on the rising edge of BCK2, and DOUT is changed on the falling edge of BCK1. The default timing specification is shown in Figure In master mode, BCK1/2 and LRCK1/2 are outputs from the PCM3060. BCK1/2 and LRCK1/2 are generated by the PCM3060 from SCKI1/2, and BCK1/2 is fixed at f S DIN is sampled on the rising edge of BCK2, and DOUT is changed on the falling edge of BCK1. The detailed timing specification is shown in Figure SYMBOL t (BCY) BCK1/2 cycle time ns t w (BCH) BCK1/2 high time ns t w (BCL) BCK1/2 low time ns t (LRS) LRCK1/2 set-up time to BCK1/2 rising edge ns t (LRH) LRCK1/2 hold time to BCK1/2 rising edge ns t (DIS) DIN setup time to BCK1/2 rising edge ns t (DIH) DIN hold time to BCK1/2 rising edge ns t (DOD) DOUT delay time from BCK1/2 falling edge ns NOTE: Load capacitance of output is pF. Figure 24. Audio Data Interface Timing (Slave Mode: BCK1/2 and LRCK1/2 Work as Inputs) Submit Documentation Feedback

www.ti.com DOUT 0.5 VDD

0.5 VDD

DIN 1.4 V 1.4 V BCK1 /2 (Output ) SCKI1 /2 (Input ) LRCK1/2 (Output ) t(BCY) t(DIH) t(BCH) t(BCL) t(LRD) t(DIS) t(DOD) t(BCD) t(BCD) T0248-01 Audio Interface Format PCM3060 SLAS533 MARCH 2007 SYMBOL PARAMETERS MIN TYP MAX UNIT t (BCY) BCK1/2 cycle time f S t w(BCH) BCK1/2 high time 0.4 t (BCY) 0.5 t (BCY) 0.6 t (BCY) t w(BCL) BCK1/2 low time 0.4 t (BCY) 0.5 t (BCY) 0.6 t (BCY) t (LRD) LRCK1/2 delay time from BCK1/2 falling edge ns t (DIS) DIN setup time to BCK1/2 rising edge ns t (DIH) DIN hold time to BCK1/2 rising edge ns t (DOD) DOUT delay time from BCK1/2 falling edge ns t (BCD) BCK1/2 delay time from SCKI1/2 rising edge (1) ns NOTE: Load capacitance of output is pF. (1) This specification applies for SCKI1/2 when the frequency is less than MHz. Figure 25. Audio Data Interface Timing (Master Mode: BCK1/2 and LRCK1/2 work as Outputs) The PCM3060 supports the following four interface formats in both slave and master modes, and they are selectable independently for the ADC and DAC using serial mode control. 24-bit I S format 24-bit left-justified format 24-bit right-justified format 16-bit right-justified format All formats are provided in MSB-first, complement data format. Submit Documentation Feedback

www.ti.com 24-Bit,□MSB-First,□I S 24-Bit,□MSB-First,□Left-Justified FMT1/2[1:0]□=□00 FMT1/2[1:0]□=□01 LRCK1/2 Right-ChannelLeft-Channel BCK1/2 DIN MSB LSB 22 23 24321 MSB LSB 22 23 24321 DOUT MSB LSB 22 23 24321 MSB LSB 22 23 24321 LRCK1/2 Right-ChannelLeft-Channel BCK1/2 DIN MSB MSBLSB LSB 22 2223 2324 243 32 21 1 1 DOUT MSB MSBLSB LSB 22 2223 2324 243 32 21 1 1 24-Bit,□MSB-First,□Right-Justified FMT1/2[1:0]□=□10 LRCK1/2 Right-ChannelLeft-Channel BCK1/2 DIN DOUT MSB LSB 22 23 2424 321 MSB LSB 22 23 2424 321 MSB LSB 22 23 24321 MSB LSB 22 23 24321 16-Bit,□MSB-First,□Right-Justified FMT1/2[1:0]□=□11 LRCK1/2 Right-ChannelLeft-Channel BCK1/2 DIN DOUT LSB 14 15 16 LSB 14 15 16 MSB 321 MSB 321 LSB 14 15 16 LSB 14 15 16 MSB 321 MSB 321 T0016-18 PCM3060 SLAS533 MARCH 2007 Figure 26. Audio Data Input/Output Format Submit Documentation Feedback

www.ti.com SYNCHRONIZATION WITH DIGITAL AUDIO SYSTEM Within□2/fS t(DACDLY3) (22/f )S Normal VCOM (0.5□V )CCUndefined DataNormal SynchronousAsynchronousSynchronous DAC□V X+/–OUT State□of□Synchronization NormalZeroNormalADC□DOUT Undefined Data T0020-08 t(ADCDLY3) (32/f )S PCM3060 SLAS533 MARCH 2007 As the PCM3060 operates under the system clock (SCKI1/2) and the audio sampling clock (LRCK1/2), SCKI1/2 and LRCK1/2 must have a specific relationship in slave mode. The PCM3060 does not need a specific phase relationship between audio the interface clocks (LRCK1/2, BCK1/2) and system clock (SCKI1/2), but does require a frequency synchronization of LRCK1/2, BCK1/2, and SCKI1/2. If the relationship between SCKI2 and LRCK2 changes more than BCK2s (BCK2 f S or BCK2s (BCK2 f S due to jitter or frequency change, etc., internal operation of DAC halts within 2/f S and analog output is forced to V COM (0.5V CC until resynchronization of SCKI2 to LRCK2 and BCK2 is completed and then t DACDLY3 passes by. If the relationship between SCKI1 and LRCK1 changes more than BCK1s (BCK1 f S or BCK1s (BCK1 f S due to jitter, frequency change, etc., internal operation of ADC halts within 2/f S and digital output is forced into ZERO code until resynchronization of SCKI1 to LRCK1 and BCK1 is completed and then t ADCDLY3 passes by. In case of changes less than BCK1/2s (BCK1/2 64) or BCK1/2s (BCK1/2 48), resynchronization does not occur, and previously described analog/digital output control and discontinuity do not occur. Figure illustrates the DAC analog output and ADC digital output for loss of synchronization. During undefined data, it may generate some noise in audio signal. Also, the transition of normal to undefined data and undefined or zero data to normal creates a discontinuity in the data on the analog and digital outputs, which may generate some noise in the audio signal. The ADC output, DOUT and DAC outputs, and V OUT X hold the previous state if the system clock halts. Figure 27. DAC Output and ADC Output for Loss of Synchronization Submit Documentation Feedback

www.ti.com ANALOG INPUTS TO ADC ANALOG OUTPUTS FROM DAC V COM OUTPUT OVERSAMPLING RATE CONTROL ZERO FLAGS Zero-Detect Condition Zero-Flag Outputs PCM3060 SLAS533 MARCH 2007 The PCM3060 has two independent input channels, V IN L and V IN These are single-ended (unbalanced) inputs, each capable of 0.6-V CC Vpp input with 10-k Ω input resistance, typically. The PCM3060 has two independent output channels, V OUT L and V OUT These are differential, (balanced) outputs, each capable of driving 0.8-V CC Vpp (1.6-Vpp in differential) typical with a 10-k Ω dc-coupled load. The internal output amplifiers for V OUT L+, V OUT L and V OUT R+, V OUT R are biased to V COM described as follows. The output amplifiers include an RC continuous-time filter, which helps to reduce the out-of-band noise energy present at the DAC outputs due to the noise shaping characteristics of the PCM3060 delta-sigma modulators. The frequency response of this filter is shown in the typical performance curves. This filter is not enough to attenuate the out-of-band noise to an acceptable level for many general. An external low-pass filter is used if further out-of-band noise rejection in required. V OUT X+, V OUT X configuration can be changed to single-ended (unbalanced) output via a MODE pin setting or serial mode control, and V OUT is assigned as an output pin in single-ended mode. One unbuffered common voltage output pin, VCOM (pin 20) is brought out for decoupling purposes. This pin is internally biased to a dc voltage level of 0.5 V CC nominal, and is used as an internal common voltage and reference voltage for the ADC and DAC. This pin can be used to bias an external circuit, but the load impedance must be high enough for operation with the output resistance of this pin, which is 12.5 k Ω typically. The ove-sampling rate of ADC of PCM3060 is fixed at f S but the oversampling rate of DAC of PCM3060 is one of f S f S or f S and this is automatically selected by the ratio of system clock frequency and sampling frequency. And it can be also set to double rate, i.e., one of 128 f S f S or f S through serial control. For each DAC channel, the PCM3060 has a zero-detect circuit that recognizes zero detection when 1024 consecutive zeros have been sampled on DIN. There are two zero-flag outputs, ZEROL and ZEROR. These pins can be used to operate external mute circuits, or used as status indicators for a microcontroller, audio signal processor, etc. These pins can be programmed in following two modes using the serial control port as described in the MODE CONTROL section. (default) L-ch zero detection R-ch zero detection L-ch and R-ch zero detection L-ch and R-ch zero detection For zero detection, these pins are set to HIGH (1) by default, but the polarity of the zero-flag outputs can be inverted through the serial control port. ZREV (default) HIGH for zero detection LOW for zero detection Submit Documentation Feedback

www.ti.com MODE CONTROL PARALLEL HARDWARE CONTROL 3-WIRE (SPI) SERIAL CONTROL PCM3060 SLAS533 MARCH 2007 The PCM3060 supports the following three types of mode control interface and four types of operation configuration, according to the input state of MODE (pin 28) as follows. The pullup or pulldown resistor must be 220 k Ω 5%. MODE MODE CONTROL INTERFACE Tie to DGND 2-wire serial control, selectable V OUT X configuration Pulldown resistor to DGND 3-wire parallel control, differential V OUT X Pullup resistor to V DD 3-wire parallel control, single-ended V OUT X Tie to V DD 3-wire (SPI) serial control, selectable V OUT X configuration The input state of the MODE pin is sampled during power-on reset or external reset; therefore, an input change after reset is ignored until the next reset is performed. The definitions (assignments) of the following three pins are changed by this control mode setting. DEFINITION PIN SPI I C H/W MD SDA DEMP MC SCL FMT MS ADR IFMD In serial mode control, the actual mode control is performed by register write (and read) through an SPI- or I C-compatible serial control port. In parallel mode control, three specific functions are controlled directly through high/low settings of three specific pins. IFMD (Interface Mode) ADC, slave mode for DAC HIGH Master (256 f S mode for ADC, slave mode for DAC The audio interface of the ADC and DAC can be independent from each other, but mode selection is applied on both. FMT (Interface Format) I S for ADC and DAC HIGH 24-bit left-justified for ADC and DAC The audio interface of the ADC and DAC can be independent from each other, but format selection is applied on both. DEMP (De-emphasis) (1) (1) The 44.1-kHz de-emphasis filter is always selected. The PCM3060 supports SPI-compatible serial ports, which operate asynchronously to the audio serial interface. The control interface consists of MD, MC, and MS MD is the serial data input, used to program the mode control registers. MC is the serial bit clock, used to shift the data into the control port. MS is the select input, used to enable the mode control port. Submit Documentation Feedback

www.ti.com Register Write Operation MSB

0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 D7 D6 D5 D4 D3 D2 D1 D00 0

Register Index (or Address) Register Data R0001-01 IDX0 D7 D6 D4 D5 D3 D2 D1 D00 MS MC MD X 0 IDX6XIDX1IDX2IDX3IDX4IDX5IDX6X T0048-01 PCM3060 SLAS533 MARCH 2007 All single-write operations via the serial control port use 16-bit data words. Figure shows the control data word format. The most significant bit must be a There are seven bits, labeled IDX[6:0], that set the register index (address) for the write operation. The least significant eight bits, D[7:0], contain the data to be written to the register specified by IDX[6:0]. Figure shows the functional timing diagram for single-write operations on the serial control port. MS is held in the High state until a register is to be written. To start the register write cycle, MS is set to the Low state. Sixteen clocks are then provided on MC, corresponding to the bits of the control data word on MD. After the sixteenth clock cycle has completed, MS is set to High to latch the data into the indexed mode control register. The PCM3060 supports the multiple-write operation in addition to the single-write operation. Multiple write is performed by sending N-sets of 8-bit register data after the first bits of register address and register data, while keeping the MC clock and MS in the Low state. Closing the multiple-write operation is done by setting MS to the High state. Figure 28. Control Data Word Format for MD Figure 29. Register Write Operation Submit Documentation Feedback

www.ti.com Timing Requirements t(MCH) 1.4□V 1.4□V 1.4□V MS t(MSS) t(MCL) t(MHH) t(MSH) t(MCY) t(MDH) t(MDS) MC MD LSB T0013-10 TWO-WIRE SERIAL CONTROL Slave Address PCM3060 SLAS533 MARCH 2007 Figure shows a detailed timing diagram for the 3-wire serial control interface. These timing parameters are critical for proper control port operation. SYMBOL PARAMETER MIN MAX UNIT t (MCY) MC cycle time 100 ns t w(MCL) MC low-level time ns t w (MCH) MC high-level time ns t (MHH) MS high-level time t (MCY) ns t (MSS) MS falling edge to MC rising edge ns t (MSH) MS rising edge from MC rising edge for LSB (1) ns t (MDH) MD hold time ns t (MDS) MD setup time ns (1) MC rise edge for LSB to MS rise edge. Figure 30. Control Interface Timing for SPI The PCM3060 supports the I C-compatible serial bus and the data transmission protocol for standard-mode and fast-mode B max 100 pF) as a slave device. This protocol is explained in the well-known I C 2.0 specification. MSB LSB ADR W Submit Documentation Feedback

www.ti.com Packet Protocol SDA SCL St 1-7 8 1-8 9 1-8 9 9 Sp Slave Address ACK DATA ACK DATA ACK ACKR/W R/ :□□□Read□Operation□if□1;□Otherwise,□Write□OperationW ACK: Acknowledgement□of□a□Byte□if□0,□not Acknowledgement□of□a□Byte□if□1 Stop Condition Start Condition T0049-06 Write Operation Transmitter M M M S M MM M Data Type St Slave Address W ACK ACK ACK ACK ACK Write□Data□1 Write□Data□2Reg Address Sp R0002-04 S S S S PCM3060 SLAS533 MARCH 2007 The PCM3060 has bits for its own slave address. The first six bits (MSBs) of the slave address are factory preset to 0011. The next bit of the address byte is the device select bit, which can be user-defined by the ADR pin (pin 27). Two PCM3060s at maximum can be connected on the same bus at one time. Each PCM3060 responds when it receives its own slave address. A master device must control packet protocol, which consists of a start condition, slave address with read/write bit, data if write or acknowledgement if read, and stop condition. The PCM3060 supports the slave receiver function. The PCM3060 supports the receiver function. A master can write to any PCM3060 registers using single or multiple accesses. The master sends a PCM3060 slave address with a write bit, a register address, and the data. If multiple access is required, the address is that of the starting register, followed by the data to be transferred. When the data are received properly, the index register is incremented by automatically. When the index register reaches 4Ah, the next value is 40h. When undefined registers are accessed, the PCM3060 does not send an acknowledgement. Figure is a diagram of the write operation. The register address and the write data are 8-bit in MSB-first format. Figure 31. Framework for Write Operation Submit Documentation Feedback

www.ti.com Timing Diagram SDA SCL t(BUF) t(D-SU) t(D-HD) Start t(LOW) t(S-HD) t(SCL-F) t(SCL-R) t(HI) Repeated□Start t(S-SU) t(S-HD) t(SDA-F) t(SDA-R) t(P-SU) Stop t(GW) T0050-04 PCM3060 SLAS533 MARCH 2007 The detailed timing diagram for SCL and SDA is shown as follows. Timing Characteristics STANDARD MODE FAST MODE SYMBOL PARAMETER UNIT MIN MAX MIN MAX f (SCL) SCL clock frequency 100 400 kHz t (BUF) Bus free time between STOP and START conditions 4.7 1.3 µ s t (LOW) Low period of the SCL clock 4.7 1.3 µ s t (HI) High period of the SCL clock 0.6 µ s t (S-SU) Setup time for START/repeated START condition 4.7 0.6 µ s t (S-HD) Hold time for START/repeated START condition 0.6 µ s t (D-SU) Data setup time 250 100 ns t (D-HD) Data hold time 3450 900 ns t (SCL-R) Rise time of SCL signal 1000 0.1 C B 300 ns t (SCL-F) Fall time of SCL signal 1000 0.1 C B 300 ns t (SDA-R) Rise time of SDA signal 1000 0.1 C B 300 ns t (SDA-F) Fall time of SDA signal 1000 0.1 C B 300 ns t (P-SU) Setup time for STOP condition 0.6 µ s t (GW) Allowable glitch width N/A ns C B Capacitive load for SDA and SCL lines 400 100 pF Noise margin at high level for each connected device (including hysteresis) 0.2 V DD 0.2 V DD V Noise margin at low level for each connected device (including hysteresis) 0.1 V DD 0.1 V DD V Hysteresis of Schmitt-trigger input N/A 0.05 V DD V Figure 32. Control Interface Timing for I C Submit Documentation Feedback

www.ti.com MODE CONTROL REGISTERS PCM3060 SLAS533 MARCH 2007 The PCM3060 has many user-programmable functions which are accessed via control registers, and they are programmed through the SPI or I C serial control port. Table lists the available mode control functions along with reset default conditions and associated register addresses. The register map is shown in Table Table User-Programmable Mode Control Functions FUNCTION RESET DEFAULT REGISTER LABEL Mode control register reset (ADC and DAC) Normal operation MRST System reset (ADC and DAC) Normal operation SRST ADC power-save control (ADC) Power save ADPSV DAC power-save control (DAC) Power save DAPSV VOUT configuration control (DAC) Differential S/E Digital attenuation control, dB to 100 dB in 0.5-dB steps dB, no attenuation and AT21[7:0], AT22[7:0] (DAC) Clock select for DAC operation (DAC) CLK2 enable CSEL2 Master/slave mode for DAC audio interface (DAC) Slave S 2[2:0] Interface format for DAC audio interface (DAC) I S FMT2[1:0] Oversampling rate control (DAC) Low (x64/x32/x16) OVER Output phase select (DAC) Normal DREV2 Soft-mute control (DAC) Mute disabled MUT22, MUT21 Digital filter rolloff control (DAC) Sharp rolloff FLT De-emphasis sampling rate selection (DAC) 44.1 kHz DMF[1:0] De-emphasis function control (DAC) De-emphasis disabled DMC Zero-flag polarity control (DAC) High for detection ZREV Zero-flag form select (DAC) L-ch, R-ch independent AZRO Digital attenuation control, dB to 100 dB in 0.5-dB steps dB, no attenuation and AT11[7:0], AT12[7:0] (ADC) Clock select for ADC operation (ADC) CLK1 enable CSEL1 Master/slave mode for ADC audio interface (ADC) Slave S 1[2:0] Interface format for ADC audio interface (ADC) I S FMT1[1:0] Zero-cross detection disable for digital attenuation control (ADC) Zero-cross detection enabled ZCDD HPF bypass control (ADC) Bypass disabled BYP Input phase select (ADC) Normal DREV1 Soft-mute control (ADC) Mute disabled MUT12, MUT11 Table Register Map REGISTER ADDRESS DATA HEX DEC B15 B14 B13 B12 B11 B10 40h Register MRST SRST ADPSV DAPSV RSV (1) S/E RSV (1) RSV (1) 41h Register AT217 AT216 AT215 AT214 AT213 AT212 AT211 AT210 42h Register AT227 AT226 AT225 AT224 AT223 AT222 AT221 AT220 43h Register CSEL2 S S S FMT21 FMT20 RSV (1) RSV (1) 44h Register OVER DREV2 MUT22 MUT21 RSV (1) RSV (1) RSV (1) RSV (1) 45h Register FLT DMF1 DMF0 DMC ZREV AZRO RSV (1) RSV (1) 46h Register AT117 AT116 AT115 AT114 AT113 AT112 AT111 AT110 47h Register AT127 AT126 AT125 AT124 AT123 AT122 AT121 AT120 48h Register CSEL1 S S S FMT11 FMT10 RSV (1) RSV (1) 49h Register ZCDD BYP DREV1 MUT12 MUT11 RSV (1) RSV (1) RSV (1) (1) RSV means reserved for factory use or future extension, and these bits should be set to during regular operation. Do not write any values in addresses other than those listed. Submit Documentation Feedback

www.ti.com REGISTER DEFINITIONS PCM3060 SLAS533 MARCH 2007 B15 B14 B13 B12 B11 B10 Register MRST SRST ADPSV DAPSV RSV RSV RSV S/E MRST: Mode Control Register Reset (ADC and DAC) Default value: MRST Set default value MRST Normal operation (default) The MRST bit controls reset of the mode control registers to their default values. Pop noise may be generated. Returning the MRST bit to is not required, as the MRST bit is automatically set to after a mode control register reset. SRST: System Reset (ADC and DAC) Default value: SRST Resynchronization SRST Normal operation (default) The SRST bit controls system reset, the relation between system clock and sampling clock is re-synchronized, and ADC operation and DAC operation is restarted. The mode control register is not reset and the PCM3060 does not go into power down state, but pop-noise may be generated. Returning the SRST bit to is not required, as the SRST bit is automatically set to after triggering a system reset. ADPSV: ADC Power-Save Control (ADC) Default value: ADPSV Normal operation ADPSV Power-save mode (default) The ADPSV bit controls the ADC power-save mode. In power-save mode, DOUT is forced to ZERO with a fade-out sequence, the internal ADC data are reset, and the ADC goes into the power-down state. For power-save mode release, a fade-in sequence is applied on DOUT during the resume process. The serial mode control is enabled during this mode. A waiting time of more than 2048/f S is required for the proper status change by this power save control on/off. As the default state after power on is the power-save mode and DOUT is disabled (ZERO), release from the power-save mode is required for normal operation. The detailed sequence and timing for ADPSV control is shown Figure and Figure NOTE: It is recommended that changing/stopping clocks or changing the audio interface mode be performed in power-down mode in order to avoid unexpected pop/click noise and performance degradation. Submit Documentation Feedback

www.ti.com PCM3060 SLAS533 MARCH 2007 DAPSV: DAC Power-Save Control (DAC) Default value: DAPSV Normal operation DAPSV Power-save mode (default) The DAPSV bit controls DAC power-save mode. In power-save mode, DAC outputs are forced to Vcom with a fade-out sequence, the internal DAC data are reset and the DAC goes into the power-down state. For power-save mode release, a fade-in sequence is applied on the DAC outputs in resume process. The serial mode control is enabled during this mode. A waiting time of more than 2048/f S is required for the proper status change by this power-save control on/off. As the default state after power on is the power-save mode and the DAC outputs are disabled COM release from the power-save mode is required for normal operation. The detailed sequence and timing for DAPSV control is shown Figure and Figure NOTE: It is recommended that changing/stopping clocks or changing the audio interface mode be performed in power-down mode in order to avoid unexpected pop/click noise and performance degradation. S/E: DAC Output Configuration Control (DAC) Default value: S/E Differential (default) S/E Single-ended The S/E bit allows the user to select the configuration of the DAC output on the V OUT X pins according to application circuit. Submit Documentation Feedback

www.ti.com PCM3060 SLAS533 MARCH 2007 B15 B14 B13 B12 B11 B10 Register AT217 AT216 AT215 AT214 AT213 AT212 AT211 AT210 B15 B14 B13 B12 B11 B10 Register AT227 AT226 AT225 AT224 AT223 AT222 AT221 AT220 AT2x[7:0]: Digital Attenuation Level Setting (DAC) Where x or corresponding to the DAC output V OUT L and V OUT R 2). Default value: 1111 1111b AT2x[7:0] DECIMAL VALUE ATTENUATION LEVEL SETTING 1111 1111b 255 dB, no attenuation (default) 1111 1110b 254 0.5 dB 1111 1101b 253 dB 1000 0001b 129 dB 1000 0000b 128 63.5 dB 0111 1111b 127 dB 0011 1000b 99.5 dB 0011 0111b 100 dB 0011 0110b Mute 0000 0000b Mute Each DAC channel OUT L and V OUT has a digital attenuator function. The attenuation level may be set from dB to 100 dB in 0.5-dB steps, and also may be set to infinite attenuation (mute). The attenuation level change from current value to target value is performed by incrementing or decrementing one 0.5-dB step for every 8/f S time interval. While the attenuation level change sequence is in progress, new commands for attenuation level change are not processed, but the new command overwrites the previous command in the command buffer. The last command for attenuation level change is performed after the present attenuation level change sequence is finished. The attenuation level for each channel can be set individually using the following formula, and the foregoing table shows attenuation levels for various settings: Attenuation level (dB) 0.5 (AT2x[7:0] DEC 255), where AT2x[7:0] DEC through 255 for AT2x[7:0] DEC through 54, the level is set to infinite attenuation (mute). Submit Documentation Feedback

www.ti.com PCM3060 SLAS533 MARCH 2007 B15 B14 B13 B12 B11 B10 Register CSEL2 S S S RSV RSV FMT21 FMT20 CSEL2: Clock Select for DAC Operation Default value: (SCKI2, BCK2, LRCK2 enabled for DAC operation) CSEL2 SCKI2, BCK2, LRCK2 enabled for DAC operation (default) CSEL2 SCKI1, BCK1, LRCK1 enabled for DAC operation The CSEL2 bit controls system clock and audio interface clocks for the DAC operation. SCKI2, BCK2, LRCK2 are used for the DAC portion if CSEL2 (default), and SCKI1, BCK1, LRCK1 are used for DAC operation if CSEL2 S 2[2:0]: Audio Interface Mode for DAC Default value: 000 (slave mode) S 2[2:0] Audio Interface Mode for DAC Slave mode (default) Master mode, 768 f S Master mode, 512 f S Master mode, 384 f S Master mode, 256 f S Master mode, 192 f S Master mode, 128 f S Reserved The S 2[2:0] bits control the audio interface mode for the DAC. FMT2[1:0]: Audio Interface Format for DAC Default value: S Mode) FMT2[1:0] Audio Interface Format for DAC 24-bit I S format (default) 24-bit left-justified format 24-bit right-justified format 16-bit right-justified format The FMT2[1:0] bits control the audio interface format for the DAC. Submit Documentation Feedback

www.ti.com PCM3060 SLAS533 MARCH 2007 B15 B14 B13 B12 B11 B10 Register RSV OVER RSV RSV RSV DREV2 MUT22 MUT21 OVER: Oversampling Rate Control (DAC) Default value: OVER System clock 512 f S or 768 f S System clock 256 f S or 384 f S System clock 128 f S or 192 f S OVER Oversampling (default) Oversampling (default) Oversampling (default) OVER 128 Oversampling Oversampling Oversampling The OVER bit is used to control the oversampling rate of the delta-sigma D/A converters. Setting OVER might improve out-of-band noise characteristics in some application environments, but it might also slightly affect baseband performance. Writing over this bit during normal operation may generate pop noise. DREV2: Output Phase Select (DAC) Default value: DREV2 Normal output (default) DREV2 Inverted output The DREV2 bit is used to control the phase of the analog signal outputs OUT L and V OUT R). MUT2x: Soft Mute Control (DAC) where x or corresponding to the DAC output V OUT L and V OUT R 2). Default value: MUT2x Mute disabled (default) MUT2x Mute enabled The mute bits, MUT21 and MUT22, are used to enable or disable the soft mute function for the corresponding DAC outputs, V OUT L and V OUT The soft mute function is incorporated into the digital attenuators. When mute is disabled (MUT2x 0), the attenuator and DAC operate normally. When mute is enabled by setting MUT2x the digital attenuator for the corresponding output is decreased from the current setting to infinite attenuation at the rate of one 0.5-dB step for every 8/f S time interval. By setting MUT2x the attenuator is increased to the previously programmed attenuation level at the rate of one 0.5-dB step for every 8/f S time interval. This provides pop-free muting of the DAC output. Submit Documentation Feedback

www.ti.com PCM3060 SLAS533 MARCH 2007 B15 B14 B13 B12 B11 B10 Register FLT DMF1 DMF0 DMC RSV RSV ZREV AZRO FLT: Digital Filter Rolloff Control (DAC) Default value: FLT Sharp rolloff (Default) FLT Slow rolloff The FLT bit allows the user to select the digital filter roll-off that is best suited to their application. Sharp and Slow filter roll-off selections are available. The filter responses for these selections are shown in the Typical Performance Curves section of this data sheet. DMF[1:0]: Sampling Frequency Selection for the De-Emphasis Function (DAC) Default value: DMF[1:0] De-Emphasis Sampling Rate Selection 44.1 kHz (default) kHz kHz Reserved The DMF[1:0] bits are used to select the sampling frequency of the digital de-emphasis function when it is enabled. DMC: Digital De-Emphasis Function Control (DAC) Default value: DMC De-emphasis disabled (default) DMC De-emphasis enabled The DMC bit is used to enable or disable the digital de-emphasis function. See the plots shown in the Typical Performance Curves section of this data sheet for frequency characteristics. ZREV: Zero-Flag Polarity Select (DAC) Default value: ZREV High for zero detect (default) ZREV Low for zero detect The ZREV bit is used to control the polarity of zero flag pins. AZRO: Zero-Flag Function Select (DAC) Default value: AZRO ZEROL: L-ch ZERO detection (default) ZEROR: R-ch ZERO detection (default) AZRO ZEROL: L and R ZERO detection ZEROR: L and R ZERO detection The AZRO bit is used to select the function of zero flag pins. Submit Documentation Feedback

www.ti.com PCM3060 SLAS533 MARCH 2007 B15 B14 B13 B12 B11 B10 Register AT117 AT116 AT115 AT114 AT113 AT112 AT111 AT110 B15 B14 B13 B12 B11 B10 Register AT127 AT126 AT125 AT124 AT123 AT122 AT121 AT120 AT1x[7:0]: Digital Attenuation Level Setting (ADC) where x or corresponding to the ADC output L-ch part of DOUT or R-ch part of DOUT 2). Default value: 1101 0111b AT1x[7:0] DECIMAL VALUE ATTENUATION LEVEL SETTING 1111 1111b 255 dB 1111 1110b 254 19.5 dB 1111 1101b 253 dB 1101 1000b 216 0.5 dB 1101 0111b 215 dB, no attenuation (default) 1101 0110b 214 0.5 dB 0001 0000b 99.5 dB 0000 1111b 100 dB 0000 1110b Mute 0000 0000b Mute Each ADC channel has a digital attenuator function with 20-dB gain. The attenuation level may be set from dB to 100 dB in 0.5-dB steps, and also may be set to infinite attenuation (mute). The attenuation level change from the current value to the target value is performed by incrementing or decrementing one by 0.5-dB step at the timing of zero-cross detection on the input signal which is sampled for every 1/f S time interval, or for every 8/f S time interval if the zero-cross detection mode is disabled by ZCDD setting. If a zero-crossing is not detected for 512/f S actual level change is done for every 1/f S time interval until a zero-crossing is detected again. While the attenuation level change sequence is in progress, new commands for attenuation level change are not processed, but the new command overwrites the previous command in the command buffer. The last command for attenuation level change is performed after the present attenuation level change sequence is finished. The attenuation level for each channel can be set individually using the following formula, and the above table shows attenuation levels for various settings: Attenuation level (dB) 0.5 (AT1x[7:0] DEC 215), where AT1x[7:0] DEC through 255 for AT1x[7:0] DEC through 14, the level is set to infinite attenuation (mute). Submit Documentation Feedback

www.ti.com PCM3060 SLAS533 MARCH 2007 B15 B14 B13 B12 B11 B10 Register CSEL1 S S S RSV RSV FMT11 FMT10 CSEL1: Clock Select for ADC Operation Default value: (SCKI1, BCK1, LRCK1 enabled for ADC operation) CSEL1 SCKI1, BCK1, LRCK1 enabled for ADC operation (default) CSEL1 SCKI2, BCK2, LRCK2 enabled for ADC operation The CSEL1 bit controls the system clock and audio interface clocks for the ADC operation. SCKI1, BCK1, LRCK1 are used for ADC portion if CSEL1 (default), and SCKI2, BCK2, LRCK2 are used for ADC portion if CSEL1 S 1[2:0]: Audio Interface Mode for ADC Default value: 000 (slave mode) S 1[2:0] Audio Interface Mode for ADC Slave mode (default) Master mode, 768 f S Master mode, 512 f S Master mode, 384 f S Master mode, 256 f S Reserved Reserved Reserved The S 1[2:0] bits control the audio interface mode for the ADC. FMT1[1:0]: Audio Interface Format for ADC Default value: S mode) FMT1[1:0] Audio Interface Format for ADC 24-bit I S format (default) 24-bit left-justified format 24-bit right-justified format 16-bit right-justified format The FMT1[1:0] bits control the audio interface mode for ADC. Submit Documentation Feedback

www.ti.com PCM3060 SLAS533 MARCH 2007 B15 B14 B13 B12 B11 B10 Register RSV RSV RSV ZCDD BYP DREV MUT12 MUT11 ZCDD: Zero-Cross Detection Disable for Digital Attenuation (ADC) Default value: ZCDD Zero-cross detection enabled (default) ZCDD Zero-cross detection disabled The ZCDD bit controls the zero-cross detect function for digital attenuation and mute. When zero-cross detection is enabled, the actual level change for digital attenuation and mute is done at the timing of zero-cross detection on the input signal which is sampled for every 1/f S time interval. If zero-crossing is not detected for 512/f S the actual level change is done for every 1/f S time interval until a zero-crossing is detected again as timeout control for no zero-crossing input signal. When zero-cross detection is disabled, the actual level change is done at the timing of 8/f S time interval. BYP: HPF Bypass Control (ADC) Default value: BYP Normal output, HPF enabled (default) BYP Bypassed output, HPF disabled The BYP bit controls the HPF function; the dc component of the input signal and the internal dc offset are converted in bypass mode. DREV1: Input Phase Select (ADC) Default value: DREV1 Normal input (default) DREV1 Inverted input The DREV1 bit is used to control the phase of analog signal inputs IN L and V IN R). MUT1x: Soft Mute Control (ADC) where x or corresponding to the ADC output L-ch part of DOUT and R-ch part of DOUT 2). Default value: MUT1x Mute disabled (default) MUT1x Mute enabled The mute bits, MUT11 and MUT12, are used to enable or disable the soft mute function for the corresponding ADC outputs, DOUT. The soft mute function is incorporated into the digital attenuators. When mute is disabled (MUT1x 0), the attenuator and ADC operate normally. When mute is enabled by setting MUT1x the digital attenuator for the corresponding output is decreased from the current setting to infinite attenuation in 0.5 dB step at the timing of zero-cross detection on the input signal which is sampled for every 1/f S time interval, or for every 8/f S time interval if zero-cross detection mode is disabled by ZCDD setting. If a zero-crossing is not detected for 512/f S actual level change is done for every 1/f S time interval until zero-crossing is detected again. By setting MUT1x the attenuator is increased to the previously programmed attenuation level in 0.5 dB step in the same manner as for decreasing. This provides pop-free muting for the ADC input. Submit Documentation Feedback

www.ti.com TYPICAL CIRCUIT CONNECTION 5□V 0□V Control MCU 3.3□V 0 V Analog Input MODE MS/IFMD/ADR V RIN V LIN VCC V L+OUT V R+OUT V L–OUT V R–OUT VCOM AGND1 AGND2 SGND RST MC/FMT/SCL MD/DEMP/SDA DOUT LRCK1 BCK1 SCKI1 VDD DGND SCKI2 BCK2 LRCK2 DIN ZEROR ZEROL Termination (3) (4) (2) (1) 3.3 V3.3 V

0 V0 V

C1, C2:□0.1- F□ceramic□capacitor□and□10- F□electrolytic□capacitor,□depend□on□power□supply. C3:□0.1- F□ceramic□capacitor□and□10- F□electrolytic□capacitor□is□recommended. C4,□C5:□4.7- F□electrolytic□capacitor□is□recommended□for□3-Hz□cutoff□frequency. The□termination□for□mode/configuration□control. Either□one□of□following□circuits□has□to□be□applied□according□to□necessary□mode/configuration. Resistor□value□must□be□220□k , 5 %□tolerance. /c109 /c109 /c109 /c109 /c109 /c87 /c177 Note: Audio Receiver /Encoder Audio Transmitter /Decoder Analog□Output Post□LPF and Buffer S0257-01 PCM3060 SLAS533 MARCH 2007 Figure illustrates typical circuit connection. Figure 33. Typical Application Diagram Submit Documentation Feedback

www.ti.com Application Examples for Analog Input and Output a) Example of V biased buffering for 2 Vrms input with over voltage protection.COM Input V XIN V X+OUT V X+OUT VCOM V X–OUT VCOM R1C1 b) Example of capacitor-less differential to single-ended converter with LPF and gain for 2 Vrms standard output. Output c) Example of V -biased single supply single-ended application with LPF and MUTE control for 2 Vrms standard output.COM Mute ZEROx Mute Output OR Example of C, R□value R1: 20□k R2: 11 k R3: 1□k C1: 10 F C2: 220□pF C3: 0.1 F fc: 66 kHz /c87 /c87 /c87 /c109 /c109 Example of C, R□value R1,□R2: 10□k R3,□R4: 7.5 k R5,□R6: 1.8□k R7:□100 C1: 1000□pF C2,□C3: 470□pF fc: 64 kHz /c87 /c87 /c87 /c87 Example of C, R□value R1: 10□k R2: 15 k R3: 2.4□k C1: 1500□pF C2: 220□pF C3: 0.1 F C4:□10 F fc: 57 kHz /c87 /c87 /c87 /c109 /c109 S0258-01 PCM3060 SLAS533 MARCH 2007 Figure 34. Application Examples for Analog Input and Output Submit Documentation Feedback

www.ti.com DESIGN AND LAYOUT CONSIDERATIONS IN APPLICTION Power Supply Pins CC V DD Grounding (AGND1, AGND2, SGND, DGND) V IN V IN R Pins V COM Pin V OUT L+, V OUT L V OUT R+, V OUT R Pins MODE Pin System Clocks PCM3060 SLAS533 MARCH 2007 The digital and analog power supply lines to the PCM3060 should be bypassed to the corresponding ground pins with 0.1- µ F ceramic and 10- µ F electrolytic capacitors as close to the pins as possible to maximize the dynamic performance of the ADC and DAC. Although the PCM3060 has two power lines to maximize the potential of dynamic performance, using one common source, 5-V power supply for V CC and a 3.3-V power supply for V DD which is generated from the 5-V power supply for V CC is recommended to avoid unexpected problems, such as latch-up, from incorrect power supply sequencing. To maximize the dynamic performance of the PCM3060, the analog and digital grounds are not connected internally. These points should have very low impedance to avoid digital noise and signal components feeding back into the analog ground. So, they should be connected directly to each other under the parts to reduce the potential of noise problems. A 4.7- µ F electrolytic capacitor is recommended as the ac coupling capacitor, which gives a 3-Hz cutoff frequency. If higher full-scale input voltage is required, it can be adjusted by adding only one series resistor to the V IN X pins, although a small gain error is added due to variations of absolute input resistance of the PCM3060. For example, adding 9.1 k Ω gives Vrms full-scale with about 10% gain error. Ceramic 0.1- µ F and electrolytic 10- µ F capacitors are recommended between V COM and AGND to ensure low source impedance of the ADC and DAC references. These capacitors should be located as close as possible to the V COM pins to reduce dynamic errors on ADC and DAC references. The differential to single-ended buffer with post LPF can be directly (without capacitor) connected to these output pins, thereby minimizing the use of coupling capacitors for the 2-Vrms outputs. The output pins in single-ended mode are assigned to V OUT and V OUT in single-ended mode, the V OUT L and V OUT R pins must be open. This pin is a logic input with quad-state input capability. The pin is connected to V DD for High, to DGND for Low, and pulled up or pulled down through an external resistor and for the two mid-states in order to distinguish the four input states. The pullup or pulldown resistor must be 220 k Ω tolerance. The quality of SCKI1/2 may influence dynamic performance, as the PCM3060 (both ADC and DAC) operates based on SCKI1/2. Therefore, it may be required to consider the jitter, duty, rise and fall time, etc. of the system clocks. The PCM3060 supports asynchronous operation between the ADC and DAC. Therefore, there is no restriction on the relationship between SCKI1 and SCKI2 for digital operation, but it is strongly recommended to use a common clock if the application does not require different base clock frequencies, like 44.1 kHz and kHz. Submit Documentation Feedback

www.ti.com Audio Interface Clocks External Mute Control PCM3060 SLAS533 MARCH 2007 In slave mode, PCM3060 does not require specific timing relationship between BCK1/LRCK1 and SCKI1, BCK2/LRCK2 and SCKI2, but there is a possibility of performance degradation with a certain timing relationship between them. In that case, specific timing-relationship control might solve this performance degradation. In master mode, there is a possibility of performance degradation due to heavy loads on BCK1/LRCK1, BCK2/LRCK2 and DOUT. It is recommended to load these pins as lightly as possible. For power-down ON/OFF control without the pop noise which is generated by a dc level change on the DAC output, the external mute control is generally required. Use of the following control sequence is recommended: external mute ON, codec power down ON, SCKI1/SCKI2 stop and resume if necessary, codec power down OFF, and external mute OFF. Submit Documentation Feedback

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) PCM3060PW ACTIVE TSSOP PW 28 50 TBD Call TI Call TI PCM3060PWR ACTIVE TSSOP PW 28 2000 TBD Call TI Call TI (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 30-Mar-2007 Addendum-Page 1

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65 M0,10 0,10 0,25 0,50 0,75 0,15 NOM Gage Plane 9,80 9,60 7,90 7,70 2016 6,60 6,40 4040064/F 01/97 0,30 6,60 6,20 0,19 4,30 4,50 0,15 A 1,20 MAX 5,10 4,90 3,10 2,90 A MAX A MIN DIM PINS ** 0,05 4,90 5,10 Seating Plane 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

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