PCM3052ARTF

PCM3052A BURR-BROWN | Alldatasheet

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24-BIT, 96-kHz STEREO AUDIO CODEC WITH MICROPHONE AMPLIFIER, BIAS, MUXTIPLEXER, AND PGA Multiple Functions With I C Interface: Microphone Amplifier and Bias Digital De-Emphasis: 32-, 44.1-, 48-kHz Monaural Microphone Amplifier: 34-dB Gain Zipper-Noise-Free Digital Attenuation and at Differential Input Soft Mute for DAC Microphone Bias: mA at 3.75 V HPF Bypass Control for ADC Multiplexer and PGA S/PDIF Output Control Multiplex of Stereo Single-Ended Line Power Down: ADC/DAC Independently Inputs and Monaural Microphone Amplifier External Power-Down Pin: 0.1 Vrms to 1.5 Vrms Full-Scale Input Range ADC/DAC Simultaneously 22-k Ω Input Resistance at 0.1-Vrms Input Audio Data Format: 24-Bit I S Only dB to dB/range, dB/step PGA Sampling Rate: Reference Output: mA at 2.5 V kHz for Both ADC and DAC 24-Bit Delta-Sigma ADC and DAC System Clock: 256 f S Only Stereo ADC: Dual Power Supplies: Full-Scale Input: Vp-p V for Analog and 3.3 V for Digital Antialiasing Filter Included Package: VQFN-32 Decimation Filter: Pass-Band Ripple: 0.05 dB Stop-Band Attenuation: dB The PCM3052A is a low-cost, single-chip, 24-bit stereo audio codec (ADC and DAC) with On-Chip High-Pass Filter: 0.91 Hz at single-ended analog voltage input and output. It also f S kHz has an analog front end consisting of a 34-dB High Performance: microphone amplifier, microphone bias generator, THD+N: dB (Typical) stereo multiplexers, and a wide-range PGA. Analog- to-digital converters (ADCs) employ delta-sigma SNR: 101 dB (Typical) modulation with 64-times oversampling. On the other Dynamic Range: 101 dB (Typical) hand, digital-to-analog converters (DACs) employ Stereo DAC: modulation with 64- and 128-times oversampling. ADCs include a digital decimation filter with a Single-Ended Voltage Output: Vp-p high-pass filter, and DACs include an 8-times Analog Low-Pass Filter Included oversampling digital interpolation filter. The Oversampling Digital Filter: PCM3052A has many functions which are controlled Pass-Band Ripple: 0.03 dB using the I C interface: DAC digital de-emphasis, digital attenuation, soft mute etc. The PCM3052A Stop-Band Attenuation: dB also has an S/PDIF output pin for the DAC digital High Performance: input. The power-down mode, which works on ADCs THD+N: dB (Typical) and DACs simultaneously, is provided by an external pin. The PCM3052A is suitable for a wide variety of SNR: 105 dB (Typical) cost-sensitive PC audio (recorder and player) Dynamic Range: 104 dB (Typical)

applications

required. S/PDIF Output for DAC Digital Input The PCM3052A is fabricated using a highly advanced A CMOS process and is available in a small 32-pin VQFN package. Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. System Two, Audio Precision are trademarks of Audio Precision, Inc. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright 2005, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS PCM3052A SLES160 NOVEMBER 2005 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. over operating free-air temperature range (unless otherwise noted) (1) PCM3052A V CC V CC V CC 0.3 V to 6.5 V Supply voltage V DD 0.3 V to V Supply voltage differences V CC V CC V CC 0.1 V Ground voltage differences AGND1, AGND2, AGND3, DGND 0.1 V PDWN DIN, SCKI, SDA, SCL, ADR, I2CEN 0.3 V to 6.5 V Digital input voltage DOUT, LRCK, BCK, DOUTS 0.3 V to DD 0.3 V V IN V IN V REF V REF REFO, ATEST, M V OUT V OUT V COM 0.3 V to CC 0.3 6.5 V Analog input voltage MINP, MINM, MBIAS Input current (any pins except supplies) mA Ambient temperature under bias C to 125 C Storage temperature C to 150 C Junction temperature 150 C Lead temperature (soldering) 260 s Package temperature (reflow, peak) 260 C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT V DD Digital supply voltage 3.3 3.6 V V CC Analog supply voltage 4.5 5.5 V Digital input logic family TTL compatible System clock MHz Digital input clock frequency Sampling clock kHz Line input, full scale, PGA dB Vp-p Analog input voltage Microphone input, full scale, PGA dB mVp-p Digital output load capacitance pF Line output load resistance k Ω Line output load capacitance pF Microphone bias output load resistance 3.75 k Ω Reference output load resistance 250 Ω T A Operating free-air temperature C

www.ti.com ELECTRICAL CHARACTERISTICS PCM3052A SLES160 NOVEMBER 2005 All specifications at T A V CC V CC V CC V DD 3.3 f S kHz, SCKI 256 f S 24-bit data, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUT/OUTPUT DATA FORMAT Audio data interface format I S Audio data bit length Bits Audio data format MSB-first, complement Sampling frequency, ADC kHz f S Sampling frequency, DAC kHz System clock frequency 256 f S MHz INPUT LOGIC V IH (1) V DD Input logic level VDC V IL (1) 0.8 V IH (2) (3) 5.5 Input logic level VDC V IL (2) (3) 0.8 I IH (2) V IN V DD Input logic current µ A I IL (2) V IN V I IH (1)(3) V IN V DD 100 Input logic current µ A I IL (1) (3) V IN V OUTPUT LOGIC V OH (4) I OUT mA 2.8 VDC V OL (4) (5) I OUT mA 0.5 Output logic level V OH (6) I OUT 0.3 mA 4.5 VDC V OL (6) I OUT 0.3 mA 0.5 MICROPHONE AMPLIFIER Input level Single-ended mVrms Gain Single-ended dB Input resistance Single-ended k Ω Frequency response dB kHz SNR 1-kHz, 100-mVrms output dB THD+N 1-kHz, 1-Vrms output dB MICROPHONE BIAS GENERATOR 0.75 V CC 0.75 V CC Output voltage I OUT mA 0.75 V CC V 0.15 0.15 Output source current mA Output impedance Ω Output noise voltage 100 Hz kHz, with 10- µ F 1.8 µ Vrms decoupling REFERENCE OUTPUT 0.5 V CC 0.5 V CC Output voltage I OUT mA 0.5 V CC V 0.15 0.15 Output source/sink current mA Output impedance Ω Output noise voltage 100 Hz kHz, with 10- µ F 1.8 µ Vrms decoupling (1) Pins 10, 11: LRCK, BCK (Schmitt-trigger input with 50-k Ω typical internal pulldown resistor) (2) Pins 12, 17, 18, 19, 21: DIN, SCKI, SDA, SCL, I2CEN (Schmitt-trigger input, 5-V tolerant) (3) Pins PDWN ADR (Schmitt-trigger input with 50-k Ω typical internal pulldown resistor, 5-V tolerant). (4) Pins 13, 14: DOUT, DOUTS (5) Pin 18: SDA (Open-drain LOW output) (6) Pin M

www.ti.com PCM3052A SLES160 NOVEMBER 2005 ELECTRICAL CHARACTERISTICS (continued) All specifications at T A V CC V CC V CC V DD 3.3 f S kHz, SCKI 256 f S 24-bit data, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AFE MULTIPLEXER Input channel CH Input range for full scale V IN V IN R 0.1 1.5 Vrms Input Impedance V IN V IN R 143 k Ω Antialiasing filter frequency response dB, PGA gain dB 300 kHz Input center voltage (VREF1) 0.5 V CC V AFE PGA Gain range dB Gain step dB Monotonicity Ensured ADC CHARACTERISTICS Resolution Bits Full-scale input voltage V IN V IN R at PGA gain dB 0.6 V CC Vp-p DC Accuracy Gain mismatch, channe-to-channel Full scale input, V IN V IN R of FSR Gain error Full scale input, V IN V IN R of FSR Bipolar-zero error HPF bypass, V IN V IN R of FSR Dynamic Performance (7) f S kHz, V IN 0.5 dB f S kHz, V IN 0.5 dB THD+N Total harmonic distortion noise dB f S kHz, V IN dB f S kHz, V IN dB f S kHz, A-weighted 101 Dynamic range dB f S kHz, A-weighted 101 f S kHz, A-weighted 101 S/N Signal-to-noise ratio dB f S kHz, A-weighted 101 f S kHz Channel separation dB (between L-ch and R-ch of line-in) f S kHz f S kHz Channel separation dB (between microphone and line-in) f S kHz Digital Filter Performance Pass band 0.05 dB 0.454 f S Hz Stop band 0.583 f S Hz Pass-band ripple 0.05 dB Stop-band attenuation 0.583 f S dB Delay time 17.4/f S s HPF frequency response dB 0.019 f S MHz DAC CHARACTERISTICS Resolution Bits DC Accuracy Gain mismatch, channel-to-channel of FSR Gain error of FSR Bipolar zero error of FSR (7) f IN kHz, using System Two audio measurement system by Audio Precision in the RMS mode with 20-kHz LPF and 400-Hz HPF in the calculation, at PGA gain dB, for V IN L and V IN

www.ti.com PCM3052A SLES160 NOVEMBER 2005 ELECTRICAL CHARACTERISTICS (continued) All specifications at T A V CC V CC V CC V DD 3.3 f S kHz, SCKI 256 f S 24-bit data, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Dynamic Performance (8) f S kHz, V OUT dB f S kHz, V OUT dB THD+N Total harmonic distortion noise dB f S kHz, V OUT dB f S kHz, V OUT dB f S kHz, EIAJ, A-weighted 104 Dynamic range dB f S kHz, EIAJ, A-weighted 106 f S kHz, EIAJ, A-weighted 105 S/N Signal-to-noise ratio dB f S kHz, EIAJ, A-weighted 106 f S kHz 103 Channel separation dB f S kHz 104 Analog Output Output voltage 0.8 V CC Vp-p Center voltage 0.5 V CC V Load impedance AC coupling k Ω f kHz 0.03 LPF frequency response dB f kHz 0.20 Digital Filter Performance Pass band 0.03 dB 0.454 f S Hz Stop band 0.546 f S Hz Pass-band ripple 0.03 dB Stop-band attenuation 0.546 f S dB Delay time 20/f S s De-emphasis error 0.1 dB POWER SUPPLY REQUIREMENTS V CC V CC 4.25 5.5 Voltage range VDC V CC V DD 3.3 3.6 f S kHz mA I CC (9) f S kHz Full power down (10) 300 µ A Supply current f S kHz mA I DD f S kHz Full power down (10) µ A Operation, f S kHz 228 300 Operation, f S kHz 268 ADC operation at f S 180 Power dissipation kHz/DAC power down mW ADC power down/DAC operation at f S kHz Full power down (10) 1.8 (8) f OUT kHz, using System Two audio measurement system by Audio Precision in the RMS mode with 20-kHz LPF and 400-Hz HPF. (9) I CC I CC I CC I CC (10) Halt SCKI, BCK, LRCK.

www.ti.com DEVICE INFORMATION Single-Ended MUX and PGA LRCK VINL Reference and Buffer VREF1 VREF2 VINR Delta-Sigma Modulator Decimation Filter with HPF Power Supply VCC3AGND3 VCC2AGND2 Clock and Timing Generator, Power Control Audio Data Interface DOUT Delta-Sigma Modulator DOUTS DIN Analog LPF and Buffer Amp VOUTL VCOM VOUTR Multilevel Delta-Sigma Modulator Oversampling Interpolation Filter Mode Control Interface I2CEN Multilevel Delta-Sigma Modulator ADR SCL SDAAnalog LPF and Buffer Amp AGND1 SCKI PDWN REFO VDDDGNDVCC1 BCLK Mic Bias Mic AmpMINM MBIAS MINP ATEST L/M B0085-01 Single-Ended MUX and PGA PCM3052A SLES160 NOVEMBER 2005 ELECTRICAL CHARACTERISTICS (continued) All specifications at T A V CC V CC V CC V DD 3.3 f S kHz, SCKI 256 f S 24-bit data, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEMPERATURE RANGE Operation temperature C θ JA Thermal resistance 100 C/W BLOCK DIAGRAM

www.ti.com PIN ASSIGNMENTS VCOM MBIAS MINM MINP AGND3 VCC3 REFO VDD DGND DOUTS DOUT DIN BCK LRCK RTF PACKAGE (TOP VIEW) P0036-01 ATEST VINL L/M VREF1 VREF2 VINR VCC1 AGND1 PDWN VOUTL VOUTR VCC2 AGND2 I2CEN ADR SCL SDA SCKI PCM3052A SLES160 NOVEMBER 2005 DEVICE INFORMATION (continued) TERMINAL FUNCTIONS TERMINAL I/O NO. ADR I Mode control address select input (1) AGND1 ADC analog ground AGND2 DAC analog ground AGND3 Microphone amplifier and bias analog ground ATEST O Analog test, must be open DGND Digital ground BCK I Audio data bit clock input (2) DIN I Audio data digital input (3) DOUT O Audio data digital output DOUTS O S/PDIF data digital output I2CEN I Mode control enable/disable input, active HIGH (3) M O ADC line/microphone select indicator LRCK I Audio data latch enable input (2) MBIAS O Microphone bias output/decoupling, 0.75 V CC MINM I Microphone amplifier input to ADC, inverting MINP I Microphone amplifier input to ADC, non-inverting PDWN I ADC and DAC power down control input, active LOW (1) REFO O Reference output decoupling, 0.5 V CC (1) Schimtt-trigger input with 50-k Ω typical internal pulldown resistor, 5-V tolerant (2) Schimtt-trigger input with 50-k Ω typical internal pulldown resistor (3) Schimtt-trigger input, 5-V tolerant

www.ti.com TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (ADC SECTION) DIGITAL FILTER Normalized Frequency [× fS] −200 −150 −100 −50 0 8 16 24 32 Amplitude − dB G001 Normalized Frequency [× fS] −100 −80 −60 −40 −20 Amplitude − dB G002 PCM3052A SLES160 NOVEMBER 2005 DEVICE INFORMATION (continued) TERMINAL FUNCTIONS (continued) TERMINAL I/O NO. SCKI I System clock input, 256 f S (3) SCL I Mode control clock input (3) SDA I/O Mode control data input/output (4) V CC ADC analog power supply, V V CC DAC analog power supply, V V CC Microphone amplifier and bias analog power supply, V V COM DAC common voltage decoupling, 0.5 V CC V DD Digital power supply, 3.3 V V IN L I Line input to ADC, L-channel V IN R I Line input to ADC, R-channel V OUT L O Analog output from DAC, L-channel V OUT R O Analog output from DAC, R-channel V REF ADC reference voltage output, 0.5 V CC V REF ADC reference voltage decoupling, V CC (4) Schimtt-trigger input/open-drain LOW output, 5-V tolerant All specifications at T A V CC V CC V CC V DD 3.3 f S kHz, SCKI 256f S 24-bit data, unless otherwise noted. OVERALL CHARACTERISTICS STOP-BAND ATTENUATION CHARACTERISTICS Figure Figure

www.ti.com Normalized Frequency [× fS] −1.0 −0.8 −0.6 −0.4 −0.2 0.0 0.2 Amplitude − dB G003 Normalized Frequency [× fS] −10 Amplitude − dB G004 −4.13 dB at 0.5 fS Normalized Frequency [× fS/1000] −1.0 −0.8 −0.6 −0.4 −0.2 0.0 0.2 0 1 2 3 4 Amplitude − dB G006 Normalized Frequency [× fS/1000] −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 Amplitude − dB G005 PCM3052A SLES160 NOVEMBER 2005 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (ADC SECTION) (continued) All specifications at T A V CC V CC V CC V DD 3.3 f S kHz, SCKI 256f S 24-bit data, unless otherwise noted. PASS-BAND RIPPLE CHARACTERISTICS TRANSITION BAND CHARACTERISTICS Figure Figure HIGH-PASS FILTER STOP-BAND CHARACTERISTICS HIGH-PASS FILTER PASS-BAND CHARACTERISTICS Figure Figure

www.ti.com ANALOG FILTER (Line Input, PGA Gain dB) −50 −40 −30 −20 −10 f − Frequency − kHz Amplitude − dB 1 10 100 10k1k G007 f−3dB = 300 kHz −1.0 −0.8 −0.6 −0.4 −0.2 0.0 f − Frequency − kHz Amplitude − dB 0.1 1 100 1k G008 PCM3052A SLES160 NOVEMBER 2005 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (ADC SECTION) (continued) All specifications at T A V CC V CC V CC V DD 3.3 f S kHz, SCKI 256f S 24-bit data, unless otherwise noted. ANTIALIASING FILTER STOP-BAND CHARACTERISTICS ANTIALIASING FILTER PASS-BAND CHARACTERISTICS Figure Figure

www.ti.com TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (DAC SECTION) DIGITAL FILTER −140 −120 −100 −80 −60 −40 −20 0 1 2 3 4 Amplitude − dB Frequency [× fS] G009 −1.0 −0.8 −0.6 −0.4 −0.2 0.0 0.2 Amplitude − dB Frequency [× fS] G010 −10 0 2 4 6 8 10 12 14 Level − dB f − Frequency − kHz G011 −0.5 −0.4 −0.3 −0.2 −0.1 0.0 0.1 0.2 0.3 0.4 0.5 0 2 4 6 8 10 12 14 Error − dB f − Frequency − kHz G012 PCM3052A SLES160 NOVEMBER 2005 All specifications at T A V CC V CC V CC V DD 3.3 f S kHz, SCKI 256f S 24-bit data, unless otherwise noted. FREQUENCY RESPONSE, STOP BAND (Sharp Rolloff) FREQUENCY RESPONSE, PASS BAND (Sharp Rolloff) Figure Figure 10. DE-EMPHASIS S kHz) DE-EMPHASIS ERROR S kHz) Figure 11. Figure 12.

www.ti.com −10 0 2 4 6 8 10 12 14 16 18 20 Level − dB f − Frequency − kHz G013 −0.5 −0.4 −0.3 −0.2 −0.1 0.0 0.1 0.2 0.3 0.4 0.5 0 2 4 6 8 10 12 14 16 18 20 Error − dB f − Frequency − kHz G014 −10 0 2 4 6 8 10 12 14 16 18 20 22 Level − dB f − Frequency − kHz G015 −0.5 −0.4 −0.3 −0.2 −0.1 0.0 0.1 0.2 0.3 0.4 0.5 0 2 4 6 8 10 12 14 16 18 20 22 Error − dB f − Frequency − kHz G016 PCM3052A SLES160 NOVEMBER 2005 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (DAC SECTION) (continued) All specifications at T A V CC V CC V CC V DD 3.3 f S kHz, SCKI 256f S 24-bit data, unless otherwise noted. DE-EMPHASIS S 44.1 kHz) DE-EMPHASIS ERROR S 44.1 kHz) Figure 13. Figure 14. DE-EMPHASIS S kHz) DE-EMPHASIS ERROR S kHz) Figure 15. Figure 16.

www.ti.com ANALOG FILTER −50 −40 −30 −20 −10 f − Frequency − kHz Amplitude − dB 1 10 100 10k1k G017 f−3dB = 300 kHz −1.0 −0.8 −0.6 −0.4 −0.2 0.0 f − Frequency − kHz Amplitude − dB 0.1 1 100 1k G018 PCM3052A SLES160 NOVEMBER 2005 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (DAC SECTION) (continued) All specifications at T A V CC V CC V CC V DD 3.3 f S kHz, SCKI 256f S 24-bit data, unless otherwise noted. STOP-BAND CHARACTERISTICS kHz MHz) PASS-BAND CHARACTERISTICS (100 Hz MHz) Figure 17. Figure 18.

www.ti.com TYPICAL PERFORMANCE CURVES (ADC SECTION) LINE INPUT (at PGA Gain dB) 100 105 110 −40 −15 10 35 60 85 Dynamic Range and SNR − dB TA − Free-Air Temperature − ° C G020 SNR Dynamic Range −100 −95 −90 −85 −40 −15 10 35 60 85 THD+N − Total Harmonic Distortion + Noise at −0.5 dB − dB TA − Free-Air Temperature − ° C G019 100 105 110 Dynamic Range and SNR − dB VCC − Supply Voltage − V G022 SNR Dynamic Range −100 −95 −90 −85 THD+N − Total Harmonic Distortion + Noise at −0.5 dB − dB VCC − Supply Voltage − V G021 PCM3052A SLES160 NOVEMBER 2005 All specifications at T A V CC V CC V CC V DD 3.3 f S kHz, SCKI 256 f S 24-bit data, unless otherwise noted. THD+N DYNAMIC RANGE AND SNR vs vs TEMPERATURE TEMPERATURE Figure 19. Figure 20. THD+N DYNAMIC RANGE AND SNR vs vs SUPPLY VOLTAGE SUPPLY VOLTAGE Figure 21. Figure 22.

www.ti.com 100 105 110 32 48 64 80 96 fS − Sampling Frequency − kHz G024 Dynamic Range and SNR − dB SNR Dynamic Range −100 −95 −90 −85 32 48 64 80 96 THD+N − Total Harmonic Distortion + Noise at −0.5 dB − dB fS − Sampling Frequency − kHz G023 PCM3052A SLES160 NOVEMBER 2005 TYPICAL PERFORMANCE CURVES (ADC SECTION) (continued) All specifications at T A V CC V CC V CC V DD 3.3 f S kHz, SCKI 256 f S 24-bit data, unless otherwise noted. THD+N DYNAMIC RANGE AND SNR vs vs SAMPLING FREQUENCY SAMPLING FREQUENCY Figure 23. Figure 24.

www.ti.com TYPICAL PERFORMANCE CURVES (DAC SECTION) −105 −100 −95 −90 −40 −15 10 35 60 85 THD+N − Total Harmonic Distortion + Noise at 0 dB − dB TA − Free-Air Temperature − ° C G025 100 105 110 −40 −15 10 35 60 85 Dynamic Range and SNR − dB TA − Free-Air Temperature − ° C G026 SNR Dynamic Range −105 −100 −95 −90 THD+N − Total Harmonic Distortion + Noise at 0 dB − dB VCC − Supply Voltage − V G027 100 105 110 Dynamic Range and SNR − dB VCC − Supply Voltage − V G028 SNR Dynamic Range PCM3052A SLES160 NOVEMBER 2005 All specifications at T A V CC V CC V CC V DD 3.3 f S kHz, SCKI 256 f S 24-bit data, unless otherwise noted. THD+N DYNAMIC RANGE AND SNR vs vs TEMPERATURE TEMPERATURE Figure 25. Figure 26. THD+N DYNAMIC RANGE AND SNR vs vs SUPPLY VOLTAGE TEMPERATURE Figure 27. Figure 28.

www.ti.com −105 −100 −95 −90 32 48 64 80 96 THD+N − Total Harmonic Distortion + Noise at 0 dB − dB fS − Sampling Frequency − kHz G029 100 105 110 32 48 64 80 96 fS − Sampling Frequency − kHz G030 Dynamic Range and SNR − dB SNR Dynamic Range PCM3052A SLES160 NOVEMBER 2005 TYPICAL PERFORMANCE CURVES (DAC SECTION) (continued) All specifications at T A V CC V CC V CC V DD 3.3 f S kHz, SCKI 256 f S 24-bit data, unless otherwise noted. THD+N DYNAMIC RANGE AND SNR vs vs SAMPLING FREQUENCY SAMPLING FREQUENCY Figure 29. Figure 30.

www.ti.com TYPICAL PERFORMANCE CURVES ADC OUTPUT SPECTRUM (Line Input, at PGA Gain dB) f − Frequency − kHz −140 −120 −100 −80 −60 −40 −20 0 5 10 15 20 Amplitude − dB G031 f − Frequency − kHz −140 −120 −100 −80 −60 −40 −20 0 5 10 15 20 Amplitude − dB G032 DAC OUTPUT SPECTRUM f − Frequency − kHz −140 −120 −100 −80 −60 −40 −20 0 5 10 15 20 Amplitude − dB G033 f − Frequency − kHz −140 −120 −100 −80 −60 −40 −20 0 5 10 15 20 Amplitude − dB G034 PCM3052A SLES160 NOVEMBER 2005 All specifications at T A V CC V CC V CC V DD 3.3 f S kHz, SCKI 256 f S 24-bit data, unless otherwise noted. OUTPUT SPECTRUM 0.5 dB, N 8192) OUTPUT SPECTRUM dB, N 8192) Figure 31. Figure 32. OUTPUT SPECTRUM dB, N 8192) OUTPUT SPECTRUM dB, N 8192) Figure 33. Figure 34.

www.ti.com SUPPLY CURRENT −40 −15 10 35 60 85 Supply Current − mA TA − Free-Air Temperature − ° C G035 IDD ICC1 + ICC2 + ICC3 32 48 64 80 96 Supply Current − mA fS − Sampling Frequency − kHz G036 IDD ICC1 + ICC2 + ICC3 3.0 3.3 3.6 Supply Current − mA VDD − Supply Voltage − V G037 IDD Supply Current − mA VCC − Supply Voltage − V G038 ICC1 + ICC2 + ICC3 PCM3052A SLES160 NOVEMBER 2005 TYPICAL PERFORMANCE CURVES (continued) All specifications at T A V CC V CC V CC V DD 3.3 f S kHz, SCKI 256 f S 24-bit data, unless otherwise noted. SUPPLY CURRENT SUPPLY CURRENT vs SAMPLING FREQUENCY, vs ADC AND DAC OPERATING TEMPERATURE Figure 35. Figure 36. SUPPLY CURRENT SUPPLY CURRENT vs vs SUPPLY VOLTAGE SUPPLY VOLTAGE Figure 37. Figure 38.

www.ti.com THEORY OF OPERATION ADC SECTION 1st SW-CAP Integrator Analog In X(z) + − 2nd SW-CAP Integrator 3rd SW-CAP Integrator + − 4th SW-CAP Integrator + + + ++ + + + 5th SW-CAP Integrator Digital Out Y(z) Comparator Qn(z) H(z) 1-Bit DAC STF(z) = H(z) / [1 + H(z)] NTF(z) = 1 / [1 + H(z)] Y(z) = STF(z) * X(z) + NTF(z) * Qn(z) Signal Transfer Function Noise Transfer Function B0005-02 DAC SECTION PCM3052A SLES160 NOVEMBER 2005 The ADC block consists of a reference circuit, two channels of single-ended to differential converter, a fifth-order delta-sigma modulator with fully differential architecture, a decimation filter with high-pass filter, and a serial interface circuit which is also used as the serial interface for the DAC input signal as shown in the block diagram. Figure is the block diagram of the fifth-order delta-sigma modulator and transfer function. An on-chip reference circuit with two external capacitors provides all reference voltages that are needed in the ADC section, and defines the full-scale voltage range of both channels. An on-chip, single-ended to differential signal converter saves the design, space, and extra parts cost of an external signal converter. Full differential architecture provides a wide dynamic range and excellent power supply rejection performance. The input signal is sampled at oversampling rate and an on-chip antialiasing filter eliminates the need for an external sample-hold amplifier. A fifth-order delta-sigma noise shaper, which consists of five integrators using the switched-capacitor technique and a comparator, shapes the quantization noise generated outside of audio signal band by the comparator and 1-bit DAC. The high-order delta-sigma modulation randomizes the modulator outputs and reduces idle-tone level. The f S 1-bit stream from the delta-sigma modulator is converted to a 1-f S 24-bit digital signal by removing high-frequency noise components with the decimation filter. The dc component of the signal is removed by the HPF, and the HPF output is converted to a time-multiplexed serial signal through the serial interface. Figure 39. Block Diagram of Fifth-Order Delta-Sigma Modulator The DAC section is based on the delta-sigma modulator, which consists of an 8-level amplitude quantizer and a fourth-order noise shaper. This section converts the oversampled input data to 8-level delta-sigma format. A block diagram of the 8-level delta-sigma modulator is shown in Figure This 8-level delta-sigma modulator has the advantage of stability and clock jitter over the typical one-bit (2-level) delta-sigma modulator. The combined oversampling rate of the delta-sigma modulator and the internal interpolation filter is f S for all system clocks. The theoretical quantization-noise performance of the 8-level delta-sigma modulator is shown in Figure

www.ti.com B0008-03 Z–1 + + 8-Level Quantizer − Z–1IN 8 fS OUT 64 fS + Z–1 + Z–1 −180 −160 −140 −120 −100 −80 −60 −40 −20 0 1 2 3 4 5 6 7 8 fS − Sampling Frequency − kHz G039 Amplitude − dB 100 105 110 115 120 125 0 100 200 300 400 500 600 Jitter − psP−P G040 Dynamic Range − dB PCM3052A SLES160 NOVEMBER 2005 THEORY OF OPERATION (continued) Figure 40. 8-Level Delta-Sigma Modulator Block Diagram Figure 41. Quantization Noise Spectrum Figure 42. Clock Jitter

www.ti.com SYSTEM CLOCK tw(SCKH) tw(SCKL) 2 V 0.8 V 1/256 fS T0005−10 System Clock POWER SUPPLY ON, EXTERNAL RESET, AND POWER DOWN PCM3052A SLES160 NOVEMBER 2005 THEORY OF OPERATION (continued) The system clock for the PCM3052A must be 256 f S where f S is the audio sampling rate, kHz to kHz. Table lists typical system clock frequencies, and Figure illustrates the system clock timing. Table Typical System Clock SAMPLING RATE SYSTEM CLOCK FREQUENCY MHz FREQUENCY S LRCK 256 f S kHz 4.096 kHz 8.192 44.1 kHz 11.2896 kHz 12.288 kHz 24.576 PARAMETER MIN MAX UNIT t w(SCKH) System clock pulse duration, HIGH ns t w(SCKL) System clock pulse duration, LOW ns Figure 43. System Clock Timing The PCM3052A has both an internal power-on-reset circuit and an external reset circuit. The sequences for both resets are shown as follows. Figure is the timing chart of the internal power-on reset. Two power-on-reset circuits are implemented, one each for for V CC and V DD Initialization (reset) is performed automatically at the time when V CC and V DD exceed 3.9 V (typical) and 2.2 V (typical), respectively. Internal reset is released after 1024 SCKI from power-on-reset release, and the PCM3052A begins normal operation. V OUT L and V OUT R from the DAC are forced to the V COM 0.5 V CC level as V CC rises. When synchronization between SCKI, BCK, and LRCK is maintained, V OUT L and V OUT R go into the fade-in sequence. Then V OUT L and V OUT R provide outputs corresponding to DIN after t (DACDLY1) 2100/f S from power-on-reset release. On the other hand, DOUT from the ADC provides an output corresponding to V IN L and V IN R after t (ADCDLY1) 4500/f S from power-on-reset release. If synchronization is not maintained, the internal reset is not released, and operation is kept in the power-down mode. After resynchronization, the DAC goes into the fade-in sequence, and the ADC goes into normal operation after internal initialization. DOUTS can provide S/PDIF data after the power-on-reset release if the SPDIF bit is HIGH (see serial control port for mode control section). Figure shows timing chart for external reset. The PDWN pin (pin initiates external forced reset when PDWN LOW, and it provides the power-down mode, which is the lowest power-dissipation state in the PCM3052A. When PDWN transitions from HIGH to LOW while SCKI, BCK, and LRCK are synchronized, V OUT L and V OUT R are faded out and forced into V COM 0.5 V CC level after t DACDLY1 2100/f S At the same time as the internal reset becomes LOW, DOUT becomes ZERO, the PCM3052A enters the power-down mode. To return to normal operation, set PDWN to HIGH. Then the power-on reset sequence, Figure is performed.

www.ti.com VCC1, VDD 0 V LRCK, BCK, SCKI DOUT

1024 SCKI

Power Down Normal Operation ZERO PDWN VOUTL, VOUTR (VCC1 = 5 V, VDD = 3.3 V Typ) (VCC1 = 3.9 V, VDD = 2.2 V Typ) DOUTS t(DACDLY1), 2100 /fS VCOM (0.5 VCC2) About 40/fS t(ADCDLY1), 4500 /fS Enable if S/PDIF Bit = HIGHDisable T0097-01 PCM3052A SLES160 NOVEMBER 2005 DOUTS is driven LOW immediately after PDWN is asserted and recovers about 40/f S following PDWN release. Notes: Large pop noises can be generated on V OUT L and V OUT R if the power supply is turned off during normal operation. To switch PDWN during fade-in or fade-out causes an immediate change between fade-in and fade-out. Changing mode controls during normal operation can degrade analog performance. It is recommended that mode controls be changed through the serial control port, and that changing or stopping the clock, switching the power supply off, etc., be done in the power-down mode. Figure 44. DAC Output and ADC Output for Power-On Reset

www.ti.com VCC1, VCC2, VCC3, VDD LRCK, BCK, SCKI DOUT Power Down Normal Operation ZERO PDWN VOUTL, VOUTR (VCC1 − VCC3 = 5 V, VDD = 3.3 V Typ) DOUTS t(DACDLY1), 2100 /fS VCOM (0.5 VCC2) About 40/fS T0098-01 0 V Synchronous Clocks

0.5 VCC2

t(DACDLY1), 2100 /fS LOW t(ADCDLY1), 4500 /fS PCM3052A SLES160 NOVEMBER 2005 Figure 45. DAC Output and ADC Output for External Reset PDWN Pin)

www.ti.com PCM AUDIO INTERFACE LRCK Right-ChannelLeft-Channel BCK DIN MSB LSB 22 23 24321 T0016-15 MSB LSB 22 23 24321 DOUT MSB LSB 22 23 24321 MSB LSB 22 23 24321 DOUTS Sub-Frame Sub-Frame Sub-Frame PCM3052A SLES160 NOVEMBER 2005 Digital audio data is interfaced to the PCM3052A on LRCK (pin 10), BCK (pin 11), DIN (pin 12), DOUT (pin 13), and DOUTS (pin 14). The PCM3052A can accept 24-bit I S format only. In case of AC-3 type output data for DOUTS, bits to of DIN must be held LOW. See the Digital Audio Interface Transmitter (DIT) section of this data sheet. Table Audio Data Format DATA FORMAT 24-bit, MSB-first, I S The PCM3052A accepts only clocks of BCK during one clock of LRCK. Figure and Figure illustrate audio data input/output format and timing. Figure 46. Audio Data Input/Output Format

www.ti.com BCK LRCK DIN t(BCH) t(BCL) t(LRP) t(LB) t(BCY) 1.4 V t(BL) DOUT t(BDO) t(LDO)

0.5 VDD

t(DIS) t(DIH) 1.4 V 1.4 V T0021−03 PCM3052A SLES160 NOVEMBER 2005 PARAMETER MIN MAX UNIT t BCY BCK pulse cycle time 160 ns t BCH BCK pulse duration, HIGH ns t BCL BCK pulse duration, LOW ns t BL BCK rising edge to LRCK edge ns t LB LRCK edge to BCK rising edge ns t LRP LRCK pulse duration 4.2 µ s t DIS DIN setup time to BCK rising edge ns t DIH DIN hold time to BCK rising edge ns t BDO DOUT delay time from BCK falling edge ns t LDO DOUT delay time from LRCK edge ns t R Rising time of all signals ns t F Falling time of all signals ns NOTE: Load capacitance at DOUT is pF. Rising and falling time is measured from 10% to 90% of IN/OUT signal swing. Figure 47. Audio Data Input/Output Timing

www.ti.com SYNCHRONIZATION WITH DIGITAL AUDIO SYSTEM Within 6/fS t(DACDLY2) (32/fS) Normal Data VCOM (0.5 VCC2) Undefined DataNormal Data SynchronousAsynchronousSynchronous ResynchronizationSynchronization Lost DAC VOUT State of Synchronization Normal DataZero DataNormal DataADC DOUT t(ADCDLY2) (32/fS) Undefined Data T0020-07 Normal DataLowNormal DataDOUTS Undefined Data MICROPHONE AMPLIFIER AND MICROPHONE BIAS GENERATOR PCM3052A SLES160 NOVEMBER 2005 The PCM3052A operates with LRCK and BCK synchronized to the system clock in slave mode. The PCM3052A does not need specific phase relationship among LRCK, BCK, and the system clock, but does require the synchronization of LRCK, BCK, and the system clock. If the relationship between system clock and LRCK changes more than BCKs during one sample period due to LRCK jitter, etc., internal operation of DAC halts within 6/f S and the analog output is forced to 0.5 V CC until re-synchronization of the system clock to LRCK and BCK has completed and then the time of t (DACDLY2) has elapsed. DOUTS is also held LOW during the same period. Internal operation of the ADC also halts within 6/f S and digital output is forced into ZERO code until re-synchronization of the system clock to LRCK and BCK has completed and then the time of t (ADCDLY2) has elapsed. In case of changes less than BCKs, re-synchronization does not occur and the previously described analog/digital output control and discontinuity does not occur. Figure illustrates the DAC analog output, ADC digital output, and DOUTS output for loss of synchronization. During undefined data, the PCM3052A can generate some noise in audio signal. Also, the transition of normal to undefined data and undefined or zero data to normal creates a discontinuity of data on analog and digital outputs, which could generate some noise in audio signal. Figure 48. DAC Output and ADC Output for Loss of Synchronization The PCM3052A has a built-in, high-performance differential-input microphone amplifier with 34-dB gain, 5-k Ω (minimum) input resistance, and 59-dB SNR at 100-mVrms output. Bandwidth is kHz for 3-dB attenuation. The PCM3052A also has a low-noise microphone bias generator with 0.75-V CC and 1-mA current-source capability for electret microphones. Output impedance is Ω for external noise reduction. The output of the microphone amplifier and the line input are connected as inputs to the multiplexer. The serial control port can be used to control which input the multiplexer selects (see Figure

www.ti.com REFERENCE OUTPUT MUX S0124-01 Electret Microphone MINM MINP REF 34 dB 10 mA 6 ΩREFO (0.5 VCC1) −1 mA 48 ΩMBIAS (0.75 VCC1) LINE AND MICROPHONE INPUT SELECT INDICATOR PCM3052A SLES160 NOVEMBER 2005 The PCM3052A has a reference output pin (RFFO, pin 32) to supply reference voltage (0.5 V CC to external components. The pin has 10-mA sink/source capability with Ω output impedance. Figure 49. Microphone Amplifier, Microphone Bias Generator, and Reference Output The PCM3052A employs an indicator pin (L/ M pin to show which analog input is selected, line or microphone. Table Line and Microphone Select Indicator M LINE/MIC SELECT INDICATOR LOW Microphone HIGH Line

www.ti.com MULTIPLEXER AND PGA RIN(k, typical) 286 1 10(PGA Gain20) (1) LIN+ S0125-01 VINL L-ch −1 PGA (−4 dB to 20 dB)R R LIN− 2-ch MUX RIN+ VINR R-ch −1 PGA (−4 dB to 20 dB)R R RIN− Mic Amp ANALOG OUTPUTS FROM DAC VCOM OUTPUT FOR DAC DIGITAL AUDIO INTERFACE TRANSMITTER (DIT) PCM3052A SLES160 NOVEMBER 2005 The PCM3052A has built-in analog front-end circuit which is shown in Figure Multiplexer input and PGA gain are selected by mode control via the serial port, as shown in the Serial Control Port for Mode Control section. The full-scale input voltage range is 0.1 Vrms to 1.5 Vrms, and it can be adjusted to an adequate level for following the ADC sections. V IN L and V IN R input resistance is maintained above k Ω for all PGA gains. The input resistance value for each gain can be calculated by Equation Figure 50. Multiplexer and PGA The PCM3052A has two independent output channels, V OUT L and V OUT These are unbalanced outputs, each capable of driving Vp-p (typical) into a 5-k Ω ac-coupled load. The internal output amplifiers for V OUT L and V OUT R are biased to the dc common-mode (or bipolar zero) voltage, equal to 0.5 V CC The output amplifiers include an RC continuous-time filter, which helps to reduce the out-of-band noise energy present at the DAC outputs due to the noise-shaping characteristics of the PCM3052A delta-sigma modulators. The frequency response of this filter is shown in the typical performance curves. By itself, this filter is not adequate to attenuate the out-of-band noise to an acceptable level for many applications. An external low-pass filter is required to provide sufficient out-of-band noise rejection. Further discussion of DAC post-filter circuits is provided in the PCM1742 data sheet SBAS176 One unbuffered common-mode voltage output pin, V COM (pin 26), is brought out for decoupling purposes. This pin is nominally biased to a dc voltage level equal to 0.5 V CC This pin can be used to bias external circuits. Output resistance of this pin is k Ω (typical). The PCM3052A employs S/PDIF output from DOUTS (pin 14). The data S format only) from DAC digital data input (DIN, pin 12) is encoded to S/PDIF format with preambles according to IEC958. S/PDIF output is controlled through the serial control port. The output data type (linear PCM or AC-3) can be also selected through the serial control port. For the output data type of AC-3, the word length is limited to bits in the PCM3052A. Therefore, bits to in the I S format data must be set to LOW.

www.ti.com T0099-01 SW DIN (I2S Format) AC PPaUV R-chL-ch Frame R-ch Frame SWAP L-ch Frame R-ch Enable LOW Disable L-ch Frame S/PDIF Output Control Bit DOUTS P: Preamble A: Aux U: User Bits C: Channel Status SW: Audio Sample Word V: Validity Bit Pa: Parity Bit AC PPaUV 32/fS Frame PCM3052A SLES160 NOVEMBER 2005 Each bit after the audio sample word is assigned in the PCM3052A as follows. Validity bit: Writable through serial control port User data: Fixed to Channel status [0]: Fixed to (consumer use) Channel status [1]: Writable through serial control port (audio sample word type) Channel status [2]: Writable through serial control port (copyright flag) Channel status [3:5]: Writable through serial control port (additional format information) Channel status [6:7]: Fixed to (mode Channel status [8:15]: Writable through serial control port (category code) Channel status [16:19]: Fixed to 0000 (source number) Channel status [20:23]: Fixed to 0000 (channel number) Channel status [24:27]: Writable through serial control port (sampling frequency) Channel status [28:29]: Writable through serial control port (clock accuracy) Channel status [30:31]: Fixed to Channel status [32:35]: Writable through serial control port (word length) Channel status [36:191]: Fixed to all Parity bit: Even parity for preceding data from preamble to channel status bit S/PDIF output timing is shown in Figure The S/PDIF block starts with a preamble after 32/f S from the frame where S/PDIF output control bit becomes HIGH. The behavior of DOUTS for power-on reset, external reset, and loss of synchronization is shown in Figure Figure and Figure respectively. Figure 51. S/PDIF Output Timing

www.ti.com SERIAL CONTROL PORT FOR MODE CONTROL Slave Address Packet Protocol SDA SCL St Start 1−7 8 1−8 9 1−8 9 9 Sp Stop Slave Address ACK DATA ACK DATA ACK ACK ConditionCondition R/W Write Operation Transmitter M M M S M S M S S M Data Type St Slave Address W ACK DATA ACK DATA ACK ACK Sp R/W: Read Operation if 1; Otherwise, Write Operation ACK: Acknowledgement of a Byte if 0 DATA: 8 Bits (Byte) NACK: Not Acknowledgement of a bite if 1 T0049-04 M: Master Device S: Slave Device St: Start Condition W : Write Sp: Stop Condition PCM3052A SLES160 NOVEMBER 2005 The several built-in functions of the PCM3052A can be controlled through the I C format serial-control port, SDA (pin 18) and SCL (pin 19). The PCM3052A supports the I C serial bus and the data transmission protocol for standard mode as a slave device. This protocol is explained in I C specification 2.0. Serial control is available even during the power-down state and without a system clock, except when the MRST bit or I2CEN (pin 21) LOW. MSB LSB ADR W The PCM3052A has seven bits for its own slave address. The first six bits (MSBs) of the slave address are factory preset to 100011. The next bit of the address byte is the device select bit which can be user-defined by ADR (pin 20). A maximum of two PCM3052As can be connected on the same bus at one time. Each PCM3052A responds when it receives its own slave address. A master device must control packet protocol, which consists of start condition, slave address with read/write bit, data if write or acknowledgement if read, and stop condition. The PCM3052A supports slave receiver function. Figure 52. Basic I C Framework

www.ti.com Write Operation R0002-03 M: Master Device S: Slave Device St: Start Condition ACK: Acknowledge W : Write Sp: Stop Condition Transmitter M M M S Data Type St Slave Address W ACK M Reg Address M Write Data 1 S ACK S ACK M Sp M Write Data 2 S ACK S ACK Serial Control Enable/Disable T0100-01 0 µs (min) 1 µs (min) Don't Care EnableDisableI2CEN SDA/SCL HIGH Fixed Don't CareADR HIGH or LOW PCM3052A SLES160 NOVEMBER 2005 The PCM3052A supports receiver function. A master can write to any PCM3052A registers using single or multiple accesses. The master sends a PCM3052A slave address with a write bit, a register address, and the data. If multiple access is required, the address is that of the starting register, followed by the data to be transferred. When the data are received properly, the index register is incremented by automatically. When the index register reaches 50h, the next value is 41h. When undefined registers are accessed, the PCM3052A does not send an acknowledgement. Figure is a diagram of the write operation. The register address and the write data are bits and MSB-first format. Figure 53. Framework for Write Operation The PCM3052A supports I C serial control enable/disable function by I2CEN (pin 21) to avoid an unstable start condition. When the I2CEN pin transitions from LOW to HIGH, both SDA (pin 18) and SCL (pin 19) must be HIGH stable and the ADR (pin 20) must be also stable. While I2CEN LOW, the write operation is disabled. A timing chart of I2CEN is shown in Figure Figure 54. I2CEN Timing Chart

www.ti.com TIMING DIAGRAM SDA SCL t(BUF) t(D-SU) t(D-HD) Start t(LOW) t(S-HD) t(SCL-F) t(SCL-R) t(HI) Repeated Start t(RS-SU) t(RS-HD) t(SDA-F) t(SDA-R) t(P-SU) Stop T0050-01 MODE CONTROL REGISTERS User-Programmable Mode Controls PCM3052A SLES160 NOVEMBER 2005 PARAMETER CONDITIONS MIN MAX UNIT f (SCL) SCL clock frequency Standard mode 100 kHz t (BUF) Bus free time between STOP and START condition Standard mode 4.7 µ s t (LOW) Low period of the SCL clock Standard mode 4.7 µ s t (HI) High period of the SCL clock Standard mode µ s t RS-SU Setup time for START/repeated START condition Standard mode 4.7 µ s t (S-HD) Hold time for START/repeated START condition Standard mode µ s t (RS-HD) t (D-SU) Data setup time Standard mode 250 ns t (D-HD) Data hold time Standard mode 900 ns t (SCL-R) Rise time of SCL signal Standard mode 0.1 C B 1000 ns t (SCL-R1) Rise time of SCL signal after a repeated START condition and after Standard mode 0.1 C B 1000 ns an acknowledge bit t (SCL-F) Fall time of SCL signal Standard mode 0.1 C B 1000 ns t (SDA-R) Rise time of SDA signal Standard mode 0.1 C B 1000 ns t (SDA-F) Fall time of SDA signal Standard mode 0.1 C B 1000 ns t (P-SU) Setup time for STOP condition Standard mode µ s C B Capacitive load for SDA and SCL line 400 pF V NH Noise margin at high level for each connected device (including Standard mode 0.2 V DD V hysteresis) Figure 55. Control Interface Timing The PCM3052A has several user programmable functions which are accessed via control registers. The registers are programmed using the I C serial control port, which was previously discussed in this data sheet. Table lists the available mode control functions, along with their reset default conditions and associated register addresses. The register map is shown in Table

www.ti.com PCM3052A SLES160 NOVEMBER 2005 Table User-Programmable Mode Controls FUNCTION RESET DEFAULT REGISTER BIT(S) Digital attenuation control, dB to dB in 0.5-dB dB, no attenuation and AT1[7:0], AT2[7:0] steps (DAC) Mode control register reset (ADC and DAC) Normal operation MRST System reset (ADC and DAC) Normal operation SRST ADC power-save control (ADC) Normal operation ADPSV DAC Power Save Control (DAC) Normal operation DAPSV Soft-mute control (DAC) Mute disabled MUT[2:1] Oversampling rate control (DAC) 64-f S oversampling OVR1 De-emphasis function control (DAC) De-emphasis disabled DM12 De-emphasis sampling rate selection (DAC) kHz DMF[1:0] Digital filter rolloff control (DAC) Sharp rolloff FLT0 Output phase select (DAC) Normal DREV Multiplexer input channel control (ADC) LINE IN AML PGA gain control (ADC) dB PG[4:0] HPF bypass control (ADC) HPF enabled BYP DAC output control (DAC) Disabled DACMSK Additional format information (DIT) Two audio channels without pre-emphasis AFI[5:3] Copyright flag (DIT) Asserted COPY Audio sample word type (DIT) PCM AUDIO DIT output control (DIT) Disable DITMSK Category code (DIT) General CAT[15:8] Clock accuracy (DIT) Level II CLK[29:28] Sampling frequency (DIT) 44.1kHz SF[27:24] Validity bit for L-channel (DIT) Valid VALIDL Validity bit for R-channel (DIT) Valid VALIDR S/PDIF output control (DIT) Disabled SPDIF Word Length (DIT) bits WL[35:32] Table Register Map REGISTER ADDRESS DATA IDX REGIS- B15 B14 B13 B12 B11 B10 (B8 B14) TER 41h AT17 AT16 AT15 AT14 AT13 AT12 AT11 AT10 42h AT27 AT26 AT25 AT24 AT23 AT22 AT21 AT20 43h MRST SRST ADPSV DAPSV RSV (1) RSV (1) RSV (1) RSV (1) 44h RSV (1) OVR1 RSV (1) RSV (1) RSV (1) RSV (1) MUT2 MUT1 45h RSV (1) DMF1 DMF0 DM12 RSV (1) RSV (1) RSV (1) RSV (1) 46h RSV (1) RSV (1) FLT0 RSV (1) RSV (1) RSV (1) RSV (1) 47h RSV (1) RSV (1) RSV (1) RSV (1) RSV (1) RSV (1) RSV (1) DREV 48h RSV (1) RSV (1) AML PG4 PG3 PG2 PG1 PG0 4Bh RSV (1) RSV (1) RSV (1) RSV (1) BYP RSV (1) RSV (1) 4Dh DACMSK RSV (1) AFI5 AFI4 AFI3 COPY AUDIO DITMSK 4Eh CAT15 CAT14 CAT13 CAT12 CAT11 CAT10 CAT9 CAT8 4Fh RSV (1) RSV (1) CLK29 CLK28 SF27 SF26 SF25 SF24 50h VALIDL VALIDR SPDIF RSV (1) WL35 WL34 WL33 WL32 (1) RSV means reserved for test operation or future extension, and these bits should be set during regular operation. Do not write any values in other addresses than those listed in the table.

www.ti.com REGISTER DEFINITIONS ATx[7:0]: Digital Attenuation Level Setting (DAC) MRST: Mode Control Register Reset (ADC and DAC) SRST: System Reset (ADC and DAC) PCM3052A SLES160 NOVEMBER 2005 B15 B14 B13 B12 B11 B10 REGISTER AT17 AT16 AT15 AT14 AT13 AT12 AT11 AT10 REGISTER AT27 AT26 AT25 AT24 AT23 AT22 AT21 AT20 Where x or corresponding to the DAC output V OUT L and V OUT R 2). Default value: 1111 1111b ATX[7:0] DECIMAL VALUE ATTENUATION LEVEL SETTING 1111 1111b 255 dB, No Attenuation. (default) 1111 1110b 254 0.5 dB 1111 1101b 253 1.0 dB 1000 0011b 131 62.0 dB 1000 0010b 130 62.5 dB 1000 0001b 129 63.0 dB 1000 0000b 128 Mute 0000 0000b Mute Each DAC channel OUT L and V OUT includes a digital attenuation function. The attenuation level can be set from dB to dB in 0.5-dB steps, and also can be set to infinite attenuation (mute). The attenuation level change from current value to target value is performed by incrementing or decrementing by one small step size for every 1/f S time interval during 2048/f S The small step size is determined automatically so that it can provide a transition in attenuation level with a characteristic S-shaped curve from the current value to the target value. While the attenuation level change sequence is in progress for 2048/f S processing of the attenuation level change for any new command is ignored, and the new command is overwritten into command buffer. The last command for an attenuation level change is performed after present attenuation level change sequence is finished. The attenuation data for each channel can be set individually. The attenuation level can be calculated using the following formula: Attenuation level (dB) 0.5 (ATx[7:0] DEC 255) where ATx[7:0] DEC through 255. For ATx[7:0] DEC through 128, attenuation is set to infinite attenuation. The preceding table shows attenuation levels for various settings. B15 B14 B13 B12 B11 B10 REGISTER MRST SRST ADPSV DAPSV RSV RSV RSV RSV Default value: MRST Set default value MRST Normal operation (default) The MRST bit controls mode control register reset. Pop-noise may be generated. Default value:

www.ti.com ADPSV: ADC Power-Save Control (ADC) DAPSV: DAC Power-Save Control (DAC) OVR1: Oversampling Rate Control (DAC) MUTx: Soft-Mute Control (DAC) PCM3052A SLES160 NOVEMBER 2005 SRST Re-synchronization SRST Normal operation (default) The SRST bit controls system reset. The PCM3052A does not go into power-down state. The mode control register is not reset by this control. Also pop-noise may be generated. Default value: ADPSV Normal operation (default) ADPSV Power-save mode The ADPSV bit controls ADC power-save mode. In power-save mode, ADC goes into power-down state, the data in ADC are reset, and DOUT is forced into ZERO immediately. I C control is enabled. Default value: DAPSV Normal operation (default) DAPSV Power-save mode The DAPSV bit controls the DAC power-save mode. In the power-save mode, the DAC output is faded out and DAC goes into the power-down state. I C control is enabled. A waiting time of more than 2100/f S from power-save-mode assertion is required for the release of the power-save mode. DIT function is available if SPDIF bit even though DAPSV B15 B14 B13 B12 B11 B10 REGISTER RSV OVR1 RSV RSV RSV RSV MUT2 MUT1 Default value: OVR1 oversampling (default) OVR1 128 oversampling The OVR1 bit is used to control the oversampling rate of the delta-sigma D/A converters. To write over this register during normal operation may generate noise. where, x or corresponding to the DAC output V OUT L and V OUT R 2). Default value: MUTx Mute disabled (default) MUTx Mute enabled The mute bits, MUT1 and MUT2, are used to enable or disable the soft-mute function for the corresponding DAC outputs, V OUT L and V OUT The soft-mute function is incorporated into the digital attenuators. When mute is disabled (MUTx 0), the attenuator and DAC operate normally. When mute is enabled by setting MUTx the digital attenuator for the corresponding output is decreased from the current setting to infinite attenuation, one attenuator step (0.5 dB) for every 8/f S seconds. This provides pop-free muting of the DAC output. By setting MUTx the attenuator is increased one step for every 8/f S seconds to the previously programmed attenuation level.

www.ti.com DMF[1:0]: Sampling Frequency Selection for the De-Emphasis Function (DAC) DM12: Digital De-Emphasis Function Control (DAC) FLT0: Digital Filter Rolloff Control (DAC) DREV: Output Phase Select (DAC) PCM3052A SLES160 NOVEMBER 2005 B15 B14 B13 B12 B11 B10 REGISTER RSV DMF1 DMF0 DM12 RSV RSV RSV RSV Default value: DMF[1:0] DE-EMPHASIS SAMPLING RATE SELECTION 44.1 kHz kHz (default) kHz Reserved The DMF[1:0] bits are used to select the sampling frequency used for the digital de-emphasis function when it is enabled. Default value: DM12 De-emphasis disabled (default) DM12 De-emphasis enabled The DM12 bit is used to enable or disable the digital de-emphasis function. See the plots shown in the Typical Performance Curves section of this data sheet. B15 B14 B13 B12 B11 B10 REGISTER RSV RSV FLT0 RSV RSV RSV RSV Default value: FLT0 Sharp rolloff (default) FLT0 Slow rolloff The FLT0 bit allows the user to select the digital filter rolloff that is best suited to their application. Two filter rolloff selections are available: Sharp and Slow. The filter responses for these selections are shown in the Typical Performance Curves section of this data sheet. B15 B14 B13 B12 B11 B10 REGISTER RSV RSV RSV RSV RSV RSV RSV DREV Default value: DREV Normal output (default) DREV Inverted output The DREV bit is used to control the output analog signal phase control.

www.ti.com AML: Multiplexer Input Channel Selection (ADC) PG[4:0]: PGA Gain Selection (ADC) BYP: HPF Bypass Control (ADC) PCM3052A SLES160 NOVEMBER 2005 B15 B14 B13 B12 B11 B10 REGISTER RSV RSV AML PG4 PG3 PG2 PG1 PG0 Default value: AML MULTIPLEXER INPUT CHANNEL SELECTION Line (default) Microphone The AML bit selects the input channel of multiplexer. Default value: 0100 dB) PG[4:0] PGA Gain Selection PG[4:0] PGA Gain Selection 11111 Digital mute 01111 dB 11110 Digital mute 01110 dB 11101 Digital mute 01101 dB 11100 dB 01100 dB 11011 dB 01011 dB 11010 dB 01010 dB 11001 dB 01001 dB 11000 dB 01000 dB 10111 dB 00111 dB 10110 dB 00110 dB 10101 dB 00101 dB 10100 dB 00100 dB (default) 10011 dB 00011 Digital mute 10010 dB 00010 Digital mute 10001 dB 00001 Digital mute 10000 dB 00000 Digital mute The PG[4:0] bits control the gain of PGA for adjusting the signal level for ADC. B15 B14 B13 B12 B11 B10 REGISTER RSV RSV RSV RSV BYP RSV RSV Default value: BYP Normal output, HPF enable (default) BYP Bypass output, HPF disable The BYP bit controls HPF function; dc components of input and dc offset are converted in bypass mode.

www.ti.com DACMSK: DAC Output Control (DAC) AFI[5:3]: Additional Format Information (DIT) COPY: Copyright Flag (DIT) AUDIO: Audio Sample Word Type (DIT) DITMSK: DIT Output Control (DIT) PCM3052A SLES160 NOVEMBER 2005 B15 B14 B13 B12 B11 B10 REGISTER DACMSK RSV AFI5 AFI4 AFI3 COPY AUDIO DITMSK Default value: DACMSK Mask disable (default) DACMSK Mask DIN to BPZ level The DACMSK bit is used to mask DIN to BPZ level. The analog outputs from DAC is forced to BPZ level immediately. Larger noise may be generated by this control. Default value: 000 audio channels without pre-emphasis) The AFI[5:3] bits control bits[5:3] of channel status bits in compliance with IEC958. Default value: (Asserted) The COPY bit controls bit[2] of channel status bits in compliance with IEC958. Default value: (PCM) The AUDIO bit controls bit[1] of channel status bits in compliance with IEC958. Default value: DITMSK Mask disable (default) DITMSK Force DOUTS to encoded ZERO status The DITMSK bit forces only aux and audio sample words on DOUTS to encoded ZERO status. As for validity and channel status bits, the values in the register are output.

www.ti.com CAT[15:8]: Category Code (DIT) CLK[29:28]: Clock Accuracy (DIT) SF[27:24]: Sampling Frequency (DIT) VALIDL: Validity Bit for L-channel (DIT) VALIDR: Validity Bit for R-channel (DIT) SPDIF: S/PDIF Output Control (DIT) WL[35:32]: Word Length (DIT) PCM3052A SLES160 NOVEMBER 2005 B15 B14 B13 B12 B11 B10 REGISTER CAT15 CAT14 CAT13 CAT12 CAT11 CAT10 CAT9 CAT8 Default value: 0000 0000 (general) The CAT[15:8] bits control bits[15:8] of channel status bits in compliance with IEC958. B15 B14 B13 B12 B11 B10 REGISTER RSV RSV CLK29 CLK28 SF27 SF26 SF25 SF24 Default value: (level II) The CLK[29:28] bits control bits[29:28] of channel status bits in compliance with IEC958. Default value: 0000 (44.1 kHz) The SF[27:24] bits control bits[27:24] of channel status bits in compliance with IEC958. B15 B14 B13 B12 B11 B10 REGISTER VALIDL VALIDR SPDIF RSV WL35 WL34 WL33 WL32 Default value: (valid) The VALIDL bit controls the validity bit for L-channel in compliance with IEC958. Default value: (valid) The VALIDR bit controls validity bit for R-channel in compliance with IEC958. Default value: SPDIF DOUTS disabled (default) SPDIF DOUTS enabled The SPDIF bit controls output from DOUTS pin. In case of default, DOUTS always becomes LOW status. Default value: 0001 (24 bits) The WL[35:32] bits control bits[35:32] of channel status bits and the actual data word length of audio sample word including auxiliary 4-bits from DOUTS pin in compliance with IEC958. If the WL[35:32] bits indicate bits, the actual data word length of audio sample word is limited to bits even though data input on DIN pin is 24-bits, for example.

www.ti.com TYPICAL CIRCUIT CONNECTION VCOM MBIAS MINM MINP AGND3 VCC3 REFO VDD DGND DOUTS DOUT DIN BCK LRCK PCM3052A ATEST VINL L/M VREF1 VREF2 VINR VCC1 AGND1 PDWN V OUTL VOUTR VCC2 AGND2 I2CEN ADR SCL SDA SCKI Post LPF + C13 + C14 + C2 Line Out Control

5 VGND

+C15 R1 Mic In 3.3 V System Clock and Audio Interface +C12 +C6 +C5 +C11 Line In S0126-01 PCM3052A SLES160 NOVEMBER 2005 Figure illustrates typical circuit connection. NOTE: C C 0.1- µ F ceramic and 10- µ F electrolytic capacitors typical, depending on power supply quality and pattern layout. C C 0.1- µ F ceramic and 10- µ F electrolytic capacitors are recommended. C C µ F non-polar electrolytic capacitors are recommended, which give 27-Hz cutoff frequency. C C 0.22- µ F electrolytic capacitors are recommended, which give 5-Hz cutoff frequency at PGA gain dB. C C 2.2- µ F electrolytic capacitors are typical. C 10- µ F electrolytic capacitor is recommended. R R 1-k Ω typical is recommended. Figure 56. Typical Application Diagram

www.ti.com DESIGN AND LAYOUT CONSIDERATIONS IN APPLICATION Power Supply Pins CC V CC V CC V DD Grounding (AGND1, AGND2, AGND3, DGND) V IN V IN R Pins V REF V REF V COM Pins MBIAS Pin REFO Pin MINM, MINP Pins System Clock External Mute Control PCM3052A SLES160 NOVEMBER 2005 The digital and analog power supply lines to the PCM3052A should be bypassed to the corresponding ground pins with 0.1- µ F ceramic and 10- µ F electrolytic capacitors as close to the pins as possible to maximize the dynamic performance of the ADC and DAC. Although the PCM3052A has four power lines to maximize the potential of dynamic performance, using one common 5-V power supply for V CC V CC and V CC A 3.3-V power supply for V DD which is generated from the 5-V power supply for V CC V CC and V CC is recommended to avoid unexpected power supply trouble like latch-up or power supply sequencing problems. To maximize the dynamic performance of the PCM3052A, the analog and digital grounds are not connected internally. These points should have low impedance to avoid digital noise and signal components feeding back into the analog ground. They should be connected directly to each other under the parts to reduce the potential of noise problems. A 0.22- µ F electrolytic capacitor is recommended as an ac-coupling capacitor, which gives a 5-Hz cutoff frequency at PGA gain dB. If higher full-scale input voltage is required, it can be adjusted by adding only one series resistor to V IN X pins. Both 0.1- µ F ceramic and 10- µ F electrolytic capacitors are recommended from V REF and V REF to AGND1, and from V COM to AGND2, to ensure low source impedance of the ADC and DAC references. These capacitors should be located as close as possible to the V REF V REF and V COM pins to reduce dynamic errors on the ADC and DAC references. A 10- µ F electrolytic capacitor is recommended between MBIAS and AGND3 to ensure low noise on MBIAS. Both 0.1- µ F ceramic and 10- µ F electrolytic capacitors are recommended between REFO and AGND1 to ensure low noise on REFO. A µ F non-polar electrolytic capacitor which gives a 27-Hz cutoff frequency, is recommended as coupling capacitor. The quality of SCKI can influence dynamic performance, as the PCM3052A (both of DAC and ADC) operates based on SCKI. Therefore, it might be necessary to consider the jitter, duty, rise and fall time, etc. of the system clock. For power-down ON/OFF control without click noise which is generated by DAC output dc level changes, the external mute control is generally required. The control sequence, which is described as External Mute ON, CODEC Power Down ON, SCKI stop and resume if necessary, CODEC Power Down OFF, and External Mute OFF is recommended.

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) PCM3052ARTF ACTIVE QFN RTF 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCM3052ARTFG4 ACTIVE QFN RTF 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCM3052ARTFR ACTIVE QFN RTF 32 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCM3052ARTFRG4 ACTIVE QFN RTF 32 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2006 Addendum-Page 1

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