PCM3010DB

PCM3010 TI | Alldatasheet

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SLES055 – NOVEMBER 2002 24-BIT STEREO AUDIO CODEC WITH 96-kHz ADC, 192-kHz DAC, AND SINGLE-ENDED ANALOG INPUT/OUTPUT 1www.ti.com

FEATURES

/C006824-Bit Delta-Sigma ADC and DAC /C0068Stereo ADC: – Single-Ended Voltage Input: 3 Vp-p – Antialiasing Filter Included – 1/128, 1/64 Decimation Filter: – Pass-Band Ripple: ±0.05 dB – Stop-Band Attenuation: –65 dB – On-Chip High-Pass Filter: 0.84 Hz at f S = 44.1 kHz – High Performance: – THD+N: –95 dB (Typical) – SNR: 100 dB (Typical) – Dynamic Range: 102 dB (Typical) /C0068Stereo DAC: – Single-Ended Voltage Output: 3 Vp-p – Analog Low-Pass Filter Included – ×8 Oversampling Digital Filter: – Pass-Band Ripple: ±0.03 dB – Stop-Band Attenuation: –50 dB – High Performance: – THD+N: –96 dB (Typical) – SNR: 104 dB (Typical) – Dynamic Range: 104 dB (Typical) /C0068Multiple Functions: – Digital De-Emphasis: 32 kHz, 44.1 kHz, 48 kHz – Power Down: ADC/DAC Simultaneous – 16-, 24-Bit Audio Data Formats /C0068Sampling Rate: 16–96 kHz (ADC), 16–192 kHz (DAC) /C0068System Clock: 128 fS, 192 fS, 256 fS, 384 fS, 512 fS, 768 fS /C0068Dual Power Supplies: 5 V for Analog and 3.3 V for Digital /C0068Package: 24-Pin SSOP, Lead-Free Product

APPLICATIONS

/C0068DVD Recorders /C0068CD Recorders /C0068PC Audio /C0068Sound Control System

DESCRIPTION

The PCM3010 is a low-cost single-chip 24-, 16-bit stereo audio codec (ADC and DAC) with single-ended analog voltage input and output. Both the analog-to-digital converters (ADCs) and digital-to- analog converters (DACs) employ delta-sigma modulation with 64-times oversampling. The ADCs include a digital decimation filter with a high-pass filter, and the DACs include an 8-times-oversampling digital interpolation filter. The DACs also include a digital de-emphasis function. The PCM3010 accepts four different audio data formats for the ADC and DAC. The PCM3010 provides a power-down mode, which works on the ADC and DAC simultaneously. The PCM3010 is suitable for a wide variety of cost-sensitive consumer applications where good performance is required. The PCM3010 is fabricated using a highly advanced CMOS process and is available in a small 24-pin SSOP package. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  2002, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SLES055 – NOVEMBER 2002 2 www.ti.com VINL VINR VREF 1 VREF 2 VCC 1 AGND1 FMT0 FMT1 TEST LRCK BCK DIN VCOM VOUT L VOUT R VCC 2 AGND2 DEMP0 DEMP1 PDWN SCKI V DD DGND DOUT DB PACKAGE (TOP VIEW) PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE PACKAGE CODE OPERATION TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA PCM3010DB 24 lead SSOP 24DB 25°Ct o8 5°C PCM3010 PCM3010DB Tube PCM3010DB 24-lead SSOP 24DB –25°C to 85°C PCM3010 PCM3010DBR Tape and reel

Figure 1. PCM3010 Block Diagram

SLES055 – NOVEMBER 2002 4 www.ti.com analog front-end (right-channel) VINL VREF 1 VREF 2 10 µF +1 µF 20 kΩ Delta-Sigma Modulator (+) (–) Reference 0.5 VCC 10.1 µF 10 µF + 0.1 µF

SLES055 – NOVEMBER 2002 5www.ti.com Terminal Functions TERMINAL I/O DESCRIPTIONSNAME NO. I/O DESCRIPTIONS AGND1 6 – ADC analog ground AGND2 20 – DAC analog ground BCK 11 I Audio data bit clock input‡ DEMP1 18 I De-emphasis select input, 1† DEMP0 19 I De-emphasis select input, 0† DGND 14 – Digital ground DIN 12 I Audio data digital input‡ DOUT 13 O Audio data digital output FMT0 7 I Audio data format select input, 0† FMT1 8 I Audio data format select input, 1† LRCK 10 I Audio data latch enable input‡ PDWN 17 I ADC and DAC power-down control input, active LOW† SCKI 16 I System clock input‡ TEST 9 I Test control, must be open or connected to DGND† VCC 1 5 – ADC analog power supply, 5 V VCC 2 21 – DAC analog power supply, 5 V VCOM 24 – DAC common voltage decoupling (= 0.5 VCC 2) VDD 15 – Digital power supply, 3.3 V VINL 1 I ADC analog input, L-channel VINR 2 I ADC analog input, R-channel VOUT L 23 O DAC analog output, L-channel VOUT R 22 O DAC analog output, R-channel VREF 1 3 – ADC reference voltage decoupling, 1 (= 0.5 VCC 1) VREF 2 4 – ADC reference voltage decoupling, 2 † Schimtt-trigger input with 50-kΩ typical internal pulldown resistor, 5-V tolerant. ‡ Schimtt-trigger input, 5-V tolerant.

SLES055 – NOVEMBER 2002 6 www.ti.com absolute maximum ratings over operating free-air temperature (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. electrical characteristics, all specifications at TA = 25°C, VCC 1 = VCC 2 = 5 V, VDD = 3.3 V, fS = 44.1 kHz, SCKI = 384 fS, 24-bit data (unless otherwise noted) PARAMETER TEST CONDITIONS PCM3010DB UNITPARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUT/OUTPUT DATA FORMAT Audio data interface format Left-justified, I2S, right-justified Audio data bit length 16, 24 Bits Audio data format MSB-first, 2s complement f Sampling frequency, ADC 16 44.1 96 kHz fS Sampling frequency, DAC 16 44.1 192 kHz System clock frequency 128 fS, 192 fS, 256 fS, 384 fS, 512 fS, 768 fS 4 50 MHz INPUT LOGIC VIH Input logic level (see Notes 1 and 2) 2.0 5.5 VDC VIL Input logic level (see Notes 1 and 2) 0.8 VDC IIH Input logic current (see Note 2) VIN = VDD ±10 µA IIL Input logic current (see Note 2) VIN = 0 V ±10 µA IIH Input logic current (see Note 1) VIN = VDD 65 100 µA IIL Input logic current (see Note 1) VIN = 0 V ±10 µA OUTPUT LOGIC VOH Output logic level (see Note 3) IOUT = –4 mA 2.4 VDCVOL Output logic level (see Note 3) IOUT = 4 mA 0.4 VDC ADC CHARACTERISTICS Resolution 24 Bits NOTES: 1. Pins 7, 8, 9, 17, 18, 19: PDWN , TEST, FMT0, FMT1, DEMP0, DEMP1 (Schmitt-trigger input with 50-kΩ typical internal pulldown resistor, 5-V tolerant). 2. Pins 10–12, 16: LRCK, BCK, DIN, SCKI (Schmitt-trigger input, 5-V tolerant). 3. Pin 13: DOUT.

SLES055 – NOVEMBER 2002 7www.ti.com electrical characteristics, all specifications at TA = 25°C, VCC 1 = VCC 2 = 5 V, VDD = 3.3 V, fS = 44.1 kHz, SCKI = 384 fS, 24-bit data (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS PCM3010DB UNITPARAMETER TEST CONDITIONS MIN TYP MAX UNIT ACCURACY Gain mismatch, channel-to-channel1 kHz, full-scale input ±1 ±6 % of FSR Gain error 1 kHz, full-scale input ±2 ±6 % of FSR DYNAMIC PERFORMANCE (see Note 4) THD N V 05d B fS = 44.1 kHz –95 –86 dBTHD+N VIN = –0.5 dB fS = 96 kHz –92 dB THD+N V 60 dB fS = 44.1 kHz –39 dBTHD+N VIN = –60 dB fS = 96 kHz –40 dB Dynamic range fS = 44.1 kHz, A-weighted 97 102 dBDynamic range fS = 96 kHz, A-weighted 102 dB S/N ratio fS = 44.1 kHz, A-weighted 95 100 dBS/N ratio fS = 96 kHz, A-weighted 102 dB Channel separation fS = 44.1 kHz 93 98 dBChannel separation fS = 96 kHz 100 dB ANALOG INPUT Input voltage 60% of VCC 1 Vp–p Center voltage 50% of VCC 1 V Input impedance 20 kΩ Anti-aliasing filter frequency response–3 dB 300 kHz DIGITAL FILTER PERFORMANCE Pass band 0.454 fS Hz Stop band 0.583 fS Hz Pass-band ripple ±0.05 dB Stop-band attenuation –65 dB Delay time 17.4/fS sec HPF frequency response –3 dB 0.019 fS mHz DAC CHARACTERISTICS Resolution 24 Bits DC ACCURACY Gain mismatch, channel-to-channel ±1.0 ±4.0 % of FSR Gain error ±2.0 ±6.0 % of FSR Bipolar zero error ±1.0 % of FSR DYNAMIC PERFORMANCE (see Note 5) fS = 44.1 kHz –96 –88 THD+N, VOUT = 0 dB fS = 96 kHz –97 dBTHD+N, VOUT 0 dB fS = 192 kHz –97 dB NOTES: 4. f IN = 1 kHz, using System Two audio measurement system, RMS mode with 20-kHz LPF, 400-Hz HPF in calculation. 5. fOUT = 1 kHz, using System Two audio measurement system, RMS mode with 20-kHz LPF, 400-Hz HPF. System Two is a trademark of Audio Precision, Inc. All other trademarks are the property of their respective owners.

SLES055 – NOVEMBER 2002 8 www.ti.com electrical characteristics, all specifications at TA = 25°C, VCC 1 = VCC 2 = 5 V, VDD = 3.3 V, fS = 44.1 kHz, SCKI = 384 fS, 24-bit data (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS PCM3010DB UNITPARAMETER TEST CONDITIONS MIN TYP MAX UNIT DYNAMIC PERFORMANCE (see Note 5) (Continued) fS = 44.1 kHz –42 THD+N VOUT = –60 dB fS = 96 kHz –43 dBTHD+N VOUT 60 dB fS = 192 kHz –43 dB fS = 44.1 kHz, EIAJ, A-weighted 98 104 Dynamic range fS = 96 kHz, EIAJ, A-weighted 105 dBDynamic range fS = 192 kHz, EIAJ, A-weighted 105 dB fS = 44.1 kHz, EIAJ, A-weighted 98 104 S/N ratio fS = 96 kHz, EIAJ, A-weighted 105 dBS/N ratio fS = 192 kHz, EIAJ, A-weighted 105 dB fS = 44.1 kHz 95 102 Channel separation fS = 96 kHz 102 dBChannel se aration fS = 192 kHz 103 dB ANALOG OUTPUT Output voltage 60% of VCC 2 Vp-p Center voltage 50% of VCC 2 V Load impedance AC coupling 5 kΩ LPF frequency response f = 20 kHz –0.03 dBLPF frequency response f = 44 kHz –0.20 dB DIGITAL FILTER PERFORMANCE Pass band ±0.03 dB 0.454 fS Hz Stop band 0.546 fS Hz Pass-band ripple ±0.03 dB Stop-band attenuation 0.546 fS –50 dB Delay time 20/fS sec De-emphasis error ±0.1 dB POWER SUPPLY REQUIREMENTS VCC 1 VCC 2 Voltage range 4.5 5.0 5.5 VDC VDD Voltage range 3.0 3.3 3.6 VDC ICC fS = 44.1 kHz 31 40ICC (ICC 1 + fS = 96 kHz 32 mA(ICC 1 + ICC 2) Supply current fS = 192 kHz 9 mA Supply current fS = 44.1 kHz 10 15 IDD fS = 96 kHz 20 mAIDD fS = 192 kHz 14 mA fS = 44.1 kHz 190 250 Power dissipation, operation fS = 96 kHz 230 mWPower dissi ation, o eration fS = 192 kHz 90 mW Power dissipation, power down (see Note 6) 1 mW TEMPERATURE RANGE Operating temperature –25 85 °C θJA Thermal resistance 24-pin SSOP 100 °C/W NOTES: 5. f OUT = 1 kHz, using System Two audio measurement system, RMS mode with 20-kHz LPF, 400-Hz HPF. 6. Halt SCKI, BCK, LRCK.

a 4th-order noise shaper. This section converts the oversampled input data to the 8-level delta-sigma format. has the advantage of improved stability and clock jitter over the typical one-bit (2-level) delta-sigma modulator. Figure 41. 8-Level Delta-Sigma Modulator Block Diagram

1024 SCKI

Figure 45. DAC Output and ADC Output for Power-On Reset Figure 46. DAC Output and ADC Output for External Reset (PDWN Pin)

FMT0 (pin 7) and FMT1 (pin 8), as shown in Table 2. Table 2. Audio Data Format Select following figures illustrate audio data input/output format and timing. Figure 47. Audio Data Input/Output Format

Figure 48. Audio Data Input/Output Format (Continued)

0.5 VDD

Figure 49. Audio Data Input/Output Timing of LRCK, BCK, and the system clock. resynchronization between the system clock, LRCK, and BCK is completed and then tDACDLY2 elapses. resynchronization between the system clock, LRCK, and BCK is completed, and then tADCDLY2 elapses. discontinuity in analog/digital output control does not occur.

SLES055 – NOVEMBER 2002 28 www.ti.com typical circuit connection The following figure illustrates typical circuit connection. VCC 1 20 AGND1 FMT0 FMT1 TEST LRCK BCK DIN AGND2 DOUT DEMP0 DEMP1 PDWN SCKI DGND VDD L-Ch IN Format 0 Clock De-emphasis 0 (See Note C) Control VINL 24 VINR VREF 1 VREF 2 VCOM VOUT L VOUT R VCC 2 (See Note B) + (See Note B) + (See Note A) + NOTES: A. 0.1 µF ceramic and 10 µF electrolytic capacitors typical, depending on power supply quality and pattern layout. B. 0.1 µF ceramic and 10 µF electrolytic capacitors are recommended. C. 1 µF electrolytic capacitor typical, gives 8-Hz cutoff frequency of input HPF in normal operation and gives settling time with 20 ms (1 µF × 20 kΩ ) time constant in power ON and power down OFF period. D. 10 µF electrolytic capacitor typical, gives 2-Hz cutoff frequency for 10-kΩ post-LPF input resistance in normal operation and gives settling time with 100 ms (10 µF × 10 kΩ ) time constant in power ON and power down OFF period. R-Ch IN 0 V 3.3 V 5 V Format 1 L/R Clock Data IN Bit Clock Control Data + (See Note B) (See Note D) (See Note D) (See Note A) (See Note C) Post LPF Post LPF De-emphasis 1 Power Down System Clock Clock Data OUT Data + (See Note A) design and layout considerations in application power supply pins (VCC 1, VCC 2, VDD ) The digital and analog power supply lines to the PCM3010 should be bypassed to the corresponding ground pins, with 0.1-µF ceramic and 10-µF electrolytic capacitors as close to the pins as possible to maximize the dynamic performance of the ADC and the DAC. Although the PCM3010 has three power lines to maximize the potential of dynamic performance, using one common 5-V power supply for VCC 1 and VCC 2 and a 3.3-V power supply, which is generated from the 5-V VCC 1 and VCC 2 power supply, for VDD . This power supply arrangement is recommended to avoid unexpected power supply trouble, like latch-up or power supply sequencing problems. grounding (AGND1, AGND2, DGND) To maximize the dynamic performance of the PCM3010, the analog and digital grounds are not connected internally. These points should have very low impedance to avoid digital noise feeding back into the analog ground. They should be connected directly to each other under the connected parts to reduce the potential for noise problems.

SLES055 – NOVEMBER 2002 29www.ti.com VIN pins A 1-µF electrolytic capacitor is recommended as an ac-coupling capacitor, which gives an 8-Hz cutoff frequency. If a higher full-scale input voltage is required, it can be adjusted by adding only one series resistor to each VIN pin. VREF 1, VREF 2 pins A 0.1-µF ceramic capacitor and a 10-µF electrolytic capacitor are recommended between VREF 1, VREF 2, and AGND1 to ensure low source impedance of the ADC references. These capacitors should be located as close as possible to the V REF 1 and VREF 2 pins and the AGND1 pin to reduce dynamic errors on the ADC references. VCOM pin A 0.1-µF ceramic capacitor and a 10-µF electrolytic capacitor are recommended between VCOM and AGND2 to ensure low source impedance of the DAC common voltage. These capacitors should be located as close as possible to the V COM pin to reduce dynamic errors on the DAC common voltage. system clock The quality of SCKI may influence dynamic performance, as the PCM3010 (both DAC and ADC) operates based on SCKI. Therefore, it may be necessary to consider the jitter, duty cycle, rise and fall time, etc., of the system clock. reset control If large capacitors (more than 22 µF) are used on V REF 1, VREF 2, and VCOM , external reset control by PDWN = LOW is required after the VREF 1, VREF 2, and VCOM transient response settles. external mute control To eliminate the clicking noise which is generated by DAC output dc level change during power-down ON/OFF control, external mute control is generally required. The recommended control sequence is: external mute ON, codec power down ON, SCKI stop and restart if necessary, codec power down OFF, and external mute OFF.

SLES055 – NOVEMBER 2002 30 www.ti.com MECHANICAL DATA DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 4040065 /E 12/01

28 PINS SHOWN

8,20 7,40 0,55 0,95 0,25 12,90 12,30 10,50 8,50 Seating Plane 9,907,90 10,50 9,90 0,38 5,60 5,00 0,22 A 2016 6,506,50 0,05 MIN 5,905,90 DIM A MAX A MIN PINS ** 2,00 MAX 6,90 7,50 0,65 M0,15 0°–/C02578° 0,10 0,09 0,25 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150

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