PCM3006T/2KG6

PCM3006_08 TI1 | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 30

Technical content

Features

a highly advanced Digital De-Emphasis CMOS process, and is available in a small 24-pin Power Down: ADC/DAC Independent TSSOP package. The PCM3006 is suitable for a wide variety of cost-sensitive consumer

applications

Rate: kHz to kHz good performance is required. System Clock: 256 f S 384 f S 512 f S Single 3-V Power Supply Small Package: 24-Lead TSSOP Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. System Two, Audio Precision are trademarks of Audio Precision, Inc. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright 2000 2004, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com ELECTRICAL CHARACTERISTICS PCM3006 SBAS089A OCTOBER 2000 REVISED OCTOBER 2004 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. All specifications at T A V DD V CC f S 44.1 kHz, SYSCLK 384 f S and 16-bit data, unless otherwise noted PCM3006T PARAMETER CONDITIONS UNITS MIN TYP MAX DIGITAL INPUT/OUTPUT Input Logic V IH (1) 0.7 V DD Input logic level VDC V IL (1) 0.3 V DD I IN (2) Input logic current µ A I IN (3) 100 Output Logic V OH (4) I OUT mA V DD 0.3 VDC Output logic level V OL (4) I OUT mA 0.3 CLOCK FREQUENCY f s Sampling frequency 44.1 kHz 256 f S 1.024 11.2896 12.288 System clock frequency 384 f S 1.536 16.9344 18.432 MHz 512 f S 2.048 22.5792 24.576 ADC CHARACTERISTICS Resolution Bits DC Accuracy Gain mismatch, channel-to-channel of FSR Gain error of FSR Gain drift ppm of FSR/ C Dynamic Performance (5) V IN 0.5 dB THD+N dB V IN dB Dynamic range A-weighted dB Signal-to-noise ratio A-weighted dB Channel separation dB Digital Filter Performance Pass band 0.454 f S Hz Stop band 0.583 f S Hz Pass-band ripple 0.05 dB Stop-band attenuation dB Delay time 17.4/f S s (1) Pins 10, 11, 15, 17, 18: PDAD PDDA SYSCLK, LRCIN, BCKIN, DIN, DEM1, DEM0 (Schmitt-trigger input with 100-k Ω typical internal pulldown resistor) (2) Pins 10, 11, 15: SYSCLK, LRCIN, BCKIN, DIN (Schmitt-trigger input) (3) Pins 17, 18: PDAD PDDA DEM1, DEM0 (Schmitt-trigger input, 100-k Ω typical internal pulldown resistor) (4) Pin 12: DOUT (5) f IN kHz, using System Two audio measurement system by Audio Precision rms mode with 20-kHz LPF, 400-Hz HPF used for performance calculation

www.ti.com PCM3006 SBAS089A OCTOBER 2000 REVISED OCTOBER 2004 ELECTRICAL CHARACTERISTICS (continued) All specifications at T A V DD V CC f S 44.1 kHz, SYSCLK 384 f S and 16-bit data, unless otherwise noted PCM3006T PARAMETER CONDITIONS UNITS MIN TYP MAX HPF frequency response dB 0.019 f S mHz Analog Input Voltage range 0.6 V CC Vp-p Center voltage 0.5 V CC VDC Input impedance k Ω Antialiasing filter frequency dB 150 kHz response DAC CHARACTERISTICS Resolution Bits DC Accuracy Gain mismatch, channel-to-channel of FSR Gain error of FSR Gain drift ppm of FSR/ C Bipolar zero error 2.5 of FSR Bipolar zero drift ppm of FSR/ C Dynamic Performance (6) V OUT dB (full scale) THD+N dB V OUT dB Dynamic range EIAJ, A-weighted dB Signal-to-noise ratio EIAJ, A-weighted dB Channel separation dB Digital Filter Performance Pass band 0.445 f S Hz Stop band 0.555 f S Hz Pass-band ripple 0.17 dB Stop-band attenuation dB Delay time 11.1/f S s Analog Output Voltage range 0.6 V CC Vp-p Center voltage 0.5 V CC VDC Load impedance AC coupling k Ω LPF frequency response f kHz 0.16 dB (6) f OUT kHz, using System Two audio measurement system by Audio Precision, rms mode with 20-kHz LPF, 400-Hz HPF used for performance calculation.

www.ti.com PCM3006 SBAS089A OCTOBER 2000 REVISED OCTOBER 2004 ELECTRICAL CHARACTERISTICS (continued) All specifications at T A V DD V CC f S 44.1 kHz, SYSCLK 384 f S and 16-bit data, unless otherwise noted PCM3006T PARAMETER CONDITIONS UNITS MIN TYP MAX POWER SUPPLY REQUIREMENTS C to C 2.7 3.6 V CC V DD Voltage range VDC C to C (7) 2.4 3.6 ADC/DAC operation, V CC V DD V ADC operation, V CC V DD mA V Supply current DAC operation, V CC V DD V ADC/DAC power down (8) µ A V CC V DD V ADC/DAC operation, V CC V DD V ADC operation, V CC V DD mW V Power dissipation DAC operation, V CC V DD V ADC/DAC power down (8) 150 µ W V CC V DD V TEMPERATURE RANGE T A Operation C T stg Storage 125 θ JA Thermal resistance 100 C/W (7) Applies for voltages between 2.4 V and 2.7 for C to and 256-f S /512-f S operation (384-f S not available) (8) SYSCLK, BCKIN, and LRCIN are stopped.

www.ti.com P0006-01 VCC1 VCC1 VINR VREF1 VREF2 VINL PDAD PDDA SYSCLK LRCIN BCKIN DOUT VCC2 NC AGND V COM VOUTR VOUTL DEM0 DEM1 NC DIN V DD DGND PCM3006 (TOP VIEW) NC = No Connection PCM3006 SBAS089A OCTOBER 2000 REVISED OCTOBER 2004 PIN CONFIGURATION PIN ASSIGNMENTS NAME PIN I/O

DESCRIPTION

I Bit clock input (1) DEM0 I De-emphasis control (1) (2) DEM1 I De-emphasis control (1) (2) DGND Digital ground DIN I Data input (1) DOUT O Data output LRCIN I Sample rate clock input s (1) NC 16, No connection PDAD I ADC power down, active LOW (1) (2) PDDA I DAC power down, active LOW (1) (2) SYSCLK I System clock input (1) V CC ADC analog power supply V CC DAC analog power supply V COM ADC/DAC common V DD Digital power supply V IN L I ADC analog input, Lch V IN R I ADC analog input, Rch V OUT L O DAC analog output, Lch V OUT R O DAC analog output, Rch V REF ADC reference, V REF ADC reference, (1) Schmitt-trigger input (2) With 100-k Ω typical internal pulldown resistor

www.ti.com ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS PCM3006 SBAS089A OCTOBER 2000 REVISED OCTOBER 2004 Supply voltage: V DD V CC V CC 0.3 V to 6.5 V Supply voltage differences 0.1 V GND voltage differences 0.1 V Digital input voltage 0.3 V to V DD 0.3 6.5 V Analog input voltage 0.3 to V CC V CC 0.3 6.5 V Power dissipation 300 mW Input current (any pins except supplies) mA Operating temperature C to C Storage temperature C to 125 C Lead temperature, soldering 260 s Package temperature (IR reflow, peak) 235 C over operating free-air temperature range MIN NOM MAX UNIT Analog supply voltage V CC V CC 2.7 3.6 V Digital supply voltage V DD 2.7 3.6 V Analog input voltage, full scale db) V CC V 1.8 Vp-p Digital input logic family CMOS Digital input clock frequency System clock 8.192 24.576 MHz Sampling clock kHz Analog output load resistance k Ω Analog output load capacitance pF Digital output load capacitance pF Operating free-air temperature, T A C PACKAGE/ORDERING INFORMATION PACKAGE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE QUANTITY CODE MARKING NUMBER MEDIA PCM3006T Rails 128 PCM3006T 24-pin TSSOP DCV PCM3006T PCM3006T/2K Tape and reel 2000

www.ti.com TYPICAL PERFORMANCE CURVES ADC SECTION −25 0 25 50 75 100 TA − Free-Air Temperature − ° C Dynamic Range − dB SNR SNR − Signal-to-Noise Ratio − dB G002 Dynamic Range 0.002 0.004 0.006 0.008 0.010 −25 0 25 50 75 100 TA − Free-Air Temperature − ° C THD+N − Total Harm. Dist. + Noise at −0.5 dB − % −0.5 dB −60 dB G001 THD+N − Total Harm. Dist. + Noise at −60 dB − % VCC − Supply Voltage − V Dynamic Range − dB SNR − Signal-to-Noise Ratio − dB G004 Dynamic Range SNR 0.002 0.004 0.006 0.008 0.010 VCC − Supply Voltage − V THD+N − Total Harm. Dist. + Noise at −0.5 dB − % THD+N − Total Harm. Dist. + Noise at −60 dB − % G003 −60 dB −0.5 dB PCM3006 SBAS089A OCTOBER 2000 REVISED OCTOBER 2004 All specifications at T A V CC V DD f S 44.1 kHz, f SYSCLK 384 f S and f SIGNAL kHz, unless otherwise noted THD+N DYNAMIC RANGE and SNR vs vs TEMPERATURE TEMPERATURE Figure Figure THD+N DYNAMIC RANGE and SNR vs vs SUPPLY VOLTAGE SUPPLY VOLTAGE Figure Figure NOTE: All characteristics at supply voltages from 2.4 V to 2.7 V are measured at SYSCLK 256 f S

www.ti.com Dynamic Range − dB SNR − Signal-to-Noise Ratio − dB G006 Dynamic Range SNR fS − Sampling Frequency − kHz 4832 44.1 0.002 0.004 0.006 0.008 0.010 fS − Sampling Frequency − kHz THD+N − Total Harm. Dist. + Noise at −0.5 dB − % G005 THD+N − Total Harm. Dist. + Noise at −60 dB − % 4832 44.1 −60 dB −0.5 dB DAC SECTION −25 0 25 50 75 100 TA − Free-Air Temperature − ° C Dynamic Range − dB SNR SNR − Signal-to-Noise Ratio − dB G008 Dynamic Range 0.002 0.004 0.006 0.008 0.010 −25 0 25 50 75 100 TA − Free-Air Temperature − ° C THD+N − Total Harm. Dist. + Noise at FS − % FS −60 dB G007 THD+N − Total Harm. Dist. + Noise at −60 dB − % PCM3006 SBAS089A OCTOBER 2000 REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES (continued) All specifications at T A V CC V DD f S 44.1 kHz, f SYSCLK 384 f S and f SIGNAL kHz, unless otherwise noted THD+N DYNAMIC RANGE and SNR vs vs SAMPLING FREQUENCY SAMPLING FREQUENCY Figure Figure THD+N DYNAMIC RANGE and SNR vs vs TEMPERATURE TEMPERATURE Figure Figure

www.ti.com VCC − Supply Voltage − V Dynamic Range − dB SNR − Signal-to-Noise Ratio − dB G010 Dynamic Range SNR 0.002 0.004 0.006 0.008 0.010 VCC − Supply Voltage − V THD+N − Total Harm. Dist. + Noise at FS − % THD+N − Total Harm. Dist. + Noise at −60 dB − % G009 −60 dB FS Dynamic Range − dB SNR − Signal-to-Noise Ratio − dB G012 SNR fS − Sampling Frequency − kHz 4832 44.1 256 fS, 512 fS 384 fS Dynamic Range 0.002 0.004 0.006 0.008 0.010 fS − Sampling Frequency − kHz THD+N − Total Harm. Dist. + Noise at FS − % G011 THD+N − Total Harm. Dist. + Noise at −60 dB − % 4832 44.1 384 fS 256 fS, 512 fS 384 fS FS −60 dB 256 fS, 512 fS PCM3006 SBAS089A OCTOBER 2000 REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES (continued) All specifications at T A V CC V DD f S 44.1 kHz, f SYSCLK 384 f S and f SIGNAL kHz, unless otherwise noted THD+N DYNAMIC RANGE and SNR vs vs SUPPLY VOLTAGE SUPPLY VOLTAGE Figure Figure 10. NOTE: All characteristics at supply voltages from 2.4 V to 2.7 V are measured at SYSCLK 256 f S THD+N DYNAMIC RANGE and SNR vs vs SAMPLING FREQUENCY and SYSTEM CLOCK SAMPLING FREQUENCY and SYSTEM CLOCK Figure 11. Figure 12.

www.ti.com TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (ADCs) DECIMATION FILTER Normalized Frequency [× fS Hz] −200 −150 −100 −50 0 8 16 24 32 Amplitude − dB G013 Normalized Frequency [× fS Hz] −100 −80 −60 −40 −20 Amplitude − dB G014 Normalized Frequency [× fS Hz] −1.0 −0.8 −0.6 −0.4 −0.2 0.0 0.2 Amplitude − dB G015 Normalized Frequency [× fS Hz] −10 Amplitude − dB G016 −4.13 dB at 0.5 fS PCM3006 SBAS089A OCTOBER 2000 REVISED OCTOBER 2004 All specifications at T A V CC V DD f S 44.1 kHz, and f SYSCLK 384 f S unless otherwise noted OVERALL CHARACTERISTICS STOP-BAND ATTENUATION CHARACTERISTICS Figure 13. Figure 14. PASS-BAND RIPPLE CHARACTERISTICS TRANSITION BAND CHARACTERISTICS Figure 15. Figure 16.

www.ti.com HIGH-PASS FILTER Normalized Frequency [× fS/1000 Hz] −1.0 −0.8 −0.6 −0.4 −0.2 0.0 0.2 0 1 2 3 4 Amplitude − dB G018 Normalized Frequency [× fS/1000 Hz] −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 Amplitude − dB G017 ANTIALIASING FILTER −50 −40 −30 −20 −10 f − Frequency − Hz Amplitude − dB 1 10 100 10M1k 10k G019 100k 1M −1.0 −0.8 −0.6 −0.4 −0.2 0.0 0.2 f − Frequency − Hz Amplitude − dB 1 10 100 100k1k 10k G020 PCM3006 SBAS089A OCTOBER 2000 REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (ADCs) (continued) All specifications at T A V CC V DD f S 44.1 kHz, and f SYSCLK 384 f S unless otherwise noted HIGH-PASS FILTER RESPONSE HIGH-PASS FILTER RESPONSE Figure 17. Figure 18. ANTIALIASING FILTER ANTIALIASING FILTER OVERALL FREQUENCY RESPONSE PASS-BAND FREQUENCY RESPONSE Figure 19. Figure 20.

www.ti.com TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (DACs) DIGITAL FILTER −100 −80 −60 −40 −20 Level − dB f − Frequency − Hz 75k25k 50k G021 0 175k100k 125k 150k −1.00 −0.80 −0.60 −0.40 −0.20 0.00 Level − dB f − Frequency − Hz G022 0 20k10k 15k DE-EMPHASIS FILTER −12 −10 Level − dB f − Frequency − Hz G023 0 25k10k 15k 20k −0.6 −0.4 −0.2 0.0 0.2 0.4 0.6 Error − dB f − Frequency − Hz 3628 G024 0 145127256 10884 PCM3006 SBAS089A OCTOBER 2000 REVISED OCTOBER 2004 All specifications at T A V CC V DD f S 44.1 kHz, and f SYSCLK 384 f S unless otherwise noted OVERALL FREQUENCY CHARACTERISTICS PASS-BAND RIPPLE CHARACTERISTICS S 44.1 kHz) S 44.1 kHz) Figure 21. Figure 22. DE-EMPHASIS FREQUENCY RESPONSE (32 kHz) DE-EMPHASIS ERROR (32 kHz) Figure 23. Figure 24.

www.ti.com −12 −10 Level − dB f − Frequency − Hz G025 0 25k10k 15k 20k −0.6 −0.4 −0.2 0.0 0.2 0.4 0.6 Error − dB f − Frequency − Hz 4999.8375 G026 0 19999.359999.675 14999.5125 −12 −10 Level − dB f − Frequency − Hz G027 0 25k10k 15k 20k −0.6 −0.4 −0.2 0.0 0.2 0.4 0.6 Error − dB f − Frequency − Hz 5442 G028 0 2176810884 16326 PCM3006 SBAS089A OCTOBER 2000 REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (DACs) (continued) All specifications at T A V CC V DD f S 44.1 kHz, and f SYSCLK 384 f S unless otherwise noted DE-EMPHASIS FREQUENCY RESPONSE (44.1 kHz) DE-EMPHASIS ERROR (44.1 kHz) Figure 25. Figure 26. DE-EMPHASIS FREQUENCY RESPONSE (48 kHz) DE-EMPHASIS ERROR (48 kHz) Figure 27. Figure 28.

www.ti.com ANALOG LOW-PASS FILTER −100 −80 −60 −40 −20 f − Frequency − Hz Level − dB 1 10 100 10M1k 10k G029 100k 1M −0.15 −0.10 −0.05 0.00 0.05 0.10 0.15 f − Frequency − Hz Level − dB 1 10 100 100k1k 10k G030 PCM3006 SBAS089A OCTOBER 2000 REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (DACs) (continued) All specifications at T A V CC V DD f S 44.1 kHz, and f SYSCLK 384 f S unless otherwise noted INTERNAL ANALOG FILTER FREQUENCY RESPONSE INTERNAL ANALOG FILTER FREQUENCY RESPONSE Hz MHz) Hz 100 kHz) Figure 29. Figure 30.

www.ti.com DEM1 Analog Front-End Circuit LRCINVINL Reference VREF1 VREF2 VINR Delta-Sigma Modulator Delta-Sigma Modulator Decimation and High-Pass Filter Power Supply Reset and Power Down Serial Data Interface DOUT VCOM (+) (−) (−) (+) Mode Control Interface Analog Front-End Circuit Decimation and High-Pass Filter ADC BCKIN DIN Analog Low-Pass Filter VOUTL Multilevel Delta-Sigma Modulator Interpolation Filter 8× Oversampling Analog Low-Pass Filter VOUTR Multilevel Delta-Sigma Modulator Interpolation Filter 8× Oversampling DAC DEM0 PDAD PDDA Clock SYSCLKVCC2 AGND DGND VDD B0004-04 VCC1 PCM3006 SBAS089A OCTOBER 2000 REVISED OCTOBER 2004 BLOCK DIAGRAM

www.ti.com 30 kΩVINR VCOM Delta-Sigma Modulator (+) VREF VREF2 1.0 µF 4.7 µF + (−) S0011-03 VREF1 4.7 µF + 4.7 µF + PCM3006 SBAS089A OCTOBER 2000 REVISED OCTOBER 2004 Figure 31. Analog Front End (Single-Channel)

www.ti.com APPLICATION INFORMATION PCM AUDIO INTERFACE DAC: 16-Bit, MSB-First, Right-Justified FORMAT 0: PCM3006 LRCIN Right-ChannelLeft-Channel BCKIN DIN MSB LSB MSB LSB 321 16151416 321 161514 BCKIN LRCIN Right-ChannelLeft-Channel DOUT 114 15 16321 MSB LSB MSB LSB 14 15 16321 ADC: 16-Bit, MSB-First, Left-Justified T0016-06 PCM3006 SBAS089A OCTOBER 2000 REVISED OCTOBER 2004 The four-wire digital audio interface for the PCM3006 comprises LRCIN (pin 10), BCKIN (pin 11), DIN (pin 15), and DOUT (pin 12). The PCM3006 accepts 16-bit MSB-first, right-justified format for the DAC and 16-bit MSB-first, left-justified format for the ADC. The PCM3006 can accept 32, 48, or bit clocks (BCKIN) in one clock of LRCIN. Figure and Figure illustrate audio data input/output format and timing. Figure 32. Audio Data Input/Output Format

www.ti.com BCKIN LRCIN DIN t(BCH) t(BCL) t(LRP) t(LB) t(BCY)

0.5 VDD

t(BL) DOUT t(BDO) t(LDO) t(DIS) t(DIH) T0021−01 SYSTEM CLOCK PCM3006 SBAS089A OCTOBER 2000 REVISED OCTOBER 2004 BCKIN pulse cycle time t (BCY) 300 ns (min) BCKIN pulse duration, HIGH t (BCH) 120 ns (min) BCKIN pulse duration, LOW t (BCL) 120 ns (min) BCKIN rising edge to LRCIN edge t (BL) ns (min) LRCIN edge to BCKIN rising edge t (LB) ns (min) LRCIN pulse duration t (LRP) t (BCY) (min) DIN setup time t (DIS) ns (min) DIN hold time t (DIH) ns (min) DOUT delay time to BCKIN falling edge t (BDO) ns (max) DOUT delay time to LRCIN edge t (LDO) ns (max) Rising time of all signals t (RISE) ns (max) Falling time of all signals t (FALL) ns (max) Figure 33. Audio Data Input/Output Timing The system clock for the PCM3006 must be either 256 f S 384 f S or 512 f S where f S is the audio sampling frequency. The system clock should be provided to SYSCLK (pin 9). The PCM3006 also has a system clock detection circuit that automatically senses if the system clock is operating at 256 f S 384 f S or 512 f S When a 384-f S or 512-f S system clock is used, the clock is divded into 256 f S automatically. The 256-f S clock is used to operate the digital filter and the delta-sigma modulator. Table lists the relationship of typical sampling frequencies and system clock frequencies, and Figure illustrates the system clock timing. Table System Clock Frequencies SAMPLING RATE FREQUENCY SYSTEM CLOCK FREQUENCY (kHz) MHz 256 f s 384 f s 512 f s 8.1920 12.2880 16.3840 44.1 11.2896 16.9344 22.5792 12.2880 18.4320 24.5760

www.ti.com t(SCKH) SYSCLK

0.3 VDD

0.7 VDD

t(SCKL) 1/256 fS, 1/384 fS, or 1/512 fS H L T0005-05 RESET

1024 System Clock Periods

2.4 V 2.2 V 2.0 V VDD Internal Reset System Clock T0014-03

3 Clocks Minimum

duration, HIGH t (SCKH) ns (min) System clock duration, LOW t (SCKL) ns (min) Figure 34. System Clock Timing The PCM3006 has an internal power-on reset circuit, as well as an external forced reset. The internal power-on reset initializes (resets) when the supply voltage V DD 2.2 V (typ). External forced reset occurs when PDAD LOW and PDDA LOW. Figure shows the internal power-on reset timing and Figure shows the external forced reset timing by PDAD and PDDA During external forced reset, the outputs of the DAC are forced to GND (see Figure The analog outputs are then forced to 0.5 V CC during t (DACDLY1) (16384/f S after reset removal. The outputs of ADC are also invalid; digital outputs are forced to all zero during t (ADCDLY1) (18432/f S after reset removal. Figure 35. Internal Power-On Reset Timing

www.ti.com t(RST) Reset Removal t(RST) = 40 ns (min) Reset T0015-03 PDAD = LOW and PDDA = LOW Pulse Duration T0019-02 Reset Ready/OperationInternal Reset or Power Down DAC VOUT t(DACDLY1) (16384/fS) Reset Removal or Power Down Off Power Down ADC DOUT Zero Data Normal Data(1) VCOM (0.5 VCC) t(ADCDLY1) (18432/fS) Zero Data GND SYNCHRONIZATION WITH THE DIGITAL AUDIO SYSTEM PCM3006 SBAS089A OCTOBER 2000 REVISED OCTOBER 2004 Figure 36. External Forced-Reset Timing (1) The HPF transient response (exponentially attenuated signal from 0.2% dc of FSR with 200-ms time constant) appears initially. Figure 37. DAC Output and ADC Output for Reset and Power Down The PCM3006 operates with LRCIN synchronized to the system clock. The PCM3006 does not require any specific phase relationship between LRCIN and the system clock, but there must be synchronization of LRCIN and the system clock. If the relationship between the system clock and LRCIN changes more than bit clocks (BCKIN) during one sample (LRCIN) period because of phase jitter on LRCIN, internal operation of the DAC stops within 1/f S and the analog output is forced to bipolar zero (0.5 V CC until t (DACDLY2) delay time after the system clock is resynchronized to LRCIN. Internal operation of the ADC also stops within 1/f S and the digital output codes are set to bipolar zero until t (DACDLY2) delay time after resynchronization occurs. If LRCIN remains synchronized to the system clock within or fewer bit clocks, operation is normal. Figure illustrates the effects on the output when synchronization is lost. Before the outputs are forced to bipolar zero <1/f S seconds), the outputs are not defined and some noise may occur. During the transitions between normal data and undefined states, the output has discontinuities, which cause output noise.

www.ti.com Within 1/fS t(DACDLY2) (32/fS) Normal Data VCOM (0.5 VCC) Undefined DataNormal Data SynchronousAsynchronousSynchronous ResynchronizationSynchronization Lost DAC VOUT State of Synchronization T0020-03 Normal Data(1)Zero DataNormal DataADC DOUT t(ADCDLY2) (32/fS) Undefined Data OPERATIONAL CONTROL PCM3006 SBAS089A OCTOBER 2000 REVISED OCTOBER 2004 (1) The HPF transient response (exponentially attenuated signal from 0.2% dc of FSR with 200-ms time constant) appears initially. Figure 38. DAC Output and ADC Output for Loss of Synchronization The PCM3006 has hardwire functional control using PDAD (pin and PDDA (pin for power-down control and DEM0 (pin 18) and DEM1 (pin 17) for de-emphasis. PDAD ADC Power-Down Control (Pin This pin places the ADC section in the lowest power-consumption mode. The ADC operation is stopped by cutting the supply current to the ADC section, and DOUT is fixed to zero during ADC power-down-mode enable. Figure illustrates the ADC DOUT response for ADC power-down ON/OFF. This does not affect the DAC operation. PDAD POWER DOWN Low ADC power-down mode enabled High ADC power-down mode disabled PDDA DAC Power-Down Control (Pin This pin places the DAC section in the lowest power-consumption mode. The DAC operation is stopped by cutting the supply current to the DAC section and VOUT is fixed to GND during DAC power-down-mode enable. Figure illustrates the DAC VOUT response for DAC power-down ON/ OFF. This does not affect the ADC operation. PDDA POWER DOWN Low DAC power-down mode enabled High DAC power-down mode disabled DEM [1:0]: DAC De-Emphasis Control (Pin and Pin 18) These pins select the de-emphasis mode as shown below: DEM1 DEM0 DE-EMPHASIS Low Low De-emphasis 44.1 kHz ON Low High De-emphasis OFF High Low De-emphasis kHz ON High High De-emphasis kHz ON

www.ti.com APPLICATION AND LAYOUT CONSIDERATIONS POWER-SUPPLY BYPASSING GROUNDING VOLTAGE INPUT V REF INPUTS V COM INPUT SYSTEM CLOCK RST CONTROL EXTERNAL MUTE CONTROL TYPICAL CONNECTION DIAGRAM PCM3006 SBAS089A OCTOBER 2000 REVISED OCTOBER 2004 The digital and analog power supply lines to the PCM3006 should be bypassed to the corresponding ground pins with both 0.1- µ F ceramic and 10- µ F tantalum capacitors as close to the device pins as possible. Although the PCM3006 has three power supply lines to optimize dynamic performance, the use of one common power supply is generally recommended to avoid unexpected latch-up or pop noise due to power-supply sequencing problems. If separate power supplies are used, back-to-back diodes are recommended to avoid latch-up problems. In order to optimize the dynamic performance of the PCM3006, the analog and digital grounds are not connected internally. The PCM3006 performance is optimized with a single ground plane for all returns. It is recommended to tie all PCM3006 ground pins to the analog ground plane using low-impedance connections. The PCM3006 should reside entirely over this plane to avoid coupling high-frequency digital switching noise into the analog ground plane. A tantalum capacitor, between µ F and µ is recommended as an ac-coupling capacitor at the inputs. Combined with the 30-k Ω characteristic input impedance, a µ F coupling capacitor establishes a 5.3-Hz cutoff frequency for blocking dc. The input voltage range can be increased by adding a series resistor on the analog input line. This series resistor, when combined with the 30-k Ω input impedance, creates a voltage divider and enables larger input ranges. A 4.7- µ F to 10- µ F tantalum capacitor is recommended between V REF V REF and AGND to ensure low source impedance for the ADC references. These capacitors should be located as close as possible to the reference pins to reduce dynamic errors on the ADC reference. A 4.7- µ F to 10- µ F tantalum capacitor is recommended between V COM and AGND to ensure low source impedance of the ADC and DAC common voltage. This capacitor should be located as close as possible to the V COM pin to reduce dynamic errors on the ADC and DAC common voltage. The quality of the system clock can influence dynamic performance of both the ADC and DAC in the PCM3006. The duty cycle and jitter at the system clock input pin should be carefully managed. When power is supplied to the part, the system clock, bit clock (BCKIN), and word clock (LCRIN) must also be supplied simultaneously. Failure to supply the audio clocks results in a power dissipation increase of up to three times normal dissipation and can degrade long-term reliability if the maximum power-dissipation limit is exceeded. If capacitors larger than µ F are used between V REF and V COM external reset control by PDAD LOW and PDDA LOW is required after the V REF V COM transient response has settled. Click noises are caused by dc level changes at the DAC output. To avoid any click noises going in and out of power-down mode, an external mute control is generally required. The recommended control sequence is as follows: external mute ON, codec power-down OFF, and then external mute OFF. NOTE: If SYSCLK is stopped when the PCM3006 is in power-down mode, the device is internally reset. Figure is a schematic diagram showing typical connections for the PCM3006.

www.ti.com VREF2 20 VINL PDAD PDDA SYSCLK LRCIN BCKIN DOUT VOUTR DGND VOUTL DEM0 DEM1 NC VDD DIN Rch In Audio Interface VCC1 24 VCC1 VINR VREF1 VCC2 NC AGND VCOM 0.1 µF and 10 µF(1) DEM0 Control Interface PCM3006 1 µF(3) 4.7 µF(2) 4.7 µF(2) Lch In + 1 µF(3) SYSCLK L/R CLK BIT CLK DATA OUT DATA IN S0014-02 +3 V Analog VCC 0.1 µF and 10 µF(1) 4.7 µF(2) +4.7 µF(4) Rch Out(5) Lch Out(5) DEM1 0.1 µF and 10 µF(1) PDDA PDAD 4.7 µF(4) + PCM3006 SBAS089A OCTOBER 2000 REVISED OCTOBER 2004 (1) 0.1- µ F ceramic and 10- µ F tantalum, typical, depending on power supply quality and pattern layout (2) 4.7- µ typical, gives settling time with a 30-ms (4.7 µ F 6.4 k Ω time constant in the power ON and power-down OFF periods. (3) µ typical, gives a 5.3-Hz cutoff frequency for the input HPF in normal operation, and gives a settling time with a 30-ms µ F k Ω time constant in the power ON and power-down OFF periods. (4) 4.7- µ typical, gives a 3.4-Hz cutoff frequency for the output HPF in normal operation, and gives a settling time with a 47-ms (4.7 µ F k Ω time constant in the power ON and power-down OFF periods. (5) Post low-pass filter with RIN k Ω depending on the system performance requirements Figure 39. Typical Connection Diagram for PCM3006

www.ti.com THEORY OF OPERATION ADC SECTION 1st SW-CAP Integrator Analog In X(z) + − 2nd SW-CAP Integrator 3rd SW-CAP Integrator + − 4th SW-CAP Integrator + + + ++ + + + 5th SW-CAP Integrator Digital Out Y(z) Comparator Qn(z) H(z) 1-Bit DAC STF(z) = H(z) / [1 + H(z)] NTF(z) = 1 / [1 + H(z)] Y(z) = STF(z) * X(z) + NTF(z) * Qn(z) Signal Transfer Function Noise Transfer Function B0005-01 DAC SECTION PCM3006 SBAS089A OCTOBER 2000 REVISED OCTOBER 2004 The PCM3006 ADC consists of two reference circuits, a stereo single-to-differential converter, a fully differential 5-order delta-sigma modulator, a decimation filter (including digital high pass), and a serial interface circuit. The block diagram in this data sheet illustrates the architecture of the ADC section, Figure shows the single-to-differential converter, and Figure illustrates the architecture of the 5-order delta-sigma modulator and transfer functions. Figure 40. Simplified 5-Order Delta-Sigma Modulator An internal reference circuit with three external capacitors provides all reference voltages that are required by the ADC, which defines the full-scale range for the converter. The internal single-to-differential voltage converter saves the design, space, and extra parts needed for the external circuitry required by many delta-sigma converters. The internal full-differential signal processing architecture provides wide dynamic range and excellent power-supply rejection performance. The input signal is sampled at the oversampling rate, eliminating the need for a sample-and-hold circuit and simplifying antialias filtering requirements. The 5-order delta-sigma noise shaper consists of five integrators using switched-capacitor topology, a comparator, and a feedback loop consisting of a one-bit DAC. The delta-sigma modulator shapes the quantization noise, shifting it out of the audio band in the frequency domain. The high order of the modulator enables it to randomize the modulator outputs, reducing idle tone levels. The 64-f S one-bit data stream from the modulator is converted to 1-f S 16-bit data words by the decimation filter, which also acts as a low-pass filter to remove the shaped quantization noise. The dc components are removed by a high-pass filter function contained within the decimation filter. The delta-sigma DAC section of the PCM3006 is based on a 5-level amplitude quantizer and a third-order noise shaper. This section converts the oversampled input data to 5-level delta-sigma format. A block diagram of the 5-level delta-sigma modulator is shown in Figure This 5-level delta-sigma modulator has the advantage of stability and clock-jitter sensitivity over the typical one-bit (2-level) delta-sigma modulator. The combined oversampling rate of the delta-sigma modulator and the internal interpolation filter is f S for a 256-f S system clock. The theoretical quantization noise performance of the 5-level delta-sigma modulator shown in Figure

www.ti.com − Z−1 + + − Z−1 In 8 fS 21-Bit Out 64 fS + Z−1 B0008-01 5-Level Quantizer f − Frequency − kHz −150 −140 −130 −120 −110 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 5 10 15 20 25 30 Gain − dB G031 PCM3006 SBAS089A OCTOBER 2000 REVISED OCTOBER 2004 THEORY OF OPERATION (continued) Figure 41. 5-Level Δ Σ Modulator Block Diagram Figure 42. Quantization Noise Spectrum

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) PCM3006T ACTIVE SSOP DCV 24 128 Green (RoHS & no Sb/Br) CU SNBI Level-1-260C-UNLIM PCM3006T/2K ACTIVE SSOP DCV 24 2000 Green (RoHS & no Sb/Br) CU SNBI Level-1-260C-UNLIM PCM3006T/2KG6 ACTIVE SSOP DCV 24 2000 Green (RoHS & no Sb/Br) CU SNBI Level-1-260C-UNLIM PCM3006TG6 ACTIVE SSOP DCV 24 128 Green (RoHS & no Sb/Br) CU SNBI Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2006 Addendum-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 8-Aug-2008 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCM3006T/2K SSOP DCV 24 2000 346.0 346.0 33.0 PACKAGE MATERIALS INFORMATION www.ti.com 8-Aug-2008 Pack Materials-Page 2

MPSS001 – MARCH 2001 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DCV (R-PSOP-G24) PLASTIC SMALL-OUTLINE C D M0,10 0,10 0,65 4202107/A 03/01 Area A A 7,70 8,20 7,40 7,806,00 MAX 0,30 0,19 1,45 MAX1,15 TYP 0,05 0,15 Gage Plane 0,25 REF 0°-10° 0,30 0,70 Base Metal With Plating 0,09 0,20 0,09 0,16 0,19 0,25 0,30 0,19 11 2 1324 Index Seating Plane C E Section A-A NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusions, but do include mold mismatch and are measured at datum plane, mold parting line. Mold flash or protrusion shall not exceed 0,20mm per side. D. Lead width dimension does not include dambar protrusion/ intrusion. Allowable dambar protrusion shall be 0,13mm total in excess of width dimension at maximum material condition. Dambar intrusion shall not reduce width dimension by more than 0,07mm at least material condition. E. All dimensions in Section A-A apply to the flat section of the lead between 0,10mm and 0,25mm from the lead tips. F. A visual index feature must be located within the cross-hatched area.

(TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for design. Customers are responsible for their products and components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. TI products are not authorized for use in safety-critical (such as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications. TI products are neither designed nor intended for use in military/aerospace "enhanced plastic." Only products designated by TI as military-grade meet military specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI products are neither designed nor intended for use in automotive requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Clocks and Timers www.ti.com/clocks Digital Control www.ti.com/digitalcontrol Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security RFID www.ti-rfid.com Telephony www.ti.com/telephony RF/IF and ZigBee Solutions www.ti.com/lprf Video Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright 2008, Texas Instruments Incorporated