PCM3006

PCM3006 BURR-BROWN | Alldatasheet

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Technical content

1 PCM3006

FEATURES

l MONOLITHIC 16-BIT ΔΣ ADC AND DAC l STEREO ADC: Single-Ended Voltage Input

64 X Oversampling

THD+N: –84dB SNR: 89dB Dynamic Range: 89dB Digital High Pass Filter l STEREO DAC: Single-Ended Voltage Output Analog Low Pass Filter 8X Oversampling Digital Filter High Performance THD+N: –85dB SNR: 93dB Dynamic Range: 93dB l SPECIAL FEATURES Digital De-emphasis Power Down: ADC/DAC Independent l SAMPLING RATE: Up to 48kHz l SYSTEM CLOCK: 256f S, 384fS, 512fS l SINGLE +3V POWER SUPPLY l SMALL PACKAGE: 24-Lead TSSOP International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132

DESCRIPTION

The PCM3006 is a low cost single chip stereo audio CODEC (analog-to-digital and digital-to-analog con- verters) with single-ended analog voltage input and output. Both ADCs and DACs employ delta-sigma modula- tion with 64X oversampling. The ADCs include a digital decimation filter, and the DACs include an 8X oversampling digital interpolation filter. The DACs also include a de-emphasis function. PCM3006 oper- ates with 16-bit, left-justified for ADC, right-justified for DAC data formats. PCM3006 provides a Power-Down Mode that oper- ates on the ADCs and DACs independently. Fabricated on a highly advanced 0.6µs CMOS pro- cess, PCM3006 is suitable for a wide variety of cost-sensitive consumer applications where good performance is required. Applications include sam- pling keyboards, digital mixers, effects processors, hard-disk recorders, data recorders and digital video cameras. © 1998 Burr-Brown Corporation PDS-1436A Printed in U.S.A. February, 1998 PCM3006 16-Bit, Single-Ended Analog Input/Output STEREO AUDIO CODEC TM Lch In Rch In Analog Front-End Delta-Sigma Modulator Decimation Digital Filter Serial Interface and Mode Control Digital Out Digital In Parallel Mode Control System Clock Lch Out Rch Out Low Pass Filter and Output Buffer Multi-Level Delta-Sigma Modulator Oversampling Interpolation Digital Filter PCM3006

All specifications at +25°C, VDD = VCC = 3.0V, fS = 44.1kHz, SYSCLK = 384fS, and 16-bit data, unless otherwise noted. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. PCM3006T PARAMETER CONDITIONS MIN TYP MAX UNITS DIGITAL INPUT/OUTPUT Input Logic Input Logic Level: VIH(1) 0.7 x VDD VDC VIL(1) 0.3 x VDD VDC Input Logic Current: IIN(2) ±1 µA Input Logic Current: IIN(3) 100 µA Output Logic Output Logic Level: VOH (4) IOUT = –1mA V DD –0.3 VDC VOL (4) IOUT = +1mA 0.3 VDC CLOCK FREQUENCY Sampling Frequency (fS) 32 44.1 48 kHz System Clock Frequency 256f S 8.1920 11.2896 12.2880 MHz 384fS 12.2880 16.9344 18.4320 MHz 512fS 16.3840 22.5792 24.5760 MHz ADC CHARACTERISTICS RESOLUTION 16 Bits DC ACCURACY Gain Mismatch Channel-to-Channel ±1.0 ±3.0 % of FSR Gain Error ±2.0 ±5.0 % of FSR Gain Drift ±20 ppm of FSR/ °C Bipolar Zero Error High-Pass Filter Disabled (6) ±1.7 % of FSR Bipolar Zero Drift High-Pass Filter Disabled (6) ±20 ppm of FSR/ °C DYNAMIC PERFORMANCE (5) THD+N: V IN = –0.5dB –84 –77 dB VIN = –60dB –26 dB Dynamic Range A-Weighted 84 89 dB Signal-to-Noise Ratio A-Weighted 84 89 dB Channel Separation 82 86 dB DIGITAL FILTER PERFORMANCE Passband 0.454fS Hz Stopband 0.583fS Hz Passband Ripple ±0.05 dB Stopband Attenuation –65 dB Delay Time 17.4/fS sec HPF Frequency Response –3dB 0.019f S mHz ANALOG INPUT Voltage Range 0.60 VCC Vp-p Center Voltage 0.50 VCC V Input Impedance 30 k Ω Anti-Aliasing Filter Frequency Response –3dB 150 kHz DAC CHARACTERISTICS RESOLUTION 16 Bits DC ACCURACY Gain Mismatch Channel-to-Channel ±1.0 ±3 % of FSR Gain Error ±1.0 ±5 % of FSR Gain Drift ±20 ppm of FSR/ °C Bipolar Zero Error ±2.5 % of FSR Bipolar Zero Drift ±20 ppm of FSR/ °C DYNAMIC PERFORMANCE (6) THD+N: V OUT = 0dB (Full Scale) –85 –77 dB VOUT = –60dB –30 dB Dynamic Range EIAJ, A-Weighted 86 93 dB Signal-to-Noise Ratio EIAJ, A-Weighted 86 93 dB Channel Separation 84 90 dB

3 PCM3006

SPECIFICATIONS (CONT) All specifications at +25°C, VDD = VCC = 3.0V, fS = 44.1kHz, SYSCLK = 384fS, CLKIO Input, 16-bit data, unless otherwise noted. PCM3006T PARAMETER CONDITIONS MIN TYP MAX UNITS DAC CHARACTERISTICS (CONT) DIGITAL FILTER PERFORMANCE Passband 0.445f S Hz Stopband 0.555fS Hz Passband Ripple ±0.17 dB Stopband Attenuation –35 dB Delay Time 11.1/fS sec ANALOG OUTPUT Voltage Range 0.6 x VCC Vp-p Center Voltage 0.5 x VCC VDC Load Impedance AC-Coupling 10 k Ω LPF Frequency Response f = 20kHz –0.16 dB POWER SUPPLY REQUIREMENTS Voltage Range: VCC , VDD –25°C to +85°C 2.7 3.0 3.6 VDC 0° C to +70°C (7) 2.4 3.0 3.6 VDC Supply Current: ADC/DAC Operation V CC = VDD = 3.0V 18 24 mA ADC Operation V CC = VDD = 3.0V 12 16 mA DAC Operation V CC = VDD = 3.0V 7 10 mA ADC/DAC Power-Down (8) VCC = VDD = 3.0V 50 µA Power Dissipation: ADC/DAC Operation V CC = VDD = 3.0V 54 72 mW ADC Operation V CC = VDD = 3.0V 36 48 mW DAC Operation V CC = VDD = 3.0V 21 30 mW ADC/DAC Power-Down (8) VCC = VDD = 3.0V 150 µW TEMPERATURE RANGE Operation –25 +85 °C Storage –55 +125 °C Thermal Resistance, Θ JA 100 °C/W NOTES: (1) Pins 7, 8, 9, 10, 11, 15, 17, 18: PDAD, PDDA, SYSCLK, LRCIN, BCKIN, DIN, DEM1, DEM0 (Schmitt-Trigger input with 100kΩ typical internal pull- down resistor). (2) Pins 9, 10, 11, 15: SYSCLK, LRCIN, BCKIN, DIN (Schmitt-Trigger input). (3) Pins 7, 8, 17, 18: PDAD, PDDA, DEM1, DEM0 (Schmitt-Trigger input, 100kΩ typical internal pull-down resistor). (4) Pin 12: DOUT. (5) f IN = 1kHz, using Audio Precision System II, rms mode with 20kHz LPF, 400Hz HPF used for performance calculation. (6) fOUT = 1kHz, using Audio Precision System II, rms mode with 20kHz LPF, 400Hz HPF used for performance calculation. (7) Applies for voltages between 2.4V to 2.7V for 0°C to +70°C and 256fS /512fS operation (384fS not available). (8) SYSCLK, BCKIN, and LRCIN are stopped.

V CC 2 NC AGND VCOM VOUT R VOUT L DEM0 DEM1 NC DIN V DD DGND PCM3006 NC = No Connection PIN CONFIGURATION Top View TSSOP PIN NAME I/O DESCRIPTION 1V CC 1 — ADC Analog Power Supply 2V CC 1 — ADC Analog Power Supply 3V INR IN ADC Analog Input, Rch 4V REF 1 — ADC Reference, 1 5V REF 2 — ADC Reference, 2 6V INL IN ADC Analog Input, Lch

7 PDAD IN ADC Power Down, Active LOW (1, 2)

8 PDDA IN DAC Power Down, Active LOW (1, 2)

9 SYSCLK IN System Clock Input (2)

10 LRCIN IN Sample Rate Clock Input (f S)(2)

11 BCKIN IN Bit Clock Input (2)

12 DOUT OUT Data Output

13 DGND — Digital Ground

DD — Digital Power Supply

15 DIN IN Data Input

16 NC IN No Connection

17 DEM1 IN De-emphasis Control (1, 2)

18 DEM0 IN De-emphasis Control 0 (1, 2)

19 V OUT L OUT DAC Analog Output, Lch

20 V OUT R OUT DAC Analog Output, Rch

21 V COM — ADC/DAC Common

22 AGND — Analog Ground

23 NC — No Connection

CC 2 — DAC Analog Power Supply NOTES: (1) With 100kΩ typical internal pull-down resistor. (2) Schmitt-Trigger input. PIN ASSIGNMENTS Supply Voltage ABSOLUTE MAXIMUM RATINGS ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degrada- tion to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PACKAGE INFORMATION

PRODUCT PACKAGE NUMBER (1) PCM3006T 24-Lead TSSOP 350 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book.

5 PCM3006

TYPICAL PERFORMANCE CURVES ADC SECTION At TA = +25°C, VCC = VDD = 3.0V, fS = 44.1kHz, fSYSCLK = 384fS, and fSIGNAL = 1kHz, unless otherwise noted. THD+N vs TEMPERATURE Temperature (°C) THD+N at –0.5dB (%) 0.010 0.008 0.006 0.004 0.002 –25 0 25 50 75 85 100 THD+N at –60dB (%) 6.0 5.0 4.0 3.0 2.0 –60dB 0.5dB DYNAMIC RANGE and SNR vs TEMPERATURE Temperature (°C) Dynamic Range (dB) –25 0 25 50 75 85 100 SNR (dB) SNR Dynamic Range DYNAMIC RANGE and SNR vs SUPPLY VOLTAGE Supply Voltage (V) Dynamic Range (dB) SNR (dB) Dynamic Range SNR THD+N vs SUPPLY VOLTAGE Supply Voltage (V) THD+N at –0.5dB (%) 0.010 0.008 0.006 0.004 0.002 THD+N at –60dB (%) 6.0 5.0 4.0 3.0 2.0 –60dB –0.5dB THD+N vs SAMPLING FREQUENCY fS (kHz) THD+N at –0.5dB (%) 0.010 0.008 0.006 0.004 0.002 32 44.1 48 THD+N at –60dB (%) 5.0 4.0 3.0 2.0 1.0 –60dB –0.5dB DYNAMIC RANGE and SNR vs SAMPLING FREQUENCY fS (kHz) Dynamic Range (dB) 32 44.1 48 SNR (dB) Dynamic Range SNR

TYPICAL PERFORMANCE CURVES DAC SECTION At TA = +25°C, VCC = VDD = 3.0V, fS = 44.1kHz, fSYSCLK = 384fS, and fSIGNAL = 1kHz, unless otherwise noted. THD+N vs TEMPERATURE Temperature (°C) THD+N at FS (%) 0.010 0.008 0.006 0.004 0.002 –25 0 25 50 75 85 100 THD+N at –60dB (%) 4.0 3.0 2.0 1.0 FS –60dB DYNAMIC RANGE and SNR vs TEMPERATURE Temperature (°C) Dynamic Range (dB) –25 0 25 50 75 85 100 SNR (dB) SNR Dynamic Range THD+N vs SUPPLY VOLTAGE Supply Voltage (V) THD+N at FS (%) 0.010 0.008 0.006 0.004 0.002 THD+N at –60dB (%) 4.0 3.0 2.0 1.0 –60dB FS DYNAMIC RANGE and SNR vs SUPPLY VOLTAGE Supply Voltage (V) Dynamic Range (dB) SNR (dB) SNR Dynamic Range THD+N vs SAMPLING FREQUENCY and SYSTEM CLOCK fS (kHz) THD+N at FS (%) 0.010 0.008 0.006 0.004 0.002 32 44.1 48 THD+N at –60dB (%) 4.0 3.0 2.0 1.0 –60dB 384fS 256fS, 512fS 384fS 256fS, 512fS FS DYNAMIC RANGE and SNR vs SAMPLING FREQUENCY and SYSTEM CLOCK fS (kHz) Dynamic Range (dB) 32 44.1 48 SNR (dB) 384fS 256fS, 512fS SNR Dynamic Range

7 PCM3006

TYPICAL PERFORMANCE CURVES At TA = +25°C, VCC = VDD = 3.0V, fS = 44.1kHz, and fSYSCLK = 384fS, unless otherwise noted. ADC DIGITAL FILTER STOPBAND ATTENUATION CHARACTERISTICS Normalized Frequency (x fS Hz) Amplitude (dB) –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 PASSBAND RIPPLE CHARACTERISTICS Normalized Frequency (x fS Hz) Amplitude (dB) 0.2 0.0 –0.2 –0.4 –0.6 –0.8 –1.0 TRANSIENT BAND CHARACTERISTICS Normalized Frequency (x fS Hz) Amplitude (dB) –10 –4.13dB at 0.5 x fS HIGH PASS FILTER RESPONSE Normalized Frequency (x fS /1000 Hz) Amplitude (dB) –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 HIGH PASS FILTER RESPONSE Normalized Frequency (x fS /1000 Hz) Amplitude (dB) 0.2 0.0 –0.2 –0.4 –0.6 –0.8 –1.0 12340 OVERALL CHARACTERISTICS Normalized Frequency (x fS Hz) Amplitude (dB) –50 –100 –150 –200 81 6 2 4 3 20

TYPICAL PERFORMANCE CURVES At TA = +25°C, VCC = VDD = 3.0V, fS = 44.1kHz, and fSYSCLK = 384fS, unless otherwise noted. ANTI-ALIASING FILTER ANTI-ALIASING FILTER OVERALL FREQUENCY RESPONSE Frequency (Hz) Amplitude (dB) –10 –20 –30 –40 –50 10 100 1k 10k 100k 1M 10M0 ANTI-ALIASING FILTER PASSBAND FREQUENCY RESPONSE Frequency (Hz) Amplitude (dB) 0.2 0.0 –0.2 –0.4 –0.6 –0.8 –1.0 10 100 1k 10k 100k0

9 PCM3006

TYPICAL PERFORMANCE CURVES At TA = +25°C, VCC = VDD = 3.0V, fS = 44.1kHz, and fSYSCLK = 384fS, unless otherwise noted. DAC DIGITAL FILTER 0 50k 100k 150k –20 –40 –60 –80 –100 Level (dB) OVERALL FREQUENCY CHARACTERISTICS (fS = 44.1kHz) Frequency (Hz) PASSBAND RIPPLE CHARACTERISTICS (f S = 44.1kHz) –0.2 –0.4 –0.6 –0.8 –1.0 0 5k 10k 15k 20k Level (dB) Frequency (Hz) DE-EMPHASIS FREQUENCY RESPONSE (32kHz) 0 5k 10k 15k 20k 25k Frequency (Hz) –10 –12 DE-EMPHASIS FREQUENCY RESPONSE (44.1kHz) 0 5k 10k 15k 20k 25k Frequency (Hz) –10 –12 DE-EMPHASIS FREQUENCY RESPONSE (48kHz) 0 5k 10k 15k 20k 25k Frequency (Hz) –10 –12 Level (dB) Level (dB) Level (dB) DE-EMPHASIS ERROR (32kHz) 0 3628 7256 10884 14512 0 4999.8375 9999.675 14999.5125 19999.35 0 5442 10884 16326 21768 Frequency (Hz) 0.6 0.4 0.2 –0.2 –0.4 –0.6 0.6 0.4 0.2 –0.2 –0.4 –0.6 0.6 0.4 0.2 –0.2 –0.4 –0.6 DE-EMPHASIS ERROR (44.1kHz) Frequency (Hz) DE-EMPHASIS ERROR (48kHz) Frequency (Hz) Error (dB) Error (dB) Error (dB) –20 –40 –60 –80 –100 10 100 1k 10k 100k 1M 10M Frequency (Hz) Level (dB) INTERNAL ANALOG FILTER FREQUENCY RESPONSE (10Hz~10MHz) 0.15 0.10 0.05 –0.05 –0.10 –0.15 Level (dB) Frequency (Hz) 10 100 1k 10k 100k INTERNAL ANALOG FILTER FREQUENCY RESPONSE (1Hz~20kHz)

FIGURE 1. Analog Front-End (Single-Channel).

11 PCM3006

input/output format and timing. FIGURE 2. Audio Data Input/Output Format. FIGURE 3. Audio Data Input/Output Timing.

system clock should be provided to SYSCLK (pin 9). FIGURE 5. Internal Power-On Reset Timing.

1024 System Clock Periods

FIGURE 6. External Forced Reset Timing. FIGURE 4. System Clock Timing. TABLE I. System Clock Frequencies. the outputs of the DAC are forced to GND (see Figure 7). ADCDLY1 (18432/fS) after reset removal.

13 PCM3006

bit clocks to the system clock, operation will be normal. which will cause output noise. FIGURE 7. DAC Output and ADC Output for Reset and Power Down. FIGURE 8. DAC Output and ADC Output for Loss of Synchronization. with 200ms time constant) appears initially. with 200ms time constant) appears initially.

In order to optimize the dynamic performance of PCM3006, the analog and digital grounds are not connected internally. The PCM3006 performance is optimized with a single ground plane for all returns. It is recommended to tie all PCM3006 ground pins with low impedance connections to the analog ground plane. PCM3006 should reside entirely over this plane to avoid coupling high frequency digital switching noise into the analog ground plane. VOLTAGE INPUT PINS A tantalum capacitor, between 1µF and 10µF, is recom- mended as an AC-coupling capacitor at the inputs. Combined with the 30kΩ characteristic input impedance, a 1.0µF cou- pling capacitor will establish a 5.3Hz cut-off frequency for blocking DC. The input voltage range can be increased by adding a series resistor on the analog input line. This series resistor, when combined with the 30kΩ input impedance, creates a voltage divider and enables larger input ranges. V REF Pins A 4.7µF to 10µF tantalum capacitor is recommended be- tween V REF 1, VREF 2, and AGND to ensure low source impedance for the ADC’s references. These capacitors should be located as close as possible to the reference pins to reduce dynamic errors on the ADC reference. V COM Pin A 4.7µF to 10µF tantalum capacitor is recommended be- tween VCOM and AGND to insure low source impedance of the ADC and DAC common voltage. This capacitor should be located as close as possible to the V COM pin to reduce dynamic errors on the DAC common. SYSTEM CLOCK The quality of the system clock can influence dynamic performance of both the ADC and DAC in the PCM3006. The duty cycle and jitter at the system clock input pin must be carefully managed. When power is supplied to the part, the system clock, bit clock (BCKIN) and a word clock (LCRIN) should also be supplied simultaneously. Failure to supply the audio clocks will result in a power dissipation increase of up to three times normal dissipation and may degrade long term reliability if the maximum power dissipa- tion limit is exceeded. RST CONTROL If the capacitance between V REF and VCOM exceeds 2.2µF, an external reset control delay time circuit must be used. OPERATIONAL CONTROL PCM3006 has hardwire functional control using PDAD (pin 7) and PDDA (pin 8) for Power-Down Control and DEM0 (pin 18) and DEM1 (pin 17) for de-emphasis. PDAD: ADC Power-Down Control (Pin 7) This pin places the ADC section in the lowest power consumption mode. The ADC operation is stopped by cutting the supply current to the ADC section, and DOUT is fixed to zero during ADC Power-Down Mode enable. Figure 7 illustrates the ADC DOUT response for ADC power-down ON/OFF. This does not affect the DAC operation. PDAD POWER-DOWN Low ADC Power-Down Mode Enabled High ADC Power-Down Mode Disabled PDDA: DAC Power-Down Control (Pin 8) This pin places the DAC section in the lowest power consumption mode. The DAC operation is stopped by cutting the supply current to the DAC section and V OUT is fixed to GND during DAC Power-Down Mode enable. Figure 8 illustrates the DAC V OUT response for DAC Power-Down ON/ OFF. This does not affect the ADC operation. PDDA POWER-DOWN Low DAC Power-Down Mode Enabled High DAC Power-Down Mode Disable DEM1, 0: DAC De-emphasis Control (Pin 17 and Pin 18) These pins select the de-emphasis mode as shown below: DEM1 DEM0 Low Low De-emphasis 44.1kHz ON Low High De-emphasis OFF High Low De-emphasis 48kHz ON High High De-emphasis 32kHz ON APPLICATION AND LAYOUT CONSIDERATIONS POWER SUPPLY BYPASSING The digital and analog power supply lines to PCM3006 should be bypassed to the corresponding ground pins with both 0.1µF ceramic and 10µF tantalum capacitors as close to the device pins as possible. Although PCM3006 has three power supply lines to optimize dynamic performance, the use of one common power supply is generally recom- mended to avoid unexpected latch-up or pop noise due to power supply sequencing problems. If separate power sup- plies are used, back-to-back diodes are recommended to avoid latch-up problems.

15 PCM3006

Power-Down Mode, the device is internally reset. the 5-level delta-sigma modulator and transfer functions. FIGURE 9. Typical Connection Diagram for PCM3006. FIGURE 10. Simplified 5-Level Delta-Sigma Modulator.