PCM3002E

PCM3003 BURR-BROWN | Alldatasheet

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Technical content

1 PCM3002/3003

FEATURES

l MONOLITHIC 20-BIT ΔΣ ADC AND DAC l 16-/20-BIT INPUT/OUTPUT DATA l SOFTWARE CONTROL: PCM3002 l HARDWARE CONTROL: PCM3003 l STEREO ADC: Single-Ended Voltage Input

64 X Oversampling

THD+N: –86dB SNR: 90dB Dynamic Range: 90dB l STEREO DAC: Single-Ended Voltage Output Analog Low Pass Filter 64X Oversampling High Performance THD+N: –86dB SNR: 94dB Dynamic Range: 94dB l SPECIAL FEATURES Digital De-emphasis Digital Attenuation (256 Steps) Soft Mute Digital Loop Back Power Down: ADC/DAC Independent l SAMPLING RATE: Up to 48kHz l SYSTEM CLOCK: 256f S, 384fS, 512fS l SINGLE +3V POWER SUPPLY l SMALL PACKAGE: SSOP-24 16-/20-Bit Single-Ended Analog Input/Output STEREO AUDIO CODECs TM

DESCRIPTION

The PCM3002 and PCM3003 are low cost single chip stereo audio CODECs (analog-to-digital and digital-to- analog converters) with single-ended analog voltage input and output. The ADCs and DACs employ delta-sigma modulation with 64X oversampling. The ADCs include a digital decimation filter, and the DACs include an 8X oversampling digital interpolation filter. The DACs also include digital attenuation, de-emphasis, infinite zero detection and soft mute to form a complete subsystem. PCM3002 and PCM3003 operate with left-justified, and right-justified formats, while the PCM3002 also supports the I 2S data format. PCM3002 and PCM3003 provide a power-down mode that operates on the ADCs and DACs independently. Fabricated on a highly advanced CMOS process, PCM3002 and PCM3003 are suitable for a wide vari- ety of cost-sensitive consumer applications where good performance is required. PCM3002’s programmable functions are controlled by software and the PCM3003’s functions include de- emphasis, power down, and audio data format selec- tions, which are controlled by hardware. © 1997 Burr-Brown Corporation PDS-1414C Printed in U.S.A. January, 2000 Lch In Rch In Analog Front-End Delta-Sigma Modulator Digital Decimation Filter Serial Interface and Mode Control Digital Out Digital In Serial Mode Control System Clock Lch Out Rch Out Low Pass Filter and Output Buffer Multi-Level Delta-Sigma Modulator Digital Interpolation Filter International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 For most current data sheet and other product information, visit www.burr-brown.com

All specifications at +25°C, VDD = VCC = 3.0V, fS = 44.1kHz, SYSCLK = 384fS, and 16-bit data, unless otherwise noted. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. NOTES: (1) Pins 7, 8, 17 and 18: RST, ML, MD, MC for the PCM3002; PDAD, PDDA, DEM1, DEM0 for PCM3003 (Schmitt-Trigger input with 100kΩ typical internal pull-down resistor). (2) Pins 9, 10, 11, 15: SYSCLK, LRCIN, BCKIN, DIN (Schmitt Trigger input). (3) Pin16: 20BIT for PCM3003 (Schmitt-Trigger input, 100kΩ typical internal pull-down resistor). (4) Pin 12: DOUT. (5) Pin 16: ZFLG (open drain output). (6) High Pass Filter for Offset Cancel. (7) Refer to Application Bulletin AB-148 for information relating to operation at lower sampling frequencies. (8) fIN = 1kHz, using Audio Precision System II, rms mode with 20kHz LPF, 400Hz HPF used for performance calculation. (9) fOUT = 1kHz, using Audio Precision System II, rms mode with 20kHz LPF, 400Hz HPF used for performance calculation. (10) Applies for voltages between 2.4V to 2.7V for 0°C to +70°C and 256fS /512fS operation (384fS not available). (11) SYSCLK, BCKIN, and LRCIN are stopped. PCM3002E/3003E PARAMETER CONDITIONS MIN TYP MAX UNITS DIGITAL INPUT/OUTPUT Input Logic Input Logic Level: VIH(1, 2, 3) 0.7 x VDD VDC VIL(1, 2, 3) 0.3 x VDD VDC Input Logic Current: IIN(2) ±1 µA Input Logic Current: IIN(1) 100 µA Output Logic Output Logic Level: VOH (5) IOUT = –1mA V DD –0.3 VDC VOL (5) IOUT = +1mA 0.3 VDC Output Logic Level: VOL (4) IOUT = +1mA 0.3 VDC CLOCK FREQUENCY Sampling Frequency (fS) 32(7) 44.1 48 kHz System Clock Frequency 256f S 8.1920 11.2896 12.2880 MHz 384fS 12.2880 16.9344 18.4320 MHz 512fS 16.3840 22.5792 24.5760 MHz ADC CHARACTERISTICS RESOLUTION 20 Bits DC ACCURACY Gain Mismatch Channel-to-Channel ±1.0 ±3.0 % of FSR Gain Error ±2.0 ±5.0 % of FSR Gain Drift ±20 ppm of FSR/ °C Bipolar Zero Error High-Pass Filter Disabled (6) ±1.7 % of FSR Bipolar Zero Drift High-Pass Filter Disabled (6) ±20 ppm of FSR/ °C DYNAMIC PERFORMANCE (8) THD+N: V IN = –0.5dB –86 –80 dB VIN = –60dB –28 dB Dynamic Range A-Weighted 86 90 dB Signal-to-Noise Ratio A-Weighted 86 90 dB Channel Separation 84 88 dB DIGITAL FILTER PERFORMANCE Passband 0.454f S Hz Stopband 0.583fS Hz Passband Ripple ±0.05 dB Stopband Attenuation –65 dB Delay Time 17.4/fS sec HPF Frequency Response –3dB 0.019f S mHz ANALOG INPUT Voltage Range 0.60 VCC Vp-p Center Voltage 0.50 VCC V Input Impedance 30 k Ω Anti-Aliasing Filter Frequency Response –3dB 150 kHz

3 PCM3002/3003

All specifications at +25°C, VDD = VCC = 3.0V, fS = 44.1kHz, SYSCLK = 384fS, CLKIO Input, 18-bit data, unless otherwise noted. PCM3002E/3003E PARAMETER CONDITIONS MIN TYP MAX UNITS Supply Voltage ABSOLUTE MAXIMUM RATINGS ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degrada- tion to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. DAC CHARACTERISTICS RESOLUTION 20 Bits DC ACCURACY Gain Mismatch Channel-to-Channel ±1.0 ±3 % of FSR Gain Error ±1.0 ±5 % of FSR Gain Drift ±20 ppm of FSR/ °C Bipolar Zero Error ±1.0 % of FSR Bipolar Zero Drift ±20 ppm of FSR/ °C DYNAMIC PERFORMANCE (9) THD+N: V OUT = 0dB (Full Scale) –86 –80 dB VOUT = –60dB –28 dB Dynamic Range EIAJ, A-Weighted 88 94 dB Signal-to-Noise Ratio EIAJ, A-Weighted 88 94 dB Channel Separation 86 91 dB DIGITAL FILTER PERFORMANCE Passband 0.445f S Hz Stopband 0.555fS Hz Passband Ripple ±0.17 dB Stopband Attenuation –35 dB Delay Time 11.1/fS sec ANALOG OUTPUT Voltage Range 0.60 x VCC Vp-p Center Voltage 0.5 x VCC VDC Load Impedance AC-Coupling 10 k Ω LPF Frequency Response f = 20kHz –0.16 dB POWER SUPPLY REQUIREMENTS Voltage Range: VCC , VDD –25°C to +85°C 2.7 3.0 3.6 VDC 0° C to +70°C (10) 2.4 3.0 3.6 VDC Supply Current: Operation V CC = VDD = 3.0V 18 24 mA Power-Down V CC = VDD = 3.0V 50 µA Power Dissipation: Operation V CC = VDD = 3.0V 54 72 mW Power-Down (11) VCC = VDD = 3.0V 150 µW TEMPERATURE RANGE Operation –25 +85 °C Storage –55 +125 °C Thermal Resistance, Θ JA 100 °C/W PACKAGE SPECIFIED DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE NUMBER RANGE MARKING NUMBER (1) MEDIA PCM3002E SSOP-24 338 –25 °C to +85°C PCM3002E PCM3002E Rails " " " " " PCM3002E/2K Tape and Reel PCM3003E SSOP-24 338 –25 °C to +85°C PCM3003E PCM3003E Rails " " " " " PCM3003E/2K Tape and Reel NOTES: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces of “PCM3002E/2K” will get a single 2000-piece Tape and Reel. PACKAGE/ORDERING INFORMATION

V CC 2 AGND1 AGND2 V COM VOUT R VOUT L DEM0 DEM1 20BIT DIN V DD DGND PCM3003 VCC 1 VCC 1 VINR VREF L VREF R VINL RST ML SYSCLK LRCIN BCKIN DOUT V CC 2 AGND1 AGND2 V COM VOUT R VOUT L MC MD ZFLG DIN V DD DGND PCM3002 PIN CONFIGURATION—PCM3002 PIN CONFIGURATION—PCM3003 Top View SSOP Top View SSOP PIN NAME I/O DESCRIPTION 1V CC 1 — ADC Analog Power Supply 2V CC 1 — ADC Analog Power Supply 3V INR IN ADC Analog Input, Rch 4V REF L — ADC Reference, Lch 5V REF R — ADC Reference, Rch 6V INL IN ADC Analog Input, Lch

7 RST IN Reset, Active LOW (1, 2)

8 ML IN Strobe Pulse for Mode Control (1, 2)

9 SYSCLK IN System Clock Input (2)

10 LRCIN IN Sample Rate Clock Input (f S)(2)

11 BCKIN IN Bit Clock Input (2)

12 DOUT OUT Data Output

13 DGND — Digital Ground

DD — Digital Power Supply

15 DIN IN Data Input (2)

16 ZFLG OUT Zero Flag Output, Active LOW (3)

17 MD IN Serial Data for Mode Control (1, 2)

18 MC IN Bit Clock for Mode Control (1, 2)

19 V OUT L OUT DAC Analog Output, Lch

20 V OUT R OUT DAC Analog Output, Rch

21 V COM — ADC/DAC Common

22 AGND2 — DAC Analog Ground

23 AGND1 — ADC Analog Ground

CC 2 — DAC Analog Power Supply NOTES: (1) With 100kΩ typical internal pull-down resistor. (2) Schmitt-Trigger input. (3) Open drain output. PIN ASSIGNMENTS—PCM3002 PIN NAME I/O DESCRIPTION 1V CC 1 — ADC Analog Power Supply 2V CC 1 — ADC Analog Power Supply 3V INR IN ADC Analog Input, Rch 4V REF L — ADC Reference, Lch 5V REF R — ADC Reference, Rch 6V INL IN ADC Analog Input, Lch

7 PDAD IN ADC Power Down, Active LOW (1, 2)

8 PDDA IN DAC Power Down, Active LOW (1, 2)

DD — Digital Power Supply

15 DIN IN Data Input

16 20BIT IN 20-Bit Format Select (1, 2)

17 DEM1 IN De-emphasis Control (1, 2)

18 DEM0 IN De-emphasis Control 0 (1, 2)

CC 2 — DAC Analog Power Supply NOTE: (1) With 100kΩ typical internal pull-down resistor. (2) Schmitt-Trigger input. PIN ASSIGNMENTS—PCM3003

5 PCM3002/3003

TYPICAL PERFORMANCE CURVES ADC SECTION At TA = +25°C, VCC = VDD = 3.0V, fS = 44.1kHz, fSYSCLK = 384fS, and FSIGNAL = 1kHz, unless otherwise noted. THD+N vs TEMPERATURE Temperature (°C) THD+N at –0.5dB (%) 0.010 0.008 0.006 0.004 0.002 –25 0 25 50 75 85 100 THD+N at –60dB (%) 5.0 4.0 2.0 3.0 1.0 –60dB 0.5dB DYNAMIC RANGE and SNR vs TEMPERATURE Temperature (°C) Dynamic Range (dB) –25 0 25 50 75 85 100 SNR (dB) 5.0 4.0 2.0 3.0 1.0 SNR Dynamic Range DYNAMIC RANGE and SNR vs SUPPLY VOLTAGE Supply Voltage (V) Dynamic Range (dB) SNR (dB) Dynamic Range SNR THD+N vs SUPPLY VOLTAGE Supply Voltage (V) THD+N at –0.50dB (%) 0.010 0.008 0.006 0.004 0.002 THD+N at –60dB (%) 5.0 4.0 3.0 2.0 1.0 –60dB –0.5dB THD+N vs SAMPLING FREQUENCY fS (kHz) THD+N at –0.5dB (%) 0.010 0.008 0.006 0.004 0.002 32 44.1 48 THD+N at –60dB (%) 5.0 4.0 3.0 2.0 1.0 –60dB –0.5dB DYNAMIC RANGE and SNR vs SAMPLING FREQUENCY fS (kHz) Dynamic Range (dB) 32 44.1 48 SNR (dB) Dynamic Range SNR

TYPICAL PERFORMANCE CURVES DAC SECTION At TA = +25°C, VCC = VDD = 3.0V, fS = 44.1kHz, fSYSCLK = 384fS, and FSIGNAL = 1kHz, unless otherwise noted. DYNAMIC RANGE and SNR vs TEMPERATURE Temperature (°C) Dynamic Range (dB) –25 0 25 50 75 85 100 SNR (dB) SNR Dynamic Range DYNAMIC RANGE and SNR vs SUPPLY VOLTAGE Supply Voltage (V) Dynamic Range (dB) SNR (dB) SNR Dynamic Range DYNAMIC RANGE and SNR vs SAMPLING FREQUENCY and SYSTEM CLOCK fS (kHz) Dynamic Range (dB) 32 44.1 48 SNR (dB) SNR Dynamic Range 384fS 256fS, 512fS THD+N vs TEMPERATURE Temperature (°C) THD+N at FS (%) 0.010 0.008 0.006 0.004 0.002 –25 0 25 50 75 85 100 THD+N at –60dB (%) 4.0 3.0 2.0 1.0 0dB –60dB THD+N vs SUPPLY VOLTAGE Supply Voltage (V) THD+N at FS (%) 0.010 0.008 0.006 0.004 0.002 THD+N at –60dB (%) 4.0 3.0 2.0 1.0 –60dB 0dB THD+N vs SAMPLING FREQUENCY and SYSTEM CLOCK fS (kHz) THD+N at FS (%) 0.010 0.008 0.006 0.004 0.002 32 44.1 48 THD+N at –60dB (%) 4.0 3.0 2.0 1.0 –60dB 384fS 256fS, 512fS 384fS 256fS, 512fS0dB

7 PCM3002/3003

OUTPUT SPECTRUM (0dB, N = 8192) Frequency (kHz) Amplitude (dB) –20 –40 –60 –80 –100 –120 –140 51 0 1 5 2 5 22200 OUTPUT SPECTRUM (–60dB, N = 8192) Frequency (kHz) Amplitude (dB) –20 –40 –60 –80 –100 –120 –140 51 0 1 5 2 5 20 220 OUTPUT SPECTRUM (–60dB, N = 8192) Frequency (kHz) Amplitude (dB) –20 –40 –60 –80 –100 –120 –140 51 0 1 5 2 5 20 220 TYPICAL PERFORMANCE CURVES Output Spectrum At TA = +25°C, VCC = VDD = 3.0V, fS = 44.1kHz, fSYSCLK = 384fS, and FSIGNAL = 1kHz, unless otherwise noted. DACs ADCs THD+N vs SIGNAL LEVEL Signal Level (dB) THD+N (%) 100 0.1 0.001 0.001 THD+N vs SIGNAL LEVEL Signal Level (dB) THD+N (%) 100 0.1 0.001 0.001 OUTPUT SPECTRUM (0dB, N = 8192) Frequency (kHz) Amplitude (dB) –20 –40 –60 –80 –100 –120 –140 51 0 1 5 2 5 22200

ICC + IDD vs SAMPLING FREQUENCY fS (kHz) ICC + IDD (mA) 32 44.1 48 ADC & DAC 512fS 256fS TYPICAL PERFORMANCE CURVES Supply Current At TA = +25°C, VCC = VDD = 3.0V, fS = 44.1kHz, fSYSCLK = 384fS, DIN = BPZ, and VIN = BPZ, unless otherwise noted. ICC + IDD vs TEMPERATURE Temperature (°C) ICC + IDD (mA) ICC + IDD: Power Down and OFF (mA) 2.5 2.0 1.5 1.0 0.5 –25–50 –0 25 50 75 100 ADC DAC Power Down & OFF ADC & DAC ICC + IDD vs SUPPLY VOLTAGE Supply Voltage (V) ICC + IDD (mA) ICC + IDD: Power Down and OFF (mA) 2.5 2.0 1.5 1.0 0.5 Power Down & OFF ADC & DAC ADC DAC

9 PCM3002/3003

TYPICAL PERFORMANCE CURVES At TA = +25°C, VCC = VDD = 3.0V, fS = 44.1kHz, and fSYSCLK = 384fS, unless otherwise noted. ADC DIGITAL FILTER OVERALL CHARACTERISTICS Normalized Frequency (x fS Hz) Amplitude (dB) –50 –100 –150 –200 81 6 2 4 3 20 STOPBAND ATTENUATION CHARACTERISTICS Normalized Frequency (x fS Hz) Amplitude (dB) –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 PASSBAND RIPPLE CHARACTERISTICS Normalized Frequency (x fS Hz) Amplitude (dB) 0.2 0.0 –0.2 –0.4 –0.6 –0.8 –1.0 HIGH PASS FILTER RESPONSE Normalized Frequency (x fS /1000 Hz) Amplitude (dB) –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 HIGH PASS FILTER RESPONSE Normalized Frequency (x fS /1000 Hz) Amplitude (dB) 0.2 0.0 –0.2 –0.4 –0.6 –0.8 –1.0 12340 TRANSITION BAND CHARACTERISTICS Normalized Frequency (x fS Hz) Amplitude (dB) –10 –4.13dB at 0.5 x fS

TYPICAL PERFORMANCE CURVES At TA = +25°C, VCC = VDD = 3.0V, fS = 44.1kHz, and fSYSCLK = 384fS, unless otherwise noted. ANTI-ALIASING FILTER ANTI-ALIASING FILTER OVERALL FREQUENCY RESPONSE Frequency (Hz) Amplitude (dB) –10 –20 –30 –40 –50 10 100 1k 10k 100k 1M 10M0 ANTI-ALIASING FILTER PASSBAND FREQUENCY RESPONSE Frequency (Hz) Amplitude (dB) 0.2 0.0 –0.2 –0.4 –0.6 –0.8 –1.0 10 100 1k 10k 100k0

11 PCM3002/3003

DE-EMPHASIS ERROR (32kHz) 0 3628 7256 10884 14512 0 4999.8375 9999.675 14999.5125 19999.35 0 5442 10884 16326 21768 Frequency (Hz) 0.6 0.4 0.2 –0.2 –0.4 –0.6 0.6 0.4 0.2 –0.2 –0.4 –0.6 0.6 0.4 0.2 –0.2 –0.4 –0.6 DE-EMPHASIS ERROR (44.1kHz) Frequency (Hz) DE-EMPHASIS ERROR (48kHz) Frequency (Hz) Error (dB) Error (dB) Error (dB) DE-EMPHASIS FREQUENCY RESPONSE (32kHz) 0 5k 10k 15k 20k 25k Frequency (Hz) –10 –12 DE-EMPHASIS FREQUENCY RESPONSE (44.1kHz) 0 5k 10k 15k 20k 25k Frequency (Hz) –10 –12 DE-EMPHASIS FREQUENCY RESPONSE (48kHz) 0 5k 10k 15k 20k 25k Frequency (Hz) –10 –12 Level (dB) Level (dB) Level (dB) TYPICAL PERFORMANCE CURVES At TA = +25°C, VCC = VDD = 3.0V, fS = 44.1kHz, and fSYSCLK = 384fS, unless otherwise noted. DAC DIGITAL FILTER –20 –40 –60 –80 –100 10 100 1k 10k 100k 1M 10M Frequency (Hz) Level (dB) INTERNAL ANALOG FILTER FREQUENCY RESPONSE (10Hz~10MHz) 0 50k 100k 150k –20 –40 –60 –80 –100 Level (dB) OVERALL FREQUENCY CHARACTERISTICS (fS = 44.1kHz) Frequency (Hz) PASSBAND RIPPLE CHARACTERISTICS (f S = 44.1kHz) –0.2 –0.4 –0.6 –0.8 –1.0 0 5k 10k 15k 20k Level (dB) Frequency (Hz) 0.15 0.10 0.05 –0.05 –0.10 –0.15 Level (dB) Frequency (Hz) 10 100 1k 10k 100k INTERNAL ANALOG FILTER FREQUENCY RESPONSE (1Hz~20kHz)

FIGURE 1. Analog Front-End (Single-Channel). NOTES: (1) MC, MD, ML, RST, and ZFLG are for PCM3002 only. (2) DEM0, DEM1, 20BIT, PDAD, and PDDA are for PCM3003 only.

13 PCM3002/3003

illustrate audio data input/output formats and timing. can be selected when 32-bit clocks/LRCIN are applied. FIGURE 2. Audio Data Input/Output Format.

15 PCM3002/3003

system clock should be provided at the SYSCLK input (pin 9). TABLE I. System Clock Frequencies. FIGURE 5. System Clock Timing.

1024 System Clock Periods

FIGURE 6. Internal Power-On Reset Timing. FIGURE 7. External Forced Reset Timing.

17 PCM3002/3003

FIGURE 10. Control Data Input Format. FIGURE 11. Control Data Input Timing. TABLE II. Selectable Functions (O = User Selectable; X = Not Available).

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 REGISTER 0 res res res res res A1 A0 LDL AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0 REGISTER 1 res res res res res A1 A0 LDR AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0 REGISTER 2 res res res res res A1 A0 PDAD BYPS PDDA ATC IZD OUT DEM1 DEM0 MUT REGISTER 3 res res res res res A1 A0 res res res LOP res FMT1 FMT0 LRP res MAPPING OF PROGRAM REGISTERS SOFTWARE CONTROL (PCM3002) PCM3002’s special functions are controlled using four pro- gram registers which are 16 bits long. There are four distinct registers, with bits 9 and 10 determining which register is in use. Table III describes the functions of the four registers. REGISTER BIT NAME NAME DESCRIPTION Register 0 A (1:0) Register Address “00” res Reserved, should be set to “0” LDL DAC Attenuation Data Load Control for Lch AL (7:0) Attenuation Data for Lch Register 1 A (1:0) Register Address “01” res Reserved, should be set to “0” LDR DAC Attenuation Data Load Control for Rch AR (7:0) DAC Attenuation for Rch Register 2 A (1:0) Register Address “10” res Reserved, should be set to “0” PDAD ADC Power-Down Control PDDA DAC Power-Down Control BYPS ADC High-Pass Filter Operation Control ATC DAC Attenuation Data Mode Control IZD DAC Infinite Zero Detection Circuit Control OUT DAC Output Enable Control DEM (1:0) DAC De-emphasis Control MUT Lch and Rch Soft Mute Control Register 3 A (1:0) Register Address “11” res Reserved, should be set to “0” LOP ADC/DAC Analog Loop-Back Control FMT (1:0) ADC/DAC Audio Data Format Selection LRP ADC/DAC Polarity of LR-clock Selection TABLE III. Functions of the Registers. PROGRAM REGISTER 0 A (1:0): Bit 10, 9 Register Address These bits define the address for REGISTER 0: A1 A0 0 0 Register 0 res: Bit 11 : 15 Reserved These bits are reserved and should be set to “0”. LDL: Bit 8 DAC Attenuation Data Load Control for Left Channel This bit is used to simultaneously set analog outputs of the left and right channels. The output level is controlled by AL (7:0) attenuation data when this bit is set to “1”. When set to “0”, the new attenuation data will be ignored, and the output level will remain at the previous attenua- tion level. The LDR bit in REGISTER 1 has the equivalent function as LDL. When either LDL or LDR is set to “1”, the output level of the left and right channels are simultaneously controlled. AL (7:0): Bit 7:0 DAC Attenuation Data for Left Channel AL7 and AL0 are MSB and LSB, respectively. The attenuation level (ATT) is given by: ATT = 20 x log10 (ATT data/255) (dB) AL (7:0) ATTENUATION LEVEL 00h – ∞ dB (Mute) 01h –48.16dB FEh –0.07dB FFh 0dB (default) PROGRAM REGISTER 1 A (1:0): Register Address These bits define the address for REGISTER 1: A1 A0 0 1 Register 1 res: Bit 15:11 Reserved These bits are reserved and should be set to “0” LDR: Bit 8 DAC Attenuation Data Load Control for Right Channel This bit is used to simultaneously set analog outputs of the left and right channels. The output level is controlled by AL (7:0) attenuation data when this bit is set to “1”. When set to “0”, the new attenuation data will be ignored, and the output level will remain at the previous attenua- tion level. The LDL bit in REGISTER 0 has the equivalent function as LDR. When either LDL or LDR is set to “1”, the output level of the left and right channels are simultaneously controlled. AR (7:0): Bit 7:0 DAC Attenuation Data for Left Channel AR7 and AR0 are MSB and LSB respectively. See REGISTER 0 for the attenuation formula.

19 PCM3002/3003

IZD: Bit 4 DAC Infinite Zero Detection Circuit Control This bit enables the Infinite Zero Detection Circuit in PCM3002. When enabled, this circuit will dis- connect the analog output amplifier from the delta- sigma DAC when the input is continuously zero for 65,536 consecutive cycles of BCKIN. IZD

0 Infinite Zero Detection Disabled (default)

1 Infinite Zero Detection Enabled

OUT: Bit 3 DAC Output Enable Control When set to “1”, the outputs are forced to VCC /2 (bipolar zero). In this case, all registers in PCM3002 hold the present data. Therefore, when set to “0”, the outputs return to the previous programmed state. OUT

0 DAC Outputs Enabled (default normal operation)

1 DAC Outputs Disabled (forced to BPZ)

DEM (1:0):Bit 2,1 DAC De-emphasis Control These bits select the de-emphasis mode as shown below: DEM1 DEM0 0 0 De-emphasis 44.1kHz ON 0 1 De-emphasis OFF (default) 1 0 De-emphasis 48kHz ON 1 1 De-emphasis 32kHz ON MUT: Bit 0 DAC Soft Mute Control When set to “1”, both left and right-channel DAC outputs are muted at the same time. This muting is done by attenuating the data in the digital filter, so there is no audible click noise when soft mute is turned on. MUT

0 Mute Disable (default)

1 Mute Enable

A (1:0): Bit 10:9 Register Address These bits define the address for REGISTER 3: A1 A0 1 1 Register 3 res: Bit 15:11, 8:6, 4:0 Reserved These bits are reserved, and should be set to “0”. PROGRAM REGISTER 2 A (1:0): Bit 10, 9 Register Address These bits define the address for REGISTER 2: A1 A0 1 0 Register 2 res: Bit 15:11, 6 Reserved These bits are reserved and should be set to “0”. PDAD: Bit 8 ADC Power-Down Control This bit places the ADC section in the lowest power consumption mode. The ADC operation is stopped by cutting the supply current to the ADC section, and DOUT is fixed to zero during ADC Power-down mode enable. Figure 8 illustrates the ADC DOUT response for ADC power-down ON/ OFF. This does not affect the DAC operation. PDAD DAC POWER-DOWN

0 Power Down Mode Disabled (default)

1 Power Down Mode Enabled

BYPS: Bit 7 ADC High-Pass Filter Bypass Control This bit enables or disables the high-pass filter for the ADC. BYPS

0 High-Pass Filter Enabled (default)

1 High-Pass Filter Disabled (bypassed)

PDDA: Bit 6 DAC Power-Down Control This bit places the DAC section in the lowest power consumption mode. The DAC operation is stopped by cutting the supply current to the DAC section and V OUT is fixed to GND during DAC Power- Down Mode enable. Figure 8 illustrates the DAC V OUT response for DAC Power-Down ON/OFF. This does not affect the ADC operation. PDDA

0 Power-Down Mode Disabled (default)

1 Power-Down Mode Enabled

ATC: Bit 5 DAC Attenuation Channel Control When set to “1”, the REGISTER 0 attenuation data can be used for both DAC channels. In this case, the REGISTER 1 attenuation data is ig- nored. ATC

0 Individual Channel Attenuation Data Control (default)

1 Common Channel Attenuation Data Control

0 Loop-back Disable (default)

1 Loop-back Enable

1 Left-channel is “L”, Right-channel is “H”. FIGURE 12. Typical Connection Diagram for PCM3002/3003. PCM3002. (7) DEM0, DEM1, 20BIT, PDAD, PDDA are for the PCM3003.

21 PCM3002/3003

PCM3003 DATA FORMAT CONTROL PCM3003 has hardware functional control using PDAD (pin 7) and PDDA (pin 8) for Power-Down Control; DEM0 (pin 18) and DEM1 (pin 17) for de-emphasis; and 20BIT (pin 16) for 16-/20-bit format selection. Power-Down Control (Pin 7 and Pin 8) Both the ADC’s and DAC’s Power-Down Control pins place the ADC or DAC section in the lowest power con- sumption mode. The ADC/DAC operation is stopped by cutting the supply current to the ADC/DAC section. DOUT is fixed to zero during ADC Power-Down Mode enable and V OUT is fixed to GND during DAC Power-Down Mode enable. Figure 8 illustrates the ADC and DAC output re- sponse for Power-Down ON/OFF. PDAD PDDA POWER DOWN Low Low Reset (ADC/DAC Power-Down Enable) Low High ADC Power-Down/DAC Operates High Low ADC Operates/DAC Power-Down High High ADC and DAC Normal Operation De-Emphasis Control (Pin 17 and Pin 18) DEM0 (pin 18) and DEM1 (pin 17) are used as de-emphasis control pins. DEM1 DEM0 DE-EMPHASIS Low Low De-Emphasis Enabled for 44.1kHz Low High De-Emphasis Disabled High Low De-Emphasis Enabled for 48kHz High High De-Emphasis Enabled for 32kHz 20BIT Audio Data Selection (Pin 16) 20BIT FORMAT Low ADC: 16-bit MSB-first, Left-justified DAC: 16-bit MSB-first, Right-justified High ADC: 20-bit MSB-first, Left-justified DAC: 20-bit MSB-first, Right-justified APPLICATION AND LAYOUT CONSIDERATIONS POWER SUPPLY BYPASSING The digital and analog power supply lines to PCM3002/ 3003 should be bypassed to the corresponding ground pins with both 0.1µF ceramic and 10µF tantalum capacitors as close to the device pins as possible. Although PCM3002/ 3003 has three power supply lines to optimize dynamic performance, the use of one common power supply is generally recommended to avoid unexpected latch-up or pop noise due to power supply sequencing problems. If separate power supplies are used, back-to-back diodes are recom- mended to avoid latch-up problems. GROUNDING In order to optimize the dynamic performance of PCM3002/ 3003, the analog and digital grounds are not connected internally. The PCM3002/3003 performance is optimized with a single ground plane for all returns. It is recommended to tie all PCM3002/3003 ground pins with low impedance connections to the analog ground plane. PCM3002/3003 should reside entirely over this plane to avoid coupling high frequency digital switching noise into the analog ground plane. VOLTAGE INPUT PINS A tantalum or aluminum electrolytic capacitor, between 1µF and 10µF, is recommended as an AC-coupling capacitor at the inputs. Combined with the 30kΩ characteristic input impedance, a 1.0µF coupling capacitor will establish a 5.3Hz cut-off frequency for blocking DC. The input voltage range can be increased by adding a series resistor on the analog input line. This series resistor, when combined with the 30kΩ input impedance, creates a voltage divider and enables larger input ranges. V REF INPUTS A 4.7µF to 10µF tantalum capacitor is recommended be- tween VREF L, VREF R, and AGND to ensure low source impedance for the ADC’s references. These capacitors should be located as close as possible to the reference pins to reduce dynamic errors on the ADC reference. V COM INPUTS A 4.7µF to 10µF tantalum capacitor is recommended be- tween VCOM and AGND to ensure low source impedance of the ADC and DAC common voltage. This capacitor should be located as close as possible to the V COM pin to reduce dynamic errors on the DC common mode voltage. SYSTEM CLOCK The quality of the system clock can influence dynamic performance of both the ADC and DAC in the PCM3002/ 3003. The duty cycle and jitter at the system clock input pin must be carefully managed. When power is supplied to the part, the system clock, bit clock (BCKIN) and a word clock (LCRIN) should also be supplied simultaneously. Failure to supply the audio clocks will result in a power dissipation increase of up to three times normal dissipation and may degrade long term reliability if the maximum power dissipa- tion limit is exceeded.

and external mute OFF is recommended. 5th-order delta-sigma modulator and transfer functions. ADC, which defines the full scale range for the converter. puts, reducing idle tone levels. a 5-level amplitude quantizer and a 3rd-order noise shaper. sigma modulator is shown in Figure 15. FIGURE 13. Simplified 5th-Order Delta-Sigma Modulator.

23 PCM3002/3003

FIGURE 14. 5-Level Delta-Sigma Modulator Block Diagram. FIGURE 15. Quantization Noise Spectrum.