PCM3000E

PCM3001 TI | Alldatasheet

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(PCM3000) serial interface for special formats. Digital De-Emphasis The PCM3001 can be pin-programmed for data Digital Attenuation (256 Steps) formats. Soft Mute The PCM3000 and PCM3001 are fabricated using a Digital Loopback highly advanced CMOS process and are available in a small 28-pin SSOP package. The PCM3000/3001 Sample Rate: kHz to kHz are suitable for a wide variety of cost-sensitive System Clock: 256 f s 384 f s 512 f s consumer

applications

required. Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. System Two, Audio Precision are trademarks of Audio Precision, Inc. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright 2000 2004, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com ELECTRICAL CHARACTERISTICS PCM3000 PCM3001 SBAS055A OCTOBER 2000 REVISED OCTOBER 2004 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. All specifications at T A V DD V CC f S 44.1 kHz, SYSCLK 384 f CLKIO input, and 18-bit data, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUT/OUTPUT Input Logic V IH (1) Input logic level VDC V IL (1) 0.8 I IN (2) Input logic current µ A I IN (3) 120 V IH (4) 0.64 V DD VDC Input logic level V IL (4) 0.28 V DD I IN (4) Input logic current µ A Output Logic V OH (5) I OUT 1.6 mA 4.5 Output logic level V OL (5) I OUT 3.2 mA 0.5 VDC V OH (6) I OUT 3.2 mA 4.5 Output logic level V OL (6) I OUT 3.2 mA 0.5 Clock Frequency f S Sampling frequency (7) 44.1 kHz 256 f S 1.024 11.2896 12.288 System clock frequency 384 f S 1.536 16.9344 18.432 MHz 512 f S 2.048 22.5792 24.576 ADC CHARACTERISTICS Resolution Bits DC Accuracy Gain mismatch, channel-to-channel of FSR Gain error Gain drift ppm of FSR/ C Bipolar zero error High-pass filter off (8) 1.7 of FSR Bipolar zero drift High-pass filter off (8) ppm of FSR/ C (1) Pins 16, 17, 18, 22, 25, 26, 27, 28: LRCIN, BCKIN, DIN, CLKIO, MC/FMT2, MD/FMT1, ML/FMT0, RSTB (2) Pins 16, 17, 18, 22: LRCIN, BCKIN, DIN, CLKIO (Schmitt-trigger input) (3) Pins 25, 26, 27, 28: MC/FMT2, MD/FMT1, ML/FMT0, RSTB (Schmitt-trigger input, 70-k Ω internal pullup resistor) (4) Pin 20: XTI (5) Pins 19, 22: DOUT, CLKIO (6) Pin 21: XTO (7) Refer to Application Bulletin SBAA033 for information relating to operation at lower sampling frequencies. (8) High-pass filter disabled (PCM3000 only) to measure dc offset

www.ti.com PCM3000 PCM3001 SBAS055A OCTOBER 2000 REVISED OCTOBER 2004 ELECTRICAL CHARACTERISTICS (continued) All specifications at T A V DD V CC f S 44.1 kHz, SYSCLK 384 f CLKIO input, and 18-bit data, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Dynamic Performance (9) f kHz, V IN 0.5 dB THD+N dB f kHz, V IN dB Dynamic range f kHz, A-weighted dB Signal-to-noise ratio f kHz, A-weighted dB Channel separation dB Digital Filter Performance Pass band 0.454 f S Hz Stop band 0.583 f S Hz Pass-band ripple 0.05 dB Stop-band attenuation dB Delay time (latency) 17.4/f S s Digital High-Pass Filter Response Cutoff frequency dB 0.019 f S mHz ANALOG INPUT Voltage range dB (full scale) 2.9 Vp-p Center voltage 2.1 VDC Input impedance k Ω Antialiasing Filter Cutoff frequency dB, C EXT 470 pF 170 kHz DAC CHARACTERISTICS Resolution Bits DC Accuracy Gain mismatch, channel-to-channel of FSR Gain error of FSR Gain drift ppm of FSR/ C Bipolar zero error of FSR Bipolar zero drift ppm of FSR/ C Dynamic Performance (9) V OUT dB (full scale) THD+N dB V OUT dB Dynamic range EIAJ A-weighted dB Signal-to-noise ratio (idle channel) EIAJ A-weighted dB Channel separation dB Digital Filter Performance Pass band 0.445 f S Hz Stop band 0.555 f S Hz Pass-band ripple 0.17 dB Stop-band attenuation dB Delay time 11.1/f S s (9) f IN kHz, using the System Two audio measurement system by Audio Precision rms mode with 20-kHz LPF, 400-Hz HPF used for performance calculation or measurement.

www.ti.com ABSOLUTE MAXIMUM RATINGS PCM3000 PCM3001 SBAS055A OCTOBER 2000 REVISED OCTOBER 2004 ELECTRICAL CHARACTERISTICS (continued) All specifications at T A V DD V CC f S 44.1 kHz, SYSCLK 384 f CLKIO input, and 18-bit data, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Analog Output Voltage range 0.62 V CC Vp-p Center voltage 0.5 V CC VDC Load impedance AC load k Ω Analog Low-Pass Filter Frequency response f kHz 0.16 dB POWER SUPPLY REQUIREMENTS V CC 4.5 5.5 VDC Voltage range V DD 4.5 5.5 VDC I CC I DD (10) Supply current V CC V DD V mA Power dissipation V CC V DD V 160 250 mW TEMPERATURE RANGE T A Operation C T stg Storage 125 C θ JA Thermal resistance 100 C/W (10) With no load on XTO and CLKIO PACKAGE/ORDERING INFORMATION PACKAGE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE QUANTITY CODE MARKING NUMBER MEDIA PCM3000E Rails PCM3000E PCM3000E PCM3000E/2K Tape and reel 2000 28-pin SSOP DB PCM3001E Rails PCM3001E PCM3001E PCM3001E/2K Tape and reel 2000 over operating free-air temperature range (unless otherwise noted) Supply voltage: V DD V CC V CC 0.3 V to 6.5 V Supply voltage differences 0.1 V GND voltage differences 0.1 V Digital input voltage 0.3 to V DD 0.3 6.5 V Analog input voltage 0.3 to V CC V CC 0.3 6.5 V Power dissipation 300 mW Input current (any pins except supplies) mA Operating temperature C to C Storage temperature C to 125 C Lead temperature, soldering 260 s Package temperature (IR reflow, peak) 235 C

www.ti.com RECOMMENDED OPERATING CONDITIONS PCM3000 PCM3001 SBAS055A OCTOBER 2000 REVISED OCTOBER 2004 over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Analog supply voltage, V CC V CC 4.5 5.5 VDC Digital supply voltage, V DD 4.5 5.5 VDC Analog input voltage, full scale dB) 2.9 Vp-p Digital input logic family TTL System clock 8.192 24.576 MHz Digital input clock frequency Sampling clock kHz Analog output load resistance k Ω Analog output load capacitance pF Digital output load capacitance pF Operating free-air temperature, T A C

www.ti.com VINL VCC1 AGND1 VREFL VREFR VINR CINPR CINNR CINNL CINPL VCOM VOUTR AGND2 VCC2 RSTB ML MD MC DGND V DD CLKIO XTO XTI DOUT DIN BCKIN LRCIN V OUTL PCM3000 (TOP VIEW) P0007-01 VINL VCC1 AGND1 VREFL VREFR VINR CINPR CINNR CINNL CINPL VCOM VOUTR AGND2 VCC2 RSTB FMT0 FMT1 FMT2 DGND V DD CLKIO XTO XTI DOUT DIN BCKIN LRCIN V OUTL PCM3001 (TOP VIEW) PCM3000 PCM3001 SBAS055A OCTOBER 2000 REVISED OCTOBER 2004 PIN CONFIGURATION PCM3000/3001 PIN ASSIGNMENTS PCM3000 NAME PIN I/O

DESCRIPTION

I Bit clock input (1) C IN NL ADC antialias filter capacitor Lch C IN NR ADC antialias filter capacitor Rch C IN PL ADC antialias filter capacitor (+), Lch C IN PR ADC antialias filter capacitor (+), Rch CLKIO I/O Buffered oscillator output or external clock input (1) DGND Digital ground DIN I Data input (1) DOUT O Data output LRCIN I Sample rate clock input S (1) MC I Serial mode control, bit clock MD I Serial mode control, data ML I Serial mode control, strobe pulse RSTB I Reset, active-low (1) (2) V CC ADC analog power supply V CC DAC analog power supply V DD Digital power supply VCOM DAC output common V IN L I ADC analog input, Lch V IN R I ADC analog input, Rch V OUT L O DAC analog output, Lch V OUT R O DAC analog output, Rch V REF L ADC input reference, Lch V REF R ADC input reference, Rch (1) Schmitt-trigger input (2) With 70-k Ω typical internal pullup resistor

www.ti.com PCM3000 PCM3001 SBAS055A OCTOBER 2000 REVISED OCTOBER 2004 PIN ASSIGNMENTS PCM3000 (continued) NAME PIN I/O I Oscillator input XTO O Oscillator output PIN ASSIGNMENTS PCM3001 NAME PIN I/O I Bit clock input (1) C IN NL ADC antialias filter capacitor Lch C IN NR ADC antialias filter capacitor Rch C IN PL ADC antialias filter capacitor (+), Lch C IN PR ADC antialias filter capacitor (+), Rch CLKIO I/O Buffered oscillator output or external clock input (1) DGND Digital ground DIN I Data input (1) DOUT O Data output FMT0 I Audio data format control (1) (2) FMT1 I Audio data format control (1) (2) FMT2 I Audio data format control (1) (2) LRCIN I Sample rate clock input S (1) RSTB I Reset, active-low (1) (2) V CC ADC analog power supply V CC DAC analog power supply V DD Digital power supply VCOM DAC output common V IN L I ADC analog input, Lch V IN R I ADC analog input, Rch V OUT L O DAC analog output, Lch V OUT R O DAC analog output, Rch V REF L ADC input reference, Lch V REF R ADC input reference, Rch XTI I Oscillator input XTO O Oscillator output (1) Schmitt-trigger input (2) With 70-k Ω typical internal pullup resistor

www.ti.com TYPICAL PERFORMANCE CURVES OF ADC SECTION 0.002 0.004 0.006 0.008 0.010 −25 0 25 50 75 100 TA − Free-Air Temperature − ° C THD+N − Total Harm. Dist. + Noise at FS − % FS −60 dB G001 THD+N − Total Harm. Dist. + Noise at −60 dB − % 0.002 0.004 0.006 0.008 0.010 VCC − Supply Voltage − V THD+N − Total Harm. Dist. + Noise at FS − % THD+N − Total Harm. Dist. + Noise at −60 dB − % G002 −60 dB FS VCC − Supply Voltage − V Dynamic Range − dB SNR − Signal-to-Noise Ratio − dB G004 Dynamic Range SNR 0.002 0.004 0.006 0.008 0.010 System Clock THD+N − Total Harm. Dist. + Noise at FS − % G003 THD+N − Total Harm. Dist. + Noise at −60 dB − % 512 fS256 fS 384 fS 44.1 kHz FS −60 dB 48 kHz 48 kHz 44.1 kHz PCM3000 PCM3001 SBAS055A OCTOBER 2000 REVISED OCTOBER 2004 All specifications at T A V CC V DD f IN kHz, f S 44.1 kHz, 18-bit data, V IN 2.9 Vp-p, and SYSCLK 384 f S unless otherwise noted THD+N THD+N vs vs TEMPERATURE POWER SUPPLY Figure Figure THD+N SNR AND DYNAMIC RANGE vs vs SYSTEM CLOCK AND SAMPLING FREQUENCY POWER SUPPLY Figure Figure

www.ti.com 0.002 0.004 0.006 0.008 0.010 Resolution THD+N − Total Harm. Dist. + Noise at FS − % G005 THD+N − Total Harm. Dist. + Noise at −60 dB − % −60 dB 18-Bit16-Bit FS TYPICAL PERFORMANCE CURVES OF DAC SECTION 0.002 0.004 0.006 0.008 0.010 −25 0 25 50 75 100 TA − Free-Air Temperature − ° C THD+N − Total Harm. Dist. + Noise at FS − %FS G006 THD+N − Total Harm. Dist. + Noise at −60 dB − % −60 dB 0.002 0.004 0.006 0.008 0.010 VCC − Supply Voltage − V THD+N − Total Harm. Dist. + Noise at FS − % THD+N − Total Harm. Dist. + Noise at −60 dB − % G007 −60 dB FS PCM3000 PCM3001 SBAS055A OCTOBER 2000 REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES OF ADC SECTION (continued) All specifications at T A V CC V DD f IN kHz, f S 44.1 kHz, 18-bit data, V IN 2.9 Vp-p, and SYSCLK 384 f S unless otherwise noted THD+N vs OUTPUT DATA RESOLUTION Figure All specifications at T A V CC V DD f IN kHz, f S 44.1 kHz, 18-bit data, and SYSCLK 384 f S unless otherwise noted THD+N THD+N vs vs TEMPERATURE POWER SUPPLY Figure Figure

www.ti.com 100 VCC − Supply Voltage − V Dynamic Range − dB 100 SNR − Signal-to-Noise Ratio − dB G009 Dynamic Range SNR 0.002 0.004 0.006 0.008 0.010 System Clock THD+N − Total Harm. Dist. + Noise at FS − % G008 THD+N − Total Harm. Dist. + Noise at −60 dB − % 512 fS256 fS 384 fS FS −60 dB 48 kHz 48 kHz 44.1 kHz 44.1 kHz 0.002 0.004 0.006 0.008 0.010 Resolution THD+N − Total Harm. Dist. + Noise at FS − % G010 THD+N − Total Harm. Dist. + Noise at −60 dB − % −60 dB 18-Bit16-Bit FS PCM3000 PCM3001 SBAS055A OCTOBER 2000 REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES OF DAC SECTION (continued) All specifications at T A V CC V DD f IN kHz, f S 44.1 kHz, 18-bit data, and SYSCLK 384 f S unless otherwise noted THD+N SNR AND DYNAMIC RANGE vs vs SYSTEM CLOCK AND SAMPLING FREQUENCY POWER SUPPLY Figure Figure THD+N vs INPUT DATA RESOLUTION Figure 10.

www.ti.com TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (ADCs) DECIMATION FILTER Normalized Frequency [× fS Hz] −200 −150 −100 −50 0 8 16 24 32 Amplitude − dB G011 Normalized Frequency [× fS Hz] −100 −80 −60 −40 −20 Amplitude − dB G012 Normalized Frequency [× fS Hz] −1.0 −0.8 −0.6 −0.4 −0.2 0.0 0.2 Amplitude − dB G013 PCM3000 PCM3001 SBAS055A OCTOBER 2000 REVISED OCTOBER 2004 All specifications at T A V CC V DD and SYSCLK 384 f S unless otherwise noted OVERALL CHARACTERISTICS STOP-BAND ATTENUATION CHARACTERISTICS Figure 11. Figure 12. PASS-BAND RIPPLE CHARACTERISTICS Figure 13.

www.ti.com HIGH-PASS FILTER Normalized Frequency [× fS/1000 Hz] −1.0 −0.8 −0.6 −0.4 −0.2 0.0 0.2 0 1 2 3 4 Amplitude − dB G014 ANTIALIASING FILTER −1.0 −0.8 −0.6 −0.4 −0.2 0.0 0.2 f − Frequency − Hz Amplitude − dB 1 10 100 100k1k 10k G015 470 pF 1000 pF −50 −40 −30 −20 −10 f − Frequency − Hz Amplitude − dB 1 10 100 10M1k 10k G016 100k 1M 470 pF 1000 pF PCM3000 PCM3001 SBAS055A OCTOBER 2000 REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (ADCs) (continued) All specifications at T A V CC V DD and SYSCLK 384 f S unless otherwise noted HIGH-PASS FILTER RESPONSE Figure 14. ANTIALIASING FILTER PASS-BAND ANTIALIASING FILTER OVERALL FREQUENCY RESPONSE EXT 470 pF, 1000 pF) FREQUENCY RESPONSE EXT 470 pF, 1000 pF) Figure 15. Figure 16.

www.ti.com TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (DACs) DIGITAL FILTER −100 −80 −60 −40 −20 Level − dB f − Frequency − Hz 0.4536 fS G017 0 1.3605 fS 2.2675 fS 4.0815 fS3.1745 fS −1.0 −0.8 −0.6 −0.4 −0.2 0.0 Level − dB f − Frequency − Hz 0.1134 fS G018 0 0.2268 fS 0.3402 fS 0.4535 fS DE-EMPHASIS FILTER −12 −10 Level − dB f − Frequency − Hz G019 0 25k10k 15k 20k −0.6 −0.4 −0.2 0.0 0.2 0.4 0.6 Error − dB f − Frequency − Hz 3628 G020 0 145127256 10884 PCM3000 PCM3001 SBAS055A OCTOBER 2000 REVISED OCTOBER 2004 All specifications at T A V CC V DD and SYSCLK 384 f S unless otherwise noted OVERALL FREQUENCY CHARACTERISTIC PASS-BAND RIPPLE CHARACTERISTIC DE-EMPHASIS FREQUENCY RESPONSE (32 kHz) DE-EMPHASIS ERROR (32 kHz)

www.ti.com −12 −10 Level − dB f − Frequency − Hz G021 0 25k10k 15k 20k −0.6 −0.4 −0.2 0.0 0.2 0.4 0.6 Error − dB f − Frequency − Hz 4999.8375 G022 0 19999.359999.675 14999.5125 −12 −10 Level − dB f − Frequency − Hz G023 0 25k10k 15k 20k −0.6 −0.4 −0.2 0.0 0.2 0.4 0.6 Error − dB f − Frequency − Hz 5442 G024 0 2176810884 16326 PCM3000 PCM3001 SBAS055A OCTOBER 2000 REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (DACs) (continued) All specifications at T A V CC V DD and SYSCLK 384 f S unless otherwise noted DE-EMPHASIS FREQUENCY RESPONSE (44.1 kHz) DE-EMPHASIS ERROR (44.1 kHz) DE-EMPHASIS FREQUENCY RESPONSE (48 kHz) DE-EMPHASIS ERROR (48 kHz)

www.ti.com ANALOG LOW-PASS FILTER −60 −55 −50 −45 −40 −35 −30 −25 −20 −15 −10 f − Frequency − Hz Level − dB 10 100 10M1k 10k G026 100k 1M −1.0 −0.5 0.0 0.5 1.0 f − Frequency − Hz Level − dB 20 100 24k1k 10k G025 PCM3000 PCM3001 SBAS055A OCTOBER 2000 REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (DACs) (continued) All specifications at T A V CC V DD and SYSCLK 384 f S unless otherwise noted INTERNAL ANALOG FILTER FREQUENCY RESPONSE INTERNAL ANALOG FILTER FREQUENCY RESPONSE (20 Hz kHz, EXPANDED SCALE) (10 Hz MHz)

www.ti.com MC(FMT2)(1) MD(FMT1)(1) Analog Front-End Circuit LRCINVINL Reference VREFL VREFR VINR Delta-Sigma Modulator Delta-Sigma Modulator Decimation and High-Pass Filter Power Supply Reset Serial Data Interface DOUT (+) (−) (−) (+) Mode Control Interface Analog Front-End Circuit Decimation and High-Pass Filter ADC BCKIN DIN Analog Low-Pass Filter VOUTL Multilevel Delta-Sigma Modulator Interpolation Filter 8× Oversampling Analog Low-Pass Filter VOUTR Multilevel Delta-Sigma Modulator Interpolation Filter 8× Oversampling DAC ML(FMT0)(1) RSTB Clock/OSC Manager CLKIOAGND2 VCC2 AGND1 VCC1 DGND VDD B0004-05 CINNL CINPL CINNR CINPR VCOM XTO XTI Loop Control PCM3000 PCM3001 SBAS055A OCTOBER 2000 REVISED OCTOBER 2004 Block Diagram

www.ti.com 15 kΩ 1 kΩ 470 pF 910 VINL VREFL CINPL CINNL Delta-Sigma Modulator (+) VREF 2.2 µF 4.7 µF + (−) 1 kΩ S0011-04 PCM AUDIO INTERFACE PCM3000 PCM3001 SBAS055A OCTOBER 2000 REVISED OCTOBER 2004 Figure 17. Analog Front-End (Single-Channel) The four-wire digital audio interface for the PCM3000/3001 is on LRCIN (pin 16), BCKIN (pin 17), DIN (pin 18), and DOUT (pin 19). The PCM3000/3001 can operate with seven different data formats. For the PCM3000, these formats are selected through program register in the software mode. For the PCM3001, data formats are selected by pin-strapping the three format pins. Figure Figure Figure and Figure illustrate the audio data input/output format. Figure shows the audio data input/output timing. The PCM3000/3001 can accept 32, 48, or bit clocks (BCKIN) during one clock of LRCIN. Only formats and can be selected when bit clocks/LRCIN are applied.

www.ti.com DAC: 16-Bit, MSB-First, Right-Justified FORMAT 0: FMT[2:0] = 000 LRCIN Right-ChannelLeft-Channel BCKIN DIN MSB LSB MSB LSB 321 16151416 321 161514 BCKIN LRCIN Right-ChannelLeft-Channel DOUT 114 15 16321 MSB LSB MSB LSB 14 15 16321 ADC: 16-Bit, MSB-First, Left-Justified LRCIN Right-ChannelLeft-Channel BCKIN DIN MSB LSB MSB LSB 16 17 18321 16 17 1832118 DAC: 18-Bit, MSB-First, Right-Justified FORMAT 1: FMT[2:0] = 001 BCKIN LRCIN Right-ChannelLeft-Channel DOUT 116 17 18321 MSB LSB MSB LSB 16 17 18321 ADC: 18-Bit, MSB-First, Left-Justified T0016-07 PCM3000 PCM3001 SBAS055A OCTOBER 2000 REVISED OCTOBER 2004 Figure 18. Audio Data Input/Output Format (Formats and

www.ti.com DAC: 16-Bit, MSB-First, Right-Justified FORMAT 2: FMT[2:0] = 010 LRCIN Right-ChannelLeft-Channel BCKIN DIN MSB LSB MSB LSB 321 16151416 321 161514 ADC: 16-Bit, MSB-First, Right-Justified LRCIN Right-ChannelLeft-Channel BCKIN DIN MSB LSB MSB LSB 16 17 18321 16 17 1832118 DAC: 18-Bit, MSB-First, Right-Justified FORMAT 3: FMT[2:0] = 011 ADC: 18-Bit, MSB-First, Right-Justified T0016-08 LRCIN Right-ChannelLeft-Channel BCKIN DOUT MSB LSB MSB LSB 321 16151416 321 161514 LRCIN Right-ChannelLeft-Channel BCKIN DOUT MSB LSB MSB LSB 16 17 18321 16 17 1832118 PCM3000 PCM3001 SBAS055A OCTOBER 2000 REVISED OCTOBER 2004 Figure 19. Audio Data Input/Output Format (Formats and

www.ti.com DAC: 18-Bit, MSB-First, Left-Justified FORMAT 4: FMT[2:0] = 100 ADC: 18-Bit, MSB-First, Left-Justified DAC: 18-Bit, MSB-First, I2S FORMAT 5: FMT[2:0] = 101 T0016-09 BCKIN LRCIN Right-ChannelLeft-Channel DIN 116 17 18321 MSB LSB MSB LSB 16 17 18321 BCKIN LRCIN Right-ChannelLeft-Channel DOUT 116 17 18321 MSB LSB MSB LSB 16 17 18321 LRCIN Right-ChannelLeft-Channel BCKIN DIN MSB LSB MSB LSB 16 17 18321 16 17 18321 LRCIN Right-ChannelLeft-Channel BCKIN DOUT MSB LSB MSB LSB 16 17 18321 16 17 18321 ADC: 18-Bit, MSB-First, I2S PCM3000 PCM3001 SBAS055A OCTOBER 2000 REVISED OCTOBER 2004 Figure 20. Audio Data Input/Output Format (Formats and

www.ti.com DAC: 16-Bit, MSB-First, DSP-Frame FORMAT 6: FMT[2:0] = 110 LRCIN Right-ChannelLeft-Channel BCKIN DIN MSB LSB MSB LSB 321 16151416 321 161514 ADC: 16-Bit, MSB-First, DSP-Frame T0016-10 LRCIN Right-ChannelLeft-Channel BCKIN DOUT MSB LSB MSB LSB 321 16151416 321 161514 1 PCM3000 PCM3001 SBAS055A OCTOBER 2000 REVISED OCTOBER 2004 Figure 21. Audio Data Input/Output Format (Format

www.ti.com BCKIN LRCIN DIN t(BCH) t(BCL) t(LRP) t(LB) t(BCY) 1.4 V t(BL) DOUT t(BDO) t(LDO)

0.5 VDD

t(DIS) t(DIH) 1.4 V 1.4 V T0021−02 SYSTEM CLOCK PCM3000 PCM3001 SBAS055A OCTOBER 2000 REVISED OCTOBER 2004 BCKIN pulse cycle time t (BCY) 300 ns (min) BCKIN pulse duration, HIGH t (BCH) 120 ns (min) BCKIN pulse duration, LOW t (BCL) 120 ns (min) BCKIN rising edge to LRCIN edge t (BL) ns (min) LRCIN edge to BCKIN rising edge t (LB) ns (min) LRCIN pulse duration t (LRP) t (BCY) (min) DIN setup time t (DIS) ns (min) DIN hold time t (DIH) ns (min) DOUT delay time to BCKIN falling edge t (BDO) ns (max) DOUT delay time to LRCIN edge t (LDO) ns (max) Rising time of all signals t (RISE) ns (max) Falling time of all signals t (FALL) ns (max Figure 22. Audio Data Input/Output Timing The system clock for the PCM3000/3001 must be either 256 f S 384 f S or 512 f S where f S is the audio sampling frequency. The system clock can be either a crystal oscillator placed between XTI (pin 20) and XTO (pin 21), or an external clock input. If an external clock is used, the clock is provided to either XTI or CLKIO (pin 22), and XTO is open. The PCM3000/3001 has an XTI clock detection circuit which senses if an XTI clock is operating. When the external clock is delivered to XTI, CLKIO is a buffered output of XTI. When XTI is connected to ground, the external clock must be tied to CLKIO. For best performance, the external-clock-input-2 circuit in Figure is recommended. The PCM3000/3001 also has a system-clock detection circuit which automatically senses if the system clock is operating at 256 f S 384 f S or 512 f S When a 384-f S or 512-f S system clock is used, the clock is divided into 256 f S automatically. The 256-f S clock is used to operate the digital filters and the modulators. Table lists the relationship of typical sampling frequencies and system clock frequencies, and Figure and Figure illustrate the typical system clock connections and external system clock timing.

www.ti.com CLKIO Clock Divider S0017−01 R 256-fS Internal System Clock PCM3000/3001 XTI XTO XtalC1 Crystal Resonator Connection (Xtal must be fundamental mode, parallel resonant) CLKIO Clock Divider R 256-fS Internal System Clock PCM3000/3001 XTI XTO External Clock (CMOS I/F) External Clock Input 1 : (XTO is open) CLKIO Clock Divider R 256-fS Internal System Clock PCM3000/3001 XTI XTO External Clock Input 2 : (XTO is open) External Clock (TTL I/F) C1 = C2 = 10 to 33 pF PCM3000 PCM3001 SBAS055A OCTOBER 2000 REVISED OCTOBER 2004 Figure 23. System Clock Connections

www.ti.com t(CLKIH) XTI or CLKIO 1.4 V 3.2 V t(CLKIL) T0005-06 XTI 0.8 V 2.0 V CLKIO POWER-ON RESET

1024 System Clock Periods

4.4 V 4.0 V 3.6 V VDD Internal Reset System Clock (XTI or CLKIO) T0014-04

3 Clocks Minimum

(kHz) SYSTEM CLOCK FREQUENCY (MHz) 256 f S 384 f S 512 f S 8.1920 12.2880 16.3840 44.1 11.2896 16.9344 22.5792 12.2880 18.4320 24.5760 System clock pulse duration, HIGH t (CLKIH) ns (min) System clock pulse duration, LOW t (CLKIL) ns (min) Figure 24. External System Clock Timing The PCM3000/3001 has internal power-on reset circuitry. Power-on reset occurs when the system clock (XTI or CLKIO) is active and V DD For the PCM3001, the system clock must complete a minimum of complete cycles prior to V DD V to ensure proper reset operation. The initialization sequence requires 1024 system cycles for completion, as shown in Figure Figure shows the state of the DAC and ADC outputs during and after the reset sequence. Figure 25. Internal Power-On Reset Timing

www.ti.com T0019-03 ResetInternal Reset DAC VOUT 32/fS Reset Removal or Power Down(1) Off ADC DOUT Zero Data Normal Data(2) VCOM (0.5 VCC2) 4096/fS Zero Data Ready/Operation EXTERNAL RESET t(RST) Reset Removal (XTI or CLKIO) t(RST) = 40 ns (min) Reset T0015-04 RSTB Pulse Duration SYNCHRONIZATION WITH THE DIGITAL AUDIO SYSTEM PCM3000 PCM3001 SBAS055A OCTOBER 2000 REVISED OCTOBER 2004 (1) Power down is for PCM3000 only. (2) The HPF transient response (exponentially attenuated signal from 1.5% dc with 200-ms time constant) appears initially. Figure 26. DAC Output and ADC Output for Reset and Power Down The PCM3000/3001 includes a reset input, RSTB (pin 28). As shown in Figure the external reset signal must drive RSTB low for a minimum of nanoseconds while the system clock is active in order to initiate the reset sequence. Initialization starts on the rising edge of RSTB, and requires 1024 system clock cycles for completion. Figure shows the state of the DAC and ADC outputs during and after the reset sequence. Figure 27. External Forced-Reset Timing The PCM3000/3001 operates with LRCIN synchronized to the system clock. The codec does not require any specific phase relationship between LRCIN and the system clock, but there must be synchronization of LRCIN and the system clock. If the synchronization between the system clock and LRCIN changes more than bit clocks (BCKIN) during one sample (LRCIN) period because of phase jitter on LRCIN, internal operation of the DAC stops within 1/f S and the analog output is forced to bipolar zero CC 2/2) until the system clock is resynchronized to LRCIN. Internal operation of the ADC also stops within 1/f S and the digital output codes are set to bipolar zero until resynchronization occurs. If LRCIN is synchronized within or fewer bit clocks to the system clock, operation remains normal. Figure illustrates the effects on the output when synchronization is lost. Before the outputs are forced to bipolar zero <1/f S seconds), the outputs are not defined and some noise may occur. During the transitions between normal data and undefined states, the output has discontinuities, which cause output noise.

www.ti.com Within 1/fS Normal DataVCOM (0.5 VCC2) Undefined DataNormal Data SynchronousAsynchronousSynchronous ResynchronizationSynchronization Lost DAC VOUT State of Synchronization T0020-04 Normal Data(1)Zero DataNormal DataADC DOUT Undefined Data 32/fS Undefined Data 22.2/fS OPERATIONAL CONTROL B8B15 ML MC MD B9B10B11B12B13B14 B0B7 B1B2B3B4B5B6 T0023-01 PCM3000 PCM3001 SBAS055A OCTOBER 2000 REVISED OCTOBER 2004 (1) The HPF transient response (exponentially attenuated signal from 1.5% dc with 200-ms time constant) appears initially. Figure 28. DAC Output and ADC Output For Loss of Synchronization The PCM3000 can be controlled in the software mode with a three-wire serial interface on MC (pin 25), MD (pin 26), and ML (pin 27). Table indicates selectable functions, and Figure and Figure illustrate control data input format and timing. The PCM3001 only allows for control of data format. Table Selectable Functions FUNCTION ADC/DAC DEFAULT (PCM3000) Audio data format selectable formats) ADC/DAC DAC: 16-bit, MSB-first, right-justified ADC: 16-bit, MSB-first, left-justified LRCIN polarity ADC/DAC Left/right high/low Loopback control ADC/DAC OFF Left-channel attenuation DAC dB Right-channel attenuation DAC dB Attenuation control DAC Left channel and right channel individual control Infinite zero detection DAC OFF DAC output control DAC Output enabled Soft mute control DAC OFF De-emphasis (OFF, kHz, 44.1 kHz, kHz) DAC OFF Power-down control ADC OFF High-pass filter operation ADC ON Figure 29. Control Data Input Format

www.ti.com t(MCH) ML LSB t(MCL) t(MHH) t(MCY) t(MDH) t(MDS) MC MD t(MLS) t(MLL) t(MLH) T0024-01 1.4 V 1.4 V 1.4 V MAPPING OF PROGRAM REGISTERS PROGRAM REGISTER (PCM3000) PCM3000 PCM3001 SBAS055A OCTOBER 2000 REVISED OCTOBER 2004 MC pulse cycle time t (MCY) 100 ns (min) MC pulse duration, LOW t (MCL) ns (min) MC pulse duration, HIGH t (MCH) ns (min) MD setup time t (MDS) ns (min) MD hold time t (MDH) ns (min) ML low-level time t (MLL) ns SYSCLK (1) (min) ML high-level time t (MHH) ns SYSCLK (1) (min) ML setup time (2) t (MLS) ns (min) ML hold time (3) t (MLH) ns (min) SYSCLK (period): f S or f S or f S (1) SYSCK: system clock cycle (2) ML rising edge to the next MC rising edge (3) MC rising edge for LSB-to-ML rising edge Figure 30. Control Data Input Timing B15 B14 B13 B12 B11 B10 REGISTER res res res res res LDL AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0 REGISTER res res res res res LDR AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0 REGISTER res res res res res PDWN BYPS res ATC IZD OUT DEM1 DEM0 MUT REGISTER res res res res res res res res LOP FMT2 FMT1 FMT0 LRP res NOTE: res indicates a reserved bit, which should be set to The software mode allows the user to control special functions. The PCM3000 special functions are controlled using four program registers which are each bits long. There are four distinct registers, with bits and determining which register is in use. Table describes the functions of the four registers.

www.ti.com PCM3000 PCM3001 SBAS055A OCTOBER 2000 REVISED OCTOBER 2004 Table Functions of the Registers REGISTER NAME REGISTER BIT(S) BIT NAME Reserved, should be set to A[1:0] Register address LDL DAC attenuation data load control for Lch AL[7:0] DAC attenuation data for Lch Register res Reserved, should be set to A[1:0] Register address LDR DAC attenuation data load control for Rch AR[7:0] DAC attenuation data for Rch Register res Reserved, should be set to A[1:0] Register address PDWN ADC power-down control BYPS ADC high-pass filter bypass control res Reserved, should be set to ATC DAC attenuation data mode control IZD DAC infinite zero detection circuit control OUT DAC output enable control DEM[1:0] DAC de-emphasis control MUT DAC Lch and Rch soft mute control Register res Reserved, should be set to A[1:0] Register address res Reserved, should be set to LOP ADC/DAC analog loopback control FMT[2:0] ADC/DAC audio data format selection LRP ADC/DAC polarity of LR-clock selection res Reserved, should be set to PROGRAM REGISTER res: Bits 15:11 Reserved These bits are reserved and should be set to A[1:0]: Bits 10:9 Register Address These bits definte the address for REGISTER Register LDL: Bit DAC Attenuation Data Load Control for Left Channel This bit is used to simultaneously set the analog outputs of the left and right channels. The output level is controlled by AL[7:0] attenuation data when this bit is set to When set to the new attenuation data is stored into a register, and the output level remains at the previous attenuation level. The LDR bit in REGISTER has the equivalent function as LDL. When either LDL or LDR is set to the output levels of the left and right channels are simultaneously controlled.

www.ti.com PCM3000 PCM3001 SBAS055A OCTOBER 2000 REVISED OCTOBER 2004 AL[7:0]: Bits 7:0 DAC Attenuation Data for Left Channel AL7 and AL0 are the MSB and LSB, respectively. The attenuation level (ATT) is given by ATT log (AL[7:0]/256) (dB), except AL[7:0] FFh AL[7:0] ATTENUATION LEVEL 00h dB (mute) 01h 48.16 dB FEh 0.07 dB FFh dB (default) PROGRAM REGISTER res: Bits 15:11 Reserved These bits are reserved and should be set to A[1:0]: Bits 10:9 Register Address These bits definte the address for REGISTER Register LDR: Bit DAC Attenuation Data Load Control for Right Channel This bit is used to simultaneously set the analog outputs of the left and right channels. The output level is controlled by AR[7:0] attenuation data when this bit is set to When set to the new attenuation data is stored into a register, and the output level remains at the previous attenuation level. The LDL bit in REGISTER has the equivalent function as LDR. When either LDL or LDR is set to the output levels of the left and right channels are simultaneously controlled. AR[7:0]: Bits 7:0 DAC Attenuation Data for Right Channel AR7 and AR0 are the MSB and LSB, respectively. The attenuation level (ATT) is given by ATT log (AR[7:0]/256) (dB), except AR[7:0] FFh AR[7:0] ATTENUATION LEVEL 00h dB (mute) 01h 48.16 dB FEh 0.07 dB FFh dB (default) PROGRAM REGISTER res: Bits 15:11 Reserved These bits are reserved and should be set to A[1:0]: Bits 10:9 Register Address These bits define the address for REGISTER Register

www.ti.com PCM3000 PCM3001 SBAS055A OCTOBER 2000 REVISED OCTOBER 2004 PDWN: Bit ADC Power-Down Control This bit places the ADC section in a power-down mode, forcing the output data to all zeroes. This has no effect on the DAC section or the

contents

registers. PDWN Power-down mode disabled (default) Power-down mode enabled BYPS: Bit ADC High-Pass Filter Bypass Control This bit enables or disables the high-pass filter for the ADC. BYPS High-pass filter enabled (default) High-pass filter disabled (bypassed) res: Bit Reserved This bit is reserved and should be set to ATC: Bit DAC Attenuation Data Mode Control When set to the REGISTER attenuation data is used for both DAC channels. In this case, the REGISTER attenuation data is ignored. ATC Individual channel attenuation data control (default) Common channel attenuation data control IZD: Bit DAC Infinite Zero Detection Circuit Control This bit enables the infinite zero detection circuit in the PCM3000. When enabled, this circuit disconnects the analog output amplifier from the delta-sigma DAC when the input is continuously zero for 65,536 consecutive cycles of BCKIN. IZD Infinite zero detection disabled (default) Infinite zero detection enabled OUT: Bit DAC Output Enable Control When set to the outputs are forced to V CC (bipolar zero). In this case, all registers in the PCM3000 hold the present data. Therefore, when set to the outputs return to the previous programmed state. OUT DAC outputs enabled (default normal operation) DAC outputs disabled (forced to BPZ) DEM[1:0]: Bits 2:1 DAC De-Emphasis Control These bits select the de-emphasis mode as shown. DEM1 DEM0 De-emphasis OFF (default) De-emphasis kHz ON De-emphasis 44.1 kHz ON De-emphasis kHz ON

www.ti.com PCM3000 PCM3001 SBAS055A OCTOBER 2000 REVISED OCTOBER 2004 MUT: Bit DAC Soft Mute Control When set to both left- and right-channel DAC outputs are muted at the same time. This muting is done by attenuating the data in the digital filter, so that there is no audible click noise when soft mute is turned on. MUT Mute disabled (default) Mute enabled PROGRAM REGISTER res: Bits 15:11 Reserved These bits are reserved and should be set to A[1:0]: Bits 10:9 Register Address These bits define the address for REGISTER Register res: Bits 8:6 Reserved These bits are reserved and should be set to LOP: Bit ADC to DAC Loopback Control When this bit is set to the ADC audio data is sent directly to the DAC. The data format defaults to I DOUT is still available in loopback mode. LOP Loopback disabled (default) Loopback enabled FMT[2:0]: Bits 4:2 Audio Data Format Select These bits determine the input and output audio data formats. (default: FMT[2:0] 000 b FM2 FMT1 FMT0 DAC DATA FORMAT ADC DATA FORMAT 16-bit, MSB-first, right-justified 16-bit, MSB-first, left-justified 18-bit, MSB-first, right-justified 18-bit, MSB-first, left-justified 16-bit, MSB-first, right-justified 16-bit, MSB-first, right-justified 18-bit, MSB-first, right-justified 18-bit, MSB-first, right-justified 16-/18-bit, MSB-first, left-justified 18-bit, MSB-first, left-justified 16-/18-bit, MSB-first, I S 18-bit, MSB-first, I S 16-bit, MSB-first, DSP-frame 16-bit, MSB-first, DSP-frame Reserved Reserved LRP: Bit ADC-to-DAC LRCK Polarity Select Polarity of LRCIN applies only to formats through LOP Left channel is right channel is L (default). Left channel is right channel is res: Bit Reserved This bit is reserved and should be set to PCM3001 DATA FORMAT CONTROL The input and output data formats are controlled by pins (FMT0), (FMT1), and (FMT2). Set these pins to the same values shown for the bit-mapped PCM3000 controls in program register

www.ti.com THEORY OF OPERATION ADC SECTION 1st SW-CAP Integrator Analog In X(z) + − 2nd SW-CAP Integrator 3rd SW-CAP Integrator + − 4th SW-CAP Integrator + + + ++ + + + 5th SW-CAP Integrator Digital Out Y(z) Comparator Qn(z) H(z) 1-Bit DAC STF(z) = H(z) / [1 + H(z)] NTF(z) = 1 / [1 + H(z)] Y(z) = STF(z) * X(z) + NTF(z) * Qn(z) Signal Transfer Function Noise Transfer Function B0005-01 DAC SECTION PCM3000 PCM3001 SBAS055A OCTOBER 2000 REVISED OCTOBER 2004 The PCM3000/3001 ADC consists of a band-gap reference, a stereo single-to-differential converter, a fully differential 5th-order delta-sigma modulator, a decimation filter (including digital high pass), and a serial interface circuit. The block diagram in this data sheet illustrates the architecture of the ADC section. Figure shows the single-to-differential converter, and Figure illustrates the architecture of the 5th-order delta-sigma modulator and transfer functions. An internal high-precision reference with two external capacitors provides all reference voltages required by the ADC, which defines the full scale range for the converter. The internal single-to-differential voltage converter saves the space and extra parts needed for external circuitry which is required by many delta-sigma converters. The internal full-differential signal processing architecture provides a wide dynamic range and excellent power supply rejection performance. The input signal is sampled at a oversampling rate, eliminating the need for a sample-and-hold circuit, and simplifying antialias filtering requirements. The 5th-order delta-sigma noise shaper consists of five integrators which use a switched-capacitor topology, a comparator, and a feedback loop consisting of a one-bit DAC. The delta-sigma modulator shapes the quantization noise, shifting it out of the audio band in the frequency domain. The high order of the modulator enables it to randomize the modulator outputs, reducing idle tone levels. The 64-f S 1-bit data stream from the modulator is converted to 1-f S 18-bit data words by the decimation filter, which also acts as a low-pass filter to remove the shaped quantization noise. The dc components are removed by a high-pass filter function contained within the decimation filter. Figure 31. Simplified Fifth-Order Delta-Sigma Modulator The delta-sigma DAC section of the PCM3000/3001 is based on a 5-level amplitude quantizer and a 3rd-order noise shaper. This section converts the oversampled input data to a 5-level delta-sigma format. A block diagram of the 5-level delta-sigma modulator is shown in Figure This 5-level delta-sigma modulator has the advantage of improved stability and reduced clock-jitter sensitivity over the typical one-bit (2-level) delta-sigma modulator. The combined oversampling rate of the delta-sigma modulator and the internal interpolation filter is f S for a 256-f S system clock. The theoretical quantization noise performance of the 5-level delta-sigma modulator is shown in Figure

www.ti.com − Z−1 + + − Z−1 In 8 fS 18-Bit Out 64 fS + Z−1 B0008-02 5-Level Quantizer f − Frequency − kHz −150 −140 −130 −120 −110 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 5 10 15 20 25 30 Gain − dB G027 PCM3000 PCM3001 SBAS055A OCTOBER 2000 REVISED OCTOBER 2004 Figure 32. 5-Level Δ Σ Modulator Block Diagram Figure 33. Quantization Noise Spectrum

www.ti.com APPLICATION INFORMATION APPLICATION AND LAYOUT CONSIDERATIONS TYPICAL CONNECTION 470 pF 470 pF 4.7 µF 4.7 µF+2.2 µF(2) +2.2 µF(2) 10 to 33 pF 4.7 µF + Register Control Interface Reference Bias Analog Front-End Decimation Filter Interpolation Filter LPF and Buffer Digital Audio Interface CLK/OSC Manager Delta-Sigma Delta-Sigma Post Low-Pass Filter (1) (1) (1) Serial Control or Format Control Digital Audio Data Reset Line In Left-Channel +5V Line In Right-Channel Line Out Right-Channel Line Out Left-Channel S0018-01 Post Low-Pass Filter Analog Front-End LPF and Buffer POWER SUPPLY BYPASSING PCM3000 PCM3001 SBAS055A OCTOBER 2000 REVISED OCTOBER 2004 A typical connection diagram for the PCM3000/3001 is shown in Figure (1) Bypass capacitor 0.1 µ F and µ (2) The input capacitor affects the pole of the HPF. Example: 2.2 µ F sets the cutoff frequency to 4.8 Hz, with a 66-ms time constant. Figure 34. Typical Connection Diagram for PCM3000/3001 The digital and analog power-supply lines to the PCM3000/3001 should be bypassed to the corresponding ground pins with both 0.1- µ F ceramic and 10- µ F tantalum capacitors as close to the device pins as possible to maximize the performance of the ADC and DAC. Although the PCM3000/3001 has three power supply lines to optimize dynamic performance, the use of one common power supply is generally recommended to avoid unexpected latch-up or pop noise due to power-supply sequencing problems. If separate power supplies are used, back-to-back diodes between the two power sources near the device are recommended to avoid latch-up problems.

www.ti.com GROUNDING VOLTAGE INPUTS V REF INPUTS C IN P AND C IN N INPUTS VCOM INPUT SYSTEM CLOCK RSTB CONTROL PCM3000 PCM3001 SBAS055A OCTOBER 2000 REVISED OCTOBER 2004 APPLICATION INFORMATION (continued) In order to optimize dynamic performance of the PCM3000/3001, the analog and digital grounds are not internally connected. PCM3000/3001 performance is optimized with a single ground plane for all returns. It is recommended to tie all PCM3000/3001 ground pins to the analog ground plane using low-impedance connections. The PCM3000/3001 should reside entirely over this plane to avoid coupling high-frequency digital switching noise into the analog ground plane. A tantalum or aluminum electrolytic capacitor, between 2.2 µ F and µ is recommended as an ac-coupling capacitor at the inputs. Combined with the 15-k Ω characteristic input impedance, a 2.2- µ F coupling capacitor establishes a 4.8-Hz cutoff frequency for blocking dc. The input voltage range can be increased by adding a series resistor on the analog input line. This series resistor, when combined with the 15-k Ω input impedance, creates a voltage divider and enables larger input ranges. A 4.7- µ F to 10- µ F tantalum capacitor is recommended between V REF V REF and AGND1 to ensure low source impedance for the ADC references. These capacitors should be located as close as possible to the reference pins to reduce dynamic errors on the ADC reference. A 470-pF to 1000-pF film or NPO ceramic capacitor is recommended between C IN PL and C IN NL, and also between C IN PR and C IN NR to create an antialias filter that has a 170-kHz to 80-kHz cutoff frequency. These capacitors should be located as close as possible to the C IN P and C IN N pins to avoid introducing undesirable noise or dynamic errors into the delta-sigma modulator. A 4.7- µ F to 10- µ F tantalum capacitor is recommended between VCOM and AGND2 to ensure low source impedance of the DAC output common. This capacitor should located as close as possible to the VCOM pin to reduce dynamic errors on the DAC common. The quality of the system clock can influence the dynamic performance of both the ADC and DAC in the PCM3000/3001. The duty cycle, jitter, and threshold voltage at the system clock input pin should be carefully managed. When power is supplied to the part, the system clock, bit clock (BCKIN), and word clock (LCRIN) must also be supplied simultaneously. Failure to supply the audio clocks results in a power dissipation increase of up to three times normal dissipation and may degrade long-term reliability if the maximum power dissipation limit is exceeded. If capacitors greater than 4.7 µ F are used on V REF and VCOM, an external reset control with delay time corresponding to the V REF VCOM response is required.

www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) PCM3000E Active Production SSOP (DB) | 28 47 | TUBE Yes NIPDAU Level-1-260C-UNLIM - PCM3000E PCM3000E.B Active Production SSOP (DB) | 28 47 | TUBE Yes NIPDAU Level-1-260C-UNLIM See PCM3000E PCM3000E PCM3000E/2K Active Production SSOP (DB) | 28 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM - PCM3000E PCM3000E/2K.B Active Production SSOP (DB) | 28 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM See PCM3000E/2K PCM3000E PCM3001E Active Production SSOP (DB) | 28 47 | TUBE Yes NIPDAU Level-1-260C-UNLIM - PCM3001E PCM3001E.B Active Production SSOP (DB) | 28 47 | TUBE Yes NIPDAU Level-1-260C-UNLIM See PCM3001E PCM3001E PCM3001E/2K Active Production SSOP (DB) | 28 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM - PCM3001E PCM3001E/2K.B Active Production SSOP (DB) | 28 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM See PCM3001E/2K PCM3001E PCM3001E/2KG4.B Active Production SSOP (DB) | 28 2000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM See PCM3001E/2KG4 PCM3001E (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative Addendum-Page 1

www.ti.com 23-May-2025 and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCM3000E/2K SSOP DB 28 2000 336.6 336.6 28.6 PCM3001E/2K SSOP DB 28 2000 356.0 356.0 35.0 PCM3001E/2K SSOP DB 28 2000 336.6 336.6 28.6 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) PCM3000E DB SSOP 28 47 500 10.6 500 9.6 PCM3000E.B DB SSOP 28 47 500 10.6 500 9.6 PCM3001E DB SSOP 28 47 500 10.6 500 9.6 PCM3001E DB SSOP 28 47 530 10.5 4000 4.1 PCM3001E.B DB SSOP 28 47 530 10.5 4000 4.1 PCM3001E.B DB SSOP 28 47 500 10.6 500 9.6 PCM3001E/2K DB SSOP 28 2000 500 10.6 500 9.6 PCM3001E/2K.B DB SSOP 28 2000 500 10.6 500 9.6 PCM3001E/2KG4.B DB SSOP 28 2000 500 10.6 500 9.6 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C 26X 0.65 8.45 28X 0.38 0.22 8.2

7.4 TYP

0.05 MIN

0.25 GAGE PLANE 0 -8

2 MAX

B 5.6 5.0 NOTE 4 A 10.5 9.9 NOTE 3 0.95 0.55 (0.15) TYP SSOP - 2 mm max heightDB0028A SMALL OUTLINE PACKAGE 4214853/B 03/2018

0.15 C A B

0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-150. A 15 DETAIL A TYPICAL SCALE 1.500

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MAX

0.07 MIN

28X (1.85) 28X (0.45) 26X (0.65) (7) (R0.05) TYP SSOP - 2 mm max heightDB0028A SMALL OUTLINE PACKAGE 4214853/B 03/2018 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 14 15 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 28X (1.85) 28X (0.45) 26X (0.65) (7) (R0.05) TYP SSOP - 2 mm max heightDB0028A SMALL OUTLINE PACKAGE 4214853/B 03/2018 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 14 15

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