PCM3000

PCM3000 BURR-BROWN | Alldatasheet

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Technical content

1 PCM3000/3001

49% FPO PCM3000 PCM3001 PCM3000E PCM3001E Stereo Audio CODEC 18-BITS, SERIAL INTERFACE TM

FEATURES

l MONOLITHIC 18-BIT ΔΣ ADC AND DAC l 16- OR 18-BIT INPUT/OUTPUT DATA l STEREO ADC: Single-ended Voltage Input 64X Oversampling High Performance: –88dB THD+N 94dB SNR 94dB Dynamic Range Digital High-Pass Filter l STEREO DAC: Single-ended Voltage Output Analog Low Pass Filter 64X Oversampling High Performance: –90dB THD+N 98dB SNR 97dB Dynamic Range l SPECIAL FEATURES (PCM3000): Digital De-emphasis Digital Attenuation (256 Steps) Soft Mute Analog Loop Back l SAMPLE RATE: Up to 48kHz l SYSTEM CLOCK: 256f S, 384fS, 512fS l SINGLE +5V POWER SUPPLY l SMALL PACKAGE: SSOP-28

DESCRIPTION

The PCM3000/3001 is a low cost single chip stereo audio CODEC (analog-to-digital and digital-to-analog converter) with single-ended analog voltage input and output. Both ADCs and DACs employ delta-sigma modula- tion with 64X oversampling. The ADCs include a digital decimation filter and the DACs include an 8X oversampling digital interpolation filter. The DACs also include digital attenuation, de-emphasis, infinite zero detection and soft mute to form a complete subsystem. The PCM3000/3001 operates with left- justified, right-justified, I 2S or DSP data formats. PCM3000 can be programmed with a 3-wire serial interface for special features and data formats. PCM3001 can be pin-programmed for data formats. Fabricated on a highly advanced CMOS process, the PCM3000/3001 is suitable for a wide variety of cost- sensitive consumer applications where good perfor- mance is required. Applications include sampling key- boards, digital mixers, mini-disc recorders, hard-disk recorders, karaoke systems, DSP-based car stereo, DAT recorders, and video conferencing. © 1996 Burr-Brown Corporation PDS-1342E Printed in U.S.A., January, 2000 International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 For most current data sheet and other product information, visit www.burr-brown.com Lch In Rch In Analog Front-End Delta-Sigma Modulator Digital Decimation Filter Serial Interface and Mode Control Digital Out Digital In Mode Control System Clock Lch Out Rch Out Low Pass Filter and Output Buffer Multi-Level Delta-Sigma Modulator Digital Interpolation Filter

All specifications at +25°C, VDD = VCC = +5V, fS = 44.1kHz, SYSCLK = 384fS, CLKIO Input, 18-bit data, unless otherwise noted. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. NOTES: (1) Pins 16, 17, 18, 22, 25, 26, 27, 28: LRCIN, BCKIN, DIN, CLKIO, MC/FMT2, MD/FMT1, ML/FMT0, RSTB. (2) Pins 16, 17, 18, 22: LRCIN, BCKIN, DIN, CLKIO (Schmitt Trigger Input). (3) Pins 25, 26, 27, 28: MC/FMT2, MD/FMT1, ML/FMT0, RSTB (Schmitt Trigger Input, 70kΩ Internal Pull-Up Resistor). (4) Pin 20: XTI. (5) Pins 19, 22: DOUT,CLKIO. (6) Pin 21: XTO. (7) Refer to Application Bulletin AB-148 for information relating to operation at lower sampling frequencies. (8) High Pass Filter disabled (PCM3000 only) to measure DC offset. (9) fIN = 1kHz, using Audio Precision System II, rms mode with 20kHz LPF, 400Hz HPF used for performance calculation. (10) With no load on XTO and CLKIO. PCM3000E/3001E PARAMETER CONDITIONS MIN TYP MAX UNITS DIGITAL INPUT/OUTPUT Input Logic Input Logic Level: V IH(1) 2.0 VDC VIL(1) 0.8 VDC Input Logic Current: IIN(2) ±1 µA Input Logic Current: IIN(3) –120 µA Input Logic Level: VIH(4) 0.64 • VDD VDC VIL(4) 0.28 • VDD VDC Input Logic Current: IIN(4) ±40 µA Output Logic Output Logic Level: VOH (5) IOUT = –1.6mA 4.5 VDC VOL (5) IOUT = +3.2mA 0.5 VDC Output Logic Level: VOH (6) IOUT = –3.2mA 4.5 VDC VOL (6) IOUT = +3.2mA 0.5 VDC CLOCK FREQUENCY Sampling Frequency (fS) 32(7) 44.1 48 kHz System Clock Frequency 256f S 8.1920 11.2896 12.2880 MHz 384fS 12.2880 16.9344 18.4320 MHz 512fS 16.3840 22.5792 24.5760 MHz ADC CHARACTERISTICS RESOLUTION 18 Bits DC ACCURACY Gain Mismatch Channel-to-Channel ±1.0 ±5.0 % of FSR Gain Error ±2.0 ±5.0 % of FSR Gain Drift ±20 ppm of FSR/ °C Bipolar Zero Error High-Pass Filter Off (8) ±1.7 %of FSR Bipolar Zero Drift High-Pass Filter Off (8) ±20 ppm of FSR/ °C DYNAMIC PERFORMANCE (9) THD+N: V IN = –0.5dB f = 1kHz –88 –80 dB VIN = –60dB f = 1kHz –31 dB Dynamic Range f = 1kHz, A-Weighted 90 94 dB Signal-to-Noise Ratio f = 1kHz, A-Weighted 90 94 dB Channel Separation 88 92 dB DIGITAL FILTER PERFORMANCE Passband 0.454f S Hz Stopband 0.583fS Hz Passband Ripple ±0.05 dB Stopband Attenuation –65 dB Delay Time (Latency) 17.4/fS sec DIGITAL HIGH PASS FILTER RESPONSE –3dB Frequency 0.019fS mHz ANALOG INPUT Voltage Range 0dB (Full Scale) 2.9 Vp-p Center Voltage 2.1 V Input Impedance 15 k Ω ANTI-ALIASING FILTER –3dB Frequency C EXT = 470pF 170 kHz

3 PCM3000/3001

PARAMETER CONDITIONS MIN TYP MAX UNITS SPECIFICATIONS (cont.) All specifications at +25°C, VDD = VCC = 5V, fS = 44.1kHz, SYSCLK = 384fS, CLKIO Input, 18-bit data, unless otherwise noted. Supply Voltage ABSOLUTE MAXIMUM RATINGSELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degrada- tion to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. DAC CHARACTERISTICS RESOLUTION 18 Bits DC ACCURACY Gain Mismatch Channel-to-Channel ±1.0 ±5.0 % of FSR Gain Error ±1.0 ±5.0 % of FSR Gain Drift ±20 ppm of FSR/ °C Bipolar Zero Error ±1.0 % of FSR Bipolar Zero Drift ±20 ppm of FSR/ °C DYNAMIC PERFORMANCE (9) THD+N: V OUT = 0dB (Full Scale) –90 –80 dB VOUT = –60dB –34 dB Dynamic Range EIAJ A-Weighted 90 97 dB Signal-to-Noise Ratio (Idle Channel) EIAJ A-Weighted 92 98 dB Channel Separation 90 95 dB DIGITAL FILTER PERFORMANCE Passband 0.445fS Hz Stopband 0.555fS Hz Passband Ripple ±0.17 dB Stopband Attenuation –35 dB Delay Time 11.1/fS sec ANALOG OUTPUT Voltage Range 0.62 • VCC Vp-p Center Voltage 0.5 • VCC VDC Load Impedance AC Load 5 k Ω ANALOG LOW PASS FILTER Frequency Response f = 20kHz –0.16 dB POWER SUPPLY REQUIREMENTS Voltage Range: VCC 4.5 5 5.5 VDC VDD 4.5 5 5.5 VDC Supply Current: +ICC , +IDD (10) VCC = VDD = 5V 32 50 mA Power Dissipation V CC = VDD = 5V 160 250 mW TEMPERATURE RANGE Operation –25 +85 °C Storage –55 +125 °C PACKAGE SPECIFIED DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE NUMBER RANGE MARKING NUMBER (1) MEDIA PCM3000E SSOP-28 324 –25 °C to +85°C PCM3000E PCM3000E Rails " " " " " PCM3000E/2K Tape and Reel PCM3001E SSOP-28 324 –25 °C to +85°C PCM3001E PCM3001E Rails " " " " " PCM3001E/2K Tape and Reel NOTES: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces of “PCM3000E/2K” will get a single 2000-piece Tape and Reel. PACKAGE/ORDERING INFORMATION

V REF L VREF R VINR C INPR C INNR C INNL C INPL VCOM V OUT R AGND2 V CC 2 RSTB FMT0 FMT1 FMT2 DGND V DD CLKIO XTO XTI DOUT DIN BCKIN LRCIN VOUT L VINL VCC 1 AGND1 V REF L VREF R VINR C INPR C INNR C INNL C INPL VCOM V OUT R AGND2 V CC 2 RSTB ML MD MC DGND V DD CLKIO XTO XTI DOUT DIN BCKIN LRCIN VOUT L PIN CONFIGURATION—PCM3000 Top View SSOP PIN CONFIGURATION—PCM3001 Top View SSOP PIN NAME I/O DESCRIPTION 1V INL IN ADC Analog Input, Lch 2V CC 1 — ADC Analog Power Supply

3 AGND1 — ADC Analog Ground

REF L — ADC Input Reference, Lch 5V REF R — ADC Input Reference, Rch 6V INR IN ADC Analog Input, Rch 7C INPR — ADC Anti-alias Filter Capacitor (+), Rch 8C INNR — ADC Anti-alias Filter Capacitor (–), Rch 9C INNL — ADC Anti-alias Filter Capacitor (–), Lch

10 C INPL — ADC Anti-alias Filter Capacitor (+), Lch

11 VCOM — DAC Output Common

12 V OUT R OUT DAC Analog Output, Rch

13 AGND2 — DAC Analog Ground

CC 2 — DAC Analog Power Supply

15 V OUT L OUT DAC Analog Output, Lch

16 LRCIN IN Sample Rate Clock Input (f S)(2)

17 BCKIN IN Bit Clock Input (2)

18 DIN IN Data Input (2)

19 DOUT OUT Data Output

20 XTI IN Oscillator Input

21 XTO OUT Oscillator Output

22 CLKIO I/O Buffered Output of Oscillator or External Clock

(2)

23 V DD — Digital Power Supply

24 DGND — Digital Ground

25 MC/FMT2 IN Serial Control Bit Clock (PCM3000)/Data

Format Control 2 (PCM3001) (1, 2)

26 MD/FMT1 IN Serial Control Data (PCM3000)/Data Format

Control 1 (PCM3001)(1, 2)

27 ML/FMT0 IN Serial Control Strobe Pulse/Data Format

Control 0 (PCM3001)(1, 2)

28 RSTB IN Reset (1, 2)

NOTES: (1) With 70kΩ typical internal pull-up resistor. (2) Schmitt trigger input. PIN ASSIGNMENTS PCM3000/3001

5 PCM3000/3001

TYPICAL PERFORMANCE CURVES ADC SECTION At TA = +25°C, VCC = VDD = +5V, fIN = 1.0kHz, fS = 44.1kHz, 18-bit data, VIN = 2.9Vp-p, and SYSCLK = 384fS, unless otherwise noted. THD+N vs TEMPERATURE Temperature (°C) THD+N at 0dB (%) 0.01 0.008 0.006 0.004 0.002 –25 0 25 50 75 85 100 THD+N at –60dB (%) 4.0 3.0 2.0 1.0 –60dB 0dB THD+N vs POWER SUPPLY VCC (V) THD+N at 0dB (%) 0.01 0.008 0.006 0.004 0.002 THD+N at –60dB (%) 4.0 3.0 2.0 1.0 –60dB 0dB THD+N vs SYSTEM CLOCK and SAMPLING FREQUENCY System Clock THD+N at 0dB (%) 0.01 0.008 0.006 0.004 0.002 256f S 384fS 512fS THD+N at –60dB (%) 4.0 3.0 2.0 1.0 44.1kHz 44.1kHz 48kHz 48kHz –60dB 0dB SNR and DYNAMIC RANGE vs POWER SUPPLY VCC (V) SNR (dB) Dynamic Range (dB) SNR Dynamic Range THD+N vs OUTPUT DATA RESOLUTION Resolution THD+N at 0dB (%) THD+N at –60dB (%) 0.01 0.008 0.006 0.004 0.002 16-Bit 18-Bit 4.0 3.0 2.0 1.0 0dB –60dB

TYPICAL PERFORMANCE CURVES DAC SECTION At TA = +25°C, VCC = VDD = +5V, fIN = 1.0kHz, fS = 44.1kHz, 18-bit data, and SYSCLK = 384fS, unless otherwise noted. THD+N vs TEMPERATURE Temperature (°C) THD+N at 0dB (%) 0.01 0.008 0.006 0.004 0.002 –25 0 25 50 75 85 100 THD+N at –60dB (%) 4.0 3.0 2.0 1.0 –60dB 0dB THD+N vs POWER SUPPLY VCC (V) THD+N at 0dB (%) 0.01 0.008 0.006 0.004 0.002 THD+N at –60dB (%) 4.0 3.0 2.0 1.0 –60dB 0dB SNR and DYNAMIC RANGE vs POWER SUPPLY VCC (V) SNR (dB) 100 Dynamic Range (dB) 100 Dynamic Range SNR THD+N vs SYSTEM CLOCK and SAMPLING FREQUENCY System Clock THD+N at 0dB (%) 0.01 0.008 0.006 0.004 0.002 256f S 384fS 512fS THD+N at –60dB (%) 4.0 3.0 2.0 1.0 44.1kHz 44.1kHz 48kHz 48kHz –60dB 0dB THD+N vs INPUT DATA RESOLUTION Resolution THD+N at 0dB (%) THD+N at –60dB (%) 0.01 0.008 0.006 0.004 0.002 16-Bit 18-Bit 4.0 3.0 2.0 1.0 0dB –60dB

7 PCM3000/3001

Normalized Frequency (x fS /1000 Hz) Amplitude (dB) 0.2 0.0 –0.2 –0.4 –0.6 –0.8 –1.0 12340 TYPICAL PERFORMANCE CURVES At TA = +25°C, VCC = VDD = +5V, and SYSCLK = 384fS, unless otherwise noted. ADC DIGITAL FILTER STOPBAND ATTENUATION CHARACTERISTICS Normalized Frequency (x fS Hz) Amplitude (dB) –20 –40 –60 –80 –100 0.25 0.50 0.75 1.000 PASSBAND RIPPLE CHARACTERISTICS Normalized Frequency (x fS Hz) Amplitude (dB) 0.2 0.0 –0.2 –0.4 –0.6 –0.8 –1.0 0.125 0.250 0.375 0.5000 OVERALL CHARACTERISTICS Normalized Frequency (x fS Hz) Amplitude (dB) –50 –100 –150 –200 81 6 2 4 3 20 ANTI-ALIASING FILTER PASSBAND FREQUENCY RESPONSE (C EXT = 470pF, 1000pF) Frequency (Hz) Amplitude (dB) 0.2 0.0 –0.2 –0.4 –0.6 –0.8 –1.0 10 100 1k 10k 100k0 470pF 1000pF ANTI-ALIASING FILTER OVERALL FREQUENCY RESPONSE (C EXT = 470pF, 1000pF) Frequency (Hz) Amplitude (dB) –10 –20 –30 –40 –50 10 100 1k 10k 100k 1M 10M0 470pF 1000pF ANTI-ALIASING FILTER

TYPICAL PERFORMANCE CURVES At TA = +25°C, VCC = VDD = +5V, and SYSCLK = 384fS, unless otherwise noted. DAC DIGITAL FILTER –20 –40 –60 –80 –100 dB OVERALL FREQUENCY CHARACTERISTIC Frequency (Hz) PASSBAND RIPPLE CHARACTERISTIC –0.2 –0.4 –0.6 –0.8 0 0.1134f S 0.2268fS 0.3402fS 0.4535fS dB Frequency (Hz) DE-EMPHASIS ERROR (3kHz) 0 3628 7256 10884 14512 0 4999.8375 9999.675 14999.5125 19999.35 0 5442 10884 16326 21768 Frequency (Hz) 0.6 0.4 0.2 –0.2 –0.4 –0.6 0.6 0.4 0.2 –0.2 –0.4 –0.6 0.6 0.4 0.2 –0.2 –0.4 –0.6 DE-EMPHASIS ERROR (44.1kHz) Frequency (Hz) DE-EMPHASIS ERROR (48kHz) Frequency (Hz) Error (dB) Error (dB) Error (dB) DE-EMPHASIS FREQUENCY RESPONSE (3kHz) 0 5k 10k 15k 20k 25k Frequency (Hz) –10 –12 DE-EMPHASIS FREQUENCY RESPONSE (44.1kHz) 0 5k 10k 15k 20k 25k Frequency (Hz) –10 –12 DE-EMPHASIS FREQUENCY RESPONSE (48kHz) 0 5k 10k 15k 20k 25k Frequency (Hz) –10 –12 Level (dB) Level (dB) Level (dB) 1.0 0.5 –0.5 –1.0 dB Frequency (Hz) 100 1k 10k 24k INTERNAL ANALOG FILTER FREQUENCY RESPONSE (20Hz~24kHz, Expanded Scale) ANALOG OUTPUT FILTER –10 –15 –20 –25 –30 –35 –40 –45 –50 –55 10 100 1k 10k 100k 1M 10M Frequency (Hz) dB –60 INTERNAL ANALOG FILTER FREQUENCY RESPONSE (10Hz~10MHz)

9 PCM3000/3001

FIGURE 1. Analog Front-End (Single-Channel). NOTE: (1) FMT0, FMT1, FMT2 are for PCM3001 only.

illustrate audio data input/output format and timing. selected when 32 bit clocks/LRCIN are applied. FIGURE 2. Audio Data Input/Output Format.

11 PCM3000/3001

FIGURE 3. Audio Data Input/Output Format.

FIGURE 4. Audio Data Input/Output Timing. TABLE I. System Clock Frequencies. circuit in Figure 5 is recommended.

13 PCM3000/3001

FIGURE 5. System Clock Connections. FIGURE 6. External System Clock Timing.

DD > 4.0V to ensure proper reset operation. system clock is active in order to initiate the reset sequence. FIGURE 9. Control Data Input Format. FIGURE 7. Internal Power-On Reset Timing.

1024 System Clock Periods

FIGURE 8. External Forced Reset Timing.

15 PCM3000/3001

FIGURE 11. DAC Output and ADC Output When Synchronization is Lost. FIGURE 10. DAC Output and ADC Output for Reset and Power-Down. NOTE: (1) The HPF transient response (exponentially attenuationed signal with 200ms time constant) appears initally. (exponentially attenuationed signal with 200ms time constant) appears intially.

FIGURE 12. Control Data Input Timing. TABLE II. Selectable Functions. PCM3001 only allows for control of data format.

17 PCM3000/3001

Register 0 A (1:0) Register Address “00” res Reserved, should be set to “0” LDL DAC Attenuation Data Load Control for Lch AL (7:0) Attenuation Data for Lch Register 1 A (1:0) Register Address “01” res Reserved, should be set to “0” LDR DAC Attenuation Data Load Control for Rch AR (7:0) DAC Attenuation for Rch Register 2 A (1:0) Register Address “10” res Reserved, should be set to “0” PDWN ADC Power Down Control BYPS ADC High-Pass Filter Operation Control ATC DAC Attenuation Data Mode Control IZD DAC Infinite Zero Detection Circuit Control OUT DAC Output Enable Control DEM (1:0) DAC De-emphasis Control MUT Lch and Rch Soft Mute Control Register 3 A (1:0) Register Address “11” res Reserved, should be set to “0” LOP ADC/DAC Analog Loop-back Control FMT (2:0) ADC/DAC Audio Data Format Selection LRP ADC/DAC Polarity of LR-clock Selection TABLE III. Functions of the Registers. PROGRAM REGISTER (PCM3000) The software mode allows the user to control special functions. PCM3000’s special functions are controlled using four pro- gram registers which are 16 bits long. There are four distinct registers, with bits 9 and 10 determining which register is in use. Table III describes the functions of the four registers. PROGRAM REGISTER 0 A (1:0): Bit 10, 9 Register Address These bits define the address for REGISTER 0: A1 A0 0 0 Register 0 res: Bit 11 : 15 Reserved These bits are reserved and should be set to “0”. LDL: Bit 8 DAC Attenuation Data Load Control for Left Channel This bit is used to simultaneously set analog outputs of the left and right channels. The output level is controlled by AL (7:0) attenuation data when this bit is set to “1”. When set to “0”, the new attenuation data will be stored into a register, and the output level will remain at the previous attenuation level. The LDR bit in REGISTER 1 has the equivalent function as LDL. When either LDL or LDR is set to “1”, the output level of the left and right channels are simultaneously con- trolled. AL (7:0): Bit 7 :0 DAC Attenuation Data for Left Channel AL7 and AL0 are MSB and LSB, respectively. The attenuation level (ATT) is given by: ATT = 20 x log10 (ATT data/256) (dB) AL (7:0) ATTENUATION LEVEL 00h – ∞ dB (Mute) 01h –48.16dB FEh –0.07dB FFh 0dB (default) PROGRAM REGISTER 1 A (1:0): Register Address These bits define the address for REGISTER 1: A1 A0 0 1 Register 1 res: Bit 15 : 11 Reserved These bits are reserved and should be set to “0” LDR: Bit 8 DAC Attenuation Data Load Control for Right Channel This bit is used to simultaneously set analog outputs of the left and right channels. The output level is controlled by AR (7:0) attenuation data when this bit is set to “1”. When set to “0”, the new attenuation data will be stored into a register, and the output level will remain at the previous attenuation level. The LDL bit in REGISTER 0 has the equivalent function as LDR. When either LDL or LDR is set to “1”, the output level of the left and right channels are simultaneously con- trolled. AR (7:0): Bit 7 : 0 DAC Attenuation Data for Right Channel AR7 and AR0 are MSB and LSB respectively. See REGISTER 0 for the attenuation formula. PROGRAM REGISTER 2 A (1:0): Bit 10, 9 Register Address These bits define the address for REGISTER 2: A1 A0 1 0 Register 2 res: Bit 15:11, 6 Reserved These bits are reserved and should be set to “0”. PDWN: Bit 8 ADC Power-Down Control This bit places the ADC section in a power-down mode, forcing the output data to all zeroes. This has no effect on the DAC section. PDWN

0 Power Down Mode Disabled (default)

1 Power Down Mode Enabled

A (1:0): Bit 10, 9 Register Address These bits define the address for REGISTER 3: A1 A0 1 1 Register 3 res: Bit 15:11, 8:6, 0 Reserved These bits are reserved, and should be set to “0”. FMT (2:0) Bit 4:2 Audio Data Format Select These bits determine the input and output audio data formats. (default: FMT [2:0] = 000H ) FMT2 FMT1 FMT0 DAC ADC Data Format Data Format 0 0 0 16-bit, MSB-first, 16-bit, MSB-first, Right-justified Left-justified 0 0 1 18-bit, MSB-first, 18-bit, MSB-first, Right-justified Left-justified 0 1 0 16-bit, MSB-first, 16-bit, MSB-first, Right-justified Right-justified 0 1 1 18-bit, MSB-first, 18-bit, MSB-first, Right-justified Right-justified 1 0 0 16-/18-bit, MSB-first, 18-bit, MSB-first, Left-justified Left-justified 1 0 1 16-/18-bit, MSB-first, I 2S 18-bit, MSB-first, I2S 1 1 0 16-bit, MSB-first, 16-bit, MSB-first, DSP-frame DSP-frame 1 1 1 Reserved Reserved LOP: Bit 5 ADC to DAC Loop-back Control When this bit is set to “1”, the ADC’s audio data is sent directly to the DAC. The data format will default to I 2S. In Format 6 (DSP Frame), Loop- back is not supported. LOP

0 Loop-back Disable (default)

1 Loop-back Enable

LRP: Bit 1 Polarity of LRCIN Applies only to Formats 0 through 4. LRP 0 Left-Channel is “H”, Right-Channel is “L”. (default) 1 Left-Channel is “L”, Right-Channel is “H”. PCM3001 DATA FORMAT CONTROL The input and output data formats are controlled by pins 27 (FMT0), 26 (FMT1), and 25 (FMT2). Set these pins to the same values shown for the bit-mapped PCM3000 controls in PROGRAM REGISTER 3. BYPS: Bit 7 ADC High-Pass Filter Bypass Control This bit determines enables or disables the high- pass filter for the ADC. BYPS

0 High-Pass Filter Enabled (default)

1 High-Pass Filter Disabled (bypassed)

ATC: Bit 5 DAC Attenuation Channel Control When set to “1”, the REGISTER 0 attenuation data can be used for both DAC channels. In this case, the REGISTER 1 attenuation data is ig- nored. ATC

0 Individual Channel Attenuation Data Control (default)

1 Common Channel Attenuation Data Control

IZD: Bit 4 DAC Infinite Zero Detection Circuit Control This bit enables the Infinite Zero Detection Circuit in PCM3000. When enabled, this circuit will dis- connect the analog output amplifier from the delta- sigma DAC when the input is continuously zero for 65,536 consecutive cycles of BCKIN. IZD

0 Infinite Zero Detection Disabled (default)

1 Infinite Zero Detection Enabled

OUT: Bit 3 DAC Output Enable Control When set to “1”, the outputs are forced to VCC /2 (bipolar zero). In this case, all registers in PCM3000 hold the present data. Therefore, when set to “0”, the outputs return to the previous programmed state. OUT

0 DAC Outputs Enabled (default normal operation)

1 DAC Outputs Disabled (forced to BPZ)

DM (1:0):Bit 2,1 DAC De-emphasis Control These bits select the de-emphasis mode as shown below: DM1 DM0 0 0 De-emphasis OFF (default) 0 1 De-emphasis 48kHz ON 1 0 De-emphasis 44.1kHz ON 1 1 De-emphasis 32kHz ON MUT: Bit 0 DAC Soft Mute Control When set to “1”, both left and right-channel DAC outputs are muted at the same time. This muting is done by attenuating the data in the digital filter, so there is no audible click noise when soft mute is turned on. MUT

0 Mute Disable (default)

1 Mute Enable

19 PCM3000/3001

FIGURE 13. Typical Connection Diagram for PCM3000/3001. mended to avoid latch-up problems. quency digital switching noise into the analog ground plane. dynamic errors on the ADC reference.

A 4.7µF to 10µF tantalum capacitor is recommended be- tween VCOM and AGND to ensure low source impedance of the DAC output common. This capacitor should be located as close as possible to the VCOM pin to reduce dynamic errors on the DAC common. SYSTEM CLOCK The quality of the system clock can influence dynamic performance of both the ADC and DAC in the PCM3000/ 3001. The duty cycle, jitter, and threshold voltage at the system clock input pin must be carefully managed. When power is supplied to the part, the system clock, bit clock (BCKIN) and a word clock (LCRIN) should also be supplied simultaneously. Failure to supply the audio clocks will result in a power dissipation increase of up to three times normal dissipation and may degrade long term reliability if the maximum power dissipation limit is exceeded. THEORY OF OPERATION ADC SECTION The PCM3000/3001 ADC consists of a bandgap reference, a stereo single-to-differential converter, a fully differential 5th-order delta-sigma modulator, a decimation filter (includ- ing digital high pass), and a serial interface circuit. The Block Diagram in this data sheet illustrates the architecture of the ADC section, Figure 1 shows the single-to-differential converter, and Figure 14 illustrates the architecture of the 5th-order delta-sigma modulator and transfer functions. An internal high precision reference with two external ca- pacitors provides all reference voltages which are required by the ADC, which defines the full scale range for the converter. The internal single-to-differential voltage con- verter saves the space and extra parts needed for external circuitry required by many delta-sigma converters. The internal full differential signal processing architecture pro- vides a wide dynamic range and excellent power supply rejection performance. The input signal is sampled at 64X oversampling rate, eliminating the need for a sample-and-hold circuit, and simplifying anti-alias filtering requirements. The 5th-order delta-sigma noise shaper consists of five integrators which use a switched-capacitor topology, a comparator and a feedback loop consisting of a one-bit DAC. The delta-sigma modulator shapes the quantization noise, shifting it out of the audio band in the frequency domain. The high order of the modulator enables it to randomize the modulator out- puts, reducing idle tone levels. The 64f S one-bit data stream from the modulator is con- verted to 1fS 18-bit data words by the decimation filter, which also acts as a low pass filter to remove the shaped quantization noise. The DC components are removed by a high pass filter function contained within the decimation filter. THEORY OF OPERATION DAC SECTION The delta-sigma DAC section of PCM3000/3001 is based on a 5-level amplitude quantizer and a 3rd-order noise shaper. This section converts the oversampled input data to 5-level delta-sigma format. A block diagram of the 5-level delta- sigma modulator is shown in Figure 15. This 5-level delta- sigma modulator has the advantage of improved stability and reduced clock jitter sensitivity over the typical one-bit (2 level) delta-sigma modulator. The combined oversampling rate of the delta-sigma modu- lator and the internal 8X interpolation filter is 64f S for a 256fS system clock. The theoretical quantization noise per- formance of the 5-level delta-sigma modulator is shown in Figure 16.

21 PCM3000/3001

FIGURE 16. Quantization Noise Spectrum. FIGURE 15. 5-Level ΔΣ Modulator Block Diagram. FIGURE 14. Simplified 5th-Order Delta-Sigma Modulator.