PCM2705DBR

PCM2704_15 TI1 | Alldatasheet

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www.ti.com SLES081F JUNE 2003 REVISED JANUARY 2009 STEREO AUDIO DAC WITH USB INTERFACE, SINGLE-ENDED HEADPHONE OUTPUT AND S/PDIF OUTPUT External ROM Interface (PCM2704/6) 2345 On-Chip USB Interface: Serial Programming Interface (PCM2705/7) No Need of Dedicated Device Driver I S Interface (Selectable on PCM2706/7) With Full-Speed Transceivers Package: Fully Compliant With USB 1.1 Specification 28-Pin SSOP (PCM2704/5) Certified by USB-IF 32-Pin TQFP (PCM2706/7) Partially Programmable Descriptors Adaptive Isochronous Transfer for USB Headphones Playback USB Audio Speaker Bus-Powered or Self-Powered Operation USB CRT/LCD Monitor Sampling Rate: 32, 44.1, kHz USB Audio Interface Box On-Chip Clock Generator With Single 12-MHz USB-Featured Consumer Audio Product Clock Source Single Power Supply: Bus-Powered: Typical BUS The PCM2704/5/6/7 is TI s single-chip USB stereo Self-Powered: 3.3 Typical audio DAC with USB-compliant full-speed protocol 16-Bit Delta-Sigma Stereo DAC controller and S/PDIF. The USB-protocol controller works with no software code, but USB descriptors Analog Performance at V (Bus-Powered), can be modified in some parts (for example, vendor 3.3 V (Self-Powered): ID/product ID) through the use of an external ROM THD+N: 0.006% R L k Ω (PCM2704/6), SPI (PCM2705/7), or on request. (1) Self-Powered The PCM2704/5/6/7 employs SpAct™ architecture, TI s unique system that recovers the audio clock from THD+N: 0.025% R L Ω USB packet data. On-chip analog PLLs with SpAct SNR dB enable playback with low clock jitter. Dynamic Range: dB P O mW, R L Ω Oversampling Digital Filter Pass-Band Ripple 0.04 dB Stop-Band Attenuation dB Single-Ended Voltage Output Analog LPF Included Multiple Functions: Up to Eight Human Interface Device (HID) Interfaces (Depending on Model and (1) The modification of the USB descriptor through external ROM Settings) or SPI must comply with USB-IF guidelines, and the vendor ID must be your own ID as assigned by the USB-IF. The Suspend Flag descriptor also can be modified by changing a mask; contact S/PDIF Out With SCMS your representative for details. Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. SpAct is a trademark of Texas Instruments. System Two, Audio Precision are trademarks of Audio Precision, Inc. I2S is a trademark of NXP Semiconductors. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright 2003 2009, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. PCM2704 and PCM2705 Not Recommended For New Designs

www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. over operating free-air temperature range unless otherwise noted (1) V BUS 0.3 V to 6.5 V Supply voltage V CCP V CCL V CCR V DD 0.3 V to V Supply voltage differences V CCP V CCL V CCR V DD 0.1 V Ground voltage differences PGND, AGNDL, AGNDR, DGND, ZGND 0.1 V HOST 0.3 V to 6.5 V Digital input voltage D+, D HID0/MS, HID1/MC, HID2/MD, XTI, XTO, DOUT, SSPND, CK, DT, 0.3 V to DD 0.3) V V PSEL, FSEL, TEST, TEST0, TEST1, FUNC0, FUNC1, FUNC2, FUNC3 V COM 0.3 V to CCP 0.3) V V Analog input voltage V OUT R 0.3 V to CCR 0.3) V V V OUT L 0.3 V to CCL 0.3) V V Input current (any pins except supplies) mA Ambient temperature under bias to 125 Storage temperature to 150 Junction temperature 150 Lead temperature (soldering) 260 °C, s Package temperature (IR reflow, peak) 260 (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. over operating free-air temperature range MIN NOM MAX UNIT V BUS 4.35 5.25 Supply voltage V V CCP V CCL V CCR V DD 3.3 3.6 Digital input logic level TTL compatible Digital input clock frequency 11.994 12.006 MHz Analog output load resistance Ω Analog output load capacitance 100 pF Digital output load capacitance pF Operating free-air temperature, T A C Submit Documentation Feedback Copyright 2003 2009, Texas Instruments Incorporated Product Folder Link(s): PCM2704 PCM2705 PCM2706 PCM2707 PCM2704 and PCM2705 Not Recommended For New Designs

www.ti.com SLES081F JUNE 2003 REVISED JANUARY 2009 all specifications at T A °C, V BUS f S 44.1 kHz, f IN kHz,16-bit data (unless otherwise noted) PCM2704DB, PCM2705DB, PCM2706PJT, PCM2707PJT PARAMETER TEST CONDITIONS UNIT MIN TYP MAX DIGITAL INPUT/OUTPUT Host interface Apply USB revision 1.1, full-speed Audio data format USB isochronous data format INPUT LOGIC V IH 3.3 V IL 0.3 0.8 Input logic level Vdc V IH (1) 5.5 V IL (1) 0.3 0.8 I IH (2) V IN 3.3 V I IL (2) V IN V Input logic current µ A I IH V IN 3.3 V 100 I IL V IN V OUTPUT LOGIC V OH (3) I OH mA 2.8 V OL (3) I OL mA 0.3 Output logic level Vdc V OH I OH mA 2.4 V OL I OL mA 0.4 CLOCK FREQUENCY Input clock frequency, XTI 11.994 12.006 MHz f s Sampling frequency 32, 44.1, kHz DAC CHARACTERISTICS Resolution Bits Audio data channel Channel DC ACCURACY Gain mismatch, channel-to-channel of FSR Gain error of FSR Bipolar zero error of FSR DYNAMIC PERFORMANCE (4) R L k Ω self-powered, 0.006% 0.01% V OUT dB Line (5) Total harmonic R L k Ω bus-powered, THD+N 0.012% 0.02% distortion noise V OUT dB R L Ω self-/ Headphone 0.025% bus-powered, V OUT dB THD+N Total harmonic distortion noise V OUT dB Dynamic range EIAJ, A-weighted dB S/N Signal-to-noise ratio EIAJ, A-weighted dB Channel separation dB (1) HOST (2) D+, D HOST, TEST, TEST0, TEST1, DT, PSEL, FSEL, XTI (3) FUNC0, FUNC1, FUNC2 (4) f IN kHz, using the System Two™ Cascade audio measurement system by Audio Precision™ in the RMS mode with a 20-kHz LPF and 400-Hz HPF. (5) THD+N performance varies slightly, depending on the effective output load, including dummy load R7, in Figure Copyright 2003 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM2704 PCM2705 PCM2706 PCM2707 PCM2704 and PCM2705 Not Recommended For New Designs

www.ti.com ELECTRICAL CHARACTERISTICS (continued) all specifications at T A °C, V BUS f S 44.1 kHz, f IN kHz,16-bit data (unless otherwise noted) PCM2704DB, PCM2705DB, PCM2706PJT, PCM2707PJT PARAMETER TEST CONDITIONS UNIT MIN TYP MAX ANALOG OUTPUT Output voltage 0.55 V CCL 0.55 V CCR Vp-p Center voltage 0.5 V CCP V Line AC coupling k Ω Load impedance Headphone AC coupling Ω dB 140 kHz LPF frequency response f kHz 0.1 dB DIGITAL FILTER PERFORMANCE Pass band 0.454 f s Hz Stop band 0.546 f s Hz Pass-band ripple 0.04 dB Stop-band attenuation dB Delay time 20/f s s POWER SUPPLY REQUIREMENTS V BUS Bus-powered 4.35 5.25 Voltage range Vdc V CCP V CCL V CCR Self-powered 3.3 3.6 V DD Line DAC operation mA Supply current Headphone DAC operation R L Ω Line/headphone Suspend mode (6) 150 190 µ A Line DAC operation 108 mW Power dissipation Headphone DAC operation R L Ω 116 166 (self-powered) Line/headphone Suspend mode (6) 495 684 µ W Line DAC operation 115 158 mW Power dissipation Headphone DAC operation R L Ω 175 242 (bus-powered) Line/headphone Suspend mode (6) 750 998 µ W Internal power-supply V CCP V CCL V CCR Bus-powered 3.2 3.35 3.5 Vdc voltage (7) V DD TEMPERATURE RANGE Operating temperature 28-pin SSOP 100 (PCM2704/5) θ JA Thermal resistance °C/W 32-pin TQFP (PCM2706/7) (6) Under USB suspend state. (7) V DD V CCP V CCL V CCR These pins work as output pins of internal power supply for bus-powered operation. Submit Documentation Feedback Copyright 2003 2009, Texas Instruments Incorporated Product Folder Link(s): PCM2704 PCM2705 PCM2706 PCM2707 PCM2704 and PCM2705 Not Recommended For New Designs

V CCP PGND V COM AGNDR V CCR VOUT R PCM2704/PCM2705 DB PACKAGE (TOP VIEW) PCM2706/PCM2707 PJT PACKAGE (TOP VIEW) 23 22 21 20 19 1 2 PSEL DT CK XTO XTI SSPND TEST FSEL ZGND AGNDL V CCL VOUT L VOUT R VCCR AGNDR VCOM 24 18 3 4 5 6 7 8 VBUS V DD DGND FUNC1 FUNC2 DOUT PGND V CCP HOST FUNC3 FUNC0 HID0/MS HID1/MC HID2/MD P0020-01 PCM2704 PCM2705 PCM2706 PCM2707 www.ti.com SLES081F JUNE 2003 REVISED JANUARY 2009 Copyright 2003 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM2704 PCM2705 PCM2706 PCM2707 PCM2704 and PCM2705 Not Recommended For New Designs

www.ti.com Terminal Functions (PCM2704DB/PCM2705DB) TERMINAL I/O NO. AGNDL Analog ground for headphone amplifier of L-channel AGNDR Analog ground for headphone amplifier of R-channel CK O Clock output for external ROM (PCM2704). Must be left open (PCM2705). I/O USB differential input/output plus (1) D I/O USB differential input/output minus (1) DGND Digital ground DOUT O S/PDIF output DT I/O Data input/output for external ROM (PCM 2704). Must be left open with pullup resistor (PCM2705). (1) HID0/MS I HID key state input (mute), active HIGH (PCM2704). MS input (PCM2705). (2) HID1/MC I HID key state input (volume up), active HIGH (PCM2704). MC input (PCM2705). (2) HID2/MD I HID key state input (volume down), active HIGH (PCM2704). MD input (PCM2705). (2) HOST I Host detection during self-powered operation (connect to V BUS Max power select during bus-powered operation (LOW: 100 mA, HIGH: 500 mA). (3) PGND Analog ground for DAC, OSC, and PLL PSEL I Power source select (LOW: self-power, HIGH: bus-power) (1) SSPND O Suspend flag, active LOW (LOW: suspend, HIGH: operational) TEST0 I Test pin. Must be set HIGH (1) TEST1 I Test pin. Must be set HIGH (1) V BUS Connect to USB power BUS for bus-powered operation. Connect to V DD for self-powered operation. V CCL Analog power supply for headphone amplifier of L-channel (4) V CCP Analog power supply for DAC, OSC, and PLL (4) V CCR Analog power supply for headphone amplifier of R-channel (4) V COM Common voltage for DAC CCP /2). Connect decoupling capacitor to PGND. V DD Digital power supply (4) V OUT L O DAC analog output for L-channel V OUT R O DAC analog output for R-channel XTI I Crystal oscillator input (1) XTO O Crystal oscillator output ZGND Ground for internal regulator (1) LV-TTL level (2) LV-TTL level with internal pulldown (3) LV-TTL level, 5-V tolerant (4) Connect decoupling capacitor to GND. Supply 3.3 V for self-powered applications. Submit Documentation Feedback Copyright 2003 2009, Texas Instruments Incorporated Product Folder Link(s): PCM2704 PCM2705 PCM2706 PCM2707 PCM2704 and PCM2705 Not Recommended For New Designs

www.ti.com SLES081F JUNE 2003 REVISED JANUARY 2009 Terminal Functions (PCM2706PJT/PCM2707PJT) TERMINAL I/O NO. AGNDL Analog ground for headphone amplifier of L-channel AGNDR Analog ground for headphone amplifier of R-channel CK O Clock output for external ROM (PCM2706). Must be left open (PCM2707). I/O USB differential input/output plus (1) D I/O USB differential input/output minus (1) DGND Digital ground DOUT O S/PDIF output/ I data output DT I/O Data input/output for external ROM (PCM2706). Must be left open with pullup resistor (PCM2707). (1) FSEL I Function select (LOW: I S DATA output, HIGH: S/PDIF output) (1) FUNC0 I/O HID key state input (next track), active HIGH (FSEL 1). I S LR clock output (FSEL 0). (2) FUNC1 I/O HID key state input (previous track), active HIGH (FSEL 1). I S bit clock output (FSEL 0). (2) FUNC2 I/O HID key state input (stop), active HIGH (FSEL 1). I S system clock output (FSEL 0). (2) FUNC3 I HID key state input (play/pause), active HIGH (FSEL 1). I S data input (FSEL 0). (2) HID0/MS I HID key state input (mute), active HIGH (PCM2706). MS input (PCM2707) (2) HID1/MC I HID key state input (volume up), active HIGH (PCM2706). MC input (PCM2707) (2) HID2/MD I HID key state input (volume down), active HIGH (PCM2706). MD input (PCM2707) (2) HOST I Host detection during self-powered operation (connect to V BUS Max power select during bus-powered operation. (LOW: 100 mA, HIGH: 500 mA). (3) PGND Analog ground for DAC, OSC, and PLL PSEL I Power source select (LOW: self-power, HIGH: bus-power) (1) SSPND O Suspend flag, active LOW (LOW: suspend, HIGH: operational) TEST I Test pin. Must be set HIGH (1) V BUS Connect to USB power BUS for bus-powered operation. Connect to V DD for self-powered operation. V CCL Analog power supply for headphone amplifier of L-channel (4) V CCP Analog power supply for DAC, OSC, and PLL (4) V CCR Analog power supply for headphone amplifier of R-channel (4) V COM Common voltage for DAC CCP /2). Connect decoupling capacitor to PGND. V DD Digital power supply (4) V OUT L O DAC analog output for L-channel V OUT R O DAC analog output for R-channel XTI I Crystal oscillator input (1) XTO O Crystal oscillator output ZGND Ground for internal regulator (1) LV-TTL level (2) LV-TTL level with internal pulldown (3) LV-TTL level, 5-V tolerant (4) Connect decoupling capacitor to GND. Supply 3.3 V for self-powered applications. Copyright 2003 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM2704 PCM2705 PCM2706 PCM2707 PCM2704 and PCM2705 Not Recommended For New Designs

Interface(1) SSPND VCCP VCCL VCCR VDD ZGNDDGNDAGNDRAGNDLPGND VCOM Analog PLL FIFO DAC VOUT L S/PDIF Encoder XTI XTO12 MHz PLL (×8) 96 MHz Tracker (SpAct) USB Protocol Controller Power Manager 5-V to 3.3-V Voltage Regulator Control Endpoint ISO-Out Endpoint HID Endpoint VBUS USB SIE XCVR DT HOST HID0/MS HID1/MC HID2/MD CK VOUT R DOUT PSEL TEST0 TEST1 SPI Interface(2) B0054-01 PCM2704 PCM2705 PCM2706 PCM2707 SLES081F JUNE 2003 REVISED JANUARY 2009 www.ti.com BLOCK DIAGRAM (PCM2704DB/PCM2705DB) (1) Applies to PCM2704DB (2) Applies to PCM2705DB Submit Documentation Feedback Copyright 2003 2009, Texas Instruments Incorporated Product Folder Link(s): PCM2704 PCM2705 PCM2706 PCM2707 PCM2704 and PCM2705 Not Recommended For New Designs

VCCP VCCL VCCR VDD ZGNDDGNDAGNDRAGNDLPGND VCOM Analog PLL FIFO DAC VOUT L S/PDIF Encoder XTI XTO12 MHz PLL (×8) 96 MHz Tracker (SpAct) USB Protocol Controller Power Manager 5-V to 3.3-V Voltage Regulator Control Endpoint ISO-Out Endpoint HID Endpoint VBUS USB SIE XCVR DT HOST HID0/MS HID1/MC HID2/MD CK VOUT R FUNC1 DOUT FUNC3 I2S I/F PSEL TEST EEPROM Interface(1) SPI Interface(2) FUNC2 FUNC0 FSEL BCK DIN SYSCK LRCK DOUT HID3: Next Track(1) HID4: Previous Track(1) HID5: Stop(1) HID6: Play/Pause(1) B0055-01 PCM2704 PCM2705 PCM2706 PCM2707 www.ti.com SLES081F JUNE 2003 REVISED JANUARY 2009 BLOCK DIAGRAM (PCM2706PJT/PCM2707PJT) (1) Applies to PCM2706PJT (2) Applies to PCM2707PJT Copyright 2003 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM2704 PCM2705 PCM2706 PCM2707 PCM2704 and PCM2705 Not Recommended For New Designs

f – Frequency [× fS] −140 −120 −100 −80 −60 −40 −20 0 1 2 3 4 Amplitude – dB G001 f – Frequency [× fS] −0.05 −0.04 −0.03 −0.02 −0.01 0.00 0.01 0.02 0.03 0.04 0.05 Amplitude – dB G002 DAC Analog Low-Pass Filter Frequency Response −2.0 −1.5 −1.0 −0.5 0.0 f – Frequency – kHz Amplitude – dB 0.01 1 10 1000.1 G003 −80 −60 −40 −20 f – Frequency – kHz Amplitude – dB 1 100 1k 10k10 G004 PCM2704 PCM2705 PCM2706 PCM2707 SLES081F JUNE 2003 REVISED JANUARY 2009 www.ti.com All specifications at T A °C, V BUS f S 44.1 kHz, f IN kHz, 16-bit data (unless otherwise noted). AMPLITUDE AMPLITUDE vs vs FREQUENCY FREQUENCY Figure Frequency Response Figure Pass-Band Ripple AMPLITUDE AMPLITUDE vs vs FREQUENCY FREQUENCY Figure Pass-Band Characteristics Figure Stop-Band Characteristics Submit Documentation Feedback Copyright 2003 2009, Texas Instruments Incorporated Product Folder Link(s): PCM2704 PCM2705 PCM2706 PCM2707 PCM2704 and PCM2705 Not Recommended For New Designs

0.00 0.01 0.02 0.03 0.04 0.05 −50 −25 0 25 50 75 100 TA – Free-Air Temperature – °C THD+N – Total Harmonic Distortion + Noise – % Bus-Powered VOUT = 0 dB 32 W 10 kW G005 0.00 0.01 0.02 0.03 0.04 0.05 −50 −25 0 25 50 75 100 TA – Free-Air Temperature – °C THD+N – Total Harmonic Distortion + Noise – % Self-Powered VOUT = 0 dB 32 W 10 kW G006 0.00 0.01 0.02 0.03 0.04 0.05 4.0 4.5 5.0 5.5 VCC – Supply Voltage – V THD+N – Total Harmonic Distortion + Noise – % 32 Ω 10 kΩ Bus-Powered VOUT = 0 dB G007 0.00 0.01 0.02 0.03 0.04 0.05 VCC – Supply Voltage – V THD+N – Total Harmonic Distortion + Noise – % 32 Ω 10 kΩ Self-Powered VOUT = 0 dB G008 PCM2704 PCM2705 PCM2706 PCM2707 www.ti.com SLES081F JUNE 2003 REVISED JANUARY 2009 All specifications at T A °C, V BUS f S 44.1 kHz, f IN kHz, 16-bit data (unless otherwise noted). TOTAL HARMONIC DISTORTION NOISE TOTAL HARMONIC DISTORTION NOISE vs vs FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE Figure Figure TOTAL HARMONIC DISTORTION NOISE TOTAL HARMONIC DISTORTION NOISE vs vs SUPPLY VOLTAGE SUPPLY VOLTAGE Figure Figure Copyright 2003 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM2704 PCM2705 PCM2706 PCM2707 PCM2704 and PCM2705 Not Recommended For New Designs

0.00 0.01 0.02 0.03 0.04 0.05 30 35 40 45 50 fS – Sampling Frequency – kHz THD+N – Total Harmonic Distortion + Noise – % 32 Ω 10 kΩ Bus-Powered VOUT = 0 dB G009 0.00 0.01 0.02 0.03 0.04 0.05 30 35 40 45 50 fS – Sampling Frequency – kHz THD+N – Total Harmonic Distortion + Noise – % 32 Ω 10 kΩ Self-Powered VOUT = 0 dB G010 101 103 105 −50 −25 0 25 50 75 100 TA – Free-Air Temperature – °C Dynamic Range and SNR – dB Bus-Powered Dynamic Range SNR G011 101 103 105 −50 −25 0 25 50 75 100 TA – Free-Air Temperature – °C Dynamic Range and SNR – dB Self-Powered Dynamic Range SNR G012 PCM2704 PCM2705 PCM2706 PCM2707 SLES081F JUNE 2003 REVISED JANUARY 2009 www.ti.com TYPICAL PERFORMANCE CURVES (continued) All specifications at T A °C, V BUS f S 44.1 kHz, f IN kHz, 16-bit data (unless otherwise noted). TOTAL HARMONIC DISTORTION NOISE TOTAL HARMONIC DISTORTION NOISE vs vs SAMPLING FREQUENCY SAMPLING FREQUENCY Figure Figure 10. DYNAMIC RANGE and SNR DYNAMIC RANGE and SNR vs vs FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE Figure 11. Figure 12. Submit Documentation Feedback Copyright 2003 2009, Texas Instruments Incorporated Product Folder Link(s): PCM2704 PCM2705 PCM2706 PCM2707 PCM2704 and PCM2705 Not Recommended For New Designs

VCC – Supply Voltage – V Dynamic Range and SNR – dB 101 103 105 4.0 4.5 5.0 5.5 Dynamic Range Bus-Powered G013 VCC – Supply Voltage – V Dynamic Range and SNR – dB SNR 101 103 105 Dynamic Range Self-Powered G014 101 103 105 30 35 40 45 50 SNR fS – Sampling Frequency – kHz Dynamic Range and SNR – dB Dynamic Range Bus-Powered G015 101 103 105 30 35 40 45 50 SNR fS – Sampling Frequency – kHz Dynamic Range and SNR – dB Dynamic Range Self-Powered G016 PCM2704 PCM2705 PCM2706 PCM2707 www.ti.com SLES081F JUNE 2003 REVISED JANUARY 2009 TYPICAL PERFORMANCE CURVES (continued) All specifications at T A °C, V BUS f S 44.1 kHz, f IN kHz, 16-bit data (unless otherwise noted). DYNAMIC RANGE and SNR DYNAMIC RANGE and SNR vs vs SUPPLY VOLTAGE SUPPLY VOLTAGE Figure 13. Figure 14. DYNAMIC RANGE and SNR DYNAMIC RANGE and SNR vs vs SAMPLING FREQUENCY SAMPLING FREQUENCY Figure 15. Figure 16. Copyright 2003 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM2704 PCM2705 PCM2706 PCM2707 PCM2704 and PCM2705 Not Recommended For New Designs

4.0 4.5 5.0 5.5 VBUS ± Supply Voltage ± V Suspend Current ± µA G017 100 150 200 −50 −25 0 25 50 75 100 TA – Free-Air Temperature – °C Suspend Current – mA G018 f – Frequency – kHz −140 −120 −100 −80 −60 −40 −20 0 5 10 15 20 Amplitude – dB G019 f – Frequency – kHz −140 −120 −100 −80 −60 −40 −20 0 20 40 60 80 100 120 Amplitude – dB G020 PCM2704 PCM2705 PCM2706 PCM2707 SLES081F JUNE 2003 REVISED JANUARY 2009 www.ti.com TYPICAL PERFORMANCE CURVES (continued) All specifications at T A °C, V BUS f S 44.1 kHz, f IN kHz, 16-bit data (unless otherwise noted). SUSPEND CURRENT SUSPEND CURRENT vs vs SUPPLY VOLTAGE FREE-AIR TEMPERATURE Figure 17. Figure 18. AMPLITUDE AMPLITUDE vs vs FREQUENCY FREQUENCY Figure 19. Output Spectrum dB, N 8192) Figure 20. Output Spectrum dB, N 8192) Submit Documentation Feedback Copyright 2003 2009, Texas Instruments Incorporated Product Folder Link(s): PCM2704 PCM2705 PCM2706 PCM2707 PCM2704 and PCM2705 Not Recommended For New Designs

(PCM2706/7) PCM2704 PCM2705 PCM2706 PCM2707 www.ti.com SLES081F JUNE 2003 REVISED JANUARY 2009 For both USB and audio functions, the PCM2704/5/6/7 requires a 12-MHz 500 ppm) clock, which can be generated by the built-in oscillator using a 12-MHz crystal resonator. The 12-MHz crystal resonator must be connected to XTI (pin for PCM2704/5, pin for PCM2706/7) and XTO (pin for PCM2704/5, pin for PCM2706/7) with one large (1-M Ω resistor and two small capacitors, the capacitance of which depends on the specified load capacitance of the crystal resonator. An external clock can be supplied from XTI (pin for PCM2704/5, pin for PCM2706/7). If an external clock is supplied, XTO (pin for PCM2704/5, pin for PCM2706/7) must be left open. Because no clock disabling pin is provided, it is not recommended to use the external clock supply. SSPND (pin for PCM2704/5, pin for PCM2706/7) is unable to use clock disabling. The PCM2704/5/6/7 has an internal power-on reset circuit, and it works automatically when V DD (pin for PCM2704/5, pin for PCM2706/7) exceeds V typical (1.6 V 2.4 V), which is equivalent to V BUS (pin for PCM2704/5, pin for PCM2706/7) exceeding V typical for bus-powered applications. Approximately 700 µ s is required until internal reset release. The PCM2704/5/6/7 has the following mode-select pins. PSEL (pin for PCM2704/5, pin for PCM2706/7) is dedicated to selecting the power source. This selection affects the configuration descriptor. While in bus-powered operation, maximum power consumption from V BUS is determined by HOST (pin for PCM2704/5, pin for PCM2706/7). For self-powered operation, HOST must be connected to V BUS of the USB bus with a pulldown resistor to detect attach and detach. (To avoid excessive suspend current, the pulldown should be a high-value resistor.) Table Power Configuration Select PSEL (self-powered)/100 mA (bus-powered) Attached to USB (self-powered)/500 mA (bus-powered) FSEL (pin determines the function of FUNC0 FUNC3 (pins 18, and 19) and DOUT (pin17). When the I S interface is required, FSEL must be set to LOW. Otherwise, FSEL must be set to HIGH. Table Function Select FSEL DOUT FUNC0 FUNC1 FUNC2 FUNC3 Data out LRCK BCK SYSCK Data in S/PDIF data Next track (HID) (1) Previous track (HID) (1) Stop (HID) (1) Play/pause (HID) (1) (1) Valid on the PCM2706; no function assigned on the PCM2707. Copyright 2003 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM2704 PCM2705 PCM2706 PCM2707 PCM2704 and PCM2705 Not Recommended For New Designs

www.ti.com Control data and audio data are transferred to the PCM2704/5/6/7 via (pin for PCM2704/5, pin for PCM2706/7) and D (pin for PCM2704/5, pin for PCM2706/7). should be pulled up with a 1.5-k Ω 5%) resistor. To avoid back voltage in self-powered operation, the device must not provide power to the pullup resistor on while V BUS of the USB port is inactive. All data to/from the PCM2704/5/6/7 are transferred at full speed. The following information is provided in the device descriptor. Some parts of the device descriptor can be modified through external ROM (PCM2704/6), SPI (PCM2705/7), or internal mask ROM on request. Table Device Descriptor DEVICE DESCRIPTOR 1.1 compliant Device class 0x00 (device defined interface level) Device subclass 0x00 (not specified) Device protocol 0x00 (not specified) Max packet size for endpoint bytes Vendor ID 0x08BB (default value, can be modified) 0x2704/0x2705/0x2706/0x2707 (These values correspond to the model number, and the value can be Product ID modified.) Device release number 1.0 (0x0100) Number of configurations Vendor strings Burr-Brown from TI (default value, can be modified) Product strings USB Audio DAC (default value, can be modified) Serial number Not supported The following information is contained in the configuration descriptor. Some parts of the configuration descriptor can be modified through external ROM (PCM2704/6), SPI (PCM2705/7), or internal mask ROM on request. Table Configuration Descriptor CONFIGURATION DESCRIPTOR (bus-powered or self-powered, depending on PSEL; no remote wake up. This value can Power attribute be modified.) 0x0A, 0x32 or 0xFA (20 mA for self-powered, 100 mA or 500 mA for bus-powered, depending on Max power PSEL and HOST. This value can be modified.) The following information is contained in the string descriptor. Some parts of the string descriptor can be modified through external ROM (PCM2704/6), SPI (PCM2705/7), or internal mask ROM on request. Table String Descriptor STRING DESCRIPTOR (default value, can be modified) USB Audio DAC (default value, can be modified) Submit Documentation Feedback Copyright 2003 2009, Texas Instruments Incorporated Product Folder Link(s): PCM2704 PCM2705 PCM2706 PCM2707 PCM2704 and PCM2705 Not Recommended For New Designs

Endpoint #2 (IF #1) Audio Streaming Interface Endpoint #0 Endpoint #5 (IF #2) HID Interface IT TID1 FU UID3 OT TID2 Standard Audio Control Interface (IF #0) PCM2704/5/6/7 M0024-01 Interface (Default/Control Interface) PCM2704 PCM2705 PCM2706 PCM2707 www.ti.com SLES081F JUNE 2003 REVISED JANUARY 2009 Figure illustrates the USB audio function topology. The PCM2704/5/6/7 has three interfaces. Each interface is enabled by some alternative settings. Figure 21. USB Audio Function Topology Interface is the control interface. Setting is the only possible setting for interface #0. Setting describes the standard audio control interface. Audio control interface consists of a terminal. The PCM2704/5/6/7 has three terminals: Input terminal (IT #1) for isochronous-out stream Output terminal (OT #2) for audio analog output Feature unit (FU #3) for DAC digital attenuator Input terminal is defined as a USB stream (terminal type 0x0101). Input terminal can accept two-channel audio streams constructed of left and right channels. Output terminal is defined as a speaker (terminal type 0x0301). Feature unit supports the following sound control features: Volume control Mute control The built-in digital volume controller can be manipulated by an audio-class-specific request from dB to dB in steps of dB. Changes are made by incrementing or decrementing one step dB) for every 1/f S time interval, until the volume level reaches the requested value. Each channel can be set to a separate value. The master volume control is not supported. A request to the master volume is stalled and ignored. The built-in digital mute controller can be manipulated by an audio-class-specific request. A master mute control request is acceptable. A mute control request to an individual channel is stalled and ignored. The digital volume control does not affect the S/PDIF and I S outputs (PCM2706/7). Copyright 2003 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM2704 PCM2705 PCM2706 PCM2707 PCM2704 and PCM2705 Not Recommended For New Designs

(Isochronous-Out Interface) Interface (HID Interface) Endpoints PCM2704 PCM2705 PCM2706 PCM2707 SLES081F JUNE 2003 REVISED JANUARY 2009 www.ti.com Interface is for the audio-streaming data-out interface. Interface has the following three alternative settings. Alternative setting is the zero-bandwidth setting. All other alternative settings are operational settings. ALTERNATIVE TRANSFER SAMPLING RATE DATA FORMAT SETTING MODE (kHz) Zero bandwidth 16-bit Stereo complement (PCM) Adaptive 32, 44.1, 16-bit Mono complement (PCM) Adaptive 32, 44.1, Interface is the interrupt-data-in interface. Interface comprises the HID consumer control device. Alternative setting is the only possible setting for interface #2. On the HID device descriptor, eight HID items are reported as follows for any model, in any configuration. Basic HID Operation Interface can report the following three key statuses for any model. These statuses can be set by the HID0 HID2 pins (PCM2704/6) or the SPI port (PCM2705/7). Mute (0xE2) Volume up (0xE9) Volume down (0xEA) Extended HID Operation (PCM2705/6/7) By using the FUNC0– FUNC3 pins (PCM2706) or the SPI port (PCM2705/7), the following additional conditions can be reported to the host. Play/Pause (0xCD) Stop (0xB7) Previous (0xB6) Next (0xB5) Auxiliary HID Status Report (PCM2705/7) One additional HID status can be reported to the host though the SPI port. This status flag is defined by SPI command or external ROM. This definition must be described as on the report descriptor with a three-byte usage ID. AL A/V Capture (0x0193) is assigned as the default for this status flag. The PCM2704/5/6/7 has three endpoints: Control endpoint (EP #0) Isochronous-out audio data-stream endpoint (EP #2) HID endpoint (EP #5) The control endpoint is a default endpoint. The control endpoint is used to control all functions of the PCM2704/5/6/7 by standard USB request and USB audio-class-specific request from the host. The isochronous-out audio data-stream endpoint is an audio sink endpoint that receives the PCM audio data. The isochronous-out audio data-stream endpoint accepts the adaptive transfer mode. The HID endpoint is an interrupt-in endpoint. The HID endpoint reports HID status every ms. The HID endpoint is defined as a consumer-control device. The HID function is designed as an independent endpoint from the isochronous-out endpoint. This means that the effect of HID operation depends on host software. Typically, the HID function is used to control the primary audio-out device. Submit Documentation Feedback Copyright 2003 2009, Texas Instruments Incorporated Product Folder Link(s): PCM2704 PCM2705 PCM2706 PCM2707 PCM2704 and PCM2705 Not Recommended For New Designs

—S/PDIF Output Channel Status Information Copyright Management Digital Audio Interface S Interface Output (PCM2706/7) LRCK SYSCK (256□f )S BCK (64□f )S R-ChannelL-Channel DOUT 1 1 1 1 1 1 2 2 2 2 2 2 3 3 3 3 MSB MSB MSBLSB LSB 1/fS 14 14 14 14 15 15 15 15 16 16 16 16DIN T0009-04 PCM2704 PCM2705 PCM2706 PCM2707 www.ti.com SLES081F JUNE 2003 REVISED JANUARY 2009 The PCM2704/5/6/7 has a DAC that uses an oversampling technique with 128-f S second-order multibit noise shaping. This technique provides extremely low quantization noise in the audio band, and the built-in analog low-pass filter removes the high-frequency components of the noise-shaping signal. DAC outputs through the headphone amplifier V OUT L and V OUT R can provide mW at Ω as well as 1.8 V PP into a 10-k Ω load. The PCM2704/5/6/7 employs S/PDIF output. Isochronous-out data from the host are encoded to S/PDIF output DOUT, as well as to DAC analog outputs V OUT L and V OUT Interface format and timing follow the IEC-60958 standard. Monaural data are converted to the stereo format at the same data rate. S/PDIF output is not supported in the I S I/F enable mode. The implementation of this feature is optional. Note that it is your responsibility to determin whether to implement this feature in your product or not. The channel status information is fixed as consumer application, PCM mode, copyright, and digital/digital converter. All other bits are fixed as 0s, except for the sample frequency, which is set automatically according to the data received through the USB. Digital audio data output always is encoded as original with SCMS control. Only one generation of digital duplication is allowed. The PCM2706 and PCM2707 can support the I S interface, which is enabled by FSEL (pin 9). In the I S interface enabled mode, pins 18, 19, and are assigned as DIN, SYSCK, BCK, LRCK, and DOUT, respectively. They provide digital output/input data in the 16-bit I S format, which also is accepted by the internal DAC. I S interface format and timing are shown in Figure Figure and Figure Figure 22. Audio Data Interface Format Copyright 2003 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM2704 PCM2705 PCM2706 PCM2707 PCM2704 and PCM2705 Not Recommended For New Designs

t(BCH) DOUT (Output) t(BCL) t(BL) t(BCY) 50% of VDD 50% of VDD 50% of VDD LRCK (Output) BCK (Output) DIN (Input) t(DH) t(DS) 50% of VDD t(BD) t(LD) T0010-05 SYSCK (Output) LRCK (Output) BCK (Output) t(SLL) t(SBH)t(SBL) t(SLH) T0196-01 PCM2704 PCM2705 PCM2706 PCM2707 SLES081F JUNE 2003 REVISED JANUARY 2009 www.ti.com SYMBOL PARAMETER MIN MAX UNIT t (BCY) BCK pulse cycle time 300 ns t (BCH) BCK pulse duration, HIGH 100 ns t (BCL) BCK pulse duration, LOW 100 ns t (BL) LRCK delay time from BCK falling edge ns t (BD) DOUT delay time from BCK falling edge ns t (LD) DOUT delay time from LRCK edge ns t (DS) DIN setup time ns t (DH) DIN hold time ns NOTE: Load capacitance of LRCK, BCK, and DOUT is pF. Figure 23. Audio Interface Timing SYMBOL PARAMETER MIN MAX UNIT t (SLL) t (SLH) LRCK delay time from SYSCK rising edge ns t (SBL) t (SBH) BCK delay time from SYSCK rising edge ns NOTE: Load capacitance is pF. Figure 24. Audio Clock Timing Submit Documentation Feedback Copyright 2003 2009, Texas Instruments Incorporated Product Folder Link(s): PCM2704 PCM2705 PCM2706 PCM2707 PCM2704 and PCM2705 Not Recommended For New Designs

(PCM2704/6) DT CK S Start Condition 1−7 8 1−8 9 1−8 9 9 P Stop Condition Device Address ACK DATA ACK DATA ACK NACKR/W R/W : Read Operation if 1; Otherwise, Write Operation ACK: Acknowledgment of a Byte if 0 DATA: 8 Bits (Byte) NACK: Not Acknowledgment if 1 T0049-02 PCM2704 PCM2705 PCM2706 PCM2707 www.ti.com SLES081F JUNE 2003 REVISED JANUARY 2009 The descriptor data can be modified through I C port by external ROM (PCM2704/6) or through our SPI port by an SPI host such as an MCU (PCM2705/7) under a particular condition of PSEL pin and HOST pin. A condition of PSEL pin High and HOST pin High is needed to modify the descriptor data, and pull-up must not be activated before completion of programming the descriptor data through external ROM or SPI port. The descriptor data have to be sent from external ROM to PCM2704/6 or or from SPI host to PCM2705/7 in LSB first with specified byte order. Also, the content of the power attribute and max power must be consistent with PSEL setting and power usage from USB VBUS of actual application. Therefore, the descriptor data modification in self-powered configuration (PSEL Low) is not supported. The PCM2704/6 supports an external ROM interface to override internal descriptors. Pin (for PCM2704)/pin (for PCM2706) is assigned as DT (serial data) and pin (for PCM2704)/pin (for PCM2706) is assigned as CK (serial clock) of the I C interface when using the external ROM descriptor. Descriptor data is transferred from the external ROM to the PCM2704/6 through the I C interface the first time when the device activates after power-on reset. Before completing a read of the external ROM, the PCM2704/6 replies with NACK for any USB command request from the host to the device itself. The descriptor data, which can be in external ROM, are as follows. String descriptors must be described in ANSI ASCII code byte for each character). String descriptors are converted automatically to unicode strings for transmission to the host. The device address of the external ROM is fixed as 0xA0. The data must be stored from address 0x00 and must consist of bytes, as described in the following items. The data bits must be sent from LSB to MSB on the I C bus. This means that each byte of data must be stored with its bits in reverse order. Read operation is performed at a frequency of XTI/384 (approximately kHz). The content of power attribute and max power must be consistent with actual application circuit configuration (PSEL setting and actual power usage from VBUS of USB connector); otherwise, it may cause improper or unexpected PCM2704/6 operation. Vendor ID bytes) Product ID bytes) Product string (16 bytes in ANSI ASCII code) Vendor string (32 bytes in ANSI ASCII code) Power attribute byte) Max power byte) Auxiliary HID usage ID in report descriptor bytes) M M M S S M S M S M M S Device address R/W ACK DATA ACK DATA ACK ... NACK P Figure 25. External ROM Read Operation Copyright 2003 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM2704 PCM2705 PCM2706 PCM2707 PCM2704 and PCM2705 Not Recommended For New Designs

t(BUF) t(D-SU) t(D-HD) Start t(LOW) t(S-HD) t(CK-F) t(CK-R) t(HI) Repeated Start t(RS-SU) t(RS-HD) t(DT-F) t(DT-R) t(P-SU) Stop T0050-02 PCM2704 PCM2705 PCM2706 PCM2707 SLES081F JUNE 2003 REVISED JANUARY 2009 www.ti.com SYMBOL PARAMETER MIN MAX UNIT f (CK) CK clock frequency 100 kHz t (BUF) Bus free time between a STOP and a START condition 4.7 µ s t (LOW) Low period of the CK clock 4.7 µ s t (HI) High period of the CK clock µ s t (RS-SU) Setup time for START/repeated START condition 4.7 µ s t (S-HD) Hold time for START/repeated START condition µ s t (RS-HD) t (D-SU) Data setup time 250 ns t (D-HD) Data hold time 900 ns t (CK-R) Rise time of CK signal 0.1 C B 1000 ns t (CK-F) Fall time of CK signal 0.1 C B 1000 ns t (DT-R) Rise time of DT signal 0.1 C B 1000 ns t (DT-F) Fall time of DT signal 0.1 C B 1000 ns t (P-SU) Setup time for STOP condition µ s C B Capacitive load for DT and CK lines 400 pF V NH Noise margin at HIGH level for each connected device (including hysteresis) 0.2 V DD V Figure 26. External ROM Read Interface Timing Requirements Submit Documentation Feedback Copyright 2003 2009, Texas Instruments Incorporated Product Folder Link(s): PCM2704 PCM2705 PCM2706 PCM2707 PCM2704 and PCM2705 Not Recommended For New Designs

www.ti.com SLES081F JUNE 2003 REVISED JANUARY 2009 Here is an example of external ROM data, with an explanation of the example following the data. 0xBB, 0x08, 0x04, 0x27, 0x50, 0x72, 0x6F, 0x64, 0x75, 0x63, 0x74, 0x20, 0x73, 0x74, 0x72, 0x69, 0x6E, 0x67, 0x73, 0x2E, 0x56, 0x65, 0x6E, 0x64, 0x6F, 0x72, 0x20, 0x73, 0x74, 0x72, 0x69, 0x6E, 0x67, 0x73, 0x20, 0x61, 0x72, 0x65, 0x20, 0x70, 0x6C, 0x61, 0x63, 0x65, 0x64, 0x20, 0x68, 0x65, 0x72, 0x65, 0x2E, 0x20, 0x80, 0x7D, 0x0A, 0x93, 0x01 The data are stored beginning at address 0x00. Vendor ID: 0x08BB Product ID: 0x2704 Product string: Product strings (16 bytes). Vendor string: Vendor strings are placed here (32 bytes, visible characters are followed by space). Power attribute (bmAttribute): 0x80 (Bus-powered). Max power (maxPower): 0x7D (250 mA). Auxiliary HID usage ID: 0x0A, 0x93, 0x01 (AL A/V capture). Note that the data bits must be sent from LSB to MSB on the I C bus. This means that each data byte must be stored with its bits in reverse order. Copyright 2003 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM2704 PCM2705 PCM2706 PCM2707 PCM2704 and PCM2705 Not Recommended For New Designs

(PCM2705/7) t(MCH) 50% of VDDMS t(MLS) LSB 50% of VDD 50% of VDD t(MCL) t(MHH) t(MLH) t(MCY) t(MDH) t(MDS) MC MD T0013-04 MC MS MD

16 Bits

(1) Single Write Operation MSB LSB MSB (2) Continuous Write Operation MSB LSB MSB LSB MSB LSB

16 Bits /C0121 N Frames

www.ti.com The PCM2705/7 supports the serial programming interface (SPI) to program the descriptor and to set the HID state. Descriptor data are described in the SubSec1 8.8 External ROM Descriptor section. SYMBOL PARAMETER MIN TYP MAX UNIT t (MCY) MC pulse cycle time 100 ns t (MCL) MC low-level time ns t (MCH) MC high-level time ns t (MHH) MS high-level time 100 ns t (MLS) MS falling edge to MC rising edge ns t (MLH) MS hold time ns t (MDH) MD hold time ns t (MDS) MD setup time ns Figure 27. SPI Timing Diagram Figure 28. SPI Write Operation Submit Documentation Feedback Copyright 2003 2009, Texas Instruments Incorporated Product Folder Link(s): PCM2704 PCM2705 PCM2706 PCM2707 PCM2704 and PCM2705 Not Recommended For New Designs

(PCM2705/7) PCM2704 PCM2705 PCM2706 PCM2707 www.ti.com SLES081F JUNE 2003 REVISED JANUARY 2009 B15 B14 B13 B12 B11 B10 ST ADDR D[7:0] Function of the lower bits depends on the value of the ST (B11) bit. ST (HID status write) Reports MUTE HID status to the host (active high) Reports volume-up HID status to the host (active high) Reports volume-down HID status to the host (active high) Reports next-track HID status to the host (active high) Reports previous-track HID status to the host (active high) Reports stop HID status to the host (active high) Reports play/pause HID status to the host (active high) Reports extended command status to the host (active high) ST (ROM data write) D[7:0] Internal descriptor ROM data, D0:LSB, D7:MSB The content of power attribute and max power must be consistent with the actual application circuit configuration (PSEL setting and actual power usage from VBUS of USB connector); otherwise, it may cause improper or unexpected PCM2705/7 operation. ADDR Starts write operation for internal descriptor reprogramming (active high) This bit resets descriptor ROM address counter and indicates following words should be ROM data (described in the External ROM Example section). 456 bits of ROM data must be continuously followed after this bit has been asserted. The data bits must be sent from LSB (D0) to MSB (D7). To set ADDR high, ST must be set low. Note that the lower bits are still active as an HID status write when ST is set low. ST Determines the function of the lower 8-bit data as follows HID status write Descriptor ROM data write Table Functionality of ST and ADDR Bit Combinations ST ADDR FUNCTION HID status write HID status write and descriptor ROM address reset Descriptor ROM data write Reserved Copyright 2003 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM2704 PCM2705 PCM2706 PCM2707 PCM2704 and PCM2705 Not Recommended For New Designs

Power-On, Attach, and Playback Sequence ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ D+/D− 2.0 V (Typ.) 0 V Internal Reset Ready for Setup Î Î Î Î ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ SOF ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ Î Î Î Î Ready for Playback Î Î Î Î Î Î Î Î Bus Reset Set Configuration SOF SOF Î Î Î Î BPZ Bus Idle 3.3 V (Typ.) 1st Audio Data 2nd Audio Data SSPND VOUT L VOUT R 700 µs Device Setup 1 ms VDD T0055-01 PCM2704 PCM2705 PCM2706 PCM2707 SLES081F JUNE 2003 REVISED JANUARY 2009 www.ti.com The PCM2704/5/6/7 is ready for setup when the reset sequence has finished and the USB bus is attached. After a connection has been established by setup, the PCM2704/5/6/7 is ready to accept USB audio data. While waiting for the audio data (idle state), the analog output is set to bipolar zero (BPZ). When receiving the audio data, the PCM2704/5/6/7 stores the first audio packet, which contains ms of audio data, into the internal storage buffer. The PCM2704/5/6/7 starts playing the audio data after detecting the next subsequent start-of-frame (SOF) packet. Figure 29. Initial Sequence Submit Documentation Feedback Copyright 2003 2009, Texas Instruments Incorporated Product Folder Link(s): PCM2704 PCM2705 PCM2706 PCM2707 PCM2704 and PCM2705 Not Recommended For New Designs

Play, Stop, and Detach Sequence VBUS VOUT L VOUT R Audio DataAudio Data Last Audio Data Detach SOF SOF SOF SOF SOF 1 ms ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ Î Î Î Î ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎ ÎÎ ÎÎ D+/D± T0056-01 Suspend and Resume Sequence 5 ms D+/D− SSPND Idle ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ Suspend VOUT L VOUT R Active Î Î Î Î Î 2.5 ms Active T0057-01 PCM2704 PCM2705 PCM2706 PCM2707 www.ti.com SLES081F JUNE 2003 REVISED JANUARY 2009 When the host finishes or aborts the playback, the PCM2704/5/6/7 stops playing after completing the output of the last audio data. Figure 30. Play, Stop, and Detach The PCM2704/5/6/7 enters the suspend state after the USB bus has been in a constant idle state for approximately ms. While the PCM2704/5/6/7 is in the suspend state, SSPND flag (pin for PCM2704/5, pin for PCM2706/7) is asserted. The PCM2704/5/6/7 wakes up immediately when detecting the non-idle state on the USB bus. Figure 31. Suspend and Resume Copyright 2003 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM2704 PCM2705 PCM2706 PCM2707 PCM2704 and PCM2705 Not Recommended For New Designs

(Example of USB Speaker) TEST0 XTO 28 PCM2704DB CK DT PSEL (2) DOUT DGND V DD V BUS SSPND HOST (2) XTI TEST1 HID2/MD PGND VCCP (3) HID0/MS HID1/MC External□ROM (3) (Optional) SCL ZGND AGNDL V CCL VOUT L (1) AGNDR VCCR VOUTR (1) VCOM GND SDA S/PDIF□OUT C7R2USB ’B’ Connector VBUS SUSPEND + C8 C10C11 C12 R6 R7 R8 TPA200X Power Amp VOLUME– VOLUME+ MUTE C13 C14 PCM2704 PCM2705 PCM2706 PCM2707 SLES081F JUNE 2003 REVISED JANUARY 2009 www.ti.com Figure illustrates a typical circuit connection for an internal-descriptor, bus-powered, 500-mA application. NOTE: X 12-MHz crystal resonator. C C 10-pF to 33-pF capacitor (depending on load capacitance of crystal resonator). C µ F ceramic capacitor. C 10- µ F electrolytic capacitor. C C 100- µ F electrolytic capacitor (depending on tradeoff between required frequency response and discharge time for resume). C C 0.022- µ F ceramic capacitor. C C µ F electrolytic capacitor. R M Ω resistor. R R 1.5 k Ω resistors. R R Ω resistors. R R Ω resistors. R R 330 Ω resistors (depending on tradeoff between required THD performance and pop-noise level for suspend). (1) Output impedance of V OUT L and V OUT R during suspend mode or lack of power supply is k Ω 20%, which is the discharge path for C and C (2) Descriptor programming through external ROM is only available when PSEL and HOST are high. (3) External ROM power can be supplied from V CC but any other active component must not use V CCP V CCL V CCR or V DD as a power source. Figure 32. Bus-Powered Application NOTE: The circuit illustrated in Figure is for information only. The entire board design should be considered to meet the USB specification as a USB-compliant product. Submit Documentation Feedback Copyright 2003 2009, Texas Instruments Incorporated Product Folder Link(s): PCM2704 PCM2705 PCM2706 PCM2707 PCM2704 and PCM2705 Not Recommended For New Designs

(Example of Remote Headphone) VOLUME+ External□ROM (3) (Optional) SDA VBUS GND SCL USB ’B’ Connector SUSPEND R7 R8 Headphone 31 30 29 28 27 FSEL TEST SSPNDXTI XTO CK DT PSEL (2) V COM AGNDR V CCR V OUT R (1) V OUT L(1) V CCL AGNDLZGND 32 26 PGND V CCP (3) HOST (2) FUNC3 FUNC0 HID0/MS HID1/MC HID2/MD PCM2706PJT 10 11 12 13 1491 5 16 VBUS VDD DGND FUNC1 FUNC2 DOUT C6 C3 C4 C1 C2 R11 C10 R9 R10 C11 C12 R4PLAY/PAUSE NEXT TRACK MUTE VOLUME– PREVIOUS□TRACK STOP PCM2704 PCM2705 PCM2706 PCM2707 www.ti.com SLES081F JUNE 2003 REVISED JANUARY 2009 Figure illustrates a typical circuit connection for a bus-powered, 100-mA headphone with seven HIDs. NOTE: X 12-MHz crystal resonator. C C 10-pF to 33-pF capacitors (depending on load capacitance of crystal resonator). C C C µ F ceramic capacitors. C 10- µ F electrolytic capacitor. C C 100- µ F electrolytic capacitors (depending on required frequency response). C C 0.022- µ F ceramic capacitors. R M Ω resistor. R R 1.5 k Ω resistors. R R Ω resistors. R R Ω resistors. R 3.3 k Ω resistors. (1) Output impedance of V OUT L and V OUT R during suspend mode or lack of power supply is k Ω 20%, which is the discharge path for C and C (2) Descriptor programming through external ROM is only available when PSEL and HOST are high. (3) External ROM power can be supplied from V CCP but any other active component must not use V CCP V CCL V CCR or V DD as a power source. Figure 33. Bus-Powered Application NOTE: The circuit illustrated in Figure is for information only. The entire board design should be considered to meet the USB specification as a USB-compliant product. Copyright 2003 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM2704 PCM2705 PCM2706 PCM2707 PCM2704 and PCM2705 Not Recommended For New Designs

(Example of DSP Surround Processing Amp) VBUS (3) GND USB ’B’ Connector SUSPEND R8 R9 Headphone 31 30 29 28 27 FSEL TEST SSPNDXTI XTO CK DT PSEL (2) V COM AGNDR V CCR V OUT R V OUT L(1) V CCL AGNDLZGND 32 26 PGND V CCP HOST (2) FUNC3 FUNC0 HID0/MS (4) HID1/MC HID2/MD PCM2707PJT 10 11 12 13 1491 51 6 VBUS VDD DGND FUNC1 FUNC2 DOUT C6 C3 C4 C1 C2 R10 R11 C10 C11 R4 R12 R 2 (3) DOUT SYSTEM□CLOCK BCK MD MC MS LRCK DIN T AS300X (4) I2S I/F□Audio□Device Power 3.3□V GND (3) PCM2704 PCM2705 PCM2706 PCM2707 SLES081F JUNE 2003 REVISED JANUARY 2009 www.ti.com Figure illustrates a typical circuit connection for an I and SPI-enabled self-powered application. NOTE: X 12-MHz crystal resonator. C C 10-pF to 33-pF capacitors (depending on load capacitance of crystal resonator). C C µ F ceramic capacitors. C C 0.1- µ F ceramic capacitor and 10- µ F electrolytic capacitor. C 10- µ F electrolytic capacitors. C C 100- µ F electrolytic capacitors (depending on required frequency response). C C 0.022- µ F ceramic capacitors. R R M Ω resistors. R R 1.5 k Ω resistors. R R Ω resistors. R R Ω resistors. R 3.3 k Ω resistors. (1) Output impedance of V OUT L and V OUT R during suspend mode or lack of power supply is k Ω 20%, which is the discharge path for C and C (2) Descriptor programming through SPI is only available when PSEL and HOST are high. (3) pull-up must not be activated (HIGH: 3.3V) while the device is detached from USB or power supply is not applied on V DD and V CC VBUS of USB (5V) can be used to detect USB power status. (4) MS must be high until the PCM2707 power supply is ready and the SPI host (DSP) is ready to send data. Also, the SPI host must handle the pull-up if the descriptor is programmed through the SPI. pull-up must not be activated (HIGH 3.3 before programming of the PCM2707 through the SPI is complete. Figure 34. Self-Powered Application NOTE: The circuit illustrated in Figure is for information only. The entire board design should be considered to meet the USB specification as a USB-compliant product. Submit Documentation Feedback Copyright 2003 2009, Texas Instruments Incorporated Product Folder Link(s): PCM2704 PCM2705 PCM2706 PCM2707 PCM2704 and PCM2705 Not Recommended For New Designs

www.ti.com SLES081F JUNE 2003 REVISED JANUARY 2009 For current information on the PCM2704/2705/2706/2707 operating environment, see the Updated Operating Environments for PCM270X, PCM290X report, SLAA374 available through the TI web site at www.ti.com Copyright 2003 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): PCM2704 PCM2705 PCM2706 PCM2707 PCM2704 and PCM2705 Not Recommended For New Designs

www.ti.com NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (November 2007) to Revision F Page Added new feature Moved text to end of Digital Audio Interface-S/PDIF Output section Added Descriptor Data Modification paragraph Deleted HOST from list of circuit configuration terms Deleted HOST from list of circuit configuration terms Added notes to Figure 32, Figure 33, and Figure for clarifying requirement of descriptor programing. Changes from Revision D (December 2006) to Revision E Page Deleted operating environment information from data sheet and added reference to application report Submit Documentation Feedback Copyright 2003 2009, Texas Instruments Incorporated Product Folder Link(s): PCM2704 PCM2705 PCM2706 PCM2707 PCM2704 and PCM2705 Not Recommended For New Designs

www.ti.com 24-Apr-2015 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples PCM2704DB NRND SSOP DB 28 47 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 PCM2704 PCM2704DBG4 NRND SSOP DB 28 47 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 PCM2704 PCM2704DBR NRND SSOP DB 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 PCM2704 PCM2704DBRG4 NRND SSOP DB 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 PCM2704 PCM2705DB NRND SSOP DB 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 PCM2705 PCM2705DBG4 NRND SSOP DB 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 PCM2705 PCM2705DBR NRND SSOP DB 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 PCM2705 PCM2705DBRG4 NRND SSOP DB 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 PCM2705 PCM2706PJT ACTIVE TQFP PJT 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 PCM2706 PCM2706PJTG4 ACTIVE TQFP PJT 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 PCM2706 PCM2706PJTR ACTIVE TQFP PJT 32 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 PCM2706 PCM2707PJT ACTIVE TQFP PJT 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 PCM2707 PCM2707PJTG4 ACTIVE TQFP PJT 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 PCM2707 PCM2707PJTR ACTIVE TQFP PJT 32 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 PCM2707 PCM2707PJTRG4 ACTIVE TQFP PJT 32 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -25 to 85 PCM2707 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

www.ti.com 24-Apr-2015 Addendum-Page 2 PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCM2704DBR SSOP DB 28 2000 336.6 336.6 28.6 PCM2705DBR SSOP DB 28 2000 367.0 367.0 38.0 PCM2706PJTR TQFP PJT 32 1000 367.0 367.0 38.0 PCM2707PJTR TQFP PJT 32 1000 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 Pack Materials-Page 2

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 4040065 /E 12/01

28 PINS SHOWN

8,20 7,40 0,55 0,95 0,25 12,90 12,30 10,50 8,50 Seating Plane 9,907,90 10,50 9,90 0,38 5,60 5,00 0,22 A 2016 6,506,50 0,05 MIN 5,905,90 DIM A MAX A MIN PINS ** 2,00 MAX 6,90 7,50 0,65 M0,15 0°–/C02578° 0,10 0,09 0,25 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150

MPQF112 – NOVEMBER 2001 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PJT (S-PQFP–N32) PLASTIC QUAD FLATPACK 4203540/A 11/01 0,45 0,30 7,00 SQ 0,95 1,05 Seating Plane 0,45 0,75 0,25 Gage Plane 0,80 0,20 SQ9,00 1,00 1,20 0,10 0,05 0,15 0,20 0,09 M 0°– 7° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026

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Summary

SINGLE-ENDED HEADPHONE OUTPUT AND S/PDIF OUTPUT

Description