PCM1602A TI | Alldatasheet
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www.ti.com SLES146A –AUGUST 2005–REVISED OCTOBER 2010 24-Bit,192-kHzSampling,6-Channel,EnhancedMultilevel, Delta-SigmaDigital-to-AnalogConverter Check forSamples: PCM1602A 1FEATURES
APPLICATIONS
2345• 24-BitResolution
- IntegratedA/V Receivers• Analog Performance:
- DVD Movie and Audio Players– Dynamic Range: 105 dB, Typical
- HDTV Receivers– SNR: 105 dB, Typical • Car Audio Systems– THD+N: 0.002%,Typical • DVD Add-On Cards forHigh-End PCs– Full-ScaleOutput:3.1VPP ,Typical • DigitalAudio Workstations
- 4×/8× Oversampling InterpolationFilter: • Other MultichannelAudio Systems – Stop-Band Attenuation:–55 dB – Pass-Band Ripple:±0.03dB DESCRIPTION
- Sampling Frequency: The PCM1602A is a CMOS, monolithicintegrated circuitthatfeaturessix24-bitaudiodigital-to-analog– 5 kHz to200 kHz (Channels1 and 2) converters(DACs) and supportcircuitryin a small– 5 kHz to100 kHz (Channels3,4,5,and 6) LQFP-48 package.The DACs use Texas Instruments'• Accepts 16-,18-,20-,and 24-BitAudio Data enhanced multilevel,delta-sigmaarchitecturethat
- Data Formats:Standard,I2S™ ,and employs fourth-ordernoise shaping and 8-level amplitude quantization to achieve excellentLeft-Justified signal-to-noiseperformanceand a hightoleranceto• System Clock:128 fS,192 fS,256 fS,384 fS,512 clockjitter.fS,or 768 fS The PCM1602A acceptsindustry-standardaudiodata• User-Programmable Functions: formatswith16- to24-bitaudiodata.Samplingrates– DigitalAttenuation:0 dB to–63 dB, up to 200 kHz (channels1 and 2) or 100 kHz0.5dB/Step (channels3,4,5,and 6) are supported.A fullsetof – SoftMute user-programmablefunctionsisaccessiblethrougha 4-wireserialcontrolportthatsupportsregisterwrite– Zero FlagsCan Be Used As General- and readfunctions.Purpose Logic Output – DigitalDe-Emphasis – DigitalFilterRolloff:Sharp or Slow
- Dual-SupplyOperation: – 5-V Analog – 3.3-VDigital
- 5-V TolerantDigitalLogic Inputs
- Package: LQFP-48 Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsofTexas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2FilterProisa trademarkofTexas Instruments. 3System Two, AudioPrecisionaretrademarksofAudioPrecision,Inc. 4I2S isa trademarkofNXP Semiconductors. 5Allothertrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2005–2010,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.
SLES146A –AUGUST 2005–REVISED OCTOBER 2010 www.ti.com This integratedcircuitcan be damaged by ESD. Texas Instrumentsrecommends thatallintegratedcircuitsbe handled with appropriateprecautions.Failuretoobserveproperhandlingand installationprocedurescan cause damage. ESD damage can rangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmay be more susceptibletodamage because verysmallparametricchanges couldcause thedevicenottomeet itspublishedspecifications. ABSOLUTE MAXIMUM RATINGS (1) Over operatingfree-airtemperaturerange(unlessotherwisenoted). VDD –0.3V to4 V Power supplyvoltage VCC –0.3V to6.5V VCC ,VDD Supplyvoltagedifference VCC – VDD < 3 V Ground voltagedifferences ±0.1V Digitalinputvoltage –0.3V to6.5V Inputcurrent(exceptpower supplypins) ±10 mA Operatingtemperatureunderbias –40°C to125°C Storagetemperature –55°C to150°C Junctiontemperature 150°C Package temperature(reflow,peak) 260°C (1) Stressesbeyond thoselistedunderAbsoluteMaximum Ratingsmay cause permanentdamage tothedevice.These arestressratings only,and functionaloperationofthedeviceattheseorany otherconditionsbeyond thoseindicatedunderRecommended Operating Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmay affectdevicereliability. RECOMMENDED OPERATING CONDITIONS Over operatingfree-airtemperaturerange. MIN NOM MAX UNIT Digitalsupplyvoltage,VDD 3 3.3 3.6 V Analogsupplyvoltage,VCC 4.5 5 5.5 V Digitalinputlogicfamily TTL System clock 8.192 36.864 MHz Digitalinputclockfrequency Samplingclock,VOUT 1,VOUT 2 32 192 kHz Samplingclock,VOUT 3,VOUT 4,VOUT 5,VOUT 6 32 96 Analogoutputloadresistance 5 kΩ Analogoutputloadcapacitance 50 pF Digitaloutputloadcapacitance 20 pF Operatingfree-airtemperature,TA –25 85 °C
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ELECTRICAL CHARACTERISTICS
AllspecificationsatTA = 25°C, VCC = 5 V,VDD = 3.3V,systemclock= 384 fS (fS = 44.1kHz),and 24-bitdata,unless otherwisenoted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RESOLUTION 24 Bits DATA FORMAT Audiodatainterfaceformats Standard,I2S,left-justified Audiodatabitlength 16-,18-,20-,24-bit,selectable Audiodataformat MSB-first,binary2s complement VOUT 1,VOUT 2 5 200 fS Samplingfrequency kHz VOUT 3,VOUT 4,VOUT 5,VOUT 6 5 100 128 fS,192 fS,256 fS,System clockfrequency 384 fS,512 fS,768 fS DIGITAL INPUT/OUTPUT Logicfamily TTL-compatible VIH 2 Inputlogiclevel Vdc VIL 0.8 IIH (1) VIN = VDD 10 IIL (1) VIN = 0 V –10 Inputlogiccurrent mA IIH (2) VIN = VDD 65 100 IIL (2) VIN = 0 V –10 VOH IOH = –4 mA 2.4 Outputlogiclevel Vdc VOL IOL = 4 mA 1 DYNAMIC PERFORMANCE (3)(4) VOUT = 0 dB,fS = 44.1kHz 0.002% 0.007% VOUT = 0 dB,fS = 96 kHz 0.004% VOUT = 0 dB,fS = 192 kHz 0.005% THD+N Totalharmonicdistortion+ noise VOUT = –60 dB,fS = 44.1kHz 0.7% VOUT = –60 dB,fS = 96 kHz 0.9% VOUT = –60 dB,fS = 192 kHz 1% EIAJ,A-weighted,fS = 44.1kHz 99 105 Dynamic range A-weighted,fS = 96 kHz 103 dB A-weighted,fS = 192 kHz 102 EIAJ,A-weighted,fS = 44.1kHz 99 105 SNR Signal-to-noiseratio A-weighted,fS = 96 kHz 103 dB A-weighted,fS = 192 kHz 102 fS = 44.1kHz 96 103 Channelseparation fS = 96 kHz 101 dB fS = 192 kHz 100 Levellinearityerror VOUT = –90 dB ±0.5 dB DC ACCURACY Gain error ±1 ±6 % ofFSR Gain mismatch,channel-to-channel ±1 ±3 % ofFSR Bipolarzeroerror VOUT = 0.5VCC atbipolarzero ±30 ±60 mV (1) Pins38,40,41,45–47 (SCKI,BCK, LRCK, DATA1, DATA2, DATA3) (2) Pins34–37 (MDI,MC, ML, RST) (3) Analogperformancespecificationsaretestedusinga System Two ™ Cascade audiomeasurement systemby AudioPrecision™ inthe averagingmode. The loadconnectedtotheanalogoutputis5 kΩ orlarger,viacapacitiveloading. (4) Conditionsin192-kHzoperationare:systemclock= 128 fS,DAC3 throughDAC6 disabledinregister8,and oversamplingrate= 64 fS inregister12. Copyright© 2005–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):PCM1602A
SLES146A –AUGUST 2005–REVISED OCTOBER 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) AllspecificationsatTA = 25°C, VCC = 5 V,VDD = 3.3V,systemclock= 384 fS (fS = 44.1kHz),and 24-bitdata,unless otherwisenoted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG OUTPUT Outputvoltage Fullscale(–0 dB) 0.62VCC VPP Centervoltage 0.5VCC Vdc Load impedance AC load 5 kΩ DIGITAL FILTER PERFORMANCE Group delaytime 20/fS De-emphasiserror ±0.1 dB FilterCharacteristics1,Sharp Rolloff Pass band ±0.03dB 0.454fS Pass band –3 dB 0.487fS Stopband 0.546fS Pass-bandripple ±0.03 dB Stop-bandattenuation Stopband = 0.546fS –50 dB Stop-bandattenuation Stopband = 0.567fS –55 dB FilterCharacteristics2,Slow Rolloff Pass band ±0.5dB 0.198fS Pass band –3 dB 0.39fS Stopband 0.884fS Pass-bandripple ±0.5 dB Stop-bandattenuation Stopband = 0.884fS –40 dB ANALOG FILTER PERFORMANCE f= 20 kHz –0.03 Frequencyresponse dB f= 44 kHz –0.2 POWER-SUPPLY REQUIREMENTS (5) VDD 3 3.3 3.6 Voltagerange Vdc VCC 4.5 5 5.5 fS = 44.1kHz 11 15 IDD (6) fS = 96 kHz 24 fS = 192 kHz 19 Supplycurrent mA fS = 44.1kHz 27 38 ICC fS = 96 kHz 28 fS = 192 kHz 28 fS = 44.1kHz 171 240 Power dissipation fS = 96 kHz 219 mW fS = 192 kHz 203 TEMPERATURE RANGE TA Operationtemperature –25 85 °C qJA Thermalresistance 100 °C/W (5) Conditionsin192-kHzoperationare:systemclock= 128 fS,DAC3 throughDAC6 disabledinregister8,and oversamplingrate= 64 fS inregister12. (6) SCKO isdisabled.
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DAT A1 (1,2) TEST DAT A2 (3,4) DAT A3 (5,6) RST ML MC MDI MDO SCKI AGND1−6 SCKO VCC 1−5 VDD DGND ZEROA ZERO2/GPO2 ZERO3/GPO3 ZERO4/GPO4 ZERO5/GPO5 ZERO6/GPO6 4× / 8× Oversampling Digital Filter With Function Controller VOUT 6 VOUT 5 PCM1602A www.ti.com SLES146A –AUGUST 2005–REVISED OCTOBER 2010 FUNCTIONAL BLOCK DIAGRAM Copyright© 2005–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):PCM1602A
37 VCC 3
(TOP VIEW) ZERO1/GPO1 ZERO2/GPO2 ZERO3/GPO3 ZERO4/GPO4 ZERO5/GPO5 ZERO6/GPO6 NC NC VOUT 6 VOUT 5 VOUT 4 VOUT 3 ML MC MDI MDO NC NC NC NC VCC 1 AGND1 VCC 2 AGND2 P0028-04 PCM1602A PCM1602A SLES146A –AUGUST 2005–REVISED OCTOBER 2010 www.ti.com TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION NAME NO. AGND1 27 – Analogground AGND2 25 – Analogground AGND3 23 – Analogground AGND4 21 – Analogground AGND5 17 – Analogground AGND6 19 – Analogground BCK 40 I Shiftclockinputforserialaudiodata.Clockmust be one of32 fS,48 fS,or64 fS.(1) DATA1 45 I SerialaudiodatainputforVOUT 1 and VOUT 2 (1) DATA2 46 I SerialaudiodatainputforVOUT 3 and VOUT 4 (1) DATA3 47 I SerialaudiodatainputforVOUT 5 and VOUT 6 (1) DGND 44 – Digitalground LRCK 41 I Leftand rightclockinput.Thisclockisequaltothesamplingrate,fS.(1) MC 35 I Shiftclockforserialcontrolport(2) MDI 34 I Serialdatainputforserialcontrolport(2) MDO 33 O Serialdataoutputforserialcontrolport(3) ML 36 I Latchenableforserialcontrolport(2) (1) Schmitt-triggerinput,5-V tolerant (2) Schmitt-triggerinputwithinternalpulldown,5-V tolerant (3) 3-stateoutput
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www.ti.com SLES146A –AUGUST 2005–REVISED OCTOBER 2010 TERMINAL FUNCTIONS (continued) TERMINAL I/O DESCRIPTION NAME NO. 7,8,16,20,29,NC – No connection30,31,32 RST 37 I System reset,active-low(2) System clockinput.Inputfrequencyisone of128 fS,192 fS,256 fS,384 fS,512 fS,or768 fS.SCKI 38 I (1) Bufferedclockoutput.Outputfrequencyisone of128 fS,192 fS,256 fS,384 fS,512 fS,orSCKO 39 O 768 fS,orone-halfof128 fS,192 fS,256 fS,384 fS,512 fS,or768 fS. TEST 42 – Testpin.Thispinshouldbe connectedtoDGND. (2) VCC 1 28 – Analogpower supply,5-V VCC 2 26 – Analogpower supply,5-V VCC 3 24 – Analogpower supply,5-V VCC 4 22 – Analogpower supply,5-V VCC 5 18 – Analogpower supply,5-V VCOM 15 O Common voltageoutput.Thispinshouldbe bypassedwitha 10-mF capacitortoAGND. VDD 43 – Digitalpower supply,3.3-V VOUT 1 14 O VoltageoutputofaudiosignalcorrespondingtoLch on DATA1. Up to192 kHz. VOUT 2 13 O VoltageoutputofaudiosignalcorrespondingtoRch on DATA1. Up to192 kHz. VOUT 3 12 O VoltageoutputofaudiosignalcorrespondingtoLch on DATA2. Up to96 kHz. VOUT 4 11 O VoltageoutputofaudiosignalcorrespondingtoRch on DATA2. Up to96 kHz. VOUT 5 10 O VoltageoutputofaudiosignalcorrespondingtoLch on DATA3. Up to96 kHz. VOUT 6 9 O VoltageoutputofaudiosignalcorrespondingtoRch on DATA3. Up to96 kHz. ZERO1/GPO1 1 O Zero-dataflagforVOUT 1.Can alsobe used as GPO pin. ZERO2/GPO2 2 O Zero-dataflagforVOUT 2.Can alsobe used as GPO pin. ZERO3/GPO3 3 O Zero-dataflagforVOUT 3.Can alsobe used as GPO pin. ZERO4/GPO4 4 O Zero-dataflagforVOUT 4.Can alsobe used as GPO pin. ZERO5/GPO5 5 O Zero-dataflagforVOUT 5.Can alsobe used as GPO pin. ZERO6/GPO6 6 O Zero-dataflagforVOUT 6.Can alsobe used as GPO pin. ZEROA 48 O Zero-dataflag.LogicalAND ofZERO1 throughZERO6 Copyright© 2005–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):PCM1602A
Frequency [×/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZrfS] −140 −120 −100 −80 −60 −40 −20 0 1 2 3 4 Amplitude − dB G001 Frequency [×/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZrfS] −0.05 −0.04 −0.03 −0.02 −0.01 0.00 0.01 0.02 0.03 0.04 0.05 Amplitude − dB G002 Frequency [×/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZrfS] −140 −120 −100 −80 −60 −40 −20 0 1 2 3 4 Amplitude − dB G003 Frequency [×/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZrfS] Amplitude − dB G004 PCM1602A SLES146A –AUGUST 2005–REVISED OCTOBER 2010 www.ti.com TYPICAL PERFORMANCE CURVES AllspecificationsatTA = 25°C, VCC = 5 V,VDD = 3.3V,fS = 44.1kHz,systemclock= 384 fS,and 24-bitinputdata,unless otherwisenoted DigitalFilter(De-Emphasis Off) FREQUENCY RESPONSE PASS-BAND FREQUENCY RESPONSE (SHARP ROLLOFF) (SHARP ROLLOFF) Figure1. Figure2. FREQUENCY RESPONSE TRANSITION CHARACTERISTICS (SLOW ROLLOFF) (SLOW ROLLOFF) Figure3. Figure4.
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f − Frequency − kHz −10 0 2 4 6 8 10 12 14 Level − dB G005 f − Frequency − kHz −0.5 −0.4 −0.3 −0.2 −0.1 0.0 0.1 0.2 0.3 0.4 0.5 0 2 4 6 8 10 12 14 Error − dB G006 f − Frequency − kHz −10 0 2 4 6 8 10 12 14 16 18 20 Level − dB G007 f − Frequency − kHz −0.5 −0.4 −0.3 −0.2 −0.1 0.0 0.1 0.2 0.3 0.4 0.5 0 2 4 6 8 10 12 14 16 18 20 Error − dB G008 PCM1602A www.ti.com SLES146A –AUGUST 2005–REVISED OCTOBER 2010 TYPICAL PERFORMANCE CURVES (continued) AllspecificationsatTA = 25°C, VCC = 5 V,VDD = 3.3V,fS = 44.1kHz,systemclock= 384 fS,and 24-bitinputdata,unless otherwisenoted DigitalFilter(De-Emphasis Curves) DE-EMPHASIS DE-EMPHASIS ERROR (fS = 32 kHz) (fS = 32 kHz) Figure5. Figure6. DE-EMPHASIS DE-EMPHASIS ERROR (fS = 44.1kHz) (fS = 44.1kHz) Figure7. Figure8. Copyright© 2005–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):PCM1602A
f − Frequency − kHz −10 0 2 4 6 8 10 12 14 16 18 20 22 Level − dB G009 f − Frequency − kHz −0.5 −0.4 −0.3 −0.2 −0.1 0.0 0.1 0.2 0.3 0.4 0.5 0 2 4 6 8 10 12 14 16 18 20 22 Error − dB G010 VCC − Supply Voltage − V 100 102 104 106 108 110 Dynamic Range − dB G012 192 kHz, 128 fS 96 kHz, 384 fS 44.1 kHz, 384 fS VCC − Supply Voltage − V THD+N − Total Harmonic Distortion + Noise − % 0.01 0.001 0.0001 G011 0.1 −60 dB/192 kHz, 128 fS 0 dB/192 kHz, 128 fS 0 dB/96 kHz, 384 fS −60 dB/44.1 kHz, 384 fS 0 dB/44.1 kHz, 384 fS −60 dB/96 kHz, 384 fS PCM1602A SLES146A –AUGUST 2005–REVISED OCTOBER 2010 www.ti.com TYPICAL PERFORMANCE CURVES (continued)(continued) AllspecificationsatTA = 25°C, VCC = 5 V,VDD = 3.3V,fS = 44.1kHz,systemclock= 384 fS,and 24-bitinputdata,unless otherwisenoted DE-EMPHASIS DE-EMPHASIS ERROR (fS = 48 kHz) (fS = 48 kHz) Figure9. Figure10. TYPICAL PERFORMANCE CURVES (continued) ANALOG DYNAMIC PERFORMANCE AllspecificationsatTA = 25°C, VCC = 5 V,VDD = 3.3V,and 24-bitinputdata,unlessotherwisenoted.Conditionsin192-kHz operationaresystemclock= 128 fS,DAC3 throughDAC6 disabledinregister8,and oversamplingrate= 64 fS (setby OVER bitinregister12). Supply-VoltageCharacteristics TOTAL HARMONIC DISTORTION + NOISE DYNAMIC RANGE vs vs VCC (VDD = 3.3V) VCC (VDD = 3.3V) Figure11. Figure12.
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VCC − Supply Voltage − V 100 102 104 106 108 110 SNR − Signal-to-Noise Ratio − dB G013 192 kHz, 128 fS 96 kHz, 384 fS 44.1 kHz, 384 fS VCC − Supply Voltage − V 100 102 104 106 108 110 Channel Separation − dB G014 192 kHz, 128 fS 96 kHz, 384 fS 44.1 kHz, 384 fS PCM1602A www.ti.com SLES146A –AUGUST 2005–REVISED OCTOBER 2010 TYPICAL PERFORMANCE CURVES (continued)(continued) AllspecificationsatTA = 25°C, VCC = 5 V,VDD = 3.3V,and 24-bitinputdata,unlessotherwisenoted.Conditionsin192-kHz operationaresystemclock= 128 fS,DAC3 throughDAC6 disabledinregister8,and oversamplingrate= 64 fS (setby OVER bitinregister12). SIGNAL-TO-NOISE RATIO CHANNEL SEPARATION vs vs VCC (VDD = 3.3V) VCC (VDD = 3.3V) Figure13. Figure14. Copyright© 2005–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLink(s):PCM1602A
TA − Free-Air Temperature − °C 100 102 104 106 108 110 −50 −25 0 25 50 75 100 Dynamic Range − dB G016 192 kHz, 128 fS 96 kHz, 384 fS 44.1 kHz, 384 fS −50 −25 0 25 50 75 100 TA − Free-Air Temperature − °C THD+N − Total Harmonic Distortion + Noise − % 0.01 0.001 0.0001 G015 0.1 0 dB/192 kHz, 128 fS0 dB/96 kHz, 384 fS −60 dB/96 kHz, 384 fS −60 dB/44.1 kHz, 384 fS 0 dB/44.1 kHz, 384 fS −60 dB/192 kHz, 128 fS TA − Free-Air Temperature − °C 100 102 104 106 108 110 −50 −25 0 25 50 75 100 SNR − Signal-to-Noise Ratio − dB G017 192 kHz, 128 fS 96 kHz, 384 fS 44.1 kHz, 384 fS TA − Free-Air Temperature − °C 100 102 104 106 108 110 −50 −25 0 25 50 75 100 Channel Separation − dB G018 192 kHz, 128 fS 96 kHz, 384 fS 44.1 kHz, 384 fS PCM1602A SLES146A –AUGUST 2005–REVISED OCTOBER 2010 www.ti.com TYPICAL PERFORMANCE CURVES (continued) ANALOG DYNAMIC PERFORMANCE (continued) AllspecificationsatTA = 25°C, VCC = 5 V,VDD = 3.3V,and 24-bitinputdata,unlessotherwisenoted.Conditionsin192-kHz operationaresystemclock= 128 fS,DAC3 throughDAC6 disabledinregister8,and oversamplingrate= 64 fS (setby OVER bitinregister12). Temperature Characteristics TOTAL HARMONIC DISTORTION + NOISE DYNAMIC RANGE vs vs TEMPERATURE (TA ) TEMPERATURE (TA ) Figure15. Figure16. SIGNAL-TO-NOISE RATIO CHANNEL SEPARATION vs vs TEMPERATURE (TA ) TEMPERATURE (TA ) Figure17. Figure18.
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tw(SCKH) System Clock tw(SCKL) 2 V 0.8 V H L System Clock Pulse Cycle Time(1) T0005A08 PCM1602A www.ti.com SLES146A –AUGUST 2005–REVISED OCTOBER 2010 SYSTEM CLOCK AND RESET FUNCTIONS SYSTEM CLOCK INPUT The PCM1602A requiresa system clockforoperatingthedigitalinterpolationfiltersand multileveldelta-sigma modulators.The system clockisappliedattheSCKI input(pin38).Table1 shows examples ofsystem clock frequenciesforcommon audiosamplingrates. Figure19 shows thetimingrequirementsforthesystem clockinput.For optimalperformance,itisimportantto use a clocksourcewithlow phase jitterand noise.The PLL170x multiclockgeneratorfromTexas Instrumentsis an excellentchoiceforprovidingthePCM1602A systemclock. The 192-kHz samplingfrequencyoperationisavailableon DATA1 forVOUT 1 and VOUT 2.Itisrecommended that VOUT 3,VOUT 4,VOUT 5,and VOUT 6 be forcedtothebipolarzerolevelusingtheDAC3, DAC4, DAC5, and DAC6 bitsofregister8 when operatingat192 kHz. Table1.System Clock Rates forCommon Audio Sampling Frequencies SAMPLING FREQUENCY SYSTEM CLOCK FREQUENCY (fSCLK )(MHz) (kHz) 128 fS 192 fS 256 fS 384 fS 512 fS 768 fS 8 (1) (1) 2.048 3.072 4.096 6.144 16 (1) (1) 4.096 6.144 8.192 12.288 32 (1) (1) 8.192 12.288 16.384 24.576 48 (1) (1) 12.288 18.432 24.576 36.864 (1) Thissystemclockisnotsupportedforthegivensamplingfrequency. SYMBOL PARAMETER MIN MAX UNIT tw(SCKH) System clockpulseduration,HIGH 7 ns tw(SCKL) System clockpulseduration,LOW 7 ns (1) 1/128fS,1/256fS,1/384fS,1/512fS,and 1/768fS. Figure19. System Clock Timing SYSTEM CLOCK OUTPUT A bufferedversionof the system clockinputisavailableat the SCKO output(pin39).SCKO can operateat eitherfull(fSCKI) or half(fSCKI/2)rate.The SCKO outputfrequencycan be programmed usingthe CLKD bitof register9.The SCKO outputpincan alsobe enabledordisabledusingtheCLKE bitofregister9.IftheSCKO outputisnotrequired,itisrecommended todisableitusingtheCLKE bit.The defaultisSCKO enabled. Copyright© 2005–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLink(s):PCM1602A
2.4 V 2 V 1.6 V Internal Reset System Clock T0014-08 0 V Don't Care 1024 System Clocks Reset Removal
1024 System Clocks
SLES146A –AUGUST 2005–REVISED OCTOBER 2010 www.ti.com POWER-ON AND EXTERNAL RESET FUNCTIONS The PCM1602A includesa power-on-resetfunction,as shown inFigure20.With thesystem clockactive,and VDD > 2 V (typical,1.6V to2.4V),thepower-on-resetfunctionisenabled.The initializationsequence requires 1024 system clocksfrom the timeVDD > 2 V. Afterthe initializationperiod,the PCM1602A issetto itsreset defaultstate,as describedintheMode ControlRegisterssectionofthisdatasheet. The PCM1602A alsoincludesan externalresetcapabilityusingtheRST input(pin37).Thisallowsan external controlleror master resetcircuitto forcethe PCM1602A to initializeto itsresetdefaultstate.For normal operation,RST shouldbe settoa logic-1. The externalresetoperationand timingisshown inFigure21.The RST pinissettologic-0fora minimum of 20 ns.Aftertheinitializationsequence iscompleted,thePCM1602A issettoitsresetdefaultstate,as described intheMode ControlRegisterssectionofthisdatasheet. Duringtheresetperiod(1024system clocks),theanalogoutputsareforcedtothebipolarzerolevel(orVCC /2). Aftertheresetperiod,theinternalregistersare initializedinthenext1/fS periodand,ifSCKI, BCK, and LRCK areprovidedcontinuously,thePCM1602A providesproperanalogoutputwiththegroupdelaytimegiveninthe ElectricalCharacteristicssectionofthisdatasheet. The externalresetisespeciallyusefulinapplicationswhere thereisa delaybetween PCM1602A power-upand system-clockactivation.In thiscase,the RST pinshouldbe heldat a logic-0leveluntilthe system clockhas been activated. Figure20. Power-On-Reset Timing Figure21. ExternalReset Timing
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www.ti.com SLES146A –AUGUST 2005–REVISED OCTOBER 2010 AUDIO SERIAL INTERFACE The audioserialinterfaceforthePCM1602A consistsofa 5-wiresynchronousserialport.ItincludesLRCK (pin 41),BCK (pin40),DATA1 (pin45),DATA2 (pin46),and DATA3 (pin47).BCK istheserialaudiobitclock,and is used toclocktheserialdatapresenton DATA1, DATA2, and DATA3 intotheaudiointerfaceserialshiftregister. SerialdataisclockedintothePCM1602A on therisingedge ofBCK. LRCK istheserialaudioleft/rightclock.Itis used tolatchserialdataintotheserialaudiointerfaceinternalregisters. Both LRCK and BCK must be synchronoustothesystem clock.Ideally,itisrecommended thatLRCK and BCK be derivedfrom the system clockinput,SCKI. LRCK isoperatedat the samplingfrequency(fS).BCK can be operatedat32,48,or64 timesthesamplingfrequency(I2S formatdoes notsupportBCK = 32 fS). InternaloperationofthePCM1602A issynchronizedwithLRCK. Accordingly,internaloperationofthedeviceis suspended when thesamplingrateclock(LRCK) ischanged,orwhen SCKI and/orBCK isinterruptedatleastfor a 3-bitclockcycle.IfSCKI, BCK, and LRCK are providedcontinuouslyafterthissuspended state,theinternal operationisresynchronizedautomaticallywithina periodoflessthan3/fS.Duringthisresynchronizationperiod and fora 3/fS timethereafter,theanalogoutputsareforcedtothebipolarzerolevel,VCC /2.Externalresettingis notrequired. AUDIO DATA FORMATS AND TIMING The PCM1602A supportsindustry-standardaudiodata formats,includingstandard,I2S, and left-justified(see Figure22).Data formatsare selectedusingtheformatbits,FMT[2:0],inregister9.The defaultdataformatis 24-bitstandard.Allformatsrequirebinary2s complement,MSB-firstaudiodata.See Figure23 fora detailed timingdiagramoftheserialaudiointerface. DATA1, DATA2, and DATA3 each carrytwo audiochannels,designatedas the leftand rightchannels.The left-channeldataalwaysprecedestheright-channeldataintheserialdatastreamforalldataformats.Table2 shows themapping ofthedigitalinputdatatotheanalogoutputpins. Copyright© 2005–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLink(s):PCM1602A
(2) I2S Data Format; L-Channel = LOW, R-Channel = HIGH MSB LSB 1/fS (= 32 fS, 48 fS, or 64 fS) 18-Bit Right-Justified 1/fS (1) Standard Data Format; L-Channel = HIGH, R-Channel = LOW (3) Left-Justified Data Format; L-Channel = HIGH, R-Channel = LOW MSB LSB 20-Bit Right-Justified MSB LSB 24-Bit Right-Justified 1/fS (= 48 fS, or 64 fS) LSB 16-Bit Right-Justified, BCK = 48 fS or 64 fS 16-Bit Right-Justified, BCK = 32 fS LSB L-Channel R-Channel BCK DATA 14 15 16 14 15 16 14 15 16 14 15 16 16 17 18 DATA DATA DATA DATA 1 2 3 16 17 18 18 19 20 1 2 3 18 19 20 22 23 24 1 2 3 MSB LSB MSB LSB LSB MSB LSB 1 2 3 14 15 16 14 15 16 1 2 3 16 17 18 1 2 3 18 19 20 22 23 24 MSB LSB 1 2 3 22 23 24 L-Channel R-ChannelLRCK BCK DATA 1 2 3 1 2 MSB N–2 NN–1 LSB L-Channel R-ChannelLRCK BCK DATA T0009-05 MSB 1 2 3 MSB 1 2 3 MSB 1 2 3 1 2 3 MSB N–2 NN–1 LSB 1 2 3 MSB N–2 NN–1 LSB 1 2 3 MSB N–2 NN–1 LSB (= 48 fS, or 64 fS) 1 2 PCM1602A SLES146A –AUGUST 2005–REVISED OCTOBER 2010 www.ti.com Figure22. Audio Data InputFormats
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DAT A1, DATA2, DATA3 t(BCH) 1.4 V BCK LRCK t(BCL) t(LB) t(BCY) t(BL) t(DS) t(DH) T0010-06 1.4 V 1.4 V PCM1602A www.ti.com SLES146A –AUGUST 2005–REVISED OCTOBER 2010 SYMBOL PARAMETER MIN MAX UNITS t(BCY) BCK pulsecycletime 1/(64fS ) t(BCH) BCK high-leveltime 35 ns t(BCL) BCK low-leveltime 35 ns t(BL) BCK risingedge toLRCK edge 10 ns t(LB) LRCK fallingedge toBCK risingedge 10 ns t(DS) DATA setuptime 10 ns t(DH) DATA holdtime 10 ns (1) fS isthesamplingfrequency(e.g.,44.1kHz,48 kHz,96 kHz,etc.) Figure23. Audio InterfaceTiming Table2.Audio InputData toAnalog Output Mapping DATA INPUT CHANNEL ANALOG OUTPUT DATA1 Left VOUT 1 (1) DATA1 Right VOUT 2 (1) DATA2 Left VOUT 3 (2) DATA2 Right VOUT 4 (2) DATA3 Left VOUT 5 (2) DATA3 Right VOUT 6 (2) (1) Up to192 kHz (2) Up to96 kHz Copyright© 2005–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLink(s):PCM1602A
IDX5 IDX4R/W IDX3 IDX2 IDX1 IDX0 D7 D6 D5 D4 D3 D2 D1 D0 Register Index (or Address) Register Data Read/W rite Operation 0 = Write Operation 1 = Read Operation (Register Index is Ignored) IDX0 D7 D6 D4 D5 D3 D2 D1 D0R/W ML MC MDI X R/W IDX6XIDX1IDX2IDX3IDX4IDX5IDX6X T0048-02 PCM1602A SLES146A –AUGUST 2005–REVISED OCTOBER 2010 www.ti.com SERIAL CONTROL INTERFACE The serialcontrolinterfaceisa 4-wiresynchronousserialportthatoperatesasynchronouslytotheserialaudio interface.The serialcontrolinterfaceisused to program and read the on-chipmode registers.The control interfaceincludesMDO (pin33),MDI (pin34),MC (pin35),and ML (pin36).MDO istheserialdataoutput,used toreadback thevaluesofthemode registers;MDI istheserialdatainput,used toprogram themode registers; MC istheserialbitclock,used toshiftdatainand outofthecontrolport;and ML isthecontrolportlatchclock. REGISTER WRITE OPERATION Allwriteoperationsforthe serialcontrolportuse 16-bitdata words.Figure24 shows the controldata word format.The most significantbitisthe read/writeR/W) bit.When setto 0, thisbitindicatesa writeoperation. Seven bits,labeledIDX[6:0],settheregisterindex(oraddress)forthewriteoperation.The leastsignificanteight bits,D[7:0],containthedatatobe writtentotheregisterspecifiedby IDX[6:0]. Figure25 shows thefunctionaltimingdiagramforwritingtotheserialcontrolport.ML isheldata logic-1state untila registeristo be written.To startthe registerwritecycle,ML issetto logic-0.Sixteenclocksare then providedon MC, correspondingtothe16 bitsofthecontroldataword on MDI. Afterthesixteenthclockcyclehas completed,ML issettologic-1tolatchthedataintotheindexedmode controlregister. Figure24. ControlData Word Format forMDI Figure25. WriteOperationTiming SINGLE REGISTER READ OPERATION Read operationsuse the16-bitcontrolword formatshown inFigure24.For read operations,theR/W bitisset to 1. Read operationsignorethe indexbits,IDX[6:0],of the controldata word.Instead,the REG[6:0]bitsin controlregister11 are used to setthe indexof the registerthatisto be read duringthe read operation.Bits IDX[6:0]shouldbe setto00h forreadoperations. The detailsofthereadoperationareshown inFigure26.First,controlregister11 must be writtenwiththeindex of the registerto be read back. Additionally,the INC bitmust be set to logic-0in order to disablethe auto-incrementreadfunction.The readcycleistheninitiatedby settingML tologic-0and settingtheR/W bitof thecontroldataword tologic-1,indicatinga read operation.MDO remainsina high-impedancestateuntilthe lasteightbitsof the 16-bitread cycle,which correspondto the eightdata bitsof the registerindexedby the REG[6:0]bitsofcontrolregister11.The readcycleiscompletedwhen ML issetto1,immediatelyaftertheMC clockcyclefortheleast-significantbitoftheindexedcontrolregisterhas completed.
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INC = 1 (Auto-Increment Read) INDEX “N” ML 1 0 0 0 0 0 0 0 X X X X X X X X D0D1D2D3D4D5D6D7High Impedance MC MDI MDO INDEX “Y” ML X X X X X X X X X X X X X X X X D0D1D2D3D4D5D6D7 High Impedance MC MDI MDO INDEX “N + 1” D0D1D2D3D4D5D6D7 INC = 0 (Single-Register Read) INDEX “N” ML 1 0 0 0 0 0 0 0 X X X X X X X X D0D1D2D3D4D5D6D7High Impedance MC MDI MDO T0075-01 PCM1602A www.ti.com SLES146A –AUGUST 2005–REVISED OCTOBER 2010 NOTES: X = Don ’tcare w Y = Lastregistertobe read w Insingle-registerread(INC= 0),theindexwhichindicatestheregistertobe readinreadoperationcan be setby REG[6:0]inregister11.Forexample,settingREG[6:0]= 000 1001b means readingfromregister9. Inauto-incrementread(INC= 1),theindexREG[6:0]indicatesthefirstregistertobe read.Forexample,setting REG[6:0]= 000 1001b means readingregistersfrom9 toY.Y isdeterminedby thelow-to-hightransitionofML in serialmode control. Figure26. Read OperationTiming Copyright© 2005–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLink(s):PCM1602A
t(MCH)
1.4 VML
t(MLS) LSB 1.4 V t(MCL) t(MHH) t(MLH) t(MCY) t(MDH) t(MDS) MC MDI LSB MDI T0013-05 LSB 50% of VDDMDO t(MOS) 1.4 V PCM1602A SLES146A –AUGUST 2005–REVISED OCTOBER 2010 www.ti.com AUTO-INCREMENT READ OPERATION The auto-incrementread functionallowsformultipleregisterstobe read sequentially.The auto-incrementread functionisenabledby settingtheINC bitofcontrolregister11 to1.The sequence alwaysstartswiththeregister indexedby theREG[6:0]bitsincontrolregister11,and ends by theML settingto1 afterMC clockcycleforthe least-significantbitoflastregister. Figure26 shows thetimingoftheauto-incrementreadoperation.The operationbeginsby writingcontrolregister 11, settingINC to 1, and settingREG[6:0] to the firstregisterto be read in the sequence.The actualread operationstartson thenextHIGH-to-LOW transitionoftheML pin. The readcyclestartsby settingtheR/W bitofthecontrolword to1,and settingalloftheIDX[6:0]bitsto0.All subsequentbitsinputon MDI areignoredwhileML issetto0.Forthefirsteightclocksofthereadcycle,MDO is settothehigh-impedancestate.Thisisfollowedby a sequence of8-bitwords,each correspondingtothedata containedincontrolregistersN throughY, where N isdefinedby theREG[6:0]bitsincontrolregister11,and where Y isthelastregistertobe read.The read cycleiscompletedwhen ML issetto1,immediatelyafterthe MC clockcyclefortheleast-significantbitofthelastregisterhas completed.IfML isheldlow and theMC clock continuesbeyond the lastphysicalregister(register12),the read operationreturnsto controlregister1 and subsequentcontrolregisters,continuinguntilML issetto1. CONTROL INTERFACE TIMING REQUIREMENTS Figure27 shows a detailedtimingdiagramfortheserialcontrolinterface.Pay specialattentiontothesetupand holdtimes,as wellas t(MLS) and t(MLH), which defineminimum delaysbetween the edges of the ML and MC clocks.These timingparametersarecriticalforpropercontrol-portoperation. SYMBOL PARAMETER MIN MAX UNITS t(MCY) MC pulsecycletime 100 ns t(MCL) MC low-leveltime 50 ns t(MCH) MC high-leveltime 50 ns t(MHH) ML high-leveltime 300 ns t(MLS) ML fallingedge toMC risingedge 20 ns t(MLH) ML holdtime 20 ns t(MDH) MDI holdtime 15 ns t(MDS) MDL setuptime 20 ns t(MOS) MC fallingedge toMDO stable 30 ns (1) MC risingedge forLSB toML risingedge. Figure27. ControlInterfaceTiming
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www.ti.com SLES146A –AUGUST 2005–REVISED OCTOBER 2010 MODE CONTROL REGISTERS User-Programmable Mode Controls The PCM1602A includesa number ofuser-programmablefunctionsthatareaccessedviacontrolregisters.The registersare programmed using the serialcontrolinterfacethatis previouslydiscussedin thisdata sheet. Table3 liststheavailablemode controlfunctions,alongwiththeirresetdefaultconditionsand associatedregister index. Table3.User-Programmable Mode Controls CONTROLFUNCTION RESET DEFAULT BIT(S)LABELREGISTER AT1[7:0],AT2[7:0], Digitalattenuationcontrol,0 dB to–63 dB in0.5-dBsteps 0 dB,no attenuation 1 through6 AT3[7:0],AT4[7:0], AT51[7:0],AT6[7:0] Softmute control Mute disabled 7 MUT[6:1] DAC1 –DAC6 operationcontrol DAC1 –DAC6 enabled 8 DAC[6:1] Audiodataformatcontrol 24-bitstandardformat 9 FMT[2:0] Digitalfilterrolloffcontrol Sharp rolloff 9 FLT SCKO frequencyselection Fullrate(=fSCKI) 9 CLKD SCKO outputenable SCKO enabled 9 CLKE De-emphasis,allchannelsDe-emphasisall-channelfunctioncontrol 10 DMCdisabled De-emphasisall-channelsample rateselection 44.1kHz 10 DMF[1:0] Outputphase select Normal phase 10 DREV Zero-flagpolarityselect High 10 ZREV Read-registerindexcontrol REG[6:0]= 01h 11 REG[6:0] Read auto-incrementcontrol Auto-incrementdisabled 11 INC General-purposeoutputenable Zero-flagenabled 12 GPOE General-purposeoutputbits(GPO1 –GPO6) Disabled 12 GPO[6:1] Oversamplingratecontrol 64× 12 OVER Copyright© 2005–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLink(s):PCM1602A
SLES146A –AUGUST 2005–REVISED OCTOBER 2010 www.ti.com Reserved Registers Register0 isreservedforfactoryuse.To ensure properoperation,the user shouldnot writeto or read from theseregisters. RegisterMap The mode controlregistermap isshown inTable4.Each registerincludesan R/W bitthatdetermineswhethera registerread R/W = 1) or writeR/W = 0) operationisperformed.Each registeralsoincludesan index(or address)indicatedby theIDX[6:0]bits. Table4.Mode ControlRegisterMap IDX (B14– B8) REGISTER B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 01h 1 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT17 AT16 AT15 AT14 AT13 AT12 AT11 AT10 02h 2 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT27 AT26 AT25 AT24 AT23 AT22 AT21 AT20 03h 3 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT37 AT36 AT35 AT34 AT33 AT32 AT31 AT30 04h 4 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT47 AT46 AT45 AT44 AT43 AT42 AT41 AT40 05h 5 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT57 AT56 AT55 AT54 AT53 AT52 AT51 AT50 06h 6 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT67 AT66 AT65 AT64 AT63 AT62 AT61 AT60 RSV (1 RSV (1 07h 7 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 MUT6 MUT5 MUT4 MUT3 MUT2 MUT1) ) RSV (1 RSV (1 08h 8 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 DAC6 DAC5 DAC4 DAC3 DAC2 DAC1) ) RSV (1 RSV (1 09h 9 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 FLT CLKD CLKE FMT2 FMT1 FMT0) ) RSV (1 0Ah 10 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 ZREV DREV DMF1 DMF0 DMC DMC DMC) 0Bh 11 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 INC REG6 REG5 REG4 REG3 REG2 REG1 REG0 0Ch 12 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 OVER GPOE GPO6 GPO5 GPO4 GPO3 GPO2 GPO1 (1) Reservedfortestoperation.Itshouldbe setto0 duringnormaloperation.
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www.ti.com SLES146A –AUGUST 2005–REVISED OCTOBER 2010 RegisterDefinitions B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 REGISTER 1 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT17 AT16 AT15 AT14 AT13 AT12 AT11 AT10 REGISTER 2 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT27 AT26 AT25 AT24 AT23 AT22 AT21 AT20 REGISTER 3 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT37 AT36 AT35 AT34 AT33 AT32 AT31 AT30 REGISTER 4 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT47 AT46 AT45 AT44 AT43 AT42 AT41 AT40 REGISTER 5 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT57 AT56 AT55 AT54 AT53 AT52 AT51 AT50 REGISTER 6 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT67 AT66 AT65 AT64 AT63 AT62 AT61 AT60 R/W – Read/WriteMode Select When R/W = 0,a writeoperationisperformed. When R/W = 1,a readoperationisperformed. Defaultvalue:0 ATx[7:0]– DigitalAttenuationLevelSetting where x = 1 through6,correspondingtotheDAC outputVOUT x. These bitsareread/write. Defaultvalue:1111 1111b Each DAC output,VOUT 1 throughVOUT 6,includesa digitalattenuatorfunction.The attenuationlevelcan be set from0 dB to–63 dB in0.5-dBsteps.Changes inattenuationlevelsaremade by incrementingordecrementing by one step(0.5dB) forevery8/fS timeintervaluntiltheprogrammed attenuatorsettingisreached.Alternatively, theattenuationlevelcan be settoinfiniteattenuation,ormute. The attenuationleveliscalculatedusingthefollowingformula: Attenuationlevel(dB)= 0.5(ATx[7:0]DEC – 255) where ATx[7:0]DEC = 0 through255. ForATx[7:0]DEC = 0 through128,theattenuatorissettoinfiniteattenuation. The followingtableshows attenuationlevelsforvarioussettings. ATx[7:0] DECIMAL VALUE ATTENUATOR LEVEL SETTING 1111 1111b 255 0 dB,no attenuation(default) 1111 1110b 254 –0.5dB 1111 1101b 253 –1 dB : : : 1000 0011b 131 –62 dB 1000 0010b 130 –62.5dB 1000 0001b 129 –63 dB 1000 0000b 128 Mute : : : 0000 0000b 0 Mute Copyright© 2005–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLink(s):PCM1602A
SLES146A –AUGUST 2005–REVISED OCTOBER 2010 www.ti.com B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 REGISTER 7 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV MUT6 MUT5 MUT4 MUT3 MUT2 MUT1 R/W – Read/WriteMode Select When R/W = 0,a writeoperationisperformed. When R/W = 1,a readoperationisperformed. Defaultvalue:0 MUTx – SoftMute Control Where x = 1 through6,correspondingtotheDAC outputVOUT x. These bitsareread/write. Defaultvalue:0 MUTx = 0 Mute disabled(default) MUTx = 1 Mute enabled The mute bits,MUT1 throughMUT6, areused toenableordisablethesoftmute functionforthecorresponding DAC outputs,VOUT 1 throughVOUT 6. The softmute functionisincorporatedintothe digitalattenuators.When mute isdisabled(MUTx = 0),the attenuatorand DAC operatenormally.When mute isenabled by setting MUTx = 1,thedigitalattenuatorforthecorrespondingoutputisdecreasedfromthecurrentsettingtotheinfinite attenuationsetting,one attenuatorstep(0.5dB) at a time.Thisprovidesa quiet,pop-freemutingof the DAC output.On returningfrom softmute,by settingMUTx = 0,theattenuatorisincreasedone stepata timetothe previouslyprogrammed attenuationlevel. B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 REGISTER 8 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV DAC6 DAC5 DAC4 DAC3 DAC2 DAC1 R/W – Read/WriteMode Select When R/W = 0,a writeoperationisperformed. When R/W = 1,a readoperationisperformed. Defaultvalue:0 DACx – DAC OperationControl Where x = 1 through6,correspondingtotheDAC outputVOUT x. These bitsareread/write. Defaultvalue:0 DACx = 0 DAC operationenabled(default) DACx = 1 DAC operationdisabled The DAC operationcontrolsare used to enable and disablethe DAC outputs,VOUT 1 throughVOUT 6. When DACx = 0,theoutputamplifierinputisconnectedtotheDAC output.When DACx = 1,theoutputamplifierinput isswitchedtothedc common-mode voltage(VCOM ),equaltoVCC /2.
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www.ti.com SLES146A –AUGUST 2005–REVISED OCTOBER 2010 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 REGISTER 9 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV RSV FLT CLKD CLKE FMT2 FMT1 FMT0 R/W – Read/WriteMode Select When R/W = 0,a writeoperationisperformed. When R/W = 1,a readoperationisperformed. Defaultvalue:0 FLT – DigitalFilterRolloffControl Thisbitisread/write. Defaultvalue:0 FLT = 0 Sharp rolloff(default) FLT = 1 Slow rolloff The FLT bitallowsuserstoselectthedigitalfilterrolloffthatisbestsuitedtotheirapplication.Two filterrolloff selectionsare available:sharp or slow.The filterresponses forthese selectionsare shown in the Typical PerformanceCurvessectionofthisdatasheet. CLKD – SCKO Frequency Selection Thisbitisread/write. Defaultvalue:0 CLKD = 0 Full-rate,fSCKO = fSCKI (default) CLKD = 1 Half-rate,fSCKO = fSCKI/2 The CLKD bitisused todeterminetheclockfrequencyatthesystemclockoutputpin,SCKO. CLKE – SCKO Output Enable Thisbitisread/write. Defaultvalue:0 CLKE = 0 SCKO enabled(default) CLKE = 1 SCKO disabled The CLKE bitisused toenableordisablethesystemclockoutputpin,SCKO. When SCKO isenabled,itoutputs eithera full-orhalf-rateclock,based on thesettingoftheCLKD bit.When SCKO isdisabled,itissettoa LOW level. FMT[2:0]– Audio InterfaceData Format These bitsareread/write. Defaultvalue:000b FMT[2:0] Audio Data Format Selection 000 24-bitstandardformat,right-justifieddata(default) 001 20-bitstandardformat,right-justifieddata 010 18-bitstandardformat,right-justifieddata 011 16-bitstandardformat,right-justifieddata
100 I2S format,16-to24-bit
101 Left-justifiedformat,16-to24-bit
110 Reserved
111 Reserved
The FMT[2:0]bitsareused toselectthedataformatfortheserialaudiointerface. Copyright© 2005–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLink(s):PCM1602A
SLES146A –AUGUST 2005–REVISED OCTOBER 2010 www.ti.com B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 REGISTER 10 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 RSV ZREV DREV DMF1 DMF0 DMC DMC DMC R/W – Read/WriteMode Select When R/W = 0,a writeoperationisperformed. When R/W = 1,a readoperationisperformed. Defaultvalue:0 ZREV – Zero-FlagPolaritySelect Defaultvalue:0 ZREV = 0 Zero-flagpinsHIGH ata zerodetect(default) ZREV = 1 Zero-flagpinsLOW ata zerodetect The ZREV bitallowstheusertoselectthepolarityofzero-flagpins. DREV – Output Phase Select Defaultvalue:0 DREV = 0 Normal output(default) DREV = 1 Invertedoutput The DREV bitallowstheusertoselectthephase oftheanalogoutputsignal. DMF[1:0]– Sampling Frequency SelectionfortheDe-Emphasis Function These bitsareread/write. Defaultvalue:00b DMF[1:0] De-Emphasis Sample Rate Selection 00 44.1kHz (default) 01 48 kHz 10 32 kHz
11 Reserved
The DMF[1:0]bitsareused toselectthesamplingfrequencyused forthedigitalde-emphasisfunctionwhen itis enabled.The de-emphasiscurvesareshown intheTypicalPerformanceCurves sectionofthisdatasheet.The precedingtableshows theavailablesamplingfrequencies. DMC – DigitalDe-Emphasis, All-ChannelFunctionControl Thisbitisread/write. Defaultvalue:0 DMC = 0 De-emphasisdisabledforallchannels(default) DMC = 1 De-emphasisenabledforallchannels The DMC bitsareused toenableordisablethede-emphasisfunctionforallchannels.The threeDMC bitsare ORed together.Settingany one DMC bit,any combinationoftwo DMC bits,or allthreeDMC bitsto1 enables digitalde-emphasisforallchannels.SettingallthreeDMC bitsto0 disablesdigitalde-emphasisforallchannels.
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www.ti.com SLES146A –AUGUST 2005–REVISED OCTOBER 2010 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 REGISTER 11 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 INC REG6 REG5 REG4 REG3 REG2 REG1 REG0 R/W – Read/WriteMode Select When R/W = 0,a writeoperationisperformed. When R/W = 1,a readoperationisperformed. Defaultvalue:0 INC – Auto-IncrementRead Control Thisbitisread/write. Defaultvalue:0 INC = 0 Auto-incrementreaddisabled(default) INC = 1 Auto-incrementreadenabled The INC bitisused toenableor disabletheauto-incrementread featureoftheserialcontrolinterface.See the SerialControlInterfacesectionofthisdatasheetfordetailsregardingauto-incrementreadoperation. REG[6:0]– Read RegisterIndex These bitsareread/write. Defaultvalue:01h The REG[6:0]bitsare used tosettheindexoftheregistertobe read when performingthesingle-registerread operation.In the case of an auto-incrementread operation,the REG[6:0] bitsindicatethe indexof the last registertobe read intheauto-incrementread sequence.For example,ifregisters1 through6 are tobe read duringan auto-incrementreadoperation,theREG[6:0]bitswould be setto06h.See theSerialControlInterface sectionofthisdatasheetfordetailsregardingthesingle-registerand auto-incrementreadoperations. Copyright© 2005–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLink(s):PCM1602A
SLES146A –AUGUST 2005–REVISED OCTOBER 2010 www.ti.com B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 REGISTER 12 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 OVER GPOE GPO6 GPO5 GPO4 GPO3 GPO2 GPO1 R/W – Read/WriteMode Select When R/W = 0,a writeoperationisperformed. When R/W = 1,a readoperationisperformed. Defaultvalue:0 OVER – Oversampling Rate Control These bitsareread/write. Defaultvalue:0 x System clockrate= 256 fS,384 fS,512 fS,or768 fS: OVER = 0 64× oversampling(default) OVER = 1 128× oversampling x System clockrate= 128 fS or192 fS: OVER = 0 32× oversampling(default) OVER = 1 64× oversampling The OVER bitisused to controlthe oversamplingrateof the delta-sigmaDACs. The OVER = 1 settingis recommended when theoversamplingrateis192 kHz (systemclockrateis128 fS or192 fS). GPOE – General-PurposeOutput Enable Thisbitisread/write. Defaultvalue:0 GPOE = 0 General-purposeoutputsdisabled(default) Pinsdefaulttozero-flagfunction(ZERO1 throughZERO6). GPOE = 1 General-purposeoutputsenabled Data writtentoGPO1 throughGPO6 appearsatthecorrespondingpins. GPOx – General-PurposeLogic Output Where: x = 1 through6,correspondingpinsGPO1 throughGPO6. These bitsareread/write. Defaultvalue:0 GPOx = 0 SetGPOx to0 (default) GPOx = 1 SetGPOx to1 The general-purposeoutputpins,GPO1 throughGPO6, areenabledby settingGPOE = 1.These pinsareused as general-purposeoutputsforcontrollinguser-definedlogicfunctions.When general-purposeoutputsare disabled(GPOE = 0),theydefaulttothezero-flagfunction,ZERO1 throughZERO6.
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f − Frequency − Hz −100 −80 −60 −40 −20 Level − dB 1 100 1k 10M G019 10 10k 100k 1M VCOM OPA337 10 µF PCM1602A S0054-05
1 VBIAS /C0043
www.ti.com SLES146A –AUGUST 2005–REVISED OCTOBER 2010 ANALOG OUTPUTS The PCM1602A includessixindependentoutputchannels,VOUT 1 throughVOUT 6.These areunbalancedoutputs, each capableof driving3.1 VPP typicalintoa 5-kΩ ac loadwithVCC = 5 V. The internaloutputamplifiersfor VOUT 1 throughVOUT 6 aredc biasedtothecommon-mode (orbipolarzero)voltage,equaltoVCC /2. The outputamplifiersincludean RC continuous-timefilter,which helpstoreducetheout-of-bandnoiseenergy presentattheDAC outputsdue tothenoise-shapingcharacteristicsofthePCM1602A delta-sigmaDACs. The frequencyresponse of thisfilteris shown in Figure28. By itself,thisfilteris not enough to attenuatethe out-of-bandnoisetoan acceptablelevelformost applications.An externallow-passfilterisrequiredtoprovide sufficientout-of-bandnoiserejection.FurtherdiscussionofDAC post-filtercircuitsisprovidedintheApplication Informationsectionofthisdatasheet. Figure28. Output-FilterFrequency Response VCOM OUTPUT One unbuffered,common-mode voltageoutputpin,VCOM (pin15),isbroughtoutfordecouplingpurposes.This pinisnominallybiasedtoa dc voltagelevelequaltoVCC /2.Ifthispinistobe used tobiasexternalcircuitry,a voltagefollowerisrequiredforbufferingpurposes.Figure29 shows an example of usingthe VCOM pin for externalbiasingapplications. Figure29. BiasingExternalCircuitsUsing theVCOM Pin Copyright© 2005–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLink(s):PCM1602A
SLES146A –AUGUST 2005–REVISED OCTOBER 2010 www.ti.com ZERO FLAG Zero-DetectCondition Zero detectionforeach outputchannelisindependentfromtheothers.Ifthedatafora givenchannelremainsat a 0 levelfor1024 sample periods(orLRCK clockperiods),a zero-detectconditionexistsforthatchannel. Zero Output Flags Given thata zero-detectconditionexistsforone ormore channels,thezero-flagpinsforthosechannelsareset toa logic-1state.Each channel,ZERO1 throughZERO6 (pins1 through6),has zero-flagpins.Inaddition,allsix zeroflagsarelogicallyANDed together,and theresultisprovidedattheZEROA pin(pin48),whichissettoa logic-1statewhen allchannelsindicatea zero-detectcondition.The zero-flagpinscan be used to operate externalmute circuits,orused as statusindicatorsfora microcontroller,audiosignalprocessor,orotherdigitally controlledfunction. The activepolarityofthezero-flagoutputcan be invertedby settingto1 theZREV bitofcontrolregister10.The resetdefaultisactive-highoutput,orZREV = 0.
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10 µF 10 µF 10 µF ZERO1−6 5-V Power Supply S0090-04 PLL170x SCKO3 ML MC MD Regulator Microcontroller LPF LPF LPF LPF LPF LPF VOUT 1 VOUT 2 VOUT 3 VOUT 4 VOUT 5 VOUT 6 LRCK RST BCK DATA1 DATA2 DATA3 ZEROA 3536 25262728293031323334 VCC 3 AGND3 VCC 4 AGND4 NC AGND6 VCC 5 AGND5 NC VCOM VOUT 1 VOUT 2 PCM1602A RST SCKI SCKO BCK LRCK TEST VDD DGND DATA1 DATA2 DATA3 ZEROA 21 1211109876543 ML MC MDI MDO NC NC NC NC VCC 1 AGND1 VCC 2 AGND2 ZERO1/GPO1 ZERO2/GPO2 ZERO3/GPO3 ZERO4/GPO4 ZERO5/GPO5 ZERO6/GPO6 NC NC VOUT 6 VOUT 5 VOUT 4 VOUT 3 PCM1602A www.ti.com SLES146A –AUGUST 2005–REVISED OCTOBER 2010
APPLICATION INFORMATION
A basicconnectiondiagramwiththenecessarypower-supplybypassingand decouplingcomponents isshown in Figure30.Texas Instrumentsrecommends usingthecomponent valuesshown inFigure30 foralldesigns. Figure30. Basic Connection Diagram Copyright© 2005–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLink(s):PCM1602A
0.1 µF 5-V Analog S0091-04 µC/µP(1) LF 3536 25262728293031323334 VCC 3 AGND3 VCC 4 AGND4 NC AGND6 VCC 5 AGND5 NC VCOM VOUT 1 VOUT 2 PCM1602A RST SCKI SCKO BCK LRCK TEST VDD DGND DATA1 DATA2 DATA3 ZEROA 21 1211109876543 Zero Flag or General-Purpose Outputs for Mute Circuits, Microcontroller, or DSP/Decoder 10 µF REG1117 3.3 V
3.3 V for VDD
10 µF Output Low-Pass Filters(4) 10 µF 10 µF + RF LS10 µF 10 µF + RS 10 µF + CTR 10 µF + SUB DIGITAL SECTION ANALOG SECTION C 11 10 µF 3.3 V for VDD C 10 0.1 µF R S(3) PLL170x Buffer SCKO3 (2) XT1 27-MHz Master Clock R S R S Audio DSP or Decoder R S R S R S PCM1602A SLES146A –AUGUST 2005–REVISED OCTOBER 2010 www.ti.com (1) Serialcontroland resetfunctionscan be providedby DSP/decoderGPIO pins. (2) Actualclockoutputused isdeterminedby theapplication. (3) R S = 22 Ω to100 Ω. (4) See theApplicationInformationsectionofthisdatasheetformore information. Figure31. TypicalApplicationDiagram
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www.ti.com SLES146A –AUGUST 2005–REVISED OCTOBER 2010 A typicalapplicationdiagram isshown in Figure31. The REG1117-3.3 from Texas Instrumentsisused to generate3.3 V forVDD from the 5-V analogpower supply.The PLL170x from Texas Instrumentsisused to generatethesystemclockinputatSCKI,as wellas generatingtheclockfortheaudiosignalprocessor. Seriesresistors(22-Ω to 100-Ω) are recommended forSCKI, LRCK, BCK, DATA1, DATA2, and DATA3. The seriesresistorcombineswiththestrayPCB and deviceinputcapacitancetoforma low-passfilterwhichremoves high-frequencynoisefromthedigitalsignal,thusreducinghigh-frequencyemission. POWER SUPPLIES AND GROUNDING The PCM1602A requiresa 5-V analogsupplyand a 3.3-Vdigitalsupply.The 5-V supplyisused topower the DAC analogand outputfiltercircuitry,whereas the 3.3-Vsupplyisused to power the digitalfilterand serial interfacecircuitry.For bestperformance,the3.3-Vsupplyshouldbe derivedfrom the5-V supplyusinga linear regulator(seeFigure31). Two capacitorsarerequiredforsupplybypassing(seeFigure30).These capacitorsshouldbe locatedas close as possibleto the PCM1602A package.The 10-mF capacitorsshouldbe tantalumor aluminum electrolytic, whereas the0.1-mF capacitorsareceramic(X7R typeisrecommended forsurface-mountapplications). DAC OUTPUT FILTER CIRCUITS Delta-sigmaDACs use noise-shapingtechniquestoimprovein-bandsignal-to-noiseratio(SNR) performanceat the expense of generatingincreasedout-of-bandnoiseabove the Nyquistfrequency,or fS/2.The out-of-band noisemust be low-passfilteredinorderto provideoptimalconverterperformance.Thisisaccomplishedby a combinationofon-chipand externallow-passfiltering. Figure 32 and Figure 33 show the recommended externallow-pass activefiltercircuitsfor dual- and single-supplyapplications.These circuitsaresecond-orderButterworthfiltersusingthemultiplefeedback(MFB) circuitarrangement,whichreducessensitivitytopassivecomponent variationsoverfrequencyand temperature. Formore informationregardingMFB activefilterdesign,see theFilterPro™ MFB and Sallen-KeyLow-Pass Filter DesignProgram applicationreport(SBFA001 ),availablefromtheTIWeb site(www.ti.com). Because the overallsystem performanceisdefinedby the qualityof the DACs and theirassociatedanalog outputcircuitry,high-qualityaudiooperationalamplifiersare recommended fortheactivefilters.The OPA2134 and OPA2353 dualoperationalamplifiersfromTexas Instrumentsareshown inFigure32 and Figure33,and are recommended foruse withthePCM1602A. Figure32. Dual-SupplyFilterCircuit Copyright© 2005–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLink(s):PCM1602A
10 µF S0056-05 R 4 OPA337 To Additional Low-Pass Filter Circuits VOUT VIN Digital Logic and Audio Processor Digital Power +VD DGND Digital Section Analog Section Return Path for Digital Signals Analog Power +VSAGND −V S+5VA Digital Ground Analog Ground Output Circuits PCM1602A AGND VCC VDD DGND REG B0031-06 PCM1602A SLES146A –AUGUST 2005–REVISED OCTOBER 2010 www.ti.com Figure33. Single-SupplyFilterCircuit PCB LAYOUT GUIDELINES A typicalPCB floorplanforthePCM1602A isshown inFigure34.A ground planeisrecommended, withthe analog and digitalsectionsbeing isolatedfrom one anotherusing a splitor cut in the circuitboard.The PCM1602A shouldbe orientedwiththedigitalI/Opinsfacingthegroundplanesplit/cuttoallowforshort,direct connectionstothedigitalaudiointerfaceand controlsignalsoriginatingfromthedigitalsectionoftheboard. Figure34. Recommended PCB Layout
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Digital Section Analog Section RF Choke or Ferrite Bead Power Supplies Common Ground Output Circuits AGND VCC +VS+5V −V SAGND VDD DGND REG PCM1602A B0032-06 Digital Logic and Audio Processor PCM1602A www.ti.com SLES146A –AUGUST 2005–REVISED OCTOBER 2010 Separatepower suppliesare recommended forthedigitaland analogsectionsoftheboard.Thispreventsthe switchingnoisepresenton the digitalsupplyfrom contaminatingthe analogpower supplyand degradingthe dynamic performanceof the DACs. In cases where a common 5-V supplymust be used forthe analogand digitalsections,an inductance(RF choke,ferritebead) shouldbe placedbetween the analogand digital5-V supplyconnectionstoavoidcouplingofthedigitalswitchingnoiseintotheanalogcircuitry.Figure35 shows the recommended approachforsingle-supplyapplications. Figure35. Single-SupplyPCB Layout Copyright© 2005–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 35 ProductFolderLink(s):PCM1602A
Z–1 + + 8-Level Quantizer − Z–1IN 8 fS OUT 64 fS + Z–1 + Z–1 PCM1602A SLES146A –AUGUST 2005–REVISED OCTOBER 2010 www.ti.com THEORY OF OPERATION The DAC sectionof the PCM1602A isbased on a multi-bitdelta-sigmaarchitecture.Thisarchitectureuses a fourth-ordernoiseshaper and an 8-levelamplitudequantizer,followedby an analog low-passfilter.A block diagramofthedelta-sigmamodulatorisshown inFigure36.Thisarchitecturehas theadvantageofstabilityand improvedjittertolerance,when compared totraditional1-bit(2-level)delta-sigmadesigns. Figure36. Eight-LevelDelta-SigmaModulator The combined oversamplingrateofthedigitalinterpolationfilterand thedelta-sigmamodulatoris32 fS,64 fS,or 128 fS. The totaloversamplingrateisdeterminedby the desiredsamplingfrequency.IffS ≤ 96 kHz, then the OVER bitinregister12 can be settoan oversamplingrateof64 fS or128 fS.IffS > 96 kHz,thentheOVER bit can be used tosettheoversamplingrateto32 fS or 64 fS.Figure37 shows theout-of-bandquantization-noise plotsforboth the 64× and 128× oversamplingscenarios.Noticethatthe 128× oversamplingplotshows significantlyimprovedout-of-bandnoiseperformance,allowingfora simplifiedlow-passfiltertobe used atthe outputoftheDAC.
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Frequency [fS] −180 −160 −140 −120 −100 −80 −60 −40 −20 0 1 2 3 4 5 6 7 8 Amplitude − dB G021 Frequency [fS] −180 −160 −140 −120 −100 −80 −60 −40 −20 0 1 2 3 4 5 6 7 8 Amplitude − dB G022 Jitter − ps 100 105 110 115 120 125 0 100 200 300 400 500 600 Dynamic Range − dB G020 PCM1602A www.ti.com SLES146A –AUGUST 2005–REVISED OCTOBER 2010 QUANTIZATION NOISE SPECTRUM QUANTIZATION NOISE SPECTRUM vs (64× OVERSAMPLING) (128× OVERSAMPLING) Figure37. Quantization-NoiseSpectrum Figure38 illustratesthesimulatedjittersensitivityofthePCM1602A. To achievebestperformance,thesystem clockjittershouldbe lessthan300 picoseconds.Thisiseasilyachievedusinga qualityclockgenerationIC,like thePLL170x fromTexas Instruments. JITTER DEPENDENCE (64× OVERSAMPLING) Figure38.JitterSensitivity Copyright© 2005–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 37 ProductFolderLink(s):PCM1602A
100% Full-Scale 24-Bit, 1-kHz Sine Wave rms Mode HPF = 22 Hz(1) LPF = 30 kHz(1) Option = 20-kHz Apogee Filter(2) fC = 1 kHz f–3 dB = 54 kHz B0062-04 PCM1602A SLES146A –AUGUST 2005–REVISED OCTOBER 2010 www.ti.com KEY PERFORMANCE PARAMETERS AND MEASUREMENT Thissectionprovidesinformationon how tomeasure key dynamic performanceparametersforthePCM1602A. In allcases,a System Two Cascade audiomeasurement system by Audio Precisionor equivalentisused to performthetesting. TOTAL HARMONIC DISTORTION + NOISE Totalharmonicdistortion+ noise(THD+N) isa significantfigureofmeritforaudioDACs, because ittakesinto accountbothharmonicdistortionand allnoisesourceswithina specifiedmeasurement bandwidth.The trueRMS valueofthedistortionand noiseisreferredtoas THD+N. The testsetupforTHD+N measurements isshown in Figure39. (1) Thereislittledifferenceinmeasured THD+N when usingthevarioussettingsforthesefilters. (2) RequiredforTHD+N test Figure39. TestSetup forTHD+N Measurements For thePCM1602A DACs, THD+N ismeasured witha full-scale,1-kHz digitalsinewave as theteststimulusat theinputoftheDAC. The digitalgeneratorissettoa 24-bitaudioword lengthand a samplingfrequencyof44.1 kHz or96 kHz.The digitalgeneratoroutputistakenfromtheunbalancedS/PDIF connectorofthemeasurement system.The S/PDIF data istransmittedviacoaxialcableto the digitalaudio receiveron the DEM-DAI1602 demonstrationboard.The receiveristhen configuredto output24-bitdata in eitherI2S or left-justifieddata format.The DAC audiointerfaceformatisprogrammed tomatch thereceiveroutputformat.The analogoutputis thentakenfromtheDAC postfilterand connectedtotheanaloganalyzerinputofthemeasurement system.The analog inputisband-limited,usingfiltersresidentin the analyzer.The resultingTHD+N ismeasured by the analyzerand displayedby themeasurement system.
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PCM1602A (1) 2nd-Order Low-Pass Filter Band Limit A-Weight Filter(1) Analyzer and Display Digital Generator S/PDIF Output 0% Full-Scale, Dither Off (SNR) –60 dB FS, 1-kHz Sine Wave (Dynamic Range) rms Mode HPF = 22 Hz LPF = 22 kHz Option = A-Weighting(2) B0063-04 f–3 dB = 54 kHz fC = 1 kHz Notch Filter PCM1602A www.ti.com SLES146A –AUGUST 2005–REVISED OCTOBER 2010 DYNAMIC RANGE Dynamic rangeisspecifiedas A-weightedTHD+N measured witha –60-dBFS,1-kHz digitalsinewave stimulus attheinputoftheDAC. Thismeasurement isdesignedtogivea good indicationofhow theDAC performs,given a low-levelinputsignal. The measurement setupforthedynamic rangemeasurement isshown inFigure40,and issimilartotheTHD+N testsetupdiscussedpreviously.The differencesincludetheband-limitfilterselection,theadditionalA-weighting filter,and the–60-dBFS inputlevel. (1) Infinite-zero-detectmute disabled (2) ResultswithoutA-weightingareapproximately3 dB worse. Figure40. TestSetup forDynamic Range and SNR Measurements IDLE-CHANNEL SIGNAL-TO-NOISE RATIO The SNR testprovidesa measure ofthenoiseoftheDAC. The inputtotheDAC isinall-0sdata,and theDAC infinite-zero-detectmute functionmust be disabled(defaultconditionat power up forthe PCM1602A). This ensuresthatthedelta-sigmamodulatoroutputisconnectedtotheoutputamplifiercircuitso thatidletones(if present)can be observedattheoutput.The ditherfunctionofthedigitalsignalgeneratormust alsobe disabled toensurean all-0sdatastreamattheinputoftheDAC. The measurement setupforSNR isidenticalto thatused fordynamic range,withthe exceptionof the input signallevel(seethenotesprovidedinFigure40). DIFFERENCES BETWEEN THE PCM1602APTR AND PCM1602AMPTR While the two devicesare identical,the key differencebetween both orderableversionsis the physical orientationofthedevicesinthereel.See theappended Package MaterialsInformationsheetformore detailson theorientationofthedevicesinthereels.When changingtheorderablepartnumber, remember toupdatethe toolingprogramtocompensate forthedifferentorientation. Copyright© 2005–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 39 ProductFolderLink(s):PCM1602A
SLES146A –AUGUST 2005–REVISED OCTOBER 2010 www.ti.com
REVISION HISTORY
NOTE: Page numbers forpreviousrevisionsmay differfrompage numbers inthecurrentversion. Changes from Original(August,2005)toRevisionA Page
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www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) PCM1602APT Active Production LQFP (PT) | 48 250 | JEDEC TRAY (10+1) Yes NIPDAU Level-1-260C-UNLIM -25 to 85 PCM1602A PCM1602APT.B Active Production LQFP (PT) | 48 250 | JEDEC TRAY (10+1) Yes NIPDAU Level-1-260C-UNLIM -25 to 85 PCM1602A (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TRAY L - Outer tray length without tabs KO - Outer tray height W - Outer tray width P1 - Tray unit pocket pitch CW - Measurement for tray edge (Y direction) to corner pocket center CL - Measurement for tray edge (X direction) to corner pocket center Text Chamfer on Tray corner indicates Pin 1 orientation of packed units. *All dimensions are nominal Device Package Name Package Type Pins SPQ Unit array matrix Max temperature (°C) L (mm) W (mm) (µm) (mm) CL (mm) CW (mm) PCM1602APT PT LQFP 48 250 10 x 25 150 315 135.9 7620 12.2 11.1 11.25 Pack Materials-Page 1
www.ti.com PACKAGE OUTLINE 0.25 GAGE PLANE 0 -7 7.2 6.8 7.2 6.8 9.2 8.8 4X 5.5 44X 0.5 9.2 8.8 48X 0.27 0.17
1.6 MAX
0.05 MIN
1.45 1.35 0.75 0.45 LQFP - 1.6 mm max heightPT0048A LOW PROFILE QUAD FLATPACK 4215159/B 11/2023 0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Reference JEDEC registration MS-026. 4. This may also be a thermally enhanced plastic package with leads conected to the die pads.
0.08 C A B
A15.000 DETAIL A SCALE 2.000 A B C
www.ti.com EXAMPLE BOARD LAYOUT
0.05 MAX
(8.2) (8.2) 48X (1.6) 48X (0.3) 44X (0.5) (R0.05) TYP LQFP - 1.6 mm max heightPT0048A LOW PROFILE QUAD FLATPACK 4215159/B 11/2023 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE 10.000 PKG SYMM PKG SYMM 13 24
3748 SEE SOLDER MASK
www.ti.com EXAMPLE STENCIL DESIGN (8.2) (8.2) 48X (1.6) 48X (0.3) 44X (0.5) (R0.05) TYP LQFP - 1.6 mm max heightPT0048A LOW PROFILE QUAD FLATPACK 4215159/B 11/2023 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE: 10X PKG SYMM PKG SYMM 13 24 3748
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