PCM1600 BURR-BROWN | Alldatasheet
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Technical content
24-Bit, 96kHz Sampling, 6-Channel, Enhanced Multi-Level, Delta-Sigma DIGITAL-TO-ANALOG CONVERTER PCM1600 PCM1601 TM
DESCRIPTION
The PCM1600 (1) and PCM1601 (1) are CMOS mono- lithic integrated circuits which feature six 24-bit audio digital-to-analog converters and support circuitry in either a LQFP-48 or MQFP-48 package. The digital- to-analog converters utilize Burr-Brown’s enhanced multi-level, delta-sigma architecture, which employ 4th-order noise shaping and 8-level amplitude quanti- zation to achieve excellent signal-to-noise performance and a high tolerance to clock jitter. The PCM1600 and PCM1601 accept industry-stan- dard audio data formats with 16- to 24-bit audio data. Sampling rates up to 100kHz are supported. A full set of user-programmable functions are accessible through a 4-wire serial control port which supports register write and readback functions.
FEATURES
l ANALOG PERFORMANCE: Dynamic Range: 105dB typ SNR: 104dB typ THD+N: 0.0018% typ Full-Scale Output: 3.1Vp-p typ l 8x OVERSAMPLING INTERPOLATION FILTER: Stopband Attenuation: –82dB Passband Ripple: ±0.002dB l SAMPLING FREQUENCY: 10kHz to 100kHz l ACCEPTS 16, 18, 20, AND 24-BIT AUDIO DATA l DATA FORMATS: Standard, I2S, and Left-Justified l SYSTEM CLOCK: 256f S, 384fS, 512fS, or 768fS l USER-PROGRAMMABLE FUNCTIONS: Digital Attenuation: 0dB to –63dB, 0.5dB/Step Soft Mute Zero Detect Mute Zero Flags for Each Output Channel Digital De-Emphasis Digital Filter Roll-Off: Sharp or Slow l DUAL SUPPLY OPERATION: +5V Analog, +3.3V Digital l 5V TOLERANT DIGITAL LOGIC INPUTS l PACKAGES (1): LQFP-48 (PCM1600) and MQFP-48 (PCM1601) © 1999 Burr-Brown Corporation PDS-1523C Printed in U.S.A. March, 2000
APPLICATIONS
l INTEGRATED A/V RECEIVERS l DVD MOVIE AND AUDIO PLAYERS l HDTV RECEIVERS l CAR AUDIO SYSTEMS l DVD ADD-ON CARDS FOR HIGH-END PCs l DIGITAL AUDIO WORKSTATIONS l OTHER MULTI-CHANNEL AUDIO SYSTEMS International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 NOTE: (1) The PCM1600 and PCM1601 utilize the same die and are electrically the same. All references to the PCM1600 apply equally to the PCM1601. For most current data sheet and other product information, visit www.burr-brown.com PCM1601 PCM1600
2PCM1600, PCM1601 SPECIFICATIONS All specifications at +25°C, +VCC = +5V, +VDD = +3.3V, system clock = 384fS (fS = 44.1kHz) and 24-bit data, unless otherwise noted. PCM1600Y, PCM1601Y PARAMETER CONDITIONS MIN TYP MAX UNITS RESOLUTION 24 Bits DATA FORMAT Audio Data Interface Formats User Selectable Standard, I 2S, Left-Justified Data Bit Length User Selectable 16, 18, 20, 24-Bit Audio Data Format MSB-First, Binary Two’s Complement Sampling Frequency (fS) 10 100 kHz System Clock Frequency 256, 384, 512, 768fS DIGITAL INPUT/OUTPUT Logic Family TTL-Compatible Input Logic Level VIH 2.0 V VIL 0.8 V Input Logic Current IIH(1) VIN = VDD 0.1 µA IIL(1) VIN = 0V –0.1 µA IIH(2) VIN = VDD 65 100 µA IIL(2) VIN = 0V –0.1 µA Output Logic Level VOH (3) IOH = –2mA 2.4 V VOL (3) IOL = +2mA 1.0 V VOH (4) IOH = –4mA 2.4 V VOL (4) IOL = +4mA 1.0 V DYNAMIC PERFORMANCE (5) THD+N, V OUT = 0dB f S = 44.1kHz 0.0018 0.0045 % fS = 96kHz 0.0035 % VOUT = –60dB f S = 44.1kHz 0.65 % fS = 96kHz 0.75 % Dynamic Range EIAJ, A-Weighted, f S =44.1kHz 100 105 dB A-Weighted, fS = 96kHz 104 dB Signal-to-Noise Ratio(6) EIAJ, A-Weighted, fS =44.1kHz 98 104 dB A-Weighted, fS = 96kHz 103 dB Channel Separation f S = 44.1kHz 96 102 dB fS = 96kHz 101 dB Level Linearity Error V OUT = –90dB ±0.5 dB DC ACCURACY Gain Error ±1.0 % of FSR Gain Mismatch, Channel-to-Channel ±1.0 % of FSR Bipolar Zero Error V O = 0.5VCC at Bipolar Zero ±30 mV ANALOG OUTPUT Output Voltage Full Scale (0dB) 62% of V CC Vp-p Center Voltage 50% V CC V Load Impedance AC Load 5 k Ω DIGITAL FILTER PERFORMANCE Filter Characteristics 1, Sharp Roll-Off Passband ±0.002dB 0.454f S Hz –3dB 0.490f S Hz Stopband 0.546fS Hz Passband Ripple ±0.002 dB Stopband Attenuation Stopband = 0.546f S –75 dB Stopband = 0.567fS –82 dB Filter Characteristics 2, Slow Roll-Off Passband ±0.002dB 0.274f S Hz –3dB 0.454f S Hz Stopband 0.732fS Hz Passband Ripple ±0.002 dB Stopband Attenuation Stopband = 0.732f S –82 dB Delay Time 34/fS sec De-Emphasis Error ±0.1 dB ANALOG FILTER PERFORMANCE Frequency Response f = 20kHz –0.03 dB f = 44kHz –0.20 dB
3 PCM1600, PCM1601
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. POWER SUPPLY REQUIREMENTS Voltage Range, VDD +3.0 +3.3 +3.6 V Supply Current, IDD (7) fS = 44.1kHz 20 28 mA fS = 96kHz 42 mA ICC fS = 44.1kHz 40 56 mA fS = 96kHz 42 mA Power Dissipation f S = 44.1kHz 266 409 mW fS = 96kHz 349 mW TEMPERATURE RANGE Operation 0 +70 °C Storage –55 +125 °C Thermal Resistance, θJA 100 °C/W NOTES: (1) Pins 38, 40, 41, 45-47 (SCLKI, BCK, LRCK, DATA1, DATA2, DATA3). (2) Pins 34-37 (MDI, MC, ML, RST). (3) Pins 1-6, 48 (ZERO1-6, ZEROA). (4) Pin 39 (SCLKO). (5) Analog performance specifications are tested with Shibasoku #725 THD Meter 400Hz HPF, 30kHz LPF on, average mode with 20kHz bandwidth limiting. The load connected to the analog output is 5kΩ or larger, AC-coupled. (6) SNR is tested with Infinite Zero Detection off. (7) CLKO is disabled. SPECIFICATIONS (Cont.) All specifications at +25°C, +VCC = +5V, +VDD = +3.3V, system clock = 384fS (fS = 44.1kHz) and 24-bit data, unless otherwise noted. PCM1600Y, PCM1601Y PARAMETER CONDITIONS MIN TYP MAX UNITS ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. NOTE: (1) Pin 33 (MDO) when output is disabled. ABSOLUTE MAXIMUM RATINGS PACKAGE SPECIFIED DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE NUMBER RANGE MARKING NUMBER (1) MEDIA PCM1600Y 48-Lead LQFP 340 0 °C to +70°C PCM1600Y PCM1600Y 250-Piece Tray "" " " " PCM1600Y/2K Tape and Reel PCM1601Y 48-Lead MQFP 359 0 °C to +70°C PCM1601Y PCM1601Y 84-Piece Tray "" " " " PCM1601Y/1K Tape and Reel NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces of “PCM1600Y/2K” will get a single 2000-piece Tape and Reel. PACKAGE/ORDERING INFORMATION
4PCM1600, PCM1601 PIN CONFIGURATION Top View LQFP, MQFP BLOCK DIAGRAM ML MC MDI MDO NC NC V CC 0 AGND0 V CC 1 AGND1 V CC 2 AGND2 ZEROA DATA3 DATA2 DATA1 DGND V DD TEST LRCK BCK SCLKO SCLKI RST V OUT 2 VOUT 1 VCOM 2 VCOM 1 AGND6 VCC 6 AGND5 VCC 5 AGND4 VCC 4 AGND3 VCC 3 ZERO1 ZERO2 ZERO3 ZERO4 ZERO5 ZERO6 AGND V CC VOUT 6 VOUT 5 VOUT 4 VOUT 3 48 47 46 45 44 43 42 41 40 39 38 13 14 15 16 17 18 19 20 21 22 23 PCM1600 PCM1601 Audio Serial I/F Output Amp and Low-Pass FilterDAC DAC DAC DAC DAC DAC Oversampling Digital Filter with Function Controller Enhanced Multi-level Delta-Sigma Modulator Output Amp and Low-Pass Filter Output Amp and Low-Pass Filter Output Amp and Low-Pass Filter Output Amp and Low-Pass Filter Output Amp and Low-Pass Filter BCK LRCK DATA1 DATA2 DATA3 Serial Control I/F System Clock Manager Zero Detect Power Supply TEST RST ML MC MDI MDO VOUT 1 VOUT 2 VOUT 5 VOUT 6 VOUT 3 VCOM 1 VCOM 2 VOUT 4 ZERO1 ZERO2 ZERO3 ZERO4 ZERO5 ZERO6 V DD DGND ZEROA SCLKI System Clock SCLKO VCC AGND VCC 0 AGND0 VCC 1-6 AGND1-6
5 PCM1600, PCM1601
1 ZERO1 O Zero Data Flag for V OUT 1. 2 ZERO2 O Zero Data Flag for V OUT 2. 3 ZERO3 O Zero Data Flag for V OUT 3. 4 ZERO4 O Zero Data Flag for V OUT 4. 5 ZERO5 O Zero Data Flag for V OUT 5. 6 ZERO6 O Zero Data Flag for V OUT 6.
7 AGND — Analog Ground
CC — Analog Power Supply, +5V 9V OUT 6 O Voltage Output of Audio Signal Corresponding to Rch on DATA3. 10 V OUT 5 O Voltage Output of Audio Signal Corresponding to Lch on DATA3. 11 V OUT 4 O Voltage Output of Audio Signal Corresponding to Rch on DATA2. 12 V OUT 3 O Voltage Output of Audio Signal Corresponding to Lch on DATA2. 13 V OUT 2 O Voltage Output of Audio Signal Corresponding to Rch on DATA1. 14 V OUT 1 O Voltage Output of Audio Signal Corresponding to Lch on DATA1. 15 V COM 2 O Common Voltage Output. This pin should be bypassed with a 10 µF capacitor to AGND. 16 V COM 1 O Common Voltage Output. This pin should be bypassed with a 10 µF capacitor to AGND.
17 AGND6 — Analog Ground
CC 6 — Analog Power Supply, +5V
19 AGND5 — Analog Ground
CC 5 — Analog Power Supply, +5V
21 AGND4 — Analog Ground
CC 4 — Analog Power Supply, +5V
23 AGND3 — Analog Ground
CC 3 — Analog Power Supply, +5V
25 AGND2 — Analog Ground
CC 2 — Analog Power Supply, +5V
27 AGND1 — Analog Ground
CC 1 — Analog Power Supply, +5V
29 AGND0 — Analog Ground
CC 0 — Analog Power Supply, +5V 31 NC — No Connection. Must be open. 32 NC — No Connection. Must be open.
33 MDO O Serial Data Output for Function Register Control Port
(3)
34 MDI I Serial Data Input for Function Register Control Port (1)
35 MC I Shift Clock for Function Register Control Port (1)
36 ML I Latch Enable for Function Register Control Port (1)
37 RST I System Reset, Active LOW (1)
38 SCLKI I System Clock In. Input frequency is 256, 384, 512 or 768f S.(2) 39 SCLKO O Buffered Clock Output. Output frequency is 256, 384, 512, or 768f S and one-half of 256, 384, 512, or 768fS.
40 BCK I Shift Clock Input for Serial Audio Data (2)
41 LRCK I Left and Right Clock Input. This clock is equal to the sampling rate, f S.(2) 42 TEST — Test Pin. This pin should be connected to DGND. (1) 43 V DD — Digital Power Supply, +3.3V 44 DGND — Digital Ground for +3.3V
45 DATA1 I Serial Audio Data Input for V
OUT 1 and VOUT 2(2)
46 DATA2 I Serial Audio Data Input for V OUT 3 and VOUT 4(2)
47 DATA3 I Serial Audio Data Input for V OUT 5 and VOUT 6(2)
48 ZEROA I Zero Data Flag. Logical “AND” of ZERO1 through ZERO6. NOTES: (1) Schmitt-Trigger input with internal pull-down, 5V tolerant. (2) Schmitt-Trigger input, 5V tolerant. (3) Tri-state output. PIN ASSIGNMENTS
6PCM1600, PCM1601 TYPICAL PERFORMANCE CURVES All specifications at +25°C, VCC = 5V, VDD = 3.3V, SYSCLK = 384fS (fS = 44.1kHz), and 24-bit input data, unless otherwise noted. DIGITAL FILTER Digital Filter (De-Emphasis Off, fS = 44.1kHz) 0 0.5 1 1.5 2 2.5 3 3.5 4 –20 –40 –60 –80 –100 –120 –140 –160 Amplitude (dB) FREQUENCY RESPONSE (Sharp Roll-Off) Frequency (x fS) PASSBAND RIPPLE (Sharp Roll-Off) Frequency (x fS) Amplitude (dB) 0.003 0.002 0.001 –0.001 –0.002 –0.003 FREQUENCY RESPONSE (Slow Roll-Off) Frequency (x fS) Amplitude (dB) –20 –40 –60 –80 –100 –120 –140 TRANSITION CHARACTERISTICS (Slow Roll-Off) Frequency (x fS) Amplitude (dB) –10 –12 –14 –16 –18 –20 DE-EMPHASIS FREQUENCY RESPONSE (f S = 32kHz) 02468 1 0 1 2 1 4 Frequency (kHz) –10 Level (dB) DE-EMPHASIS FREQUENCY RESPONSE (f S = 48kHz) 02468 1 0 1 2 1 4 1 6 1 8 2 0 2 2 Frequency (kHz) –10 Level (dB) DE-EMPHASIS FREQUENCY RESPONSE (f S = 44.1kHz) 02468 1 0 1 2 1 4 1 6 1 8 2 0 Frequency (kHz) –10 Level (dB) DE-EMPHASIS ERROR (f S = 32kHz) 02468 1 0 1 2 1 4 Frequency (kHz) 0.5 0.3 0.1 –0.1 –0.3 –0.5 0.5 0.3 0.1 –0.1 –0.3 –0.5 0.5 0.3 0.1 –0.1 –0.3 –0.5 Level (dB) DE-EMPHASIS ERR0R (f S = 48kHz) 02468 1 0 1 2 1 4 1 6 1 8 2 0 2 2 Frequency (kHz) Level (dB) DE-EMPHASIS ERROR (f S = 44.1kHz) 02468 1 0 1 2 1 4 1 6 1 8 2 0 Frequency (kHz) Level (dB) De-Emphasis Error
7 PCM1600, PCM1601
TYPICAL PERFORMANCE CURVES (Cont.) All specifications at +25°C, VCC = 5V, VDD = 3.3V, SYSCLK = 384fS (fS = 44.1kHz), and 24-bit input data, unless otherwise noted. ANALOG DYNAMIC PERFORMANCE Supply Voltage Characteristics TOTAL HARMONIC DISTORTION + NOISE vs V CC (VDD = 3.3V) VCC (V) THD+N (%) 0.1 0.01 0.001 44.1kHz, 384fS 44.1kHz, 384fS 96kHz, 384fS –60dB 0dB 96kHz, 384fS DYNAMIC RANGE vs V CC (VDD = 3.3V) VCC (V) Dynamic Range (dB) 110 108 106 104 102 100 96kHz, 384fS 44.1kHz, 384fS SIGNAL-TO-NOISE RATIO vs VCC (VDD = 3.3V) VCC (V) SNR (dB) 110 108 106 104 102 100 96kHz, 384fS 44.1kHz, 384fS CHANNEL SEPARATION vs V CC (VDD = 3.3V) VCC (V) Channel Separation (dB) 110 108 106 104 102 100 96kHz, 384fS 44.1kHz, 384fS
8PCM1600, PCM1601 TOTAL HARMONIC DISTORTION + NOISE vs TEMPERATURE (VDD = 3.3V) Temperature (°C) THD+N (%) 0.1 0.01 0.001 –25 0 25 50 75 100 44.1kHz, 384fS 44.1kHz, 384fS 96kHz, 384fS –60dB 0dB 96kHz, 384fS DYNAMIC RANGE vs TEMPERATURE (VDD = 3.3V) Temperature (°C) Dynamic Range (dB) 110 108 106 104 102 100 –25 0 25 50 75 100 96kHz, 384fS 44.1kHz, 384fS TYPICAL PERFORMANCE CURVES (Cont.) All specifications at +25°C, VCC = 5V, VDD = 3.3V, SYSCLK = 384fS (fS = 44.1kHz), and 24-bit input data, unless otherwise noted. ANALOG DYNAMIC PERFORMANCE (con.t) Temperature Characteristics SIGNAL-TO-NOISE RATIO vs TEMPERATURE (VDD = 3.3V) Temperature (°C) SNR (dB) 110 108 106 104 102 100 –25 0 25 50 100 75 96kHz, 384fS 44.1kHz, 384fS CHANNEL SEPARATION vs TEMPERATURE (VDD = 3.3V) Temperature (°C) Channel Separation (dB) 110 108 106 104 102 100 –25 0 25 50 75 100 96kHz, 384fS 44.1kHz, 384fS
9 PCM1600, PCM1601
FIGURE 1. System Clock Input Timing. may be 256, 384, or 512 times the sampling frequency. common audio sampling rates. providing the PCM1600 system clock source.
- The default is SCLKO enabled.
shows the operation of this function. should be set to a logic ‘1’. tion sequence, which lasts for 1024 system clock periods. Control Registers section of this data sheet. NOTE: (1) The 768fS system clock rate is not supported for fS > 64kHz.
11 PCM1600, PCM1601
FIGURE 4. Audio Data Input Formats.
data words. Figure 6 shows the control data word format. FIGURE 6. Control Data Word Format for MDI. FIGURE 7. Write Operation Timing.
0 D7 D6 D5 D4 D3 D2 D15 D14 D1 D0X XXIDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0
FIGURE 5. Audio Interface Timing.
13 PCM1600, PCM1601
FIGURE 8. Read Operation Timing with INC = 0 (Single Register Read). FIGURE 9. Read Operation Timing with INC = 1 (Auto-Increment Read).
15 PCM1600, PCM1601
User-Programmable Mode Controls The PCM1600 includes a number of user-programmable functions which are accessed via control registers. The registers are programmed using the Serial Control Interface which was previously discussed in this data sheet. Table III lists the available mode control functions, along with their reset default conditions and associated register index. FUNCTION RESET DEFAULT CONTROL REGISTER INDEX, IDX[6:0] Digital Attenuation Control, 0dB to –63dB in 0.5dB Steps 0dB, No Attenuation 1 through 6 01 H - 07H Digital Attenuation Load Control Data Load Disabled 7 07 H Digital Attenuation Rate Select 2/f S 70 7 H Soft Mute Control Mute Disabled 7 07 H DAC 1-6 Operation Control DAC 1-6 Enabled 8 08 H Infinite Zero Detect Mute Disabled 8 08 H Audio Data Format Control 24-Bit Standard Format 9 09 H Digital Filter Roll-Off Control Sharp Roll-Off 9 09 H SCLKO Frequency Selection Full Rate (= f SCLKI)9 0 9 H SCLKO Output Enable SCLKO Enabled 9 09 H De-Emphasis Function Control De-Emphasis Disabled 10 0A H De-Emphasis Sample Rate Selection 44.1kHz 10 0A H Read Register Index Control REG[6:0] = 01 H 11 0B H Read Auto-Increment Control Auto-Increment Disabled 11 0B H TABLE III. User-Programmable Mode Controls. TABLE IV. Mode Control Register Map. B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Register 0 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 N/A N/A N/A N/A N/A N/A N/A N/A Register 1 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT17 AT16 AT15 AT14 AT13 AT12 AT11 AT10 Register 2 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT27 AT26 AT25 AT24 AT23 AT22 AT21 AT20 Register 3 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT37 AT36 AT35 AT34 AT33 AT32 AT31 AT30 Register 4 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT47 AT46 AT45 AT44 AT43 AT42 AT41 AT40 Register 5 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT57 AT56 AT55 AT54 AT53 AT52 AT51 AT50 Register 6 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT67 AT66 AT65 AT64 AT63 AT62 AT61 AT60 Register 7 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 ATLD ATTS MUT6 MUT5 MUT4 MUT3 MUT2 MUT1 Register 8 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 res INZD DAC6 DAC5 DAC4 DAC3 DAC2 DAC1 Register 9 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 res res FLT0 CLKD CLKE FMT2 FMT1 FMT0 Register 10 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 res res res DMF1 DMF0 DM56 DM34 DM12 Register 11 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 INC REG6 REG5 REG4 REG3 REG2 REG1 REG0 Register 12 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 N/A N/A N/A N/A N/A N/A N/A N/A Register Map The mode control register map is shown in Table IV. Each register includes a R/W bit, which determines whether a register read (R/W =1) or write (R/W = 0) operation is performed. Each register also includes an index (or address) indicated by the IDX[6:0] bits. Reserved Registers Registers 0 and 12 are reserved for factory use. To ensure proper operation, the user should not write or read these registers.
16PCM1600, PCM1601 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Register 1 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT17 AT16 AT15 AT14 AT13 AT12 AT11 AT10 Register 2 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT27 AT26 AT25 AT24 AT23 AT22 AT21 AT20 Register 3 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT37 AT36 AT35 AT34 AT33 AT32 AT31 AT30 Register 4 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT47 AT46 AT45 AT44 AT43 AT42 AT41 AT40 Register 5 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT57 AT56 AT55 AT54 AT53 AT52 AT51 AT50 Register 6 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 AT67 AT66 AT65 AT64 AT63 AT62 AT61 AT60 REGISTER DEFINITIONS R/W Read/Write Mode Select When R/W = 0, a Write operation is performed. When R/W = 1, a Read operation is performed. Default Value: 0 ATx[7:0] Digital Attenuation Level Setting where x = 1-6, corresponding to the DAC output V OUT x. These bits are Read/Write. Default Value: 1111 1111 B Each DAC output, VOUT 1 through VOUT 6, has a digital attenuator associated with it. The attenuator may be set from 0dB to –63dB, in 0.5dB steps. Alternatively, the attenuator may be set to infinite attenuation (or mute). The attenuation data for each channel can be set individually. However, the data load control (ATLD bit of Control Register 7) is common to all six attenuators. ATLD must be set to ‘1’ in order to change an attenuator’s setting. The attenuation level may be set using the formula below. Attenuation Level (dB) = 0.5 (AT x [7:0] DEC – 255) where: AT x [7:0]DEC = 0 through 255 for: AT x [7:0]DEC = 0 through 128, the attenuator is set to infinite attenuation. The following table shows attenuator levels for various settings. ATx[7:0] Decimal Value Attenuator Level Setting 1111 1111B 255 0dB, No Attenuation (default) 1111 1110B 254 –0.5dB 1111 1101B 253 –1.0dB
- • •
- • •
- • • 1000 0010 B 130 –62.5dB 1000 0001B 129 –63.0dB 1000 0000B 128 Mute
- • •
- • •
- • • 0000 0000 B 0 Mute
17 PCM1600, PCM1601
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Register 7 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 ATLD ATTS MUT6 MUT5 MUT4 MUT3 MUT2 MUT1 R/W Read/Write Mode Select When R/W = 0, a Write operation is performed. When R/W = 1, a Read operation is performed. Default Value: 0 ATLD Attenuation Control This bit is Read/Write. Default Value: 0 ATLD = 0 Attenuation Control Disabled (default) ATLD = 1 Attenuation Control Enabled The ATLD bit must be set to logic “1” in order for the attenuators to function. Setting ATLD to logic “0” will disable the attenuator function and cause the current attenuator data to be lost. Set ATLD = 1 immediately after reset. ATTS Attenuation Rate Select This bit is Read/Write. Default Value: 0 ATTS = 0 Attenuation rate is 2/f S (default) ATTS = 1 Attenuation rate is 4/fS Changes in attenuator levels are made by incrementing or decrementing the attenuator by one step (0.5dB) for every 2/fS or 4/fS time interval until the programmed attenuator setting is reached. This helps to minimize audible ‘clicking’, or zipper noise, while the attenuator is changing levels. The ATTS bit allows you to select the rate at which the attenuator is decremented/incremented during level transitions. MUTx Soft Mute Control where x = 1-6, corresponding to the DAC output V OUT x. These bits are Read/Write. Default Value: 0 MUTx = 0 Mute Disabled (default) MUTx = 1 Mute Enabled The mute bits, MUT1 through MUT6, are used to enable or disable the Soft Mute function for the corresponding DAC outputs, VOUT 1 through VOUT 6. The Soft Mute function is incorporated into the digital attenuators. When Mute is disabled (MUTx = 0), the attenuator and DAC operate normally. When Mute is enabled by setting MUTx = 1, the digital attenuator for the corresponding output will be decremented from the current setting to the infinite attenuation setting one attenuator step (0.5dB) at a time, with the rate of change programmed by the ATTS bit. This provides a quiet, ‘pop’ free muting of the DAC output. Upon returning from Soft Mute, by setting MUTx = 0, the attenuator will be incremented one step at a time to the previously programmed attenuator level.
18PCM1600, PCM1601 R/W Read/Write Mode Select When R/W = 0, a Write operation is performed. When R/W = 1, a Read operation is performed. Default Value: 0 INZD Infinite Zero Detect Mute Control This bit is Read/Write. Default Value: 0 INZD = 0 Infinite Zero Detect Mute Disabled (default) INZD = 1 Infinite Zero Detect Mute Enabled The INZD bit is used to enable or disable the Zero Detect Mute function described in the Zero Flag and Infinite Zero Detect Mute section in this data sheet. The Zero Detect Mute function is independent of the Zero Flag output operation, so enabling or disabling the INZD bit has no effect on the Zero Flag outputs (ZERO1-ZERO6, ZEROA). DACx DAC Operation Control where x = 1-6, corresponding to the DAC output V OUT x. These bits are Read/Write. Default Value: 0 DACx = 0 DAC Operation Enabled (default) DACx = 1 DAC Operation Disabled The DAC operation controls are used to enable and disable the DAC outputs, VOUT 1 through VOUT 6. When DACx = 0, the output amplifier input is connected to the DAC output. When DACx = 1, the output amplifier input is switched to the DC common-mode voltage (V COM 1 or VCOM 2), equal to VCC /2. B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 REGISTER 8 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 res INZD DAC6 DAC5 DAC4 DAC3 DAC2 DAC1
19 PCM1600, PCM1601
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 REGISTER 9 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 res res FLT0 CLKD CLKE FMT2 FMT1 FMT0 R/W Read/Write Mode Select When R/W = 0, a Write operation is performed. When R/W = 1, a Read operation is performed. Default Value: 0 FLT0 Digital Filter Roll-Off Control These bits are Read/Write. Default Value: 000 B FLT0 = 0 Sharp Roll-Off (default) FLT0 = 1 Slow Roll-Off Bit FLT0 allows the user to select the digital filter roll-off that is best suited to their application. Two filter roll- off sections are available: Sharp or Slow. The filter responses for these selections are shown in the Typical Performance Curves section of this data sheet. CLKD SCLKO Frequency Selection This bit is Read/Write. Default Value: 0 CLKD = 0 Full Rate, f SCLKO = fSCLKI (default) CLKD = 1 Half Rate, f SCLKO = fSCLKL /2 The CLKD bit is used to determine the clock frequency at the system clock output pin, SCLKO. CLKE SCLKO Output Enable This bit is Read/Write. Default Value: 0 CLKE = 0 SCLKO Enabled (default) CLKE = 1 SCLKO Disabled The CLKE bit is used to enable or disable the system clock output pin, SCLKO. When SCLKO is enabled, it will output either a full or half rate clock, based upon the setting of the CLKD bit. When SCLKO is disabled, it is set to a high impedance state. FMT[2:0] Audio Interface Data Format These bits are Read/Write. Default Value: 000 B FMT[2:0] Audio Data Format Selection 000 24-Bit Standard Format, Right-Justified Data (default) 001 20-Bit Standard Format, Right-Justified Data 010 18-Bit Standard Format, Right-Justified Data 011 16-Bit Standard Format, Right-Justified Data 100 I 2S Format, 16- to 24-bits
101 Left-Justified Format, 16- to 24-Bits
110 Reserved
111 Reserved
The FMT[2:0] bits are used to select the data format for the serial audio interface.
20PCM1600, PCM1601 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 REGISTER 10 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 res res res DMF1 DMF0 DM56 DM34 DM12 R/W Read/Write Mode Select When R/W = 0, a Write operation is performed. When R/W = 1, a Read operation is performed. Default Value: 0 DMF[1:0] Sampling Frequency Selection for the De-Emphasis Function These bits are Read/Write. Default Value: 00 B DMF[1:0] De-Emphasis Same Rate Selection 00 44.1 kHz (default) 01 48 kHz 10 32 kHz
11 Reserved
The DMF[1:0] bits are used to select the sampling frequency used for the Digital De-Emphasis function when it is enabled. The de-emphasis curves are shown in the Typical Performance Curves section of this data sheet. The table below shows the available sampling frequencies. DM12 Digital De-Emphasis Control for Channels 1 and 2 This bit is Read/Write. Default Value: 0 DM12 = 0 De-Emphasis Disabled for Channels 1 and 2 (default) DM12 = 1 De-Emphasis Enabled for Channels 1 and 2 The DM12 bit is used to enable or disable the De-emphasis function for V OUT 1 and VOUT 2, which correspond to the Left and Right channels of the DATA1 input. DM34 Digital De-Emphasis Control for Channels 3 and 4 This bit is Read/Write. Default Value: 0 DM34 = 0 De-Emphasis Disabled for Channels 3 and 4 (default) DM34 = 1 De-Emphasis Enabled for Channels 3 and 4 The DM34 bit is used to enable or disable the De-Emphasis function for VOUT 3 and VOUT 4, which correspond to the Left and Right channels of the DATA2 input. DM56 Digital De-Emphasis Control for Channels 5 and 6 This bit is Read/Write. Default Value: 0 DM56 = 0 De-Emphasis Disabled for Channels 5 and 6 (default) DM56 = 1 De-Emphasis Enabled for Channels 5 and 6 The DM56 bit is used to enable or disable the de-emphasis function for VOUT 5 and VOUT 6, which correspond to the Left and Right channels of the DATA3 input.
21 PCM1600, PCM1601
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 REGISTER 11 R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 INC REG6 REG5 REG4 REG3 REG2 REG1 REG0 R/W Read/Write Mode Select When R/W = 0, a Write operation is performed. When R/W = 1, a Read operation is performed. Default Value: 0 INC Auto-Increment Read Control This bit is Read/Write. Default Value: 0 INC = 0 Auto-Increment Read Disabled (default) INC = 1 Auto-Increment Read Enabled The INC bit is used to enable or disable the Auto-Increment Read feature of the Serial Control Interface. Refer to the Serial Control Interface section of this data sheet for details regarding Auto-Increment Read operation. REG[6:0] Read Register Index These bits are Read/Write. Default Value: 01 H Bits REG[6:0] are used to set the index of the register to be read when performing a Single Register Read operation. In the case of an Auto-Increment Read operation, bits REG[6:0] indicate the index of the last register to be read in the in the Auto-Increment Read sequence. For example, if Registers 1 through 6 are to be read during an Auto-Increment Read operation, bits REG[6:0] would be set to 06 H . Refer to the Serial Control Interface section of this data sheet for details regarding the Single Register and Auto- Increment Read operations.
FIGURE 11. Output Filter Frequency Response.
1 VBIAS ≈ VCC
FIGURE 12. Biasing External Circuits Using the VCOM 1 COM 1 and VCOM 2 pins for external biasing applications. condition for the data input pins, DATA1 through DATA3. Zero Detect condition exists for the that channel. ‘1’ state when all channels indicate a zero detect condition. shown in Figure 13 for all designs. as generating the clock for the audio signal processor. for SCLKI, LRCK, BCK, DATA1, DATA2, and DATA3.
23 PCM1600, PCM1601
FIGURE 13. Basic Connection Diagram.
FIGURE 14. Typical Application Diagram. section of this data sheet for more information.
25 PCM1600, PCM1601
used to power the digital filter and serial interface circuitry. mended for surface-mount applications). combination of on-chip and external low-pass filtering. active filter circuits for dual and single-supply applications. are recommended for use with the PCM1600 and PCM1601. FIGURE 15. Dual Supply Filter Circuit. FIGURE 16. Single-Supply Filter Circuit.
27 PCM1600, PCM1601
FIGURE 20. Quantization Noise Spectrum. FIGURE 21. Jitter Sensitivity. FIGURE 19. Eight-Level Delta-Sigma Modulator. typical one-bit (2 level) delta-sigma modulator. system clock combinations (256/384/512/768fS). value of the distortion and noise is referred to as THD+N.