PCIMX6D4AYM08CC

IMX6DQIEC NXP | Alldatasheet

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Technical content

Data Sheet: Technical Data Document Number: IMX6DQIEC Rev. 6, 11/2018

Package Information

21 x 21 mm, 0.8 mm pitch NXP Reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.

Ordering Information

1 Introduction

The i.MX 6Dual/6Quad processors represent the latest achievement in integrated multimedia applications processors. These processors are part of a growing family of multimedia-focused products that offer high performance processing and are optimized for lowest power consumption. The i.MX 6Dual/6Quad processors feature advanced implementation of the quad Arm ® Cortex®-A9 core, which operates at speeds up to 800 MHz. They include 2D and 3D graphics processors, 1080p video processing, and integrated power management. Each processor provides a 64-bit DDR3/DDR3L/LPDDR2-800 memory interface and a number of other interfaces for connecting peripherals, such as WLAN, Bluetooth ®, GPS, hard drive, displays, and camera sensors. i.MX 6Dual/6Quad Applications Processors for Industrial Products

3.2 Recommended Connections for Unused Analog

4.2 Power Supplies Requirements and Restrictions . . 31 4.3 Integrated LDO Voltage Regulator Parameters . . 32 4.11 General-Purpose Media In terface (GPMI) Timing. 60

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The i.MX 6Dual/6Quad processors are specifically useful for applications such as the following: The i.MX 6Dual/6Quad processors offers numerous advanced features, such as:  Multilevel memory system—The multilevel memory system of each processor is based on the L1 instruction and data caches, L2 cache, and internal and external memory. The processors support many types of external memory devices, including DDR3, DDR3L, LPDDR2, NOR Flash, PSRAM, cellular RAM, NAND Flash (MLC and SLC), OneNAND™, and managed NAND, including eMMC up to rev 4.4/4.41.  Smart speed technology—The processors have power management throughout the device that enables the rich suite of multimedia features and peripherals to consume minimum power in both active and various low power modes. Smart speed technology enables the designer to deliver a feature-rich product, requiring levels of power far lower than industry expectations.  Dynamic voltage and frequency sca ling—The processors improve th e power efficiency of devices by scaling the voltage and frequency to optimize performance.  Multimedia powerhouse—The multimedia performa nce of each processor is enhanced by a multilevel cache system, Neon® MPE (Media Processor Engine) co-processor, a multi-standard hardware video codec, 2 autonomous and independent image processing units (IPU), and a programmable smart DMA (SDMA) controller.  Powerful graphics acceleration—Ea ch processor provides three independent, integrated graphics processing units: an OpenGL® ES 2.0 3D graphics accelerator with four shaders (up to 200 MTri/s and OpenCL support), 2D graphics accelerator, and dedicated OpenVG™ 1.1 accelerator.  Interface flexibility—Each processor supports c onnections to a variety of interfaces: LCD controller for up to four displays (including parallel display, HDMI1.4, MIPI display, and LVDS display), dual CMOS sensor interface (parallel or through MIPI), high-speed USB on-the-go with PHY, high-speed USB host with PHY, multiple expansion card ports (high-speed MMC/SDIO host and other), 10/100/1000 Mbps Gigabit Ethernet controller, and a variety of other popular interfaces (such as UART, I2C, and I2S serial audio, SATA-II, and PCIe-II).  Advanced security—The processors deliver hardware-enabled security features that enable secure e-commerce, digital rights management (DRM), information encryption, secure boot, and secure software downloads. The security features are discussed in detail in the i.MX 6Dual/6Quad security reference manual (IMX6DQ6SDLSRM).  Integrated power management—The processors integrate linear regulators and internally generate voltage levels for different domains. This significantly simplifies system power management structure.

1.1 Ordering Information

Table 1 shows examples of orderable part numbers covered by this data sheet. This table does not include all possible orderable part numbers. The latest part numbers are available on nxp.com/imx6series. If your desired part number is not listed in the table, or you have questions about available parts, see nxp.com/imx6series or contact your NXP representative.

applies to the i.MX 6Dual/6Quad. contact your NXP representative. Table 1. Example Orderable Part Numbers 1 If a 24 MHz input clock is used (required for USB), the maximum SoC speed is limited to 792 MHz.

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Figure 1. Part Number Nomenclature—i.MX 6Quad and i.MX 6Dual

1.2 Features

800 MHz2 (Industrial grade) 08

852 MHz (Automotive grade) 08

1 GHz

1.2 GHz 12

1. See the nxp.com\\imx6series Web page for latest information on the available silicon revision.
2. If a 24 MHz input clock is used (required for USB), the maximum SoC speed is limited to 792 MHz.
3. If a 24 MHz input clock is used (required for USB), the maximum SoC speed is limited to 996 MHz.

i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018 NXP Semiconductors 5  Frequency of the core (incl uding Neon and L1 cache) as per Table 6.  NEON MPE coprocessor — SIMD Media Processing Architecture — NEON register file with 32x64- bit general-purpose registers — NEON Integer execute pipeline (ALU, Shift, MAC) — NEON dual, single-precision floating poi nt execute pipeline (FADD, FMUL) — NEON load/store and permute pipeline The SoC-level memory system consists of the following additional components:  Boot ROM, including HAB (96 KB)  Internal multimedia / shared, fast access RAM (OCRAM, 256 KB)  Secure/non-secure RAM (16 KB)  External memory interfaces: — 16-bit, 32-bit, and 64-bit DDR3-1066, DDR3L-1066, and 1/2 LPDDR2-800 channels, supporting DDR interleaving mode, for dual x32 LPDDR2 — 8-bit NAND-Flash, including support for Raw MLC/SLC, 2 KB, 4 KB, and 8 KB page size, BA-NAND, PBA-NAND, LBA-NAND, OneNAND™ and others. BCH ECC up to 40 bit. — 16/32-bit NOR Flash. All EIMv2 pi ns are muxed on other interfaces. — 16/32-bit PSRAM, Cellular RAM Each i.MX 6Dual/6Quad processor enables the following interfaces to external devices (some of them are muxed and not available simultaneously):  Hard Disk Drives—SATA II, 3.0 Gbps  Displays—Total five interfaces available. Tota l raw pixel rate of all interfaces is up to 450 Mpixels/sec, 24 bpp. Up to four interfaces may be active in parallel. — One Parallel 24-bit display port, up to 225 Mpix els/sec (for example, WUXGA at 60 Hz or dual HD1080 and WXGA at 60 Hz) — LVDS serial ports—One port up to 170 Mpixels/ sec (for example, WUXGA at 60 Hz) or two ports up to 85 MP/sec each — HDMI 1.4 port — MIPI/DSI, two lanes at 1 Gbps  Camera sensors: — Parallel Camera port (up to 20 bit and up to 240 MHz peak) — MIPI CSI-2 serial camera port, supporting up to 1000 Mbps/lane in 1/2/3-lane mode and up to 800 Mbps/lane in 4-lane mode. The CSI-2 Receiver core can manage one clock lane and up to four data lanes. Each i.MX 6Dual/6Quad processor has four lanes.  Expansion cards: — Four MMC/SD/SDIO card ports all supporting: – 1-bit or 4-bit transfe r mode specifications for SD and SDIO cards up to UHS-I SDR-104 mode (104 MB/s max)

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– 1-bit, 4-bit, or 8-bit transfer mode specific ations for MMC cards up to 52 MHz in both SDR and DDR modes (104 MB/s max) U S B : — One High Speed (HS) USB 2.0 OTG (Up to 480 Mbps), with integrated HS USB PHY — Three USB 2.0 (480 Mbps) hosts: – One HS host with integrated High Speed PHY – Two HS hosts with integrated Hi gh Speed Inter-Chip (HS-IC) USB PHY  Expansion PCI Express por t (PCIe) v2.0 one lane — PCI Express (Gen 2.0) dual m ode complex, supporting Root complex operations and Endpoint operations. Uses x1 PHY configuration.  Miscellaneous IPs and interfaces: — SSI block capable of supporting audio sample frequencies up to 192 kHz stereo inputs and outputs with I2S mode — ESAI is capable of supporting audio sample frequencies up to 260 kHz in I2S mode with 7.1 multi channel outputs — Five UARTs, up to 5.0 Mbps each: – Providing RS232 interface – Supporting 9-bit RS485 multidrop mode – One of the five UARTs (UART1 ) supports 8-wire while the other four support 4-wire. This is due to the SoC IOMUX limitation, because all UART IPs are identical. — Five eCSPI (Enhanced CSPI) — Three I2C, supporting 400 kbps — Gigabit Ethernet Controller (IEEE1588 compliant), 10/100/1000

1 Mbps

— Four Pulse Width Modulators (PWM) — System JTAG Controller (SJC) — GPIO with interrupt capabilities — 8x8 Key Pad Port (KPP) — Sony Philips Digital Interconnect Format (SPDIF), Rx and Tx — Two Controller Area Network (FlexCAN), 1 Mbps each — Two Watchdog timers (WDOG) — Audio MUX (AUDMUX) The i.MX 6Dual/6Quad processors integrate advanced power management unit and controllers:  Provide PMU, including LDO su pplies, for on-chip resources  Use Temperature Sensor for mo nitoring the die temperature  Support DVFS techniques for low power modes  Use Software State Retention and Power Gating for Arm and MPE 1. The theoretical maximum performance of 1 Gbps ENET is limited to 470 Mbps (total for Tx and Rx) due to internal bus throughput limitations. The actual measured performance in optimized environment is up to 400 Mbps. For details, see the ERR004512 erratum in the i.MX 6Dual/6Quad errata document (IMX6DQCE).

i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018 NXP Semiconductors 7  Support various levels of system power modes  Use flexible clock gating control scheme The i.MX 6Dual/6Quad processors use dedicated hardware accelerators to meet the targeted multimedia performance. The use of hardware accelerators is a key factor in obtaining high performance at low power consumption numbers, while having the CPU core relatively free for performing other tasks. The i.MX 6Dual/6Quad processors incorporate the following hardware accelerators:  VPU—Video Processing Unit  IPUv3H—Image Processing Un it version 3H (2 IPUs)  GPU3Dv4—3D Graphics Processing Un it (OpenGL ES 2.0) version 4  GPU2Dv2—2D Graphics Processing Unit (BitBlt) version 2  GPUVG—OpenVG 1.1 Graphics Processing Unit  ASRC—Asynchronous Sample Rate Converter Security functions are enabled and accelerated by the following hardware:  Arm TrustZone including the TZ architecture (s eparation of interrupts, memory mapping, etc.)  SJC—System JTAG Controller. Pr otecting JTAG from debug port attacks by regulating or blocking the access to the system debug features.  CAAM—Cryptographic Acceleration and Assuran ce Module, containing 16 KB secure RAM and True and Pseudo Random Number Generator (NIST certified)  SNVS—Secure Non-Volatile Storage, including Secure Real Time Clock  CSU—Central Security Unit. Enhancement for the IC Identification Module (IIM). Will be configured during boot and by eFUSEs and will determine the security level operation mode as well as the TZ policy.  A-HAB—Advanced High Assurance Boot—HAB v4 with the new embedded enhancements: SHA-256, 2048-bit RSA key, version control mechanism, warm boot, CSU, and TZ initialization.

1.3 Signal Naming Convention

Throughout this document, the updated signal names are used except where referenced as a ball name (such as the Functional Contact Assignments table, Ball Map table, and so on). A master list of the signal name changes is in the document, IMX 6 Series Standardized Signal Name Map (EB792). This list can be used to map the signal names used in older documentation to the new standardized naming conventions. The signal names of the i.MX6 series of products are standardized to align the signal names within the family and across the documentation. Benefits of this standardization are as follows:  Signal names are unique within the scope of an SoC and within the series of products  Searches will return all o ccurrences of the named signal  Signal names are consistent between i.MX 6 series products implementing the same modules  The module instance is incorporated into the signal name This standardization applies only to signal names. The ball names are preserved to prevent the need to change schematics, BSDL models, IBIS models, and so on.

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2 Architectural Overview

The following subsections provide an architectural overview of the i.MX 6Dual/6Quad processor system.

2.1 Block Diagram

Figure 2 shows the functional modules in the i.MX 6Dual/6Quad processor system. Figure 2. i.MX 6Dual/6Quad Industrial Grade System Block Diagram PWM (4) indicates four separate PWM peripherals.

3 HS Ports

3 Modules List

modules in alphabetical order. Table 2. i.MX 6Dual/6Quad Modules List Security Keys, and many other system parameters. accessible through OCOTP_CTRL interface. DMA controller used for GPMI2 operation. timers, Watchdog, and CoreSight debug modules. 6Dual/6Quad processors, the security memory provided is 16 KB. system, and also for the system power management.

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and are locked to prevent further writing. CTM Cross Trigger Matrix Debug / Trace Cross Trigger Matrix IP is used to route triggering events between CTIs. The CTM module is internal to the Cortex-A9 Core Platform. module is internal to the Cortex-A9 Core Platform. 6Dual/6Quad processor has two such modules, one for each IPU. interface support 80 Mbps to 1 Gbps speed per data lane. chapter of the i.MX 6Dual/6Quad reference manual (IMX6DQRM). 6Dual/6Quad errata document (IMX6DQCE). Table 2. i.MX 6Dual/6Quad Modules List (continued)

industry-standard codecs, SPDIF transceivers, and other processors. and extended message frames. module supports 32 bits of I/O. separate DMA channels per NAND device. algorithms, such as Bit BLT, stretch BLT, and many other 2D functions.

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various Vector Drawing functions. Each signal pair contains LVDS special differential pad (PadP, PadM).

256 KB multimedia RAM through a 64-bit AXI bus. OSC 32 kHz OSC 32 kHz Clocking Generates 32. 768 kHz clock from an external crystal. The PCIe IP provides PCI Express Gen 2.0 functionality. Secure/non-secure Internal RAM, interfaced through the CAAM. Internal RAM, which is accessed through OCRAM memory controllers. designed to implement SATA II, 3.0 Gbps HDD connectivity.

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complies with IEEE1149.1 and IEEE1149.6 standards. accesses. Modes are selected through eFUSE configuration. Phillips corporations. It supports Transmitter and Receiver functionality. AC-97), bit depths (up to 24 bits per word), and clock / frame sync options. external DMA controller to minimize its impact on system performance. slots are being used simultaneously.

 Two identical high-speed Host modules connected to HSIC USB ports.

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high-capacity SDHC cards up to 32 GB and SDXC cards up to 2TB. embedded MMC memory or interfaces to on-board SDIO devices. and do support hardware reset. processing, such as rotation and mirroring. list of VPU’s decoding/encoding capabilities.

3.1 Special Signal Considerations

Assignments.” Signal descriptions are defined in the i.MX 6Dual/6Quad reference manual (IMX6DQRM). 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors (IMX6DQ6SDLHDG).

3.2 Recommended Connections fo r Unused Analog Interfaces

programmed or deactivated by a normal mode Software. device. In a typical application use-case, it is used for 24 MHz oscillator.

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Electrical Characteristics

4 Electrical Characteristics

This section provides the device and module-level electrical characteristics for the i.MX 6Dual/6Quad processors.

4.1 Chip-Level Conditions

This section provides the device-level electrical characteristics for the SoC. See Table 3 for a quick reference to the individual tables and sections.

4.1.1 Absolute Maximum Ratings

Stresses beyond those listed under Table 4 may affect reliability or cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated in the Operating Ranges or Parameters tables is not implied. Table 3. i.MX 6Dual/6Quad Chip-Level Conditions

i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018 NXP Semiconductors 19 Table 4. Absolute Maximum Ratings allowed signal overshoot must be derated if NVCC_DRAM exceeds 1.575V. 2 OVDD is the I/O supply voltage.

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4.1.2 Thermal Resistance

Per JEDEC JESD51-2, the intent of thermal resistance measurements is solely for a thermal performance comparison of one package to another in a standardized environment. This methodology is not meant to and will not predict the performance of a package in an application-specific environment.

4.1.2.1 FCPBGA Package Thermal Resistance

Table 5 provides the FCPBGA package thermal resistance data. Table 5. FCPBGA Package Thermal Resistance Data 3 Per JEDEC JESD51-6 with the board horizontal. the top surface of the board near the package.

i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018 NXP Semiconductors 21

4.1.3 Operating Ranges

Table 6 provides the operating ranges of the i.MX 6Dual/6Quad processors. Table 6. Operating Ranges 1.150 V minimum for operation up to 792 MHz. 0.925 V minimum for operation up to 396 MHz. VDD_PU_CAP) require 1.225 V minimum. 1.150 — 1.3 V LDO bypassed for operation up to 792 MHz. 0.925 — 1.3 V LDO bypassed for operation up to 396 MHz. rechargeable backup battery supports. keeping real time and other data on OFF state.

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GPIO supplies10 NVCC_CSI, NVCC_EIM0, NVCC_EIM1, NVCC_EIM2, NVCC_ENET, NVCC_GPIO, NVCC_LCD, NVCC_NANDF, NVCC_SD1, NVCC_SD2, NVCC_SD3, NVCC_JTAG 1.65 1.8, 2.8, 3.3

3.6 V Isolation between the NVCC_EIMx and

NVCC_SDx different supplies allow them to operate at different voltages within the specified range. Example: NVCC_EIM1 can operate at 1.8 V while NVCC_EIM2 operates at 3.3 V. NVCC_LVDS_2P5 NVCC_MIPI 2.25 2.5 2.75 V — HDMI supply voltages HDMI_VP 0.99 1.1 1.3 V — HDMI_VPH 2.25 2.5 2.75 V — PCIe supply voltages PCIE_VP 1.023 1.1 1.3 V — PCIE_VPH 2.325 2.5 2.75 V — PCIE_VPTX 1.023 1.1 1.3 V — SATA Supply voltages SATA_VP 0.99 1.1 1.3 V — SATA_VPH 2.25 2.5 2.75 V — Junction temperature T J -40 90 105 °CS e e i.MX 6Dual/6Quad Product Lifetime Usage Estimates Application Note, AN4724, for information on product lifetime (power-on years) for this processor. 1 Applying the maximum voltage results in maximum power consumption and heat generation. NXP recommends a voltage set point = (Vmin + the supply tolerance). This results in an optimized power/speed ratio. 2 See the Hardware Development Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors (IMX6DQ6SDLHDG) for bypass capacitors requirements for each of the *_CAP supply outputs. 3 For Quad core system, connect to VDD_ARM_IN. For Dual core system, may be shorted to GND together with VDD_ARM23_CAP to reduce leakage. 4 VDD_ARM_IN and VDD_SOC_IN must be at least 125 mV higher than the LDO Output Set Point for correct voltage regulation. 5 VDD_ARM_CAP must not exceed VDD_CACHE_CAP by more than +50 mV. VDD_CACHE_CAP must not exceed VDD_ARM_CAP by more than 200 mV. 6 VDDSOC and VDDPU output voltages must be set according to this rule: VDDARM-VDDSOC/PU<50mV.

7 In LDO enabled mode, the internal LDO output set points must be configured such that the:

VDD_ARM LDO output set point does not exceed the VDD_SOC LDO output set point by more than 100 mV. VDD_SOC LDO output set point is equal to the VDD_PU LDO output set point. The VDD_ARM LDO output set point can be lower than the VDD_SOC LDO output set point, however, the minimum output set points shown in this table must be maintained. 8 In LDO bypassed mode, the external power supply must ensure that VDD_ARM_IN does not exceed VDD_SOC_IN by more than 100 mV. The VDD_ARM_IN supply voltage can be lower than the VDD_SOC_IN supply voltage. The minimum voltages shown in this table must be maintained. 9 To set VDD_SNVS_IN voltage with respect to Charging Currents and RTC, see the Hardware Development Guide for i.MX 6Dual, 6Quad, 6Solo, 6DualLite Families of Applications Processors (IMX6DQ6SDLHDG). Table 6. Operating Ranges (continued)

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4.1.4 External Clock Sources

Each i.MX 6Dual/6Quad processor has two external input system clocks: a low frequency (RTC_XTALI) and a high frequency (XTALI). The RTC_XTALI is used for low-frequency functions. It supplies the clock for wake-up circuit, power-down real time clock operation, and slow system and watchdog counters. The clock input can be connected to either an external oscillator or a crystal using the internal oscillator amplifier. Additionally, there is an internal ring oscillator, that can be used instead of RTC_XTALI when accuracy is not important. The system clock input XTALI is used to generate the main system clock. It supplies the PLLs and other peripherals. The system clock input can be connected to either an external oscillator or a crystal using the internal oscillator amplifier. NOTE The internal RTC oscillator does not provide an accurate frequency and is affected by process, voltage and temperature variations. NXP strongly recommends using an external crystal as the RTC_XTALI reference. If the internal oscillator is used instead, careful consideration should be given to the timing implications on all of the SoC modules dependent on this clock. Table 7 shows the interface frequency requirements. The typical values shown in Table 7 are required for use with NXP BSPs to ensure precise time keeping and USB operation. For RTC_XTALI operation, two clock sources are available:  On-chip 40 kHz ring oscillator: This cloc k source has the following characteristics: — Approximately 25 μA more Idd than crystal oscillator — Approximately ±50% tolerance — No external component required — Starts up quicker than 32 kHz crystal oscillator  External crystal os cillator with on-chip support circuit 10 All digital I/O supplies (NVCC_xxxx) must be powered under normal conditions whether the associated I/O pins are in use or not, and associated I/O pins need to have a pull-up or pull-down resistor applied to limit any floating gate current. 11 This supply also powers the pre-drivers of the DDR I/O pins; therefore, it must always be provided, even when LVDS is not used. Table 7. External Input Clock Frequency 1 External oscillator or a crystal with internal oscillator amplifier. Development Guide for i.MX 6Dual, 6Quad, 6Solo, 6DualLite Families of Applications Processors (IMX6DQ6SDLHDG). 3 Recommended nominal frequency 32.768 kHz. 4 External oscillator or a fundamental frequency crystal with internal oscillator amplifier.

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— At power up, an internal ring oscillator is used. After crystal oscillator is stable, the clock circuit switches over to the crystal oscillator automatically. — Higher accuracy than ring oscillator. — If no external crystal is present, then the ring oscillator is used. The decision to choose a clock source should be based on real-time clock use and precision timeout.

4.1.5 Maximum Measured Supply Currents

Power consumption is highly dependent on the application. Estimating the maximum supply currents required for power supply design is difficult because the use case that requires maximum supply current is not a realistic use case. To help illustrate the effect of the application on power consumption, data was collected while running industry standard benchmarks that are designed to be compute and graphic intensive. The results provided are intended to be used as guidelines for power supply design. Description of test conditions:  The Power Virus data shown in Table 8 represent a use case designed specifically to show the maximum current consumption possible for the Arm core complex. All cores are running at the defined maximum frequency and are limited to L1 cache accesses only to ensure no pipeline stalls. Although a valid condition, it would have a very limited, if any, practical use case, and be limited to an extremely low duty cycle unless the intention was to specifically cause the worst case power consumption.  EEMBC CoreMark: Benchmark designed speci fically for the purpose of measuring the performance of a CPU core. More information available at www.eembc.org/coremark. Note that this benchmark is designed as a core performance benchmark, not a power benchmark. This use case is provided as an example of power consumption that would be typical in a computationally-intensive application rather than the Power Virus.  3DMark Mobile 2011: Suite of benchmarks designed for the purpose of measuring graphics and overall system performance. Note that this benchmark is designed as a graphics performance benchmark, not a power benchmark. This use case is provided as an example of power consumption that would be typical in a very graphics-intensive application.  Devices used for the tests were from the hi gh current end of the expected process variation. The NXP power management IC, MMPF0100xxxx, which is targeted for the i.MX 6 series processor family, supports the power consumption shown in Table 8, however a robust thermal design is required for the increased system power dissipation. See the i.MX 6Dual/6Quad Power Consumption Measurement Application Note (AN4509) for more details on typical power consumption under various use case definitions.

i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018 NXP Semiconductors 25 Table 8. Maximum Supply Currents

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4.1.6 Low Power Mode Supply Currents

Table 9 shows the current core consumption (not including I/O) of the i.MX 6Dual/6Quad processors in selected low power modes. MISC DRAM_VREF — 1 mA 1 The actual maximum current drawn from VDD_HIGH_IN will be as shown plus any additional current drawn from the VDD_HIGH_CAP outputs, depending upon actual application configuration (for example, NVCC_LVDS_2P5, NVCC_MIPI, or HDMI, PCIe, and SATA VPH supplies). 2 Under normal operating conditions, the maximum current on VDD_SNVS_IN is shown Table 8. The maximum VDD_SNVS_IN current may be higher depending on specific operating configurations, such as BOOT_MODE[1:0] not equal to 00, or use of the Tamper feature. During initial power on, VDD_SNVS_IN can draw up to 1 mA if the supply is capable of sourcing that current. If less than 1 mA is available, the VDD_SNVS_CAP charge time will increase. 3 This is the maximum current per active USB physical interface. 4 The DRAM power consumption is dependent on several factors such as external signal termination. DRAM power calculators are typically available from memory vendors which take into account factors such as signal termination. See the i.MX 6Dual/6Quad Power Consumption Measurement Application Note (AN4509) for examples of DRAM power consumption during specific use case scenarios.

5 General equation for estimated, maximum power consumption of an IO power supply:

Imax = N x C x V x (0.5 x F) Where: N—Number of IO pins supplied by the power line C—Equivalent external capacitive load V—IO voltage (0.5 xF)—Data change rate. Up to 0.5 of the clock rate (F) In this equation, Imax is in Amps, C in Farads, V in Volts, and F in Hertz.Table 9. Stop Mode Current and Power Consumption Mode Test Conditions Supply Typical 1 Unit WAIT  Arm, SoC, and PU LDOs are set to 1.225 V  HIGH LDO set to 2.5 V  Clocks are gated  DDR is in self refresh  PLLs are active in bypass (24 MHz)  Supply voltages remain ON VDD_ARM_IN (1.4 V) 6 mA VDD_SOC_IN (1.4 V) 23 mA VDD_HIGH_IN (3.0 V) 3.7 mA Total 52 mW STOP_ON  Arm LDO set to 0.9 V  SoC and PU LDOs set to 1.225 V  HIGH LDO set to 2.5 V  PLLs disabled  DDR is in self refresh VDD_ARM_IN (1.4 V) 7.5 mA VDD_SOC_IN (1.4 V) 22 mA VDD_HIGH_IN (3.0 V) 3.7 mA Total 52 mW Table 8. Maximum Supply Currents (continued)

i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018 NXP Semiconductors 27 STOP_OFF  Arm LDO set to 0.9 V  SoC LDO set to 1.225 V  PU LDO is power gated  HIGH LDO set to 2.5 V  PLLs disabled  DDR is in self refresh VDD_ARM_IN (1.4 V) 7.5 mA VDD_SOC_IN (1.4 V) 13.5 mA VDD_HIGH_IN (3.0 V) 3.7 mA Total 41 mW STANDBY  Arm and PU LDOs are power gated  SoC LDO is in bypass  HIGH LDO is set to 2.5 V  PLLs are disabled  Low voltage  Well Bias ON  Crystal oscillator is enabled VDD_ARM_IN (0.9 V) 0.1 mA VDD_SOC_IN (0.9 V) 13 mA VDD_HIGH_IN (3.0 V) 3.7 mA Total 22 mW Deep Sleep Mode (DSM)  Arm and PU LDOs are power gated  SoC LDO is in bypass  HIGH LDO is set to 2.5 V  PLLs are disabled  Low voltage  Well Bias ON  Crystal oscillator and bandgap are disabled VDD_ARM_IN (0.9 V) 0.1 mA VDD_SOC_IN (0.9 V) 2 mA VDD_HIGH_IN (3.0 V) 0.5 mA Total 3.4 mW SNVS Only  VDD_SNVS_IN powered  All other supplies off  SRTC running VDD_SNVS_IN (2.8V) 41 μA Total 115 μW 1 The typical values shown here are for information only and are not guaranteed. These values are average values measured on a worst-case wafer at 25°C. Table 9. Stop Mode Current and Power Consumption (continued)

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4.1.7 USB PHY Current Consumption

4.1.7.1 Power Down Mode

In power down mode, everything is powered down, including the VBUS valid detectors, typical condition. Table 10 shows the USB interface current consumption in power down mode. NOTE The currents on the VDD_HIGH_CAP and VDD_USB_CAP were identified to be the voltage divider circuits in the USB-specific level shifters.

4.1.8 SATA Typical Power Consumption

Table 11 provides SATA PHY currents for certain Tx operating modes. NOTE Tx power consumption values are provided for a single transceiver. If T = single transceiver power and C = Clock module power, the total power required for N lanes = N x T + C. Table 10. USB PHY Current Consumption in Power Down Mode Table 11. SATA PHY Current Drain

i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018 NXP Semiconductors 29 4.1.9 PCIe 2.0 Maximum Power Consumption Table 12 provides PCIe PHY currents for certain operating modes. P1: Transmitter idle, Rx powered down, LOS disabled Single Transceiver SATA_VP 0.67 mA SATA_VPH 0.23 Clock Module SATA_VP 6.9 SATA_VPH 6.2 P2: Powered-down state, only LOS and POR enabled Single Transceiver SATA_VP 0.53 mA SATA_VPH 0.11 Clock Module SATA_VP 0.036 SATA_VPH 0.12 PDDQ mode3 Single Transceiver SATA_VP 0.13 mA SATA_VPH 0.012 Clock Module SATA_VP 0.008 SATA_VPH 0.004 1 Programmed for 1.0 V peak-to-peak Tx level. 2 Programmed for 0.9 V peak-to-peak Tx level with no boost or attenuation. 3 LOW power non-functional. Table 12. PCIe PHY Current Drain Table 11. SATA PHY Current Drain (continued)

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4.1.10 HDMI Maximum Power Consumption

Table 13 provides HDMI PHY currents for both Active 3D Tx with LFSR15 data pattern and Power-down modes. P1: Longer Recovery Time Latency, Lower Power State — PCIE_VP (1.1 V) 12 mA PCIE_VPTX (1.1 V) 2.4 PCIE_VPH (2.5 V) 12 Power Down — PCIE_VP (1.1 V) 1.3 mA PCIE_VPTX (1.1 V) 0.18 PCIE_VPH (2.5 V) 0.36 Table 13. HDMI PHY Current Drain Table 12. PCIe PHY Current Drain (continued)

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4.2 Power Supplies Requirements and Restrictions

The system design must comply with power-up sequence, power-down sequence, and steady state guidelines as described in this section to ensure the reliable operation of the device. Any deviation from these sequences may result in the following situations:  Excessive current during power-up phase  Prevention of the device from booting  Irreversible damage to the processor

4.2.1 Power-Up Sequence

For power-up sequence, the restrictions are as follows:  VDD_SNVS_IN supply must be tu rned ON before any other power supply. It may be connected (shorted) with VDD_HIGH_IN supply.  If a coin cell is used to power VDD_SNVS_IN, th en ensure that it is connected before any other supply is switched on.  The SRC_POR_B signal controls the processor POR and must be immediately asserted at power-up and remain asserted until the VDD_ARM_CAP, VDD_SOC_CAP, and VDD_PU_CAP supplies are stable. VDD_ARM_IN and VDD_SOC_IN may be applied in either order with no restrictions. NOTE Ensure that there is no back voltage (leakage) from any supply on the board towards the 3.3 V supply (for example, from the external components that use both the 1.8 V and 3.3 V supplies). NOTE USB_OTG_VBUS and USB_H1_VBUS are not part of the power supply sequence and can be powered at any time.

4.2.2 Power-Down Sequence

There are no special restrictions for i.MX 6Dual/6Quad SoC.

4.2.3 Power Supplies Usage

 All I/O pins must not be exte rnally driven while the I/O power supply for the pin (NVCC_xxx) is OFF. This can cause internal latch-up and malfunctions due to reverse current flows. For information about I/O power supply of each pin, see the “Power Group” column of Table 87, “21 x 21 mm Functional Contact Assignments”.  When the SATA interface is not used, the SATA_VP and SATA_VPH supplies should be grounded. The input and output supplies for rest of the ports (SATA_REXT, SATA_PHY_RX_N, SATA_PHY_RX_P, and SATA_PHY_TX_N) can remain unconnected. It is recommended not to turn OFF the SATA_VPH supply while the SATA_VP supply is ON, as it may lead to excessive

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power consumption. If boundary scan test is used, SATA_VP and SATA_VPH must remain powered.  When the PCIE interface is not used, the PC IE_VP, PCIE_VPH, and PCIE_VPTX supplies should be grounded. The input and output supplies for rest of the ports (PCIE_REXT, PCIE_RX_N, PCIE_RX_P, PCIE_TX_N, and PCIE_TX_P) can remain unconnected. It is recommended not to turn the PCIE_VPH supply OFF while the PCIE_VP supply is ON, as it may lead to excessive power consumption. If boundary scan test is used, PCIE_VP, PCIE_VPH, and PCIE_VPTX must remain powered.

4.3 Integrated LDO Voltage Regulator Parameters

Various internal supplies can be powered ON from internal LDO voltage regulators. All the supply pins named *_CAP must be connected to external capacitors. The onboard LDOs are intended for internal use only and should not be used to power any external circuitry. See the i.MX 6Dual/6Quad reference manual (IMX6DQRM) for details on the power tree scheme recommended operation. NOTE The *_CAP signals should not be powered externally. These signals are intended for internal LDO or LDO bypass operation only.

4.3.1 Digital Regulators (LDO_ARM, LDO_PU, LDO_SOC)

There are three digital LDO regulators (“Digital”, because of the logic loads that they drive, not because of their construction). The advantages of the regulators are to reduce the input supply variation because of their input supply ripple rejection and their on die trimming. This translates into more voltage for the die producing higher operating frequencies. These regulators have three basic modes.  Bypass. The regulation FET is sw itched fully on passing the external voltage, DCDC_LOW, to the load unaltered. The analog part of the regulator is powered down in this state, removing any loss other than the IR drop through the power grid and FET.  Power Gate. The regulation FET is switched fu lly off limiting the current draw from the supply. The analog part of the regulator is powered down here limiting the power consumption.  Analog regulation mode. The regulation FET is c ontrolled such that the output voltage of the regulator equals the programmed target voltage. The target voltage is fully programmable in 25 mV steps. Optionally LDO_SOC/VDD_SOC_CAP can be used to power the HDMI, PCIe, and SATA PHY's through external connections. For additional information, see the i.MX 6Dual/6Quad reference manual (IMX6DQRM).

4.3.2 Regulators for Analog Modules

4.3.2.1 LDO_1P1 / NVCC_PLL_OUT

The LDO_1P1 regulator implements a programmable linear-regulator function from VDD_HIGH_IN (see Table 6 for minimum and maximum input requirements). Typical Programming Operating Range is 1.0 V

i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018 NXP Semiconductors 33 to 1.2 V with the nominal default setting as 1.1 V. The LDO_1P1 supplies the 24 MHz oscillator, PLLs, and USB PHY. A programmable brown-out detector is included in the regulator that can be used by the system to determine when the load capability of the regulator is being exceeded to take the necessary steps. Current-limiting can be enabled to allow for in-rush current requirements during start-up, if needed. Active-pull-down can also be enabled for systems requiring this feature. For information on external capacitor requirements for this regulator, see the Hardware Development Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors (IMX6DQ6SDLHDG). For additional information, see the i.MX 6Dual/6Quad reference manual (IMX6DQRM).

4.3.2.2 LDO_2P5

The LDO_2P5 module implements a programmable linear-regulator function from VDD_HIGH_IN (see Table 6 for min and max input requirements). Typical Programming Operating Range is 2.25 V to 2.75 V with the nominal default setting as 2.5 V. The LDO_2P5 supplies the SATA PHY, USB PHY, LVDS PHY, HDMI PHY, MIPI PHY, E-fuse module and PLLs. A programmable brown-out detector is included in the regulator that can be used by the system to determine when the load capability of the regulator is being exceeded, to take the necessary steps. Current-limiting can be enabled to allow for in-rush current requirements during start-up, if needed. Active-pull-down can also be enabled for systems requiring this feature. An alternate self-biased low-precision weak-regulator is included that can be enabled for applications needing to keep the output voltage alive during low-power modes where the main regulator driver and its associated global bandgap reference module are disabled. The output of the weak-regulator is not programmable and is a function of the input supply as well as the load current. Typically, with a 3 V input supply the weak-regulator output is 2.525 V and its output impedance is approximately 40 Ω. For information on external capacitor requirements for this regulator, see the Hardware Development Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors (IMX6DQ6SDLHDG). For additional information, see the i.MX 6Dual/6Quad reference manual (IMX6DQRM).

4.3.2.3 LDO_USB

The LDO_USB module implements a programmable linear-regulator function from the USB_OTG_VBUS and USB_H1_VBUS voltages (4.4 V–5.25 V) to produce a nominal 3.0 V output voltage. A programmable brown-out detector is included in the regulator that can be used by the system to determine when the load capability of the regulator is being exceeded, to take the necessary steps. This regulator has a built in power-mux that allows the user to select to run the regulator from either VBUS supply, when both are present. If only one of the VBUS voltages is present, then the regulator automatically selects this supply. Current limit is also included to help the system meet in-rush current targets. If no VBUS voltage is present, then the VBUSVALID threshold setting will prevent the regulator from being enabled. For information on external capacitor requirements for this regulator, see the Hardware Development Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors (IMX6DQ6SDLHDG).

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For additional information, see the i.MX 6Dual/6Quad reference manual (IMX6DQRM).

4.4 PLL Electrical Characteristics

4.4.1 Audio/Video PLL Electrical Parameters

4.4.2 528 MHz PLL

4.4.3 Ethernet PLL

4.4.4 480 MHz PLL Table 14. Audio/Video PLL Electrical Parameters Table 15. 528 MHz PLL Electrical Parameters Table 16. Ethernet PLL Electrical Parameters Table 17. 480 MHz PLL Electrical Parameters

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4.4.5 Arm PLL

4.5 On-Chip Oscillators

4.5.1 OSC24M

This block implements an amplifier that when combined with a suitable quartz crystal and external load capacitors implements an oscillator. The oscillator is powered from NVCC_PLL_OUT. The system crystal oscillator consists of a Pierce-type structure running off the digital supply. A straight forward biased-inverter implementation is used.

4.5.2 OSC32K

This block implements an amplifier that when combined with a suitable quartz crystal and external load capacitors implements a low power oscillator. It also implements a power mux such that it can be powered from either a ~3 V backup battery (VDD_SNVS_IN) or VDD_HIGH_IN such as the oscillator consumes power from VDD_HIGH_IN when that supply is available and transitions to the back up battery when VDD_HIGH_IN is lost. In addition, if the clock monitor determines that the OSC32K is not present, then the source of the 32 kHz clock will automatically switch to the internal ring oscillator. CAUTION The internal RTC oscillator does not provide an accurate frequency and is affected by process, voltage, and temperature variations. NXP strongly recommends using an external crystal as the RTC_XTALI reference. If the internal oscillator is used instead, careful consideration must be given to the timing implications on all of the SoC modules dependent on this clock. The OSC32k runs from VDD_SNVS_CAP, which comes from the VDD_HIGH_IN/VDD_SNVS_IN power mux. Table 18. Arm PLL Electrical Parameters

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4.6 I/O DC Parameters

This section includes the DC parameters of the following I/O types:  General Purpose I/O (GPIO)  Double Data Rate I/O (DDR) fo r LPDDR2 and DDR3/DDR3L modes L V D S I / O NOTE The term ‘OVDD’ in this section refers to the associated supply rail of an input or output. Figure 3. Circuit for Parameters Voh and Vol for I/O Cells Table 19. OSC32K Main Characteristics —4 μA — The typical value shown is only for the oscillator, driven by an external crystal. approximately 25 μA must be added to this value. typically 1/2 of the capacitances realized on the PCB on either side of the quartz. will decrease the oscillating margin.

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4.6.1 XTALI and RTC_XTALI (C lock Inputs) DC Parameters

Table 20 shows the DC parameters for the clock inputs. NOTE The Vil and Vih specifications only apply when an external clock source is used. If a crystal is used, Vil and Vih do not apply.

4.6.2 General Purpose I/O (GPIO) DC Parameters

Table 21 shows DC parameters for GPIO pads. The parameters in Table 21 are guaranteed per the operating ranges in Table 6, unless otherwise noted. Table 20. XTALI and RTC_XTALI DC Parameters 1 This voltage specification must not be exceeded and, as such, is an absolute maximum specification.

24 MHz clock

2 This current draw is present even if an external clock source directly drives XTALI. Table 21. GPIO I/O DC Parameters

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4.6.3 DDR I/O DC Parameters

The DDR I/O pads support LPDDR2 and DDR3/DDR3L operational modes. 4.6.4 RGMII I/O 2.5V I/O DC Electrical Parameters The RGMII interface complies with the RGMII standard version 1.3. The parameters in Table 22 are guaranteed per the operating ranges in Table 6, unless otherwise noted. Input current (no pull-up/down) Iin Vin = OVDD or 0 -1 1 μA Input current (22 kΩ pull-up) Iin Vin = 0 V Vin = OVDD —2 1 2 1 μA Input current (47 kΩ pull-up) Iin Vin = 0 V Vin = OVDD —1 0 0 1 μA Input current (100 kΩ pull-up) Iin Vin = 0 V Vin= OVDD —4 8 1 μA Input current (100 kΩ pull-down) Iin Vin = 0 V Vin = OVDD 48 μA Keeper circuit resistance Rkeep Vin = 0.3 x OVDD Vin = 0.7 x OVDD 105 175 kΩ 1 Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.6 V, and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/ undershoot must be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device. 2 DSE is the Drive Strength Field setting in the associated IOMUX control register. 3 To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC level through to the target DC level, Vil or Vih. Monotonic input transition time is from 0.1 ns to 1 s. 4 Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled. Table 22. RGMII I/O 2.5V I/O DC Electrical Parameters1 Table 21. GPIO I/O DC Parameters (continued)

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4.6.4.1 LPDDR2 Mode I/O DC Parameters

For details on supported DDR memory configurations, see Section 4.10.2, “MMDC Supported DDR3/DDR3L/LPDDR2 Configurations.” The parameters in Table 23 are guaranteed per the operating ranges in Table 6, unless otherwise noted. Schmitt trigger VT+ 3, 4 VTH+ —0 . 5 x O V D D — m V Schmitt trigger VT- 3, 4 VTH- — — 0.5xOVDD mV Pull-up resistor (22 kΩ PU) R PU_22K Vin=0V — 212 μA Pull-up resistor (22 kΩ PU) R PU_22K Vin=OVDD — 1 μA Pull-up resistor (47 kΩ PU) R PU_47K Vin=0V — 100 μA Pull-up resistor (47 kΩ PU) R PU_47K Vin=OVDD — 1 μA Pull-up resistor (100 kΩ PU) R PU_100K Vin=0V — 48 μA Pull-up resistor (100 kΩ PU) R PU_100K Vin=OVDD — 1 μA Pull-down resistor (100 kΩ PD) R PD_100K Vin=OVDD — 48 μA Pull-down resistor (100 kΩ PD) R PD_100K Vin=0V — 1 μA Keeper Circuit Resistance R keep — 105 165 k Ω Input current (no pull-up/down) I in VI = 0,VI = OVDD -2.9 2.9 μA 1 Input Mode Selection: SW_PAD_CTL_GRP_DDR_TYPE_RGMII = 10 (1.8V Mode) SW_PAD_CTL_GRP_DDR_TYPE_RGMII = 11 (2.5V Mode). 2 Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.6 V, and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/ undershoot must be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device. 3 To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC level through to the target DC level, Vil or Vih. Monotonic input transition time is from 0.1 ns to 1 s.

4 Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled

(register IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC[HYS]= 0). Table 23. LPDDR2 I/O DC Electrical Parameters1 Table 22. RGMII I/O 2.5V I/O DC Electrical Parameters1 (continued)

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4.6.4.2 DDR3/DDR3L Mode I/O DC Parameters

For details on supported DDR memory configurations, see Section 4.10.2, “MMDC Supported DDR3/DDR3L/LPDDR2 Configurations.” The parameters in Table 24 are guaranteed per the operating ranges in Table 6, unless otherwise noted. Pull-up/pull-down impedance mismatch MMpupd — -15 +15 % 240 Ω unit calibration resolution Rres — — 10 Ω Keeper circuit resistance Rkeep — 110 175 k Ω 1 Note that the JEDEC LPDDR2 specification (JESD209_2B) supersedes any specification in this document. 2 The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well as the limitations for overshoot and undershoot (see Table 28). Table 24. DDR3/DDR3L I/O DC Electrical Parameters 2 Vref – DDR3/DDR3L external reference voltage. the limitations for overshoot and undershoot (see Table 29). Table 23. LPDDR2 I/O DC Electrical Parameters1 (continued)

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4.6.5 LVDS I/O DC Parameters

The LVDS interface complies with TIA/EIA 644-A standard. See TIA/EIA STANDARD 644-A, “Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits” for details. Table 25 shows the Low Voltage Differential Signaling (LVDS) I/O DC parameters.

4.7 I/O AC Parameters

This section includes the AC parameters of the following I/O types:  General Purpose I/O (GPIO)  Double Data Rate I/O (DDR) fo r LPDDR2 and DDR3/DDR3L modes L V D S I / O The GPIO and DDR I/O load circuit and output transition time waveforms are shown in Figure 4 and Figure 5. Figure 4. Load Circuit for Output Figure 5. Output Transition Time Waveform Table 25. LVDS I/O DC Parameters

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4.7.1 General Purpose I/O AC Parameters

The I/O AC parameters for GPIO in slow and fast modes are presented in the Table 26 and Table 27, respectively. Note that the fast or slow I/O behavior is determined by the appropriate control bits in the IOMUXC control registers. Table 26. General Purpose I/O AC Parameters 1.8 V Mode 1 Hysteresis mode is recommended for inputs with transition times greater than 25 ns. Table 27. General Purpose I/O AC Parameters 3.3 V Mode 1 Hysteresis mode is recommended for inputs with transition times greater than 25 ns.

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4.7.2 DDR I/O AC Parameters

For details on supported DDR memory configurations, see Section 4.10.2, “MMDC Supported DDR3/DDR3L/LPDDR2 Configurations.” Table 28 shows the AC parameters for DDR I/O operating in LPDDR2 mode. Table 29 shows the AC parameters for DDR I/O operating in DDR3/DDR3L mode. Table 28. DDR I/O LPDDR2 Mode AC Parameters1 1 Note that the JEDEC LPDDR2 specification (JESD209_2B) supersedes any specification in this document. the “complementary” input signal. The Minimum value is equal to Vih(ac) – Vil(ac). indicates the voltage at which differential input signal must cross. Table 29. DDR I/O DDR3/DDR3L Mode AC Parameters1

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4.7.3 LVDS I/O AC Parameters

The differential output transition time waveform is shown in Figure 6. Figure 6. Differential LVDS Driver Transition Time Waveform Table 30 shows the AC parameters for LVDS I/O. 1 Note that the JEDEC JESD79_3C specification supersedes any specification in this document. the “complementary” input signal. The Minimum value is equal to Vih(ac) – Vil(ac). indicates the voltage at which differential input signal must cross. Table 30. I/O AC Parameters of LVDS Pad the negative going edge of the same channel. 2 Measurement levels are 20–80% from output voltage. Table 29. DDR I/O DDR3/DDR3L Mode AC Parameters1 (continued)

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4.8 Output Buffer Impedance Parameters

This section defines the I/O impedance parameters of the i.MX 6Dual/6Quad processors for the following I/O types:  General Purpose I/O (GPIO)  Double Data Rate I/O (DDR) for LPDDR2, and DDR3 modes L V D S I / O NOTE GPIO and DDR I/O output driver impedance is measured with “long” transmission line of impedance Ztl attached to I/O pad and incident wave launched into transmission line. Rpu/Rpd and Ztl form a voltage divider that defines specific voltage of incident wave relative to OVDD. Output driver impedance is calculated from this voltage divider (see Figure 7).

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Figure 7. Impedance Matching Load for Measurement

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4.8.1 GPIO Output Buffer Impedance

Table 31 shows the GPIO output buffer impedance (OVDD 1.8 V). Table 32 shows the GPIO output buffer impedance (OVDD 3.3 V). Table 31. GPIO Output Buffer Average Impedance (OVDD 1.8 V) Table 32. GPIO Output Buffer Average Impedance (OVDD 3.3 V)

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4.8.2 DDR I/O Output Buffer Impedance

For details on supported DDR memory configurations, see Section 4.10.2, “MMDC Supported DDR3/DDR3L/LPDDR2 Configurations.” Table 33 shows DDR I/O output buffer impedance of i.MX 6Dual/6Quad processors. Note: 1. Output driver impedance is controlled across PVTs using ZQ calibration procedure. 2. Calibration is done against 240 W external reference resistor. 3. Output driver impedance deviation (calibration accuracy) is ±5% (max/min impedance) across PVTs.

4.8.3 LVDS I/O Output Buffer Impedance

The LVDS interface complies with TIA/EIA 644-A standard. See, TIA/EIA STANDARD 644-A, “Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits” for details.

4.9 System Modules Timing

This section contains the timing and electrical parameters for the modules in each i.MX 6Dual/6Quad processor.

4.9.1 Reset Timing Parameters

Figure 8 shows the reset timing and Table 34 lists the timing parameters. Figure 8. Reset Timing Diagram Table 33. DDR I/O Output Buffer Impedance

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4.9.2 WDOG Reset Timing Parameters

Figure 9 shows the WDOG reset timing and Table 35 lists the timing parameters. Figure 9. WDOG1_B Timing Diagram XTALOSC_RTC_XTALI is approximately 32 kHz. XTALOSC_RTC_XTALI cycle is one period or approximately 30 μs. manual for detailed information.

4.9.3 External Interface Module (EIM)

clock periods are valid for the entire range of allowed frequencies (0–104 MHz). Table 34. Reset Timing Parameters Table 35. WDOG1_B Timing Parameters

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4.9.3.1 EIM Interface Pads Allocation

EIM supports 32-bit, 16-bit and 8-bit devices operating in address/data separate or multiplexed modes. Table 36 provides EIM interface pads allocation in different modes. Table 36. EIM Internal Module Multiplexing1

8 Bit 16 Bit 32 Bit 16 Bit 32 Bit

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4.9.3.2 General EIM Timing-Synchronous Mode

Figure 10, Figure 11, and Table 37 specify the timings related to the EIM module. All EIM output control signals may be asserted and deasserted by an internal clock synchronized to the EIM_BCLK rising edge according to corresponding assertion/negation control fields. Figure 10. EIM Output Timing Diagram Figure 11. EIM Input Timing Diagram

4.9.3.3 Examples of EI M Synchronous Accesses

Table 37. EIM Bus Timing Parameters

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WE4 Clock rise to address valid -0.5 × t × (k+1) - 1.25 -0.5 × t × (k+1) + 2.25 ns WE5 Clock rise to address invalid 0.5 × t × (k+1) - 1.25 0.5 × t × (k+1) + 2.25 ns WE6 Clock rise to EIM_CSx_B valid -0.5 × t × (k+1) - 1.25 -0.5 × t × (k+1) + 2.25 ns WE7 Clock rise to EI M_CSx_B invalid 0.5 × t × (k+1) - 1.25 0.5 × t × (k+1) + 2.25 ns WE8 Clock rise to EIM_WE_B valid -0.5 × t × (k+1) - 1.25 -0.5 × t × (k+1) + 2.25 ns WE9 Clock rise to EI M_WE_B invalid 0.5 × t × (k+1) - 1.25 0.5 × t × (k+1) + 2.25 ns WE10 Clock rise to EIM_OE_B valid -0.5 × t × (k+1) - 1.25 -0.5 × t × (k+1) + 2.25 ns WE11 Clock rise to EIM_OE_B invalid 0.5 × t × (k+1) - 1.25 0.5 × t × (k+1) + 2.25 ns WE12 Clock rise to EIM_EBx_B valid -0.5 × t × (k+1) - 1.25 -0.5 × t × (k+1) + 2.25 ns WE13 Clock rise to EIM_EBx_B invalid 0.5 × t × (k+1) - 1.25 0.5 × t × (k+1) + 2.25 ns WE14 Clock rise to EIM_LBA_B valid -0.5 × t × (k+1) - 1.25 -0.5 × t × (k+1) + 2.25 ns WE15 Clock rise to EI M_LBA_B invalid 0.5 × t × (k+1) - 1.25 0.5 × t × (k+1) + 2.25 ns WE16 Clock rise to output data valid -0.5 × t × (k+1) - 1.25 -0.5 × t × (k+1) + 2.25 ns WE17 Clock rise to output data invalid 0.5 × t × (k+1) - 1.25 0.5 × t × (k+1) + 2.25 ns WE18 Input data setup time to clock rise 2.3 — ns WE19 Input data hold time from clock rise 2 — ns WE20 EIM_WAIT_B setup ti me to clock rise 2 — ns WE21 EIM_WAIT_B hold time from clock rise 2 — ns 1 k represents register setting BCD value. 2 t is clock period (1/Freq). For 104 MHz, t = 9.165 ns. Table 37. EIM Bus Timing Parameters (continued)

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Figure 14. Muxed Address/Data (A/D) Mode, Synchronous Write Access, Figure 15. 16-Bit Muxed A/D Mode, Synchronous Read Access,

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4.9.3.4 General EIM Timing-Asynchronous Mode

Figure 16 through Figure 20 and Table 38 provide timing parameters relative to the chip select (CS) state for asynchronous and DTACK EIM accesses with corresponding EIM bit fields and the timing parameters mentioned above. Asynchronous read and write access length in cycles may vary from what is shown in Figure 16 through Figure 19 as RWSC, OEN & CSN is configured differently. See the i.MX 6Dual/6Quad reference manual (IMX6DQRM) for the EIM programming model. Figure 16. Asynchronous Memory Read Access (RWSC = 5)

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Figure 17. Asynchronous A/D Muxed Read Access (RWSC = 5) Figure 18. Asynchronous Memory Write Access

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Figure 21. DTACK Mode Write Access (DAP=0) Table 38. EIM Asynchronous Timing Parameters Relative to Chip Select1, 2

i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018 NXP Semiconductors 59 WE40 EIM_LBA_B Invalid to EIM_CSx_B Invalid (ADVL is asserted) WE7-WE15-CSN ×t- 3 . 5 - C S N ×t3 . 5 - C S N ×tn s WE40A (muxed A/D) EIM_CSx_B Valid to EIM_LBA_B Invalid WE14-WE6+(ADVN+ADVA+1- CSA)×t -3.5+(ADVN+AD VA+1-CSA) ×t 3.5+(ADVN+ADVA +1-CSA) ×t ns WE41 EIM_CSx_B Valid to Output Data Valid WE16-WE6-WCSA ×t- 3 . 5 - W C S A ×t3 . 5 - W C S A ×tn s WE41A (muxed A/D) EIM_CSx_B Valid to Output Data Valid WE16-WE6+(WADVN+WADVA +ADH+1-WCSA) ×t -3.5+(WADVN+ WADVA +ADH+1-WCSA) 3.5+(WADVN+WADVA +ADH+1-WCSA) ×t ns WE42 Output Data Invalid to EIM_CSx_B Invalid WE17-WE7-CSN ×t- 3 . 5 - C S N ×t3 . 5 - C S N ×tn s MAXCO Output maximum delay from internal driving EIM_ADDRxx/control flip-flops to chip outputs. 10 — 10 ns MAXCSO Output maximum delay from internal chip selects driving flip-flops to EIM_CSx_B out. 10 — 10 ns MAXDI EIM_DATAxx MAXIMUM delay from chip input data to its internal flip-flop 5— 5 n s WE43 Input Data Valid to EIM_CSx_B Invalid MAXCO-MAXCSO+MAXDI MAXCO-MAXCS O+MAXDI —n s WE44 EIM_CSx_B Invalid to Input Data Invalid 00 — n s WE45 EIM_CSx_B Valid to EIM_EBx_B Valid (Write access) WE12-WE6+(WBEA-WCSA) ×t -3.5+(WBEA-WC SA)×t 3.5+(WBEA-WCSA) ×tn s WE46 EIM_EBx_B Invalid to EIM_CSx_B Invalid (Write access) WE7-WE13+(WBEN-WCSN) ×t -3.5+(WBEN-WC SN)×t 3.5+(WBEN-WCSN) ×tn s MAXDTI Maximum delay from EIM_DTACK_B input to its internal flip-flop + 2 cycles for synchronization 10 — 10 ns WE47 EIM_DTACK_B Active to EIM_CSx_B Invalid MAXCO-MAXCSO+MAXDTI MAXCO-MAXCS O+MAXDTI —n s WE48 EIM_CSx_B Invalid to EIM_DTACK_B invalid 00 — n s 1 For more information on configuration parameters mentioned in this table, see the i.MX 6Dual/6Quad reference manual (IMX6DQRM). Table 38. EIM Asynchronous Timing Parameters Relative to Chip Select1, 2 (continued)

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4.10 Multi-Mode DDR Controller (MMDC)

The Multi-mode DDR Controller is a dedicated interface to DDR3/DDR3L/LPDDR2 SDRAM.

4.10.1 MMDC Compatibility with JEDEC-Compliant SDRAMs

The i.MX 6Dual/6Quad MMDC supports the following memory types:  LPDDR2 SDRAM compliant to JESD209-2B LPDDR2 JEDEC standard release June, 2009  DDR3/DDR3L SDRAM compliant to JESD79-3D DDR3 JEDEC standard release April, 2008 MMDC operation with the standards stated above is contingent upon the board DDR design adherence to the DDR design and layout requirements stated in the Hardware Development Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors (IMX6DQ6SDLHDG).

4.10.2 MMDC Supported DDR3/ DDR3L/LPDDR2 Configurations

The table below shows the supported DDR3/DDR3L/LPDDR2 configurations:

4.11 General-Purpose Media Interface (GPMI) Timing

The i.MX 6Dual/6Quad GPMI controller is a flexible interface NAND Flash controller with 8-bit data width, up to 200 MB/s I/O speed and individual chip select. It supports Asynchronous timing mode, Source Synchronous timing mode, and Samsung Toggle timing mode separately described in the following subsections.

2 In this table:

 t means clock period from axi_clk frequency.  CSA means register setting for WCSA when in write operations or RCSA when in read operations.  CSN means register setting for WCSN when in write operations or RCSN when in read operations.  ADVN means register setting for WADVN when in write operations or RADVN when in read operations.  ADVA means register setting for WADVA when in write operations or RADVA when in read operations. Table 39. i.MX 6Dual/6Quad Supported DDR3/DDR3L/LPDDR2 Configurations

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Figure 25. Read Data Latch Cycle Timing Diagram (Non-EDO Mode) Figure 26. Read Data Latch Cycle Timing Diagram (EDO Mode) Table 40. Asynchronous Mode Timing Parameters1

i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018 NXP Semiconductors 63 In EDO mode (Figure 26), NF16/NF17 are different from the definition in non-EDO mode (Figure 25). They are called tREA/tRHOH (NAND_RE_B access time/NAND_RE_B HIGH to output hold). The typical value for them are 16 ns (max for tREA)/15 ns (min for tRHOH) at 50 MB/s EDO mode. In EDO mode, GPMI will sample NAND_DATAxx at rising edge of delayed NAND_RE_B provided by an internal DPLL. The delay value can be controlled by GPMI_CTRL1.RDN_DELAY (see the GPMI chapter of the i.MX 6Dual/6Quad reference manual (IMX6DQRM)). The typical value of this control register is 0x8 at 50 MT/s EDO mode. However, if the board delay is large enough and cannot be ignored, the delay value should be made larger to compensate the board delay. NF16 Data setup on read tDSR — (DS × T -0.67)/18.38 [see 5,6]n s NF17 Data hold on read tDHR 0.82/11.83 [see 5,6]— n s

1 The GPMI asynchronous mode output timing can be controlled by the module’s internal registers

HW_GPMI_TIMING0_ADDRESS_SETUP, HW_GPMI_TIMING0_DATA_SETUP, and HW_GPMI_TIMING0_DATA_HOLD. This AC timing depends on these registers settings. In the table, AS/DS/DH represents each of these settings. 2 AS minimum value can be 0, while DS/DH minimum value is 1. 3 T = GPMI clock period -0.075ns (half of maximum p-p jitter). 4 NF12 is met automatically by the design. 5 Non-EDO mode.

6 EDO mode, GPMI clock ≈ 100 MHz

(AS=DS=DH=1, GPMI_CTL1 [RDN_DELAY] = 8, GPMI_CTL1 [HALF_PERIOD] = 0). Table 40. Asynchronous Mode Timing Parameters1 (continued)

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4.11.2 Source Synchronous Mode AC Timing (ONFI 2.x Compatible) Figure 27 shows the write and read timing of Source Synchronous mode. Figure 27. Source Synchronous Mode Command and Address Timing Diagram

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Figure 30. NAND_DQS/NAND_DQ Read Valid Window Synchronous mode, the typical value of tDQSQ is 0.85 ns (max) and 1 ns (max) for tQHS at 200MB/s. be ignored, the delay value should be made larger to compensate the board delay. Table 41. Source Synchronous Mode Timing Parameters1

1 The GPMI source synchronous mode output timing can be controlled by the module’s internal registers

on these registers settings. In the table, CE_DELAY/PRE_DELAY/POST_DELAY represents each of these settings. 2 T = tCK (GPMI clock period) -0.075ns (half of maximum p-p jitter).

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4.11.3 Samsung Toggle Mode AC Timing

4.11.3.1 Command and Address Timing

Samsung Toggle mode command and address timing is the same as ONFI 1.0 compatible Async mode AC

4.11.3.2 Read and Write Timing

Figure 31. Samsung Toggle Mode Data Write Timing

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Figure 32. Samsung Toggle Mode Data Read Timing Table 42. Samsung Toggle Mode Timing Parameters1

i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018 NXP Semiconductors 69 Figure 30 shows the timing diagram of NAND_DQS/NAND_DATAxx read valid window. For DDR Toggle mode, the typical value of tDQSQ is 1.4 ns (max) and 1.4 ns (max) for tQHS at 133 MB/s. GPMI will sample NAND_DATA[7:0] at both rising and falling edge of a delayed NAND_DQS signal, which is provided by an internal DPLL. The delay value of this register can be controlled by GPMI register GPMI_READ_DDR_DLL_CTRL.SLV_DLY_TARGET (see the GPMI chapter of the i.MX 6Dual/6Quad reference manual (IMX6DQRM)). Generally, the typical delay value is equal to 0x7 which means 1/4 clock cycle delay expected. However, if the board delay is large enough and cannot be ignored, the delay value should be made larger to compensate the board delay.

4.12 External Peripheral Interface Parameters

The following subsections provide information on external peripheral interfaces.

4.12.1 AUDMUX Timing Parameters

The AUDMUX provides a programmable interconnect logic for voice, audio, and data routing between internal serial interfaces (SSIs) and external serial interfaces (audio and voice codecs). The AC timing of AUDMUX external pins is governed by the SSI module. For more information, see the respective SSI electrical specifications found within this document.

4.12.2 ECSPI Timing Parameters

This section describes the timing parameters of the ECSPI block. The ECSPI has separate timing parameters for master and slave modes. NF28 Data write setup tDS 6 0.25 × tCK - 0.32 — ns NF29 Data write hold tDH 6 0.25 × tCK - 0.79 — ns NF30 NAND_DQS/NAND_DQ read setup skew tDQSQ 7 —3 . 1 8 — NF31 NAND_DQS/NAND_DQ read hold skew tQHS 7 —3 . 2 7 —

1 The GPMI toggle mode output timing can be controlled by the module’s internal registers

HW_GPMI_TIMING0_ADDRESS_SETUP, HW_GPMI_TIMING0_DATA_SETUP, and HW_GPMI_TIMING0_DATA_HOLD. This AC timing depends on these registers settings. In the table, AS/DS/DH represents each of these settings. 2 AS minimum value can be 0, while DS/DH minimum value is 1. 3 T = tCK (GPMI clock period) -0.075ns (half of maximum p-p jitter). 4 CE_DELAY represents HW_GPMI_TIMING2[CE_DELAY]. NF18 is met automatically by the design. Read/Write operation is started with enough time of ALE/CLE assertion to low level. 5 PRE_DELAY+1) ≥ (AS+DS). 6 Shown in Figure 28. 7 Shown in Figure 29. Table 42. Samsung Toggle Mode Timing Parameters1 (continued)

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4.12.2.1 ECSPI Master Mode Timing

Figure 33 depicts the timing of ECSPI in master mode and Table 43 lists the ECSPI master mode timing characteristics. Figure 33. ECSPI Master Mode Timing Diagram Table 43. ECSPI Master Mode Timing Parameters

1 ECSPI slow includes:

2 ECSPI fast includes:

4 ECSPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals. connected between a single master and a single slave.

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4.12.2.2 ECSPI Slave Mode Timing

Figure 34 depicts the timing of ECSPI in slave mode and Table 44 lists the ECSPI slave mode timing characteristics. Figure 34. ECSPI Slave Mode Timing Diagram Table 44. ECSPI Slave Mode Timing Parameters nected between a single master and a single slave.

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4.12.3 Enhanced Serial Audio Inte rface (ESAI) Timing Parameters

The ESAI consists of independent transmitter and receiver sections, each section with its own clock generator. Table 45 shows the interface timing values. The number field in the table refers to timing signals found in Figure 35 and Figure 36. Table 45. Enhanced Serial Audio Interface (ESAI) Timing

62 Clock cycle 4 tSSICC 4 × Tc

63 Clock high period:

64 Clock low period:

65 ESAI_RX_CLK rising edge to ESAI_RX_FS out (bl) high —

66 ESAI_RX_CLK rising edge to ESAI_RX_FS out (bl) low —

67 ESAI_RX_CLK rising edge to ESAI_RX_FS out (wr)

68 ESAI_RX_CLK rising edge to ESAI_RX_FS out (wr) low

69 ESAI_RX_CLK rising edge to ESAI_RX_FS out (wl) high —

70 ESAI_RX_CLK rising edge to ESAI_RX_FSout (wl) low —

71 Data in setup time before ESAI_RX_CLK (serial clock in

72 Data in hold time afte r ESAI_RX_CLK falling edge —

73 ESAI_RX_FS input (bl, w r) high before ESAI_RX_CLK

74 ESAI_RX_FS input (wl) hi gh before ESAI_RX_CLK

75 ESAI_RX_FS input hold time after ESAI_RX_CLK falling

78 ESAI_TX_CLK rising edge to ESAI_TX_FS out (bl) high —

79 ESAI_TX_CLK rising edge to ESAI_TX_FS out (bl) low —

80 ESAI_TX_CLK rising edge to ESAI_TX_FS out (wr)

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81 ESAI_TX_CLK rising edge to ESAI_TX_FS out (wr) low 5 —

22.0 12.0 x ck i ck ns

82 ESAI_TX_CLK rising edge to ESAI_TX_FS out (wl) high —

19.0 9.0 x ck i ck ns

83 ESAI_TX_CLK rising edge to ESAI_TX_FS out (wl) low —

20.0 10.0 x ck i ck ns

84 ESAI_TX_CLK rising edge to da ta out enable from high

22.0 17.0 x ck i ck ns

86 ESAI_TX_CLK rising edge to data out valid —

19.0 13.0 x ck i ck ns

87 ESAI_TX_CLK rising edge to data out high impedance 67 —

21.0 16.0 x ck i ck ns

89 ESAI_TX_FS input (bl, wr) setup time before

ESAI_TX_CLK falling edge5 2.0 18.0 x ck i ck ns

90 ESAI_TX_FS input (wl) se tup time before ESAI_TX_CLK

2.0 18.0 x ck i ck ns

91 ESAI_TX_FS input hold time after ESAI_TX_CLK falling

4.0 5.0 x ck i ck ns

95 ESAI_RX_HF_CLK/ESAI_TX_HF _CLK clock cycle — 2 x T

C 15 — — ns

96 ESAI_TX_HF_CLK i nput rising edge to ESAI_TX_CLK

—— — 1 8 . 0 — n s

97 ESAI_RX_HF_CLK input ri sing edge to ESAI_RX_CLK

—— — 1 8 . 0 — n s 1 i ck = internal clock x ck = external clock i ck a = internal clock, asynchronous mode (asynchronous implies that ESAI_TX_CLK and ESAI_RX_CLK are two different clocks) i ck s = internal clock, synchronous mode (synchronous implies that ESAI_TX_CLK and ESAI_RX_CLK are the same clock) 2 bl = bit length wl = word length wr = word length relative

3 ESAI_TX_CLK(ESAI_TX_CLK pin) = transmit clock

ESAI_RX_CLK(ESAI_RX_CLK pin) = receive clock ESAI_TX_FS(ESAI_TX_FS pin) = transmit frame sync ESAI_RX_FS(ESAI_RX_FS pin) = receive frame sync ESAI_TX_HF_CLK(ESAI_TX_HF_CLK pin) = transmit high frequency clock ESAI_RX_HF_CLK(ESAI_RX_HF_CLK pin) = receive high frequency clock 4 For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register. 5 The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync signal waveform, but it spreads from one serial clock before the first bit clock (like the bit length frame sync signal), until the second-to-last bit clock of the first word in the frame. 6 Periodically sampled and not 100% tested. Table 45. Enhanced Serial Audio Interface (ESAI) Timing (continued)

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Figure 35. ESAI Transmitter Timing

i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018 NXP Semiconductors 75 Figure 36. ESAI Receiver Timing

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4.12.4 Ultra High Speed SD/SDIO/MMC Host Interface (uSDHC)

This section describes the electrical information of the uSDHC, which includes SD/eMMC4.3 (Single Data Rate) timing and eMMC4.4/4.1 (Dual Date Rate) timing. 4.12.4.1 SD/eMMC4.3 (Singl e Data Rate) AC Timing Figure 37 depicts the timing of SD/eMMC4.3, and Table 46 lists the SD/eMMC4.3 timing characteristics. Figure 37. SD/eMMC4.3 Timing Table 46. SD/eMMC4.3 Interface Timing Specification

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4.12.4.3 SDR50/SDR104 AC Timing

Figure 39 depicts the timing of SDR50/SDR104, and Table 48 lists the SDR50/SDR104 timing characteristics. Figure 39. SDR50/SDR104 Timing Table 48. SDR50/SDR104 Interface Timing Specification 1Data window in SDR100 mode is variable.

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4.12.5 Ethernet Controller (ENET) AC Electrical Specifications

4.12.5.1 ENET MII Mode Timing

This subsection describes MII receive, transmit, asynchronous inputs, and serial management signal timings.

4.12.5.1.1 MII Receive Si gnal Timing (ENET_RX_DATA3,2,1,0, ENET_RX_EN,

ENET_RX_ER, and ENET_RX_CLK) The receiver functions correctly up to an ENET_RX_CLK maximum frequency of 25 MHz + 1%. There is no minimum frequency requirement. Additionally, the processor clock frequency must exceed twice the ENET_RX_CLK frequency. Figure 40 shows MII receive signal timings. Table 49 describes the timing parameters (M1–M4) shown in the figure. Figure 40. MII Receive Signal Timing Diagram 1 ENET_RX_EN, ENET_RX_CLK, and ENET0_RXD0 have the same timing in 10 Mbps 7-wire interface mode. Table 49. MII Receive Signal Timing

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4.12.5.1.2 MII Tra nsmit Signal Timing

(ENET_TX_DATA3,2,1,0, ENET_TX_EN, ENET_TX_ER, and ENET_TX_CLK) The transmitter functions correctly up to an ENET_TX_CLK maximum frequency of 25 MHz + 1%. There is no minimum frequency requirement. Additionally, the processor clock frequency must exceed twice the ENET_TX_CLK frequency. Figure 41 shows MII transmit signal timings. Table 50 describes the timing parameters (M5–M8) shown in the figure. Figure 41. MII Transmit Signal Timing Diagram 1 ENET_TX_EN, ENET_TX_CLK, and ENET0_TXD0 have the same timing in 10-Mbps 7-wire interface mode.

4.12.5.1.3 MII Asynchronous I nputs Signal Timing (ENET_CRS and ENET_COL)

Figure 42. MII Async Inputs Timing Diagram Table 50. MII Transmit Signal Timing

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4.12.5.1.4 MII Serial Management Cha nnel Timing (ENET_MDIO and ENET_MDC)

The MDC frequency is designed to be equal to or less than 2.5 MHz to be compatible with the IEEE 802.3 MII specification. However the ENET can function correctly with a maximum MDC frequency of 15 MHz. Figure 43 shows MII asynchronous input timings. Table 52 describes the timing parameters (M10–M15) shown in the figure. Figure 43. MII Serial Management Channel Timing Diagram Table 51. MII Asynchronous Inputs Signal Timing Table 52. MII Serial Management Channel Timing

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4.12.5.2 RMII Mode Timing

In RMII mode, ENET_CLK is used as the REF_CLK, which is a 50 MHz ± 50 ppm continuous reference clock. ENET_RX_EN is used as the ENET_RX_EN in RMII. Other signals under RMII mode include ENET_TX_EN, ENET0_TXD[1:0], ENET_RXD[1:0] and ENET_RX_ER. Figure 44 shows RMII mode timings. Table 53 describes the timing parameters (M16–M21) shown in the figure. Figure 44. RMII Mode Signal Timing Diagram Table 53. RMII Signal Timing

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4.12.5.3 RGMII Signal Switching Specifications

The following timing specifications meet the requirements for RGMII interfaces for a range of transceiver devices. Figure 45. RGMII Transmit Signal Timing Diagram Original Table 54. RGMII Signal Switching Specifications1

1 The timings assume the following configuration:

2 For 10 Mbps and 100 Mbps, Tcyc will scale to 400 ns ±40 ns and 40 ns ±4 ns respectively.

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Figure 46. RGMII Receive Signal Timing Diagram Original Figure 47. RGMII Receive Signal Timing Diagram with Internal Delay

4.12.6 Flexible Controller Area Ne twork (FlexCAN) AC Electrical

expose Tx and Rx pins; these ports are named FLEXCAN_TX and FLEXCAN_RX, respectively.

4.12.7 HDMI Module Timing Parameters

4.12.7.1 Latencies and Timing Information

PHY while operating with the slowest input reference clock supported (13.5 MHz) is 3.35 ms.

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4.12.7.2 Electrical Characteristics

The table below provides electrical characteristics for the HDMI 3D Tx PHY. The following three figures illustrate various definitions and measurement conditions specified in the table below. Figure 48. Driver Measuring Conditions Figure 49. Driver Definitions Figure 50. Source Termination Table 55. Electrical Characteristics

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4.12.8 Switching Characteristics

Table 56 describes switching characteristics for the HDMI 3D Tx PHY. Figure 51 to Figure 55 illustrate various parameters specified in table. NOTE All dynamic parameters related to the TMDS line drivers’ performance imply the use of assembly guidelines. RT Termination resistance — 45 50 55 Ω TMDS drivers DC specifications VOFF Single-ended standby voltage RT = 50 Ω For measurement conditions and definitions, see the first two figures above. Compliance point TP1 as defined in the HDMI specification, version 1.3a, section 4.2.4. avddtmds ± 10 mV mV VSWING Single-ended output swing voltage 400 — 600 mV VH Single-ended output high voltage For definition, see the second figure above. If attached sink supports TMDSCLK < or = 165 MHz avddtmds ± 10 mV mV If attached sink supports TMDSCLK >

165 MHz

– 200 mV — avddtmds + 10 mV mV VL Single-ended output low voltage For definition, see the second figure above. If attached sink supports TMDSCLK < or = 165 MHz avddtmds – 600 mV — avddtmds – 400mV mV If attached sink supports TMDSCLK > – 700 mV — avddtmds – 400 mV mV RTERM Differential source termination load (inside HDMI 3D Tx PHY) Although the HDMI 3D Tx PHY includes differential source termination, the user-defined value is set for each single line (for illustration, see the third figure above). Note: R TERM can also be configured to be open and not present on TMDS channels. — 50 — 200 Ω Hot plug detect specifications HPDVH Hot plug detect high range — 2.0 — 5.3 V VHPD VL Hot plug detect low range — 0 — 0.8 V HPD Z Hot plug detect input impedance — 10 — — k Ω HPD t Hot plug detect time delay — — — 100 µs Table 55. Electrical Characteristics (continued)

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Figure 54. Inter-Pair Skew Definition Figure 55. TMDS Output Signals Rise and Fall Time Definition Table 56. Switching Characteristics

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4.12.9 I 2C Module Timing Parameters

This section describes the timing parameters of the I2C module. Figure 56 depicts the timing of I2C module, and Table 57 lists the I2C module timing characteristics. Figure 56. I2C Bus Timing

2 HDMI 3D Tx PHY power-up time From power-down to

1 Relative to ideal recovery clock, as specified in the HDMI specification, version 1.4a, section 4.2.3. Table 57. I2C Module Timing Parameters Table 56. Switching Characteristics (continued)

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4.12.10 Image Processing Unit (IPU) Module Parameters

The purpose of the IPU is to provide comprehensive support for the flow of data from an image sensor and/or to a display device. This support covers all aspects of these activities:  Connectivity to relevant devices — cameras, displays, graphics accelerators, and TV encoders.  Related image processing and manipulation: sensor image signal processing, display processing, image conversions, and other related functions.  Synchronization and control cap abilities, such as avoidance of tearing artifacts. IC9 Bus free time between a STOP and START condition 4.7 — 1.3 — µs IC10 Rise time of both I2Cx_SDA and I2Cx_SCL signals — 1000 20 + 0.1C b 4 300 ns IC11 Fall time of both I2Cx_SDA and I2Cx_SCL signals — 300 20 + 0.1C b 4 300 ns IC12 Capacitive load for each bus line (C b) — 400 — 400 pF 1 A device must internally provide a hold time of at least 300 ns for I2Cx_SDA signal to bridge the undefined region of the falling edge of I2Cx_SCL. 2 The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC5) of the I2Cx_SCL signal. 3 A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement of Set-up time (ID No IC7) of 250 ns must be met. This automatically is the case if the device does not stretch the LOW period of the I2Cx_SCL signal. If such a device does stretch the LOW period of the I2Cx_SCL signal, it must output the next data bit to the I2Cx_SDA line max_rise_time (IC9) + data_setup_time (IC7) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the I2Cx_SCL line is released. 4 Cb = total capacitance of one bus line in pF. Table 57. I2C Module Timing Parameters (continued)

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4.12.10.1 IPU Sensor Interface Signal Mapping

The IPU supports a number of sensor input formats. Table 58 defines the mapping of the Sensor Interface Pins used for various supported interface formats. Table 58. Camera Input Signal Cross Reference, Format, and Bits Per Cycle 1 IPU2_CSIx stands for IPU2_CSI1 or IPU2_CSI2.

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4.12.10.2 Sensor Interface Timings

There are three camera timing modes supported by the IPU. Smart camera sensors, which include imaging processing, usually support video mode transfer. They use an embedded timing syntax to replace the IPU2_CSIx_VSYNC and IPU2_CSIx_HSYNC signals. The timing syntax is defined by the BT.656/BT.1120 standards. This operation mode follows the recommendations of ITU BT.656/ ITU BT.1120 specifications. The only control signal used is IPU2_CSIx_PIX_CLK. Start-of-frame and active-line signals are embedded in the data stream. An active line starts with a SAV code and ends with a EAV code. In some cases, digital blanking is inserted in between EAV and SAV code. The CSI decodes and filters out the timing-coding from the data stream, thus recovering IPU2_CSIx_VSYNC and IPU2_CSIx_HSYNC signals for internal use. On BT.656 one component per cycle is received over the IPU2_CSIx_DATA_EN bus. On BT.1120 two components per cycle are received over the IPU2_CSIx_DATA_EN bus.

4.12.10.2.2 Gated Clock Mode

The IPU2_CSIx_VSYNC, IPU2_CSIx_HSYNC, and IPU2_CSIx_PIX_CLK signals are used in this mode. See Figure 57. Figure 57. Gated Clock Mode Timing Diagram 2 The MSB bits are duplicated on LSB bits implementing color extension. 3 The two MSB bits are duplicated on LSB bits implementing color extension. 4 YCbCr, 8 bits—Supported within the BT.656 pr otocol (sync embedded within the data stream). processing, but only under some restrictions on the control protocol. 6 YCbCr, 16 bits—Supported as a “generic-d ata” input—with no on -the-fly processing. 7 YCbCr, 16 bits—Supported as a sub-case of the YCbCr, 20 bits, under the same conditions (BT.1120 protocol). 8 YCbCr, 20 bits—Supported only within the BT.1120 prot ocol (syncs embedded within the data stream).

i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018 NXP Semiconductors 93 stops receiving data from the stream. For the next line, the IPU2_CSIx_HSYNC timing repeats. For the next frame, the IPU2_CSIx_VSYNC timing repeats.

4.12.10.2.3 Non-Gated Clock Mode

The timing is the same as the gated-clock mode (described in Section 4.12.10.2.2, “Gated Clock Mode,”) except for the IPU2_CSIx_HSYNC signal, which is not used (see Figure 58). All incoming pixel clocks are valid and cause data to be latched into the input FIFO. The IPU2_CSIx_PIX_CLK signal is inactive (states low) until valid data is going to be transmitted over the bus. Figure 58. Non-Gated Clock Mode Timing Diagram

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4.12.10.3 Electrical Characteristics

Figure 59 depicts the sensor interface timing. IPU2_CSIx_PIX_CLK signal described here is not generated by the IPU. Table 59 lists the sensor interface timing characteristics. Figure 59. Sensor Interface Timing Diagram

4.12.10.4 IPU Display Interface Signal Mapping

Interface Pins used during various supported video interface formats. Table 59. Sensor Interface Timing Characteristics Table 60. Video Signal Cross-Reference

24 Bit

i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018 NXP Semiconductors 95 IPUx_DISPx_DAT05 DAT[5] G[0] B[5] B[5] Y/C[5] C[5] C[5] — IPUx_DISPx_DAT06 DAT[6] G[1] G[0] B[6] Y/C[6] C[6] C[6] — IPUx_DISPx_DAT07 DAT[7] G[2] G[1] B[7] Y/C[7] C[7] C[7] — IPUx_DISPx_DAT08 DAT[8] G[3] G[2] G[0] — Y[0] C[8] — IPUx_DISPx_DAT09 DAT[9] G[4] G[3] G[1] — Y[1] C[9] — IPUx_DISPx_DAT10 DAT[10] G[5] G[4] G[2] — Y[2] Y[0] — IPUx_DISPx_DAT11 DAT[11] R [0] G[5] G[3] — Y[3] Y[1] — IPUx_DISPx_DAT12 DAT[12] R [1] R[0] G[4] — Y[4] Y[2] — IPUx_DISPx_DAT13 DAT[13] R [2] R[1] G[5] — Y[5] Y[3] — IPUx_DISPx_DAT14 DAT[14] R [3] R[2] G[6] — Y[6] Y[4] — IPUx_DISPx_DAT15 DAT[15] R [4] R[3] G[7] — Y[7] Y[5] — IPUx_DISPx_DAT16 DAT[16] — R[4] R[0] — — Y[6] — IPUx_DISPx_DAT17 DAT[17] — R[5] R[1] — — Y[7] — IPUx_DISPx_DAT18 DAT[18] — — R[2] — — Y[8] — IPUx_DISPx_DAT19 DAT[19] — — R[3] — — Y[9] — IPUx_DISPx_DAT20 DAT[20] — — R[4] — — — — IPUx_DISPx_DAT21 DAT[21] — — R[5] — — — — IPUx_DISPx_DAT22 DAT[22] — — R[6] — — — — IPUx_DISPx_DAT23 DAT[23] — — R[7] — — — — IPUx_DIx_DISP_CLK PixCLK — IPUx_DIx_PIN01 — May be required for anti-tearing IPUx_DIx_PIN02 HSYNC — IPUx_DIx_PIN03 VSYNC VSYNC out Table 60. Video Signal Cross-Reference (continued)

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Table 60 provides information for both the DISP0 and DISP1 ports. However, DISP1 port has reduced pinout depending on IOMUXC configuration and therefore may not support all configurations. See the IOMUXC table for details.

4.12.10.5 IPU Display Interface Timing

The IPU Display Interface supports two kinds of display accesses: synchronous and asynchronous. There are two groups of external interface pins to provide synchronous and asynchronous controls.

4.12.10.5.1 Synchronous Controls

The synchronous control changes its value as a function of a system or of an external clock. This control has a permanent period and a permanent waveform. IPUx_DIx_PIN04 — Additional frame/row synchronous signals with programmable timingIPUx_DIx_PIN05 — IPUx_DIx_PIN06 — IPUx_DIx_PIN07 — IPUx_DIx_PIN08 — IPUx_DIx_D1_CS — Alternate mode of PWM output for contrast or brightness control IPUx_DIx_PIN11 — — IPUx_DIx_PIN12 — — IPUx_DIx_PIN13 — Register select signal IPUx_DIx_PIN14 — Optional RS2 IPUx_DIx_PIN15 DRDY/DV Data validation/blank, data enable IPUx_DIx_PIN16 — Additional data synchronous signals with programmable features/timing IPUx_DIx_PIN17 Q 1 Signal mapping (both data and control/synchronization) is flexible. The table provides examples.

2 Restrictions for ports IPUx_DISPx_DAT00 through IPUx_DISPx_DAT23 are as follows:

 A maximum of three continuous groups of bits can be independently mapped to the external bus. Groups must not overlap.  The bit order is expressed in each of the bit groups, for example, B[0] = least significant blue pixel bit. 3 This mode works in compliance with recommendation ITU-R BT.656. The timing reference signals (frame start, frame end, line start, and line end) are embedded in the 8-bit data bus. Only video data is supported, transmission of non-video related data during blanking intervals is not supported.

i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018 NXP Semiconductors 97 There are special physical outputs to provide synchronous controls:  The ipp_disp_clk is a dedicated base synchronous signal that is used to generate a base display (component, pixel) clock for a display.  The ipp_pin_1– ipp_pin_7 are general purpose synchr onous pins, that can be used to provide HSYNC, VSYNC, DRDY or any else independent signal to a display. The IPU has a system of internal binding counters for internal events (such as, HSYNC/VSYNC) calculation. The internal event (local start point) is synchronized with internal DI_CLK. A suitable control starts from the local start point with predefined UP and DOWN values to calculate control’s changing points with half DI_CLK resolution. A full description of the counter system can be found in the IPU chapter of the i.MX 6Dual/6Quad reference manual (IMX6DQRM).

4.12.10.5.2 Asynchronous Controls

The asynchronous control is a data-oriented signal that changes its value with an output data according to additional internal flags coming with the data. There are special physical outputs to provide asynchronous controls, as follows:  The ipp_d0_cs and ipp_d1_cs pins are dedicated to provide chip select signals to two displays.  The ipp_pin_11– ipp_pin_17 are genera l purpose asynchronous pins, that can be used to provide WR. RD, RS or any other data-oriented signal to display. NOTE The IPU has independent signal generators for asynchronous signals toggling. When a DI decides to put a new asynchronous data on the bus, a new internal start (local start point) is generated. The signal generators calculate predefined UP and DOWN values to change pins states with half DI_CLK resolution.

4.12.10.6 Synchronous Interfaces to St andard Active Matrix TFT LCD Panels

4.12.10.6.1 IPU Display Operating Signals

The IPU uses four control signals and data to operate a standard synchronous interface:  IPP_DISP_CLK—Clock to display  HSYNC—Horizontal synchronization  VSYNC—Vertical synchronization  DRDY—Active data All synchronous display controls are generated on the base of an internally generated “local start point”. The synchronous display controls can be placed on time axis with DI’s offset, up and down parameters. The display access can be whole number of DI clock (Tdiclk) only. The IPP_DATA can not be moved relative to the local start point. The data bus of the synchronous interface is output direction only.

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4.12.10.6.2 LCD Interfac e Functional Description

Figure 60 depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure, signals are shown with negative polarity. The sequence of events for active matrix interface timing is:  DI_CLK internal DI clock is used for calculation of other controls.  IPP_DISP_CLK latches data into the panel on its ne gative edge (when positive polarity is selected). In active mode, IPP_DISP_CLK runs continuously.  HSYNC causes the panel to start a new line. (U sually IPUx_DIx_PIN02 is used as HSYNC.)  VSYNC causes the panel to start a new frame. It always encompasses at least one HSYNC pulse. (Usually IPUx_DIx_PIN03 is used as VSYNC.)  DRDY acts like an output enable signal to the CR T display. This output enables the data to be shifted onto the display. When disabled, the data is invalid and the trace is off. (DRDY can be used either synchronous or asynchronous generic purpose pin as well.) Figure 60. Interface Timing Diagram for TFT (Active Matrix) Panels

4.12.10.6.3 TFT Panel Sync Pulse Timing Diagrams

the IPP_DISP_CLK signal and active-low polarity of the HSYNC, VSYNC, and DRDY signals.

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Table 61 shows timing characteristics of signals presented in Figure 61 and Figure 62. Table 61. Synchronous Display Interface Timing Characteristics (Pixel Level) components in one pixel (1.n). FW—with of active line in interface clocks. be built by suitable DI’s counter.

i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018 NXP Semiconductors 101 The maximum accuracy of UP/DOWN edge of controls is: The maximum accuracy of UP/DOWN edge of IPP_DISP_DATA is: The DISP_CLK_PERIOD, DI_CLK_PERIOD parameters are register-controlled. IP5o Offset of IPP_DISP_CLK Todicp DISP_CLK_OFFSET × Tdiclk DISP_CLK_OFFSET—offset of IPP_DISP_CLK edges from local start point, in DI_CLK×2 (0.5 DI_CLK Resolution). Defined by DISP_CLK counter. ns IP13o Offset of VSYNC Tovs VSYNC_OFFSET × Tdiclk VSYNC_OFFSET—offset of Vsync edges from a local start point, when a Vsync should be active, in DI_CLK×2 (0.5 DI_CLK Resolution). The VSYNC_OFFSET should be built by suitable DI’s counter. ns IP8o Offset of HSYNC Tohs HSYNC_OFFSET × Tdiclk HSYNC_OFFSET—offset of Hsync edges from a local start point, when a Hsync should be active, in DI_CLK (0.5 DI_CLK Resolution). The HSYNC_OFFSET should be built by suitable DI’s counter. ns IP9o Offset of DRDY Todrdy DRDY_OFFSET × Tdiclk DRDY_OFFSET—offset of DRDY edges from a suitable local start point, when a corresponding data has been set on the bus, in DI_CLK (0.5 DI_CLK Resolution). The DRDY_OFFSET should be built by suitable DI’s counter. ns 1 Display interface clock period immediate value. DISP_CLK_PERIOD—number of DI_CLK per one Tdicp. Resolution 1/16 of DI_CLK. DI_CLK_PERIOD—relation of between programing cl ock frequency and current system clock frequency Display interface clock period average value. 2 DI’s counter can define offset, period and UP/DOWN characteristic of output signal according to programed parameters of the counter. Same of parameters in the table are not defined by DI’s registers directly (by name), but can be generated by corresponding DI’s counter. The SCREEN_WIDTH is an input value for DI’s HSYNC generation counter. The distance between HSYNCs is a SCREEN_WIDTH. Table 61. Synchronous Display Interface Timing Characteristics (Pixel Level) (continued)

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Figure 63 depicts the synchronous display interface timing for access level. The DISP_CLK_DOWN and DISP_CLK_UP parameters are register-controlled. Table 62 lists the synchronous display interface timing characteristics. Figure 63. Synchronous Display Interface Timing Diagram—Access Level Table 62. Synchronous Display Interface Timing Characteristics (Access Level) 1The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display. These conditions may be chip specific.

2 Display interface clock down time

3 Display interface clock up time where CEIL(X) rounds the elements of X to the nearest integers towards infinity.

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4.12.11 LVDS Display Bridge (LDB) Module Parameters

The LVDS interface complies with TIA/EIA 644-A standard. For more details, see TIA/EIA STANDARD 644-A, “Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits.”

4.12.12 MIPI D-PHY Timing Parameters

This section describes MIPI D-PHY electrical specifications, compliant with MIPI CSI-2 version 1.0, D-PHY specification Rev. 1.0 (for MIPI sensor port x4 lanes) and MIPI DSI Version 1.01, and D-PHY MIPI display port x2 lanes).

4.12.12.1 Electrical and Timing Information

Table 63. LVDS Display Bridge (LDB) Electrical Specification voltage measured between the 2 resistors. Table 64. Electrical and Timing Information

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HS Line Drivers DC Specifications |VOD| HS Transmit Differential output voltage magnitude 80 Ω<= RL< = 125 Ω 140 200 270 mV Δ|VOD| Change in Differential output voltage magnitude between logic states 80 Ω<= RL< = 125 Ω —— 1 0m V V CMTX Steady-state common-mode output voltage. 80 Ω<= RL< = 125 Ω 150 200 250 mV ΔVCMTX(1,0) Changes in steady-state common-mode output voltage between logic states 80 Ω<= RL< = 125 Ω —— 5 m V V OHHS HS output high voltage 80 Ω<= RL< = 125 Ω ——3 6 0 m V ZOS Single-ended output impedance. — 40 50 62.5 Ω ΔZOS Single-ended output impedance mismatch. —— — 1 0 % LP Line Drivers DC Specifications VOL Output low-level SE voltage — -50 50 mV VOH Output high-level SE voltage — 1.1 1.2 1.3 V ZOLP Single-ended output impedance. — 110 — — Ω ΔZOLP(01-10) Single-ended output impedance mismatch driving opposite level —— — 2 0 % ΔZOLP(0-11) Single-ended output impedance mismatch driving same level —— — 5 % HS Line Receiver DC Specifications V IDTH Differential input high voltage threshold —— — 7 0 m V VIDTL Differential input low voltage threshold —- 7 0 — — m V VIHHS Single ended input high voltage —— — 4 6 0 m V VILHS Single ended input low voltage —- 4 0 — — m V VCMRXDC Input common mode voltage — 70 — 330 mV ZID Differential input impedance — 80 — 125 Ω Table 64. Electrical and Timing Information (continued)

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4.12.12.2 D-PHY Signaling Levels

The signal levels are different for differential HS mode and single-ended LP mode. Figure 64 shows both the HS and LP signal levels on the left and right sides, respectively. The HS signaling levels are below the LP low-level input threshold such that LP receiver always detects low on HS signals. Figure 64. D-PHY Signaling Levels

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4.12.12.3 HS Line Driver Characteristics

Figure 65. Ideal Single-ended and Resulting Differential HS Signals

4.12.12.4 Possible ΔVCMTX and ΔVOD Distortions of the Single-ended HS Signals

Figure 66. Possible ΔVCMTX and ΔVOD Distortions of the Single-ended HS Signals

4.12.12.5 D-PHY Switching Characteristics

Table 65. Electrical and Timing Information

i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018 NXP Semiconductors 107 tCDC DDR CLK duty cycle t CDC = tCPH / PDDRCLK —5 0 —% tCPH DDR CLK high time — — 1 — UI tCPL DDR CLK low time — — 1 — UI — DDR CLK / DATA Jitter — — 75 — ps pk-pk t SKEW[PN] Intra-Pair (Pulse) skew — — 0.075 — UI tSKEW[TX] Data to Clock Skew — 0.350 — 0.650 UI tr Differential output signal rise time 20% to 80%, RL = 50 Ω 150 — 0.3UI ps tf Differential output signal fall time 20% to 80%, RL = 50 Ω 150 — 0.3UI ps ΔVCMTX(HF) Common level variation above 450 MHz 80 Ω<= RL< = 125 Ω —— 1 5 m V rms ΔVCMTX(LF) Common level variation between 50 MHz and 450 MHz 80 Ω<= RL< = 125 Ω —— 2 5 m V p LP Line Drivers AC Specifications trlp,tflp Single ended output rise/fall time 15% to 85%, C L<70 pF — — 25 ns treo — 30% to 85%, C L<70 pF — — 35 ns δV/δtSR Signal slew rate 15% to 85%, C L<70 pF — — 120 mV/ns CL Load capacitance — 0 — 70 pF HS Line Receiver AC Specifications tSETUP[RX] Data to Clock Receiver Setup time — 0.15 — — UI tHOLD[RX] Clock to Data Receiver Hold time — 0.15 — — UI ΔVCMRX(HF) Common mode interference beyond

450 MHz

— — — 200 mVpp ΔVCMRX(LF) Common mode interference between

50 MHz and 450 MHz

—- 5 0 — 5 0 m V p p CCM Common mode termination — — — 60 pF LP Line Receiver AC Specifications eSPIKE Input pulse rejection — — — 300 Vps TMIN Minimum pulse response — 50 — — ns VINT Pk-to-Pk interference voltage — — — 400 mV fINT Interference frequency — 450 — — MHz Model Parameters used for Driver Load switching performance evaluation CPAD Equivalent Single ended I/O PAD capacitance. —— — 1 p F CPIN Equivalent Single ended Package + PCB capacitance. —— — 2 p F Table 65. Electrical and Timing Information (continued)

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4.12.12.6 High-Speed Clock Timing

Figure 67. DDR Clock Definition

4.12.12.7 Forward High-Spee d Data Transmission Timing

Figure 68. Data to Clock Timing Definitions

4.12.12.8 Reverse High-Speed Data Transmission Timing

Figure 69. Reverse High-Speed Data Transmission Timing at Slave Side

1 Data Bit Time = 1UI

1 DDR Clock Period = UIINST(1) + UIINST(2)

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4.12.12.9 Low-Power Receiver Timing

Figure 70. Input Glitch Rejection of Low-Power Receivers

4.12.13 HSI Host Controller Timing Parameters

High-Speed Synchronous Serial Interface (HSI) Physical Layer specification version 1.01.

4.12.13.1 Synchronous Data Flow

Figure 71. Synchronized Data Flow READY Signal Timing (Frame and Stream Transmission)

4.12.13.2 Pipelined Data Flow

Figure 72. Pipelined Data Flow READY Signal Timing (Frame Transmission Mode)

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4.12.13.3 Receiver Real-Time Data Flow

Figure 73. Receiver Real-Time Data Flow READY Signal Timing

4.12.13.4 Synchronized Data Flow Transmission with Wake

Figure 74. Synchronized Data Flow Transmission with WAKE

4.12.13.5 Stream Transmission Mode Frame Transfer

Figure 75. Stream Transmission Mode Frame Transfer (Synchronized Data Flow)

Description

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4.12.13.6 Frame Transmission M ode (Synchronized Data Flow)

Figure 76. Frame Transmission Mode Transfer of Two Frames (Synchronized Data Flow)

4.12.13.7 Frame Transmission Mode (Pipelined Data Flow)

Figure 77. Frame Transmission Mode Transfer of Two Frames (Pipelined Data Flow)

4.12.13.8 DATA and FLAG Signal Timi ng Requirement for a 15 pF Load

Table 66. DATA and FLAG Timing including all timing defects, for example, jitter and skew, inside the transmitter. including all timing defects, for example, jitter and skew, inside the receiver. Complete N-bits Frame Complete N-bits Frame DATA FLAG READY Channel

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4.12.13.9 DATA and FLAG Signal Timing

Figure 78. DATA and FLAG Signal Timing

4.12.14 PCIe PHY Parameters

4.12.14.1 PCIE_REXT Refere nce Resistor Connection

on PCIE_REXT pads to ground. It is used for termination impedance calibration.

4.12.15 Pulse Width Modulator (PWM) Timing Parameters

Figure 79 depicts the timing of the PWM, and Table 67 lists the PWM timing parameters. Figure 79. PWM Timing Table 67. PWM Output Timing Parameters

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4.12.16 SATA PHY Parameters

This section describes SATA PHY electrical specifications.

4.12.16.1 Transmitter and Receiver Characteristics

The SATA PHY meets or exceeds the electrical compliance requirements defined in the SATA specifications. NOTE The tables in the following sections indicate any exceptions to the SATA specification or aspects of the SATA PHY that exceed the standard, as well as provide information about parameters not defined in the standard. The following subsections provide values obtained from a combination of simulations and silicon characterization.

4.12.16.1.1 SATA PHY Tra nsmitter Characteristics

Table 68 provides specifications for SATA PHY transmitter characteristics.

4.12.16.1.2 SATA PHY R eceiver Characteristics

Table 69 provides specifications for SATA PHY receiver characteristics.

4.12.16.2 SATA_REXT Refere nce Resistor Connection

The impedance calibration process requires connection of reference resistor 191 Ω. 1% precision resistor on SATA_REXT pad to ground. Resistor calibration consists of learning which state of the internal Resistor Calibration register causes an internal, digitally trimmed calibration resistor to best match the impedance applied to the SATA_REXT pin. The calibration register value is then supplied to all Tx and Rx termination resistors. During the calibration process (for a few tens of microseconds), up to 0.3 mW can be dissipated in the external SATA_REXT resistor. At other times, no power is dissipated by the SATA_REXT resistor. Table 68. SATA PHY Transmitter Characteristics Table 69. SATA PHY Receiver Characteristics

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4.12.17 SCAN JTAG Controlle r (SJC) Timing Parameters

Figure 80 depicts the SJC test clock input timing. Figure 81 depicts the SJC boundary scan timing. Figure 82 depicts the SJC test access port. Figure 83 depicts the JTAG_TRST_B timing. Signal parameters are listed in Table 70. Figure 80. Test Clock Input Timing Diagram Figure 81. Boundary Scan (JTAG) Timing Diagram

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4.12.18 SPDIF Timing Parameters

The Sony/Philips Digital Interconnect Format (SPDIF) data is sent using the bi-phase marking code. When encoding, the SPDIF data signal is modulated by a clock that is twice the bit rate of the data signal. Table 71 and Figure 84 and Figure 85 show SPDIF timing parameters for the Sony/Philips Digital Interconnect Format (SPDIF), including the timing of the modulating Rx clock (SPDIF_SR_CLK) for SPDIF in Rx mode and the timing of the modulating Tx clock (SPDIF_ST_CLK) for SPDIF in Tx mode. SJ9 JTAG_TMS, JTAG_TDI data hold time 25 — ns SJ10 JTAG_TCK low to JT AG_TDO data valid — 44 ns SJ11 JTAG_TCK low to JTAG _TDO high impedance — 44 ns SJ12 JTAG_TRST_B assert time 100 — ns SJ13 JTAG_TRST_B set-up time to JTAG_TCK low 40 — ns

1 TDC = target frequency of SJC

2 VM = mid-point voltage

Table 71. SPDIF Timing Parameters Table 70. JTAG Timing (continued)

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4.12.19 SSI Timing Parameters

synchronous interfaces are summarized in Table 72. Length (WL) and Bit Length (BL). Table 72. AUDMUX Port Allocation

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4.12.19.1 SSI Transmitter Timing with Internal Clock

Figure 86 depicts the SSI transmitter internal clock timing and Table 73 lists the timing parameters for the SSI transmitter internal clock. Figure 86. SSI Transmitter Internal Clock Timing Diagram Table 73. SSI Transmitter Timing with Internal Clock

i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018 NXP Semiconductors 119 NOTE  All the timings for the SSI are gi ven for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal AUDx_TXC/AUDx_RXC and/or the frame sync AUDx_TXFS/AUDx_RXFS shown in the tables and in the figures.  All timings are on Audiomux Pads wh en SSI is being used for data transfer.  The terms, WL and BL, refer to Word Length(WL) and Bit Length(BL).  For internal Frame Sync operation us ing external clock, the frame sync timing is the same as that of transmit data (for example, during AC97 mode of operation). Synchronous Internal Clock Operation SS42 AUDx_RXD setup before AUDx_TXC falling 10.0 — ns SS43 AUDx_RXD hold after AUDx_TXC falling 0.0 — ns Table 73. SSI Transmitter Timing with Internal Clock (continued)

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4.12.19.2 SSI Receiver Timing with Internal Clock

Figure 87 depicts the SSI receiver internal clock timing and Table 74 lists the timing parameters for the receiver timing with the internal clock. Figure 87. SSI Receiver Internal Clock Timing Diagram Table 74. SSI Receiver Timing with Internal Clock

i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018 NXP Semiconductors 121 NOTE  All the timings for the SSI are gi ven for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal AUDx_TXC/AUDx_RXC and/or the frame sync AUDx_TXFS/AUDx_RXFS shown in the tables and in the figures.  All timings are on Audiomux Pads wh en SSI is being used for data transfer.  AUDx_TXC and AUDx_RXC refer to the Transmit and Receive sections of the SSI.  The terms, WL and BL, refer to Wo rd Length (WL) and Bit Length(BL).  For internal Frame Sync operation us ing external clock, the frame sync timing is same as that of transmit data (for example, during AC97 mode of operation). Oversampling Clock Operation SS47 Oversampling clock period 15.04 — ns SS48 Oversampling clock high period 6.0 — ns SS49 Oversampling clock rise time — 3.0 ns SS50 Oversampling clock low period 6.0 — ns SS51 Oversampling clock fall time — 3.0 ns Table 74. SSI Receiver Timing with Internal Clock (continued)

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4.12.19.3 SSI Transmitter Timing with External Clock

Figure 88 depicts the SSI transmitter external clock timing and Table 75 lists the timing parameters for the transmitter timing with the external clock. Figure 88. SSI Transmitter External Clock Timing Diagram Table 75. SSI Transmitter Timing with External Clock

i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018 NXP Semiconductors 123 NOTE  All the timings for the SSI are gi ven for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal AUDx_TXC/AUDx_RXC and/or the frame sync AUDx_TXFS/AUDx_RXFS shown in the tables and in the figures.  All timings are on Audiomux Pads wh en SSI is being used for data transfer.  AUDx_TXC and AUDx_RXC refer to the Transmit and Receive sections of the SSI.  The terms WL and BL refer to Word Length (WL) and Bit Length (BL).  For internal Frame Sync operation us ing external clock, the frame sync timing is same as that of transmit data (for example, during AC97 mode of operation).

4.12.19.4 SSI Receiver Timing with External Clock

Figure 89 depicts the SSI receiver external clock timing and Table 76 lists the timing parameters for the receiver timing with the external clock. Figure 89. SSI Receiver External Clock Timing Diagram Table 75. SSI Transmitter Timing with External Clock (continued)

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 All the timings for the SSI are gi ven for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal AUDx_TXC/AUDx_RXC and/or the frame sync AUDx_TXFS/AUDx_RXFS shown in the tables and in the figures.  All timings are on Audiomux Pads wh en SSI is being used for data transfer.  AUDx_TXC and AUDx_RXC refer to the Transmit and Receive sections of the SSI.  The terms, WL and BL, refer to Wo rd Length (WL) and Bit Length(BL).  For internal Frame Sync operation us ing external clock, the frame sync timing is same as that of transmit data (for example, during AC97 mode of operation). Table 76. SSI Receiver Timing with External Clock

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4.12.20 UART I/O Configuration and Timing Parameters

4.12.20.1 UART RS-232 I/O Config uration in Different Modes

The i.MX 6Dual/6Quad UART interfaces can serve both as DTE or DCE device. This can be configured by the DCEDTE control bit (default 0 – DCE mode). Table 77 shows the UART I/O configuration based on the enabled mode. Table 77. UART I/O Configuration vs. Mode

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4.12.20.2 UART RS-232 Serial Mode Timing

The following sections describe the electrical information of the UART module in the RS-232 mode.

4.12.20.2.1 UART Transmitter

Figure 90 depicts the transmit timing of UART in the RS-232 serial mode, with 8 data bit/1 stop bit format. Table 78 lists the UART RS-232 serial mode transmit timing characteristics. Figure 90. UART RS-232 Serial Mode Transmit Timing Diagram

4.12.20.2.2 UART Receiver

serial mode receive timing characteristics. Figure 91. UART RS-232 Serial Mode Receive Timing Diagram Table 78. RS-232 Serial Mode Transmit Timing Parameters 1 Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16. 2 Tref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider). Table 79. RS-232 Serial Mode Receive Timing Parameters 2 Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.

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4.12.20.2.3 UART IrDA Mode Timing

The following subsections give the UART transmit and receive timings in IrDA mode. UART IrDA Mode Transmitter Figure 92 depicts the UART IrDA mode transmit timing, with 8 data bit/1 stop bit format. Table 80 lists the transmit timing characteristics. Figure 92. UART IrDA Mode Transmit Timing Diagram the receive timing characteristics. Figure 93. UART IrDA Mode Receive Timing Diagram Table 80. IrDA Mode Transmit Timing Parameters 1 Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16. 2 Tref_clk: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider). Table 81. IrDA Mode Receive Timing Parameters 2 Fbaud_rate: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.

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4.12.21 USB HSIC Timings

This section describes the electrical information of the USB HSIC port. NOTE HSIC is a DDR signal. The following timing specification is for both rising and falling edges.

4.12.21.1 Transmit Timing

Figure 94. USB HSIC Transmit Waveform

4.12.21.2 Receive Timing

Figure 95. USB HSIC Receive Waveform Table 82. USB HSIC Transmit Parameters Table 83. USB HSIC Receive Parameters1

1 The timings in the table are guaranteed when:

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4.12.22 USB PHY Parameters

This section describes the USB-OTG PHY and the USB Host port PHY parameters. The USB PHY meets the electrical compliance requirements defined in the Universal Serial Bus Revision

2.0 OTG, USB Host with the amendments below (On-The-Go and Embedded Host Supplement to the USB

Revision 2.0 Specification is not applicable to Host port).  USB ENGINEERIN G CHANGE NOTICE — Title: 5V Short Circuit Withstand Requirement Change — Applies to: Universal Serial Bus Specification, Revision 2.0  Errata for USB Revision 2.0 April 27, 2000 as of 12/7/2000  USB ENGINEERIN G CHANGE NOTICE — Title: Pull-up/Pull-down resistors — Applies to: Universal Serial Bus Specification, Revision 2.0  USB ENGINEERIN G CHANGE NOTICE — Title: Suspend Current Limit Changes — Applies to: Universal Serial Bus Specification, Revision 2.0  USB ENGINEERIN G CHANGE NOTICE — Title: USB 2.0 Phase Locked SOFs — Applies to: Universal Serial Bus Specification, Revision 2.0  On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification — Revision 2.0 plus erra ta and ecn June 4, 2010  Battery Charging Specificati on (available from USB-IF) — Revision 1.2, December 7, 2010 — Portable device only

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5 Boot Mode Configuration

5.1 Boot Mode Configuration Pins

sampled at reset and can be used to override fuse values, depending on the value of BT_FUSE_SEL fuse. Table 84. Fuses and Associated Pins Used for Boot

5.2 Boot Devices Interfaces Allocation

which are configured during boot when appropriate. the boot configuration can be controlled by fuses. Table 85. Interfaces Allocation During Boot Table 84. Fuses and Associated Pins Used for Boot (continued)

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Table 85. Interfaces Allocation During Boot (continued)

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6 Package Information and Contact Assignments

This section includes the contact assignment information and mechanical package drawing.

6.1 Signal Naming Convention

The signal names of the i.MX6 series of products are standardized to align the signal names within the family and across the documentation. Benefits of this standardization are as follows:  Signal names are unique within the scope of an SoC and within the series of products  Searches will return all o ccurrences of the named signal  Signal names are consistent between i.MX 6 series products implementing the same modules  The module instance is incorporated into the signal name This standardization applies only to signal names. The ball names are preserved to prevent the need to change schematics, BSDL models, IBIS models, and so on. Throughout this document, the signal names are used except where referenced as a ball name (such as the Functional Contact Assignments table, Ball Map table, and so on). A master list of signal names is in the document, IMX 6 Series Standardized Signal Name Map (EB792). This list can be used to map the signal names used in older documentation to the standardized naming conventions. 6.2 21 x 21 mm Package Information 6.2.1 Case FCPBGA, 21 x 21 mm, 0.8 mm Pitch, 25 x 25 Ball Matrix

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Figure 96 and Figure 97 show the top, bottom, and side views of the 21 × 21 mm lidded package. Figure 96. 21 x 21 mm Lidded Package Top, Bottom, and Side Views (Sheet 1 of 2)

Figure 97. 21 x 21 mm Lidded Package Top, Bottom, and Side Views (Sheet 2 of 2)

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Table 86 shows the device connection list for ground, power, sense, and reference contact signals. Table 86. 21 x 21 mm Supplies Contact Assignment

Table 86. 21 x 21 mm Supplies Contact Assignment (continued)

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includes out of reset pad state.

Table 87. 21 x 21 mm Functional Contact Assignments (continued)

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3 V22 NVCC_ENET GPIO ALT5 GP IO1_IO23 Input PU (100K)

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1 The state immediately after reset and before ROM firmware or software has executed.

2 Variance of the pull-up and pull-down strengths are shown in the tables as follows:

 Table 21, “GPIO I/O DC Parameters,” on page 37.  Table 23, “LPDDR2 I/O DC Electrical Parameters,” on page 39.  Table 24, “DDR3/DDR3L I/O DC Electrical Parameters,” on page 40. Development Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors (IMX6DQ6SDLHDG).

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6.2.4 Signals with Different Reset States

reset are given in Table 88. Table 88. Signals with Differing Before Reset and After Reset States

Table 88. Signals with Differing Before Reset and After Reset States (continued)

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Table 89 shows the FCPBGA 21 x 21 mm, 0.8 mm pitch ball map. Table 89. 21 x 21 mm, 0.8 mm Pitch Ball Map

Table 89. 21 x 21 mm, 0.8 mm Pitch Ball Map (continued)

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1 MLB is only supported in automotive and consumer graded parts. These balls are not connected in industrial graded parts.

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Revision History

7 Revision History

Table 90 provides a revision history for the i.MX 6Dual/6Quad data sheet. Table 90. i.MX 6Dual/6Quad Data Sheet Document Revision History

i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018 NXP Semiconductors 157 5 09/2017 Rev. 5 changes include the following:  Changed throughout: – Changed terminology from “floating” to “not connected”. – Removed VADC feature from 19mm x 19mm package. Contact NXP sales and marketing with enablement options.  Section 1, “Introduction” on page 1: Corrected A9 core speed from 1 GHz to 800 MHz.  Section 1.2, “Features” on page 4: Changed Internal/external peripheral item from “LVDS serial ports— One port up to 165 MPixels/sec…” to: “…—One port up to 170 MPixels/sec…”.  Table 1, “Example Orderable Part Numbers”: Added part numbers for silicon revision 1.4 with suffix “E”.  Section 1.3, “Signal Naming Convention” on page 7” and Section 6.1, “Signal Naming Convention”: changed wording from updated or changed signal naming, to standard signal naming.  Table 2, “i.MX 6Dual/6Quad Modules List,” on page 9: – Added bullet to uSDHC row: “Conforms to the SD Host Controller Standard Specification v3.0”  Section 4, “Electrical Characteristics” on page 18: Changed several references from JESD and JEDEC standards to cross references to the Section 4.10, “Multi-Mode DDR Controller (MMDC).  Table 4, “Absolute Maximum Ratings,” on page 19: Multiple changes: – Core supply voltages: Separated rows by LDO enabled and LDO bypass. For LDO enabled, changed maximum value from 1.5 to 1.6V. – Renamed Internal supply voltages to Core supply output voltage (LDO enabled) and changed maximum value from 1.3 to 1.4V. Added symbol NVCC_PLL_OUT. – Reordered VDD_HIGH_IN row and changed maximum value from 3.6 to 3.7V. – DDR I/O supply voltage row changes: — Changed Symbols from “Supplies denoted as I/O supply” to: “NVCC_DRAM” — Added footnote. – GPIO I/O supply voltage: Added symbols. Changed maximum value from 3.6 to 3.7V. – Resequenced: HDMI, PCIe, and SATA PHY high (VPH) supply voltage to precede low (VP) – Added row: RGMII I/O supply voltage – Added row, Vin/Vout input/output voltage range (non-DDR pins) distinguishing between DDR pins. – Changed maximum value for Vin/Vout input/output voltage range DDR pins to OVDD+0.4. – Added footnotes to both maximum values of Vin/Vout input/output voltage range. – Added row: USB_OTG_CHD_B  Section 4.1.2, “Thermal Resistance” on page 20: Added NOTE: “Per JEDEC JESD51-2, the intent of thermal resistance measurements…”.  Section 4.1.5, “Maximum Measured Supply Currents” on page 24: Clarified language throughout this section regarding the use case to estimate the maximum supply current.  Section 4.2.1, “Power-Up Sequence” on page 31: – Removed content about calculating the proper current limiting resistor for a coin cell. – Removed inference to internal POR.  Section 4.5.2, “OSC32K” on page 35: Removed content about calculating the proper current limiting resistor for a coin cell.  Section 4.6.1, “XTALI and RTC_XTALI (Clock Inputs) DC Parameters” on page 37: – Added “NOTE: The Vil and Vih specifications only apply when an external clock source is used…”. (Revision History table continues on next page.) Table 90. i.MX 6Dual/6Quad Data Sheet Document Revision History (continued)

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(Cont.) 09/2017  Table 20, “XTALI and RTC_XTALI DC Parameters,” on page 37: – Added footnote to RTC_XTALI high level DC input voltage row: “This voltage specification must not be exceeded and …”. Section 4.6.4, “RGMII I/O 2.5V I/O DC Electrical Parameters” on page 38: Added section and table.  Section 4.10, “Multi-Mode DDR Controller (MMDC)” on page 60: Replaced section with new content. Was: 4.9.4 “DDR SDRAM Specific Parameters (DDR3/DDR3L/LPDDR2)” with timing diagrams and parameter tables for DDR3/DDR3L/LPDDR2.  Table 47, “eMMC4.4/4.41 Interface Timing Specification,” on page 77, – Corrected SD3, uSDHC Input Setup Time, minimum value from 2.6ns to 1.7ns. – Added footnote to Card Input Clock regarding duty cycle range.  Table 48, “SDR50/SDR104 Interface Timing Specification,” on page 78: Changes to Min/Max values: – SD2 min from: 0.3 x tCLK; to: 0.46 x tCLK – SD2 max from: 0.7 x tCLK to: 0.54 x tCLK – SD3 min from: 0.3 x tCLK; to: 0.46 x tCLK. Also corrected ID from duplicate SD2 to SD3. – SD3 max from: 0.7 x tCLK; to: 0.54 x tCLK – SD5 max from: 1 ns; to: 0.74 ns  Table 58, “Camera Input Signal Cross Reference, Format, and Bits Per Cycle,” on page 91: Changed RGB565, 16 bits column heading from 2 cycles to 1 cycle.  Table 59, “Sensor Interface Timing Characteristics,” on page 94, Sensor Interface Timing characteristics: Added rows to include Vsync values.  Table 86, “21 x 21 mm Supplies Contact Assignment,” on page 136: Added description to ZQPAD.  Table 87, “21 x 21 mm Functional Contact Assignments,” on page 138: – Changed rows DRAM_SDCLK_0 and DRAM_SDCLK_1, Out of Reset Conditions from “Input–Hi-Z” to “Output–0”. – Added description to GPANAIO row: “…output for NXP use only…” (Revision History table continues on next page.)

i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018 NXP Semiconductors 159 4 07/2015  Added footnote to Table 1, “Example Orderable Part Numbers,” on page 3: If a 24 MHz input clock is used (required for USB), the maximum SoC speed is limited to 996 MHz.  Section 1.2, “Features” changed Five UARTs, from up to 4.0 Mbps, to up to 5.0 Mbps.  Table 6, “Operating Ranges,” on page 21, Row: run mode: LDO bypassed, removed LDO bypassed for operation up to 852 MHz.  Table 6, “Operating Ranges,” on page 21: Row: VDD_HIGH internal regulator, changed minimum parameter value from 2.8 to 2.7V.  Table 6, “Operating Ranges,” on page 21: Removed footnote: VDDSOC and VDDPU output voltages must be set according to this rule: VDDARM-VDDSOC/PU<50mV. This was a duplicate footnote, renumbered footnotes accordingly.  Table 6, “Operating Ranges,” on page 21: Changed value: Standby/DSM Mode, VDD_SOC_IN, minimum voltage, from 0.9V to 1.05V.  Table 8, “Maximum Supply Currents,” on page 25, Differentiated VDD_ARM_IN, VDD_ARM23_IN, and VDD_SOC_IN by frequency and by Power Virus/CoreMark maximum current.  Table 20, “XTALI and RTC_XTALI DC Parameters,” on page 37, Added rows: Input capacitance; Startup current; and DC input current and their values.  Table 37, “EIM Bus Timing Parameters,” on page 51, Changed WE4–WE17 minimum and maximum  Table 38, “EIM Asynchronous Timing Parameters Relative to Chip Select,,” on page 58 Added to end of formulas in the minimum, typical, and maximum parameter values for WE31–WE42 and WE45–WE46, × t. For example from 3-CSN, to 3-CSN× t. Also added maximum value to MAXDTI of 10.  Table 58, “DDR3/DDR3L Write Cycle,” on page 90, Changed minimum parameter value of DDR17 from 240 to 125; and of DDR18 from 240 to 150.  Figure 29, “LPDDR2 Command and Address Timing Diagram,” on page 91, LP2 signal cycle reduced.  Table 62, “LPDDR2 Write Cycle,” on page 93, Changed LP21 minimum and maximum parameter value  Figure 33, "ECSPI Master Mode Timing Diagram," on page 70, Added footnote: Note: ECSPIx_MOSI is always driven (not tri-stated) between actual data transmissions. This limits the ECSPI to be connected between a single master and a single slave.  Figure 34, "ECSPI Slave Mode Timing Diagram," on page 71, Added footnote: Note: ECSPIx_MISO is always driven (not tri-stated) between actual data transmissions. This limits the ECSPI to be connected between a single master and a single slave.  Figure 57, "Gated Clock Mode Timing Diagram," on page 92, Corrected IPU2_CSIx_HSYNC trace drawing.  Section 4.12.22, “USB PHY Parameters” Specified Battery Charging Specification applies to portable devices only. (Revision History table continues on next page.)

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Rev. 3 02/2014  Updates throughout for Silicon revision D, include: - Figure 1 Part number nomenclature diagram. - Example Orderable Part Number tables, Table 1  Feature description for Miscellaneous IPs and interfaces; SSI and ESAI.  Table 6, UART 1–5 description change: programmable baud rate up to 5 MHz.  Table 6, uSDHC 1–4 description change: including SDXC cards up to 2 TB.  Table 6, operating range for Run mode: LDO bypassed, minimum value corrected to 1.150 V.  Table 6, table footnotes, added LDO enabled m ode footnote for internal LDO output set points.  Table 61, added table footnote to the Comment heading in the Comment column.  Removed table “On-Chip LDOs and their On-Chip Loads.”  Section 4.1.4, External Clock Sources; added Note, “The internal RTC oscillator does not …”.  Section 4.1.5, reworded second paragraph about the power management IC to explain that a robust thermal design is required for the increased system power dissipation.  Table 8, Maximum Supply Currents: NVCC_RGMII Condition value changed to N=6.  Table 8, Maximum Supply currents: Added row; NVCC_LVDS2P5  Section 4.2.1 Power-Up Sequence: reworded third bulleted item regarding POR control.  Section 4.2.1 Power-Up Sequence: removed Note.  Section 4.5.2 OSC32K, second paragraph reworded to describe OSC32K automatic switching.  Section 4.5.2 OSC32K, added Note following second paragraph to caution use of internal oscillator use.  Table 20 XTALI and RTC_XTALI DC parameters; changed RTC_XTALI Vih minimum value to 0.8.  Table 20 XTALI and RTC_XTALI DC parameters; changed RTC_XTALI Vih maximum value to 1.1.  Table 34 Reset Timing Parameters; removed footnote.  Section 4.9.3 External Interface Module; enhanced wording to first paragraph to describe operating frequency for data transfers, and to explain register settings are valid for entire range of frequencies.  Table 37. EIM Bus Timing Parameters; reworded footnotes for clarity.  Table 38. EIM Asynchronous Timing Parameters; removed comment from the Max heading cell.  Table 38. EIM Asynchronous Timing Parameters; reworded footnote 2 for clarity.  Table 53. RMII Signal Timing; parameter M19 Max value relaxed to 13.5 ns.  Table 95. Corrected the ALT5 Default Function names.  Figure 96 and Figure 97 21 x 21 mm Lidded Package; updated drawing (Rev D). Rev. 2.3 07/26 /2013  Table 95, 21 x 21Functional Contact Assignments: Restored NANDF_WP_B row and description.  System Timing Parameters Table 34, Reset timing parameter, CC1 description clarified, change from: “Duration of SRC_POR_B to be qualified as valid (input slope <= 5 ns)” to: “Duration of SRC_POR_B to be qualified as valid” and added a footnote to the parameter with the following text: “SRC_POR_B rise and fall times must be 5 ns or less.” This change was made for clarity and does not represent a specification change. Rev. 2.2 07/2013  Editor corrections to revision history links. No technical content changes. Rev. 2.1 07/2013  Figure 1, Changed temperature references from Consumer to Commercial.  Table 95, 21 x 21Functional Contact Assignments: —Removed rows: DRAM_VREF, HDMI_DDCCEC, and HDMI_REF. —Due to a typographical error in revision 2.0, the ball names for rows EIM_DA2 through EIM_DA15 were ordered incorrectly. This has been corrected in revision 2.1. The ball map is correct in both revision 2.0 and 2.1. (Revision History table continues on next page.)

i.MX 6Dual/6Quad Applications Processors for Industrial Products, Rev. 6, 11/2018 NXP Semiconductors 161 Rev. 2 04/2013 Substantive changes thro ughout this document are as follows:  Incorporated standardized signal names. This change is extensive throughout. Added reference to EB792, i.MX Signal Name Mapping.  Figures updated to align to standardized signal names.  Aligned references to FCBGA to read FC PBGA throughout document.  Updated references to eMMC standard to include 4.41.  Table 1 “Example Industrial Grade Orderable Part Numbers”: Part Numbers MCIMX6Q4AVT10AC, MCIMX6Q4AVT08AC, MCIMX6D4AVT10AC, and MCIMX6D4AVT08AC were updated to show GPU instead of VPU as an option.  Table 2, “i.MX 6Dual/6Quad Modules List,” Changed reference to Global Power Controller to read General Power Controller.  Table 4, “Absolute Maximum Ratings,” Added VDD_ARM23_IN to Core supply voltages.  Table 6 “Operating Ranges”: Run Mode - LDO Enabled, VDD_ARM_IN/VDD_ARM23_IN, 792 MHz, input voltage minimum changed to 1.275V and VDD_ARM CAP minimum changed to 1.150V. NVCC_NAND, changed to NVCC_NANDF.  Table 6 “Operating Ranges”: Added reference for information on product lifetime: i.MX 6Dual/6Quad Product Usage Lifetime Estimates Application Note, AN4724.  Table 9. “Maximum Supply Currents”: Added current for i.MX6Dual  Table 10 “Stop Mode Current and Power Consumption”: Added SNVS Only mode.  Table 22 “GPIO I/O DC Parameters”: Removed parameters Iskod and Isspp.  Table 48, “ECSPI Master Mode Timing Parameters,” Updated parameter CS6 ECSPIx_SSx Lag Time (CS hold time) Min from Half SCLK period to Half SCLK period-2.  Table 77 “SD/eMMC4.3 Interface Timing Specification,” eMMC parameter SD8 value Min updated from 5.6 ns to 1.5 ns.  Table 89 RGMII Signal Switching Specifications RGMII parameter TskewR units corrected.  Table 134 “21 x 21 mm Functional Contact Assignments,” Updated GPIO_1 Ball Name value to PU (100K).  Table 134 “21 x 21 mm Functional Contact Assignments,” Clarification of ENET_REF_CLK naming.  Removed section, EIM Signal Cross Reference. Signal names are now aligned with reference manual.  Section 1.2, “Features added bulleted item regarding the SOC-level memory system.  Section 4.2.1, “Power-Up Sequence” updated wording.  Section 4.3.2, “Regulators for Analog Modules”: Added NVCC_PLL_OUT to section heading.  Section 4.6.1, “XTALI and RTC_XTALI (Clock Inputs) DC Parameters”: Added section.  Section 4.10, “General-Purpose Media Interface (GPMI) Timing” figures replaced, tables revised.

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