PCI1225GHK

PCI1225 TI | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 131

Technical content

SCPS035B – MAY 1998 – REVISED – MAY 2000 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI Bus Power Management Interface Specification 1.0 Compliant ACPI 1.0 Compliant Fully Compatible With the Intel 430TX (Mobile Triton II) Chipset Packaged in a 208-Pin Low-Profile QFP (PDV) or GHK High Density Ball Grid Array (BGA) PCI Local Bus Specification Revision 2.2 Compliant

1997 PC Card Standard Compliant

3.3-V Core Logic With Universal PCI Interfaces Compatible With 3.3-V and 5-V PCI Signaling Environments Mix-and-Match 5-V/3.3-V 16-bit PC Cards and 3.3-V CardBus Cards Supports Two PC Card or CardBus Slots With Hot Insertion and Removal Uses Serial Interface to TI TPS2202/2206 Dual-Slot PC Card Power Switch Supports Burst Transfers to Maximize Data Throughput on the PCI Bus and CardBus Bus Supports Parallel PCI Interrupts, Parallel ISA IRQ and Parallel PCI Interrupts, Serial ISA IRQ With Parallel PCI Interrupts, and Serial ISA IRQ and PCI Interrupts Serial EEPROM Interface for Loading Subsystem ID and Subsystem Vendor ID Pipelined Architecture Allows Greater Than 130-MBps Throughput From CardBus-to-PCI and From PCI-to-CardBus Supports up to Five General-Purpose I/Os Programmable Output Select for CLKRUN Multifunction PCI Device With Separate Configuration Space for Each Socket Five PCI Memory Windows and Two I/O Windows Available for Each R2 Socket Two I/O Windows and Two Memory Windows Available to Each CardBus Socket Exchangeable Card Architecture (ExCA) Compatible Regesters Are Mapped in Memory and I/O Space Intel 82365SL-DF Register Compatible Supports Distributed DMA (DDMA) and PC/PCI DMA Supports 16-Bit DMA on Both PC Card Sockets Supports Ring Indicate, SUSPEND, PCI CLKRUN, and CardBus CCLKRUN LED Activity Pins Supports PCI Bus Lock (LOCK) Advanced Submicron, Low-Power CMOS Technology Table of Contents Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2000, Texas Instruments Incorporated Intel is a trademark of Intel Corporation. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

SCPS035B – MAY 1998 – REVISED – MAY 2000

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description

The TI PCI1225 is a high-performance PCI-to-PC Card controller that supports two independent card sockets compliant with the 1997 PC Card Standard. The PCI1225 provides a rich feature set that makes it the best choice for bridging between PCI and PC Cards in both notebook and desktop computers. The 1997 PC Card Standard retains the 16-bit PC Card specification defined in PCMCIA Release 2.2 and defines the new 32-bit PC Card (CardBus), capable of full 32-bit data transfers at 33 MHz. The PCI1225 supports any combination of 16-bit and CardBus PC Cards in the two sockets, powered at 5 V or 3.3 V, as required. The PCI1225 is compliant with the PCI Local Bus Specification 2.2, and its PCI interface can act as either a PCI master device or a PCI slave device. The PCI bus mastering is initiated during 16-bit PC Card DMA transfers or CardBus PC Card bridging transactions. The PCI1225 is also compliant with the latest PCI Bus Power Management Interface Specification. All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI1225 is register compatible with the Intel 82365SL-DF ExCA controller. The PCI1225 internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent buffering and a pipeline architacture provide an unsurpassed performance level with sustained bursting. The PCI1225 can also be programmed to accept fast posted writes to improve system-bus utilization. Multiple system-interrupt signaling options are provided, including: parallel PCI, parallel ISA, serialized ISA, and serialized PCI. Furthermore, general-purpose inputs and outputs are provided for the board designer to implement sideband functions. Many other features designed into the PCI1225, such as socket activity light-emitting diode (LED) outputs, are discussed in detail throughout the design specification. An advanced complementary metal-oxide semiconductor (CMOS) process is used to achieve low system-power consumption while operating at PCI clock rates up to 33 MHz. Several low-power modes enable the host power management system to further reduce power consumption. Unused PCI1225 inputs must be pulled up using a 43-k resistor.

SCPS035B – MAY 1998 – REVISED – MAY 2000 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 system block diagram A simplified block diagram of the PCI1225 is provided below. The PCI interface includes all address/data and control signals for PCI protocol. The interrupt interface includes terminals for parallel PCI, parallel ISA, and serialized PCI and ISA signaling. Miscellaneous system interface terminals include multifunction terminals: SUSPEND , RI_OUT/PME (power management control signal), and SPKROUT. PCI Bus PCI1225 Activity LEDs PCI950 IRQSER Deserializer IRQSER Interrupt Controller INTA INTB IRQ2–15 PCI930 ZV Switch23 PC Card Socket A TPS2206 Power Switch 3 PC Card Socket B External ZV Port VGA Controller Audio Subsystem Zoom Video Zoom Video NOTE: The PC Card interface is 68 pins for CardBus and 16-bit PC Cards. In zoomed-video mode 23 pins are used for routing the zoomed video signals to the VGA controller and audio subsystem. 68 68

SCPS035B – MAY 1998 – REVISED – MAY 2000

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

B_CCLKRUN A_CAD25 A_CAD13 A_CAD0 B_CAD9 B_CAD1 B_CCD1 AD4 AD17 CCP AD10 AD9 AD8 AD7 AD6 AD5 AD3 GND AD1 AD0 B_CAD0 B_CAD2 B_CAD4 B_CAD3 GND B_CAD6 B_CAD5 B_RSVD B_CAD7 B_CC/BE0 B_CAD10 B_CAD11 B_CAD14 B_CAD12 B_CAD15 B_CAD16 B_CPAR B_CPERR GND B_CSTOP B_CGNT B_CIRDY B_CDEVSEL B_CCLK B_CTRDY B_CFRAME B_CC/BE2 AD2 B_CAD8 B_CAD13 B_CC/BE1 B_RSVD B_CBLOCK MFUNC2 C/BE3 RI_OUT/PME AD25 GND REQ PRST AD11 AD31 AD30 AD29 AD28 AD27 AD24 PCLK GND IDSEL AD22 AD20 AD26 AD23 AD16 FRAME GND IRDY DEVSEL PERR SERR PAR AD15 AD14 AD13 GND AD12 A_CC/BE1 A_CAD16 A_CAD14 A_CAD12 A_CAD11 A_CAD10 GND A_CAD7 A_CAD9 A_CC/BE0 A_CAD8 A_RSVD A_CAD5 A_CAD6 A_CAD4 A_CAD1 A_CAD2 A_CCD1 B_CAD31 B_RSVD B_CAD30 B_CAD29 B_CAD28 B_CAD27 GND B_CCD2 B_CSTSCHG B_CAUDIO B_CVS1 B_CAD26 B_CAD25 B_CSERR B_CC/BE3 B_CAD24 V B_CAD23 B_CREQ B_CAD22 B_CAD21 B_CRST B_CAD20 B_CVS2 B_CAD19 B_CAD18 B_CAD17 158 157 160 159 162 161 164 163 166 165 168 167 170 169 172 171 174 173 176 175 178 177 180 179 182 181 184 183 186 185 188 187 190 189 192 191 194 193 196 195 198 197 200 199 202 201 204 203 206 205 208 207 103 104 101 102 100 A_CAD3 B_CINT A_CAD15 51 106 105 108 107 110 109 112 111 114 113 116 115 118 117 120 119 122 121 124 123 126 125 128 127 130 129 132 131 134 133 136 135 138 137 140 139 142 141 144 143 146 145 148 147 150 149 152 151 154 153 156 155 SUSPEND GND MFUNC0 DATA SPKROUT LATCH CLOCK A_CAD31 VCCI A_CAD30 A_RSVD A_CAD28 A_CAD29 A_CCD2 A_CAD27 A_CCLKRUN A_CAUDIO A_CSTSCHG A_CINT A_CSERR A_CAD26 A_CVS1 A_CC/BE3 A_CAD24 A_CAD23 GND A_CAD21 A_CAD22 A_CREQ A_CAD20 A_CRST A_CAD19 A_CVS2 A_CAD18 A_CFRAME A_CC/BE2 A_CTRDY A_CIRDY A_CCLK V A_CDEVSEL A_CAD17 A_CSTOP A_CGNT A_CBLOCK A_CPERR A_RSVD A_CPAR GNT AD21 AD19 AD18 TRDY STOP PCI-to-CardBus Terminal Diagram V C/BE0 CCV CCV CCBV CC VCC CC VCCA VCC MFUNC1 MFUNC3 MFUNC4 MFUNC5 MFUNC6 VCC VCC VCC C/BE2 VCC C/BE1 CCPV Card A Card B PCI1225 CorePCI PDV LOW-PROFILE QUAD FLAT PACKAGE TOP VIEW

SCPS035B – MAY 1998 – REVISED – MAY 2000 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 terminal assignments (continued) C/BE1 B_CD1 A_A1 A_D3 B_A10 B_D4 AD4 AD18 CCP AD10 AD9 AD8 AD7 AD6 AD5 AD3 GND AD1 AD0 B_D3 B_D11 B_D12 B_D5 GND B_D13 B_D6 B_D14 B_D7 B_CE1 B_A9 B_A11 B_A17 B_A13 B_A14 GND B_A20 B_WE B_A15 B_A21 B_A16 B_A22 B_A23 B_A12 AD2 B_D15 B_A8 B_A18 B_A19 MFUNC2 AD26 C/BE3 AD28 GND PRST GNT REQ AD31 AD30 AD11 AD27 PCLK GND AD24 AD23 AD21 AD29 IDSEL AD17 FRAME GND IRDY DEVSEL PERR SERR PAR AD15 AD14 AD13 GND AD12 A_A8 A_A17 A_A9 A_A11 GND A_D7 A_A10 A_D15 A_D14 A_D6 A_D13 A_D12 A_D4 A_D11 A_CD1 B_D10 B_D2 B_D9 B_D1 B_D8 B_D0 GND B_CD2 B_WP(IOIS16) B_BVD1(STSCHG/RI) B_VS1 B_A0 B_A1 B_WAIT B_REG B_A2 V B_A3 B_INPACK B_A4 B_A5 B_RESET B_A6 B_A25 B_A7 B_A24 158 157 160 159 162 161 164 163 166 165 168 167 170 169 172 171 174 173 176 175 178 177 180 179 182 181 184 183 186 185 188 187 190 189 192 191 194 193 196 195 198 197 200 199 202 201 204 203 206 205 208 207 103 104 101 102 100 A_D5 B_READY(IREQ) A_IOWR 51 106 105 108 107 110 109 112 111 114 113 116 115 118 117 120 119 122 121 124 123 126 125 128 127 130 129 132 131 134 133 136 135 138 137 140 139 142 141 144 143 146 145 148 147 150 149 152 151 154 153 156 155 SPKROUT GND MFUNC0 DATA LATCH CLOCK A_D10 A_D9 A_D2 A_D8 A_D1 A_CD2 A_D0 A_WP(IOIS16) A_BVD1(STSCHG/RI) A_READY(IREQ) A_WAIT A_A0 A_VS1 A_REG A_A2 A_A3 GND A_A5 A_A4 A_INPACK A_A6 A_RESET A_A25 A_VS2 A_A7 A_A23 A_A12 A_A22 A_A15 A_A16 V A_A21 A_A24 A_A20 A_WE A_A19 A_A14 A_A18 A_A13 AD25 AD22 AD20 AD19 TRDY STOP PCI-to-PC Card (16-Bit) Terminal Diagram V C/BE0 CCV CCV CCBV CC VCC CC VCCA VCC MFUNC1 MFUNC3 MFUNC4 MFUNC5 MFUNC6 VCC VCC VCC AD16 VCC CCPV B_CE2 B_OE B_IORD B_IOWR A_IORD A_OE A_CE2 A_CE1 B_BVD2(SPKR) B_VS2 VCCI A_BVD2(SPKR) Card A Card B PCI1225 CorePCI SUSPEND RI_OUT/PME C/BE2 PDV LOW-PROFILE QUAD FLAT PACKAGE TOP VIEW

SCPS035B – MAY 1998 – REVISED – MAY 2000

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

terminal assignments (continued) 1917 1511 81 0 V U R N P L M K T H F G E C D A B J W GHK PLASTIC BALL GRID ARRAY BOTTOM VIEW signal names and terminal assignments Table 1 and Table 2 show the terminal assignments for the CardBus PC Card; Table 3 and Table 4 show the terminal assignments for the 16-bit PC Card; Table 1 and Table 3 show the CardBus PC Card and the 16-bit PC Card terminals sorted alphanumerically by the associated GHK package terminal number; and Table 2 and Table 4 show the CardBus PC Card and the 16-bit PC Card terminals sorted alphanumerically by the signal name and its associated terminal numbers.

Table 1. CardBus PC Card Signal Names by GHK/PDV Terminal Number

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Table 2. CardBus PC Card Signal Names Sorted Alphabetically

Table 3. 16-Bit PC Card Signal Names by GHK/PDV Terminal Number

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Table 3. 16-Bit PC Card Signal Names by GHK/PDV Terminal Number (Continued) Table 4. 16-Bit PC Card Signal Names Sorted Alphabetically SIGNAL NAME TERMINAL NO. SIGNAL NAME TERMINAL NO. SIGNAL NAME TERMINAL NO.

Table 4. 16-Bit PC Card Signal Names Sorted Alphabetically (Continued)

SCPS035B – MAY 1998 – REVISED – MAY 2000

12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

The terminals are grouped in tables by functionality, such as PCI system function, power-supply function, etc. The terminal numbers are also listed for convenient reference. power supply TERMINAL FUNCTIONNAME PDV NUMBER GHK NUMBER FUNCTION GND 13, 22, 44, 75, 96, 129, 153, 167, 181, 194, 207 G2, J5, P2, P9, V14, K18, E18, F12, B10, E8, C5 Device ground terminals VCC 7, 31, 64, 86, 113, 143, 164, 175, 187, 201 F3, L3, U7, W12, N15, G19, B14, A11, C9, E7 Power supply terminal for core logic (3.3 V) VCCA 120 M17 Rail voltage for PC Card A interface. Indicates Card A signaling environment (5 V or 3.3 V) VCCB 38 M5 Rail voltage for PC Card B interface. Indicates Card B signaling environment (5 V or 3.3 V) VCCI 148 F18 Rail voltage for interrupt subsystem interface and miscellaneous I/O (5 V or 3.3 V) VCCP 1, 178 D1, E11 Rail voltage for PCI signaling (5 V or 3.3 V) PC Card power switch TERMINAL I/O NAME NUMBER I/O TYPE FUNCTIONNAME PDV GHK TYPE FUNCTION CLOCK 151 E19 I/O Three-line power switch clock. Information on the DATA line is sampled at the rising edge of CLOCK. CLOCK defaults to an input, but can be changed to a PCI1225 output by using the P2CCLK bit in the system control register. The TPS2206 defines the maximum frequency of this signal to be 2 MHz. If a system design defines this terminal as an output, then this terminal requires an external pull down resistor. The frequency of the PCI1225 output CLOCK is derived from dividing the PCI CLK by 36. DATA 152 F14 O Three-line power switch data. DATA is used to serially communicate socket power control information to the power switch. LATCH 150 F17 O Three-line power switch latch. LATCH is asserted by the PCI1225 to indicate to the PC Card power switch that the data on the DATA line is valid. When a pulldown resistor is implemented on this terminal, the MFUNC4 and MFUNC1 terminals provide the serial EEPROM SCL and SDA interface. PCI system TERMINAL I/O NAME NUMBER I/O TYPE FUNCTIONNAME PDV GHK TYPE FUNCTION PCLK 180 A10 I PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled at the rising edge of PCLK. PRST 166 A14 I PCI reset. When the PCI bus reset is asserted, PRST causes the PCI1225 to place all output buffers in a high-impedance state and reset all internal registers. When PRST is asserted, the device is completely nonfunctional. After PRST is deasserted, the PCI1225 is in its default state. When SUSPEND and PRST are asserted, the device is protected from PRST clearing the internal registers. All outputs are placed in a high-impedance state, but the contents of the registers are preserved.

SCPS035B – MAY 1998 – REVISED – MAY 2000 13POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) PCI address and data TERMINAL NAME NUMBER I/O TYPE FUNCTIONNAME PDV GHK TYPE AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 170 171 173 174 176 177 165 179 183 184 185 186 188 189 190 191 204 205 206 208 172 A13 E12 B12 A12 B11 C11 E13 F11 E10 F10 C12 I/O PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the primary interface. During the address phase of a primary bus PCI cycle, AD31–AD0 contain a 32-bit address or other destination information. During the data phase, AD31–AD0 contain data. C/BE3 C/BE2 C/BE1 C/BE0 162 192 203 A15 I/O PCI bus commands and byte enables. These signals are multiplexed on the same PCI terminals. During the address phase of a primary bus PCI cycle, C/BE3 –C/BE0 define the bus command. During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit data bus carry meaningful data. C/BE0 applies to byte 0 (AD7–AD0), C/BE1 applies to byte 1 (AD15–AD8), C/BE2 applies to byte 2 (AD23–AD16), and C/BE3 applies to byte 3 (AD31–AD24). PAR 202 C6 I/O PCI bus parity. In all PCI bus read and write cycles, the PCI1225 calculates even parity across the AD31–AD0 and C/BE3 –C/BE0 buses. As an initiator during PCI cycles, the PCI1225 outputs this parity indicator with a one-PCLK delay. As a target during PCI cycles, the calculated parity is compared to the initiator parity indicator. A compare error results in the assertion of a parity error (PERR).

SCPS035B – MAY 1998 – REVISED – MAY 2000

14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions (Continued) PCI interface control TERMINAL NAME NUMBER I/O TYPE FUNCTIONNAME PDV GHK TYPE DEVSEL 197 C7 I/O PCI device select. The PCI1225 asserts DEVSEL to claim a PCI cycle as the target device. As a PCI initiator on the bus, the PCI1225 monitors DEVSEL until a target responds. If no target responds before timeout occurs, the PCI1225 terminates the cycle with an initiator abort. FRAME 193 F8 I/O PCI cycle frame. FRAME is driven by the initiator of a bus cycle. FRAME is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. When FRAME is deasserted, the PCI bus transaction is in the final data phase. GNT 168 C13 I PCI bus grant. GNT is driven by the PCI bus arbiter to grant the PCI1225 access to the PCI bus after the current data transaction has completed. GNT may or may not follow a PCI bus request, depending on the PCI bus parking algorithm. IDSEL 182 C10 I Initialization device select. IDSEL selects the PCI1225 during configuration space accesses. IDSEL can be connected to one of the upper 24 PCI address lines on the PCI bus. IRDY 195 A7 I/O PCI initiator ready. IRDY indicates the PCI bus initiator’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of PCLK where both IRDY and TRDY are asserted. Until IRDY and TRDY are both sampled asserted, wait states are inserted. PERR 199 A6 I/O PCI parity error indicator. PERR is driven by a PCI device to indicate that calculated parity does not match PAR when PERR is enabled through bit 6 of the command register. REQ 169 B13 O PCI bus request. REQ is asserted by the PCI1225 to request access to the PCI bus as an initiator. SERR 200 B6 O PCI system error. SERR is an output that is pulsed from the PCI1225 when enabled through the command register indicating a system error has occurred. The PCI1225 need not be the target of the PCI cycle to assert this signal. When SERR is enabled in the control register, this signal also pulses, indicating that an address parity error has occurred on a CardBus interface. STOP 198 F7 I/O PCI cycle stop signal. STOP is driven by a PCI target to request the initiator to stop the current PCI bus transaction. STOP is used for target disconnects and is commonly asserted by target devices that do not support burst data transfers. TRDY 196 B7 I/O PCI target ready. TRDY indicates the primary bus target’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of PCLK when both IRDY and TRDY are asserted. Until both IRDY and TRDY are asserted, wait states are inserted.

SCPS035B – MAY 1998 – REVISED – MAY 2000 15POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) multifunction and miscellaneous terminals TERMINAL I/O NAME NUMBER I/O TYPE FUNCTION NAME PDV GHK TYPE MFUNC0 154 F15 I/O Multifunction terminal 0. MFUNC0 can be configured as parallel PCI interrupt INTA, GPI0, GPO0, socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE, or a parallel IRQ. See the multifunction routing register description on page 64 for configuration details. MFUNC1 155 E17 I/O Multifunction terminal 1. MFUNC1 can be configured as parallel PCI interrupt INTB, GPI1, GPO1, socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE, or a parallel IRQ. See the multifunction routing register description on page 64 for configuration details. Serial data (SDA). When the serial bus mode is implemented by pulling the LATCH terminal low, the MFUNC1 terminal provides the SDA signaling. The two-terminal serial interface is used to load the subsystem identification and other register defaults from an EEPROM after a PCI reset. See the serial bus interface implementation description on page 31 for details on other serial bus applications. MFUNC2 157 A16 I/O Multifunction terminal 2. MFUNC2 can be configured as PC/PCI DMA request, GPI2, GPO2, socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE , or a parallel IRQ. See the multifunction routing register description on page 64 for configuration details. MFUNC3 158 C15 I/O Multifunction terminal 3. MFUNC3 can be configured as a parallel IRQ or the serialized interrupt signal IRQSER. See the multifunction routing register description on page 64 for configuration details. MFUNC4 159 E14 I/O Multifunction terminal 4. MFUNC4 can be configured as PCI LOCK, GPI3, GPO3, socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE, or a parallel IRQ. See the multifunction routing register description on page 64 for configuration details. Serial clock (SCL). When the serial bus mode is implemented by pulling the LATCH terminal low, the MFUNC4 terminal provides the SCL signaling. The two-terminal serial interface is used to load the subsystem identification and other register defaults from an EEPROM after a PCI reset. See the serial bus interface implementation description on page 31 for details on other serial bus applications. MFUNC5 160 F13 I/O Multifunction terminal 5. MFUNC5 can be configured as PC/PCI DMA grant GPI4, GPO4, socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE , or a parallel IRQ. See the multifunction routing register description on page 64 for configuration details. MFUNC6 161 B15 I/O Multifunction terminal 6. MFUNC6 can be configured as a PCI CLKRUN or a parallel IRQ. See the multifunction routing register description on page 64 for configuration details. RI_OUT /PME 163 C14 O Ring indicate out and power management event output. Terminal provides an output for ring-indicate or PME signals. SPKROUT 149 G15 O Speaker output. SPKROUT is the output to the host system that can carry SPKR or CAUDIO through the PCI1225 from the PC Card interface. SPKROUT is driven as the exclusive-OR combination of card SPKR//CAUDIO inputs. SUSPEND 156 D19 I Suspend. SUSPEND is used to protect the internal registers from clearing when the PRST signal is asserted. See suspend mode description on page 42 for details.

SCPS035B – MAY 1998 – REVISED – MAY 2000

16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions (Continued) 16-bit PC Card address and data (slots A and B) TERMINAL NUMBER I/O FUNCTION NAME SLOT A † SLOT B ‡ I/O TYPE FUNCTION NAME PDV GHK PDV GHK A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 121 118 116 114 111 109 107 105 103 112 115 108 106 117 100 102 104 119 123 125 126 128 131 132 133 M18 N19 N17 P19 P17 R18 P15 T19 U15 P18 M14 N14 R17 N18 P14 W14 R14 W16 M15 L19 L17 L15 K19 K15 K14 J19 O PC Card address. 16-bit PC Card address lines. A25 is the most-significant bit. D15 D14 D13 D12 D11 D10 147 145 142 146 144 141 U13 W13 P12 V12 P11 F19 G17 H15 V13 R12 U12 R11 U11 G14 G18 H14 W11 R10 V10 P10 U10 W10 I/O PC Card data. 16-bit PC Card data lines. D15 is the most-significant bit. † Terminal name for slot A is preceded with A_. For example, the full name for terminals 121 and M18 is A_A25. ‡ Terminal name for slot B is preceded with B_. For example, the full name for terminals 55 and R6 is B_A25.

SCPS035B – MAY 1998 – REVISED – MAY 2000 17POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) 16-bit PC Card interface control (slots A and B) TERMINAL NUMBER I/O FUNCTIONNAME SLOT A † SLOT B ‡ I/O TYPE FUNCTIONNAME PDV GHK PDV GHK BVD1 (STSCHG /RI) 138 H19 72 V9 I Battery voltage detect 1. BVD1 is generated by 16-bit memory PC Cards that include batteries. BVD1 is used with BVD2 as an indication of the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are kept high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and should be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost. See ExCA card status-change interrupt configuration register on page 92 for enable bits. See ExCA card status-change register on page 91 and the ExCA interface status register on page 88 for the status bits for this signal. Status change. STSCHG is used to alert the system to a change in the READY, write protect, or battery voltage detect condition of a 16-bit I/O PC Card. Ring indicate. RI is used by 16-bit modem cards to indicate a ring detection. BVD2 (SPKR ) 137 J15 71 W9 I Battery voltage detect 2. BVD2 is generated by 16-bit memory PC Cards that include batteries. BVD2 is used with BVD1 as an indication of the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and should be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost. See ExCA card status-change interrupt configuration register on page 92 for enable bits. See ExCA card status-change register on page 91 and the ExCA interface status register on page 88 for the status bits for this signal. Speaker. SPKR is an optional binary audio signal available only when the card and socket have been configured for the 16-bit I/O interface. The audio signals from cards A and B are combined by the PCI1225 and are output on SPKROUT. DMA request. BVD2 can be used as the DMA request signal during DMA operations to a 16-bit PC Card that supports DMA. The PC Card asserts BVD2 to indicate a request for a DMA operation. CD1 CD2 140 V11 H17 I PC Card detect 1 and PC Card detect 2. CD1 and CD2 are internally connected to ground on the PC Card. When a PC Card is inserted into a socket, CD1 and CD2 are pulled low. For signal status, see interface status register on page 88. CE1 CE2 P13 R13 L2 O Card enable 1 and card enable 2. CE1 and CE2 enable even- and odd-numbered address bytes. CE1 enables even-numbered address bytes, and CE2 enables odd-numbered address bytes. INPACK 127 L14 61 R7 I Input acknowledge. INPACK is asserted by the PC Card when it can respond to an I/O read cycle at the current address. DMA request. INPACK can be used as the DMA request signal during DMA operations from a 16-bit PC Card that supports DMA. If used as a strobe, the PC Card asserts this signal to indicate a request for a DMA operation. IORD 99 W15 33 L5 O I/O read. IORD is asserted by the PCI1225 to enable 16-bit I/O PC Card data output during host I/O read cycles. DMA write. IORD is used as the DMA write strobe during DMA operations from a 16-bit PC Card that supports DMA. The PCI1225 asserts IORD during DMA transfers from the PC Card to host memory. IOWR 101 V15 35 M2 O I/O write. IOWR is driven low by the PCI1225 to strobe write data into 16-bit I/O PC Cards during host I/O write cycles. DMA read. IOWR is used as the DMA write strobe during DMA operations from a 16-bit PC Card that supports DMA. The PCI1225 asserts IOWR during transfers from host memory to the PC Card. OE 98 U14 32 L6 O Output enable. OE is driven low by the PCI1225 to enable 16-bit memory PC Card data output during host memory read cycles. DMA terminal count. OE is used as terminal count (TC) during DMA operations to a 16-bit PC Card that supports DMA. The PCI1225 asserts OE to indicate TC for a DMA write operation. † Terminal name for slot A is preceded with A_. For example, the full name for terminals 127 and L14 is A_INPACK. ‡ Terminal name for slot B is preceded with B_. For example, the full name for terminals 61 and R7 is B_INPACK.

SCPS035B – MAY 1998 – REVISED – MAY 2000

18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions (Continued) 16-bit PC Card interface control (slots A and B) (continued) TERMINAL NUMBER I/O FUNCTION NAME SLOT A † SLOT B ‡ I/O TYPE FUNCTION NAME PDV GHK PDV GHK READY (IREQ) 135 J17 69 V8 I Ready. The ready function is provided by READY when the 16-bit PC Card and the host socket are configured for the memory-only interface. READY is driven low by the 16-bit memory PC Cards to indicate that the memory card circuits are busy processing a previous write command. READY is driven high when the 16-bit memory PC Card is ready to accept a new data transfer command. Interrupt request. IREQ is asserted by a 16-bit I/O PC Card to indicate to the host that a device on the 16-bit I/O PC Card requires service by the host software. IREQ is high (deasserted) when no interrupt is requested. REG 130 K17 63 P8 O Attribute memory select. REG remains high for all common memory accesses. When REG is asserted, access is limited to attribute memory (OE or WE active) and to the I/O space (IORD or IOWR active). Attribute memory is a separately accessed section of card memory and is generally used to record card capacity and other configuration and attribute information. DMA acknowledge. REG is used as a DMA acknowledge (DACK) during DMA operations to a 16-bit PC Card that supports DMA. The PCI1225 asserts REG to indicate a DMA operation. REG is used in conjunction with the DMA read (IOWR) or DMA write (IORD) strobes to transfer data. RESET 124 L18 58 W5 O PC Card reset. RESET forces a hard reset to a 16-bit PC Card. VS1 VS2 134 122 J18 M19 P7 I/O Voltage sense 1 and voltage sense 2. VS1 and VS2, when used in conjunction with each other, determine the operating voltage of the 16-bit PC Card. WAIT 136 J14 70 W8 I Bus cycle wait. WAIT is driven by a 16-bit PC Card to delay the completion of (i.e., extend) the memory or I/O cycle in progress. WE 110 R19 46 P3 O Write enable. WE is used to strobe memory write data into 16-bit memory PC Cards. WE is also used for memory PC Cards that employ programmable memory technologies. DMA terminal count. WE is used as TC during DMA operations to a 16-bit PC Card that supports DMA. The PCI1225 asserts WE to indicate TC for a DMA read operation. WP (IOIS16) 139 H18 73 U9 I Write protect. WP applies to 16-bit memory PC Cards. WP reflects the status of the write-protect switch on 16-bit memory PC Cards. For 16-bit I/O cards, WP is used for the 16-bit port (IOIS16 ) function. I/O is 16 bits. IOIS16 applies to 16-bit I/O PC Cards. IOIS16 is asserted by the 16-bit PC Card when the address on the bus corresponds to an address to which the 16-bit PC Card responds, and the I/O port that is addressed is capable of 16-bit accesses. DMA request. WP can be used as the DMA request signal during DMA operations to a 16-bit PC Card that supports DMA. If used, the PC Card asserts WP to indicate a request for a DMA operation. † Terminal name for slot A is preceded with A_. For example, the full name for terminals 110 and R19 is A_WE. ‡ Terminal name for slot B is preceded with B_. For example, the full name for terminals 46 and P3 is B_WE.

SCPS035B – MAY 1998 – REVISED – MAY 2000 19POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) CardBus PC Card interface system (slots A and B) TERMINAL NUMBER I/O FUNCTION NAME SLOT A † SLOT B ‡ I/O TYPE FUNCTION NAME PDV GHK PDV GHK CCLK 112 P18 48 P6 O CardBus PC Card clock. CCLK provides synchronous timing for all transactions on the CardBus interface. All signals except CRST, CCLKRUN , CINT, CSTSCHG, CAUDIO, CCD2 , CCD1, CVS2, and CVS1 are sampled on the rising edge of CCLK, and all timing parameters are defined with the rising edge of this signal. CCLK operates at the PCI bus clock frequency, but it can be stopped in the low state or slowed down for power savings. CCLKRUN 139 H18 73 U9 O CardBus PC Card clock run. CCLKRUN is used by a CardBus PC Card to request an increase in the CCLK frequency, and by the PCI1225 to indicate that the CCLK frequency is going to be decreased. CRST 124 L18 58 W5 I/O CardBus PC Card reset. CRST is used to bring CardBus PC Card-specific registers, sequencers, and signals to a known state. When CRST is asserted, all CardBus PC Card signals must be 3-stated, and the PCI1225 drives these signals to a valid logic level. Assertion can be asynchronous to CCLK, but deassertion must be synchronous to CCLK. † Terminal name for slot A is preceded with A_. For example, the full name for terminals 112 and P18 is A_CCLK. ‡ Terminal name for slot B is preceded with B_. For example, the full name for terminals 48 and P6 is B_CCLK.

SCPS035B – MAY 1998 – REVISED – MAY 2000

20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions (Continued) CardBus PC Card address and data (slots A and B) TERMINAL PIN NUMBER I/O FUNCTION NAME SLOT A † SLOT B ‡ I/O TYPE FUNCTION NAME PDV GHK PDV GHK CAD31 CAD30 CAD29 CAD28 CAD27 CAD26 CAD25 CAD24 CAD23 CAD22 CAD21 CAD20 CAD19 CAD18 CAD17 CAD16 CAD15 CAD14 CAD13 CAD12 CAD11 CAD10 CAD9 CAD8 CAD7 CAD6 CAD5 CAD4 CAD3 CAD2 CAD1 CAD0 147 145 144 142 141 133 132 131 128 126 125 123 121 119 118 103 101 102 100 F19 G17 G18 H15 H14 J19 K14 K15 K19 L15 L17 L19 M18 M15 N19 U15 V15 R14 W15 P14 U14 R13 W14 U13 V13 P12 R12 V12 U12 P11 R11 U11 W11 R10 U10 V10 W10 I/O PC Card address and data. These signals make up the multiplexed CardBus address and data bus on the CardBus interface. During the address phase of a CardBus cycle, CAD31–CAD0 contain a 32-bit address. During the data phase of a CardBus cycle, CAD31–CAD0 contain data. CAD31 is the most-significant bit. CC/BE3 CC/BE2 CC/BE1 CC/BE0 130 117 104 K17 N18 W16 P13 I/O CardBus bus commands and byte enables. CC/BE3–CC/BE0 are multiplexed on the same CardBus terminals. During the address phase of a CardBus cycle, CC/BE3 –CC/BE0 defines the bus command. During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit data bus carry meaningful data. CC/BE0 applies to byte 0 (CAD7–CAD0), CC/BE1 applies to byte 1 (CAD15–CAD8), CC/BE2 applies to byte 2 (CAD23–CAD8), and CC/BE3 applies to byte 3 (CAD31–CAD24). CPAR 106 R17 41 N3 I/O CardBus parity. In all CardBus read and write cycles, the PCI1225 calculates even parity across the CAD and CC/BE buses. As an initiator during CardBus cycles, the PCI1225 outputs CPAR with a one-CCLK delay. As a target during CardBus cycles, the calculated parity is compared to the initiator parity indicator; a compare error results in a parity error assertion. † Terminal name for slot A is preceded with A_. For example, the full name for terminals 106 and R17 is A_CPAR. ‡ Terminal name for slot B is preceded with B_. For example, the full name for terminals 41 and N3 is B_CPAR.

SCPS035B – MAY 1998 – REVISED – MAY 2000 21POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) CardBus PC Card interface control (slots A and B) TERMINAL PIN NUMBER I/O FUNCTION NAME SLOT A † SLOT B ‡ I/O TYPE FUNCTION NAME PDV GHK PDV GHK CAUDIO 137 J15 71 W9 I CardBus audio. CAUDIO is a digital input signal from a PC Card to the system speaker. The PCI1225 supports the binary audio mode and outputs a binary signal from the card to SPKROUT. CBLOCK 107 P15 42 N6 I/O CardBus lock. CBLOCK is used to gain exclusive access to a target. CCD1 82 V11 16 H3 I CardBus detect 1 and CardBus detect 2. CCD1 and CCD2 are used in conjunction ith CVS1 d CVS2 t id tif d i ti d i t t d t d t i thCCD1 CCD2 140 V11 H17 R9 I with CVS1 and CVS2 to identify card insertion and interrogate cards to determine the operating voltage and card type. CDEVSEL 111 P17 47 R1 I/O CardBus device select. The PCI1225 asserts CDEVSEL to claim a CardBus cycle as the target device. As a CardBus initiator on the bus, the PCI1225 monitors CDEVSEL until a target responds. If no target responds before timeout occurs, the PCI1225 terminates the cycle with an initiator abort. CFRAME 116 N17 51 R3 I/O CardBus cycle frame. CFRAME is driven by the initiator of a CardBus bus cycle. CFRAME is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. When CFRAME is deasserted, the CardBus bus transaction is in the final data phase. CGNT 110 R19 46 P3 I CardBus bus grant. CGNT is driven by the PCI1225 to grant a CardBus PC Card access to the CardBus bus after the current data transaction has been completed. CINT 135 J17 69 V8 I CardBus interrupt. CINT is asserted low by a CardBus PC Card to request interrupt servicing from the host. CIRDY 115 M14 50 P5 I/O CardBus initiator ready. CIRDY indicates the ability of the CardBus initiator to complete the current data phase of the transaction. A data phase is completed on a rising edge of CCLK when both CIRDY and CTRDY are asserted. Until CIRDY and CTRDY are both sampled asserted, wait states are inserted. CPERR 108 N14 43 P1 I/O CardBus parity error. CPERR is used to report parity errors during CardBus transactions, except during special cycles. It is driven low by a target two clocks following that data when a parity error is detected. CREQ 127 L14 61 R7 I CardBus request. CREQ indicates to the arbiter that the CardBus PC Card desires use of the CardBus bus as an initiator. CSERR 136 J14 70 W8 I CardBus system error. CSERR reports address parity errors and other system errors that could lead to catastrophic results. CSERR is driven by the card synchronous to CCLK, but deasserted by a weak pullup, and may take several CCLK periods. The PCI1225 can report CSERR to the system by assertion of SERR on the PCI interface. CSTOP 109 R18 45 N5 I/O CardBus stop. CSTOP is driven by a CardBus target to request the initiator to stop the current CardBus transaction. CSTOP is used for target disconnects, and is commonly asserted by target devices that do not support burst data transfers. CSTSCHG 138 H19 72 V9 I CardBus status change. CSTSCHG is used to alert the system to a change in the card status, and is used as a wake-up mechanism. CTRDY 114 P19 49 R2 I/O CardBus target ready. CTRDY indicates the ability of the CardBus target to complete the current data phase of the transaction. A data phase is completed on a rising edge of CCLK, when both CIRDY and CTRDY are asserted; until this time, wait states are inserted. CVS1 134 J18 68 U8 I/O CardBus voltage sense 1 and CardBus voltage sense 2. CVS1 and CVS2 are used in conjunction with CCD1and CCD2 to identify card insertion and interrogate cardsCVS1 CVS2 134 122 J18 M19 P7 I/O in conjunction with CCD1 and CCD2 to identify card insertion and interrogate cards to determine the operating voltage and card type. † Terminal name for slot A is preceded with A_. For example, the full name for terminals 137 and J15 is A_CAUDIO. ‡ Terminal name for slot B is preceded with B_. For example, the full name for terminals 71 and W9 is B_CAUDIO.

22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

on the interface. The following power-up and power-down sequences are recommended.

1. Apply 3.3-V power to the core.

the high-impedance state to prevent high current levels through the clamp diodes to the 5-V supply. to switch outputs to a high-impedance state.

1. Remove the 3.3-V power from the core.

provides the electrical characteristics of the inputs and outputs. Figure 1. 3-State Bidirectional Buffer Unused pins (input or I/O) must be held high or low to prevent them from floating. CCP can be connected to a 5-V power supply. are listed and defined in the recommended operating conditions, on page 120.

SCPS035B – MAY 1998 – REVISED – MAY 2000 23POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 peripheral component interconnect (PCI) interface The PCI1225 is fully compliant with the PCI Local Bus Specification Rev. 2.2. The PCI1225 provides all required signals for PCI master or slave operation, and may operate in either a 5-V or 3.3-V signaling environment by connecting the V CCP terminals to the desired voltage level. In addition to the mandatory PCI signals, the PCI1225 provides the optional interrupt signals INTA and INTB. PCI bus lock (LOCK) The bus-locking protocol defined in the PCI specification is not highly recommended, but is provided on the PCI1225 as an additional compatibility feature. The PCI LOCK signal can be routed to the MFUNC4 terminal via the multifunction routing register; see the multifunction routing register description on page 64 for details. Note that the use of LOCK is only supported by PCI-to-CardBus bridges in the downstream direction (away from the processor). PCI LOCK indicates an atomic operation that may require multiple transactions to complete. When LOCK is asserted, nonexclusive transactions can proceed to an address that is not currently locked. A grant to start a transaction on the PCI bus does not guarantee control of LOCK ; control of LOCK is obtained under its own protocol. It is possible for different initiators to use the PCI bus while a single master retains ownership of LOCK. Note that the CardBus signal for this protocol is CBLOCK to avoid confusion with the bus clock. An agent may need to do an exclusive operation because a critical access to memory might be broken into several transactions, but the master wants exclusive rights to a region of memory. The granularity of the lock is defined by PCI to be 16 bytes, aligned. The lock protocol defined by PCI allows a resource lock without interfering with nonexclusive real-time data transfer, such as video. The PCI bus arbiter may be designed to support only complete bus locks using the LOCK protocol. In this scenario, the arbiter will not grant the bus to any other agent (other than the LOCK master) while LOCK is asserted. A complete bus lock may have a significant impact on the performance of the video. The arbiter that supports complete bus lock must grant the bus to the cache to perform a writeback due to a snoop to a modified line when a locked operation is in progress. The PCI1225 supports all LOCK protocols associated with PCI-to-PCI bridges, as also defined for PCI-to-CardBus bridges. This includes disabling write posting while a locked operation is in progress, which can solve a potential deadlock when using devices such as PCI-to-PCI bridges. The potential deadlock can occur if a CardBus target supports delayed transactions and blocks access to the target until it completes a delayed read. This target characteristic is prohibited by the 2.2 PCI specification, and the issue is resolved by the PCI master using LOCK loading subsystem identification The subsystem vendor ID register and subsystem ID register make up a doubleword of PCI configuration space located at offset 40h for functions 0 and 1. This doubleword register is used for system and option card (mobile dock) identification purposes and is required by some operating systems. Implementation of this unique identifier register is a PC 95 requirement. The PCI1225 offers two mechanisms to load a read-only value into the subsystem registers. The first mechanism relies upon the system BIOS providing the subsystem ID value. The default access mode to the subsystem registers is read-only, but can be made read/write by setting the SUBSYSRW bit in the system control register (bit 5, at PCI offset 80h). Once this bit is set, the BIOS can write a subsystem identification value into the registers at offset 40h. The BIOS must clear the SUBSYSRW bit such that the subsystem vendor ID register and subsystem ID register is limited to read-only access. This approach saves the added cost of implementing the serial electrically erasable programmable ROM (EEPROM).

24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

The PCI1225 provides a two-line serial bus host controller that can be used to interface to a serial EEPROM. See serial bus interface on page 31 for details on the two-wire serial bus controller and applications. interrogation, card voltage requirements and interface (16 bit versus CardBus) are determined. configuration of these four terminals identifies the card type and voltage requirements of the PC Card interface. The encoding scheme is defined in the 1997 PC Card Standard and in Table 5. Table 5. PC Card Card-Detect and Voltage-Sense Connections

26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

to access PC Card CIS registers for PC Card configuration. Figure 4 illustrates a PCI1225 ZV implementation. Figure 4. Zoom Video Implementation Using PCI1225 streams using external logic. Figure 5. Zoom Video Switching Application

Figure 5 illustrates an implementation using standard three-state bus drivers with active-low output enables. software to select the socket ZV source priority. Table 6 illustrates the functionality of the ZV output signals. Table 6. PC Card Card-Detect and Voltage-Sense Connections

1 X 1 1 0 1

shown in Figure 5 can be used if PC Card ZV is prioritized over other sources. SPKROUTEN bit in the card control register. PCI1225 implementation includes a signal for PWM, CAUDPWM, which can be routed to a MFUNC terminal. 64 for details on configuring the MFUNC terminals. Figure 6 provides an illustration of a sample application using SPKROUT and CAUDPWM. Figure 6. Sample Application of SPKROUT and CAUDPWM

28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

multifunction routing register description on page 64 for details on configuring the multifunction terminals. it is left for the board designer to implement the circuit that best fits the application. pulsed if CFRAME, IRDY, or CREQ is active. Figure 7. Two Sample LED Circuits driven. If socket activity is frequent (at least once every 64 ms), the LED signals remain driven. register configuration is provided in Table 7.

Table 7. Distributed DMA Registers as read-only and return zeros when read. Write transactions to reserved registers have no effect. the PCI1225 accepts the next byte(s) from the PC Card until the transfer count expires.

30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

multifunction routing register description on page 64 for details on configuring the multifunction terminals. PC/PCI DMA is enabled for each 16-bit PC Card slot by setting bit 19 in the respective system control register. in the system control register. The channels are configured as indicated in Table 8. Table 8. PC/PCI Channel Assignments register 0. The data transfer width is a function of channel number, and the DDMA slave registers are not used. addresses listed in Table 9 and performs actions dependent upon the address. Table 9. I/O Addresses Used for PC/PCI DMA master state machine is required to support PC/PCI DMA, since the DMA control is centralized in the chipset. This DMA scheme is often referred to as centralized DMA for this reason. specification. These registers exist as the CardBus socket registers, and are listed in Table 10.

32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

interpreted as control signals, that is, a start or a stop condition. Figure 9. Serial Bus Start/Stop Conditions and Bit Transfers indicated by the receiver pulling the SDA signal low so that it remains low during the high state of the SCL signal. The acknowledge protocol is illustrated in Figure 10. Figure 10. Serial Bus Protocol Acknowledge three-states SCL (zero frequency) during idle states. loads the subsystem identification and other register defaults through a serial bus EEPROM. address and the command bit zero. A zero in the R/W command bit indicates that the data transfer is a write. the data byte MSB first and expects a final acknowledgment before issuing the stop condition.

34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

be loaded with defaults through the EEPROM are provided in Table 11. Table 11. Registers and Bits Loadable Through Serial EEPROM ROM_ERR bit in the serial bus control and status register. Figure 14. EEPROM Data Format considered when programming the EEPROM. terminal inputs to the chip, and the sample application shows these terminal inputs tied to GND. Figure 13. The address autoincrements after every byte transfer according to the doubleword read protocol.

is 01h, 02h, 03h, 04h. If the offsets are not sequential, the registers may be loaded incorrectly. Figure 15. Send Byte Protocol The power switch may support an interrupt mode to indicate overcurrent or other power switch related events. Power Interface Specification for details on implementing the PCI1225 in an ACPI system. registers used to program a serial bus device through software. Table 12. PCI1225 Registers Used to Program Serial Bus Devices register is not used in the quick command protocol. command selector are programmed through this register. register. In addition, the protocol select bit is programmed through this register.

SCPS035B – MAY 1998 – REVISED – MAY 2000

36 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

programmable interrupt subsystem Interrupts provide a way for I/O devices to let the microprocessor know that they require servicing. The dynamic nature of PC Cards, and the abundance of PC Card I/O applications require substantial interrupt support from the PCI1225. The PCI1225 provides several interrupt signaling schemes to accommodate the needs of a variety of platforms. The different mechanisms for dealing with interrupts in this device are based on various specifications and industry standards. The ExCA register set provides interrupt control for some 16-bit PC Card functions, and the CardBus socket register set provides interrupt control for the CardBus PC Card functions. The PCI1225 is, therefore, backward compatible with existing interrupt control register definitions, and new registers have been defined where required. The PCI1225 detects PC Card interrupts and events at the PC Card interface and notifies the host controller using one of several interrupt signaling protocols. To simplify the discussion of interrupts in the PCI1225, PC Card interrupts are classified as either card status change (CSC) or as functional interrupts. The method by which any type of PCI1225 interrupt is communicated to the host interrupt controller varies from system to system. The PCI1225 offers system designers the choice of using parallel PCI interrupt signaling, parallel ISA-type IRQ interrupt signaling, or the IRQSER serialized ISA and/or PCI interrupt protocol. It is possible to use the parallel PCI interrupts in combination with either parallel IRQs or serialized IRQs, as detailed in the sections that follow. All interrupt signalling is provided through the seven multifunction terminals, MFUNC0–MFUNC6. PC Card functional and card status change interrupts PC Card functional interrupts are defined as requests from a PC Card application for interrupt service and are indicated by asserting specially-defined signals on the PC Card interface. Functional interrupts are generated by 16-bit I/O PC Cards and by CardBus PC Cards. Card status change (CSC)-type interrupts are defined as events at the PC Card interface that are detected by the PCI1225 and may warrant notification of host card and socket services software for service. CSC events include both card insertion and removal from PC Card sockets, as well as transitions of certain PC Card signals. Table 13 summarizes the sources of PC Card interrupts and the type of card associated with them. CSC and functional interrupt sources are dependent on the type of card inserted in the PC Card socket. The three types of cards that can be inserted into any PC Card socket are: 16-bit memory card 16-bit I/O card CardBus cards

Table 13. Interrupt Mask and Flag Registers independent of the card type. Table 14. PC Card Interrupt Events and Description of the memory PC Card to accept or provide data.

SCPS035B – MAY 1998 – REVISED – MAY 2000

38 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PC Card functional and CSC interrupts (continued) The naming convention for PC Card signals describes the function for 16-bit memory, I/O cards, and CardBus. For example, READY(IREQ)//CINT includes READY for 16-bit memory cards, IREQ for 16-bit I/O cards, and CINT for CardBus cards. The 16-bit memory card signal name is first, with the I/O card signal name second, enclosed in parentheses. The CardBus signal name follows after a forward double slash (//). The PC Card standard describes the power-up sequence that must be followed by the PCI1225 when an insertion event occurs and the host requests that the socket VCC and VPP be powered. Upon completion of this power-up sequence, the PCI1225 interrupt scheme can be used to notify the host system (see Table 14), denoted by the power cycle complete event. This interrupt source is considered a PCI1225 internal event because it depends on the completion of applying power to the socket rather than on a signal change at the PC Card interface. interrupt masks and flags Host software may individually mask (or disable) most of the potential interrupt sources listed in Table 14 by setting the appropriate bits in the PCI1225. By individually masking the interrupt sources listed, software can control those events that cause a PCI1225 interrupt. Host software has some control over the system interrupt the PCI1225 asserts by programming the appropriate routing registers. The PCI1225 allows host software to route PC Card CSC and PC Card functional interrupts to separate system interrupts. Interrupt routing somewhat specific to the interrupt signaling method used is discussed in more detail in the following sections. When an interrupt is signaled by the PCI1225, the interrupt service routine must determine which of the events listed in Table 13 caused the interrupt. Internal registers in the PCI1225 provide flags that report the source of an interrupt. By reading these status bits, the interrupt service routine can determine the action to be taken. Table 13 details the registers and bits associated with masking and reporting potential interrupts. All interrupts can be masked except the functional PC Card interrupts, and an interrupt status flag is available for all types of interrupts. Notice that there is not a mask bit to stop the PCI1225 from passing PC Card functional interrupts through to the appropriate interrupt scheme. These interrupts are not valid until the card is properly powered, and there should never be a card interrupt that does not require service after proper initialization. Various methods of clearing the interrupt flag bits are listed in Table 13. The flag bits in the ExCA registers (16-bit PC Card-related interrupt flags) can be cleared using two different methods. One method is an explicit write of 1 to the flag bit to clear, and the other is by reading the flag bit register. The selection of flag bit clearing is made by bit 2 in the global control register (ExCA offset 1Eh/5Eh/81Eh), and defaults to the flag cleared on read method. The CardBus-related interrupt flags can be cleared by an explicit write of 1 to the interrupt flag in the socket event register. Although some of the functionality is shared between the CardBus registers and the ExCA registers, software should not program the chip through both register sets when a CardBus card is functioning. using parallel IRQ interrupts The seven multifunction terminals, MFUNC6:0, implemented in the PCI1225 may be routed to obtain a subset of the ISA IRQs. The IRQ choices provide ultimate flexibility in PC Card host interruptions. To use the parallel ISA type IRQ interrupt signaling, software must program the device control register, located at PCI offset 92h, to select the parallel IRQ signaling scheme. See the multifunction routing register description on page 64 for details on configuring the multifunction terminals. A system using parallel IRQs requires (at a minimum) one PCI terminal, INTA, to signal CSC events. This requirement is dictated by certain card and socket services software. The INTA requirement calls for routing the MFUNC0 terminal for INTA signaling. The INTRTIE bit is used, in this case, to route socket 1 interrupt events to INTA. This leaves (at a maximum) six different IRQs to support legacy 16-bit PC Card functions.

40 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Table 15. Interrupt Pin Register Cross Reference be configured as IRQSER prior to setting the INTRTIE bit. INTD. For details on the IRQSER protocol see the document Serialized IRQ Support for PCI Systems. cycle change sequence sent on the power switch interface. SMIROUTE, SMISTATUS, and SMIENB. The SMI control bits function as described in Table 16. Table 16. SMI Control SMIROUTE This shared bit controls whether the SMI interrupts are sent as a CSC interrupt or as IRQ2. SMISTAT This socket-dependent bit is set when an SMI interrupt is pending. This status flag is cleared by writing back a 1. SMIENB When set, SMI interrupt generation is enabled. This bit is shared by functions 0 and 1. MFUNC3 or MFUNC6 through the multifunction routing register.

SCPS035B – MAY 1998 – REVISED – MAY 2000 41POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 power management overview TI has expended great effort to provide a high-performance device with low power consumption. In addition to the low-power CMOS technology process used for the PCI1225, various features are designed into the device to allow implementation of popular power-saving techniques. These features and techniques are discussed in this section. clock run protocol The PCI CLKRUN feature is the primary method of power management on the PCI interface of the PCI1225. CLKRUN signalling is provided through the MFUNC6 terminal. Since some chipsets do not implement CLKRUN , this is not always available to the system designer, and alternate power-saving features are provided. For details on the CLKRUN protocol see the PCI Mobile Design Guide. The PCI1225 does not permit the central resource to stop the PCI clock under any of the following conditions: The KEEPCLK bit in the system control register is set. The 16-bit PC Card resource manager is busy. The PCI1225 CardBus master state machine is busy. A cycle may be in progress on CardBus. The PCI1225 master is busy. There may be posted data from CardBus to PCI in the PCI1225. There are pending interrupts. The CardBus CCLK for either socket has not been stopped by the PCI1225 CLKRUN manager. The PCI1225 restarts the PCI clock using the CLKRUN protocol under any of the following conditions: A 16-bit PC Card IREQ or a CardBus CINT has been asserted by either card. A CardBus wake-up (CSTSCHG) or 16-bit PC Card STSCHG/RI event occurs in either socket. A CardBus attempts to start CCLK using CCLKRUN. A CardBus card arbitrates for the CardBus bus using CREQ. A 16-bit DMA PC Card asserts DREQ. CardBus PC card power management The PCI1225 implements its own card power management engine that can be used to turn off the CCLK to a socket when there is no activity to the CardBus PC Card. The PCI clock-run protocol is followed on the CardBus CCLKRUN interface to control this clock management. 16-Bit PC card power management The COE and PWRDOWN bits in the ExCA registers are provided for 16-bit PC Card power management. The COE bit three states the card interface to save power. The power savings when using this feature are minimal. The COE bit will reset the PC Card when used, and the PWRDOWN bit will not. Furthermore, the PWRDOWN bit is an automatic COE, that is, the PWRDOWN performs the COE function when there is no card activity. NOTE: The 16-bit PC Card must implement the proper pullup resistors for the COE and PWRDOWN modes.

42 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

How to pass CSC (insertion/removal) events. functional implementation diagram. Figure 17. SUSPEND Functional Implementation Figure 18 is a signal diagram of the suspend function.

Figure 18. Signal Diagram of Suspend Function A powered down CardBus card asserts CSTSCHG (CBWAKE) requesting system and interface wake up. A CSC event occurs, such as insertion/removal of cards, battery voltage levels.

44 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Figure 19. RI_OUT Functional Diagram mask bit, CSTSMASK, is programmed through the socket mask register in the CardBus socket registers. software-visible power-management states that result in varying levels of power savings. power state of the originating bridge device.

access to a capabilities list. Table 17. Power-Management Registers register that can provide dynamic data. PCI Bus Power Management Interface Specification. ACPI driver. The PCI1225 offers a generic interface that is compliant with ACPI design rules. are implemented as defined by ACPI, and illustrated in Figure 20. Figure 20. Block Diagram of a Status/Enable Cell in some level of power state to report events. Advanced Configuration and Power Interface Specification.

46 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

The PCI1225 is a multifunction PCI device, and the PC Card controller is integrated as PCI functions 0 and 1. the configuration space and the user-definable registers. Table 18. PCI Configuration Registers (Functions 0 and 1)

SCPS035B – MAY 1998 – REVISED – MAY 2000 47POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 vendor ID register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Vendor ID Type R R R R R R R R R R R R R R R R Default 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0 Register: Vendor ID Type: Read-only Offset: 00h (functions 0, 1) Default: 104Ch Description: This 16-bit read-only register contains a value allocated by the PCI Special Interest Group (SIG) and identifies the manufacturer of the PCI device. The vendor ID assigned to TI is 104Ch. device ID register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Device ID Type R R R R R R R R R R R R R R R R Default 1 0 1 0 1 1 0 0 0 0 0 1 1 1 0 0 Register: Device ID Type: Read-only Offset: 02h (functions 0, 1) Default: AC1Ch Description: This 16-bit read-only register contains a value assigned to the PCI1225 by TI. The device identification for the PCI1225 is AC1Ch. command register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Command Type R R R R R R R R/W R R/W R R R R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Command Type: Read-only, read/write (see individual bit descriptions) Offset: 04h Default: 0000h Description: The command register provides control over the PCI1225 interface to the PCI bus. All bit functions adhere to the definitions in PCI Local Bus Specification 2.2. None of the bit functions in this register are shared between the two PCI1225 PCI functions. Two command registers exist in the PCI1225, one for each function. Software must manipulate the two PCI1225 functions as separate entities when enabling functionality through the command register. The SERR_EN and PERR_EN enable bits in this register are internally wired-OR between the two functions, and these control bits appear separately according to their software function. See Table 19 for the complete description of the register contents.

48 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Table 19. Command Register 15–10 RSVD R Reserved. Bits 15–10 are read-only and return 0s when read. Write transactions have no effect. 9 is read-only and returns 0s when read.

8 SERR_EN R/W

for the PCI1225 to report address parity errors. hardwired to 0. Write transactions to this bit have no effect.

6 PERR_EN R/W

5 VGA_EN R

5 is read-only and returns 0 when read. Write transactions to this bit have no effect.

4 MWI_EN R

and returns 0 when read. Write transactions to this bit have no effect.

3 SPECIAL R

0 when read. Write transactions to this bit have no effect.

2 MAST_EN R/W

PCI1225 can take control of the PCI bus only when this bit is set.

1 MEM_EN R/W

Memory space enable. Bit 1 controls whether or not the PCI1225 can claim cycles in PCI memory space.

0 IO_EN R/W

I/O space control. Bit 0 controls whether or not the PCI1225 can claim cycles in PCI I/O space.

complete description of the register contents. Table 20. Status Register 15 PAR_ERR R/C Detected parity error. Bit 15 is set when a parity error is detected (either address or data). terminated by a master abort. the PCI1225 asserts PCI_SPEED at a medium speed on nonconfiguration cycle accesses.

8 DATAPAR R/C

0 = The conditions for setting bit 8 have not been met. a. PERR was asserted by any PCI device including the PCI1225. b. The PCI1225 was the bus master during the data parity error. c. The PERR_EN bit is set in the command register.

4 CAPLIST R

implemented in this function. 3–0 RSVD R Reserved. Bits 3–0 return 0s when read.

SCPS035B – MAY 1998 – REVISED – MAY 2000

50 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Register: Revision ID Type: Read-only Offset: 08h (functions 0, 1) Default: 01h Description: This read-only register indicates the silicon revision of the PCI1225. PCI class code register Bit 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Class code Base class Sub class Programming interface Type R R R R R R R R R R R R R R R R R R R R R R R R Default 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 Register: PCI Class code Type: Read-only Offset: 09h (functions 0, 1) Default: 060700h Description: The class code register recognizes the PCI1225 functions 0 and 1 as a bridge device (06h), and CardBus bridge device (07h) with a 00h programming interface. cache line size register Bit 7 6 5 4 3 2 1 0 Name Cache line size Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register: Cache line size Type: Read/write Offset: 0Ch (functions 0, 1) Default: 00h Description: The cache line size register is programmed by host software to indicate the system cache line size.

SCPS035B – MAY 1998 – REVISED – MAY 2000 51POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 latency timer register Bit 7 6 5 4 3 2 1 0 Name Latency timer Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register: Latency timer Type: Read/write Offset: 0Dh Default: 00h Description: The latency timer register specifies the latency timer for the PCI1225 in units of PCI clock cycles. When the PCI1225 is a PCI bus initiator and asserts FRAME , the latency timer begins counting from zero. If the latency timer expires before the PCI1225 transaction has terminated, the PCI1225 terminates the transaction when its GNT is deasserted. This register is separate for each of the two PCI1225 functions. This allows platforms to prioritize the two PCI1225 functions’ use of the PCI bus. header type register Bit 7 6 5 4 3 2 1 0 Name Header type Type R R R R R R R R Default 1 0 0 0 0 0 1 0 Register: Header type Type: Read-only Offset: 0Eh (functions 0, 1) Default: 82h Description: This read-only register returns 82h when read, indicating that the PCI1225 functions 0 and 1 configuration spaces adhere to the CardBus bridge PCI header. The CardBus bridge PCI header ranges from PCI register 00h to 7Fh, and 80h–FFh is user-definable extension registers. BIST register Bit 7 6 5 4 3 2 1 0 Name BIST Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Register: BIST Type: Read-only Offset: 0Fh (functions 0, 1) Default: 00h Description: Because the PCI1225 does not support a built-in self-test (BIST), this register is read-only and returns the value of 00h when read.

SCPS035B – MAY 1998 – REVISED – MAY 2000

52 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CardBus socket registers/ExCA base-address register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name CardBus socket/ExCA base address Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name CardBus socket/ExCA base address Type R/W R/W R/W R/W R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: CardBus socket/ExCA base address Type: Read-only, read/write Offset: 10h Default: 0000 0000h Description: The CardBus socket registers/ExCA base-address register is programmed with a base address referencing the CardBus socket registers and the memory-mapped ExCA register set. Bits 31–12 are read/write, and allow the base address to be located anywhere in the 32-bit PCI memory address space on a 4-Kbyte boundary. Bits 11–0 are read-only, returning 0s when read. When software writes all 1s to this register, the value read back is FFFF F000h, indicating that at least 4 Kbytes of memory address space are required. The CardBus registers start at offset 000h, and the memory-mapped ExCA registers begin at offset 800h. Since this register is not shared by functions 0 and 1, mapping of each socket control is performed separately. capability pointer register Bit 7 6 5 4 3 2 1 0 Name Capability pointer Type R R R R R R R R Default 1 0 1 0 0 0 0 0 Register: Capability pointer Type: Read-only Offset: 14h Default: A0h Description: The capability pointer register provides a pointer into the PCI configuration header where the PCI power management register block resides. PCI header doublewords at A0h and A4h provide the power management (PM) registers. Each socket has its own capability pointer register. This register is read-only and returns A0h when read.

Table 21 for a complete description of the register contents. Table 21. Secondary Status Register 15 CBPARITY R/C Detected parity error. Bit 15 is set when a CardBus parity error is detected (either address or data). terminated by a master abort. terminated by a target abort. indicating that the PCI1225 asserts CB_SPEED at a medium speed.

8 CB_DPAR R/C

CardBus data parity error detected. 0 = The conditions for setting bit 8 have not been met. a. CPERR was asserted on the CardBus interface. b. The PCI1225 was the bus master during the data parity error. c. The PERR_EN bit is set in the bridge control register. therefore, bit 5 is hardwired to 0. 4–0 RSVD R Reserved. Bits 4–0 return 0s when read.

SCPS035B – MAY 1998 – REVISED – MAY 2000

54 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register: PCI bus number Type: Read/write Offset: 18h (functions 0, 1) Default: 00h Description: This read/write register is programmed by the host system to indicate the bus number of the PCI bus to which the PCI1225 is connected. The PCI1225 uses this register in conjunction with the CardBus bus number and subordinate bus number registers to determine when to forward PCI configuration cycles to its secondary buses. CardBus bus number register Bit 7 6 5 4 3 2 1 0 Name CardBus bus number Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register: CardBus bus number Type: Read/write Offset: 19h Default: 00h Description: This read/write register is programmed by the host system to indicate the bus number of the CardBus bus to which the PCI1225 is connected. The PCI1225 uses this register in conjunction with the PCI bus number and subordinate bus number registers to determine when to forward PCI configuration cycles to its secondary buses. This register is separate for each PCI1225 controller function. subordinate bus number register Bit 7 6 5 4 3 2 1 0 Name Subordinate bus number Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register: Subordinate bus number Type: Read/write Offset: 1Ah Default: 00h Description: This read/write register is programmed by the host system to indicate the highest-numbered bus below the CardBus bus. The PCI1225 uses this register in conjunction with the PCI bus number and CardBus bus number registers to determine when to forward PCI configuration cycles to its secondary buses. This register is separate for each CardBus controller function.

SCPS035B – MAY 1998 – REVISED – MAY 2000 55POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CardBus latency timer register Bit 7 6 5 4 3 2 1 0 Name CardBus latency timer Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register: CardBus latency timer Type: Read/write Offset: 1Bh (functions 0, 1) Default: 00h Description: This read/write register is programmed by the host system to specify the latency timer for the PCI1225 CardBus interface in units of CCLK cycles. When the PCI1225 is a CardBus initiator and asserts CFRAME , the CardBus latency timer begins counting. If the latency timer expires before the PCI1225 transaction has terminated, then the PCI1225 terminates the transaction at the end of the next data phase. A recommended minimum value for this register is 20h, which allows most transactions to be completed. memory base registers 0, 1 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Memory base registers 0, 1 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Memory base registers 0, 1 Type R/W R/W R/W R/W R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Memory base registers 0, 1 Type: Read-only, read/write Offset: 1Ch, 24h Default: 0000 0000h Description: The memory base registers indicate the lower address of a PCI memory address range. These registers are used by the PCI1225 to determine when to forward a memory transaction to the CardBus bus and when to forward a CardBus cycle to PCI. Bits 31–12 of these registers are read/write and allow the memory base to be located anywhere in the 32-bit PCI memory space on 4-Kbyte boundaries. Bits 11–0 are read-only and always return 0s. Write transactions to these bits have no effect. Bits 8 and 9 of the bridge control register specify whether memory windows 0 and 1 are prefetchable or nonprefetchable. The memory base register or the memory limit register must be nonzero for the PCI1225 to claim any memory transactions through CardBus memory windows (i.e., these windows are not enabled by default to pass the first 4 Kbytes of memory to CardBus).

SCPS035B – MAY 1998 – REVISED – MAY 2000

56 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

memory limit registers 0, 1 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Memory limit registers 0, 1 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Memory limit registers 0, 1 Type R/W R/W R/W R/W R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Memory limit registers 0, 1 Type: Read-only, read/write Offset: 20h, 28h Default: 0000 0000h Description: The memory limit registers indicate the upper address of a PCI memory address range. These registers are used by the PCI1225 to determine when to forward a memory transaction to the CardBus bus and when to forward a CardBus cycle to PCI. Bits 31–12 of these registers are read/write and allow the memory base to be located anywhere in the 32-bit PCI memory space on 4-Kbyte boundaries. Bits 11–0 are read-only and always return 0s. Write transactions to these bits have no effect. Bits 8 and 9 of the bridge control register specify whether memory windows 0 and 1 are prefetchable or nonprefetchable. The memory base register or the memory limit register must be nonzero for the PCI1225 to claim any memory transactions through CardBus memory windows (i.e., these windows are not enabled by default to pass the first 4 Kbytes of memory to CardBus). I/O base registers 0, 1 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name I/O base registers 0, 1 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name I/O base registers 0, 1 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: I/O base registers 0, 1 Type: Read-only, read/write Offset: 2Ch, 34h Default: 0000 0000h Description: The I/O base registers indicate the lower address of a PCI I/O address range. These registers are used by the PCI1225 to determine when to forward an I/O transaction to the CardBus bus and when to forward a CardBus cycle to the PCI bus. The lower 16 bits of this register locate the bottom of the I/O window within a 64K byte page, and the upper sixteen bits (31–16) are a page register which locates this 64K byte page in 32-bit PCI I/O address space. Bits 31–2 are read/write. Bits 1–0 are read-only and always return 0s, forcing I/O windows to be aligned on a natural doubleword boundary. NOTE: Either the I/O base or the I/O limit register must be nonzero to enable any I/O transactions.

SCPS035B – MAY 1998 – REVISED – MAY 2000 57POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 I/O limit registers 0, 1 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name I/O limit registers 0, 1 Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name I/O limit registers 0, 1 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: I/O limit registers 0, 1 Type: Read-only, read/write Offset: 30h, 38h Default: 0000 0000h Description: The I/O limit registers indicate the upper address of a PCI I/O address range. These registers are used by the PCI1225 to determine when to forward an I/O transaction to the CardBus bus and when to forward a CardBus cycle to PCI. The lower 16 bits of this register locate the top of the I/O window within a 64-Kbyte page, and the upper 16 bits are a page register that locates this 64-Kbyte page in 32-bit PCI I/O address space. Bits 15–2 are read/write and allow the I/O limit address to be located anywhere in the 64-Kbyte page (indicated by bits 31–16 of the appropriate I/O base) on doubleword boundaries. Bits 31–16 are read-only and always return 0s when read. The page is set in the I/O base register. Bits 1–0 are read-only and always return 0s, forcing I/O windows to be aligned on a natural doubleword boundary. Write transactions to read-only bits have no effect. The PCI1225 assumes that the lower two bits of the limit address are 1s. NOTE: The I/O base or the I/O limit register must be nonzero to enable an I/O transaction. interrupt line register Bit 7 6 5 4 3 2 1 0 Name Interrupt line Type R/W R/W R/W R/W R/W R/W R/W R/W Default 1 1 1 1 1 1 1 1 Register: Interrupt line Type: Read/write Offset: 3Ch Default: FFh Description: The interrupt line register is read/write and is used to communicate interrupt line routing information. Each PCI1225 function has an interrupt line register.

58 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Table 22. Interrupt Pin Register Cross Reference be configured as IRQSER prior to setting the INTRTIE bit.

for a complete description of the register contents. Table 23. Bridge Control Register 15–11 RSVD R Reserved. Bits 15–11 return 0s when read.

10 POSTEN R/W

dependent and is not shared between functions 0 and 1.

9 PREFETCH1 R/W

0 = Memory window 1 is nonprefetchable. 1 = Memory window 1 is prefetchable (default).

8 PREFETCH0 R/W

0 = Memory window 0 is nonprefetchable. 1 = Memory window 0 is prefetchable (default).

7 INTR R/W

routed to PCI interrupts or to the IRQ specified in the ExCA registers.

6 CRST R/W

asserted by passing a PRST assertion to CardBus. an initiator on the CardBus interface. This bit is common between each socket. 4 RSVD R Reserved. Bit 4 returns 0 when read. to VGA addresses are forwarded.

2 ISAEN R/W

of each 1K I/O range to CardBus. bit is common between the two sockets. 0 = CSERR is not forwarded to PCI SERR. 1 = CSERR is forwarded to PCI SERR. errors. This bit is common between the two sockets. 0 = CardBus parity errors are ignored. † These bits are global and should be accessed only through function 0.

SCPS035B – MAY 1998 – REVISED – MAY 2000

60 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

subsystem vendor ID register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Subsystem vendor ID Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Subsystem vendor ID Type: Read-only (read/write when bit 5 in the system control register is 0) Offset: 40h (functions 0, 1) Default: 0000h Description: The subsystem vendor ID register is used for system and option-card identification purposes and may be required for certain operating systems. This register is read-only or read/write, depending on the setting of bit 5 (SUBSYSRW) in the system control register. When bit 5 is 0, this register is read/write; when bit 5 is 1, this register is read-only. The default mode is read-only. subsystem ID register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Subsystem ID Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Subsystem ID Type: Read-only (read/write when bit 5 in the system control register is 0) Offset: 42h (functions 0, 1) Default: 0000h Description: The subsystem ID register is used for system and option-card identification purposes and may be required for certain operating systems. This register is read-only or read/write, depending on the setting of bit 5 (SUBSYSRW) in the system control register. When bit 5 is 0, this register is read/write; when bit 5 is 1, this register is read-only. The default mode is read-only.

SCPS035B – MAY 1998 – REVISED – MAY 2000 61POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PC Card 16-bit I/F legacy-mode base address register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name PC Card 16-bit I/F legacy-mode base address Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name PC Card 16-bit I/F legacy-mode base address Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Register: PC Card 16-bit I/F legacy-mode base address Type: Read-only, read/write (see individual bit descriptions) Offset: 44h (functions 0, 1) Default: 0000 0001h Description: The PCI1225 supports the index/data scheme of accessing the ExCA registers, which are mapped by this register. An address written to this register is the address for the index register and the address + 1 is the data address. Using this access method, applications requiring index/data ExCA access can be supported. The base address can be mapped anywhere in 32-bit I/O space on a word boundary; hence, bit 0 is read-only, returning 1 when read. As specified in the PCI to PCMCIA CardBus Bridge Register Description (Yenta), this register is shared by functions 0 and 1. See ExCA compatibility registers on page 83 for register offsets. system control register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name System control Type R/W R/W R/W R R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name System control Type R/W R/W R R R R R R R R/W R/W R/W R/W R R/W R/W Default 1 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 Register: System control Type: Read-only, read/write (see individual bit descriptions) Offset: 80h (functions 0, 1) Default: 0044 9060h Description: System-level initializations are performed through programming this doubleword register. Some of the bits are global and should be written only through function 0. See Table 24 for a complete description of the register contents.

62 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Table 24. System Control Register slots. Bits 31–30 are global to all PCI1225 functions. be configured as IRQSER prior to setting the INTRTIE bit. 28 RSVD R Reserved. Bit 28 is read-only and returns 0 when read. is signaled when a write occurs to power a PC Card socket. 1 = A CSC interrupt is generated on PC Card power changes.

25 SMISTATUS R/W

the SMIENB bit is set. Writing a 1 to bit 25 clears the status. 23 RSVD R Reserved. This bit is read-only and returns 0 when read.

22 CBRSVD R/W

when a CardBus card is inserted. When this bit is low (as default), these signals are 3-stated.

21 VCCPROT R/W

VCC protection enable. Bit 21 is socket dependent.

20 REDUCEZV R/W

19 CDREQEN R/W

signaling. DREQ is selected through the socket DMA register 0. 4 = PCI master; not used (default). † These bits are global and should be accessed only through function 0.

Table 24. System Control Register (Continued) 0 = Downstream memory read burst is disabled. 1 = Downstream memory read burst is enabled (default). 0 = Upstream memory read burst is disabled (default). 1 = Upstream memory read burst is enabled.

13 SOCACTIVE R

is cleared upon read of this status bit. This bit is socket dependent. 12 RSVD R Reserved. Bit 12 is read-only and returns 1 when read. 0 = Power stream is complete and delay has expired. 1 = Power stream is in progress. power-down delay has expired.

8 INTERROGATE R

interrogation completes. This bit is socket dependent. 7 RSVD R Reserved. Bit 7 is read-only and returns 0 when read. the applicable CB state machine will not be clocked. enable. Bit 5 is shared by functions 0 and 1. 0 = SSID, SSVID, ExCA ID, and revision register are read/write. 1 = SSID, SSVID, ExCA ID, and revision register are read-only (default).

2 RSVD R Reserved

Keep clock. This bit works with PCI and CB CLKRUN protocols. 1 = Does not allow CB clock or PCI clock to be stopped using the CLKRUN protocols.

0 RIMUX R/W

RI_OUT/PME multiplex enable. at the same time, RI_OUT has precedence over PME. 1 = Only PME is routed to the RI_OUT/PME terminal. † These bits are global and should be accessed only through function 0.

64 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Description: The multifunction routing register is used to configure the MFUNC0–MFUNC6 terminals. for a complete description of the register contents. Table 25. Multifunction Routing Register 31–28 RSVD R Bits 31–28 are read/only and return 0s when read.

Table 25. Multifunction Routing Register (Continued) terminal provides the SCL signaling.

66 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

terminal provides the SDA signaling.

a complete description of the register contents. Table 26. Retry Status Register

7 PCIRETRY R/W

5 TEXP_CBB R/C

CardBus target B retry expired. Write a 1 to clear bit 5. 4 RSVD R Reserved. Bit 4 returns 0 when read. CardBus target A retry expired. Write a 1 to clear bit 3. 2 RSVD R Reserved. Bit 2 returns 0 when read.

1 TEXP_PCI R/C

PCI target retry expired. Write a 1 to clear bit 1. 0 RSVD R Reserved. Bit 0 returns 0 when read. † These bits are global and should be accessed only through function 0.

68 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

complete description of the register contents. Table 27. Card Control Register Ring indicate output enable. 0 = Disables any routing of RI_OUT signal (default). RIMUX is set to 0, and for routing to MFUNC2/4. enter a high-impedance state. This bit defaults to 0.

5 PORT_SEL R/W

0 = Socket 0 takes priority, as signaled through ZVSEL0, when both sockets are in ZV mode. 1 = Socket 1 takes priority, as signaled through ZVSEL1, when both sockets are in ZV mode. 4–3 RSVD R Reserved. Bits 4–3 are read-only and default to 0.

2 AUD2MUX R/W

have AUD2MUX set, socket 0 takes precedence.

1 SPKROUTEN R/W

SPKR signal from socket 0 is exclusive ORed with the SPKR signal from socket 1 and sent to SPKROUT.

0 IFG R/C

0 = No PC Card functional interrupt detected (default). 1 = PC Card functional interrupt detected. † This bit is global and should be accessed only through function 0.

Table 28. Device Control Register 7 RSVD R Reserved. Bit 7 Returns 0 when read. 5 IO16R2 R/W Diagnostic bit. This bit defaults to 1. 4 RSVD R Reserved. Bit 4 returns 0 when read. Write transactions have no effect. 3† TEST R/W TI test. Only a 0 should be written to bit 3. 0† RSVD R/W Reserved. This read/write bit is reserved for test purposes. Only 0 should be written to this bit. † These bits are global and should be accessed only through function 0.

70 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Table 29. Diagnostic Register 6 RSVD R/W Reserved. These bits are R/W with no function.

5 CSC R/W

of ExCA 803 bit 4 is a don’t care. 4† DIAG4 R/W Diagnostic RETRY_DIS. Delayed transaction disable. 3† DIAG3 R/W Diagnostic RETRY_EXT. Extends the latency from 16 to 64. 2† DIAG2 R/W Diagnostic DISCARD_TIM_SEL_CB. Set = 210, reset = 215. 1† DIAG1 R/W Diagnostic DISCARD_TIM_SEL_PCI. Set = 210, reset = 215.

0 ASYNC R/W

Asynchronous interrupt enable. † These bits are global and should be accessed only through function 0. See Table 30 for a complete description of the register contents.

Table 30. Socket DMA Register 0 31–2 RSVD R Reserved. Bits 31–2 are read-only and return 0s when read. 00 = Socket not configured for DMA (default). complete description of the register contents. 32-bit transfers are not supported; the maximum transfer possible for 16-bit PC Cards is 16 bits. Table 31. Socket DMA Register 1 31–16 RSVD R Reserved. Bits 31–16 are read-only and return 0s when read. decode. Thus, the window is aligned to a natural 16-byte boundary. 3 EXTMODE R Extended addressing. This feature is not supported by the PCI1225 and and always returns a 0. 00 = Transfers are 8 bits (default).

0 DDMAEN R/W

SCPS035B – MAY 1998 – REVISED – MAY 2000

72 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Register: Capability ID Type: Read-only Offset: A0h Default: 01h Description: The capability ID register identifies the linked list item as the register for PCI power management. The register returns 01h when read, which is the unique ID assigned by the PCI SIG for the PCI location of the capabilities pointer and the value. next-item pointer register Bit 7 6 5 4 3 2 1 0 Name Next-item pointer Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Register: Next-item pointer Type: Read-only Offset: A1h Default: 00h Description: The next-item pointer register is used to indicate the next item in the linked list of the PCI power management capabilities. Because the PCI1225 functions include only one capabilities item, this register returns 0s when read.

Table 32. Power-Management Capabilities Register PME support. This 5-bit field indicates the power states from which the PCI1225 supports asserting PME. Bit 15 contains the value 0, indicating that PME cannot be asserted from D3cold state. Bit 14 contains the value 1, indicating that PME can be asserted from D3hot state. Bit 13 contains the value 1, indicating that PME can be asserted from D2 state. Bit 12 contains the value 1, indicating that PME can be asserted from D1 state. Bit 11 contains the value 1, indicating that PME can be asserted from the D0 state. dynamic power consumption data. 7–6 RSVD R Reserved. These bits are reserved and return 00b when read.

5 DSI R

generic class device driver is able to use it. indicates that the function supplies its own auxiliary power source.

74 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

complete description of the register contents. Table 33. Power-Management Control/Status Register

15 PMESTAT R/C

signal if PME was asserted by this function. Writing a 0 to this bit has no effect. return any dynamic data as indicated by the DYN_DATA bit. not return any dynamic data as indicated by the DYN_DATA bit. 7–2 RSVD R Reserved. Bits 7–2 are read-only and return 0s when read.

specific functionality. See Table 34 for a complete description of the register contents. Table 34. Power-Management Control/Status Register Bridge Support Extensions 7 BPCC_EN R Bus power/clock control. When read, bit 7 returns 1b. 6 B2_B3 R B2/B3 support for D3hot. ThIs bit is read-only and returns a 0 when read. 5–0 RSVD R Reserved. These bits are read-only and return 0s when read. CardBus functions do not report dynamic data.

76 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description of the register contents. Table 35. General-Purpose Event Status Register function 0 PC card controller function of the PCI1225. function 1 PC card controller function of the PCI1225. 13–12 RSVD R Reserved. These bits are read-only and return zero when read. 11 PWR_STS R/C Power change status. Bit 11 is set when software has changed the power state of either socket. A change in either VCC or VPP for either socket causes this bit to be set. 10–9 RSVD R Reserved. These bits are read-only and return zero when read. or from 12 V for either of the two PC Card sockets. 7–5 RSVD R Reserved. These bits are read-only and return zero when read. 4 GP4_STS R/C GPI4 Status. Bit 4 is set on a change in status of the MFUNC5 terminal input level. 3 GP3_STS R/C GPI3 Status. Bit 3 is set on a change in status of the MFUNC4 terminal input level . 2 GP2_STS R/C GPI2 Status. Bit 2 is set on a change in status of the MFUNC2 terminal input level. 1 GP1_STS R/C GPI1 Status. Bit 1 is set on a change in status of the MFUNC1 terminal input level. 0 GP0_STS R/C GPI0 Status. Bit 0 is set on a change in status of the MFUNC0 terminal input level.

The GPE signal is driven until the corresponding status bit is cleared and the event is serviced. description of the register contents. Table 36. General-Purpose Event Enable Register ZVENABLE in the function 0 PC Card controller function of the PCI1225. ZVENABLE in the function 1 PC Card controller function of the PCI1225. 13–12 RSVD R Reserved. These bits are read-only and return zero when read. the power state of either socket. 10–9 RSVD R Reserved. These bits are read-only and return zero when read. requested VPP level to or from 12 V for either card socket. 7–5 RSVD R Reserved. These bits are read-only and return zero when read. the MFUNC5 terminal input level if configured as GPI4. the MFUNC4 terminal input level if configured as GPI3. the MFUNC2 terminal input if configured as GPI2. the MFUNC1 terminal input if configured as GPI1. the MFUNC0 terminal input if configured as GPI0.

78 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

function 0. See Table 37 for a complete description of the register contents. Table 37. General-Purpose Input Register 15–5 RSVD R Reserved. Bits 15–5 are read-only and return 0 when read. Write transactions have no effect. MFUNC5 terminal. Write transactions have no effect. MFUNC4 terminal. Write transactions have no effect. MFUNC2 terminal. Write transactions have no effect. MFUNC1 terminal. Write transactions have no effect. MFUNC0 terminal. Write transactions have no effect.

Description: The general-purpose output register is used for control of the general-purpose outputs. Table 38. General-Purpose Output Register 15–5 RSVD R Reserved. Bits 15–5 are read-only and return 0 when read. Write transactions have no effect. MFUNC5 terminal if configured as GPO4. Read transactions return the last data value written. MFUNC4 terminal if configured as GPO3. Read transactions return the last data value written. MFUNC2 terminal if configured as GPO2. Read transactions return the last data value written. MFUNC1 terminal if configured as GPO1. Read transactions return the last data value written. MFUNC0 terminal if configured as GPO0. Read transactions return the last data value written.

80 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

address, and the read/write indicator bit must be reset. interface. See Table 39 for a complete description of the register contents. Table 39. Serial Bus Data Register 7–0 SBDATA R/W Serial bus data. This bit field represents the data byte in a read or write transaction on the serial interface. On reads, the REQBUSY bit must be polled to verify that the contents of this register are valid. with both the 7-bit slave address and the read/write indicator. the contents of the serial bus data register are valid read data from the serial bus interface. See Table 40 for a complete description of the register contents.

Table 40. Serial Bus Index Register must be programmed with both the 7-bit slave address and the read/write indicator bit. the contents of the serial bus data register are valid read data from the serial bus interface. See Table 41 for a complete description of the register contents. Table 41. Serial Bus Slave Address Register

0 RWCMD R/W

0 = A byte write access is requested to the serial bus interface. 1 = A byte read access is requested to the serial bus interface.

82 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Table 42 for a complete description of the register contents. Table 42. Serial Bus Control and Status Register

7 PROT_SEL R/W

by the PCI1225 when bit 7 is set. 6 RSVD R Reserved. Bit 6 is read-only and returns zero when read.

5 REQBUSY R

read data is valid in the serial bus data register.

4 ROMBUSY R

set during the loading of the subsystem ID and other default values from the serial bus EEPROM.

3 SBDETECT R/C

MFUNC1 terminals can be used for alternate functions such as general-purpose inputs and outputs.

2 SBTEST R/W

Serial bus test. When bit 2 is set, the serial bus clock frequency is increased for test purposes.

1 REQ_ERR R/C

a requested cycle and may be set due to a missing acknowledge. Bit 1 is cleared by a writeback of 1.

0 ROM_ERR R/C

EEPROM data format. Bit 0 is cleared by a writeback of 1.

the data from that location is returned in the data register. Figure 21. ExCA Register Access Through I/O

84 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(PCI offset 10h) at memory offset 800h. Each socket has a separate base address programmable by function. the same 4-Kbyte window at memory offset 0h. Figure 22. ExCA Register Access Through Memory are critical to the interrupt signaling are at memory address ExCA offset 803h and 805h. Access to memory mapped 16-bit PC Cards is available to the host system via five ExCA memory windows. defined by start, end, and offset addresses programmed in the ExCA registers described in this section.

Table 43. ExCA Registers and Offsets

86 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Table 43. ExCA Registers and Offsets (Continued)

82365SL-DF compatibility. See Table 44 for a complete description of the register contents. Table 44. ExCA Identification and Revision Register provided by the PCI1225. The PCI1225 supports both I/O and memory 16-bit PC cards. 5–4 RSVD R/W Reserved. Bits 5–4 can be used for Intel 82365SL-DF emulation. PCI1225. Host software can read this field to determine compatibility to the Intel 82365SL-DF register set. This field defaults to 0100b upon PCI1225 reset.

88 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PC Card interface. See Table 45 for a complete description of the register contents. Table 45. ExCA Interface Status Register 7 RSVD R Reserved. Bit 7 is read-only and returns 0 when read. Write transactions have no effect.

6 CARDPWR R

5 READY R

Ready. Bit 5 indicates the current status of the READY signal at the PC Card interface.

4 CARDWP R

0 = WP is 0. PC Card is R/W. 1 = WP is 1. PC Card is read-only.

3 CDETECT2 R

CDETECT1 to determine if a PC Card is fully seated in the socket. 0 = CD2 is 1. No PC Card is inserted. 1 = CD2 is 0. PC Card is at least partially inserted.

2 CDETECT1 R

CDETECT2 to determine if a PC Card is fully seated in the socket. 0 = CD1 is 1. No PC Card is inserted. 1 = CD1 is 0. PC Card is at least partially inserted.

applications. See Table 46 for a complete description of the register contents. Table 46. ExCA Power-Control Register

7 COE R/W

6–5 RSVD R Reserved. Bits 6–5 are read-only and return 0s when read. Write transactions have no effect. 2 RSVD R Reserved. Bit 2 is read-only and returns 0 when read. Write transactions have no effect.

90 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PC Card functions. See Table 47 for a complete description of the register contents. Table 47. ExCA Interrupt and General-Control Register

7 RINGEN R/W

6 RESET R/W

5 CARDTYPE R/W

4 CSCROUTE R/W

0 = CSC interrupts are routed by ExCA registers (default). 1 = CSC interrupts are routed to PCI interrupts. is ORed with ExCA bit 4 for backwards compatibility.

complete description of the register contents. Table 48. ExCA Card Status-Change Register 7–4 RSVD R Reserved. Bits 7–4 are read-only and return 0s when read. Write transactions have no effect.

3 CDCHANGE R

2 READYCHANGE R

When a 16-bit I/O card is installed, bit 2 is always 0.

1 BATWARN R

When a 16-bit I/O card is installed, bit 1 is always 0.

0 BATDEAD R

92 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CSC interrupt sources. See Table 49 for a complete description of the register contents. Table 49. ExCA Card Status-Change-Interrupt Configuration Register is set to 1b. In this case bit 4 of ExCA 803 is a don’t care. This is the default setting.

3 CDEN R/W

2 READYEN R/W

1 BATWARNEN R/W

Battery warning enable. Bit 1 enables/disables a battery warning condition to generate a CSC interrupt.

0 BATDEADEN R/W

of the STSCHG I/O PC Card signal to generate a CSC interrupt.

for a complete description of the register contents. Table 50. ExCA Address Window Enable Register

7 IOWIN1EN R/W

6 IOWIN0EN R/W

5 RSVD R Reserved. Bit 5 is read-only and returns 0 when read. Write transactions have no effect.

4 MEMWIN4EN R/W

3 MEMWIN3EN R/W

2 MEMWIN2EN R/W

1 MEMWIN1EN R/W

0 MEMWIN0EN R/W

94 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

for a complete description of the register contents. Table 51. ExCA

7 WAITSTATE1 R/W

effect on 8-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF . 0 = 16-bit cycles have standard length (default). 1 = 16-bit cycles are extended by one equivalent ISA wait state.

6 ZEROWS1 R/W

0 = 8-bit cycles have standard length (default). 1 = 8-bit cycles are reduced to equivalent of three ISA cycles.

5 IOSIS16W1 R/W

0 = Window data width determined by DATASIZE1, bit 4 (default). 1 = Window data width determined by IOIS16.

4 DATASIZE1 R/W

0 = Window data width is 8 bits (default). 1 = Window data width is 16 bits.

3 WAITSTATE0 R/W

0 = 16-bit cycles have standard length (default). 1 = 16-bit cycles are extended by one equivalent ISA wait state.

2 ZEROWS0 R/W

0 = 8-bit cycles have standard length (default). 1 = 8-bit cycles are reduced to equivalent of three ISA cycles.

1 IOSIS16W0 R/W

0 = Window data width is determined by DATASIZE0, bit 0 (default). 1 = Window data width is determined by IOIS16.

0 DATASIZE0 R/W

0 = Window data width is 8 bits (default). 1 = Window data width is 16 bits.

SCPS035B – MAY 1998 – REVISED – MAY 2000 95POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ExCA I/O window 0 and 1 start-address low-byte register Bit 7 6 5 4 3 2 1 0 Name ExCA I/O window 0 and 1 start-address low byte Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register: ExCA I/O window 0 start-address low byte Offset: CardBus socket address + 808h; Card A ExCA offset 08h Card B ExCA offset 48h Register: ExCA I/O window 1 start-address low byte Offset: CardBus socket address + 80Ch; Card A ExCA offset 0Ch Card B ExCA offset 4Ch Type: Read/write Default: 00h Description: These registers contain the low byte of the 16-bit I/O window start address for I/O windows 0 and 1. The eight bits of these registers correspond to the lower eight bits of the start address. ExCA I/O window 0 and 1 start-address high-byte register Bit 7 6 5 4 3 2 1 0 Name ExCA I/O window 0 and 1 start-address high byte Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register: ExCA I/O window 0 start-address high byte Offset: CardBus socket address + 809h; Card A ExCA offset 09h Card B ExCA offset 49h Register: ExCA I/O window 1 start-address high byte Offset: CardBus socket address + 80Dh; Card A ExCA offset 0Dh Card B ExCA offset 4Dh Type: Read/write Default: 00h Description: These registers contain the high byte of the 16-bit I/O window start address for I/O windows 0 and 1. The eight bits of these registers correspond to the upper eight bits of the end address.

SCPS035B – MAY 1998 – REVISED – MAY 2000

96 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ExCA I/O window 0 and 1 end-address low-byte register Bit 7 6 5 4 3 2 1 0 Name ExCA I/O window 0 and 1 end-address low byte Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register: ExCA I/O window 0 end-address low byte Offset: CardBus socket address + 80Ah; Card A ExCA offset 0Ah Card B ExCA offset 4Ah Register: ExCA I/O window 1 end-address low byte Offset: CardBus socket address + 80Eh; Card A ExCA offset 0Eh Card B ExCA offset 4Eh Type: Read/write Default: 00h Description: These registers contain the low byte of the 16-bit I/O window end address for I/O windows 0 and 1. The eight bits of these registers correspond to the lower eight bits of the end address. ExCA I/O window 0 and 1 end-address high-byte register Bit 7 6 5 4 3 2 1 0 Name ExCA I/O window 0 and 1 end-address high byte Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register: ExCA I/O window 0 end-address high byte Offset: CardBus socket address + 80Bh; Card A ExCA offset 0Bh Card B ExCA offset 4Bh Register: ExCA I/O window 1 end-address high byte Offset: CardBus socket address + 80Fh; Card A ExCA offset 0Fh Card B ExCA offset 4Fh Type: Read/write Default: 00h Description: These registers contain the high byte of the 16-bit I/O window end address for I/O windows 0 and 1. The eight bits of these registers correspond to the upper eight bits of the end address.

SCPS035B – MAY 1998 – REVISED – MAY 2000 97POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ExCA memory window 0–4 start-address low-byte register Bit 7 6 5 4 3 2 1 0 Name ExCA memory window 0–4 start-address low byte Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register: ExCA memory window 0 start-address low byte Offset: CardBus socket address + 810h; Card A ExCA offset 10h Card B ExCA offset 50h Register: ExCA memory window 1 start-address low byte Offset: CardBus socket address + 818h; Card A ExCA offset 18h Card B ExCA offset 58h Register: ExCA memory window 2 start-address low byte Offset: CardBus socket address + 820h; Card A ExCA offset 20h Card B ExCA offset 60h Register: ExCA memory window 3 start-address low byte Offset: CardBus socket address + 828h; Card A ExCA offset 28h Card B ExCA offset 68h Register: ExCA memory window 4 start-address low byte Offset: CardBus socket address + 830h; Card A ExCA offset 30h Card B ExCA offset 70h Type: Read/write Default: 00h Description: These registers contain the low byte of the 16-bit memory window start address for memory windows 0, 1, 2, 3, and 4. The eight bits of these registers correspond to bits A19–A12 of the start address.

98 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

this register. See Table 52 for a complete description of the register contents. Table 52. ExCA Memory Window 0–4 Start-Address High-Byte Register

7 DATASIZE R/W

0 = Window data width is 8 bits (default). 1 = Window data width is 16 bits.

6 ZEROWAIT R/W

0 = 8- and 16-bit cycles have standard length (default). 1 = 8-bit cycles are reduced to equivalent of three ISA cycles. 16-bit cycles are reduced to equivalent of two ISA cycles. 5–4 SCRATCH R/W Scratch pad bits. Bits 5–4 are read/write and have no effect on memory window operation.

SCPS035B – MAY 1998 – REVISED – MAY 2000 99POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ExCA memory window 0–4 end-address low-byte register Bit 7 6 5 4 3 2 1 0 Name ExCA memory window 0–4 end-address low byte Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register: ExCA memory window 0 end-address low byte Offset: CardBus socket address + 812h; Card A ExCA offset 12h Card B ExCA offset 52h Register: ExCA memory window 1 end-address low byte Offset: CardBus socket address + 81Ah; Card A ExCA offset 1Ah Card B ExCA offset 5Ah Register: ExCA memory window 2 end-address low byte Offset: CardBus socket address + 822h; Card A ExCA offset 22h Card B ExCA offset 62h Register: ExCA memory window 3 end-address low byte Offset: CardBus socket address + 82Ah; Card A ExCA offset 2Ah Card B ExCA offset 6Ah Register: ExCA memory window 4 end-address low byte Offset: CardBus socket address + 832h; Card A ExCA offset 32h Card B ExCA offset 72h Type: Read/write Default: 00h Description: These registers contain the low byte of the 16-bit memory window end address for memory windows 0, 1, 2, 3, and 4. The eight bits of these registers correspond to bits A19–A12 of the end address.

100 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Table 53 for a complete description of the register contents. Table 53. ExCA Memory Window 0–4 End-Address High-Byte Register 7–6 MEMWS R/W Wait state. Bits 7–6 specify the number of equivalent ISA wait states to be added to 16-bit memory accesses. The number of wait states added is equal to the binary value of these two bits. 5–4 RSVD R Reserved. Bits 5–4 are read-only and return 0s when read. Write transactions have no effect.

SCPS035B – MAY 1998 – REVISED – MAY 2000 101POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ExCA memory window 0–4 offset-address low-byte register Bit 7 6 5 4 3 2 1 0 Name ExCA memory window 0–4 offset-address low byte Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register: ExCA memory window 0 offset-address low byte Offset: CardBus socket address + 814h; Card A ExCA offset 14h Card B ExCA offset 54h Register: ExCA memory window 1 offset-address low byte Offset: CardBus socket address + 81Ch; Card A ExCA offset 1Ch Card B ExCA offset 5Ch Register: ExCA memory window 2 offset-address low byte Offset: CardBus socket address + 824h; Card A ExCA offset 24h Card B ExCA offset 64h Register: ExCA memory window 3 offset-address low byte Offset: CardBus socket address + 82Ch; Card A ExCA offset 2Ch Card B ExCA offset 6Ch Register: ExCA memory window 4 offset-address low byte Offset: CardBus socket address + 834h; Card A ExCA offset 34h Card B ExCA offset 74h Type: Read/write Default: 00h Description: These registers contain the low byte of the 16-bit memory window offset address for memory windows 0, 1, 2, 3 and 4. The eight bits of these registers correspond to bits A19–A12 of the offset address.

102 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Table 54. ExCA Memory Window 0–4 Offset-Address High-Byte Register

7 WINWP R/W

0 = Write operations are allowed (default). 1 = Write operations are not allowed.

6 REG R/W

0 = Memory window is mapped to common memory (default). 1 = Memory window is mapped to attribute memory.

SCPS035B – MAY 1998 – REVISED – MAY 2000 103POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ExCA I/O window 0 and 1 offset-address low-byte register Bit 7 6 5 4 3 2 1 0 Name ExCA I/O window 0 and 1 offset-address low byte Type R/W R/W R/W R/W R/W R/W R/W R Default 0 0 0 0 0 0 0 0 Register: ExCA I/O window 0 offset-address low byte Offset: CardBus socket address + 836h; Card A ExCA offset 36h Card B ExCA offset 76h Register: ExCA I/O window 1 offset-address low byte Offset: CardBus socket address + 838h; Card A ExCA offset 38h Card B ExCA offset 78h Type: Read-only, read/write Default: 00h Description: These registers contain the low byte of the 16-bit I/O window offset address for I/O windows 0 and 1. The eight bits of these registers correspond to the lower eight bits of the offset address, and bit 0 is always 0. ExCA I/O window 0 and 1 offset-address high-byte register Bit 7 6 5 4 3 2 1 0 Name ExCA I/O window 0 and 1 offset-address high byte Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register: ExCA I/O window 0 offset-address high byte Offset: CardBus socket address + 837h; Card A ExCA offset 37h Card B ExCA offset 77h Register: ExCA I/O window 1 offset-address high byte Offset: CardBus socket address + 839h; Card A ExCA offset 39h Card B ExCA offset 79h Type: Read/write Default: 00h Description: These registers contain the high byte of the 16-bit I/O window offset address for I/O windows 0 and 1. The eight bits of these registers correspond to the upper eight bits of the offset address.

104 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description of the register contents. Table 55. ExCA Card Detect and General-Control Register

7 VS2STAT R

6 VS1STAT R

5 SWCSC R/W

of this bit always returns 0.

4 CDRESUME R/W

3–2 RSVD R Reserved. Bits 3–2 are read-only and return 0s when read. Write transactions have no effect.

1 REGCONFIG R/W

0 RSVD R Reserved. Bit 0 is read-only and returns 0 when read. Write transactions have no effect.

Table 56 for a complete description of the register contents. Table 56. ExCA Global-Control Register 7–5 RSVD R Reserved. Bits 7–5 are is read-only and return 0s when read. Write transactions have no effect.

4 INTMODEB R/W

0 = Host interrupt is edge mode (default). 1 = Host interrupt is level mode.

3 INTMODEA R/W

0 = Host interrupt is edge mode (default). 1 = Host interrupt is level mode.

2 IFCMODE R/W

0 = Interrupt flags are cleared by read of CSC register (default). 1 = Interrupt flags are cleared by explicit writeback of 1.

1 CSCMODE R/W

0 = Host interrupt is edge mode (default). 1 = Host interrupt is level mode.

0 PWRDWN R/W

on the card interface. Following an active cycle, the outputs are again placed in a high-impedance state. 0 = Power-down mode is disabled (default). 1 = Power-down mode is enabled.

106 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

memory mapped, i.e., these registers can not be accessed using the index/data I/O scheme. gives the location of the socket registers in relation to the CardBus socket/ExCA base address. Figure 23. Accessing CardBus Socket Registers Through PCI Memory

Table 57. CardBus Socket Registers Table 58. Socket Event Register 31–4 RSVD R Reserved. Bits 31–4 are read-only and return 0s when read. register has changed. This bit is cleared by writing a 1. register has changed. This bit is cleared by writing a 1. register has changed. This bit is cleared by writing a 1.

0 CSTSEVENT R/C

CSTSCHG. Bit 0 is set when the CARDSTS field in the socket present-state register has changed state. transitions of CSTSCHG. This bit is reset by writing a 1.

108 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Table 59. Socket Mask Register 31–4 RSVD R Reserved. Bits 31–4 are read-only and return 0s when read.

3 PWRMASK R/W

0 = PWRCYCLE event does not cause CSC interrupt (default). 1 = PWRCYCLE event causes CSC interrupt. from causing a CSC interrupt. 00 = Insertion/removal does not cause CSC interrupt (default). 11 = Insertion/removal causes CSC interrupt.

0 CSTSMASK R/W

0 = CARDSTS event does not cause CSC interrupt (default). 1 = CARDSTS event causes CSC interrupt.

SCPS035B – MAY 1998 – REVISED – MAY 2000 109POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 socket present-state register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Socket present-state Type R R R R R R R R R R R R R R R R Default 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Socket present-state Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 X 0 0 0 X X X Register: Socket present-state Type: Read-only Offset: CardBus socket address + 08h Default: 3000 00XXh Description: The socket present-state register reports information about the socket interface. Write transactions to the socket force event register are reflected here, as well as general socket interface status. Information about PC Card V CC support and card type is only updated at each insertion. Also note that the PCI1225 uses CCD1 and CCD2 during card identification, and changes on these signals during this operation are not reflected in this register. See Table 60 for a complete description of the register contents.

110 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Table 60. Socket Present-State Register

31 YVSOCKET R

register. This bit is hardwired to 0.

30 XVSOCKET R

event register. This bit is hardwired to 0. 27–14 RSVD R Reserved. Bits 27–14 are read-only and return 0s when read. 13 YVCARD R YV card. Bit 13 indicates whether or not the PC Card inserted in the socket supports VCC = Y.Y V. 12 XVCARD R XV card. Bit 12 indicates whether or not the PC Card inserted in the socket supports VCC = X.X V. 11 3VCARD R 3-V card. Bit 11 indicates whether or not the PC Card inserted in the socket supports VCC = 3.3 V. 10 5VCARD R 5-V card. Bit 10 indicates whether or not the PC Card inserted in the socket supports VCC = 5 V.

9 BADVCCREQ R

8 DATALOST R

did not terminate properly or because write data still resides in the PCI1225.

7 NOTACARD R

not updated until a valid PC Card is inserted into the socket.

6 IREQCINT R

updated until another card interrogation sequence occurs (card insertion). until another card interrogation sequence occurs (card insertion).

3 PWRCYCLE R

2 CDETECT2 R

card interrogation are not reflected here.

1 CDETECT1 R

card interrogation are not reflected here.

0 CARDSTS R

CSTSCHG. Bit 0 reflects the current status of CSTSCHG at the PC Card interface.

Table 61. Socket Force Event Register 31–15 RSVD R Reserved. Bits 31–15 are read-only and return 0s when read. state register, and enables the socket power control. to be written. When set, this bit disables the socket power control. to be written. When set, this bit disables the socket power control. to be written. When set, this bit disables the socket power control. to be written. When set, this bit disables the socket power control. 6 RSVD R Reserved. Bit 6 is read-only and returns 0 when read. to be written, and the PWRCYCLE bit in the socket present state register is unaffected. written, and the CDETECT2 bit in the socket present state register is unaffected. written, and the CDETECT1 bit in the socket present state register is unaffected. to be written, and the CARDSTS bit in the socket present state register is unaffected.

112 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description of the register contents. Table 62. Socket Control Register 31–8 RSVD R Reserved. Bits 31–8 are read-only and return 0s when read.

7 STOPCLK R/W

CB CLKRUN protocol instructions. the PCI CLKRUN protocol is preparing to stop/slow the PCI bus clock. 1 = CB CLKRUN protocol can attempt to stop/slow the CB clock if the socket is idle. VCC control. Bits 6–4 are used to request card VCC changes. 3 RSVD R Reserved. Bit 3 is read-only and returns 0 when read. VPP control. Bits 2–0 are used to request card VPP changes.

complete description of the register contents. Table 63. Socket Power Management Register 31–26 RSVD R Reserved. Bits 31–26 are read-only and return 0s when read.

25 SKTACCES R

0 = A PC Card access has not occurred (default). 1 = A PC Card access has occurred.

24 SKTMODE R

Socket mode status. This bit provides clock mode information. 0 = Clock is operating normally. 1 = Clock frequency has changed. 23–17 RSVD R Reserved. Bits 23–17 are read-only and return 0s when read.

16 CLKCTRLEN R/W

CardBus clock control enable. When bit 16 is set, clock control (CLKCTRL bit 0) is enabled. 0 = Clock control is disabled (default). 1 = Clock control is enabled. 15–1 RSVD R Reserved. Bits 15–1 are read-only and return 0s when read.

0 CLKCTRL R/W

the CB clock during idle states. Bit 16 enables this bit. 0 = Allows CB CLKRUN protocol to stop the CB clock (default). 1 = Allows CB CLKRUN protocol to slow the CB clock by a factor of 16.

114 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

implemented as read-only and return 0s when read. Write transactions to reserved registers have no effect. Table 64. Distributed DMA Registers Description: This read/write register is used to set the starting (base) memory address of a DMA transfer. presented on AD23–AD16 of the PCI bus during the address phase.

SCPS035B – MAY 1998 – REVISED – MAY 2000 115POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DMA current address/base address register (continued) For the 16-bit DMA transfer mode, the current address register contents are presented on AD16–AD1 of the PCI bus during the address phase, and AD0 is driven to logic 0. Bits 7–1 of the page register are presented on AD23–AD17 of the PCI bus during the address phase, and bit 0 is ignored. DMA page register Bit 7 6 5 4 3 2 1 0 Name DMA page Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register: DMA page Type: Read/write Offset: DMA base address + 02h Default: 00h Description: This read/write register is used to set the upper byte of the address of a DMA transfer. Details of the address represented by this register are explained in DMA current address/base address register. DMA current count/base count register Bit 15 14 13 12 11 10 9 8 Name DMA current count/base count Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Name DMA current count/base count Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register: DMA current count/base count Type: Read/write Offset: DMA base address + 04h Default: 0000h Description: This read/write register is used to set the total transfer count, in bytes, of a direct memory transfer. Read transactions to this register indicate the current count of a direct memory transfer. In the 8-bit transfer mode, the count is decremented by 1 after each transfer, and the count is decremented by 2 after each transfer in the 16-bit transfer mode.

116 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

complete description of the register contents. Table 65. DMA Command Register 7–3 RSVD R Reserved. Bits 7–3 are read-only and return 0s when read.

2 DMAEN R/W

defaults to the enabled state. 1–0 RSVD R Reserved. Bits 1–0 are read-only and return 0s when read. Table 66 for a complete description of the register contents. Table 66. DDMA Status Register bit in the multichannel mask register has no effect on these bits. Channel terminal count. The 8327 uses bits 3–0 to indicate the TC status of each of its four DMA channels. when the TC is reached by the DMA channel. These bits are reset when read or the DMA channel is reset.

register enables software requests, and this register is to be used in block mode only. Table 67. DMA Mode Register Mode select. The PCI1225 uses bits 7–6 to determine the transfer mode.

5 INCDEC R/W

0 = Addresses increment (default).

4 AUTOINIT R/W

1–0 RSVD R Reserved. Bits 1–0 are read-only and return 0s when read.

118 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Description: This write-only register is used to reset the DDMA controller and resets all DDMA registers. Table 68 for a complete description of the register contents. Table 68. DMA Multichannel/Mask Register 7–1 RSVD R Reserved. Bits 7–1 are read-only and return 0s when read.

0 MASKBIT R

requests from the card. When cleared (or when reset), incoming DREQ assertions are serviced normally.

SCPS035B – MAY 1998 – REVISED – MAY 2000 119POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 absolute maximum ratings over operating temperature ranges (unless otherwise noted)† † Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Applies for external input and bidirectional buffers. VI > VCC does not apply to fail-safe terminals. PCI terminals are measured with respect to VCCP instead of VCC . PC Card terminals are measured with respect to VCCA or VCCB . Miscellaneous signals are measured with respect to VCCI. The limit specified applies for a dc condition. 2. Applies for external output and bidirectional buffers. VO > VCC does not apply to fail-safe terminals. PCI terminals are measured with respect to VCCP instead of VCC . PC Card terminals are measured with respect to VCCA or VCCB . Miscellaneous signals are measured with respect to VCCI. The limit specified applies for a dc condition.

SCPS035B – MAY 1998 – REVISED – MAY 2000

120 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

recommended operating conditions (see Note 3) OPERATION MIN NOM MAX UNIT VCC Core voltage Commercial 3.3 V 3 3.3 3.6 V VCCP PCI I/O clamping rail voltage Commercial 3.3 V 3 3.3 3.6 VVCCP PCI I/O clamping rail voltage Commercial 5 V 4.75 5 5.25 V VCCA PC Card I/O clamping rail voltage Commercial 3.3 V 3 3.3 3.6 VVCCA VCCB PC Card I/O clamping rail voltage Commercial 5 V 4.75 5 5.25 V VCCI Miscellaneous I/O clamping rail voltageCommercial 3.3 V 3 3.3 3.6 VVCCI Miscellaneous I/O clamping rail voltageCommercial 5 V 4.75 5 5.25 V PCI 3.3 V 0.5 VCCP VCCPPCI

5 V 2 VCCP

VIH† High-level input voltage PC Card 3.3 V 0.475 VCC(A/B) VCC(A/B) VVIH† High level in ut voltage PC Card 5 V 2.4 VCC(A/B) V MISC ‡ 2 VCCI Fail safe§ 2 VCC PCI 3.3 V 0 0.3 VCCPPCI 5 V 0 0.8 VIL† Low-level input voltage PC Card 3.3 V 0 0.325 VCC(A/B) VVIL† Low level in ut voltage PC Card 5 V 0 0.8 V MISC ‡ 0 0.8 Fail safe§ 0 0.8 PCI 0 VCCP VI Input voltage PC Card 0 VCC(A/B) VVI Input voltage MISC ‡ 0 VCCI V Fail safe§ 0 VCC PCI 0 VCC VO ¶ Output voltage PC Card 0 VCC VVO ¶ Output voltage MISC ‡ 0 VCC V Fail safe§ 0 VCC tt Input transition time (t and tf) PCI and PC Card 1 4 nstt Input transition time (tr and tf) MISC ‡ and fail safe§ 0 6 ns TA Operating ambient temperature range 0 25 70 °C TJ# Virtual junction temperature 0 25 115 °C NOTE 3: Unused terminals (input or I/O) must be held high or low to prevent them from floating. † Applies to external inputs and bidirectional buffers without hysteresis ‡ Miscellaneous terminals are 149, 150, 151, 152, 154, 155, 156, 157, 158, 159, 161, 163 for the PDV packaged device and G15, F17, E19, F14, F15, E17, D19, A16, A16, C15, C15, E14, B15 and C14 for the GHK packaged device (SUSPEND, SPKROUT, RI_OUT, multifunction terminals (MFUNC0–MFUNC6), and power switch control terminals). § Fail-safe terminals are 16, 56, 68, 74, 82, 122, 134, and 140 for the PDV packaged device and H3, P7, U8, R9, V11, M19, J18, and H17 for the GHK packaged device (card detect and voltage sense terminals). ¶ Applies to external output buffers # These junction temperatures reflect simulation conditions. The customer is responsible for verifying junction temperature.

SCPS035B – MAY 1998 – REVISED – MAY 2000 121POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER PINS OPERATION TEST CONDITIONS MIN MAX UNIT PCI 3.3 V IOH = –0.5 mA 0.9 VCCPCI 5 V IOH = –2 mA 2.4 VOH High-level output voltage PC Card 3.3 V IOH = –0.15 mA 0.9 VCC VVOH High level out ut voltage PC Card 5 V IOH = –0.15 mA 2.4 V MISC I4 m A V0 6MISC IOH = –4 mA VCC –0.6 PCI 3.3 V IOL = 1.5 mA 0.1 VCCPCI 5 V IOL = 6 mA 0.55 V Low level output voltage PC Card 3.3 V IOL = 0.7 mA 0.1 VCC VVOL Low-level output voltage PC Card 5 V IOL = 0.7 mA 0.55 V MISC IOL = 4 mA 0.5 SERR IOL = 12 mA 0.5 I 3-state, high-impedance low-level Output pins

3.6 V VI = VCC –1

3-state, high-im edance low-level output current Output pins 5.25 V VI = VCC –1 mA I 3-state, high-impedance high-level Output pins

3.6 V VI = VCC † 10

3-state, high-im edance high-level output current Output pins 5.25 V VI = VCC † 25 mA I Lll it t Input pins VI = GND –1 AIIL Low-level input current I/O pins VI = GND –10 mA Input pins

3.6 V VI = VCC ‡ 10

Input pins 5.25 V VI = VCC ‡ 20 IIH High-level input current I/O pins

3.6 V VI = VCC ‡ 10 mAIH High level in ut current

I/O pins 5.25 V VI = VCC ‡ 25 m Fail-safe pins 3.6 V VI = VCC 10 † For PCI pins, VI = VCCP . For PC Card pins, VI = VCC(A/B). For miscellaneous pins, VI = VCCI‡ For I/O pins, input leakage (IIL and IIH) includes IOZ leakage of the disabled output. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

SCPS035B – MAY 1998 – REVISED – MAY 2000

122 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PCI clock/reset timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Figure 25 and Figure 26) PARAMETER ALTERNATE SYMBOL TEST CONDITIONS MIN MAX UNIT tc Cycle time, PCLK tcyc 30 ns twH Pulse duration (width), PCLK high thigh 11 ns twL Pulse duration (width), PCLK low tlow 11 ns Dv/Dt Slew rate, PCLK tr, tf 1 4 V/ns tw Pulse duration (width), RSTIN trst 1 ms tsu Setup time, PCLK active at end of RSTIN trst-clk 100 /C0109s PCI timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Note 4 and Figure 24 and Figure 27) PARAMETER ALTERNATE SYMBOL TEST CONDITIONS MIN MAX UNIT t Propagation delay time, PCLK-to-shared signal valid delay time tval C L = 50 pF, nstpd Pro agation delay time, See Note 5 PCLK-to-shared signal invalid delay time tinv C L = 50 F, See Note 5 ns ten Enable time, high impedance-to-active delay time from PCLKton 2 ns tdis Disable time, active-to-high impedance delay time from PCLKtoff 28 ns tsu Setup time before PCLK valid tsu 7 ns th Hold time after PCLK high th 0 ns NOTES: 4. This data sheet uses the following conventions to describe time ( t ) intervals. The format is tA, where subscript A indicates the type of dynamic parameter being represented. One of the following is used: tpd = propagation delay time, td = delay time, tsu = setup time, and th = hold time. 5. PCI shared signals are AD31–AD0, C/BE3–C/BE0, FRAME , TRDY, IRDY, STOP, IDSEL, DEVSEL, and PAR.

following characteristics: PRR = 1 MHz, ZO = 50 W , tr = 6 ns. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. For tPLZ and tPHZ , VOL and VOH are measured values. Figure 24. Load Circuit and Voltage Waveforms

124 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2 V MIN Peak-to-Peak

Figure 25. PCLK Timing Waveform Figure 26. RSTIN Timing Waveforms Figure 27. Shared Signals Timing Waveforms

the Intel 82365SL-DF values. This ensures compatibility with existing software and maximizes throughput. cycles and nanoseconds for I/O and memory cycles. Table 69. PC Card Address Setup Time, t Table 70. PC Card Command Active Time, tc(A), 8-Bit PCI Cycles

01 X 23/690

11 X 23/690

Table 71. PC Card Command Active Time, tc(A), 16-Bit PCI Cycles

01 X 13/390

11 X 23/630

126 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Table 72. PC Card Address Hold Time, th(A), 8-Bit and 16-Bit PCI Cycles observed if programmed for zero wait state, 16-bit cycles) with a 33-MHz PCI clock.

Figure 28. PC Card Memory Cycle

128 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Figure 29. PC Card I/O Cycle Figure 30. Miscellaneous PC Card Delay Times

SCPS035B – MAY 1998 – REVISED – MAY 2000 129POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA GHK (S-PBGA-N257) PLASTIC BALL GRID ARRAY 14,40 TYP 1511 8 10 V U W R N P L M K T H F G E C D A B J Seating Plane 4145273–3/B 12/98 SQ16,10 15,90 0,95 0,45 0,35 0,55 0,45 0,12 0,08 0,85 1,40 MAX 0,10 0,80 M0,08 0,80 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. MicroStar BGA configuration MicroStar BGA is a trademark of Texas Instruments.

SCPS035B – MAY 1998 – REVISED – MAY 2000

130 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PDV (S-PQFP-G208) PLASTIC QUAD FLATPACK 0,13 NOM 105 104 0,27 0,17 0,25 0,45 0,75 0,05 MIN Seating Plane 4087729/B 06/96 157 208 156 SQ SQ 28,05 29,90 30,10 27,95 25,50 TYP 1,60 MAX 0,08 0,50 M0,08 0°–7° Gage Plane 1,35 1,45 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MO-136

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright  2000, Texas Instruments Incorporated