PCI1210GGU

PCI1210GGU TI1 | Alldatasheet

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SCPS032A– APRIL 1998 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI Bus Power Management Interface Specification 1.0 Compliant Advanced Configuration and Power Interface (ACPI) 1.0 Compliant Fully Compatible With the Intel 430TX (Mobile Triton II) Chipset PCI Local Bus Specification Revision 2.1 Compliant

1997 PC Card Standard Compliant

3.3-V Core Logic With Universal PCI Interfaces Compatible With 3.3-V and 5-V PCI Signaling Environments Mix-and-Match 5-V/3.3-V PC Card16 Cards and 3.3-V CardBus Cards Supports a Single PC Card or CardBus Slot With Hot Insertion and Removal Provides Interface to Parallel Single-Slot PC Card Power-Interface Switches like the TI TPS2211 Supports Burst Transfers to Maximize Data Throughput on the PCI Bus and the CardBus Bus Supports Parallel PCI Interrupts, Parallel ISA IRQ and Parallel PCI Interrupts, Serial ISA IRQ With Parallel PCI Interrupts, and Serial ISA IRQ and PCI Interrupts Serial EEPROM Interface for Loading Subsystem ID and Subsystem Vendor ID Pipelined Architecture Allows Greater Than 130M-Bytes-Per-Second Throughput From CardBus to PCI and From PCI to CardBus Supports Up to Five General-Purpose I/Os Five PCI Memory Windows and Two I/O Windows Available to the PC Card16 Socket Two I/O Windows and Two Memory Windows Available to the CardBus Socket Exchangeable Card Architecture (ExCA) Compatible Registers Are Mapped in Memory and I/O Space Intel 82365SL-DF Register Compatible Supports Distributed DMA (DDMA) and PC/PCI DMA Supports 16-Bit DMA on the PC Card Socket Supports Ring Indicate, SUSPEND, PCI CLKRUN , and CardBus CCLKRUN Supports PCI Bus Lock (LOCK) LED Activity Pin Advanced Submicron, Low-Power CMOS Technology Choice of Surface-Mount Packaging: – PGE Low-Profile Plastic Quad Flat Package (LQFP) – GGU High Density Ball Grid Array (BGA) Table of Contents PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Intel is a trademark of Intel Corporation. PC Card is a trademark of Personal Computer Memory Card International Association (PCMCIA). TI is a trademark of Texas Instruments Incorporated.

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description

The Texas Instruments PCI1210 is a high-performance PCI-to-PC Card controller that supports a single PC Card socket compliant with the 1997 PC Card Standard. The PCI1210 provides a rich feature set that makes it the best choice for bridging between PCI and PC Cards in both notebook and desktop computers. The 1997 PC Card Standard retains the 16-bit PC Card specification defined in PCMCIA Release 2.1 and defines the new 32-bit PC Card, CardBus, capable of full 32-bit data transfers at 33 MHz. The PCI1210 supports both 16-bit and CardBus PC Cards, powered at 5 V or 3.3 V, as required. The PCI1210 is compliant with the PCI Local Bus Specification 2.1, and its PCI interface can act as either a PCI master device or a PCI slave device. The PCI bus mastering is initiated during 16-bit PC Card direct memory access (DMA) transfers or CardBus PC Card bridging transactions. The PCI1210 is also compliant with the latest PCI Bus Power Management Interface Specification. All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI1210 is register compatible with the Intel 82365SL-DF ExCA controller. The PCI1210 internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. The PCI1210 can also be programmed to accept fast posted writes to improve system-bus utilization. Multiple system-interrupt signaling options are provided, including: parallel PCI, parallel ISA, serialized ISA, and serialized PCI. Furthermore, general-purpose inputs and outputs are provided for the board designer to implement sideband functions. Many other features are designed into the PCI1210, such as socket activity light-emitting diode (LED) output, that is discussed in detail throughout the design specification. An advanced complementary metal-oxide semiconductor (CMOS) process is used to achieve low system-power consumption while operating at PCI clock rates up to 33 MHz. Several low-power modes enable the host power management system to further reduce power consumption. Unused PCI1210 inputs must be pulled up using a 43 k resistor.

SCPS032A– APRIL 1998 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 system block diagram A simplified system block diagram using the PCI1210 is provided below. The PCI950 IRQ deseralizer and the PCI930 zoomed video (ZV) switch are optional functions that can be used when the system requires that capability. The PCI interface includes all address/data and control signals for PCI protocol. The 68-pin PC Card interface includes all address/data and control signals for CardBus and 16-bit (R2) protocols. When zoomed video (ZV) is enabled (in 16-bit PC Card mode) 23 of the 68 signals are redefined to support the ZV protocol. The interrupt interface includes terminals for parallel PCI, parallel ISA, and serialized PCI and ISA signaling. Other miscellaneous system interface terminals are available on the PCI1210 that include: Programmable multifunction terminals SUSPEND , RI_OUT/PME (power management control signal) SPKROUT PCI Bus PCI1210 Activity LED PCI950 IRQSER Deserializer IRQSER Interrupt Controller INTA IRQ2–15 PCI930 ZV Switch PC Card Socket TPS2211 Power Switch 4 External ZV Port VGA Controller Audio Sub-System Zoom Video Zoom Video NOTE: The PC Card interface is 68 pins for CardBus and 16-bit PC Cards. In zoomed-video mode 23 pins are used for routing the zoomed video signals to the VGA controller.

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RI_OUT /PME VCCI VCC VCC VCCD0 CCV CCPV AD20 CCV PAR C/BE1 AD14 VCCP C/BE0 AD7 VCC AD6AD6 AD5 GND VCC SUSPEND VPPD0 VPPD1 CCV CCCBV CCLK CCV CPERR CDEVSEL CTRDY CIRDY CFRAME CC/BE2 CRST CREQ CC/BE3 VCCCB GND CSERR CCLKRUN CCD2 PCI-to-CardBus Pin Diagram VCCD1 PGE LOW-PROFILE QUAD FLAT PACKAGE (BOTTOM VIEW)

SCPS032A– APRIL 1998 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 terminal assignments (continued) WP(IOIS16) RI_OUT /PME 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 CE1 FRAME VS1 STOP REQ GNT AD31 AD30 AD29 GND AD28 AD27 AD26 AD25 AD24 C/BE3 IDSEL AD23 AD21 RST PCLK GND AD19 AD18 AD17 AD16 C/BE2 IRDY TRDY DEVSEL PERR SERR AD15 AD13 AD12 GND AD11 AD10 AD9 AD8 AD4 AD3 AD2 AD1 AD0 SPKROUT MFUNC2 MFUNC3 MFUNC4 MFUNC5 MFUNC6 MFUNC0 MFUNC1 CD1 D11 GND D12 D13 D14 D15 A10 CE2 OE IORD GND A11 IOWR A17 A18 A13 A19 A20 WE A24 GND A25 D10 READY(IREQ ) BVD2(SPKR ) AD22 VCCI VCC VCC CCV CCPV AD20 CCV PAR C/BE1 AD14 VCCP C/BE0 AD7 VCC AD6AD6 AD5 GND VCC SUSPEND VPPD0 VPPD1 CCV CCCBV A16 CCV A14 A21 A22 A15 A23 A12 RESET INPACK REG VCCCB GND WAIT CD2 VS2 BVD1(STSCHG /RI) PCI-to-PC Card (16-Bit) Diagram VCCD0 VCCD1 PGE LOW-PROFILE QUAD FLAT PACKAGE (BOTTOM VIEW)

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terminal assignments (continued) 12 1310 118967 N M K L J H 423 F E C B D A G GGU BALL GRID ARRAY PACKAGE (BOTTOM VIEW) ÍÍ ÍÍ ÎÎ ÎÎ P CVCC GND Power Switch Interrupt and Miscellaneous PCI Signals CardBus Signals P P P P P P ÏÏ ÏÏ P P P P P P ÍÍ ÍÍ C C P P P P P P P P P P P P P P P P P Í Í C C C C C C C C C P P P P P P P P ÏÏ ÏÏ ÍÍ ÍÍ P P P P C C C ÍÍ ÍÍ C C C ÏÏ ÏÏ C C C C C C C C C C C C C C ÍÍ C C P P P P P P P P ÏÏ ÏÏ ÍÍ ÍÍ C C C C C C C C ÍÍ ÍÍ ÏÏ ÏÏ ÎÎ ÎÎ ÎÎ ÎÎ Î Î Î Î C C C C C Í Í C C C C C C C C C C C C C C PCI-to-CardBus and PCI-to-PC Card (16-Bit) Diagram PCI Signals Interrupt and Misc. Power Switch CardBus Signals ÏÏ ÏÏ Clamping Rails signal names and terminal assignments Signal names and their terminal assignments are shown in Table 1 through Table 4. Table 1 and Table 2 show the terminal assignments for the CardBus PC Card, and Table 3 and Table 4 show the terminal assignments for the 16-bit PC Card. Table 2 and Table 4 show the CardBus PC Card and the 16-bit PC Card terminals sorted alphanumerically by the signal name and it’s associated terminal number.

Table 1. CardBus PC Card Signal Names – Sorted by BGA Terminal Number† † The PGE (LQFP) pin numbers are shown also.

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Table 2. CardBus PC Card Signal Names – Sorted Alphabetically

Table 3. 16-Bit PC Card Signal Names – Sorted by BGA Terminal Number† † The PGE (LQFP) pin numbers are shown also.

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Table 4. 16-Bit PC Card Signal Names – Sorted Alphabetically

SCPS032A– APRIL 1998 11POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions The terminals are grouped in tables by functionality, such as PCI system function, power-supply function, etc. The terminal numbers are also listed for convenient reference. Terminal numbers are shown for both the PGE LQF package and the GGU ball grid array package. power supply TERMINAL FUNCTION NAME PGE NUMBER GGU NUMBER FUNCTION GND 6, 22, 42, 58, 78, 94, 114, 130D3, H2, L4, M8, K11, F12, C10, B6 Device ground terminals VCC 14, 30, 50, 66, 86, 102, 122, 138 F3, K2, L6, M10, H11, D12, C8, B4 Power supply terminal for core logic (3.3 V) VCCCB 90, 126 G13, A7 Rail power input for PC Card interface. Indicates card signaling environment of 5 V or 3.3 V. VCCI 63 L9 Rail power input for multifunction terminals (5 V or 3.3 V) VCCP 18, 44 G1, N4 Rail power input for PCI signaling (5 V or 3.3 V) PC Card power switch TERMINAL I/O FUNCTION NAME PIN NUMBER I/O TYPE FUNCTION NAME PGE GGU TYPE VCCD0 VCCD1 N13 M13 I Logic input controls to the TPS2211 PC Card power interface switch to control AVCC. VPPD0 VPPD1 N12 M12 I Logic input controls to the TPS2211 PC Card power interface switch to control AVPP. PCI system TERMINAL I/O FUNCTION NAME PIN NUMBER I/O TYPE FUNCTION NAME PGE GGU TYPE PCLK 21 H1 I PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled at the rising edge of PCLK. RST 20 G4 I PCI reset. When the PCI bus reset is asserted, RST causes the PCI1210 to place all output buffers in a high-impedance state and reset all internal registers. When RST is asserted, the device is completely nonfunctional. After RST is deasserted, the PCI1210 is in its default state. When SUSPEND and RST are asserted, the device is protected from RST clearing the internal registers. All outputs are placed in a high-impedance state, but the contents of the registers are preserved.

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Terminal Functions (Continued) PCI address and data TERMINAL I/O FUNCTION NAME PIN NUMBER I/O TYPE FUNCTION NAME PGE GGU TYPE AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 I/O PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the primary interface. During the address phase of a primary bus PCI cycle, AD31–AD0 contain a 32-bit address or other destination information. During the data phase, AD31–AD0 contain data. C/BE3 C/BE2 C/BE1 C/BE0 I/O PCI bus commands and byte enables. These signals are multiplexed on the same PCI terminals. During the address phase of a primary bus PCI cycle, C/BE3 –C/BE0 define the bus command. During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit data bus carry meaningful data. C/BE0 applies to byte 0 (AD7–AD0), C/BE1 applies to byte 1 (AD15–AD8), C/BE2 applies to byte 2 (AD23–AD16), and C/BE3 applies to byte 3 (AD31–AD24). PAR 36 M2 I/O PCI bus parity. In all PCI bus read and write cycles, the PCI1210 calculates even parity across the AD31–AD0 and C/BE3 –C/BE0 buses. As an initiator during PCI cycles, the PCI1210 outputs this parity indicator with a one-PCLK delay. As a target during PCI cycles, the calculated parity is compared to the initiator’s parity indicator. A compare error results in the assertion of a parity error (PERR).

SCPS032A– APRIL 1998 13POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) PCI interface control TERMINAL I/O FUNCTION NAME PIN NUMBER I/O TYPE FUNCTION NAME PGE GGU TYPE DEVSEL 32 L1 I/O PCI device select. The PCI1210 asserts DEVSEL to claim a PCI cycle as the target device. As a PCI initiator on the bus, the PCI1210 monitors DEVSEL until a target responds. If no target responds before timeout occurs, the PCI1210 terminates the cycle with an initiator abort. FRAME 28 J4 I/O PCI cycle frame. FRAME is driven by the initiator of a bus cycle. FRAME is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. When FRAME is deasserted, the PCI bus transaction is in the final data phase. GNT 2 B1 I PCI bus grant. GNT is driven by the PCI bus arbiter to grant the PCI1210 access to the PCI bus after the current data transaction has completed. GNT may or may not follow a PCI bus request, depending on the PCI bus parking algorithm. IDSEL 13 F4 I Initialization device select. IDSEL selects the PCI1210 during configuration space accesses. IDSEL can be connected to one of the upper 24 PCI address lines on the PCI bus. IRDY 29 K1 I/O PCI initiator ready. IRDY indicates the PCI bus initiator’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of PCLK where both IRDY and TRDY are asserted. Until IRDY and TRDY are both sampled asserted, wait states are inserted. PERR 34 L3 I/O PCI parity error indicator. PERR is driven by a PCI device to indicate that calculated parity does not match PAR when PERR is enabled through bit 6 of the command register. REQ 1 A1 O PCI bus request. REQ is asserted by the PCI1210 to request access to the PCI bus as an initiator. SERR 35 M1 O PCI system error. SERR is an output that is pulsed from the PCI1210 when enabled through the command register indicating a system error has occurred. The PCI1210 need not be the target of the PCI cycle to assert this signal. When SERR is enabled in the control register, this signal also pulses, indicating that an address parity error has occurred on a CardBus interface. STOP 33 L2 I/O PCI cycle stop signal. STOP is driven by a PCI target to request the initiator to stop the current PCI bus transaction. STOP is used for target disconnects and is commonly asserted by target devices that do not support burst data transfers. TRDY 31 K3 I/O PCI target ready. TRDY indicates the primary bus target’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of PCLK when both IRDY and TRDY are asserted. Until both IRDY and TRDY are asserted, wait states are inserted.

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Terminal Functions (Continued) multifunction and miscellaneous pins TERMINAL I/O FUNCTION NAME PIN NUMBER I/O TYPE FUNCTION NAME PGE GGU TYPE MFUNC0 60 K8 I/O Multifunction Terminal 0. MFUNC0 can be configured as parallel PCI interrupt INTA, GPI0, GPO0, GPE , socket activity LED output, ZV output select, CardBus audio PWM, or a parallel IRQ. Refer to the multifunction routing register description on page 61 for configuration details. MFUNC1 61 N9 I/O Multifunction Terminal 1. MFUNC1 can be configured as GPI1, GPO1, GPE, socket activity LED output, ZV output select, CardBus audio PWM, or a parallel IRQ. Refer to the multifunction routing register description on page 61 for configuration details. Serial Data (SDA). When the serial bus mode is implemented by pulling up the SCA and SCL terminals, the MFUNC1 terminal provides the SDA signaling. The two pin serial interface is used to load the subsystem identification and other register defaults from an EEPROM after a PCI reset. Refer to the serial bus interface protocol description on page 31 for details on other serial bus applications. MFUNC2 64 K9 I/O Multifunction Terminal 2. MFUNC2 can be configured as PC/PCI DMA Request, GPI2, GPO2, socket activity LED output, ZV output select, CardBus audio PWM, GPE , RI_OUT, or a parallel IRQ. Refer to the multifunction routing register description on page 61 for configuration details. MFUNC3 65 N10 I/O Multifunction Terminal 3. MFUNC3 can be configured as a parallel IRQ or the serialized interrupt signal IRQSER. Refer to the multifunction routing register description on page 61 for configuration details. MFUNC4 67 L10 I/O Multifunction Terminal 4. MFUNC4 can be configured as PCI LOCK, GPI3, GPO3, socket activity LED, RI_OUT output, ZV output select, CardBus audio PWM, GPE, or a parallel IRQ. Refer to the multifunction routing register description on page 61 for configuration details. Serial Clock (SCL). When the serial bus mode is implemented by pulling the SDA and SCL terminals, the MFUNC4 terminal provides the SCL signaling. The two pin serial interface is used to load the subsystem identification and other register defaults from an EEPROM after a PCI reset. Refer to the serial bus interface protocol description on page 31 for details on other serial bus applications. MFUNC5 68 N11 I/O Multifunction Terminal 5. MFUNC5 can be configured as PC/PCI DMA Grant, GPI4, GPO4, socket activity LED output, ZV output select, CardBus audio PWM, GPE , or a parallel IRQ. Refer to the multifunction routing register description on page 61 for configuration details. MFUNC6 69 M11 I/O Multifunction Terminal 6. MFUNC6 can be configured as a PCI CLKRUN or a parallel IRQ. Refer to the multifunction routing register description on page 61 for configuration details. RI_OUT /PME 59 L8 O Ring Indicate Out and Power Management Event Output. Provides output for either RI_OUT or PME signals. SUSPEND 70 L11 I Suspend. SUSPEND is used to protect the internal registers from clearing when the RST signal is asserted. See suspend mode on page 39 for details. SPKROUT 62 M9 O Speaker output. SPKROUT is the output to the host system that can carry SPKR or CAUDIO through the PCI1210 from the PC Card interface. SPKROUT is driven as the exclusive-OR combination of card SPKR //CAUDIO inputs.

SCPS032A– APRIL 1998 15POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) The address and data and interface control terminals for the 16-bit PC Card are shown in the following two tables. 16-bit PC Card address and data TERMINAL I/O FUNCTION NAME PIN NUMBER I/O TYPE FUNCTION NAME PGE GGU TYPE A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 116 113 111 109 107 105 103 100 108 110 104 101 112 115 118 120 121 124 127 128 129 A10 D10 B11 A13 B13 C12 D11 E10 E12 B12 A12 C13 D13 A11 F11 G12 E13 E11 B10 O PC Card address. 16-bit PC Card address lines. A25 is the most-significant bit. D15 D14 D13 D12 D11 D10 144 142 140 143 141 139 H12 J13 J11 K13 K10 H10 J12 J10 K12 L13 I/O PC Card data. 16-bit PC Card data lines. D15 is the most-significant bit.

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21Terminal Functions (Continued) 16-bit PC Card interface control TERMINAL I/O FUNCTION NAME PIN NUMBER I/O TYPE FUNCTION NAME PGE GGU TYPE BVD1 (STSCHG /RI) 135 C5 I Battery voltage detect 1. BVD1 is generated by 16-bit memory PC Cards that include batteries. BVD1 is used with BVD2 as an indication of the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are kept high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and should be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost. See ExCA card status-change interrupt configuration register on page 89 for enable bits. See ExCA card status-change register on page 88 and the ExCA interface status register on page 85 for the status bits for this signal. Status change. STSCHG is used to alert the system to a change in the READY, write protect, or battery voltage dead condition of a 16-bit I/O PC Card. Ring indicate. RI is used by 16-bit modem cards to indicate a ring detection. BVD2 (SPKR ) 134 B5 I Battery voltage detect 2. BVD2 is generated by 16-bit memory PC Cards that include batteries. BVD2 is used with BVD1 as an indication of the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and should be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost. See ExCA card status-change interrupt configuration register on page 89 for enable bits. See ExCA card status-change register on page 88 and the interface status register on page 85 for the status bits for this signal. Speaker. SPKR is an optional binary audio signal available only when the card and socket have been configured for the 16-bit I/O interface. The audio signals from cards A and B are combined by the PCI1210 and are output on SPKROUT. DMA request. BVD2 can be used as the DMA request signal during DMA operations to a 16-bit PC Card that supports DMA. The PC Card asserts BVD2 to indicate a request for a DMA operation. CD1 CD2 137 L12 A4 I PC Card detect 1 and PC Card detect 2. CD1 and CD2 are internally connected to ground on the PC Card. When a PC Card is inserted into a socket, CD1 and CD2 are pulled low. For signal status, see interface status register information in Table 42. CE1 CE2 H13 G11 O Card enable 1 and card enable 2. CE1 and CE2 enable even- and odd-numbered address bytes. CE1 enables even-numbered address bytes, and CE2 enables odd-numbered address bytes. INPACK 123 B8 I Input acknowledge. INPACK is asserted by the PC Card when it can respond to an I/O read cycle at the current address. DMA request. INPACK can be used as the DMA request signal during DMA operations from a 16-bit PC Card that supports DMA. If used as a strobe, the PC Card asserts this signal to indicate a request for a DMA operation. IORD 93 F13 O I/O read. IORD is asserted by the PCI1210 to enable 16-bit I/O PC Card data output during host I/O read cycles. DMA write. IORD is used as the DMA write strobe during DMA operations from a 16-bit PC Card that supports DMA. The PCI1210 asserts IORD during DMA transfers from the PC Card to host memory. IOWR 96 F10 O I/O write. IOWR is driven low by the PCI1210 to strobe write data into 16-bit I/O PC Cards during host I/O write cycles. DMA read. IOWR is used as the DMA write strobe during DMA operations from a 16-bit PC Card that supports DMA. The PCI1210 asserts IOWR during transfers from host memory to the PC Card. OE 92 G10 O Output enable. OE is driven low by the PCI1210 to enable 16-bit memory PC Card data output during host memory read cycles. DMA terminal count. OE is used as terminal count (TC) during DMA operations to a 16-bit PC Card that supports DMA. The PCI1210 asserts OE to indicate TC for a DMA write operation.

SCPS032A– APRIL 1998 17POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) 16-bit PC Card interface control (continued) TERMINAL I/O FUNCTION NAME PIN NUMBER I/O TYPE FUNCTION NAME PGE GGU TYPE READY (IREQ) 132 D6 I Ready. The ready function is provided by READY when the 16-bit PC Card and the host socket are configured for the memory-only interface. READY is driven low by the 16-bit memory PC Cards to indicate that the memory card circuits are busy processing a previous write command. READY is driven high when the 16-bit memory PC Card is ready to accept a new data transfer command. Interrupt request. IREQ is asserted by a 16-bit I/O PC Card to indicate to the host that a device on the 16-bit I /O PC Card requires service by the host software. IREQ is high (deasserted) when no interrupt is requested. REG 125 B7 O Attribute memory select. REG remains high for all common memory accesses. When REG is asserted, access is limited to attribute memory (OE or WE active) and to the I/O space (IORD or IOWR active). Attribute memory is a separately accessed section of card memory and is generally used to record card capacity and other configuration and attribute information. DMA acknowledge. REG is used as a DMA acknowledge (DACK) during DMA operations to a 16-bit PC Card that supports DMA. The PCI1210 asserts REG to indicate a DMA operation. REG is used in conjunction with the DMA read (IOWR) or DMA write (IORD) strobes to transfer data. RESET 119 B9 O PC Card reset. RESET forces a hard reset to a 16-bit PC Card. WAIT 133 A5 I Bus cycle wait. WAIT is driven by a 16-bit PC Card to delay the completion of (i.e., extend) the memory or I/O cycle in progress. WE 106 C11 O Write enable. WE is used to strobe memory write data into 16-bit memory PC Cards. WE is also used for memory PC Cards that employ programmable memory technologies. DMA terminal count. WE is used as TC during DMA operations to a 16-bit PC Card that supports DMA. The PC1210 asserts WE to indicate TC for a DMA read operation. WP (IOIS16) 136 D5 I Write protect. WP applies to 16-bit memory PC Cards. WP reflects the status of the write-protect switch on 16-bit memory PC Cards. For 16-bit I/O cards, WP is used for the 16-bit port (IOIS16) function. I/O is 16 bits. IOIS16 applies to 16-bit I/O PC Cards. IOIS16 is asserted by the 16-bit PC Card when the address on the bus corresponds to an address to which the 16-bit PC Card responds, and the I/O port that is addressed is capable of 16-bit accesses. DMA request. WP can be used as the DMA request signal during DMA operations to a 16-bit PC Card that supports DMA. If used, the PC Card asserts WP to indicate a request for a DMA operation. VS1 VS2 131 117 I/O Voltage sense 1 and voltage sense 2. VS1 and VS2, when used in conjunction with each other, determine the operating voltage of the 16-bit PC Card.

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Terminal Functions (Continued) The interface system, address and data, and interface control terminals for the CardBus PC Card system are shown in the following three tables. CardBus PC Card interface system TERMINAL I/O FUNCTION NAME PIN NUMBER I/O TYPE FUNCTION NAME PGE GGU TYPE CCLK 108 B12 O CardBus PC Card clock. CCLK provides synchronous timing for all transactions on the CardBus interface. All signals except CRST, CLKRUN , CINT, CSTSCHG, CAUDIO, CCD2:1 , and CVS2–CVS1 are sampled on the rising edge of CCLK, and all timing parameters are defined with the rising edge of this signal. CCLK operates at the PCI bus clock frequency, but it can be stopped in the low state or slowed down for power savings. CCLKRUN 136 D5 O CardBus PC Card clock run. CCLKRUN is used by a CardBus PC Card to request an increase in the CCLK frequency, and by the PCI1210 to indicate that the CCLK frequency is going to be decreased. CRST 119 B9 I/O CardBus PC Card reset. CRST is used to bring CardBus PC Card-specific registers, sequencers, and signals to a known state. When CRST is asserted, all CardBus PC Card signals must be 3-stated, and the PCI1210 drives these signals to a valid logic level. Assertion can be asynchronous to CCLK, but deassertion must be synchronous to CCLK.

SCPS032A– APRIL 1998 19POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) CardBus PC Card address and data TERMINAL I/O FUNCTION NAME PIN NUMBER I/O TYPE FUNCTION NAME PGE GGU TYPE CAD31 CAD30 CAD29 CAD28 CAD27 CAD26 CAD25 CAD24 CAD23 CAD22 CAD21 CAD20 CAD19 CAD18 CAD17 CAD16 CAD15 CAD14 CAD13 CAD12 CAD11 CAD10 CAD9 CAD8 CAD7 CAD6 CAD5 CAD4 CAD3 CAD2 CAD1 CAD0 144 142 141 140 139 129 128 127 124 121 120 118 116 115 113 A10 B10 D10 E12 F10 E13 F13 F11 G10 G11 G12 H12 H10 J11 J12 K13 J10 K10 K12 L13 I/O PC Card address and data. These signals make up the multiplexed CardBus address and data bus on the CardBus interface. During the address phase of a CardBus cycle, CAD31–CAD0 contain a 32-bit address. During the data phase of a CardBus cycle, CAD31–CAD0 contain data. CAD31 is the most-significant bit. CC/BE3 CC/BE2 CC/BE1 CC/BE0 I/O CardBus bus commands and byte enables. CC/BE3–CC/BE0 are multiplexed on the same CardBus terminals. During the address phase of a CardBus cycle, CC/BE3–CC/BE0 defines the bus command. During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit data bus carry meaningful data. CC/BE0 applies to byte 0 (CAD7–CAD0), CC/BE1 applies to byte 1 (CAD15–CAD8), CC/BE2 applies to byte 2 (CAD23–CAD16), and CC/BE3 applies to byte 3 (CAD31–CAD24). CPAR 101 D13 I/O CardBus parity. In all CardBus read and write cycles, the PCI1210 calculates even parity across the CAD and CC/BE buses. As an initiator during CardBus cycles, the PCI1210 outputs CPAR with a one-CCLK delay. As a target during CardBus cycles, the calculated parity is compared to the initiator’s parity indicator; a compare error results in a parity error assertion.

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Terminal Functions (Continued) CardBus PC Card interface control TERMINAL I/O FUNCTION NAME PIN NUMBER I/O TYPE FUNCTION NAME PGE GGU TYPE CAUDIO 134 B5 I CardBus audio. CAUDIO is a digital input signal from a PC Card to the system speaker. The PCI1210 supports the binary audio mode and outputs a binary signal from the card to SPKROUT. CBLOCK 103 D11 I/O CardBus lock. CBLOCK is used to gain exclusive access to a target. CCD1 75 L12 I CardBus detect 1 and CardBus detect 2. CCD1 and CCD2 are used in conjunction with CVS1 and CVS2 to identify card insertion and interrogate cards to determine the operating voltage and cardCCD1 CCD2 137 L12 A4 I CVS2 to identify card insertion and interrogate cards to determine the operating voltage and card type. CDEVSEL 107 B13 I/O CardBus device select. The PCI1210 asserts CDEVSEL to claim a CardBus cycle as the target device. As a CardBus initiator on the bus, the PCI1210 monitors CDEVSEL until a target responds. If no target responds before timeout occurs, the PCI1210 terminates the cycle with an initiator abort. CFRAME 111 B11 I/O CardBus cycle frame. CFRAME is driven by the initiator of a CardBus bus cycle. CFRAME is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. When CFRAME is deasserted, the CardBus bus transaction is in the final data phase. CGNT 106 C11 I CardBus bus grant. CGNT is driven by the PCI1210 to grant a CardBus PC Card access to the CardBus bus after the current data transaction has been completed. CINT 132 D6 I CardBus interrupt. CINT is asserted low by a CardBus PC Card to request interrupt servicing from the host. CIRDY 110 A12 I/O CardBus initiator ready. CIRDY indicates the CardBus initiator’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of CCLK when both CIRDY and CTRDY are asserted. Until CIRDY and CTRDY are both sampled asserted, wait states are inserted. CPERR 104 C13 I/O CardBus parity error. CPERR is used to report parity errors during CardBus transactions, except during special cycles. It is driven low by a target two clocks following that data when a parity error is detected. CREQ 123 B8 I CardBus request. CREQ indicates to the arbiter that the CardBus PC Card desires use of the CardBus bus as an initiator. CSERR 133 A5 I CardBus system error. CSERR reports address parity errors and other system errors that could lead to catastrophic results. CSERR is driven by the card synchronous to CCLK, but deasserted by a weak pullup, and may take several CCLK periods. The PCI1210 can report CSERR to the system by assertion of SERR on the PCI interface. CSTOP 105 C12 I/O CardBus stop. CSTOP is driven by a CardBus target to request the initiator to stop the current CardBus transaction. CSTOP is used for target disconnects, and is commonly asserted by target devices that do not support burst data transfers. CSTSCHG 135 C5 I CardBus status change. CSTSCHG is used to alert the system to a change in the card’s status, and is used as a wake-up mechanism. CTRDY 109 A13 I/O CardBus target ready. CTRDY indicates the CardBus target’s ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of CCLK, when both CIRDY and CTRDY are asserted; until this time, wait states are inserted. CVS1 131 C6 I/O CardBus voltage sense 1 and CardBus voltage sense 2. CVS1 and CVS2 are used in conjunction with CCD1 and CCD2 to identify card insertion and interrogate cards to determine the operatingCVS2 117 D9 I/O w ith CCD1 and CCD2 to identify card insertion and interrogate cards to determine the operating voltage and card type.

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peripheral component interconnect (PCI) interface The PCI1210 is fully compliant with the PCI Local Bus Specification Rev. 2.1. The PCI1210 provides all required signals for PCI master or slave operation, and may operate in either a 5–V of 3.3–V signaling environment by connecting the V CCP terminals to the desired voltage level. In addition to the mandatory PCI signals the PCI1210 provides the optional interrupt signal INTA. PCI bus lock (LOCK) The bus-locking protocol defined in the PCI specification is not highly recommended, but is provided on the PCI1210 as an additional compatibility feature. The PCI LOCK signal can be routed to the MFUNC4 terminal via the multifunction routing register, see the multifunction routing register description on page 61 for details. Note that the use of LOCK is only supported by PCI-to-CardBus bridges in the downstream direction (away from the processor). PCI LOCK indicates an atomic operation that may require multiple transactions to complete. When LOCK is asserted, nonexclusive transactions can proceed to an address that is not currently locked. A grant to start a transaction on the PCI bus does not guarantee control of LOCK ; control of LOCK is obtained under its own protocol. It is possible for different initiators to use the PCI bus while a single master retains ownership of LOCK. Note that the CardBus signal for this protocol is CBLOCK to avoid confusion with the bus clock. An agent may need to do an exclusive operation because a critical access to memory might be broken into several transactions, but the master wants exclusive rights to a region of memory. The granularity of the lock is defined by PCI to be 16 bytes, aligned. The lock protocol defined by PCI allows a resource lock without interfering with nonexclusive real-time data transfer, such as video. The PCI bus arbiter may be designed to support only complete bus locks using the LOCK protocol. In this scenario, the arbiter will not grant the bus to any other agent (other than the LOCK master) while LOCK is asserted. A complete bus lock may have a significant impact on the performance of the video. The arbiter that supports complete bus lock must grant the bus to the cache to perform a writeback due to a snoop to a modified line when a locked operation is in progress. The PCI1210 supports all LOCK protocol associated with PCI-to-PCI bridges, as also defined for PCI-to-CardBus bridges. This includes disabling write posting while a locked operation is in progress, which can solve a potential deadlock when using devices such as PCI-to-PCI bridges. The potential deadlock can occur if a CardBus target supports delayed transactions and blocks access to the target until it completes a delayed read. This target characteristic is prohibited by the 2.1 PCI Specification, and the issue is resolved by the PCI master using LOCK loading subsystem identification The subsystem vendor ID register and subsystem ID register make up a doubleword of PCI configuration space located at offset 40h. This doubleword register is used for system and option card (mobile dock) identification purposes and is required by some operating systems. Implementation of this unique identifier register is a PC ’97 requirement. The PCI1210 offers two mechanisms to load a read-only value into the subsystem registers. The first mechanism relies upon the system BIOS providing the subsystem ID value. The default access mode to the subsystem registers is read only, but can be made read/write by setting the SUBSYSRW bit in the system control register (bit 5, at PCI offset 80h). Once this bit is set, the BIOS can write a subsystem identification value into the registers at offset 40h. The BIOS must clear the SUBSYSRW bit such that the subsystem vendor ID register and subsystem ID register is limited to read-only access. This approach saves the added cost of implementing the serial electrically erasable programmable ROM (EEPROM).

SUSPEND ) input gates the PCI reset from the entire PCI1210 core, including the serial bus state machine. The PCI1210 provides a two-line serial bus host controller that can be used to interface to a serial EEPROM. Refer to serial bus interface on page 30 for details on the two-wire serial bus controller and applications. interrogation, card voltage requirements and interface (16 bit versus CardBus) are determined. configuration of these four terminals identifies the card type and voltage requirements of the PC Card interface. The encoding scheme is defined in the 1997 PC Card Standard and is shown in Table 5. Table 5. PC Card Card-Detect and Voltage-Sense Connections

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The PCI1210 provides a P2C (PCMCIA peripheral control) interface for control of the PC Card power switch. a typical application, where the PCI1210 represents the PC Card controller. Figure 2. TPS2211 Terminal Assignments network. Application of this power switch would be similar to the TPS2211. Figure 3. TPS2211 Typical Application for PC Card configuration. Figure 4 illustrates a PCI1210 ZV implementation.

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Figure 6 provides an illustration of a sample application using SPKROUT and CAUDPWM. Figure 6. Sample Application of SPKROUT and CAUDPWM configuring the multifunction terminals. it is left for the board designer to implement the circuit that best fits the application. CFRAME , CIRDY, or CREQ is active.

Figure 7. Two Sample LED Circuits in the D2 or D1 power state. driven. If socket activity is frequent (at least once every 64 ms), the LED signal remains driven. register configuration is provided in Table 6. accompanying register descriptions for details. Table 6. Distributed DMA Registers

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PC Card16 Distributed DMA support (continued) The DDMA registers contain control and status information consistent with the 8237 DMA controller; however, the register locations are reordered and expanded in some cases. While the DDMA register definitions are identical to those in the 8237 DMA controller of the same name, some register bits defined in the 8237 DMA controller do not apply to distributed DMA in a PCI environment. In such cases, the PCI1210 implements these obsolete register bits as read-only, nonfunctional bits. The reserved registers shown in Table 6 are implemented as read only and return zeros when read. Writes to reserved registers have no effect. The DDMA transfer is prefaced by several configuration steps that are specific to the PC Card and must be completed after the PC Card is inserted and interrogated. These steps include setting the proper DREQ signal assignment, setting the data transfer width, and mapping and enabling the DDMA register set. As discussed above, this is done through socket DMA register 0 and socket DMA register 1. The DMA register set is then programmed similarly to an 8237 controller, and the PCI1210 awaits a DREQ assertion from the PC Card requesting a DMA transfer. DMA writes transfer data from the PC Card to PCI memory addresses. The PCI1210 accepts data 8 or 16 bits at a time, depending on the programmed data width, and then requests access to the PCI bus by asserting its REQ signal. Once granted, the PCI bus returns to an idle state. The PCI1210 initiates a PCI memory write command to the current memory address and transfers the data in a single data phase. After terminating the PCI cycle, the PCI1210 accepts the next byte(s) from the PC Card until the transfer count expires. DMA reads transfer data from PCI memory addresses to the PC Card application. Upon the assertion of DREQ the PCI1210 asserts REQ to acquire the PCI bus. Once granted and the bus is idle, the PCI1210 initiates a PCI memory read operation to the current memory address and accepts 8 or 16 bits of data, depending on the programmed data width. After terminating the PCI cycle, the data is passed onto the PC Card. After terminating the PC Card cycle, the PCI1210 requests access to the PCI bus again until the transfer count has expired. The PCI1210 target interface acts normally during this procedure, and accepts I/O reads and writes to the DDMA registers. While a DDMA transfer is in progress and the host resets the DMA channel, the PCI1210 asserts TC and ends the PC Card cycle(s). TC is indicated in the DDMA status register. At the PC Card interface, the PCI1210 supports demand mode transfers. The PCI1210 asserts DACK during the transfer unless DREQ is deasserted before TC. TC is mapped to the OE PC Card terminal for DMA write operations, and is mapped to the WE PC Card terminal for DMA read operations. The DACK signal is mapped to the PC Card REG signal in all transfers, and the DREQ terminal is routed to one of three options, which is programmed through socket DMA register 0. PC Card-16 PC/PCI DMA Some chipsets provide a way for legacy I/O devices to do DMA transfers on the PCI bus. In the PC/PCI DMA protocol, the PCI1210 acts as a PCI target device to certain DMA related I/O addresses. The PCI1210 PCREQ and PCGNT signals are provided as a point-to-point connection to a chipset supporting PC/PCI DMA. The PCREQ and PCGNT signals may be routed to the MFUNC2 and MFUNC5 terminals, respectively. Refer to the multifunction routing register description on page 61 for details on configuring the multifunction terminals. Under the PC/PCI protocol, a PCI DMA slave device (such as the PCI1210) requests a DMA transfer on a particular channel using a serialized protocol on PCREQ. The I/O DMA bus master arbitrates for the PCI bus, and grants the channel through a serialized protocol on PCGNT when it is ready for the transfer. The I/O cycle and memory cycles are then presented on the PCI bus which perform the DMA transfers similarly to legacy DMA master devices. PC/PCI DMA is enabled for the PC Card-16 slot by setting bit 19 in the respective system control register. On power up this bit is reset and the card PC/PCI DMA is disabled. Bit 3 of the system control register is a global enable for PC/PCI DMA, and is set at power-up and never cleared if the PC/PCI DMA mechanism is implemented. The desired DMA channel for the PC Card-16 slot must be configured through bits 18–16 in the system control register. The channels are configured as indicated in Table 7.

Table 7. PC/PCI Channel Assignments register 0. The data transfer width is a function of channel number, and the DDMA slave registers are not used. addresses listed in Table 8 and performs actions dependent upon the address. Table 8. I/O Addresses Used for PC/PCI DMA scheme is often referred to as centralized DMA for this reason. specification. These registers exist as the CardBus socket registers, and are listed in Table 9. Table 9. CardBus Socket Registers

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the system control register is set. The SBDETECT bit is cleared by a write back of 1. 2C. An example application implementing the two–wire serial bus is illustrated in Figure 8. Figure 8. Serial EEPROM Application switches are discussed in the sections that follow. Figure 8. The PCI1210 supports up to 100 kb/s data transfer rate and is compatible with standard mode I interpreted as control signals, that is, a start or a stop condition.

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Figure 11. Serial Bus Protocol – Byte Write during read data transfers. The SCL signal remains driven by the PCI1210 master. Figure 12. Serial Bus Protocol – Byte Read be loaded with defaults through the EEPROM are provided in Table 10. Table 10. Registers and Bits Loadable Through Serial EEPROM ROM_ERR bit in the serial bus control and status register.

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illustrates the registers used to program a serial bus device through software. Table 11. PCI1210 Registers Used to Program Serial Bus Devices is not used in the quick command protocol. command selector are programmed through this register. Read data valid, general busy, and general error status are communicated through this register. In addition, the protocol select bit is programmed through this register. functions, and the CardBus socket register set provides interrupt control for the CardBus PC Card functions. registers have been defined where required. Card interrupts are classified as either card status change (CSC) or as functional interrupts. by 16-bit I/O PC Cards and by CardBus PC Cards. include both card insertion and removal from PC Card sockets, as well as transitions of certain PC Card signals.

Table 12. Interrupt Mask and Flag Registers independent of the card type. Table 13 describes the PC Card interrupt events. Table 13. PC Card Interrupt Events and Description power-up cycle has completed.

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PC Card functional and card status change interrupts (continued) The naming convention for PC Card signals describes the function for 16-bit memory and I/O cards, as well as CardBus. For example, READY(IREQ)//CINT includes READY for 16-bit memory cards, IREQ for 16-bit I/O cards, and CINT for CardBus cards. The 16-bit memory card signal name is first, with the I/O card signal name second, enclosed in parentheses. The CardBus signal name follows after a forward double slash (//). The PC Card standard describes the power-up sequence that must be followed by the PCI1210 when an insertion event occurs and the host requests that the socket VCC and VPP be powered. Upon completion of this power-up sequence, the PCI1210 interrupt scheme can be used to notify the host system (see Table 13), denoted by the power cycle complete event. This interrupt source is considered a PCI1210 internal event because it does not depend on a signal change at the PC Card interface, rather the completion of applying power to the socket. interrupt masks and flags Host software may individually mask (or disable) most of the potential interrupt sources listed in Table 13 by setting the appropriate bits in the PCI1210. By individually masking the interrupt sources listed, software can control those events that cause a PCI1210 interrupt. Host software has some control over the system interrupt the PCI1210 asserts by programming the appropriate routing registers. The PCI1210 allows host software to route PC Card CSC and PC Card functional interrupts to separate system interrupts. A discussion of interrupt routing is somewhat specific to the interrupt signaling method used, and is discussed in more detail in the following sections. When an interrupt is signaled by the PCI1210, the interrupt service routine must determine which of the events in Table 12 caused the interrupt. Internal registers in the PCI1210 provide flags that report the source of an interrupt. By reading these status bits, the interrupt service routine can determine the action to be taken. Table 12 details the registers and bits associated with masking and reporting potential interrupts. All interrupts can be masked except the functional PC Card interrupts, and an interrupt status flag is available for all types of interrupts. Notice that there is not a mask bit to stop the PCI1210 from passing PC Card functional interrupts through to the appropriate interrupt scheme. These interrupts are not valid until the card is properly powered, and there should never be a card interrupt that does not require service after proper initialization. There are various methods of clearing the interrupt flag bits listed in Table 12. The flag bits in the ExCA registers (16-bit PC Card-related interrupt flags) can be cleared using two different methods. One method is an explicit write of 1 to the flag bit to clear, and the other is by reading the flag bit register. The selection of flag bit clearing is made by bit 2 in the global control register (ExCA offset 1Eh/81Eh), and defaults to the flag cleared on read method. The CardBus-related interrupt flags can be cleared by an explicit write of 1 to the interrupt flag in the socket event register. Although some of the functionality is shared between the CardBus registers and the ExCA registers, software should not program the chip through both register sets when a CardBus card is functioning. using parallel IRQ interrupts The seven multifunction terminals, MFUNC6:0, implemented in the PCI1210 may be routed to obtain a subset of the ISA IRQs . The IRQ choices provide ultimate flexibility in PC Card host interruptions. To use the parallel ISA type IRQ interrupt signaling, software must program the device control register, located at PCI offset 92h, to select the parallel IRQ signaling scheme. Refer to the multifunction routing register description on page 61 for details on configuring the multifunction terminals. A system using parallel IRQs requires (at a minimum) one PCI terminal, INTA, to signal CSC events. This requirement is dictated by certain card and socket services software. The INTA requirement calls for routing the MFUNC0 terminal for INTA signaling. This leaves (at a maximum) six different IRQs to support legacy 16-bit PC Card functions.

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Table 14. SMI Control SMIROUTE SMI route. This shared bit controls whether the SMI interrupts are sent as a CSC interrupt or as IRQ2. SMISTAT SMI status. This bit is set when an SMI interrupt is pending. This status flag is cleared by writing back a 1. SMIENB SMI interrupt mode enable. When set, SMI interrupt generation is enabled. level or edge mode depending upon the CSCMODE bit in the ExCA global control register. MFUNC1, MFUNC3 or MFUNC6 through the multifunction routing register. The PCI CLKRUN feature is the primary method of power management on the PCI interface of the PCI1210. The KEEPCLK bit in the system control register is set. The PC Card-16 resource manager is busy. The PCI1210 CardBus master state machine is busy. A cycle may be in progress on CardBus. The PCI1210 master is busy. There may be posted data from CardBus to PCI in the PCI1210. There are pending interrupts. The CardBus CCLK has not been stopped by the PCI1210 PCI CCLKRUN manager. A PC Card-16 IREQ or a CardBus CINT has been asserted by either card. A CardBus wakeup (CSTSCHG) or PC Card-16 STSCHG/RI event occurs. A CardBus card attempts to start the CCLK using CCLKRUN. A CardBus card arbitrates for the CardBus bus using CREQ. A 16-bit DMA PC Card asserts DREQ. CardBus interface to control this clock management. COE bit three states the card interface to save power. The power savings when using this feature are minimal. bit is an automatic COE, that is, the PWRDOWN performs the COE function when there is no card activity.

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Figure 17. Signal Diagram of Suspend Function A powered down CardBus card asserts CSTSCHG (CBWAKE) requesting system and interface wake up. A CSC event occurs, such as insertion/removal of cards, battery voltage levels. description of CSC interrupt masks and flags.

Figure 18. RI_OUT Functional Diagram mask bit, CSTSMASK, is programmed through the socket mask register in the CardBus socket registers. software-visible power-management states that result in varying levels of power savings. power state of the originating bridge device. access to a capabilities list.

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Table 15. Power-Management Registers register that can provide dynamic data. compliant with ACPI design rules. bits are implemented as defined by ACPI, and illustrated in Figure 19. Figure 19. Block Diagram of a Status/Enable Cell in some level of power state to report events.

header for each PCI1210 function. the configuration space and the user-definable registers. Table 16. PCI Configuration Registers

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Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Vendor ID Type R R R R R R R R R R R R R R R R Default 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0 Register: Vendor ID Type: Read only Offset: 00h Default: 104Ch Description: This 16-bit read-only register contains a value allocated by the PCI SIG (special interest group) and identifies the manufacturer of the PCI device. The vendor ID assigned to TI is 104Ch. device ID register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Device ID Type R R R R R R R R R R R R R R R R Default 1 0 1 0 1 1 0 0 0 0 0 1 1 0 1 0 Register: Device ID Type: Read only Offset: 02h Default: AC1Ah Description: This 16-bit read-only register contains a value assigned to the PCI1210 by TI. The device identification for the PCI1210 is AC1A. command register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Command Type R R R R R R R R/W R R/W R R R R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Command Type: Read only, read/write (see individual bit descriptions) Offset: 04h Default: 0000h Description: The command register provides control over the PCI1210 interface to the PCI bus. All bit functions adhere to the definitions in PCI Local Bus Specification 2.1. See Table 17 for the complete description of the register contents.

Table 17. Command Register 15–10 RSVD R Reserved. Bits 15–10 are read only and return 0s when read. Writes have no effect. 9 is read only and returns 0s when read.

8 SERR_EN R/W

for the PCI1210 to report address parity errors. hardwired to 0. Writes to this bit have no effect.

6 PERR_EN R/W

5 VGA_EN R

5 is read only and returns 0 when read. Writes to this bit have no effect.

4 MWI_EN R

and returns 0 when read. Writes to this bit have no effect.

3 SPECIAL R

0 when read. Writes to this bit have no effect.

2 MAST_EN R/W

PCI1210 can take control of the PCI bus only when this bit is set.

1 MEM_EN R/W

Memory space enable. Bit 1 controls whether or not the PCI1210 can claim cycles in PCI memory space.

0 IO_EN R/W

I/O space control. Bit 0 controls whether or not the PCI1210 can claim cycles in PCI I/O space.

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complete description of the register contents. Table 18. Status Register 15 PAR_ERR R/C Detected parity error. Bit 15 is set when a parity error is detected (either address or data). terminated by a master abort. the PCI1210 asserts PCI_SPEED at a medium speed on nonconfiguration cycle accesses.

8 DATAPAR R/C

0 = The conditions for setting bit 8 have not been met. a. PERR was asserted by any PCI device including the PCI1210. b. The PCI1210 was the bus master during the data parity error. c. The parity error response bit is set in the command.

4 CAPLIST R

implemented in this function. 3–0 RSVD R Reserved. Bits 3–0 return 0s when read.

SCPS032A– APRIL 1998 47POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 revision ID register Bit 7 6 5 4 3 2 1 0 Name Revision ID Type R R R R R R R R Default 0 0 0 0 0 0 0 1 Register: Revision ID Type: Read only Offset: 08h Default: 01h Description: This read-only register indicates the silicon revision of the PCI1210. PCI class code register Bit 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Class code Base class Sub class Programming interface Type R R R R R R R R R R R R R R R R R R R R R R R R Default 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 Register: PCI Class code Type: Read only Offset: 09h Default: 060700h Description: The class code register recognizes the PCI1210 as a bridge device (06h), and CardBus bridge device (07h) with a 00h programming interface. cache line size register Bit 7 6 5 4 3 2 1 0 Name Cache line size Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register: Cache line size Type: Read/write Offset: 0Ch Default: 00h Description: The cache line size register is programmed by host software to indicate the system cache line size.

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Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register: Latency timer Type: Read/write Offset: 0Dh Default: 00h Description: The latency timer register specifies the latency timer for the PCI1210 in units of PCI clock cycles. When the PCI1210 is a PCI bus initiator and asserts FRAME , the latency timer begins counting from zero. If the latency timer expires before the PCI1210 transaction has terminated, the PCI1210 terminates the transaction when its GNT is deasserted. header type register Bit 7 6 5 4 3 2 1 0 Name Header type Type R R R R R R R R Default 0 0 0 0 0 0 1 0 Register: Header type Type: Read only Offset: 0Eh Default: 02h Description: This read-only register returns 02h when read, indicating that the PCI1210 configuration spaces adhere to the CardBus bridge PCI header. The CardBus bridge PCI header ranges from PCI register 0 to 7Fh, leaving 80h–FFh is user-definable extension registers. BIST register Bit 7 6 5 4 3 2 1 0 Name BIST Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Register: BIST Type: Read only Offset: 0Fh Default: 00h Description: Because the PCI1210 does not support a built-in self-test (BIST), this register is read only and returns the value of 00h when read.

SCPS032A– APRIL 1998 49POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CardBus socket registers/ExCA registers base-address register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name CardBus socket/ExCA registers base address Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name CardBus socket/ExCA registers base address Type R/W R/W R/W R/W R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: CardBus socket/ExCA registers base address Type: Read only, read/write Offset: 10h Default: 0000 0000h Description: The CardBus socket registers/ExCA base-address register is programmed with a base address referencing the CardBus socket registers and the memory-mapped ExCA register set. Bits 31–12 are read/write, and allow the base address to be located anywhere in the 32-bit PCI memory address space on a 4K-byte boundary. Bits 11–0 are read only, returning 0s when read. When software writes all 1s to this register, the value readback is FFFF F000h, indicating that at least 4K-bytes of memory address space are required. The CardBus registers start at offset 000h, and the memory-mapped ExCA registers begin at offset 800h. capability pointer register Bit 7 6 5 4 3 2 1 0 Name Capability pointer Type R R R R R R R R Default 1 0 1 0 0 0 0 0 Register: Capability pointer Type: Read only Offset: 14h Default: A0h Description: The capability pointer register provides a pointer into the PCI configuration header where the PCI power management register block resides. PCI header doublewords at A0h and A4h provide the power management (PM) registers. The socket has its own capability pointer register. This register is read only and returns A0h when read.

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very similar to the PCI status register (offset 06h), and status bits are cleared by writing a 1. See Table 19 for the complete description of the register contents. Table 19. Secondary Status Register 15 CBPARITY R/C Detected parity error. Bit 15 is set when a CardBus parity error is detected (either address or data). terminated by a master abort. terminated by a target abort. indicating that the PCI1210 asserts CB_SPEED at a medium speed.

8 CB_DPAR R/C

CardBus data parity error detected. 0 = The conditions for setting bit 8 have not been met. a. CPERR was asserted on the CardBus interface. b. The PCI1210 was the bus master during the data parity error. c. The parity error response bit is set in the bridge control. therefore, bit 5 is hardwired to 0. 4–0 RSVD R Reserved. Bits 4–0 return 0s when read.

SCPS032A– APRIL 1998 51POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI bus number register Bit 7 6 5 4 3 2 1 0 Name PCI bus number Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register: PCI bus number Type: Read/write Offset: 18h Default: 00h Description: This read/write register is programmed by the host system to indicate the bus number of the PCI bus to which the PCI1210 is connected. The PCI1210 uses this register in conjunction with the CardBus bus number and subordinate bus number registers to determine when to forward PCI configuration cycles to its secondary buses. CardBus bus number register Bit 7 6 5 4 3 2 1 0 Name CardBus bus number Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register: CardBus bus number Type: Read/write Offset: 19h Default: 00h Description: This read/write register is programmed by the host system to indicate the bus number of the CardBus bus to which the PCI1210 is connected. The PCI1210 uses this register in conjunction with the PCI bus number and subordinate bus number registers to determine when to forward PCI configuration cycles to its secondary buses. subordinate bus number register Bit 7 6 5 4 3 2 1 0 Name Subordinate bus number Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register: Subordinate bus number Type: Read/write Offset: 1Ah Default: 00h Description: This read/write register is programmed by the host system to indicate the highest-numbered bus below the CardBus bus. The PCI1210 uses this register in conjunction with the PCI bus number and CardBus bus number registers to determine when to forward PCI configuration cycles to its secondary buses.

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CardBus latency timer register Bit 7 6 5 4 3 2 1 0 Name CardBus latency timer Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register: CardBus latency timer Type: Read/write Offset: 1Bh Default: 00h Description: This read/write register is programmed by the host system to specify the latency timer for the PCI1210 CardBus interface in units of CCLK cycles. When the PCI1210 is a CardBus initiator and asserts CFRAME , the CardBus latency timer begins counting. If the latency timer expires before the PCI1210 transaction has terminated, then the PCI1210 terminates the transaction at the end of the next data phase. A recommended minimum value for this register is 20h, which allows most transactions to be completed. memory base registers 0, 1 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Memory base registers 0, 1 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Memory base registers 0, 1 Type R/W R/W R/W R/W R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Memory base registers 0, 1 Type: Read only, read/write Offset: 1Ch, 24h Default: 0000 0000h Description: These registers indicate the lower address of a PCI memory address range and are used by the PCI1210 to determine when to forward a memory transaction to the CardBus bus, and likewise, when to forward a CardBus cycle to PCI. Bits 31–12 of these registers are read/write and allow the memory base to be located anywhere in the 32-bit PCI memory space on 4K-byte boundaries. Bits 11–0 are read only and always return 0s. Writes to these bits have no effect. Bits 8 and 9 of the bridge control register specify whether memory windows 0 and 1 are prefetchable or nonprefetchable. The memory base register or the memory limit register must be nonzero for the PCI1210 to claim any memory transactions through CardBus memory windows (i.e., these windows are not enabled by default to pass the first 4K-bytes of memory to CardBus).

SCPS032A– APRIL 1998 53POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 memory limit registers 0, 1 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Memory limit registers 0, 1 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Memory limit registers 0, 1 Type R/W R/W R/W R/W R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Memory limit registers 0, 1 Type: Read only, read/write Offset: 20h, 28h Default: 0000 0000h Description: These registers indicate the upper address of a PCI memory address range and are used by the PCI1210 to determine when to forward a memory transaction to the CardBus bus, and likewise, when to forward a CardBus cycle to PCI. Bits 31–12 of these registers are read/write and allow the memory base to be located anywhere in the 32-bit PCI memory space on 4K-byte boundaries. Bits 11–0 are read only and always return 0s. Writes to these bits have no effect. Bits 8 and 9 of the bridge control register specify whether memory windows 0 and 1 are prefetchable or nonprefetchable. The memory base register or the memory limit register must be nonzero for the PCI1210 to claim any memory transactions through CardBus memory windows (i.e., these windows are not enabled by default to pass the first 4K-bytes of memory to CardBus). I/O base registers 0, 1 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name I/O base registers 0, 1 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name I/O base registers 0, 1 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: I/O base registers 0, 1 Type: Read only, read/write Offset: 2Ch, 34h Default: 0000 0000h Description: These registers indicate the lower address of a PCI I/O address range and are used by the PCI1210 to determine when to forward an I/O transaction to the CardBus bus, and likewise, when to forward a CardBus cycle to the PCI bus. The lower 16 bits of this register locate the bottom of the I/O window within a 64K byte page, and the upper sixteen bits (31–16) are a page register which locates this 64K byte page in 32-bit PCI I/O address space. Bits 31–2 are read/write. Bits 1–0 are read only and always return 0’s, forcing I/O windows to be aligned on a natural doubleword boundary. NOTE: Either the I/O base or the I/O limit register must be nonzero to enable any I/O transactions.

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I/O limit registers 0, 1 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name I/O limit registers 0, 1 Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name I/O limit registers 0, 1 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: I/O limit registers 0, 1 Type: Read only, read/write Offset: 30h, 38h Default: 0000 0000h Description: These registers indicate the upper address of a PCI I/O address range and are used by the PCI1210 to determine when to forward an I/O transaction to the CardBus bus, and likewise, when to forward a CardBus cycle to PCI. The lower 16 bits of this register locate the top of the I/O window within a 64K-byte page, and the upper 16 bits are a page register that locates this 64K-byte page in 32-bit PCI I/O address space. Bits 15–2 are read/write and allow the I/O limit address to be located anywhere in the 64K-byte page (indicated by bits 31–16 of the appropriate I/O base) on doubleword boundaries. Bits 31–16 are read only and always return 0s when read. The page is set in the I/O base register. Bits 1–0 are read only and always return 0s, forcing I/O windows to be aligned on a natural doubleword boundary. Writes to read-only bits have no effect. The PCI1210 assumes that the lower two bits of the limit address are 1s. NOTE: The I/O base or the I/O limit register must be nonzero to enable an I/O transaction.

SCPS032A– APRIL 1998 55POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 interrupt line register Bit 7 6 5 4 3 2 1 0 Name Interrupt line Type R/W R/W R/W R/W R/W R/W R/W R/W Default 1 1 1 1 1 1 1 1 Register: Interrupt line Type: Read/write Offset: 3Ch Default: FFh Description: The interrupt line register is read/write and is used to communicate interrupt line routing information. interrupt pin register Bit 7 6 5 4 3 2 1 0 Name Interrupt pin Type R R R R R R R R Default 0 0 0 0 0 0 0 1 Register: Interrupt pin Type: Read only Offset: 3Dh Default: 01h Description The value read from the interrupt pin register is function dependent and reflects the interrupt signalling mode selected through the device control register (92h). The PCI1210 defaults to serialized PCI and ISA interrupt mode.

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Table 20 for a complete description of the register contents. Table 20. Bridge Control Register 15–11 RSVD R Reserved. Bits 15–11 return 0s when read.

10 POSTEN R/W

cycles. Note that bursted write data can be posted, but various write transactions may not.

9 PREFETCH1 R/W

0 = Memory window 1 is nonprefetchable. 1 = Memory window 1 is prefetchable (default).

8 PREFETCH0 R/W

0 = Memory window 0 is nonprefetchable. 1 = Memory window 0 is prefetchable (default).

7 INTR R/W

routed to PCI interrupts or the IRQ specified in the ExCA registers.

6 CRST R/W

asserted by passing a RST assertion to CardBus.

5 MABTMODE R/W

an initiator on the CardBus interface. This bit is common between each socket. 4 RSVD R Reserved. Bit 4 returns 0 when read. to VGA addresses are forwarded.

2 ISAEN R/W

of each 1K I/O range to CardBus.

1 CSERREN R/W

bit is common between the two sockets. 0 = CSERR is not forwarded to PCI SERR. 1 = CSERR is forwarded to PCI SERR.

0 CPERREN R

errors. This bit is common between the two sockets. 0 = CardBus parity errors are ignored.

SCPS032A– APRIL 1998 57POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 subsystem vendor ID register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Subsystem vendor ID Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Subsystem vendor ID Type: Read only (read/write when bit 5 in the system control register is 0) Offset: 40h Default: 0000h Description: The subsystem vendor ID register is used for system and option-card identification purposes, and may be required for certain operating systems. This register is read only or read/write, depending on the setting of bit 5 (SUBSYSRW) in the system control register. When bit 5 is 0, this register is read/write; when bit 5 is 1, this register is read only. The default mode is read only. subsystem ID register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Subsystem ID Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Subsystem ID Type: Read only (read/write when bit 5 in the system control register is 0) Offset: 42h Default: 0000h Description: The subsystem ID register is used for system and option-card identification purposes, and may be required for certain operating systems. This register is read only or read/write, depending on the setting of bit 5 (SUBSYSRW) in the system control register. When bit 5 is 0, this register is read/write; when bit 5 is 1, this register is read only. The default mode is read only.

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PC Card 16-bit I/F legacy-mode base address register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name PC Card 16-bit I/F legacy-mode base address Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name PC Card 16-bit I/F legacy-mode base address Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Register: PC Card 16-bit I/F legacy-mode base address Type: Read only, read/write (see individual bit descriptions) Offset: 44h Default: 0000 0001h Description: The PCI1210 supports the index/data scheme of accessing the ExCA registers, which is mapped by this register. An address written to this register is the address for the index register and the address + 1 is the data address. Using this access method, applications requiring index/data ExCA access can be supported. The base address can be mapped anywhere in 32-bit I/O space on a word boundary; hence, bit 0 is read only, returning 1 when read. Refer to ExCA compatibility registers on page 80 for register offsets. system control register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name System control Type R/W R/W R R R R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name System control Type R/W R/W R R R R R R R R/W R/W R/W R/W R R/W R/W Default 1 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 Register: System control Type: Read only, read/write (see individual bit descriptions) Offset: 80h Default: 0044 9060h Description: System-level initializations are performed through programming this doubleword register. See Table 21 for a complete description of the register contents.

Table 21. System Control Register 00 = INTA is signaled in the INTA IRQSER slot. 01 = INTA is signaled in the INTB IRQSER slot. 10 = INTA is signaled in the INTC IRQSER slot. 11 = INTA is signaled in the INTD IRQSER slot. 29–27 RSVD R Reserved. These bits are read only and return 0 when read.

26 SMIROUTE R/W

1 = A CSC interrupt is generated on PC Card power changes.

25 SMISTATUS R/W

the SMIENB bit is set. Writing a 1 to bit 25 clears the status. an interrupt when a write to the socket power control occurs. This bit defaults to 0 (disabled). 23 RSVD R Reserved. This bit is read only and returns 0 when read.

22 CBRSVD R/W

when a CardBus card is inserted. When this bit is low (as default), these signals are 3-stated.

21 VCCPROT R/W

20 REDUCEZV R/W

19 CDREQEN R/W

signaling. DREQ is selected through the socket DMA register 0. 4 = PCI master; not used (default).

15 MRBURSTDN R/W

0 = Downstream memory read burst is disabled. 1 = Downstream memory read burst is enabled (default).

14 MRBURSTUP R/W

0 = Upstream memory read burst is disabled (default). 1 = Upstream memory read burst is enabled.

13 SOCACTIVE R

and is cleared upon read of this status bit. This bit is socket dependent. 12 RSVD R Reserved. Bit 12 is read only and returns 1 when read. This is the power rail bit.

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Table 21. System Control Register (Continued)

11 PWRSTREAM R

10 DELAYUP R

9 DELAYDOWN R

power-down delay has expired.

8 INTERROGATE R

7 RSVD R Reserved. Bit 7 is read only and returns 0 when read. the applicable CB state machine will not be clocked.

5 SUBSYSRW R/W

0 = SSID, SSVID, ExCA ID, and revision register are read/write. 1 = SSID, SSVID, ExCA ID, and revision register are read only (default).

4 CB_DPAR R/W

3 CDMA_EN R/W

2 RSVD R Reserved. Bit 2 is read only and returns 0 when read.

1 KEEPCLK R/W

1 = Does not allow CB clock or PCI clock to be stopped using the CLKRUN protocols.

0 RIMUX R/W

RI_OUT /PME multiplex enable. at the same time, RI_OUT has precedence over PME. 1 = Only PME is routed to the RI_OUT/PME terminal.

for a complete description of the register contents. Table 22. Multifunction Routing Register 31–28 RSVD R Reserved. These bits are read only and return 0 when read.

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Table 22. Multifunction Routing Register (Continued) MFUNC4 terminal provides the SCL signaling.

MFUNC1 terminal provides the SDA signaling.

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Table 23. Retry Status Register

7 PCIRETRY R/W

6 CBRETRY R/W

5–4 RSVD R Reserved. These bits return 0 when read.

3 TEXP_CB R/C

CardBus target retry expired. Write a 1 to clear bit 3. 2 RSVD R Reserved. Bit 2 returns 0 when read.

1 TEXP_PCI R/C

PCI target retry expired. Write a 1 to clear bit 1. 0 RSVD R Reserved. Bit 0 returns 0 when read.

this register. See Table 24 for a complete description of the register contents. Table 24. Card Control Register

7 RIENB R/W

Ring-indicate output enable. 0 = Disables any routing of RI_OUT signal (default). to 0, or for routing to MFUNC2/4. 5 No function R/W These bits are read/write and have no assigned function. 4–3 RSVD R Reserved. Bits 4–3 are read only and default to 0. which can be routed to a multifunction terminal.

1 SPKROUTEN R/W

Speaker out enable. This bit is the enable for routing PC Card SPKR through to the SPKROUT terminal. The SPKROUT terminal drives valid data only when the socket SPKROUTEN bit is set.

0 IFG R/C

a functional interrupt is signaled from a PC Card interface. Write back a 1 to clear this bit. 0 = No PC Card functional interrupt detected (default). 1 = PC Card functional interrupt detected.

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description of the register contents. Table 25. Device Control Register 7 RSVD R Reserved. Bit 7 Returns 0 when read. 5 IO16R2 R/W Diagnostic bit. 4 RSVD R Reserved. Bit 4 returns 0 when read. Writes have no effect. 3 TEST R/W TI test. Only a 0 should be written to bit 3. This bit can be set to shorten the interrogation counter. 0 RSVD R/W Reserved. This read/write bit is reserved for test purposes. Only 0 should be written to this bit.

Table 26. Diagnostic Register

7 TRUE_VAL R/W

When bit 5 is set to a 1, CSC interrupts are routed through the PCI interrupts. When bit 6 is set to a 1, Legacy IRQs are routed through the PCI interrupts. 4 DIAG4 R/W Diagnostic RETRY_DIS. Delayed transaction disable. 3 DIAG3 R/W Diagnostic RETRY_EXT. Extends the latency from 16 to 64. 2 DIAG2 R/W Diagnostic DISCARD_TIM_SEL_CB. Set = 210, reset = 215. 1 DIAG1 R/W Diagnostic DISCARD_TIM_SEL_PCI. Set = 210, reset = 215. See Table 27 for a complete description of the register contents.

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Table 27. Socket DMA Register 0 31–2 RSVD R Reserved. Bits 31–2 are read only and return 0s when read. 00 = Socket not configured for DMA (default). complete description of the register contents. 32-bit transfers are not supported; the maximum transfer possible for 16-bit PC Cards is 16 bits. Table 28. Socket DMA Register 1 31–16 RSVD R Reserved. Bits 31–16 are read only and return 0s when read. decode. Thus, the window is aligned to a natural 16-byte boundary. 3 EXTMODE R Extended addressing. This feature is not supported by the PCI1210 and and always returns a 0. 00 = Transfers are 8 bits (default).

0 DDMAEN R/W

SCPS032A– APRIL 1998 69POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 capability ID register Bit 7 6 5 4 3 2 1 0 Name Capability ID Type R R R R R R R R Default 0 0 0 0 0 0 0 1 Register: Capability ID Type: Read only Offset: A0h Default: 01h Description: The capability ID register identifies the linked list item as the register for PCI power management. The register returns 01h when read, which is the unique ID assigned by the PCI SIG for the PCI location of the capabilities pointer and the value. next-item pointer register Bit 7 6 5 4 3 2 1 0 Name Next-item pointer Type R R R R R R R R Default 0 0 0 0 0 0 0 0 Register: Next-item pointer Type: Read only Offset: A1h Default: 00h Description: The next-item pointer register is used to indicate the next item in the linked list of the PCI power management capabilities. Because the PCI1210 functions include only one capabilities item, this register returns 0s when read.

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Table 29. Power-Management Capabilities Register PME support. This 5-bit field indicates the power states from which the PCI1210 supports asserting PME. Bit 15 contains the value 0, indicating that PME cannot be asserted from D3cold state. Bit 14 contains the value 1, indicating that PME can be asserted from D3hot state. Bit 13 contains the value 1, indicating that PME can be asserted from D2 state. Bit 12 contains the value 1, indicating that PME can be asserted from D1 state. Bit 11 contains the value 1, indicating that PME can be asserted from the D0 state. dynamic power consumption data. 7–6 RSVD R Reserved. These bits are reserved and return 00b when read.

5 DSI R

generic class device driver is able to use it. that the function supplies its own auxiliary power source.

complete description of the register contents. Table 30. Power-Management Control/Status Register

15 PMESTAT R/C

PME signal if PME was asserted by this function. Writing a 0 to this bit has no effect. return any dynamic data as indicated by the DYN_DATA bit. not return any dynamic data as indicated by the DYN_DATA bit. 7–5 RSVD R Reserved. Bits 7–5 are read only and return 0s when read. function does not report dymanic data. 3–2 RSVD R Reserved. Bits 3–2 are read only and return 0s when read.

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specific functionality. See Table 31 for a complete description of the register contents. Table 31. Power-Management Control/Status Register Bridge Support Extensions 7 BPCC_EN R Bus power/clock control. When read, bit 7 returns a 1. 6 B2_B3 R B2/B3 support for D3hot. ThIs bit is read only and returns a 0 when read. 5–0 RSVD R Reserved. These bits are read only and return 0s when read. CardBus functions do not report dynamic data.

enable register. See Table 32 for a complete description of the register contents. Table 32. General-Purpose Event Status Register controller function of the PCI1210. 14–12 RSVD R Reserved. These bits are read only and return zero when read. change in either VCC or VPP for the socket causes this bit to be set. 10–9 RSVD R Reserved. These bits are read only and return zero when read. or from 12 Volts for the PC Card socket. 7–5 RSVD R Reserved. These bits are read only and return zero when read. 4 GP4_STS R/C GPI4 Status. Bit 4 is set on a change in status of the MFUNC5 terminal input level. 3 GP3_STS R/C GPI3 Status. Bit 3 is set on a change in status of the MFUNC4 terminal input level . 2 GP2_STS R/C GPI2 Status. Bit 2 is set on a change in status of the MFUNC2 terminal input level. 1 GP1_STS R/C GPI1 Status. Bit 1 is set on a change in status of the MFUNC1 terminal input level. 0 GP0_STS R/C GPI0 Status. Bit 0 is set on a change in status of the MFUNC0 terminal input level.

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The GPE signal is driven until the corresponding status bit is cleared and the event is serviced. Table 33. General-Purpose Event Enable Register ZVENABLE in the PC Card controller function of the PCI1210. 14–12 RSVD R Reserved. These bits are read only and return zero when read. changed the power state of the socket. 10–9 RSVD R Reserved. These bits are read only and return zero when read. changed the requested VPP level to or from 12 Volts for the card socket. 7–5 RSVD R Reserved. These bits are read only and return zero when read. of the MFUNC5 terminal input level if configured as GPI4. of the MFUNC4 terminal input level if configured as GPI3. of the MFUNC2 terminal input if configured as GPI2. of the MFUNC1 terminal input if configured as GPI1. of the MFUNC0 terminal input if configured as GPI0.

Table 34. General-Purpose Input Register 15–5 RSVD R Reserved. Bits 15–5 are read only and return 0 when read. Writes have no effect. MFUNC5 terminal. Writes have no effect. MFUNC4 terminal. Writes have no effect. MFUNC2 terminal. Writes have no effect. MFUNC1 terminal. Writes have no effect. MFUNC0 terminal. Writes have no effect.

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Table 35 for a complete description of the register contents. Table 35. General-Purpose Output Register 15–5 RSVD R Reserved. Bits 15–5 are read only and return 0 when read. Writes have no effect. MFUNC5 terminal if configured as GPO4. Reads return the last data value written. MFUNC4 terminal if configured as GPO3. Reads return the last data value written. MFUNC2 terminal if configured as GPO2. Reads return the last data value written. MFUNC1 terminal if configured as GPO1. Reads return the last data value written. MFUNC0 terminal if configured as GPO0. Reads return the last data value written.

7-bit slave address and the read/write indicator bit must be reset. bus interface. See Table 36 for a complete description of the register contents. Table 36. Serial Bus Data Register 7–0 SBDATA R/W Serial bus data. This bit field represents the data byte in a read or write transaction on the serial interface. On reads, the REQBUSY bit must be polled to verify that the contents of this register are valid. must be programmed with both the 7-bit slave address and the read/write indicator. from the serial bus interface. See Table 37 for a complete description of the register contents.

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Table 37. Serial Bus Index Register must be programmed with both the 7-bit slave address and the read/write indicator bit. and the REQBUSY bit in the serial bus control and status register must be polled until clear. interface. See Table 38 for a complete description of the register contents. Table 38. Serial Bus Slave Address Register

0 RWCMD R/W

Table 39 for a complete description of the register contents. Table 39. Serial Bus Control and Status Register

7 PROT_SEL R/W

by the PCI1210 when bit 7 is set. 6 RSVD R Reserved. Bit 6 is read only and returns zero when read.

5 REQBUSY R

read data is valid in the serial bus data register.

4 ROMBUSY R

set during the loading of the subsystem ID and other default values from the serial bus EEPROM.

3 SBDETECT R/C

general-purpose inputs and outputs.

2 SBTEST R/W

Serial bus test. When bit 2 is set, the serial bus clock frequency is increased for test purposes.

1 REQ_ERR R/C

a requested cycle, and may be set due to a missing acknowledge. Bit 1 is cleared by a write back of 1.

0 ROM_ERR R/C

format. Bit 0 is cleared by a write back of 1.

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to 3Fh for the socket. Refer to Figure 20 for an ExCA I/O mapping illustration. Figure 20. ExCA Register Access Through I/O

Figure 21. ExCA Register Access Through Memory are critical to the interrupt signaling are at memory address ExCA offset 803h and 805h. Access to memory mapped 16-bit PC Cards is available to the host system via five ExCA memory windows. defined by start, end, and offset addresses programmed in the ExCA registers described in this section.

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Table 40. ExCA Registers and Offsets

Table 40. ExCA Registers and Offsets (Continued)

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82365SL-DF compatibility. See Table 41 for a complete description of the register contents. Table 41. ExCA Identification and Revision Register (Index 00h) provided by the PCI1210. The PCI1210 supports both I/O and memory 16-bit PC cards. 5–4 RSVD R/W Reserved. Bits 5–4 can be used for Intel 82365SL-DF emulation. PCI1210. Host software can read this field to determine compatibility to the Intel 82365SL-DF register set. This field defaults to 0100b upon PCI1210 reset.

PC Card interface. See Table 42 for a complete description of the register contents. Table 42. ExCA Interface Status Register (Index 01h) 7 RSVD R Reserved. Bit 7 is read only and returns 0 when read. Writes have no effect.

6 CARDPWR R

5 READY R

Ready. Bit 5 indicates the current status of the READY signal at the PC Card interface.

4 CARDWP R

0 = WP is 0. PC Card is R/W. 1 = WP is 1. PC Card is read only.

3 CDETECT2 R

CDETECT1 to determine if a PC Card is fully seated in the socket. 0 = CD2 is 1. No PC Card is inserted. 1 = CD2 is 0. PC Card is at least partially inserted.

2 CDETECT1 R

CDETECT2 to determine if a PC Card is fully seated in the socket. 0 = CD1 is 1. No PC Card is inserted. 1 = CD1 is 0. PC Card is at least partially inserted.

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applications. See Table 43 for a complete description of the register contents. Table 43. ExCA Power-Control Register (Index 02h)

7 COE R/W

6–5 RSVD R Reserved. Bits 6–5 are read only and return 0s when read. Writes have no effect. 2 RSVD R Reserved. Bit 2 is read only and returns 0 when read. Writes have no effect.

PC Card functions. See Table 44 for a complete description of the register contents. Table 44. ExCA Interrupt and General-Control Register (Index 03h)

7 RINGEN R/W

6 RESET R/W

5 CARDTYPE R/W

4 CSCROUTE R/W

0 = CSC interrupts are routed by ExCA registers (default). 1 = CSC interrupts are routed to PCI interrupts. 0000 = No interrupt routing (default).

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occurs, the corresponding bit in this register is set to indicate that the interrupt source is active. for a complete description of the register contents. Table 45. ExCA Card Status-Change Register (Index 04h) 7–4 RSVD R Reserved. Bits 7–4 are read only and return 0s when read. Writes have no effect.

3 CDCHANGE R

2 READYCHANGE R

When a 16-bit I/O card is installed, bit 2 is always 0.

1 BATWARN R

When a 16-bit I/O card is installed, bit 1 is always 0.

0 BATDEAD R

CSC interrupt sources. See Table 46 for a complete description of the register contents. Table 46. ExCA Card Status-Change-Interrupt Configuration Register (Index 05h)

3 CDEN R/W

2 READYEN R/W

1 BATWARNEN R/W

Battery Warning Enable. Bit 1 enables/disables a battery warning condition to generate a CSC interrupt.

0 BATDEADEN R/W

of the STSCHG I/O PC Card signal to generate a CSC interrupt.

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for a complete description of the register contents. Table 47. ExCA Address Window Enable Register (Index 06h)

7 IOWIN1EN R/W

6 IOWIN0EN R/W

5 RSVD R Reserved. Bit 5 is read only and returns 0 when read. Writes have no effect.

4 MEMWIN4EN R/W

3 MEMWIN3EN R/W

2 MEMWIN2EN R/W

1 MEMWIN1EN R/W

0 MEMWIN0EN R/W

for a complete description of the register contents. Table 48. ExCA

7 WAITSTATE1 R/W

effect on 8-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF . 0 = 16-bit cycles have standard length (default). 1 = 16-bit cycles are extended by one equivalent ISA wait state.

6 ZEROWS1 R/W

0 = 8-bit cycles have standard length (default). 1 = 8-bit cycles are reduced to equivalent of three ISA cycles.

5 IOSIS16W1 R/W

0 = Window data width determined by DATASIZE1, bit 4 (default). 1 = Window data width determined by IOIS16.

4 DATASIZE1 R/W

0 = Window data width is 8 bits (default). 1 = Window data width is 16 bits.

3 WAITSTATE0 R/W

0 = 16-bit cycles have standard length (default). 1 = 16-bit cycles are extended by one equivalent ISA wait state.

2 ZEROWS0 R/W

0 = 8-bit cycles have standard length (default). 1 = 8-bit cycles are reduced to equivalent of three ISA cycles.

1 IOSIS16W0 R/W

0 = Window data width is determined by DATASIZE0, bit 0 (default). 1 = Window data width is determined by IOIS16.

0 DATASIZE0 R/W

0 = Window data width is 8 bits (default). 1 = Window data width is 16 bits.

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ExCA I/O window 0 and 1 start-address low-byte register (index 08h, 0Ch) Bit 7 6 5 4 3 2 1 0 Name ExCA I/O window 0 and 1 start-address low byte Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register: ExCA I/O window 0 start-address low byte Offset: CardBus socket address + 808h; ExCA offset 08h Register: ExCA I/O window 1 start-address low byte Offset: CardBus socket address + 80Ch; ExCA offset 0Ch Type: Read/write Default: 00h Size: One byte Description: These registers contain the low byte of the 16-bit I/O window start address for I/O windows 0 and 1. The eight bits of these registers correspond to the lower eight bits of the start address. ExCA I/O window 0 and 1 start-address high-byte register (index 09h, 0Dh) Bit 7 6 5 4 3 2 1 0 Name ExCA I/O window 0 and 1 start-address high byte Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register: ExCA I/O window 0 start-address high byte Offset: CardBus socket address + 809h; ExCA offset 09h Register: ExCA I/O window 1 start-address high byte Offset: CardBus socket address + 80Dh; ExCA offset 0Dh Type: Read/write Default: 00h Size: One byte Description: These registers contain the high byte of the 16-bit I/O window start address for I/O windows 0 and 1. The eight bits of these registers correspond to the upper eight bits of the end address.

SCPS032A– APRIL 1998 93POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ExCA I/O window 0 and 1 end-address low-byte register (index 0Ah, 0Eh) Bit 7 6 5 4 3 2 1 0 Name ExCA I/O window 0 and 1 end-address low byte Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register: ExCA I/O window 0 end-address low byte Offset: CardBus socket address + 80Ah; ExCA offset 0Ah Register: ExCA I/O window 1 end-address low byte Offset: CardBus socket address + 80Eh; ExCA offset 0Eh Type: Read/write Default: 00h Size: One byte Description: These registers contain the low byte of the 16-bit I/O window end address for I/O windows 0 and 1. The eight bits of these registers correspond to the lower eight bits of the end address. ExCA I/O window 0 and 1 end-address high-byte register (index 0Bh, 0Fh) Bit 7 6 5 4 3 2 1 0 Name ExCA I/O window 0 and 1 end-address high byte Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register: ExCA I/O window 0 end-address high byte Offset: CardBus socket address + 80Bh; ExCA offset 0Bh Register: ExCA I/O window 1 end-address high byte Offset: CardBus socket address + 80Fh; ExCA offset 0Fh Type: Read/write Default: 00h Size: One byte Description: These registers contain the high byte of the 16-bit I/O window end address for I/O windows 0 and 1. The eight bits of these registers correspond to the upper eight bits of the end address.

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ExCA memory window 0–4 start-address low-byte register (index 10h, 18h, 20h, 28h, 30h) Bit 7 6 5 4 3 2 1 0 Name ExCA memory window 0–4 start-address low byte Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register: ExCA memory window 0 start-address low byte Offset: CardBus socket address + 810h; ExCA offset 10h Register: ExCA memory window 1 start-address low byte Offset: CardBus socket address + 818h; ExCA offset 18h Register: ExCA memory window 2 start-address low byte Offset: CardBus socket address + 820h; ExCA offset 20h Register: ExCA memory window 3 start-address low byte Offset: CardBus socket address + 828h; ExCA offset 28h Register: ExCA memory window 4 start-address low byte Offset: CardBus socket address + 830h; ExCA offset 30h Type: Read/write Default: 00h Size: One byte Description: These registers contain the low byte of the 16-bit memory window start address for memory windows 0, 1, 2, 3, and 4. The eight bits of these registers correspond to bits A19–A12 of the start address.

this register. See Table 49 for a complete description of the register contents. Table 49. ExCA Memory Window 0–4 Start-Address High-Byte Register (Index 11h, 19h, 21h, 29h, 31h)

7 DATASIZE R/W

0 = Window data width is 8 bits (default). 1 = Window data width is 16 bits.

6 ZEROWAIT R/W

0 = 8- and 16-bit cycles have standard length (default). 1 = 8-bit cycles are reduced to equivalent of three ISA cycles. 16-bit cycles are reduced to equivalent of two ISA cycles. 5–4 SCRATCH R/W Scratch pad bits. Bits 5–4 are read/write and have no effect on memory window operation.

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ExCA memory window 0–4 end-address low-byte register (index 12h, 1Ah, 22h, 2Ah, 32h) Bit 7 6 5 4 3 2 1 0 Name ExCA memory window 0–4 end-address low byte Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register: ExCA memory window 0 end-address low byte Offset: CardBus socket address + 812h; ExCA offset 12h Register: ExCA memory window 1 end-address low byte Offset: CardBus socket address + 81Ah; ExCA offset 1Ah Register: ExCA memory window 2 end-address low byte Offset: CardBus socket address + 822h; ExCA offset 22h Register: ExCA memory window 3 end-address low byte Offset: CardBus socket address + 82Ah; ExCA offset 2Ah Register: ExCA memory window 4 end-address low byte Offset: CardBus socket address + 832h; ExCA offset 32h Type: Read/write Default: 00h Size: One byte Description: These registers contain the low byte of the 16-bit memory window end address for memory windows 0, 1, 2, 3, and 4. The eight bits of these registers correspond to bits A19–A12 of the end address.

Table 50 for a complete description of the register contents. Table 50. ExCA Memory Window 0–4 End-Address High-Byte Register (Index 13h, 1Bh, 23h, 2Bh, 33h) 7–6 MEMWS R/W Wait state. Bits 7–6 specify the number of equivalent ISA wait states to be added to 16-bit memory accesses. The number of wait states added is equal to the binary value of these two bits. 5–4 RSVD R Reserved. Bits 5–4 are read only and return 0s when read. Writes have no effect.

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ExCA memory window 0–4 offset-address low-byte register (index 14h, 1Ch, 24h, 2Ch, 34h) Bit 7 6 5 4 3 2 1 0 Name ExCA memory window 0–4 offset-address low byte Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register: ExCA memory window 0 offset-address low byte Offset: CardBus socket address + 814h; ExCA offset 14h Register: ExCA memory window 1 offset-address low byte Offset: CardBus socket address + 81Ch; ExCA offset 1Ch Register: ExCA memory window 2 offset-address low byte Offset: CardBus socket address + 824h; ExCA offset 24h Register: ExCA memory window 3 offset-address low byte Offset: CardBus socket address + 82Ch; ExCA offset 2Ch Register: ExCA memory window 4 offset-address low byte Offset: CardBus socket address + 834h; ExCA offset 34h Type: Read/write Default: 00h Size: One byte Description: These registers contain the low byte of the 16-bit memory window offset address for memory windows 0, 1, 2, 3 and 4. The eight bits of these registers correspond to bits A19–A12 of the offset address.

Table 51. ExCA Memory Window 0–4 Offset-Address High-Byte Register (Index 15h, 1Dh, 25h, 2Dh, 35h)

7 WINWP R/W

0 = Write operations are allowed (default). 1 = Write operations are not allowed.

6 REG R/W

0 = Memory window is mapped to common memory (default). 1 = Memory window is mapped to attribute memory.

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ExCA I/O window 0 and 1 offset-address low-byte register (index 36h, 38h) Bit 7 6 5 4 3 2 1 0 Name ExCA I/O window 0 and 1 offset-address low byte Type R/W R/W R/W R/W R/W R/W R/W R Default 0 0 0 0 0 0 0 0 Register: ExCA I/O window 0 offset-address low byte Offset: CardBus socket address + 836h; ExCA offset 36h Register: ExCA I/O window 1 offset-address low byte Offset: CardBus socket address + 838h; ExCA offset 38h Type: Read only, read/write (see description) Default: 00h Size: One byte Description: These registers contain the low byte of the 16-bit I/O window offset address for I/O windows 0 and 1. The eight bits of these registers correspond to the lower eight bits of the offset address, and bit 0 is always 0. ExCA I/O window 0 and 1 offset-address high-byte register (index 37h, 39h) Bit 7 6 5 4 3 2 1 0 Name ExCA I/O window 0 and 1 offset-address high byte Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register: ExCA I/O window 0 offset-address high byte Offset: CardBus socket address + 837h; ExCA offset 37h Register: ExCA I/O window 1 offset-address high byte Offset: CardBus socket address + 839h; ExCA offset 39h Type: Read/write Default: 00h Size: One byte Description: These registers contain the high byte of the 16-bit I/O window offset address for I/O windows 0 and 1. The eight bits of these registers correspond to the upper eight bits of the offset address.

description of the register contents. Table 52. ExCA Card Detect and General-Control Register (Index 16h)

7 VS2STAT R

6 VS1STAT R

5 SWCSC W

configuration register, writing a 1 to the software card detect interrupt bit has no effect. Bit 5 is write only.

4 CDRESUME R/W

3–2 RSVD R Reserved. Bits 3–2 are read only and return 0s when read. Writes have no effect.

1 REGCONFIG R/W

0 RSVD R Reserved. Bit 0 is read only and returns 0 when read. Writes have no effect.

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Table 53. ExCA Global-Control Register (Index 1Eh) 7–5 RSVD R Reserved. Bits 7–5 are is read only and returns 0s when read. Writes have no effect. 4 No function R/W This read/write bit has no assigned function.

3 INTMODE R/W

0 = Host interrupt is edge mode (default). 1 = Host interrupt is level mode.

2 IFCMODE R/W

0 = Interrupt flags are cleared by read of CSC register (default). 1 = Interrupt flags are cleared by explicit write back of 1.

1 CSCMODE R/W

0 = Host interrupt is edge mode (default). 1 = Host interrupt is level mode.

0 PWRDWN R/W

mode, the PCI1210 card outputs are 3-stated until an active cycle is executed on the card interface. 0 = Power-down mode is disabled (default). 1 = Power-down mode is enabled.

memory mapped, i.e., these registers can not be accessed using the index/data I/O scheme. gives the location of the socket registers in relation to the CardBus socket/ExCA base address. Figure 22. Accessing CardBus Socket Registers Through PCI Memory

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Table 54. CardBus Socket Registers Table 55. Socket Event Register 31–4 RSVD R Reserved. Bits 31–4 are read only and return 0s when read. register has changed. This bit is cleared by writing a 1. register has changed. This bit is cleared by writing a 1. register has changed. This bit is cleared by writing a 1.

0 CSTSEVENT R/C

CSTSCHG. Bit 0 is set when the CARDSTS field in the socket present-state register has changed state. transitions of CSTSCHG. This bit is reset by writing a 1.

Table 56. Socket Mask Register 31–4 RSVD R Reserved. Bits 31–4 are read only and return 0s when read.

3 PWRMASK R/W

0 = PWRCYCLE event does not cause CSC interrupt (default). 1 = PWRCYCLE event causes CSC interrupt. from causing a CSC interrupt. 00 = Insertion/removal does not cause CSC interrupt (default). 11 = Insertion/removal causes CSC interrupt.

0 CSTSMASK R/W

0 = CARDSTS event does not cause CSC interrupt (default). 1 = CARDSTS event causes CSC interrupt.

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socket present-state register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Socket present state Type R R R R R R R R R R R R R R R R Default 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Socket present state Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 X 0 0 0 X X X Register: Socket present state Type: Read only Offset: CardBus socket address + 08h Default: 3000 00XXh Description: The socket present-state register reports information about the socket interface. Writes to the socket force event register are reflected here, as well as general socket interface status. Information about PC Card V CC support and card type is updated only at each insertion. Also note that the PCI1210 uses CCD1 and CCD2 during card identification, and changes on these signals during this operation are not reflected in this register. See Table 57 for a complete description of the register contents.

Table 57. Socket Present-State Register

31 YVSOCKET R

30 XVSOCKET R

27–14 RSVD R Reserved. Bits 27–14 are read only and return 0s when read. 13 YVCARD R YV card. Bit 13 indicates whether or not the PC Card inserted in the socket supports VCC = Y.Y V. 12 XVCARD R XV card. Bit 12 indicates whether or not the PC Card inserted in the socket supports VCC = X.X V. 11 3VCARD R 3-V card. Bit 11 indicates whether or not the PC Card inserted in the socket supports VCC = 3.3 V. 10 5 VCARD R 5-V card. Bit 10 indicates whether or not the PC Card inserted in the socket supports VCC = 5 V.

9 BADVCCREQ R

8 DATALOST R

did not terminate properly or because write data still resides in the PCI1210.

7 NOTACARD R

not updated until a valid PC Card is inserted into the socket.

6 IREQCINT R

updated until another card interrogation sequence occurs (card insertion). until another card interrogation sequence occurs (card insertion).

3 PWRCYCLE R

2 CDETECT2 R

card interrogation are not reflected here.

1 CDETECT1 R

card interrogation are not reflected here.

0 CARDSTS R

CSTSCHG. Bit 0 reflects the current status of CSTSCHG at the PC Card interface.

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Table 58. Socket Force Event Register 31–15 RSVD R Reserved. Bits 31–15 are read only and return 0s when read. state register, and reenables the socket power control. 13 FYVCARD W Force YV card. Writes to bit 13 cause the YVCARD bit in the socket present state register to be written. When set, this bit disables the socket power control. 12 FXVCARD W Force XV card. Writes to bit 12 cause the XVCARD bit in the socket present state register to be written. When set, this bit disables the socket power control. 11 F3VCARD W Force 3-V card. Writes to bit 11 cause the 3VCARD bit in the socket present state register to be written. When set, this bit disables the socket power control. 10 F5 VCARD W Force 5-V card. Writes to bit 10 cause the 5 VCARD bit in the socket present state register to be written. When set, this bit disables the socket power control. 6 RSVD R Reserved. Bit 6 is read only and returns 0 when read. and the PWRCYCLE bit in the socket present state register is unaffected. the CDETECT2 bit in the socket present state register is unaffected. the CDETECT1 bit in the socket present state register is unaffected. and the CARDSTS bit in the socket present state register is unaffected.

description of the register contents. Table 59. Socket Control Register 31–8 RSVD R Reserved. Bits 31–8 are read only and return 0s when read.

7 STOPCLK R/W

CB CLKRUN protocol instructions. 1 = CB CLKRUN protocol can attempt to stop/slow the CB clock if the socket is idle. VCC control. Bits 6–4 are used to request card VCC changes. 3 RSVD R Reserved. Bit 3 is read only and returns 0 when read. VPP control. Bits 2–0 are used to request card VPP changes.

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complete description of the register contents. Table 60. Socket Power Management Register 31–26 RSVD R Reserved. Bits 31–26 are read only and return 0s when read.

25 SKTACCES R

0 = A PC card access has not occurred (default). 1 = A PC card access has occurred.

24 SKTMODE R

Socket mode status. This bit provides clock mode information. 0 = Clock is operating normally. 1 = Clock frequency has changed. 23–17 RSVD R Reserved. Bits 23–17 are read only and return 0s when read.

16 CLKCTRLEN R/W

CardBus clock control enable. When bit 16 is set, clock control (CLKCTRL bit 0) is enabled. 0 = Clock control is disabled (default). 1 = Clock control is enabled. 15–1 RSVD R Reserved. Bits 15–1 are read only and return 0s when read.

0 CLKCTRL R/W

the CB clock during idle states. Bit 16 enables this bit. 0 = Allows CB CLKRUN protocol to stop the CB clock (default). 1 = Allows CB CLKRUN protocol to slow the CB clock by a factor of 16.

implemented as read only and return 0s when read. Writes to reserved registers have no effect. Table 61. Distributed DMA Registers Description: This read/write register is used to set the starting (base) memory address of a DDMA transfer. Reads from this register indicate the current memory address of a direct memory transfer. on AD23–AD16 of the PCI bus during the address phase.

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DDMA current address/base address register (continued) For the 16-bit DDMA transfer mode, the current address register contents are presented on AD16–AD1 of the PCI bus during the address phase, and AD0 is driven to logic 0. Bits 7–1 of the page register are presented on AD23–AD17 of the PCI bus during the address phase, and bit 0 is ignored. DDMA page register Bit 7 6 5 4 3 2 1 0 Name DDMA page Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register: DDMA page Type: Read/write Offset: DDMA base address + 02h Default: 00h Size: One byte Description: This read/write register is used to set the upper byte of the address of a DDMA transfer. Details of the address represented by this register are explained in DDMA current address/base address register. DDMA current count/base count register Bit 15 14 13 12 11 10 9 8 Name DDMA current count/base count Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Name DMA current count/base count Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register: DDMA current count/base count Type: Read/write Offset: DDMA base address + 04h Default: 0000h Size: Two bytes Description: This read/write register is used to set the total transfer count, in bytes, of a direct memory transfer. Reads to this register indicate the current count of a direct memory transfer. In the 8-bit transfer mode, the count is decremented by 1 after each transfer. Likewise, the count is decremented by 2 in the 16-bit transfer mode.

complete description of the register contents. Table 62. DDMA Command Register 7–3 RSVD R Reserved. Bits 7–3 are read only and return 0s when read.

2 DMAEN R/W

defaults to the enabled state. 1–0 RSVD R Reserved. Bits 1–0 are read only and return 0s when read. Table 63 for a complete description of the register contents. Table 63. DDMA Status Register bit in the multichannel mask register has no effect on these bits. Channel terminal count. The 8327 uses bits 3–0 to indicate the TC status of each of its four DMA channels. when the TC is reached by the DMA channel. These bits are reset when read or the DMA channel is reset.

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register enables software requests, and this register is to be used in block mode only. description of the register contents. Table 64. DDMA Mode Register Mode select. The PCI1210 uses bits 7–6 to determine the transfer mode.

5 INCDEC R/W

0 = Addresses increment (default).

4 AUTOINIT R/W

1–0 RSVD R Reserved. Bits 1–0 are read only and return 0s when read.

Description: This write-only register is used to reset the DMA controller and resets all DDMA registers. Table 65 for a complete description of the register contents. Table 65. DDMA Multichannel/Mask Register 7–1 RSVD R Reserved. Bits 7–1 are read only and returns 0s when read.

0 MASKBIT R

requests from the card. When cleared (or when reset), incoming DREQ assertions are serviced normally.

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absolute maximum ratings over operating temperature ranges (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Applies for external input and bidirectional buffers. VI > VCC does not apply to fail-safe terminals. PCI terminals are measured with respect to VCCP instead of VCC . PC Card terminals are measured with respect to VCCCB . Miscellaneous signals are measured with respect to VCCI. The limit specified applies for a dc condition. 2. Applies for external output and bidirectional buffers. VO > VCC does not apply to fail-safe terminals. PCI terminals are measured with respect to VCCP instead of VCC . PC Card terminals are measured with respect to VCCCB . Miscellaneous signals are measured with respect to VCCI. The limit specified applies for a dc condition.

SCPS032A– APRIL 1998 117POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 recommended operating conditions (see Note 3) OPERATION MIN NOM MAX UNIT VCC Supply voltage (core) Commercial 3.3 V 3 3.3 3.6 V VCCP PCI I/O clamping rail voltage Commercial 3.3 V 3 3.3 3.6 VVCCP PCI I/O clamp ing rail voltage Commercial 5 V 4.75 5 5.25 V VCCCB PC Card I/O clamping rail voltage Commercial 3.3 V 3 3.3 3.6 VVCCCB PC C ard I/O clamp ing rail voltage Commercial 5 V 4.75 5 5.25 V VCCI Miscellaneous I/O clamping rail voltageCommercial 3.3 V 3 3.3 3.6 VVCCI Miscellaneous I/O clamp ing rail voltage Commercial 5 V 4.75 5 5.25 V PCI 3.3 V 0.5 VCCP VCCP PCI

5 V 2 VCCP

VVIH† High-level input voltage PC Card 3.3 V 0.475 VCCCB VCCCB VIH gp g 5 V 2.4 VCCCB MISC ‡ 2 VCCI Fail safe§ 2 VCC PCI 3.3 V 0 0.3 VCCP PCI 5 V 0 0.8 VVIL† Low-level input voltage PC Card 3.3 V 0 0.325 VCCCB VIL pg 5 V 0 0.8 MISC ‡ 0 0.8 Fail safe§ 0 0.8 V Il PCI 0 VCCP VVI Input voltage PC Card 0 VCCCB VVI Input voltage MISC ‡ 0 VCCI V Fail safe§ 0 VCC V ¶ Ol PCI 0 VCCP VVO ¶ Output voltage PC Card 0 VCCCB VVO ¶ Output voltage MISC ‡ 0 VCCI V Fail safe§ 0 VCC Ii i i ( d ) PCI and PC Card 1 4 tt Input transition time (tr and tf) Miscellaneous, and fail safe 0 6 ns TA Operating ambient temperature range 0 25 70 °C TJ# Virtual junction temperature 0 25 115 °C † Applies to external inputs and bidirectional buffers without hysteresis ‡ Miscellaneous pins are 70, 62, 59, 60, 61, 64, 65, 67, 68, and 69 for the PGE packaged device and L11, M9, L8, K8, N9, K9, N10, L10, N11, and M11 for the GGU packaged device (SUSPEND, SPKROUT, RI_OUT, multifunction terminals (MFUNC0–6), and power switch control pins). § Fail-safe pins are 75, 117, 131, and 137 for the PGE packaged device and L12, D9, C6, and A4 for the GGU packaged device (card detect and voltage sense pins). ¶ Applies to external output buffers # These junction temperatures reflect simulation conditions. The customer is responsible for verifying junction temperature. NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.

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electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER PINS OPERATION TEST CONDITIONS MIN MAX UNIT V PCI 3.3 V IOH = –0.5 mA 0.9 VCC VV PCI 5 V IOH = –2 mA 2.4 VVOH High-level output voltage (see Note 4) PC Card 3.3 V IOH = –0.15 mA 0.9 VCC V PC C ard 5 V IOH = –0.15 mA 2.4 MISC IOH = –4 mA VCC –0.6 V PCI 3.3 V IOL = 1.5 mA 0.1 VCC VV PCI 5 V IOL = 6 mA 0.55 VVOL Low-level output voltage PC Card 3.3 V IOL = 0.7 mA 0.1 VCC VVOL Low-level output voltage PC C ard 5 V IOL = 0.7 mA 0.55 V MISC IOL = 4 mA 0.5 SERR IOL = 12 mA 0.5 IOZL 3-state output, high-impedance stateOutput pins

3.6 V VI = VCC –1

µAIOZL 3 state output, high impedance state output current (see Note 4) O utput pins

5.25 V VI = VCC –1

µA IOZH 3-state output, high-impedance stateOutput pins

3.6 V VI = VCC † 10

µAIOZH 3 state output, high impedance state output current O utput pins

5.25 V VI = VCC † 25

µA IIL Low level input current (see Note 5) Input pins VI = GND –1 µAIIL Low-level input current (see Note 5) I/O pins VI = GND –10 µA I Input pins

3.6 V VI = VCC ‡ 10

5.25 V VI = VCC ‡ 20

AIIH High-level input current I/O pins

3.6 V VI = VCC ‡ 10 µA

5.25 V VI = VCC ‡ 25

Fail-safe pins 3.6 V VI = VCC 10 † For PCI pins, VI = VCCP . For PC Card pins, VI = VCCCB . For miscellaneous pins, VI = VCCI‡ For I/O pins, input leakage (IIL and IIH) includes IOZ leakage of the disabled output. NOTES: 4. V OH and IOL are not tested on SERR(35, M1) and RI_OUT(59, L8) because they are open drain outputs. 5. IIL is not tested on VCCD0 (73, N13) and VCCD1(74, M13) because they are pulled down with an internal resistor.

SCPS032A– APRIL 1998 119POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI clock/reset timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Figure 24 and Figure 25) PARAMETER ALTERNATE SYMBOL TEST CONDITIONS MIN MAX UNIT tc Cycle time, PCLK tcyc 30 ns twH Pulse duration, PCLK high thigh 11 ns twL Pulse duration, PCLK low tlow 11 ns Δv/Δt Slew rate, PCLK tr, tf 1 4 V/ns tw Pulse duration, RSTIN trst 1 ms tsu Setup time, PCLK active at end of RSTIN trst-clk 100 /C0109s PCI timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Note 6 and Figures 19 and 22) PARAMETER ALTERNATE SYMBOL TEST CONDITIONS MIN MAX UNIT tpd Propagation delay time, PCLK-to-shared signal valid delay time tval C L = 50 pF See Note 7 nstpd Propagation delay time, See Note 7 PCLK-to-shared signal invalid delay time tinv C L = 50 pF, See N ote 7 ns ten Enable time, high impedance-to-active delay time from PCLK ton 2 ns tdis Disable time, active-to-high impedance delay time from PCLK toff 28 ns tsu Setup time before PCLK valid tsu 7 ns th Hold time after PCLK high th 0 ns NOTES: 6. This data sheet uses the following conventions to describe time ( t ) intervals. The format is tA, where subscript A indicates the type of dynamic parameter being represented. One of the following is used: tpd = propagation delay time, td = delay time, tsu = setup time, and th = hold time. 7. PCI shared signals are AD31–0, C/BE3–0, FRAME , TRDY, IRDY, STOP, IDSEL, DEVSEL, and PAR.

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following characteristics: PRR = 1 MHz, ZO = 50 Ω , tr = 6 ns. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. For tPLZ and tPHZ , VOL and VOH are measured values. Figure 23. Load Circuit and Voltage Waveforms

2 V MIN Peak-to-Peak

Figure 24. PCLK Timing Waveform Figure 25. RSTIN Timing Waveforms Figure 26. Shared Signals Timing Waveforms

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the Intel 82365SL-DF values. This ensures compatibility with existing software and maximizes throughput. cycles and nanoseconds for I/O and memory cycles. Table 66. PC Card Address Setup Time, t Table 67. PC Card Command Active Cycle Time, tc(A), 8-Bit PCI Cycles

01 X 23/690

11 X 23/690

Table 68. PC Card Command Active Cycle Time, tc(A), 16-Bit PCI Cycles

01 X 13/390

11 X 23/630

Table 69. PC Card Address Hold Time, th(A), 8-Bit and 16-Bit PCI Cycles observed if programmed for zero wait state, 16-bit cycles) with a 33-MHz PCI clock.

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Figure 27. PC Card Memory Cycle

SCPS032A– APRIL 1998

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PGE (S-PQFP-G144) PLASTIC QUAD FLATPACK 4040147/C 11/96 0,27 0,17 0,13 NOM 0,25 0,75 0,45 0,05 MIN Seating Plane Gage Plane 108 109 144 SQ SQ22,20 21,80 19,80 17,50 TYP 20,20 1,35 1,45 1,60 MAX M0,08 0°–7° 0,08 0,50 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026

SCPS032A– APRIL 1998 127POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA GGU (S-PBGA-N144) PLASTIC BALL GRID ARRAY 4073221/B 11/97 9,60 TYP 12 1310 118967 N M K L J H 42 3 F E C B D A G Seating Plane SQ12,10 11,90 0,95 0,35 0,450,45 0,55 0,85 0,08 0,12 1,40 MAX 0,80 0,10M0,08 0,80 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Micro Star BGA configuration Micro Star is a trademark of Texas Instruments Incorporated.

SCPS032A– APRIL 1998

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