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PCI11414C

Microchip Technology

PCIe Switch with Integrated USB 3.2 Gen 2 Host Controller 11-11-25

Manufacturer: Microchip Technology

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Features

Integrated PCI switching fabric - 512 byte maximum payload size
Integrated PCIe physical interfaces - 4-lane (4x 8 GT/s) upstream port - Allowing single, dual, or four lane links - 1-lane (1x 8 GT/s) downstream port
Integrated USB 3.2 Gen 2 (10 Gbps) physical interfaces
Integrated xHCI USB 3.2 Gen 2 (10 Gbps) USB host controller - 2x 10 Gbps Gen 2 PHY - 4x USB HS/FS/LS PHY - Multiple config. options for Type-C® or Type-A
2.5 Gbps Ethernet MAC - IEEE 802.3 compliant - RMII support for 10/100 Mbps - RGMII support for 10/100/1000 Mbps - SGMII support for 1 Gbps - SGMII+ support for 2.5 Gbps - Jumbo frame support
Precision Time Protocol - IEEE Std 1588™-2008 E2E and P2P one and two step support - IEEE Std 1588-2008 Programmable Time Compare output (e.g., 1PPS) *USB Type-C® and USB-C® are trademarks of USB Implementers Forum.
Two external power supplies: +3.3V and +1.1V
Comprehensive power management features - PCIe 3.1 LPSS (Low Power Sub States): L2 (with aux. power supply) LPSS L1.1 (snooze), L1.2 (off)
Power and I/O - Integrated power-on reset circuit with configurable under/over-voltage protection - Latch-up performance exceeds 150 mA per EIA/JESD78, Class II - JEDEC Class 2 ESD performance
UARTs - RS232/RS422/RS485 - Auto-direction control - Standard and advanced speed support - Basic or comprehensive signal support
Additional features - Multifunction GPIOs - Programmable pin multiplexer - Ability to use low-cost 25 MHz crystal or clock for reduced BOM - PCIe Precision Time Measurement (PTM) - Support for Common Reference Clock and Separate Reference Clocks (SRNS and SRIS) - SPI peripheral interface - SMBus target interface - SMBus controller interface - JTAG TAP - PVT sensor
Packaging - Pb-free RoHS compliant 164-pin DQFN package
Environmental - Available in commercial, industrial, and AEC-Q100 Grade 3 temperature ranges This document is a truncated version of the full PCI11414C datasheet. The comprehensive ver- sion may be obtained by contacting your Microchip sales representative. PCI11414C PCIe Switch with Integrated USB 3.2 Gen 2 Host Controller, Ethernet MAC and Programmable I/O

 2025 Microchip Technology Inc. and its subsidiaries DS00006234A-page 2 PCI11414C TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for cur - rent devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following:

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 2025 Microchip Technology Inc. and its subsidiaries DS00006234A-page 3 PCI11414C

1.0 PREFACE

Section 1.1, "General Terms"
Section 1.2, "Buffer Types"
Section 1.3, "Pin Reset States"
Section 1.4, "Reference Documents"

1.1 General Terms

TABLE 1-1: GENERAL TERMS Term Description AFE Analogue Front End ( AFE) Bandwidth Bandwidth is defined as the rate of data transfer, bit rate or throughput. CC CC is an abbreviation for Configuration Channel. This is used in the discovery, configuration and management of connections across a [USBTYPEC] cable. CDM CDM is an abbreviation for Charge Device Model. This is a Model of ESD caused by mechanical handling. See [JS-002-2014]. Completion In PCIe Completion refers to the Packet used to terminate, or to partially terminate, a transaction sequence. A Completion always corresponds to a preceding Request, and, in some cases, includes data. See [PCIe5]. Configuration Request Retry Status For PCI Configuration Requests only, following reset it is possible for a device to terminate the request but indicate that it is temporarily unable to process the Request, but will be able to process the PCI Configuration Request in the future - in this case, the Configuration Request Retry Status ( CRS) Completion Status is used. See [PCIe5]. Configuration Space One of the four address spaces within the PCI Express architecture. Packets with a Configuration Space address are used to configure Physical Functions. See [PCIe5]. CPU CPU is an abbreviation for Central Processing Unit. This is the main processor for the system. Note: In this case, the CPU is located on the Host system and not in the device itself which has no CPU. CRS CRS is an abbreviation for Configuration Request Retry Status . DFP DFP is an abbreviation for Downward Facing Port. This is a Port typically used to connect devices/peripherals (e.g. for USB or PCIe). Debouncer A Debouncer is a piece of hardware where the signal is passed through if it is stable for longer than a Debouncer period. Direct Memory Access Direct Memory Access is a feature of computer systems that allows certain hardware subsystems to access main system memory (RAM) independently of the central processing unit (CPU). With DMA, the CPU first initiates the transfer, then it does other operations while the transfer is in progress, and it finally receives an interrupt from the DMA Controller (DMAC) when the operation is done. DMA DMA is an abbreviation for Direct Memory Access. DMAC DMAC is an abbreviation for DMA Controller. DMA Controller A DMA Controller is a hardware device that allows I/O devices to directly access memory with less participation from the processor. EEPROM EEPROM is an abbreviation for Electrically Erasable Programmable Read-only Memory. EEPROM I²C Controller The EEPROM I²C Controller is used to read and write EEPROMs via I²C. ESD ESD is an abbreviation for Electro-static Discharge. FCS FCS is an abbreviation for Frame Check Sequence. FET FET is an abbreviation for Field Effect Transistor. This is typically used to switch on/off power. GPIO GPIO is an abbreviation for General Programmable I/O. It is used to refer to PIO accessible externally to the part. Since there is no internal PIO used in the device the terms PIO and GPIO have been used interchangeably. HBM HBM is an abbreviation for Human Body Model. The HBM simulates ESD from humans. See [JESD22-A115C]. Hot-Plug In PCI Hot-Plug is the insertion and removal of add-in cards without powering down the Platform or restarting the operating system from a specific Hot-Plug slot. See [PCIHotPlug].

 2025 Microchip Technology Inc. and its subsidiaries DS00006234A-page 4 PCI11414C I²C Inter-integrated Circuit: multi-Controller/multi-Target architecture. I²C is a 2-wire bus consisting of: I²C SDA, I²C SCL. Defined in [I2CBus]. I²C SCL I²C SCL is an abbreviation for the I²C Serial Clock line. I²C SDA I²C SDA is an abbreviation for the I²C Serial Data line. I²C Controller An I²C Controller refers to any device that initiates I²C transactions and drives the clock as defined in [I2CBus]. I²C Controller Core The I²C Controller Core implements both an I²C Controller and I²C Target. I²C Target An I²C Target is the Target of an I²C transaction which is driven by an I²C Controller as defined in [I2CBus]. In-Band In-Band refers to signaling sent using the main communication channel. See also Out-Of-Band. IRQ IRQ is an abbreviation for the Interrupt Request Line. MAC The Medium Access Control ( MAC) forms part of the Data Link Layer as defined in OSI. The MAC is responsible for controlling how devices in a network gain access to a medium and permission to transmit data. MFD MFD is an abbreviation for Multi-Function Device. Multi-Function Device A Multi-Function Device is a PCI Device with more than one Physical Function. Physical Functions in an MFD are numbered PF0, PF1, PF2 etc. N/A N/A is an abbreviation for Not Applicable. NC NC is an abbreviation for Not Connected. OCS OCS is an abbreviation for Over-Current Sense. OEM OEM is an abbreviation for Original Equipment Manufacturer. OTP OTP is an abbreviation for One Time Programmable Memory. Out-Of-Band Out-Of-Band refers to signaling sent outside of the main communication channel. See also In- Band. PCB PCB is an abbreviation for Printed Circuit Board. PCI Bridge The PCI Bridge is one of several PCI defined System Elements. A Function that connects a PCI/ PCI-X segment or PCI Express Port with an internal component interconnect or with another PCI/PCI-X bus segment or PCI Express Port. A virtual PCI Bridge in a Root Complex or PCI Switch must use the software configuration interface described in [PCIe5]. PCI Switch A PCI Switch is a [PCIe5] System Element that connects two or more Ports to allow Packets to be routed from one Port to another. To configuration software, a PCI Switch appears as a collection of virtual PCI Bridges. PCI Configuration Request A PCI Configuration Request PCI Packet targeted at the Configuration Space. See [PCIe5]. Note: This is not the same as a System Configuration Request . PD PD is an abbreviation for USB Power Delivery as defined in [USBPD3]. PF PF is an abbreviation for Physical Function. PHY PHY is an abbreviation for “physical layer ”, an electronic circuit required to implement physical layer functions of OSI in a network interface controller. Physical Function Within a Device, the Physical Function, is an addressable entity in Configuration Space associated with a single Function Number. Used to refer to one Function of a Multi-Function Device, or to the only Function in a Single-Function Device. Pin A Pin is an external connection on the package enabling connection to the PCB. PIO PIO is an abbreviation for Programmable I/O. These are fully programmable input/output lines. PLL PLL is an abbreviation for Phase-Locked Loop. Port Partner Port Partner refers to a remote port which is connected to the device’s local port. PVT Sensor PVT Sensor is an abbreviation for Process-Voltage-Temperature Sensor. QFN QFN is an abbreviation for a Quad-Flat No-leads package. RAM RAM is an abbreviation for Random-access Memory (read/write). RFE RFE is an abbreviation for Receive Filtering Engine. RGMII RGMII is an abbreviation for Reduced Gigabit Media-Independent Interface as defined in [RGMII]. RMII RMII is an abbreviation for Reduced Media-Independent Interface as defined in [RMII]. ROM ROM is an abbreviation for Read-only Memory. TABLE 1-1: GENERAL TERMS (CONTINUED) Term Description

 2025 Microchip Technology Inc. and its subsidiaries DS00006234A-page 5 PCI11414C Root Complex A Root Complex is a PCI defined System Element that includes at least one Host PCI Bridge, Root Port, or Root Complex Integrated Endpoint. The Host PCI Bridge connects a host CPU or CPUs to a PCI Hierarchy connected to the Root Port or Root Complex Integrated Endpoint. See [PCIe5]. SGMII+ SGMII+ is an abbreviation used in this document to refer to Serial Gigabit Media-Independent Interface as defined in [SGMII] which has been additionally over-clocked to run at bit rates up to 2.5 Gbit/s rather than the specification defined 1 Gbit/s. Side-Band In this document, Side-Band is used to refer to Registers or control paths accessed via any of the Side-Band options (SMBus/SPI). Sink Role A USB Type-C Port in Sink Role is sinking power from its Port Partner. SMBus SMBus is an abbreviation for System Management Bus, a two-wire bus derived from I²C. Defined in [SMBus3]. SMBus Controller An SMBus Controller refers to any device that initiates SMBus transactions and drives the clock as defined in [SMBus3]. SMBus Target An SMBus Target is the Target of an SMBus transaction which is driven by a SMBus Controller as defined in [SMBus3]. Source Role USB Type-C Port is in Source Role when it is sourcing power to its Port Partner as defined in [USBTYPEC] and [USBPD3]. Source-only Operation Source-only Operation refers to a USB Type-C Port which operates exclusively in USB Type-C/ Power Delivery Source Role as defined in [USBTYPEC] and [USBPD3]. SPI SPI is an abbreviation for Serial Peripheral Interface bus: a full-duplex bus utilizing a single- Controller/multi-Peripheral architecture. SPI is a 4-wire bus consisting of: SPI CLK, SPI COPI, SPI CIPO, SPI CS. SPI CLK SPI CLK refers to the SPI clock line. SPI CIPO SPI CIPO is an abbreviation for Controller In Peripheral Out for SPI connections. SPI Controller A SPI Controller is any device that initiates SPI transactions and drives the clock. SPI COPI SPI COPI is an abbreviation for Controller Out Peripheral In for SPI connections. SPI Peripheral Target of an SPI transaction which is driven by an SPI Controller. SPI CS SPI CS is an abbreviation for SPI Peripheral Chip Select used to select each individual SPI Peripheral on the bus. SRIS Separate Reference Clock with Independent SSC. SRNS Separate Reference Clock With No SSC. SSC Spread Spectrum Clocking System Configuration Request A System Configuration Request is a request initiated by setting bits in the GENERAL_SYS_CONFIG_REQ_REG Register indicating that part of the device needs to be configured from OTP/EEPROM and/or via SPI/SMBus. Note: This is not the same as a PCI Configuration Request . UART UART is an abbreviation for Universal Asynchronous Receiver Transmitter. UFP UFP is an abbreviation for Upward Facing Port: a Port typically taking the Device role. USB Host Controller A USB Host Controller provides a means for a computer system to manage USB Peripherals connected to the USB. The USB Host Controller provides an interface conforming with either [xHCI] for SuperSpeed USB or [eHCI] for low, full and high speed USB. USB Power Delivery Operation USB Power Delivery Operation refers to a Port which is operating using USB Power Delivery protocols in conformance to [USBPD3]. USB Type-C Operation USB Type-C Operation refers to a Port which is operating without using USB Power Delivery protocols and in conformance to [USBTYPEC]. UUID UUID is an abbreviation for Universally Unique Identifier. VBUS VBUS is the USB main power supply which operates as defined in [USB3.2], [USBTYPEC] and [USBPD3]. VCONN VCONN is the USB Supplementary power supply defined for the USB Type-C Connector in [USBTYPEC]. VSAFE0V Vsafe0V is the VBUS “0 Volt” level as defined by [USBPD3]. VSAFE5V Vsafe5V is the VBUS “5 Volt” level as defined by [USBPD3]. TABLE 1-1: GENERAL TERMS (CONTINUED) Term Description

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1.2 Buffer Types

The pin buffer type definitions are detailed in Table 1-2. Refer to Chapter 3.0, "Pin Descriptions and Configuration" for details on individual pin buffer type assignments. TABLE 1-2: BUFFER TYPE DESCRIPTIONS Buffer Description AI Analog input. AIO Analog bidirectional. DB Debouncer available on input pin (refer to Section 3.4, "Debouncers" ). I Input. I/O-P Analog input/output defined per the [PCIe3.1a] Specification. I/O-U Analog input/output defined per the USB 2.0 Specification. ICLK Crystal oscillator input pin. IR RBIAS pin. IS Input with Schmitt trigger in the VDD33 power domain. LVDS Low Voltage Differential Signaling. O_V10 Fixed voltage output with programmable output buffer up to 10 mA (2/4/8/10 mA) in the VDD33 power domain. OD_V10 Fixed voltage open drain output with programmable output buffer up to 10 mA (2/4/8/10 mA) in the VDD33 power domain. OCLK Crystal oscillator output pin. P Power pin. PD Internal pull-down. Unless otherwise noted in the pin description, internal pull-downs are always enabled. Internal pull-down resistors prevent unconnected inputs from floating. Do not rely on internal resistors to drive signals external to the device. When connected to a load that must be pulled low, an external resistor must be added. PU Internal pull-up. Unless otherwise noted in the pin description, internal pull-ups are always enabled. Internal pull-up resistors prevent unconnected inputs from floating. Do not rely on internal resistors to drive signals external to the device. When connected to a load that must be pulled high, an external resistor must be added. RGMII_I High-speed input defined per the Reduced Gigabit Media Independent Interface (RGMII) 2.0 Specification. RGMII_O High-speed output defined per the Reduced Gigabit Media Independent Interface (RGMII) 2.0 Specification. SGMII_I High-speed input defined per the Serial Gigabit Media Independent Interface (SGMII) 1.8 Specification. SGMII_O High-speed output defined per the Serial Gigabit Media Independent Interface (SGMII) 1.8 Specification. VIS Variable voltage Schmitt-triggered input in the VDDVARIO power domain. VO_V10 Variable voltage output with programmable output buffer up to 10 mA (2/4/8/10 mA) in the VDDV ARIO power domain. VOD_V10 Variable voltage open drain output with programmable output buffer up to 10 mA (2/4/8/10 mA) in the VDDV ARIO power domain. VIS-R Variable voltage Schmitt-triggered input in the VDDRGMII power domain.

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1.3 Pin Reset States

The pin reset state definitions are detailed in Table 1-3. Refer to Table 3-1 for details on individual pin reset states. VO-R_V10 Variable voltage output with programmable output buffer up to 10 mA (2/4/8/10 mA) in the VDDRGMII power domain. VOD-R_V10 Variable voltage open drain output with programmable output buffer up to 10 mA (2/4/8/10 mA) in the VDDRGMII power domain. VO-R_5 Variable voltage output with 5 mA sink and 5 mA source in the VDDRGMII power domain. VO-R_8 Variable voltage output with 8 mA sink and 8 mA source in the VDDRGMII power domain. VOD-R_8 Variable voltage open drain output with 8 mA sink in the VDDRGMII power domain. TABLE 1-3: PIN RESET STATE LEGEND Symbol Description AI Analog input AO Analog output IR RBIAS P Power PD Hardware enables pull-down Y Hardware enables function Z Hardware disables output driver (high impedance) TABLE 1-2: BUFFER TYPE DESCRIPTIONS (CONTINUED) Buffer Description

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1.4 Reference Documents

TABLE 1-4: REFERENCE DOCUMENTS Reference Document Name Revision/Version Date [ACPI] Advance Configuration and Power Interface (ACPI) Specification. https://uefi.org/sites/default/files/resources/ACPI_6_3_May16.pdf 6.3 2019-01 [AEC-Q100-002E] AEC - Q100-002, Human Body Model Electrostatic Discharge Test. http://www.aecouncil.com/Documents/AEC_Q100-002E.pdf E August 20, 2013 [AEC-Q100-003E] AEC - Q100-003, Machine Model (MM) Electrostatic Discharge Test (decommissioned specification). http://www.aecouncil.com/AECDocuments.html E [AEC-Q100-011C1] AEC - Q100-011, Charged Device Model ( CDM) Electrostatic Discharge Test. http://www.aecouncil.com/Documents/AEC_Q100-011C1.pdf 2013-03-12 [AN4255] AN4255 PCI12000/PCI11xxx Register Map Contact your Microchip representative for more information. Rev. A (02-21-22) [ASME-Y14.5M] ASME Y14.5M-2018, Dimensioning and Tolerancing. https://www.asme.org/products/codes-standards/y145-2018-dimensioning-and- tolerancing 14.5-2018 [eHCI] Enhanced Host Controller for USB 2.0 specification. https://www.intel.com/content/www/us/en/products/docs/io/universal-serial-bus/ehci- specification-for-usb.html R1.0 2002-03-12 [I2CBus] I2C bus specification and user manual. https://www.nxp.com/docs/en/user-guide/UM10204.pdf V.6 2014-04-04 [I2SBus] I2S bus specification. https://web.archive.org/web/20070102004400/http://www.nxp.com/acrobat_download/ various/I2SBUS.pdf N/A 1996-06-05 [IEC61000-4-2] IEC 61000-4-2:2008, Electromagnetic Compatibility (EMC) - Part 4-2: Testing and measurement techniques - Electrostatic discharge immunity test. https://webstore.iec.ch/publication/4189 2.0 2008-12-09 [JEP106] JEDEC Standard, JEP106, Standard Manufacturer’s Identification Code. https://www.jedec.org/system/files/docs/JEP106BB.pdf BB 2020-06 [JESD22-A115C] JEDEC, JESD22-A114F, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). https://www.jedec.org/sites/default/files/docs/22A115C_0.pdf 2010-11 [JESD78D] JEDEC, IC Latch-Up Test, JESD78D. https://www.jedec.org/sites/default/files/docs/JESD78D.pdf D 2011-11 [JS-001-2017] ANSI/ESDA/JEDEC JS-001-2017, for Electrostatic Discharge Sensitivity Testing, Human Body Model (HBM) - Component Level. https://www.jedec.org/system/files/docs/JS-001-2017.pdf 2017-05-12 [JS-002-2014] ANSI/ESDA/JEDEC JS-002-2014, for Electrostatic Discharge Sensitivity Testing, Charged Device Model ( CDM) - Device Level. https://www.jedec.org/system/files/docs/JS-002-2014.pdf 2015-04-07 [M.2] PCI Express M.2 Specification. https://pcisig.com/specifications/pciexpress/ Rev 3.0 v1.2 2019-06-26 [PCICode] PCI Code and ID Assignment Specification. https://pcisig.com/specifications/pciexpress/ Rev 1.11 2019-01-24 [PCIHotPlug] PCI Hot-Plug Specification. https://pcisig.com/specifications/pciexpress/ 1.1 2001-06-20 [PCIe3.1a] PCI Express Base Specification Revision 3.1a. https://pcisig.com/specifications/pciexpress/ R3.1a 2015-12-07 [PCIe4] PCI Express Base Specification Revision 4.0. https://pcisig.com/specifications/pciexpress/ R4.0, V1.0 2017-09-27 [PCIe5] PCI Express Base Specification Revision 5.0. https://pcisig.com/specifications/pciexpress/ R5.0 V1.0 2019-05-22

 2025 Microchip Technology Inc. and its subsidiaries DS00006234A-page 9 PCI11414C [RMII] Reduced Media Independent Interface (RMII). http://ebook.pldworld.com/_eBook/-Telecommunications%2CNetworks-/TCPIP/RMII/ rmii_rev12.pdf V1.2 1998-03-20 [RGMII] Reduced Gigabit Media Independent Interface (RGMII). https://web.archive.org/web/20160303171328/http://www.hp.com/rnd/pdfs/ RGMIIv2_0_final_hp.pdf V2.0 2002-04-01 [SGMII] Serial-GMII Specification (SGMII). https://archive.org/details/sgmii R1.8 2005-04-27 [SMBus2] System Management Bus (SMBus) Specification. http://www.smbus.org/specs/smbus20.pdf 2.0 2000-08-03 [SMBus3] System Management Bus (SMBus) Specification. http://www.smbus.org/specs/SMBus_3_0_20141220.pdf 3.0 2014-12-20 [USB2] Universal Serial Bus Revision 2.0 Specification. https://www.usb.org/document-library/usb-20-specification 2.0 + errata + ECNs, 2019-05-24 [USB3.2] Universal Serial Bus Revision 3.2 Specification + ECNs. https://www.usb.org/document-library/usb-32-specification-released-september-22-2017- and-ecns 3.2 + ECNs 2018-09-12 [USBHID1_11] USB Device Class Definition for Human Interface Devices (HID). https://www.usb.org/document-library/device-class-definition-hid-111 1.11 2001-06-27 [USBPD3] USB Power Delivery Specification. https://www.usb.org/document-library/usb-power-delivery 3.0 Version 1.2 + ECNs 2018-12-03 [USBTYPEC] USB Type-C Specification. https://www.usb.org/document-library/usb-type-cr-cable-and-connector-specification- revision-20 R2.1 2021-05 [xHCI] Intel eXtensible Host Controller Interface for Universal Serial Bus (xHCI). https://www.intel.com/content/dam/www/public/us/en/documents/technical- specifications/extensible-host-controler-interface-usb-xhci.pdf 1.2 2019-05 TABLE 1-4: REFERENCE DOCUMENTS (CONTINUED) Reference Document Name Revision/Version Date

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2.0 INTRODUCTION

2.1 General Description

The Microchip PCI11414C is a single-chip PCIe switch with an integrated USB 3.2 Gen 2 host controller, Ethernet MAC and programmable I/O. The integrated PCIe physical interfaces provide a 4-lane (4x8 GT/s) upstream port and a 1-lane (1x8 GT/s) downstream port. The device is targeted to address customer requests for higher bandwidth PCIe subsys- tems within embedded applications, with a maximum line rate of 8 GT/s. PCIe upstream can be delivered across a single or multiple lanes to accommodate best system architecture. The PCI11414C includes a compliant PCIe implementation from external facing physical interfaces through to switch fabric and endpoint controllers. PCIe PTM communicates precise timing information between components for scenarios where the time difference between the PCIe Host clock and the device clock needs to be determined, per PCI Express Base Specification R5.0 V1.0. PTM enables components to calculate the relationship between their local times and a shared, independent time domain called PTM Master Time. The PCI11414C includes a USB-IF and xHCI compliant USB 3.2 Gen 2 host controller which provides two USB 3.2 Gen 2 (USB Type-C) ports, and three USB 2.0 HS/FS/LS (USB Type-A) ports. USB-C support is provided, with CC1 & CC2 (Configuration Control) being managed by the PCI11414C. Overcurrent Sense (OCS) and Port Control are provided for control of Vbus. The PCI11414C also includes an IEEE 802.3 compliant 2.5 Gbps Ethernet MAC. The integrated RMII, RGMII, and SGMII interfaces support 10/100 Mbps, 10/100/1000 Mbps, and 1/2.5 Gbps operation, respectively. A programmable pin multiplexer is used to map I/O functions to package pins. This enables designers to work with either a default configuration or modify signals to best fit their application. Example signals include those associated with USB operation, through to GPIO or SMBus, which are accessed via a dedicated PCIe Endpoint Controller. Though many clocks are required for PCI11414C operation, these are generated within an integrated clock farm. Only a single-ended 25 MHz clock or crystal is required externally together with a PCIe reference clock. PCI11414C software presentation is enabled using standard abstractions to major operating systems. The PCI11414C is available in a 164-pin DQFN package in commercial (0°C to +70°C), industrial (-40°C to +85°C), or automotive Grade 3 (-40°C to +85°C) temperature ranges. Note: This document is for PCI11414C silicon revision C0 or newer only. For information on older PCI11414 silicon revisions A0 or B0, contact your Microchip sales representative.

 2025 Microchip Technology Inc. and its subsidiaries DS00006234A-page 11 PCI11414C An internal block diagram of the PCI11414C is shown in Figure 2-1. FIGURE 2-1: INTERNAL BLOCK DIAGRAM PCIe 1x Lane Downstream Port

25 MHz XTAL

1.1V PCIe PHY C PCIe EP Controller I/O Multiplexer Peripheral Devices PCIe PHY A & B PCIe 4x Lanes (4x 8 GT/s) Upstream Port PCIe Switch 4x Gen3 Port 1x Gen3 Port 4x Gen3 Po rt 1x Gen1 Port Configuration Registers

8 GT/s

3.3V SMBUS/SP I/UART/ GPIO PCI11414C

100 MHz

 2025 Microchip Technology Inc. and its subsidiaries DS00006234A-page 12 PCI11414C

3.0 PIN DESCRIPTIONS AND CONFIGURATION

The device pin diagram for the PCI11414C can be seen in Figure 3-1. Table 3-1 provides a PCI11414C pin assignments table with reset states. Pin descriptions are detailed in Section 3.1, "Pin Descriptions". Configuration strap descriptions are detailed in Section 3.2, "Configuration Straps". Programmable function pin descriptions are detailed in Section 3.3, "Programmable Function Pins". Buffer type and pin reset state definitions are provided in Section 1.2, "Buffer Types" and Section 1.3, "Pin Reset States", respectively. FIGURE 3-1: PIN ASSIGNMENTS Note: Configuration straps are identified by an underlined symbol name. Signals that function as configuration straps must be augmented with an external resistor when connected to a load. Microchip PCI11414C (Top View 164-DQFN) 100 102 104 106 10 8 110 11 2 114 11 6 11 8 12 0 12 2 125 12 7 12 9 13 1 13 3 13 5 13 7 13 9 14 1 14 3 14 5 14 7 14 9 15 1 15 3 15 5 12 4 12 6 12 8 13 0 13 2 13 4 13 6 13 8 14 0 14 2 14 4 14 6 14 8 15 0 15 2 15 4 15 6 163 16 1 15 9 15 7 PROG1 PROG2 PROG3 PROG4 PROG5 PROG6 VDD33 PROG7 PROG8 PROG9 PROG10 PROG18/PVT2 VDD33PVTREF VSSPVTREF PROG17/PVT1 PCIE_RXP_L1_P0 PCIE_RXM_L1_P0 PCIE_TXP_L0_P0 PCIE_TXM_L0_P0 PCIE_RXP_L0_P0 PCIE_RXM_L0_P0 VDD11PA VDD11 VDD33PA VDD33PA VDD11PA VDD33PA VDD11PA PROG19 PROG20 PROG21 PROG22 VDDVARIO PROG23 PROG24 PROG31 VDDVARIO PROG32 PROG33 PROG34 VDD11PB PCIE_TXP_L2_P0 PCIE_TXM_L2_P0 PCIE_RXP_L2_P0 PCIE_RXM_L2_P0 PCIE_TXP_L3_P0 PCIE_TXM_L3_P0 PCIE_RXP_L3_P0 PCIE_RXM_L3_P0 VDD33WRPLL VSSWRPLL VDD11PB VDD11 VDD33PB VDD33PB VDD11PB VDD33PB PROG46/ENET_MDC PROG47/ENET_MDIO VDDRGMII PROG56/SGMII_CLKM/RGMII_RXD2/RMII_RX_ER PROG55/SGMII_TXM/RGMII_RXD1/RMII_RXD1 PROG54/SGMII_TXP/RGMII_RXD0/RMII_RXD0 PROG53/SGMII_RXM/RGMII_RXC/RMII_REF_CLK_IN PROG52/SGMII_RXP/RGMII_RX_CTL/RMII_CRS_DV PROG51/ENET_PHY_INT_N PROG57/SGMII_CLKP/RGMII_RXD3 PROG50/ENET_LINK PROG49/ENET_DUPLEX PROG48/ENET_PHY_RESET_N PROG63/RGMII_TXD3 PROG62/RGMII_TXD2 PROG61/RGMII_TXD1/RMII_TXD1 PROG60/RGMII_TXD0/RMII_TXD0 PROG59/RGMII_TX_CTL/RMII_TX_EN ENET_RESREF PROG58/RGMII_TXC/RMII_REF_CLK_OUT VDDRGMII VSSXTAL USB2_DM_P2 CC1_P2 USB2_DP_P2 USB3_TX1P_P2/USB3_TX2P_P1 USB3_TX1M_P2/USB3_TX2M_P1 USB3_RX1P_P2/USB3_RX2P_P1 USB3_RX1M_P2/USB3_RX2M_P1 VDD11ARX0 VDD33A0 CC2_P2 USB2_DM_P1 CC1_P1 USB2_DP_P1 USB3_TX1P_P1 USB3_TX1M_P1 USB3_RX1P_P1 USB3_RX1M_P1 VDD11 CC2_P1 XTALO XTALI/CLK_IN VDD11XTAL VDDVARIO PROG64/SMBUS_SCL_PU VDD11ARX1 VDD33A1 PROG65/SMBUS_SDA_PU PROG66 PROG67 PROG68/SERIAL_SEL_STRAP ATEST0 VBUS_MON_P1 TESTEN RESET_N USB2_DP_P3 USB2_DM_P3 VBUS_MON_P2 USB2_DP_P4 USB2_DM_P4 VDD11 PCIE_REFCLK_IN_P PCIE_REFCLK_IN_M PCIE_TXP_L0_P1 PCIE_TXM_L0_P1 PCIE_RXP_L0_P1 PCIE_RXM_L0_P1 PROG75/PCIE_ATEST VDD11 VDD33 PROG76 PROG77 PROG78 PROG79/EEPROM_STRAP PROG80 VDD33PC VDD11PC VDD11PC VDD33PC VDD11PC PROG81 PROG82 PROG83 PROG84 PROG85 PROG86 VDD33 PROG87 VDD11PA VDD11PA VDD11PB VDD11PB VDD11ENET VDD33ENET PROG69 PROG70 PROG71 PCIE_PERST_N E-PAD is VSS VDD33 PROG0 PROG29 PROG30 VDD11ATX0 VDD11ATX1

 2025 Microchip Technology Inc. and its subsidiaries DS00006234A-page 13 PCI11414C TABLE 3-1: PIN ASSIGNMENTS Pin Pin Name Reset Pin Pin Name Reset

1 PROG1 Z 83 PROG59/RGMII_TX_CTL/RMII_TX-

_EN Z

2 PROG2 Z 84 VDDRGMII P

3 PROG3 Z 85 PROG60/RGMII_TXD0/RMII_TXD0 Z

4 PROG4 Z 86 PROG61/RGMII_TXD1/RMII_TXD1 Z

5 PROG5 Z 87 PROG62/RGMII_TXD2 Z

6 VDD33 P 88 PROG63/RGMII_TXD3 Z

7 PROG6 Z 89 PROG64/SMBUS_SCL_PU Z

8 PROG7 Z 90 PROG65/SMBUS_SDA_PU Z

9 PROG8 Z 91 PROG66 Z

10 PROG9 Z 92 PROG67 Z

11 PROG10 Z 93 PROG68/SERIAL_SEL_STRAP Z

12 PCIE_RXP_L0_P0 Z 94 VSSXTAL P

13 PCIE_RXM_L0_P0 Z 95 XTALI/CLK_IN AI

14 VDD11PA P 96 XTALO AO

15 VDD33PA P 97 VDD11XTAL P

16 PCIE_TXP_L0_P0 Z 98 VDDV ARIO P

17 PCIE_TXM_L0_P0 Z 99 PROG69 Z

18 VDD11PA P 100 PROG70 Z

19 VDD11PA P 101 PROG71 Z

20 VDD33PA P 102 VDD11 P

21 VDD11PA P 103 CC1_P2 AI

22 PCIE_TXM_L1_P0 Z 104 CC2_P2 AI

23 PCIE_TXP_L1_P0 Z 105 USB2_DP_P2 Z

24 VDD33PA P 106 USB2_DM_P2 Z

25 VDD11PA P 107 USB3_TX1P_P2/USB3_TX2P_P1 Z

26 PCIE_RXM_L1_P0 Z 108 USB3_TX1M_P2/USB3_TX2M_P1 Z

27 PCIE_RXP_L1_P0 Z 109 VDD11ATX0 P

28 VDD11 P 110 VDD11ARX0 P

29 VDD33PVTREF P 111 USB3_RX1P_P2/USB3_RX2P_P1 Z

30 VSSPVTREF P 112 USB3_RX1M_P2/USB2_RX2M_P1 Z

31 PROG17/PVT1 Z 113 VDD33A0 P

32 PROG18/PVT2 Z 114 CC1_P1 AI

33 PROG19 Z 115 CC2_P1 AI

34 PROG20 Z 116 USB2_DP_P1 Z

35 PROG21 Z 117 USB2_DM_P1 Z

36 PROG22 Z 118 USB3_TX1P_P1 Z

37 VDDV ARIO P 119 USB3_TX1M_P1 Z

 2025 Microchip Technology Inc. and its subsidiaries DS00006234A-page 14 PCI11414C

38 PROG23 Z 120 VDD11ATX1 P

39 PROG24 Z 121 VDD11ARX1 P

40 PROG29 Z 122 USB3_RX1P_P1 Z

41 PROG30 Z 123 USB3_RX1M_P1 Z

42 PROG31 Z 124 VDD33A1 P

43 PROG32 Z 125 ATEST0 Z

44 PROG33 Z 126 RESET_N Z/Y

45 PROG34 Z 127 TESTEN PD

46 VDDV ARIO P 128 PCIE_PERST_N Z

47 PCIE_RXP_L2_P0 Z 129 VBUS_MON_P1 Z

48 PCIE_RXM_L2_P0 Z 130 USB2_DP_P3 Z

49 VDD11PB P 131 USB2_DM_P3 Z

50 VDD33PB P 132 VBUS_MON_P2 Z

51 PCIE_TXP_L2_P0 Z 133 USB2_DP_P4 Z

52 PCIE_TXM_L2_P0 Z 134 USB2_DM_P4 Z

53 VDD11PB P 135 VDD11 P

54 VDD11PB P 136 PCIE_RXP_L0_P1 Z

55 VDD33PB P 137 PCIE_RXM_L0_P1 Z

56 VDD11PB P 138 VDD11PC P

57 PCIE_TXM_L3_P0 Z 139 VDD33PC P

58 PCIE_TXP_L3_P0 Z 140 PCIE_TXP_L0_P1 Z

59 VDD33PB P 141 PCIE_TXM_L0_P1 Z

60 VDD11PB P 142 VDD11PC P

61 PCIE_RXM_L3_P0 Z 143 VDD11PC P

62 PCIE_RXP_L3_P0 Z 144 VDD33PC P

63 VSSWRPLL P 145 PCIE_REFCLK_IN_P Z

64 VDD33WRPLL P 146 PCIE_REFCLK_IN_M Z

65 PROG46/ENET_MDC Z 147 VDD11 P

66 PROG47/ENET_MDIO Z 148 PROG75 Z

67 VDD11 P 149 PROG76 Z

68 VDDRGMII P 150 PROG77 Z

69 PROG48/ENET_PHY_RESET_N Z 151 PROG78 Z

70 PROG49/ENET_DUPLEX Z 152 PROG79/EEPROM_STRAP Z

71 PROG50/ENET_LINK Z 153 PROG80 Z

72 PROG51/ENET_PHY_INT_N Z 154 VDD33 P

73 PROG52/SGMII_RXP/

RGMII_RX_CTL/RMII_CRS_DV Z 155 PROG81 Z

74 PROG53/SGMIIRXM/RGMII_RXC/

RMII_REF_CLK_IN Z 156 PROG82 Z TABLE 3-1: PIN ASSIGNMENTS (CONTINUED) Pin Pin Name Reset Pin Pin Name Reset

 2025 Microchip Technology Inc. and its subsidiaries DS00006234A-page 15 PCI11414C

75 PROG54/SGMII_TXP/RGMII_RXD0/

RMII_RXD0 Z 157 PROG83 Z

76 PROG55/SGMII_TXM/RGMII_RXD1/

RMII_RXD1 Z 158 PROG84 Z

77 PROG56/SGMII_CLKM/RGMII_RXD2/

RMII_RX_ER Z 159 PROG85 Z

78 PROG57/SGMII_CLKP/RGMII_RXD3 Z 160 PROG86 Z

79 VDD11ENET P 161 VDD33 P

80 VDD33ENET P 162 PROG87 Z

81 ENET_RESREF IR 163 VDD33 P

82 PROG58/RGMII_TXC/

RMII_REF_CLK_OUT Z 164 PROG0 Z Exposed Pad (VSS) must be connected to ground. TABLE 3-1: PIN ASSIGNMENTS (CONTINUED) Pin Pin Name Reset Pin Pin Name Reset

 2025 Microchip Technology Inc. and its subsidiaries DS00006234A-page 16 PCI11414C

3.1 Pin Descriptions

TABLE 3-2: PIN DESCRIPTIONS Name Symbol Buffer Type Description USB 3.2 Data Interface Pins USB 3.2 Port 1 TX1+ USB3_TX1P_P1 I/O-U USB 3.2 Port 1 TX1+ USB 3.2 Port 1 TX1- USB3_TX1M_P1 I/O-U USB 3.2 Port 1 TX1- USB 3.2 Port 1 RX1+ USB3_RX1P_P1 I/O-U USB 3.2 Port 1 RX1+ USB 3.2 Port 1 RX1- USB3_RX1M_P1 I/O-U USB 3.2 Port 1 RX1- USB 3.2 Port 1 TX2+ USB3_TX2P_P1 I/O-U USB 3.2 Port 1 TX2+ USB 3.2 Port 1 TX2- USB3_TX2M_P1 I/O-U USB 3.2 Port 1 TX2- USB 3.2 Port 1 RX2+ USB3_RX2P_P1 I/O-U USB 3.2 Port 1 RX2+ USB 3.2 Port 1 RX2- USB3_RX2M_P1 I/O-U USB 3.2 Port 1 RX2- USB 3.2 Port 2 TX1+ USB3_TX1P_P2 I/O-U USB 3.2 Port 2 TX1+ USB 3.2 Port 2 TX1- USB3_TX1M_P2 I/O-U USB 3.2 Port 2 TX1- USB 3.2 Port 2 RX1+ USB3_RX1P_P2 I/O-U USB 3.2 Port 2 RX1+ USB 3.2 Port 2 RX1- USB3_RX1M_P2 I/O-U USB 3.2 Port 2 RX1- USB 2.0 Data Interface Pins USB 2.0 Port 1 USB2_DP_P1 I/O-U USB 2.0 Port 1 D+ USB 2.0 Port 1 USB2_DM_P1 I/O-U USB 2.0 Port 1 D- USB 2.0 Port 2 USB2_DP_P2 I/O-U USB 2.0 Port 2 D+ USB 2.0 Port 2 USB2_DM_P2 I/O-U USB 2.0 Port 2 D- USB 2.0 Port 3 USB2_DP_P3 I/O-U USB 2.0 Port 3 D+ USB 2.0 Port 3 USB2_DM_P3 I/O-U USB 2.0 Port 3 D-

 2025 Microchip Technology Inc. and its subsidiaries DS00006234A-page 17 PCI11414C USB 2.0 Port 4 USB2_DP_P4 I/O-U USB 2.0 Port 4 D+ USB 2.0 Port 4 USB2_DM_P4 I/O-U USB 2.0 Port 4 D- USB Type-C Pins USB Type-C Port 1 CC1 CC1_P1 I/O-U USB Type-C CC1 Port 1 USB Type-C Port 2 CC1 CC1_P2 I/O-U USB Type-C CC1 Port 2 USB Type-C Port 1 CC2 CC2_P1 I/O-U USB Type-C CC2 Port 1 USB Type-C Port 2 CC2 CC2_P2 I/O-U USB Type-C CC2 Port 2 VBUS Monitor Pins VBUS Monitor Port 1 VBUS_MON_P1 AI VBUS Monitor on Port 1 VBUS Monitor Port 2 VBUS_MON_P2 AI VBUS Monitor on Port 2 PCIe Common Pins PCIe REFCLK+ Input PCIE_REFCLK_IN_P LVDS Common PCIe REFCLK+ input from host PCIe REFCLK- Input PCIE_REFCLK_IN_M LVDS Common PCIe REFCLK- input from host PCIe Reset# Input PCIE_PERST_N IS Power and Clock Good Indication The PERST# signal indicated that both PCIe power and clock are available. This active low signal is used by the system to reset the chip. The active low pulse should be at least 1 µs wide. Note: When the device is powered down, this pin is isolated from the PCIe bus and does not pres- ent any significant loading or provide any drive. PCIe Port 0 (Upstream) Pins PCIe TX+ Lane 0 Port 0 PCIE_TXP_L0_P0 I/O-P Upstream PCIe Port 0 Lane 0 TX+ PCIe TX- Lane 0 Port 0 PCIE_TXM_L0_P0 I/O-P Upstream PCIe Port 0 Lane 0 TX- PCIe RX+ Lane 0 Port 0 PCIE_RXP_L0_P0 I/O-P Upstream PCIe Port 0 Lane 0 RX+ PCIe RX- Lane 0 Port 0 PCIE_RXM_L0_P0 I/O-P Upstream PCIe Port 0 Lane 0 RX- TABLE 3-2: PIN DESCRIPTIONS (CONTINUED) Name Symbol Buffer Type Description

 2025 Microchip Technology Inc. and its subsidiaries DS00006234A-page 18 PCI11414C PCIe TX+ Lane 1 Port 0 PCIE_TXP_L1_P0 I/O-P Upstream PCIe Port 0 Lane 1 TX+ PCIe TX- Lane 1 Port 0 PCIE_TXM_L1_P0 I/O-P Upstream PCIe Port 0 Lane 1 TX- PCIe RX+ Lane 1 Port 0 PCIE_RXP_L1_P0 I/O-P Upstream PCIe Port 0 Lane 1 RX+ PCIe RX- Lane 1 Port 0 PCIE_RXM_L1_P0 I/O-P Upstream PCIe Port 0 Lane 1 RX- PCIe TX+ Lane 2 Port 0 PCIE_TXP_L2_P0 I/O-P Upstream PCIe Port 0 Lane 2 TX+ PCIe TX- Lane 2 Port 0 PCIE_TXM_L2_P0 I/O-P Upstream PCIe Port 0 Lane 2 TX- PCIe RX+ Lane 2 Port 0 PCIE_RXP_L2_P0 I/O-P Upstream PCIe Port 0 Lane 2 RX+ PCIe RX- Lane 2 Port 0 PCIE_RXM_L2_P0 I/O-P Upstream PCIe Port 0 Lane 2 RX- PCIe TX+ Lane 3 Port 0 PCIE_TXP_L3_P0 I/O-P Upstream PCIe Port 0 Lane 3 TX+ PCIe TX- Lane 3 Port 0 PCIE_TXM_L3_P0 I/O-P Upstream PCIe Port 0 Lane 3 TX- PCIe RX+ Lane 3 Port 0 PCIE_RXP_L3_P0 I/O-P Upstream PCIe Port 0 Lane 3 RX+ PCIe RX- Lane 3 Port 0 PCIE_RXM_L3_P0 I/O-P Upstream PCIe Port 0 Lane 3 RX- PCIe Port 1 (Downstream) Pins PCIe TX+ Lane 0 Port 1 PCIE_TXP_L0_P1 I/O-P Downstream PCIe Port 1 Lane 0 TX+ PCIe TX- Lane 0 Port 1 PCIE_TXM_L0_P1 I/O-P Downstream PCIe Port 1 Lane 0 TX- PCIe RX+ Lane 0 Port 1 PCIE_RXP_L0_P1 I/O-P Downstream PCIe Port 1 Lane 0 RX+ PCIe RX- Lane 0 Port 1 PCIE_RXM_L0_P1 I/O-P Downstream PCIe Port 1 Lane 0 RX- TABLE 3-2: PIN DESCRIPTIONS (CONTINUED) Name Symbol Buffer Type Description

 2025 Microchip Technology Inc. and its subsidiaries DS00006234A-page 19 PCI11414C Ethernet PHY Management Pins Ethernet MDC ENET_MDC VO-R_8 This is the management clock output to an external PHY Ethernet MDIO ENET_MDIO VIS-R/ VO-R_8 (PU) This is the management data to/from an external PHY Note: To avoid a floating signal, an external pull-up is recommended when the MDIO interface is not used. Note: To ensure the IDLE state of the MDIO signal is logic one, an external pull-up is required when the MDIO interface is used. APPLICATION NOTE: A pull-up (internal or external) will result in a return value of FFFFh when a non-existent or non- addressed PHY is read. If a value of 0000h is desired instead, a pull-down may be used. Ethernet PHY Reset ENET_PHY_RESET_N VO-R_8 Reset to external Ethernet PHY Ethernet Duplex Mode ENET_DUPLEX VIS-R Duplex mode. This signal connects to the Duplex Mode output from the partner PHY . Note: When set, the partner PHY is in Full Duplex mode. Note: If the partner PHY does not have a duplex out- put signal, then it is recommended that this signal should be tied to VDD33ENET to force full duplex operation. Ethernet Link ENET_LINK VIS-R Ethernet link status change indication Ethernet PHY Interrupt ENET_PHY_INT_N VIS-R Interrupt from external Ethernet PHY RGMII (10/100/1000 PHY) Pins RGMII Receive Control RGMII_RX_CTL RGMII_I RGMII receive control indicates both the receive data valid (RXDV) and receive error (RXER) functions per the RGMII specification. The PHY transfers data to the MAC using this signal. Note: This pin function is muxed with SGMII_RXP. RGMII Receive Clock RGMII_RXC RGMII_I RGMII receive clock signal (recovered from incoming received data). Note: This signal can be shared with an input-only programmable pin function. Note: This pin function is muxed with SGMII_RXM. TABLE 3-2: PIN DESCRIPTIONS (CONTINUED) Name Symbol Buffer Type Description

 2025 Microchip Technology Inc. and its subsidiaries DS00006234A-page 20 PCI11414C RGMII Receive Data 0 RGMII_RXD0 RGMII_I RGMII Receive Data 0. The PHY transfers data to the MAC using this signal. Note: This signal can be shared with an input-only programmable pin function. Note: This pin function is muxed with SGMII_TXP. RGMII Receive Data 1 RGMII_RXD1 RGMII_I RGMII Receive Data 1. The PHY transfers data to the MAC using this signal. Note: This signal can be shared with an input-only programmable pin function. Note: This pin function is muxed with SGMII_TXM. RGMII Receive Data 2 RGMII_RXD2 RGMII_I RGMII Receive Data 2. The PHY transfers data to the MAC using this signal. Note: This signal can be shared with an input-only programmable pin function. Note: This pin function is muxed with SGMII_- CLKM. RGMII Receive Data 3 RGMII_RXD3 RGMII_I RGMII Receive Data 3. The PHY transfers data to the MAC using this signal. Note: This signal can be shared with an input-only programmable pin function. Note: This pin function is muxed with SGMII_CLKP. RGMII Transmit Clock RGMII_TXC RGMII_O RGMII transmit clock is used to latch data from the MAC into the PHY in RGMII mode. RGMII Transmit Control RGMII_TX_CTL RGMII_O RGMII transmit control indicates both the transmit data enable (TXEN) and transmit error (TXER) func- tions per the RGMII specification. RGMII Transmit Data 0 RGMII_TXD0 RGMII_O RGMII Transmit Data 0. The MAC transmits data to the PHY using this signal. RGMII Transmit Data 1 RGMII_TXD1 RGMII_O RGMII Transmit Data 1. The MAC transmits data to the PHY using this signal. RGMII Transmit Data 2 RGMII_TXD2 RGMII_O RGMII Transmit Data 2. The MAC transmits data to the PHY using this signal. RGMII Transmit Data 3 RGMII_TXD3 RGMII_O RGMII Transmit Data 3. The MAC transmits data to the PHY using this signal. RMII (10/100 PHY) Pins RMII Carrier Sense (CRS) and RX Data Valid (RX_DV) RMII_CRS_DV RGMII_I Multiplexed on alternate clock cycles. In 10 Mbit/s mode, it alternates every 10 clock cycles. Note: This pin function is muxed with SGMII_RXP. TABLE 3-2: PIN DESCRIPTIONS (CONTINUED) Name Symbol Buffer Type Description

 2025 Microchip Technology Inc. and its subsidiaries DS00006234A-page 21 PCI11414C RMII 50 MHz Reference Clock (in) RMII_REF_CLK_IN RGMII_I Reference clock may be an input on both devices from an external clock source, or may be driven from the MAC to the PHY , or may be driven from the PHY to the MAC. Note: This signal can be shared with an input-only programmable pin function. Note: This pin function is muxed with SGMII_RXM. RMII Receive Data 0 RMII_RXD0 RGMII_I RMII Receive Data 0. The PHY transfers data to the MAC using this signal. Note: This signal can be shared with an input-only programmable pin function. Note: This pin function is muxed with SGMII_TXP. RMII Receive Data 1 RMII_RXD1 RGMII_I RMII Receive Data 1. The PHY transfers data to the MAC using this signal. Note: This signal can be shared with an input-only programmable pin function. Note: This pin function is muxed with SGMII_TXM. RMII Receive Error RMII_RX_ER RGMII_I RMII Receive error. Note: This pin function is muxed with SGMII_- CLKM. RMII 50 MHz Reference Clock (out) RMII_REF_CLK_OUT RGMII_O Reference clock may be an input on both devices from an external clock source, or may be driven from the MAC to the PHY , or may be driven from the PHY to the MAC. Note: This signal can be shared with an input-only programmable pin function. Note: This pin function is muxed with SGMII_CLKP. RMII Transmit Control RMII_TX_EN RGMII_O Indicates the transmit data enable (TXEN) function per the RMII specification. RMII Transmit Data 0 RMII_TXD0 RGMII_O RMII Transmit Data 0. The MAC transmits data to the PHY using this signal. RMII Transmit Data 1 RMII_TXD1 RGMII_O RMII Transmit Data 1. The MAC transmits data to the PHY using this signal. SGMII+ (10/100/1000/2.5G PHY) Pins SGMII+ Receive Data+ SGMII_RXP SGMII_I SGMII+ Receive Data+ Note: This pin function is muxed with RGMII_RX- _CTL. SGMII+ Receive Data- SGMII_RXM SGMII_I SGMII+ Receive Data- Note: This pin function is muxed with RGMII_RXC. SGMII+ Transmit Data+ SGMII_TXP SGMII_O SGMII+ Transmit Data+ Note: This pin function is muxed with RGMII_RXD0. TABLE 3-2: PIN DESCRIPTIONS (CONTINUED) Name Symbol Buffer Type Description

 2025 Microchip Technology Inc. and its subsidiaries DS00006234A-page 22 PCI11414C SGMII+ Transmit Data- SGMII_TXM SGMII_O SGMII+ Transmit Data- Note: This pin function is muxed with RGMII_RXD1. SGMII+ Clock- SGMII_CLKM SGMII_I SGMII+ Clock- Note: This pin function is muxed with RGMII_RXD2. SGMII+ Clock+ SGMII_CLKP SGMII_I SGMII+ Clock+ Note: This pin function is muxed with RGMII_RXD3. Programmable Function Pins Programmable Pins 0-10 PROG[0:10] IS/O_V10/ OD_V10 DB Programmable pins 0-10. Refer to Section 3.3, Programmable Function Pins for additional information. Programmable Pins 17-24 PROG[17:24] VIS/VO_V10/ VOD_V10 DB Programmable pins 17-24. Refer to Section 3.3, Programmable Function Pins for additional information. Programmable Pins 29-34 PROG[29:34] VIS/VO_V10/ VOD_V10 DB Programmable pins 29-34. Refer to Section 3.3, Programmable Function Pins for additional information. Programmable Pins 46-51 PROG[46:51] VIS-R/ VO-R_V10/ VOD-R_V10 DB Programmable pins 46-51. Refer to Section 3.3, Programmable Function Pins for additional information. Programmable Pins 52-57 PROG[52:57] VIS-R DB Programmable pins 52-57. Refer to Section 3.3, Programmable Function Pins for additional information. Programmable Pins 58-63 PROG[58:63] VIS-R VO-R_5 DB Programmable pins 58-63. Refer to Section 3.3, Programmable Function Pins for additional information. Programmable Pins 64-71 PROG[64:71] VIS/VO_V10/ VOD_V10 DB Programmable pins 64-71. Refer to Section 3.3, Programmable Function Pins for additional information. Programmable Pins 75-87 PROG[75:87] IS/O_V10/ OD_V10 DB Programmable pins 75-87. Refer to Section 3.3, Programmable Function Pins for additional information. Miscellaneous Pins Reset Input RESET_N IS This active low signal is used by the system to reset the chip. The active low pulse should be at least 1 µs wide. PVT Input 1 PVT1 AI PVT thermal monitor input 1 PVT Input 2 PVT2 AI PVT thermal monitor input 2 TABLE 3-2: PIN DESCRIPTIONS (CONTINUED) Name Symbol Buffer Type Description

 2025 Microchip Technology Inc. and its subsidiaries DS00006234A-page 23 PCI11414C

25 MHz

XTALI/CLK_IN ICLK 25 MHz crystal or external clock input. This pin can be connected to one terminal of the crystal. The device may alternatively be driven by a single-ended clock oscillator. When this method is used, XTALO should be left unconnected. XTALO OCLK 25 MHz crystal output. SGMII Refer- ence Resistor ENET_RESREF IR Connect a 200 Ω 1% +/-100 ppm/°C resistor between this pin and ground using a short trace to avoid noise coupling. Test Enable TESTEN I This pin is used to enter test mode (JTAG) and is read during the negation of reset. 1: Test Mode enabled 0: Test Mode disabled Note: This pin should be pulled down to ground for normal operation. Analog Test Point ATEST0 AIO Analog test point 0. Note: This pin should be pulled down to ground for normal operation. Configuration Strap Pins EEPROM Configuration Strap EEPROM_STRAP I This configuration strap defines whether a device configuration should be read from EEPROM. See Note 3-1. Refer to Section 3.2, "Configuration Straps" for additional information. Note: When enabled, the EEPROM interface must also be enabled via the PROGxx pins. Refer to Section 3.3, "Programmable Function Pins" for additional information. Serial Interface Configuration Strap SERIAL_SEL_STRAP I This configuration strap defines whether a configura - tion will be written via a serial interface (SMBus or SPI). See Note 3-1. Refer to Section 3.2, "Configura- tion Straps" for additional information. Note: When enabled, the SMBus or SPI interface must be also enabled via the PROGxx pins. Refer to Section 3.3, "Programmable Function Pins" for additional information. TABLE 3-2: PIN DESCRIPTIONS (CONTINUED) Name Symbol Buffer Type Description

 2025 Microchip Technology Inc. and its subsidiaries DS00006234A-page 24 PCI11414C SMBus SCL Pull-Up Configuration Strap SMBUS_SCL_PU I This configuration strap defines whether an external pull-up on the SCL line is used for normal operation (typically 10 kΩ). When the SERIAL_SEL_STRAP is present, this pull-up is used together with the SMBUS_SDA_PU to determine whether SMBus or SPI has been configured as the serial configuration mechanism. See Note 3-1. Refer to Section 3.2, "Configuration Straps" for additional information. Note: When both SMBUS_SDA_PU and SMBUS_S- CL_PU are present, the SMBus interface must also be enabled via the PROGxx pins. Otherwise, the SPI interface must be enabled via the PROGxx pins. Refer to Section 3.3, "Programmable Function Pins" for additional information. SMBus SDA Pull-Up Configuration Strap SMBUS_SDA_PU I This configuration strap defines whether an external pull-up on the SDA line is used for normal operation (typically 10 kΩ). When the SERIAL_SEL_STRAP is present, this pull-up is used together with the SMBUS_SCL_PU to determine whether SMBus or SPI has been configured as the serial configuration mechanism. See Note 3-1. Refer to Section 3.2, "Configuration Straps" for additional information. Note: When both SMBUS_SDA_PU and SMBUS_S- CL_PU are present, the SMBus interface must also be enabled via the PROGxx pins. Otherwise, the SPI interface must be enabled via the PROGxx pins. Refer to Section 3.3, "Programmable Function Pins" for additional information. Power/Ground Pins +3.3V Power Supply Input VDD33 P +3.3V power supply input. Provides +3.3V supply to the I/O rail. Connect to an external +3.3V supply. See Note 3-3. +1.1V Core Supply Input VDD11 P +1.1V power supply input. Provides +1.1V supply to the core. Connect to an external +1.1V supply. See Note 3-2. +3.3V USB AFE Power Supply Input 0 VDD33A0 P +3.3V power supply input to USB AFE. Provides +3.3V supply to the USB AFE. Connect to an external +3.3V supply. See Note 3-3. +1.1V USB AFE Core Transmit Supply Input 0 VDD11ATX0 P +1.1V power supply input to USB AFE core. Provides +1.1V supply to the USB AFE. Connect to an external +1.1V supply. See Note 3-2. +1.1V USB AFE Core Receive Supply Input 0 VDD11ARX0 P +1.1V power supply input to USB AFE core. Provides +1.1V supply to the USB AFE. Connect to an external +1.1V supply. See Note 3-2. TABLE 3-2: PIN DESCRIPTIONS (CONTINUED) Name Symbol Buffer Type Description

 2025 Microchip Technology Inc. and its subsidiaries DS00006234A-page 25 PCI11414C +3.3V USB AFE Power Supply Input 1 VDD33A1 P +3.3V power supply input to USB AFE. Provides +3.3V supply to the USB AFE. Connect to an external +3.3V supply. See Note 3-3. +1.1V USB AFE Core Transmit Supply Input 1 VDD11ATX1 P +1.1V power supply input to USB AFE core. Provides +1.1V supply to the USB AFE. Connect to an external +1.1V supply. See Note 3-2. +1.1V USB AFE Core Receive Supply Input 1 VDD11ARX1 P +1.1V power supply input to USB AFE core. Provides +1.1V supply to the USB AFE. Connect to an external +1.1V supply. See Note 3-2. +1.8V to +3.3V Variable I/O Supply Input VDDV ARIO P +1.8V to +3.3V variable I/O supply input. Provides variable +1.8/2.5/3.3V supply to the I/O rail. Connect to an external +1.8/2.5/3.3V supply. +3.3V Wide- Range PLL Supply Input VDD33WRPLL P +3.3V wide-range PLL supply input. Provides +3.3V supply to the wide-range PLL. See Note 3-3. Wide-Range PLL Ground VSSWRPLL P Wide-Range PLL ground. This is the analog ground reference for the VDD33WRPLL power input pin. The VSSWRPLL pin must not be connected to any other signals or ground references external to the ASIC. +1.1V PCIe PHY A Supply Input VDD11PA P +1.1V PCIe PHY A supply input. Provides +1.1V supply to PCIe PHY A. See Note 3-2. +1.1V PCIe PHY B Supply Input VDD11PB P +1.1V PCIe PHY B supply input. Provides +1.1V supply to PCIe PHY B. See Note 3-2. +1.1V PCIe PHY C Supply Input VDD11PC P +1.1V PCIe PHY C supply input. Provides +1.1V supply to PCIe PHY C. See Note 3-2. +3.3V PCIe PHY A Supply Input VDD33PA P +3.3V PCIe PHY A supply input. Provides +3.3V supply to PCIe PHY A. See Note 3-3. +3.3V PCIe PHY B Supply Input VDD33PB P +3.3V PCIe PHY B supply input. Provides +3.3V supply to PCIe PHY B. See Note 3-3. TABLE 3-2: PIN DESCRIPTIONS (CONTINUED) Name Symbol Buffer Type Description

 2025 Microchip Technology Inc. and its subsidiaries DS00006234A-page 26 PCI11414C Note 3-1: C onfiguration strap values are latched on Power-On Reset (POR) and the rising edge of RESET_N (external chip reset). Configuration straps are identified by an underlined symbol name. Signals that function as configuration straps must be augmented with an external resistor when connected to a load. Note 3- 2: All +1.1V power supplies must be powered from a common +1.1V source and cannot be powered separately. Note 3- 3: All +3.3V power supplies must be powered from a common +3.3V source and cannot be powered separately. +3.3V PCIe PHY C Supply Input VDD33PC P +3.3V PCIe PHY C supply input. Provides +3.3V supply to PCIe PHY C. See Note 3-3. +3.3V Ethernet SerDes Supply Input VDD33ENET P +3.3V SGMII+ SerDes supply input. Provides +3.3V supply to the SGMII+ SerDes. See Note 3-3. +1.1V Ethernet SerDes Supply Input VDD11ENET P +1.1V SGMII+ SerDes supply input. Provides +1.1V supply to the SGMII+ SerDes. See Note 3-2. +1.8V to +3.3V Variable Ethernet SerDes Supply Input VDDRGMII P +1.8V to +3.3V variable SGMII+ SerDes supply input. Provides +1.8/2.5/3.3V variable supply to the SGMII+ SerDes. +3.3V PVT Supply Input VDD33PVTREF P +3.3V PVT thermal monitor power supply. See Note 3-3. PVT Ground VSSPVTREF P PVT thermal monitor ground. This is the analog ground reference for the VDD33PVTREF power input pin. The VSSPVTREF pin must not be connected to any other signals or ground references external to the ASIC. +1.1V 25 MHz XTAL Clock Supply Input VDD11XTAL P +1.1V 25 MHz XTAL clock supply input. See Note 3-2. VSSXTAL P 25 MHz XTAL clock ground. Ground VSS P Ground (e-pad). TABLE 3-2: PIN DESCRIPTIONS (CONTINUED) Name Symbol Buffer Type Description

 2025 Microchip Technology Inc. and its subsidiaries DS00006234A-page 27 PCI11414C

3.2 Configuration Straps

Configuration straps are multi-function pins that are used during Power-On Reset (POR) or external chip reset (RESET_N) to determine the default configuration of a particular feature. The state of the signal is latched following de- assertion of the reset. Configuration straps are identified by an underlined symbol name. This section details the various device configuration straps.

3.2.1 EEPROM CONFIGURATION STRAP ( EEPROM_STRAP)

The EEPROM_STRAP configuration strap is used to define whether a device configuration should be read from EEPROM.

3.2.2 SERIAL CONFIGURATION STRAP ( SERIAL_SEL_STRAP)

The SERIAL_SEL_STRAP configuration strap is used to define whether a configuration will be written via a serial inter- face (SMBus or SPI).

3.2.3 SMBUS SCL PULL-UP CONFIGURATION STRAP ( SMBUS_SCL_PU)

The SMBUS_SCL_PU configuration strap is used to define whether an external pull-up on the SCL line is used for nor- mal operation (typically 10 kΩ). When the SERIAL_SEL_STRAP is present, this pull-up is used together with the SMBUS_SDA_PU to determine whether SMBus or SPI has been configured as the serial configuration mechanism.

3.2.4 SMBUS SDA PULL-UP CONFIGURATION STRAP ( SMBUS_SDA_PU)

The SMBUS_SDA_PU configuration strap is used to define whether an external pull-up on the SDA line is used for nor- mal operation (typically 10 kΩ). When the SERIAL_SEL_STRAP is present, this pull-up is used together with the SMBUS_SCL_PU to determine whether SMBus or SPI has been configured as the serial configuration mechanism. Note: The system designer must ensure that configuration straps meet the timing requirements specified in the device data sheet. If configuration straps are not at the correct voltage level prior to being latched, the device may capture incorrect strap values. Note: When enabled, the EEPROM interface must also be enabled via the PROGxx pins. Note: When enabled, the SMBus or SPI interface must be enabled via the PROGxx pins. Note: When both SMBUS_SDA_PU and SMBUS_SCL_PU are present, the SMBus interface must also be enabled via the PROGxx pins. Otherwise, the SPI interface must be enabled via the PROGxx pins. Note: When both SMBUS_SDA_PU and SMBUS_SCL_PU are present, the SMBus interface must also be enabled via the PROGxx pins. Otherwise, the SPI interface must be enabled via the PROGxx pins.

 2025 Microchip Technology Inc. and its subsidiaries DS00006234A-page 28 PCI11414C

3.3 Programmable Function Pins

The PCI11414C provides 64 individually programmable function pins PROGx. Each PROGx pin can be configured in firmware to 15 different functions. When the system is in reset, the pins revert to func0 until the device configuration is completed. Table 3-3 provides a list of default and typical values for each PROGx pin. The programmable function defi- nitions are detailed in Table 3-4.PCI11414C Note: The buffer type of a given programmable function depends on which programmable pin the function has been selected on. The buffer type will be the same as that of the associated PROGx pin, as defined in Table 3-2. TABLE 3-3: PROGRAMMABLE PIN VOLTAGE DOMAIN AND DEFAULT/TYPICAL FUNCTION VALUES Pin Voltage I/O Domain Default Function Typical Application Function PROG0 VDD33 GPIO0 EE_CTLR_SCL PROG1 VDD33 GPIO1 EE_CTLR_SDA PROG2 VDD33 GPIO2 PCIE_CLKREQ1_N PROG3 VDD33 UART0_TXD UART0_TXD PROG4 VDD33 UART0_RXD UART0_RXD PROG5 VDD33 UART1_TXD UART1_TXD PROG6 VDD33 UART1_RXD UART1_RXD PROG7 VDD33 UART2_TXD UART2_TXD PROG8 VDD33 UART2_RXD UART2_RXD PROG9 VDD33 UART3_TXD UART3_TXD PROG10 VDD33 UART3_RXD UART3_RXD PROG17 (Note 3-4) VDDVARIO UART0_RTS_N (Note 3-4) UART0_RTS_N PROG18 (Note 3-4) VDDVARIO UART0_CTS_N (Note 3-4) UART0_CTS_N PROG19 VDDVARIO UART1_RTS_N UART1_RTS_N PROG20 VDDVARIO UART1_CTS_N UART1_CTS_N PROG21 VDDVARIO UART2_RTS_N UART2_RTS_N PROG22 VDDVARIO UART2_CTS_N UART2_CTS_N PROG23 VDDVARIO UART3_RTS_N UART3_RTS_N PROG24 VDDVARIO UART3_CTS_N UART3_CTS_N PROG29 VDDVARIO PCIE_CLKREQ0_N PCIE_CLKREQ0_N PROG30 VDDVARIO PCIE_WAKE_N PCIE_WAKE_N PROG31 VDDVARIO VAUX_DET VAUX_DET PROG32 VDDVARIO GPIO32 SMBUS_CTLR_SCL PROG33 VDDVARIO GPIO33 SMBUS_CTLR_SDA PROG34 VDDVARIO GPIO34 SMBUS_CTLR_ALERT_N PROG46 VDDRGMII ENET_MDC ENET_MDC PROG47 VDDRGMII ENET_MDIO ENET_MDIO PROG48 VDDRGMII ENET_PHY_RESET_N ENET_PHY_RESET_N PROG49 VDDRGMII ENET_DUPLEX ENET_DUPLEX PROG50 VDDRGMII ENET_LINK ENET_LINK PROG51 VDDRGMII ENET_PHY_INT_N ENET_PHY_INT_N

 2025 Microchip Technology Inc. and its subsidiaries DS00006234A-page 29 PCI11414C PROG52 (Note 3-5) VDDRGMII SGMII_RXP/RGMII_RX_CTL/ RMII_CRS_DV (Note 3-5) SGMII_RXP/RGMII_RX_CTL/ RMII_CRS_DV (Note 3-5) PROG53 (Note 3-5) VDDRGMII SGMII_RXM/RGMII_RXC/ RMII_REF_CLK_IN (Note 3-5) SGMII_RXM/RGMII_RXC/ RMII_REF_CLK_IN (Note 3-5) PROG54 (Note 3-5) VDDRGMII SGMII_TXP/RGMII_RXD0/RMII_RXD0 (Note 3-5) SGMII_TXP/RGMII_RXD0/RMII_RXD0 (Note 3-5) PROG55 (Note 3-5) VDDRGMII SGMII_TXM/RGMII_RXD1/RMII_RXD1 (Note 3-5) SGMII_TXM/RGMII_RXD1/RMII_RXD1 (Note 3-5) PROG56 (Note 3-5) VDDRGMII SGMII_CLKM/RGMII_RXD2/ RMII_RX_ER (Note 3-5) SGMII_CLKM/RGMII_RXD2/ RMII_RX_ER (Note 3-5) PROG57 (Note 3-5) VDDRGMII SGMII_CLKP/RGMII_RXD3 (Note 3-5) SGMII_CLKP/RGMII_RXD3 (Note 3-5) PROG58 VDDRGMII RGMII_TXC/RMII_REF_CLK_OUT RGMII_TXC/RMII_REF_CLK_OUT PROG59 VDDRGMII RGMII_TX_CTL/RMII_TX_EN RGMII_TX_CTL/RMII_TX_EN PROG60 VDDRGMII RGMII_TXD0/RMII_TXD0 RGMII_TXD0/RMII_TXD0 PROG61 VDDRGMII RGMII_TXD1/RMII_TXD1 RGMII_TXD1/RMII_TXD1 PROG62 VDDRGMII RGMII_TXD2 RGMII_TXD2 PROG63 VDDRGMII RGMII_TXD3 RGMII_TXD3 PROG64 VDDVARIO GPIO64 SMBUS_TGT_SCL PROG65 VDDVARIO GPIO65 SMBUS_TGT_SDA PROG66 VDDVARIO GPIO66 GPIO66 PROG67 VDDVARIO GPIO67 GPIO67 PROG68 VDDVARIO GPIO68 GPIO68 PROG69 VDDVARIO GPIO69 GPIO69 PROG70 VDDVARIO GPIO70 GPIO70 PROG71 VDDVARIO GPIO71 GPIO71 PROG75 VDD33 GPIO75 GPIO75 PROG76 VDD33 VBUS_DIS_P1 VBUS_DIS_P1 PROG77 VDD33 VCONN1_EN_P1 VCONN1_EN_P1 PROG78 VDD33 VCONN2_EN_P1 VCONN2_EN_P1 PROG79 VDD33 GPIO79 GPIO79 PROG80 VDD33 GPIO80 GPIO80 PROG81 VDD33 VB_PRT_CTL_P1/VB_OCS_P1 VB_PRT_CTL_P1/VB_OCS_P1 PROG82 VDD33 VB_PRT_CTL_P2/VB_OCS_P2 VB_PRT_CTL_P2/VB_OCS_P2 PROG83 VDD33 VB_PRT_CTL_P3/VB_OCS_P3 VB_PRT_CTL_P3/VB_OCS_P3 PROG84 VDD33 VB_PRT_CTL_P4/VB_OCS_P4 VB_PRT_CTL_P4/VB_OCS_P4 PROG85 VDD33 GPIO85 PTP_IO0 PROG86 VDD33 GPIO86 PTP_IO1 PROG87 VDD33 GPIO87 PTP_IO2 TABLE 3-3: PROGRAMMABLE PIN VOLTAGE DOMAIN AND DEFAULT/TYPICAL FUNCTION VALUES (CONTINUED) Pin Voltage I/O Domain Default Function Typical Application Function

 2025 Microchip Technology Inc. and its subsidiaries DS00006234A-page 30 PCI11414C Note 3-4: I n order to use the PVT functions PVT1 and PVT2, shared on the PROG17 and PROG18 pins respectively, GPIO functions must be selected on PROG17 and PROG18 with the GPIOs disabled, which ensures that they are tri-stated. Note 3- 5: Pin can be used as either the Ethernet pin indicated or as an input-only GPIO. Note 3- 6: Pin can be used as either the Ethernet pin indicated or as an input-only GPIO.

 2025 Microchip Technology Inc. and its subsidiaries DS00006234A-page 31 PCI11414C TABLE 3-4: PROGRAMMABLE FUNCTIONS DESCRIPTIONS Programmable Function Description USB Port Control Functions VB_PRT_CTL_P1/ VB_OCS_P1 VBUS Port Control/OCS Port 1 Active high control signal to enable VBUS power to the downstream Port 1: 1: Enable VBUS power and disable VBUS discharge 0: Disable VBUS power and enable VBUS discharge Note: This pin also serves as the overcurrent sense for Port 1. VB_PRT_CTL_P2/ VB_OCS_P2 VBUS Port Control/OCS Port 2 Active high control signal to enable VBUS power to the downstream Port 2: 1: Enable VBUS power and disable VBUS discharge 0: Disable VBUS power and enable VBUS discharge Note: This pin also serves as the overcurrent sense for Port 2. VB_PRT_CTL_P3/ VB_OCS_P3 VBUS Port Control/OCS Port 3 Active high control signal to enable VBUS power to the downstream Port 3: 1: Enable VBUS power and disable VBUS discharge 0: Disable VBUS power and enable VBUS discharge Note: This pin also serves as the overcurrent sense for Port 3. VB_PRT_CTL_P4/ VB_OCS_P4 VBUS Port Control/OCS Port 4 Active high control signal to enable VBUS power to the downstream Port 4: 1: Enable VBUS power and disable VBUS discharge 0: Disable VBUS power and enable VBUS discharge Note: This pin also serves as the overcurrent sense for Port 4. VCONN1_EN_P1 CC1 Port 1 VCONN enable signal to external FET VCONN1_EN_P2 CC1 Port 2 VCONN enable signal to external FET VCONN2_EN_P1 CC2 Port 1 VCONN enable signal to external FET VCONN2_EN_P2 CC2 Port 2 VCONN enable signal to external FET VBUS_DIS_P1 Port 1 VBUS discharge signal to external FET VBUS_DIS_P2 Port 2 VBUS discharge signal to external FET CC_ATTACH_P1 Port 1 USB Type-C CC attach signal output CC_ATTACH_P2 Port 2 USB Type-C CC attach signal output CC_ORIENT_P1 Port 1 USB Type-C orientation signal output CC_ORIENT_P2 Port 2 USB Type-C orientation signal output

 2025 Microchip Technology Inc. and its subsidiaries DS00006234A-page 32 PCI11414C PCIe Functions PCIE_WAKE_N Common PCIe Wake This signal is driven low when the device detects a wakeup. In OBFF mode, OBFF events are signaled using the WAKE# pin as an input. Note: When the device is powered down, these pins are isolated from the PCIe bus and do not present any significant loading or provide any drive. Note: Open drain pin; requires an external pull-up. VAUX_DET Auxiliary voltage detection The VAUX_DET is used to indicate when PME from D3cold is supported. When tied to VSS, PME from D3cold is not supported. The weak pull-down will create a logic low when plugged into a system board that does not support the delivery of the aux- iliary voltage (the auxiliary voltage connection is floating). When the device is powered exclusively from auxiliary voltage, this is tied to the auxiliary voltage (3.3V) to indicate PME from D3cold is supported. When the device is powered from a multiplexed main voltage/auxiliary voltage, this is tied to the auxiliary voltage (3.3V) to indicate PME from D3cold is supported and to mon- itor presence of the auxiliary voltage. Note: This function enables an internal pull-down (PD). If alternate usage of this pin is enabled, the pull-down is disabled and the input value of the pin is overridden to a low value. Because this pin is shared with GPIOs, a series resistor is recommended to prevent an accidental conflict with the auxiliary voltage. This resistor must be low enough in value to override the on-chip pull-down. PCIE_CLKREQ0_N Port 0 PCIe Clock Request input/output Note: When the device is powered down, these pins are isolated from the PCIe bus and do not present any significant loading or provide any drive. Note: Open drain pin; requires an external pull-up. PCIE_CLKREQ1_N Port 1 PCIe Clock Request input/output Note: When the device is powered down, these pins are isolated from the PCIe bus and do not present any significant loading or provide any drive. Note: Open drain pin; requires an external pull-up. Ethernet Functions PTP_IO0 Ethernet Precision Time Protocol I/O 0 Note: Used for PTP input control and output events. Programmable as either a push-pull output, an open-drain output, or a Schmitt-triggered input. PTP_IO1 Ethernet Precision Time Protocol I/O 1 Note: Used for PTP input control and output events. Programmable as either a push-pull output, an open-drain output, or a Schmitt-triggered input. TABLE 3-4: PROGRAMMABLE FUNCTIONS DESCRIPTIONS (CONTINUED) Programmable Function Description

 2025 Microchip Technology Inc. and its subsidiaries DS00006234A-page 33 PCI11414C PTP_IO2 Ethernet Precision Time Protocol I/O 2 Note: Used for PTP input control and output events. Programmable as either a push-pull output, an open-drain output, or a Schmitt-triggered input. PTP_IO3 Ethernet Precision Time Protocol I/O 3 Note: Used for PTP input control and output events. Programmable as either a push-pull output, an open-drain output, or a Schmitt-triggered input. PTP_IO4 Ethernet Precision Time Protocol I/O 4 Note: Used for PTP input control and output events. Programmable as either a push-pull output, an open-drain output, or a Schmitt-triggered input. PTP_IO5 Ethernet Precision Time Protocol I/O 5 Note: Used for PTP input control and output events. Programmable as either a push-pull output, an open-drain output, or a Schmitt-triggered input. PTP_IO6 Ethernet Precision Time Protocol I/O 6 Note: Used for PTP input control and output events. Programmable as either a push-pull output, an open-drain output, or a Schmitt-triggered input. PTP_IO7 Ethernet Precision Time Protocol I/O 7 Note: Used for PTP input control and output events. Programmable as either a push-pull output, an open-drain output, or a Schmitt-triggered input. SPI Peripheral Interface Functions SPI_PERI_CLK SPI Peripheral Clock This is the SPI clock input from the SPI controller. If the SPI interface is enabled, this pin must be driven low during reset. SPI_PERI_DO SPI Peripheral Data Out This is the data out for the SPI port when configured for SPI operation (MISO). SPI_PERI_DI SPI Peripheral Data In This is the SPI data in to the controller from the SPI controller (MOSI). This pin must have a weak pull-down applied at all times to prevent floating if configured for SPI opera- tion. SPI_PERI_CE_N SPI Peripheral Chip Enable This is an active low SPI chip enable input. If the SPI interface is enabled, this pin must be pulled high in power-down states. SPI_PERI_ALERT_N SPI Peripheral Alert SPI Controller Interface 0 Functions SPI_CTRL0_CLK SPI Controller 0 Clock This is the SPI clock output from the SPI controller. If the SPI interface is enabled, this pin must be driven low during reset. TABLE 3-4: PROGRAMMABLE FUNCTIONS DESCRIPTIONS (CONTINUED) Programmable Function Description

 2025 Microchip Technology Inc. and its subsidiaries DS00006234A-page 34 PCI11414C SPI_CTRL0_DO SPI Controller 0 Data Out This is the data out for the SPI port when configured for SPI operation (MOSI). SPI_CTRL0_DI SPI Controller 0 Data In This is the SPI data in to the controller from the SPI controller (MISO). This pin must have a weak pull-down applied at all times to prevent floating if configured for SPI opera- tion. SPI_CTRL0_CE0_N SPI Controller 0 Chip Enable 0 This is an active low SPI chip enable output 0. If the SPI interface is enabled, this pin must be pulled high in power-down states. SPI_CTRL0_CE1_N SPI Controller 0 Chip Enable 1 This is an active low SPI chip enable output 1. If the SPI interface is enabled, this pin must be pulled high in power-down states. SPI_CTRL0_CE2_N SPI Controller 0 Chip Enable 2 This is an active low SPI chip enable output 2. If the SPI interface is enabled, this pin must be pulled high in power-down states. SPI_CTRL0_CE3_N SPI Controller 0 Chip Enable 3 This is an active low SPI chip enable output 3. If the SPI interface is enabled, this pin must be pulled high in power-down states. SPI_CTRL0_CE4_N SPI Controller 0 Chip Enable 4 This is an active low SPI chip enable output 4. If the SPI interface is enabled, this pin must be pulled high in power-down states. SPI_CTRL0_CE5_N SPI Controller 0 Chip Enable 5 This is an active low SPI chip enable output 5. If the SPI interface is enabled, this pin must be pulled high in power-down states. SPI_CTRL0_CE6_N SPI Controller 0 Chip Enable 6 This is an active low SPI chip enable output 6. If the SPI interface is enabled, this pin must be pulled high in power-down states. SPI_CTRL0_ALERT_N SPI Peripheral Alert Active low SPI chip input. This pin enables a Debouncer (DB). SPI Controller Interface 1 Functions SPI_CTRL1_CLK SPI Controller 1 Clock This is the SPI clock output from the SPI controller. If the SPI interface is enabled, this pin must be driven low during reset. TABLE 3-4: PROGRAMMABLE FUNCTIONS DESCRIPTIONS (CONTINUED) Programmable Function Description

 2025 Microchip Technology Inc. and its subsidiaries DS00006234A-page 35 PCI11414C SPI_CTRL1_DO SPI Controller 1 Data Out This is the data out for the SPI port when configured for SPI operation (MOSI). SPI_CTRL1_DI SPI Controller 1 Data In This is the SPI data in to the controller from the SPI controller (MISO). This pin must have a weak pull-down applied at all times to prevent floating if configured for SPI opera- tion. SPI_CTRL1_CE0_N SPI Controller 1 Chip Enable 0 This is an active low SPI chip enable output 0. If the SPI interface is enabled, this pin must be pulled high in power-down states. SPI_CTRL1_CE1_N SPI Controller 1 Chip Enable 1 This is an active low SPI chip enable output 1. If the SPI interface is enabled, this pin must be pulled high in power-down states. SPI_CTRL1_CE2_N SPI Controller 1 Chip Enable 2 This is an active low SPI chip enable output 2. If the SPI interface is enabled, this pin must be pulled high in power-down states. SPI_CTRL1_CE3_N SPI Controller 1 Chip Enable 3 This is an active low SPI chip enable output 3. If the SPI interface is enabled, this pin must be pulled high in power-down states. SPI_CTRL1_CE4_N SPI Controller 1 Chip Enable 4 This is an active low SPI chip enable output 4. If the SPI interface is enabled, this pin must be pulled high in power-down states. SPI_CTRL1_CE5_N SPI Controller 1 Chip Enable 5 This is an active low SPI chip enable output 5. If the SPI interface is enabled, this pin must be pulled high in power-down states. SPI_CTRL1_CE6_N SPI Controller 1 Chip Enable 6 This is an active low SPI chip enable output 6. If the SPI interface is enabled, this pin must be pulled high in power-down states. SPI_CTRL1_ALERT_N SPI Peripheral Alert Active low SPI chip input. This pin enables a Debouncer (DB). SMBus Controller Functions SMBUS_CTLR_SCL SMBus Controller 1 MHz Clock SMBUS_CTLR_SDA SMBus Controller Data This pin enables an internal pull-down (PD). TABLE 3-4: PROGRAMMABLE FUNCTIONS DESCRIPTIONS (CONTINUED) Programmable Function Description

 2025 Microchip Technology Inc. and its subsidiaries DS00006234A-page 36 PCI11414C SMBUS_CTL- R_ALERT_N SMBus Controller Alert This pin enables a Debouncer (DB). SMBus Target Functions SMBUS_TGT_SCL SMBus Target Clock SMBUS_TGT_SDA SMBus Target Data This pin enables an internal pull-down (PD). SMBUS_T- GT_ALERT_N SMBus Target Alert UART0 Functions UART0_TXD UART0 Transmit Data UART0_RXD UART0 Receive Data UART0_RTS_N UART0 Ready To Send UART0_CTS_N UART0 Clear To Send UART0_DTR_N UART0 Data Terminal Ready UART0_DSR_N UART0 Data Set Ready UART0_DCD_N UART0 Data Carrier Detect UART0_RI_N UART0 Ring Indicator UART0_WAKE_N UART0 Wake Out-of-band signaling used to wake up the platform. This signal is open drain, active low, and enables a Debouncer (DB). A pull-up is required on the host side (100 kΩ recom- mended). UART1 Functions UART1_TXD UART1 Transmit Data UART1_RXD UART1 Receive Data UART1_RTS_N UART1 Ready To Send UART1_CTS_N UART1 Clear To Send UART1_DTR_N UART1 Data Terminal Ready UART1_DSR_N UART1 Data Set Ready UART1_DCD_N UART1 Data Carrier Detect UART1_RI_N UART1 Ring Indicator TABLE 3-4: PROGRAMMABLE FUNCTIONS DESCRIPTIONS (CONTINUED) Programmable Function Description

 2025 Microchip Technology Inc. and its subsidiaries DS00006234A-page 37 PCI11414C UART1_WAKE_N UART1 Wake Out-of-band signaling used to wake up the platform. This signal is open drain, active low, and enables a Debouncer (DB). A pull-up is required on the host side (100 kΩ recom- mended). UART2 Functions UART2_TXD UART2 Transmit Data UART2_RXD UART2 Receive Data UART2_RTS_N UART2 Ready To Send UART2_CTS_N UART2 Clear To Send UART2_DTR_N UART2 Data Terminal Ready UART2_DSR_N UART2 Data Set Ready UART2_DCD_N UART2 Data Carrier Detect UART2_RI_N UART2 Ring Indicator UART2_WAKE_N UART2 Wake Out-of-band signaling used to wake up the platform. This signal is open drain, active low, and enables a Debouncer (DB). A pull-up is required on the host side (100 kΩ recom- mended). UART3 Functions UART3_TXD UART3 Transmit Data UART3_RXD UART3 Receive Data UART3_RTS_N UART3 Ready To Send UART3_CTS_N UART3 Clear To Send UART3_DTR_N UART3 Data Terminal Ready UART3_DSR_N UART3 Data Set Ready UART3_DCD_N UART3 Data Carrier Detect UART3_RI_N UART3 Ring Indicator UART3_WAKE_N UART3 Wake Out-of-band signaling used to wake up the platform. This signal is open drain, active low, and enables a Debouncer (DB). A pull-up is required on the host side (100 kΩ recom- mended). EEPROM Interface Functions EE_CTLR_SCL 1 MHz EEPROM SMBus Controller Clock TABLE 3-4: PROGRAMMABLE FUNCTIONS DESCRIPTIONS (CONTINUED) Programmable Function Description

 2025 Microchip Technology Inc. and its subsidiaries DS00006234A-page 38 PCI11414C EE_CTLR_SDA 1 MHz EEPROM SMBus Controller Data This pin enables an internal pull-down (PD). General Purpose Input/Output (GPIO) Functions GPIO[0:10] General Purpose Input/Output pins 0-10 GPIO[17:24] General Purpose Input/Output pins 17-24 GPIO[29:34] General Purpose Input/Output pins 29-34 GPIO[46:71] General Purpose Input/Output pins 46-71 GPIO[75:87] General Purpose Input/Output pins 75-87 TABLE 3-4: PROGRAMMABLE FUNCTIONS DESCRIPTIONS (CONTINUED) Programmable Function Description

 2025 Microchip Technology Inc. and its subsidiaries DS00006234A-page 39 PCI11414C

3.4 Debouncers

Some pins have associated Debouncers (indicated by a DB buffer type) which can be enabled or disabled as needed. The pins may be connected to pushbuttons that require debouncing, or they may be connected to digital outputs from other chips which are perfectly clean (and may even be signaling something at a very high rate higher than the minimum period resolution of the debounce timer). Via static (or even dynamic software driven) configuration, the system designer can decide whether a Debouncer is needed and the associated timer value. When the Debouncer is disabled, the raw input is used as the pin input. When the Debouncer is enabled, it will start to debounce if there is a change in the value on the pin. The debounce will continue for the specified period of debounce time. Once the debounce is complete, the signal is passed through (see Figure 3-2). If the pin value changes within the debounce time, then the debouncing is restarted for the new input value. This behav- ior is shown in Figure 3-3. FIGURE 3-2: DEBOUNCED RAW PIN INPUT FIGURE 3-3: DEBOUNCER RESTART Raw Input Signal De-bounced Signal De-bounce time Raw Input Signal De-bounced Signal De-bounce Period 1 (not completed) De-bo uncer restarts here De-bouncer Starts here De-bounce period2 (Completed)

 2025 Microchip Technology Inc. and its subsidiaries DS00006234A-page 40 PCI11414C

4.0 OPERATIONAL CHARACTERISTICS

4.1 Absolute Maximum Ratings*

+3.3V Supply Voltage (VDD33, VDD33A0, VDD33PA, VDD33PB, VDD33PC, VDD33A1, VDD33WRPLL, +1.1V Supply Voltage (VDD11, VDD11ATX0, VDD11ARX0, VDD11ATX1, VDD11ARX1, VDD11PA, VDD11PB, Note 4- 1: When powering this device from laboratory or system power supplies, it is important that the absolute maximum ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on their outputs when AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output. If this possibility exists, it is suggested to use a clamp circuit. *Stresses exceeding those listed in this section could cause permanent damage to the device. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at any condition exceeding those indicated in Section 4.2, "Operating Conditions**" or any other applicable section of this specification is not implied.

4.2 Operating Conditions**

+3.3V Supply Voltage (VDD33, VDD33A0, VDD33PA, VDD33PB, VDD33PC, VDD33A1, VDD33WRPLL, +1.1V Supply Voltage (VDD11, VDD11ATX0, VDD11ARX0, VDD11ATX1, VDD11ARX1, VDD11PA, VDD11PB, Note 4- 2: (0°C to +70°C) for commercial version, (-40°C to +85°C) for industrial version, or (-40°C to +85°C) for Automotive Grade 3 version. **Proper operation of the device is guaranteed only within the ranges specified in this section. Note: Do not drive input signals without power supplied to the device.

 2025 Microchip Technology Inc. and its subsidiaries DS00006234A-page 41 PCI11414C

4.3 Power Consumption

Note 4-3: An alog input/output as defined in the Universal Serial Bus Revision 3.2/2.0 Specifications or USB Type-C Specification. TABLE 4-1: DEVICE POWER CONSUMPTION Typical Current (mA) +1.1V Supplies +3.3 Supplies Reset Current 187.2 15.48 Sleep Current 329 42.8 Idle 704 110 USB Active Current

1 SSP 1040 125

1 SSP + 1 HS 1055 135

2 SSP 1195 135

2 SSP + 1 HS 1200 140

2 SSP + 2 HS 1237 148

1 SS 987 124

1 SS + 1 HS 1004 132

2 SS + 1 HS 1086 135

1 HS 810 125

4 HS 825 146

RGMII @ 1000 Mbps link 421 87 SGMII @ 2500 Mbps link 480 78 Peripheral Active Current

4 UART channel with max baud rate (4 Mbps) 334 56

2 SPI Controller with 30 MHz speed 174 35

1 I2C Controller with 1 MHz speed 174 35

4 lane UFP + 1 lane DFP at 8GT/s 746 116 Maximum Current USB 2SSP+2HS, SGMII @ 2500 Mbps, 4 UART channel,

2 SPI Controller, 1 I2C Controller, 1 PCIe DFP at 8GT/s

Note: All active power data is based the maximum UFP lane width (see PCIe Active Current above). Note: End system integrators should ensure their power design meets the power consumption requirements for their individual systems maximal use-case by taking power measurements during development. Note: In the USB Active Current sections of Table 4-1, the various port configurations are indicated via the fol- lowing acronyms: HS = Hi-Speed FS = Full-Speed SS = Super-Speed (5 Gbps) SSP = Super-Speed Plus (10 Gbps)

 2025 Microchip Technology Inc. and its subsidiaries DS00006234A-page 42 PCI11414C

4.4 AC Specifications

This section details the various AC timing specifications of the device.

4.4.1 POWER SEQUENCE TIMING

Power supplies must adhere to the following rules:

All power supplies of the same voltage must be powered up/down together.
There is no power-up sequencing requirement. However all power supplies must reach operational levels within the time periods specified in Table 4-2.
There is no power-down sequencing or timing requirement, however the device must not be powered for an extended period of time without all supplies at operational levels.
Following initial power-on, or if a power supply brownout occurs (i.e., one or more supplies drops below opera- tional limits), a power-on reset must be executed once all power supplies reach operational levels.
Do not drive input signals without power supplied to the device.

4.4.2 PCIE TIMING

All device PCIe signals (PCIE_xx) conform to the voltage, power, and timing characteristics/specifications as set forth in the PCI Express Base Specification Revision 3.1a. Please refer to the PCI Express Base Specification Revision 3.1a for additional information.

4.4.3 USB TIMING

4.4.3.1 USB 2.0 All device USB 2.0 signals (USB2_xx pins) conform to the voltage, power, and timing characteristics/specifications as set forth in the Universal Serial Bus Revision 2.0 Specification. Please refer to the Universal Serial Bus Revision 2.0 Specification for additional information. 4.4.3.2 USB 3.2 All device USB 3.2 signals (USB3_xx pins) conform to the voltage, power, and timing characteristics/specifications as set forth in the Universal Serial Bus Revision 3.2 Specification. Please refer to the Universal Serial Bus Revision 3.2 Specification for additional information.

4.4.3.3 USB Type-C

All device USB Type-C signals (CC1_xx/CC2_xx pins) conform to the voltage, power, and timing characteristics/speci- fications as set forth in the USB Type-C Cable and Connector Specification Revision 2.1. Please refer to the USB Type- C Cable and Connector Specification Revision 2.1 for additional information. Note: Violation of these specifications may damage the device. FIGURE 4-1: POWER SEQUENCE TIMING TABLE 4-2: POWER SEQUENCE TIMING Symbol Description Min Typ Max Unit tpon Power supply turn-on time 0 — 5 ms All Power Supply Pins tpon

 2025 Microchip Technology Inc. and its subsidiaries DS00006234A-page 43 PCI11414C

4.4.4 SMBUS TIMING

All device SMBus signals (SMBUS_xx) conform to the voltage, power, and timing characteristics/specifications as set forth in the System Management Bus Specification Revision 2.0. Please refer to the System Management Bus Specifi- cation, Version 2.0 for additional information. Additionally, when operating at 1 MHz, the SMBus signals confirm to the timing characteristics/specifications as set forth in the System Management Bus Specification Revision 3.0. Please refer to the System Management Bus Specification, Version 3.0 for additional information.

4.4.5 UART TIMING

All device UART signals (UART_xx) conform to the timing characteristics/specifications as set forth in the RS-232, RS-422 and RS-485 specifications. Please refer to the RS-232, RS-422 and RS-485 specifications for additional infor- mation.

4.4.6 SPI CONTROLLER TIMING

This section specifies the SPI controller (SPI_CTRL[0:1]_xx) timing requirements for the device. The SPI controllers support operation at 30, 20, 15, 12, 10 or 2 MHz. Note 4- 4: 30, 20, 15, 12, 10 or 2 MHz, depending on the mode of operation. FIGURE 4-2: SPI CONTROLLER TIMING TABLE 4-3: SPI CONTROLLER TIMING Symbol Description Min Typ Max Unit tfc Clock frequency — — Note 4-4 MHz tceh Chip enable (SPI_CTRL[0:1]_CE[0:6]_N) high time 100 — — ns tclq Clock to input data — — 13 ns tdh Input data hold time 0 — — ns tos Output setup time 5 — — ns toh Output hold time 5 — — ns tov Clock to output valid 4 — — ns tcel Chip enable (SPI_CTRL[0:1]_CE[0:6]_N) low to first clock 12 — — ns tceh Last clock to chip enable (SPI_CTRL[0:1]_CE[0:6]_N) high 12 — — ns SPI_CTRL[0:1]_CLK SPI_CTRL[0:1]_DI SPI_CTRL[0:1]_DO SPI_CTRL[0:1]_CE[0:6]_N tcel tfc Output data valid tclq tceh tdh tohtos tov toh Output data valid Input data valid tceh

 2025 Microchip Technology Inc. and its subsidiaries DS00006234A-page 44 PCI11414C

4.5 Clock Specifications

The device can accept either a 25 MHz crystal or a 25 MHz single-ended clock oscillator input. If the single-ended clock oscillator method is implemented, XTALO should be left unconnected and XTALI/CLK_IN should be driven with a nominal 0-3.3V clock signal. The input clock duty cycle is 40% minimum, 50% typical and 60% maximum. It is recommended that a crystal utilizing matching parallel load capacitors be used for the crystal input/output signals (XTALI/XTALO). The following circuit design (Figure 4-3) is required to ensure proper operation.

4.5.1 EXTERNAL REFERENCE CLOCK ( CLK_IN)

When using an external reference clock, the following clock characteristics are required:

25 MHz
50% duty cycle ±10%, 25 MHz ±300 ppm
Jitter < 100 ps pk-pk

4.5.1.1 TX Ref Clocks

It has a built in, trimmable 100Ω termination, but does not include any common-mode VCM generation, so it's suitable for DC-coupling. In the case of AC-coupling you will have to add resistors on the board to set the proper VCM outside of the chip. This receiver can operate with the VCM ranging from 0.2V to (VDDHV-0.2V), with at least 100 mVpp of input swing, regardless of AC vs DC coupling. There is no maximum swing specification, but the pins should not exceed the VDDDHV level by more than 300 mV, to avoid leakage through ESD up diodes. If the host/clock generator output is in HCSL format, then the clock does not need any LVDS conversion or common mode biasing using a resistor; you can directly connect the HCSL clock source to the REFCLK pin. This LVDS RX does not have a build in hysteresis. FIGURE 4-3: 25 MHZ CRYSTAL CIRCUIT PCI11414C XTALO XTALI C1 C2

 2025 Microchip Technology Inc. and its subsidiaries DS00006234A-page 45 PCI11414C

5.0 PACKAGE INFORMATION

5.1 Package Marking Information

Standard device marking consists of Microchip part number, year code, week code and traceability code. For device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. Legend: i Temperature range designator (Blank = Commercial, i = Industrial/Automotive Grade 3) V Automotive designator (Blank = Commercial/Industrial, V = Automotive) R Product revision nnn Internal code e3 Pb-free JEDEC ® designator for Matte Tin (Sn) YY Year code (last two digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 164-VQFN-DR (13x13 mm) PIN 1 PCI11414CiVRnnn e3YYWWNNN

 2025 Microchip Technology Inc. and its subsidiaries DS00006234A-page 46 PCI11414C

5.2 Package Drawings

FIGURE 5-1: 164-VQFN-DR PACKAGE (DRAWING) B A 0.10 C 0.20 C

0.10 C A B

0.05 C C TOP VIEW SIDE VIEW BOTTOM VIEW 0.10 C 0.08 C Sheet 1 of 2 164X Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 164-Lead Very Thin Plastic Quad Flat, No Lead Package (PMX) - 13x13x0.9 mm Body [VQFN]; Dual Row, Punch Singulated © 2023 Microchip Technology Inc. Microchip Technology Drawing C04-527 Rev E SEATING PLANE (DATUM A) (DATUM B) NOTE 1 NOTE 1 D EE1 0.20 C 0.10 C (A3) A 164X b L L eR eR 4X CH 4X CH 123 122 103 164 124 163 144 (K) ș e e

 2025 Microchip Technology Inc. and its subsidiaries DS00006234A-page 47 PCI11414C FIGURE 5-2: 164-VQFN-DR PACKAGE (DIMENSIONS) For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: © 2023 Microchip Technology Inc. REF: Reference Dimension, usually without tolerance, for information purposes only. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Pin 1 visual index feature may vary, but must be located within the hatched area. Package is punch singulated Dimensioning and tolerancing per ASME Y14.5M Sheet 2 of 2 Number of Terminals Overall Height Terminal Width Overall Width Terminal Length Exposed Pad Width Terminal Thickness Pitch Standoff Units Dimension Limits A b e L E N

0.50 BSC

0.152 REF

0.30 0.18 0.00 0.22 0.40 0.02

13.00 BSC

0.50 0.30 0.90 0.05 MAX K 1.45 REFTerminal-to-Exposed-Pad Overall Length Exposed Pad Length D D2 7.90 8.00 8.10 CH – 0.70 0.75 E1 12.75 BSC Molded Package Length D1 12.75 BSC Package Corner Chamfer – – 0.60 A2Molded Package Height 7.90 8.00 8.10 Molded Package Width șMold Draft Angle Terminal Row Spacing eR 0.65 BSC 164-Lead Very Thin Plastic Quad Flat, No Lead Package (PMX) - 13x13x0.9 mm Body [VQFN]; Dual Row, Punch Singulated Microchip Technology Drawing C04-527 Rev E –5° 15°

 2025 Microchip Technology Inc. and its subsidiaries DS00006234A-page 48 PCI11414C FIGURE 5-3: 164-VQFN-DR PACKAGE (LAND PATTERN) RECOMMENDED LAND PATTERN Dimension Limits Units Center Pad Width Outer Row Contact Pad Spacing Center Pad Length Contact Pitch 8.10 8.10 MILLIMETERS E MAX 12.96 Outer Contact Pad Length (X80) Outer Contact Pad Width (X80) 0.78 0.30 NOM C1Outer Row Contact Pad Spacing 12.96 Contact Pad to Contact Pad G2 0.20 Thermal Via Diameter V Thermal Via Pitch EV 0.33 1.20 BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Dimensioning and tolerancing per ASME Y14.5M For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: © 2023 Microchip Technology Inc. Contact Pad to Center Pad G1 1.35 Microchip Technology Drawing C04-2527 Rev E EV EV E ØV Inner Row Contact Pad Spacing Inner Row Contact Pad Spacing Outer Contact Pad to Inner Contact Pad G3 0.20 I84er Contact Pad Length (X84) I84er Contact Pad Width (X84) 0.48 0.30 11.32 11.32 123 122 124 164 125 163 164-Lead Very Thin Plastic Quad Flat, No Lead Package (PMX) - 13x13x0.9 mm Body [VQFN]; Dual Row, Punch Singulated SILK SCREEN (R0.05) E

 2025 Microchip Technology Inc. and its subsidiaries DS00006234A-page 49 PCI11414C APPENDIX A: PRODUCT BRIEF REVISION HISTORY TABLE A-1: REVISION HISTORY Revision Level & Date Section/Figure/Entry Correction DS00006234A (11-11-25) All Preliminary release.

 2025 Microchip Technology Inc. and its subsidiaries DS00006234A-page 50 PCI11414C PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Pin 1 orientation is in quadrant 1, as detailed in the direction of unreeling diagram below. Device: PCI11414C= PCIe Switch with USB Host, Ethernet MAC, I/O Tape and Reel Option: Blank = Standard packaging (tray) T = Tape and Reel ( Note 1) Temperature Range: Blank = 0 C to +70 C (Commercial) I = -40 C to +85 C (Industrial/Automotive Grade 3) Package: PMX = 164-pin VQFN-DR Automotive Code: Vxx = 3 character code with “V” prefix, specifying automotive product. Examples: a) PCI11414C/PMX Tray, 0C to +70C (Commercial), 164-pin VQFN-DR b) PCI11414CT/PMX Tape & reel, 0C to +70C (Commercial), 164-pin VQFN-DR c) PCI11414C-I/PMX Tray, -40C to +85C (Industrial), 164-pin VQFN-DR d) PCI11414CT-I/PMX Tape & reel, -40C to +85C (Industrial), 164-pin VQFN-DR e) PCI11414C-I/PMXVAO Tray, -40C to +85C (Automotive Grade 3), 164-pin VQFN-DR f) PCI11414CT-I/PMXVAO Tape & reel, -40C to +85C (Automotive Grade 3), 164-pin VQFN-DR Note 1: Tape and Reel identifier only appears in the catalog part number description. This identi- fier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. PART NO. Device Tape and Reel Option Temperature Range XXXX X- Package XXX Automotive Code

 2025 Microchip Technology Inc. and its subsidiaries DS00006234A-page 51 PCI11414C THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site con- tains the following information:

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Product Information

PCI11414C specifications and overview.

Summary

PCIe Switch with Integrated USB 3.2 Gen 2 Host Controller 11-11-25

Description

PCIe Switch with Integrated USB 3.2 Gen 2 Host Controller 11-11-25

Source title PCI11414C Datasheet(PDF) - Microchip Technology

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