PCI1131

PCI1131 TI | Alldatasheet

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PCI-TO-CARDBUS CONTROLLER UNIT XCPS011 – DECEMBER 1997 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C00683.3-V Core Logic With Universal PCI Interface Compatible With 3.3-V or 5-V PCI Signaling Environments /C0068Supports PCI Local Bus Specification 2.1 /C0068Mix-and-Match 3.3-V/5-V PC Card16 Cards and 3.3-V CardBus Cards /C0068Supports Two PC Card or CardBus Slots With Hot Insertion and Removal /C00681995 PC Card-Standard Compliant /C0068Low-Power Advanced Submicron CMOS Technology /C0068Uses Serial Interface to Texas Instruments (TI ) TPS2206 Dual Power Switch /C0068System Interrupts Can Be Programmed as PCI-Style or ISA IRQ-Style Interrupts /C0068ISA IRQ Interrupts Can Be Serialized Onto a Single IRQSER Pin /C0068Programmable Output Select for CLKRUN /C0068Supports Burst Transfers to Maximize Data Throughput on the PCI and CardBus Bus /C0068Multifunction PCI Device With Separate Configuration Spaces for Each Socket /C0068Five PCI Memory Windows and Two I/O Windows Available to Each PC Card16 Socket /C0068Two I/O Windows and Two Memory Windows Available to Each CardBus Socket /C0068CardBus Memory Windows Can Be Individually Selected Prefetchable or Nonprefetchable /C0068Exchangeable Card Architecture (ExCA)-Compatible Registers Mapped in Memory or I/O Space /C0068TI Extension Registers Mapped in the PCI Configuration Space /C0068Intel 82365SL-DF Register Compatible /C0068Supports 16-Bit Distributed Direct Memory Access (DMA) on Both PC Card Sockets /C0068Supports PC/PCI DMA on Both PC Card Sockets /C0068Supports Zoom Video Mode /C0068Supports Ring Indicate /C0068Packaged in 208-Pin Thin Plastic Quad Flatpack Recommended Operating Conditions for PC Cards A and B 16. Table of Contents Copyright  1997, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Intel and MPIIX are trademarks of Intel Corporation. PC Card is a trademark of Personal Computer Memory Card International Association (PCMCIA). TI is a trademark of Texas Instruments Incorporated.

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description

The TI PCI1131 is a high-performance PCI-to-PC Card controller that supports two independent PC Card sockets compliant with the 1995 PC Card standard. The PCI1131 provides a set of features that makes it ideal for bridging between PCI and PC Cards in both notebook and desktop computers. The 1995 PC Card standard retains the 16-bit PC Card specification defined in PCMCIA release 2.1 and defines the new 32-bit PC Card, called CardBus, capable of full 32-bit data transfers at 33 MHz. The PCI1131 supports any combination of 16-bit and CardBus PC Cards in its two sockets, powered at 3.3 V or 5 V, as required. The PCI1131 is compliant with the PCI local bus specification revision 2.1, and its PCI interface can act as either a PCI master device or a PCI slave device. The PCI bus mastering is initiated during 16-bit PC Card DMA transfers or CardBus PC Card bus-mastering cycles. All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI1131 is register compatible with the Intel 82365SL-DF ExCA controller. The PCI1131 internal datapath logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent 32-bit write buffers allow fast-posted writes to improve system-bus utilization. An advanced CMOS process is used to achieve low system-power consumption while operating at PCI clock rates up to 33 MHz. Several low-power modes allow the host power-management system to further reduce power consumption. All unused PCI1131 inputs should be pulled high through a 43-kW resistor.

PCI-TO-CARDBUS CONTROLLER UNIT XCPS011 – DECEMBER 1997 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 system block diagram A simplified system block diagram using the PCI1131 is provided below. The PCI950 IRQ deseralizer and the PCI930 zoomed video (ZV) switch are optional functions that can be used when the system requires that capability. The PCI interface includes all address/data and control signals for PCI protocol. The 68-pin PC Card interface includes all address/data and control signals for CardBus and 16-bit (R2) protocols. When zoomed video (ZV) is enabled (in 16-bit PC Card mode) 23 of the 68 signals are redefined to support the ZV protocol. The interrupt interface includes terminals for parallel PCI, parallel ISA, and serialized PCI and ISA signaling. Other miscellaneous system interface terminals are available on the PCI1131 that include: /C0068Multifunction IRQ terminals /C0068SUSPEND , RI_OUT (power management control signals) /C0068SPKROUT. PCI Bus PCI1131 PCI950 IRQSER Deserializer IRQSER Interrupt Controller INTA INTB IRQ2–15 PCI930 ZV Switch23 PC Card Socket A TPS22xx Power Switch 3 PC Card Socket B External ZV Port VGA Controller Audio Sub-System Zoom Video Zoom Video 68 68 NOTE: The PC Card interface is 68 pins for CardBus and 16-bit PC Cards. In zoomed-video mode 23 pins are used for routing the zoomed video signals too the VGA controller.

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terminal assignments – PCI-to-PC Card (16 bit) CC C/BE2 A_D1 A_D7 B_IOWR B_D12 B_D11 B_CD1 GND AD9 AD8 C/BE0 AD7 AD6 AD5 GND B_D6 B_D7 B_D15 B_D3 B_D4 GND B_D5 B_A10 B_CE2 B_OE B_A11 B_A9 B_A17 B_A8 B_A19 B_A13 B_A14 B_A20 B_A16 B_A15 B_A23 B_A12 B_D14 B_IORD B_A18 B_WE B_A21 B_A22 IRQ7/PCDMAREQ IRQ10/CLKRUN IRQ11/PCDMAGNT IRQ9/IRQSER IRQ12/CLKRUN PCLK RSTIN GND AD30 AD28 AD31 AD26 AD27 AD25 AD24 C/BE3 IDSEL AD23 AD22 AD21 AD20 AD18 AD16 GND AD19 TRDY DEVSEL STOP PAR AD15 AD13 AD12 A_A9 A_A8 A_A17 A_IOWR A_A11 A_IORD A_CE2 A_A10 A_CE1 A_D15 A_D14 GND A_D6 A_D13 A_D5 A_D12 A_D4 A_D3 B_D10 B_D2 B_D1 B_D8 B_D0 B_BVD1(STSCHG/RI) B_CD2 B_WP(IOIS16) B_BVD2(SPKR) B_WAIT B_READY(IREQ) B_VS1 B_A3 B_A4 B_REG GND B_A6 158 157 160 159 162 161 164 163 166 165 168 167 170 169 172 171 174 173 176 175 178 177 180 179 182 181 184 183 186 185 188 187 190 189 192 191 194 193 196 195 198 197 200 199 202 201 204 203 206 205 208 207 103 104 101 102 100 A_OE B_D9 51 106 105 108 107 110 109 112 111 114 113 116 115 118 117 120 119 122 121 124 123 126 125 128 127 130 129 132 131 134 133 136 135 138 137 140 139 142 141 144 143 146 145 148 147 150 149 152 151 154 153 156

155 IRQ4/INTB

A_D10 A_D9 A_D2 A_D8 A_CD2 A_D0 A_BVD2(SPKR) A_BVD1(STSCHG/RI) A_WP(IOIS16) A_WAIT A_VS1 A_READY(IREQ) A_A4 A_A2 GND A_REG A_A25 A_A6 A_RESET A_A7 A_A12 A_A5 A_A15 A_A23 A_A16 A_A22 A_WE A_A21 AD29 AD17 FRAME IRDY C/BE1 AD14 Card A Card B PCI1131 CorePCI VCCB V CC V V CC VCCP VCC V CC A_VS2 A_INPACK AD4 A_A20 AD3 AD2 AD1 AD0 B_CE1 B_RESET B_A5 B_INPACK A_D11 A_A24 A_A3 A_A1 A_A0 GND IRQ14 VCC IRQ15/RI_OUT VCCP GNT REQ PERR SERR V CC A_CD1 B_A0 B_A1 B_A2 VCC GND AD10 AD11 DATA CLOCK LATCH VCCA VCC A_A14 A_A19 A_A13 A_A18 B_VS2 B_A25 B_A7 B_A24 GND V CC B_D13 PDV PACKAGE (TOP VIEW)

PCI-TO-CARDBUS CONTROLLER UNIT XCPS011 – DECEMBER 1997 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 terminal assignments – PCI-to-CardBus Card V CC CC C/BE2 A_CAD29 A_CAD7 B_CCD1 GND AD9 AD8 C/BE0 AD7 AD6 AD5 GND GND B_CAD16 B_CBLOCK B_CPAR B_CPERR B_CSTOP B_CCLK B_CIRDY B_CFRAME B_CC/BE2 B_RSVD B_CGNT B_CDEVSEL B_CTRDY IRQ7/PCDMAREQ IRQ10/CLKRUN IRQ11/PCDMAGNT IRQ9/IRQSER IRQ12/CLKRUN PCLK RSTIN GND AD30 AD28 AD31 AD26 AD27 AD25 AD24 C/BE3 IDSEL AD23 AD22 AD21 AD20 AD18 AD16 GND AD19 TRDY DEVSEL STOP PAR AD15 AD13 AD12 A_CAD14 A_CC/BE1 A_CAD16 A_CAD15 A_CAD12 A_CAD13 A_CAD10 A_CAD9 A_CAD8 A_RSVD GND A_CAD5 A_CAD6 A_CAD3 A_CAD4 A_CAD1 A_CAD0 B_CAD31 B_RSVD B_CAD29 B_CAD28 B_CAD27 B_CSTSCHG B_CCLKRUN B_CAUDIO B_CSERR B_CINT B_CVS1 B_CAD23 B_CAD22 B_CC/BE3 GND B_CAD20 158 157 160 159 162 161 164 163 166 165 168 167 170 169 172 171 174 173 176 175 178 177 180 179 182 181 184 183 186 185 188 187 190 189 192 191 194 193 196 195 198 197 200 199 202 201 204 203 206 205 208 207 103 104 101 102 100 A_CAD11 B_CAD30 51 106 105 108 107 110 109 112 111 114 113 116 115 118 117 120 119 122 121 124 123 126 125 128 127 130 129 132 131 134 133 136 135 138 137 140 139 142 141 144 143 146 145 148 147 150 149 152 151 154 153 156 A_CAD31 A_CAD30 A_RSVD A_CAD28 A_CCD2 A_CAD27 A_CAUDIO A_CSTSCHG A_CCLKRUN A_CSERR A_CVS1 A_CINT A_CAD22 A_CAD24 GND A_CC/BE3 A_CAD19 A_CAD20 A_CRST A_CAD18 A_CAD21 A_CIRDY A_CFRAME A_CCLK A_CTRDY A_CGNT A_CDEVSEL AD29 AD17 FRAME IRDY C/BE1 AD14 Card A Card B PCI1131 CorePCI VCCB V CC V CC VCCP VCC V CC A_CVS2 A_CREQ AD4 A_CSTOP AD3 AD2 AD1 AD0 B_CRST B_CAD21 B_CREQ A_CAD2 A_CAD17 A_CAD23 A_CAD25 A_CAD26 GND IRQ14 VCC IRQ15/RI_OUT VCCP GNT REQ PERR SERR V CC A_CCD1 B_CAD26 B_CAD25 B_CAD24 VCC GND AD10 AD11 DATA CLOCK LATCH VCCA VCC A_CPERR A_CBLOCK A_CPAR A_RSVD B_CVS2 B_CAD19 B_CAD18 B_CAD17 GND V A_CC/BE2 A_CC/BE0 B_CCD2 B_CC/BE1 B_CAD14 B_CAD15 B_CAD12 B_CAD13 B_CAD11 B_CC/BE0 B_CAD10 B_CAD9 B_CAD8 B_CAD7 B_RSVD B_CAD5 B_CAD6 B_CAD3 B_CAD1 B_CAD2 B_CAD4 B_CAD0 PDV PACKAGE (TOP VIEW)

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NAME NO. TYPE FUNCTION PCLK 165 I PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled at the rising edge of PCLK. RSTIN 166 I PCI reset. When the RSTIN signal is asserted low, the PCI1131 forces all output buffers to the high-impedance state and resets all internal registers. When asserted, the PCI1131 is nonfunctional. After RSTIN is deasserted, the PCI1131 returns to the default state. When the PCI1131 SUSPEND mode is enabled, the device is protected from any RSTIN reset (i.e., the PCI1131 internal register contents are preserved). PCI address and data TERMINAL I/O FUNCTION NAME NO. TYPE FUNCTION AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 170 171 173 174 176 177 178 179 183 184 185 186 188 189 190 191 204 205 206 208 I/O Address/data bus. AD31–AD0 are the multiplexed PCI address and data bus. During the address phase of a PCI cycle, AD31–AD0 contain a 32-bit address or other destination information. During the data phase, AD31–AD0 contain data. C/BE3 C/BE2 C/BE1 C/BE0 180 192 203 I/O Bus commands and byte enables. C/BE3–C/BE0 are multiplexed on the same PCI terminals. During the address phase, C/BE3–C/BE0 define the bus command. During the data phase, C/BE3–C/BE0 are used as byte enables. The byte enables determine which byte lanes carry meaningful data. C/BE0 applies to byte 0 (AD7–AD0), C/BE1 applies to byte 1 (AD15–AD8), C/BE2 applies to byte 2 (AD23–AD16), and C/BE3 applies to byte 3 (AD31–AD24). PAR 202 I/O Parity. As a PCI target during PCI read cycles, or as PCI bus master during PCI write cycles, the PCI1131 calculates even parity across the AD and C/BE buses and outputs the results on PAR, delayed by one clock.

PCI-TO-CARDBUS CONTROLLER UNIT XCPS011 – DECEMBER 1997 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) PCI interface control TERMINAL I/O FUNCTION NAME NO. TYPE FUNCTION DEVSEL 197 I/O Device select. As a PCI target, the PCI1131 asserts DEVSEL to claim the current cycle. As a PCI master, the PCI1131 monitors DEVSEL until a target responds or a time-out occurs. FRAME 193 I/O Cycle frame. FRAME is driven by the current master to indicate the beginning and duration of an access, FRAME is low (asserted) to indicate that a bus transaction is beginning. While FRAME is asserted, data transfers continue. When FRAME is sampled high (deasserted), the transaction is in the final data phase. GNT 168 I Grant. GNT is driven by the PCI arbiter to grant the PCI1131 access to the PCI bus after the current data transaction is complete. IDSEL 182 I Initialization device select. IDSEL selects the PCI1131 during configuration accesses. IDSEL can be connected to one of the upper 24 PCI address lines. IRDY 195 I/O Initiator ready. IRDY indicates the bus master’s ability to complete the current data phase of the transaction. IRDY is used with TRDY. A data phase is completed on any clock where both IRDY and TRDY are sampled low (asserted). During a write, IRDY indicates that valid data is present on AD31–AD0. During a read, IRDY indicates that the master is prepared to accept data. Wait cycles are inserted until both IRDY and TRDY are low (asserted) at the same time. This signal is an output when the PCI1131 is the PCI bus master and an input when the PCI bus is the target. IRQ10/CLKRUN IRQ12/CLKRUN 159 161 I/O Interrupt request 10 and 12. IRQ10/CLKRUN and IRQ12/CLKRUN are software configurable and used by the PCI1131 to support the PCI clock run protocol. When configured as CLKRUN by setting bit 0 in the system control register offset 80h, this terminal is an open-drain output. To select between IRQ10 and IRQ12 as the output, use bit 7 of register 80h. PERR 199 I/O Parity error. PERR is driven by the PCI target during a write to indicate that a data parity error has been detected. REQ 169 O Request. REQ is asserted by the PCI1131 to request access to the PCI bus as a master. SERR 200 O System error. SERR pulsed from the PCI1131 indicates an address parity error has occurred. STOP 198 I/O Stop. STOP is driven by the current PCI target to request the master to stop the current transaction. TRDY 196 I/O Target ready. TRDY indicates the ability of the PCI1131 to complete the current data phase of the transaction. TRDY is used with IRDY. A data phase is completed on any clock where both TRDY and IRDY are sampled asserted. During a read, TRDY indicates that valid data is present on AD31–AD0. During a write, TRDY indicates that the PCI1131 is prepared to accept data. Wait cycles are inserted until both IRDY and TRDY are asserted together. This signal is an output when the PCI1131 is the PCI target and an input when the PCI1131 is the PCI bus master. power supply TERMINAL FUNCTION NAME NO. FUNCTION GND 13, 22, 44, 75, 96, 129, 153, 167, 181, 194, 207Device ground terminals VCC 7, 31, 64, 86, 113, 143, 164, 175, 187, 201Power supply terminal for core logic (3.3 V) VCCA 120 Power supply terminal for PC Card A (5 V or 3.3 V) VCCB 38 Power supply terminal for PC Card B (5 V or 3.3 V) VCCP 148, 172 Power supply terminal for PCI interface (5 V or 3.3 V)

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Terminal Functions (Continued) PC Card power switch TERMINAL I/O FUNCTION NAME NO. TYPE FUNCTION CLOCK 151 O Power switch clock. Information on the DATA line is sampled at the rising edge of CLOCK. The frequency of the clock is derived from dividing PCICLK by 36. The maximum frequency of CLOCK is 2 MHz. DATA 152 O Power switch data. DATA is used by the PCI1131 to serially communicate socket power control information. LATCH 150 O Power switch latch. LATCH is asserted by the PCI1131 to indicate to the PC Card power switch that the data on the DATA line is valid. interrupt TERMINAL I/O FUNCTION NAME NO. TYPE FUNCTION IRQ3/INTA IRQ4/INTB 154 155 O Interrupt request 3 and interrupt request 4. IRQ3/INTA–IRQ4/INTB can be connected to either PCI or ISA interrupts. IRQ3/INTA–IRQ4/INTB are software configurable as IRQ3 or INTA and as IRQ4 or INTB. When configured for IRQ3 and IRQ4, IRQ3/INTA–IRQ4/INTB must be connected to the ISA IRQ programmable interrupt controller. When IRQ3/INTA–IRQ4/INTB are configured for INTA and INTB, IRQ3/INTA–IRQ4/INTB must be connected to interrupts on the PCI bus. IRQ7/PCDMAREQ 157 O Interrupt request 7. IRQ7/PCDMAREQ is software configurable and is used by the PCI1131 to request PC/PCI DMA transfers from chipsets that support the PC/PCI DMA scheme. When IRQ7/PCDMAREQ is configured for PC/PCI DMA request (IRQ7), it must be connected to the appropriate request (REQ) pin on the Intel Mobile Triton PCI I/O accelerator (MPIIX ). IRQ9/IRQSER 158 O I/O Interrupt request 9/serial IRQ. IRQ9/IRQSER is software configurable and indicates an interrupt request from a PC Card to the PCI1131. When IRQ9/IRQSER is configured for IRQ9, it must be connected to the system programmable interrupt controller. IRQSER allows all IRQ signals to be serialized onto one pin. IRQ9/IRQSER is configured via bits 2–1 in the device control register of the TI extension registers. IRQ10/CLKRUN IRQ12/CLKRUN 159 161 I/O Interrupt request 10 and 12. IRQ10/CLKRUN and IRQ12/CLKRUN are software configurable and used by the PCI1131 to support the PCI clock run protocol. When configured as CLKRUN by setting bit 0 in the system control register offset 80h, this terminal is an open-drain output. To select between IRQ10 and IRQ12 as the output, use bit 7 of register 80h. IRQ11/PCDMAGNT 160 I/O Interrupt request 11. IRQ11/PCDMAGNT is software configurable and is used by the PCI1131 to accept a grant for PC/PCI DMA transfers from chipsets that support the PC/PCI DMA scheme. When IRQ11/PCDMAGNT is configured for PC/PCI DMA grant (IRQ11), it must be connected to the appropriate grant (GNT) pin on the Intel MPIIX controller. IRQ5 IRQ14 156 162 O Interrupt request 5 and 14. These signals are ISA interrupts. These terminals indicate an interrupt request from one of the PC Cards. The interrupt mode is selected in the device control register of the TI extension registers. IRQ15/RI_OUT 163 I/O Interrupt request 15. IRQ15/RI_OUT indicates an interrupt request from one of the PC Cards. RI_OUT allows the RI input from the 16-bit PC Card to be output to the system. IRQ15/RI_OUT is configured in the card control register of the TI extension registers. speaker control TERMINAL I/O FUNCTION NAME NO. TYPE FUNCTION SPKROUT/ SUSPEND 149 O Speaker. SPKROUT carries the digital audio signal from the PC Card. SUSPEND places the PCI1131 in suspend mode. SPKROUT/SUSPEND is configured in the card control register of the TI extension registers.

PCI-TO-CARDBUS CONTROLLER UNIT XCPS011 – DECEMBER 1997 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) 16-bit PC Card address and data (slots A and B) TERMINAL NUMBER I/O FUNCTION NAME SLOT A † SLOT B ‡ TYPE FUNCTION A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 121 118 116 114 111 109 107 105 103 112 115 108 106 117 100 102 104 119 123 125 126 128 131 132 133 O PC Card address. 16-bit PC Card address lines. A25 is the most-significant bit. D15 D14 D13 D12 D11 D10 147 145 142 146 144 141 I/O PC Card data. 16-bit PC Card data lines. D15 is the most-significant bit. † Terminal name is preceded with A_. For example, the full name for terminal 121 is A_A25. ‡ Terminal name is preceded with B_. For example, the full name for terminal 55 is B_A25.

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Terminal Functions (Continued) 16-bit PC Card interface control signals (slots A and B) TERMINAL NUMBER I/O FUNCTION NAME SLOT A † SLOT B ‡ TYPE FUNCTION BVD1 (STSCHG /RI) 138 72 I Battery voltage detect 1. Generated by 16-bit memory PC Cards that include batteries. BVD1 is used with BVD2 as an indication of the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are kept high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and needs to be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost. Status change. STSCHG is used to alert the system to a change in the READY, write protect, or battery voltage dead condition of a 16-bit I/O PC Card. Ring indicate. RI is used by 16-bit modem cards to indicate ring detection. BVD2(SPKR ) 137 71 I Battery voltage detect 2. Generated by 16-bit memory PC Cards that include batteries. BVD2 is used with BVD1 as an indication of the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and needs to be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost. Speaker. SPKR is an optional binary audio signal available only when the card and socket have been configured for the 16-bit I/O interface. The audio signals from cards A and B can be combined by the PCI1131 and output on SPKROUT. DMA request. BVD2 can be used as the DMA request signal during DMA operations to a 16-bit PC Card that supports DMA. If used, the PC Card asserts BVD2 to request a DMA operation. CD1 CD2 140 I PC Card detect 1 and PC Card detect 2. CD1 and CD2 are internally connected to ground on the PC Card. When a PC Card is inserted into a socket, CD1 and CD2 are pulled low. CE1 CE2 O Card enable 1 and card enable 2. CE1 and CE2 enable even- and odd-numbered address bytes. CE1 enables even-numbered address bytes, and CE2 enables odd-numbered address bytes. INPACK 127 61 I Input acknowledge. INPACK is asserted by the PC Card when it can respond to an I/O read cycle at the current address. DMA request. INPACK can be used as the DMA request signal during DMA operations to a 16-bit PC Card that supports DMA. If used, the PC Card asserts INPACK to indicate a request for a DMA operation. IORD 99 33 O I/O read. IORD is asserted by the PCI1131 to enable 16-bit I/O PC Card data output during host I/O read cycles. DMA write. IORD is used as the DMA write strobe during DMA operations from a 16-bit PC Card that supports DMA. The PCI1131 asserts IORD during DMA transfers from the PC Card to host memory. IOWR 101 35 O I/O write. IOWR is driven low by the PCI1131 to strobe write data into 16-bit I/O PC Cards during host I/O write cycles. DMA read. IOWR is used as the DMA read strobe during DMA operations to a 16-bit PC Card that supports DMA. The PCI1131 asserts IOWR during DMA transfers from host memory to the PC Card. OE 98 32 O Output enable. OE is driven low by the PCI1131 to enable 16-bit memory PC Card data output during host memory read cycles. DMA terminal count. OE is used as terminal count (TC) during DMA operations to a 16-bit PC Card that supports DMA. The PCI1131 asserts OE to indicate TC for a DMA write operation. † Terminal name is preceded with A_. For example, the full name for terminal 138 is A_BVD1. ‡ Terminal name is preceded with B_. For example, the full name for terminal 72 is B_BVD1.

PCI-TO-CARDBUS CONTROLLER UNIT XCPS011 – DECEMBER 1997 11POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) 16-bit PC Card interface control signals (slots A and B) (continued) TERMINAL NUMBER I/O FUNCTION NAME SLOT A † SLOT B ‡ TYPE FUNCTION READY(IREQ ) 135 69 I Ready. The ready function is provided by READY when the 16-bit PC Card and the host socket are configured for the memory-only interface. READY is driven low by the 16-bit memory PC Cards to indicate that the memory card circuits are busy processing a previous write command. READY is driven high when the 16-bit memory PC Card is ready to accept a new data transfer command. Interrupt request. IREQ is asserted by a 16-bit I/O PC Card to indicate to the host that a device on the 16-bit I/O PC Card requires service by the host software. IREQ is high (deasserted) when no interrupt is requested. REG 130 63 O Attribute memory select. REG remains high for all common memory accesses. When REG is asserted, access is limited to attribute memory (OE or WE active) and to the I/O space (IORD or IOWR active). Attribute memory is a separately accessed section of card memory and is generally used to record card capacity and other configuration and attribute information. DMA acknowledge. REG is used as a DMA acknowledge (DACK) during DMA operations to a 16-bit PC Card that supports DMA. The PCI1131 asserts REG to indicate a DMA operation. REG is used with the DMA read (IOWR) or DMA write (IORD) strobes to transfer data. RESET 124 58 O PC Card reset. RESET forces a hard reset to a 16-bit PC Card. WAIT 136 70 I Bus cycle wait. WAIT is driven by a 16-bit PC Card to delay the completion of (i.e., extend) the memory or I/O cycle in progress. WE 110 46 O Write enable. WE is used to strobe memory write data into 16-bit memory PC Cards. WE also is used for memory PC Cards that employ programmable memory technologies. DMA terminal count. WE is used as TC during DMA operations to a 16-bit PC Card that supports DMA. The PCI1131 asserts WE to indicate TC for a DMA read operation. WP(IOIS16) 139 73 I Write protect. This signal applies to 16-bit memory PC Cards. WP reflects the status of the write-protect switch on 16-bit memory PC Cards. For 16-bit I/O cards, WP is used for the 16-bit port (IOIS16 ) function. The status of WP can be read from the ExCA interface status register. I/O is 16 bits. WP applies to 16-bit I/O PC Cards. IOIS16 is asserted by the 16-bit PC Card when the address on the bus corresponds to an address to which the 16-bit PC Card responds, and the I/O port that is addressed is capable of 16-bit accesses. DMA request. WP can be used as the DMA request signal during DMA operations to a 16-bit PC Card that supports DMA. If used, the PC Card asserts WP to request a DMA operation. VS1 VS2 134 122 I/O Voltage sense 1 and voltage sense 2. VS1 and VS2, when used together, determine the operating voltage of the 16-bit PC Card. † Terminal name is preceded with A_. For example, the full name for terminal 98 is A_OE. ‡ Terminal name is preceded with B_. For example, the full name for terminal 32 is B_OE.

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Terminal Functions (Continued) CardBus PC Card address and data signals (slots A and B) TERMINAL NUMBER I/O FUNCTION NAME SLOT A † SLOT B ‡ TYPE FUNCTION CAD31 CAD30 CAD29 CAD28 CAD27 CAD26 CAD25 CAD24 CAD23 CAD22 CAD21 CAD20 CAD19 CAD18 CAD17 CAD16 CAD15 CAD14 CAD13 CAD12 CAD11 CAD10 CAD9 CAD8 CAD7 CAD6 CAD5 CAD4 CAD3 CAD2 CAD1 CAD0 147 145 144 142 141 133 132 131 128 126 125 123 121 119 118 103 101 102 100 I/O CardBus PC Card address and data. CAD31–CAD0 are multiplexed address and data signals. A bus transaction consists of an address phase followed by one or more data phases. The PCI1131 supports both read and write bursts. The address phase is the clock cycle in which CFRAME is asserted. During the address phase, CAD31-CAD0 contain a physical address (32 bits). For I/O, this is a byte address; for configuration and memory, it is a DWORD address. During data phases, CAD7–CAD0 contain the least-significant byte and CAD31–CAD24 contain the most-significant byte. Write data is stable and valid when CIRDY is asserted. Read data is stable and valid when CTRDY is asserted. Data is transferred during those clocks when CIRDY and CTRDY are asserted. CC/BE0 CC/BE1 CC/BE2 CC/BE3 104 117 130 I/O CardBus PC Card command and byte enables. CC/BE0–CC/BE3 are multiplexed on the same pin. During the address phase of the transaction, CC/BE3–CC/BE0 define the bus command. During the data phase transaction, CC/BE3–CC/BE0 are used as byte enables. Byte enables are valid during the entire data phase and determine the byte lanes that carry the data. CC/BE0 applies to byte 0, CC/BE1 applies to byte 1, CC/BE2 applies to byte 2, and CC/BE3 applies to byte 3. CPAR 106 41 I/O CardBus PC Card parity. Even parity across CAD31–CAD0 and CC/BE3–CC/BE0 is calculated and driven by this signal. CPAR is stable and valid for one clock after the address phase. For data phases, CPAR is stable and valid one clock after either CIRDY is asserted on a write transaction or CTRDY is asserted on a read transaction. Once CPAR is valid, it remains valid for one clock after the completion of the current data phase. NOTE: CPAR has the same timing as CAD31–CAD0 but delays by one clock. When the PCI1131 is acting as an initiator, it drives CPAR for address and write data phases; and when acting as a target, the PCI1131 drives CPAR for read data phases. † Terminal name is preceded with A_. For example, the full name for terminal 147 is A_CAD31. ‡ Terminal name is preceded with B_. For example, the full name for terminal 81 is B_CAD31.

PCI-TO-CARDBUS CONTROLLER UNIT XCPS011 – DECEMBER 1997 13POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) CardBus PC Card interface system signals (slots A and B) TERMINAL NUMBER I/O FUNCTION NAME SLOT A † SLOT B ‡ TYPE FUNCTION CCLK 112 48 O CardBus PC Card clock. CCLK provides synchronous timing for all transactions on the CardBus PC Card interface. All signals except CRST (upon assertion) CCLKRUN, CINT, CSTSCHG, CAUDIO, CCD 2–CCD 1, and CVS2–CVS1 are sampled on the rising edge of the clock, and all timing parameters are defined with the rising edge of CCLK. The CardBus clock operates at 33 MHz but can be stopped in the low state. CCLKRUN 139 73 I/O CardBus PC Card clock run. CCLKRUN is used by a CardBus PC Card to request an increase in the CCLK frequency. It is used by the PCI1131 to indicate that the CCLK frequency is decreased. CRST 124 58 O CardBus PC Card reset. CRST is used to bring CardBus PC Card specific registers, sequencers, and signals to a consistent state. When CRST is asserted, all CardBus PC Card signals must be driven to the high-impedance state. Assertion can be asynchronous to CCLK, but deassertion must be synchronous to CCLK. CardBus PC Card interface control signals (slots A and B) TERMINAL NUMBER I/O FUNCTION NAME SLOT A † SLOT B ‡ TYPE FUNCTION CAUDIO 137 71 I CardBus audio. CAUDIO is an optional digital output signal from a PC Card to the system speaker. CardBus cards support two types of audio: single amplitude, binary waveform and/or pulsewidth modulation (PWM) encoded signal. The PCI1131 supports the binary audio mode and can output a binary audio signal from the PC Card to SPKROUT. CBLOCK 107 42 I/O CardBus lock. CBLOCK is an optional signal used to lock a particular address, ensuring a bus initiator exclusive access. This signal is not supported on the PCI1131. CCD1 82 16 I CardBus detect 1 and CardBus detect 2. CCD1 and CCD2 are used with CVS1 and CVS2 to CCD2 140 74 I determine the type and voltage of the CardBus PC Card. CDEVSEL 111 47 I/O CardBus device select. When actively driven, CDEVSEL indicates that the PCI1131 has decoded its address as the target of the current access. As an input, CDEVSEL indicates whether any device on the bus has been selected. CFRAME 116 51 I/O CardBus cycle frame. CFRAME is driven by the PCI1131 or a CardBus card when it is acting as an initiator to indicate the beginning and duration of a transaction. CFRAME is asserted to indicate a bus transaction is beginning, and while it is asserted, data transfer is continuous. When CFRAME is high (deasserted), the transaction is in its final data phase. CGNT 110 46 O CardBus grant. CGNT is driven by the PCI1131 to grant a CardBus PC Card access to the CardBus bus after the current data transaction is complete. CINT 135 69 I CardBus interrupt. CINT is asserted low by a CardBus PC Card to request interrupt servicing from the host. † Terminal name is preceded with A_. For example, the full name for terminal 112 is A_CCLK. ‡ Terminal name is preceded with B_. For example, the full name for terminal 48 is B_CCLK.

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Terminal Functions (Continued) CardBus PC Card interface control signals (slots A and B) (continued) TERMINAL NUMBER I/O FUNCTION NAME SLOT A † SLOT B ‡ TYPE FUNCTION CIRDY 115 50 I/O CardBus initiator ready. CIRDY indicates that the PCI1131 is initiating the ability of the bus initiator to complete a current data phase of the transaction. It is used with CTRDY. When both CIRDY and CTRDY are sampled asserted, a data phase is completed on any clock. During a write, CIRDY indicates that valid data is present on CAD31–CAD0. During a read, CIRDY indicates the PCI1131, as an initiator, is prepared to accept the data. Wait cycles are inserted until CIRDY and CTRDY are both low (asserted). CPERR 108 43 I/O CardBus parity error. CPERR reports errors during all CardBus PC Card transactions except during special cycles. CPERR is sustained in the high-impedance state and must be driven active by the agent receiving data, two clocks following the data, when a data parity error is detected. CPERR must be driven active for a minimum duration of one clock for each data phase. CPERR must be driven high for one clock before it is returned to the high-impedance state. An agent cannot report a CPERR until it claims the access by asserting CDEVSEL and completes a data phase. CREQ 127 61 I CardBus request. CREQ indicates to the arbiter that the CardBus PC Card requires use of the CardBus bus. CSERR 136 70 I CardBus system error. CSERR reports address parity error, data errors on the special cycle command, or any other system error such that the CardBus card can no longer operate correctly. CSERR is open drain and is actively driven for a single CardBus PC Card clock by the agent reporting the error. The assertion of CSERR is synchronous to the clock and meets the setup and hold times of all bused signals. Restoring CSERR to the deasserted state is accomplished by a weak pullup provided by the system designer. This pullup can take two to three clock periods to fully restore CSERR . The PCI1131 reports CSERR to the operating system any time it is sampled low (asserted). CSTOP 109 45 I/O CardBus stop. CSTOP indicates the current target is requesting the initiator to stop the current transaction. CSTSCHG 138 72 I CardBus status change. CSTSCHG is used to alert the system to a change in the READY, WP, or BVD condition of the I/O CardBus PC Card. CTRDY 114 49 I/O CardBus target ready. CTRDY indicates that the PCI1131, as a selected target, can complete a current data phase of the transaction. CTRDY is used with CIRDY. When both of these signals are sampled asserted, a data phase is completed on any clock. During a read, CTRDY indicates that valid data is present on CAD31–CAD0. During a write, CIRDY indicates the PCI1131, as a target, is prepared to accept the data. Wait cycles are inserted until CIRDY and CTRDY are both low (asserted). CVS1 134 68 I/O CardBus voltage sense 1 and voltage sense 2. CVS1 and CVS2, together with CCD1 and CCD2, CVS2 122 56 I/O gg , g , determine the operating voltage of the CardBus PC Card. † Terminal name is preceded with A_. For example, the full name for terminal 115 is A_CIRDY. ‡ Terminal name is preceded with B_. For example, the full name for terminal 50 is B_CIRDY.

PCI-TO-CARDBUS CONTROLLER UNIT XCPS011 – DECEMBER 1997 15POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 absolute maximum ratings over operating temperature ranges (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Applies to external input and bidirectional buffers. VI > VCC does not apply to fail-safe terminals. 2. Applies to external output and bidirectional buffers. VO > VCC does not apply to fail-safe terminals. recommended operating conditions MIN NOM MAX UNIT tt Input transition (rise and fall) time CMOS compatible 0 25 ns TA Operating ambient temperature Commercial 0 25 70 °C TJ‡ Virtual junction temperature Commercial 0 25 115 °C ‡ These junction temperatures reflect simulation conditions. The customer is responsible for verifying junction temperature. recommended operating conditions for PCI interface OPERATION MIN NOM MAX UNIT VCC Core voltage Commercial 3.3 V 3 3.3 3.6 V VCCP PCI supply voltage Commercial 3.3 V 3 3.3 3.6 VVCCP PCI supply voltage Commercial 5 V 4.75 5 5.25 V VI Input voltage

3.3 V 0 VCCP VVI Input voltage

5 V 0 VCCP

V V § Output voltage

3.3 V 0 VCCP VVO § O utput voltage 5 V 0 VCCP

V ¶ CMOS com patible 3.3 V 0.5 VCCP VIH¶ High-level input voltage CMOS compatible

5 V 2 VIH gg

Fail safe# 3.3 V 0.5 VCC ¶ CMOS compatible 3.3 V 0.3 VCCP VIL¶ Low-level input voltage CMOS compatible 5 V 0.8 V Fail safe# 3.3 V 0.3 VCC § Applies to external output buffers ¶ Applies to external input and bidirectional buffers without hysteresis # Fail-safe pins are 16, 56, 68, 72, 74, 82, 122, 134, 138, 140, 149, and 152.

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recommended operating conditions for PC Cards A and B and miscellaneous inputs and outputs OPERATION MIN NOM MAX UNIT VCC(A/B) PC Card supply voltage Commercial 3.3 V 3 3.3 3.6 VVCC(A/B) PC C ard supply voltage Commercial 5 V 4.75 5 5.25 V VI Input voltage

3.3 V 0 VCC(A/B) VVI In ut voltage

5 V 0 VCC(A/B)

V VO † Output voltage

3.3 V 0 VCC(A/B) VVO † Out ut voltage

V CMOS compatible 3.3 V 0.475 VCC(A/B)¶ VIH‡ High-level input voltage 5 V 2.4 V Fail safe§ 3.3 V 0.475 VCC(A/B)¶ CMOS compatible 3.3 V 0.325 VCC(A/B)¶ VIL‡ Low-level input voltage 5 V 0.8 V Fail safe§ 3.3 V 0.325 VCC(A/B)¶ † Applies to external output buffers ‡ Applies to external input and bidirectional buffers without hysteresis § Fail-safe pins are 16, 56, 68, 72, 74, 82, 122, 134, 138, 140, 149, and 152. ¶ Meets TTL levels, VIH MIN =1.65 V and VIL MAX = 0.99 V

PCI-TO-CARDBUS CONTROLLER UNIT XCPS011 – DECEMBER 1997 17POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER SIDE TEST CONDITIONS OPERATION MIN MAX UNIT PCI IOH = –0.5 mA 3.3 V 0.9 VCC PCI IOH = –2 mA 5 V 2.4 VOH High-level output voltage† PC Card IOH = –0.15 mA 3.3 V 0.9 VCC V PC C ard IOH = –0.15 mA 5 V 2.4 Miscellaneous‡ IOH = –4 mA 2.1 PCI IOL = 1.5 mA 3.3 V 0.1 VCCPCI IOL = 6 mA 5 V 0.55 VOL Low level output voltage PC Card IOL = 0.7 mA 3.3 V 0.1 VCC VVOL Low-level output voltage PC C ard IOL = 0.7 mA 5 V 0.55 V Miscellaneous‡ IOL = 4 mA 0.5 SERR IOL = 12 mA 0.5 Inputpins VI = VCC ¶ 3.6 V 10 Input pins VI = VCC ¶ 5.25 V 20 IIH High le el inp t c rrent§ I/O pins# VI = VCC ¶ 3.6 V 10 mAIIH High-level input current§ I/O pins# VI = VCC ¶ 5.25 V 25 mA Fail safe VI = VCC ¶ 3.6 V 10 DATA VI = VCCP 290 IIL Low level input current§ Input pins VI = GND –1 mAIIL Low-level input current§ I/O pins VI = GND –10 mA † VOH is not tested on SERR (pin 200) due to open-drain output. ‡ Miscellaneous pins are 150, 151, 156, 157, 159, 160, 161, 162, 163. § IIL is not tested on DATA (pin 152) due to internal pulldown resistor, and IIH is not tested on SPKROUT (pin 149) due to internal pullup resistor. ¶ For PCI and miscellaneous pins, VCC = VCCP . For card A/B, VCC = VCCA /VCCB , respectively. # For I/O pins, the input leakage current includes the off-state output current IOZ .

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PCI clock/reset timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Figure 2 and Figure 3) ALTERNATE SYMBOL MIN MAX UNIT tc Cycle time, PCLK tcyc 30 ∞ ns twH Pulse duration, PCLK high thigh 11 ns twL Pulse duration, PCLK low tlow 11 ns Dv/Dt Slew rate, PCLK tr, tf 1 4 V/ns tw Pulse duration, RSTIN trst 1 ms tsu Setup time, PCLK active at end of RSTIN trst-clk 100 /C0109s PCI timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Note 3, Figure 1, and Figure 4) TEST CONDITIONS ALTERNATE SYMBOL MIN MAX UNIT t d Propagation delay time PCLK to shared signal valid delay time C L = 50 pF, See Note 4 tval 11 nstpd Propagation delay time PCLK to shared signal invalid delay time C L = 50 pF, See Note 4 tinv 2 ns ten Enable time, high-impedance-to-active delay time from PCLK ton 2 ns tdis Disable time, active-to-high-impedance delay time from PCLK toff 28 ns tsu Setup time before PCLK valid tsu 7 ns th Hold time after PCLK high th 0 ns NOTES: 3. This data sheet uses the following conventions to describe time (t) intervals. The format is: tA, where subscript A indicates the type of dynamic parameter being represented. One of the following is used: tpd = propagation delay time, td = delay time, tsu = setup time, and th = hold time. 4. PCI shared signals are AD31–AD0, C/BE3–C/BE0, FRAME , TRDY, IRDY, STOP, IDSEL, DEVSEL, and PAR.

† C LOAD includes the typical load-circuit distributed capacitance. following characteristics: PRR = 1 MHz, ZO = 50 W , tr ≤ 6 ns, tf ≤ 6 ns. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. For tPLZ and tPHZ , VOL and VOH are measured values. Figure 1. Load Circuit and Voltage Waveforms

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2 V MIN Peak to Peak

Figure 2. PCLK Timing Waveform Figure 3. RSTIN Timing Waveforms Figure 4. Shared-Signals Timing Waveforms

the Intel 82365SL-DF values. This ensures compatibility with existing software and maximizes throughput. cycles and nanoseconds for I/O and memory cycles. Table 1. PC Card Address Setup Time, t Table 2. PC Card Command Active Time, tc(A), 8-Bit PCI Cycles

01 X 23/690

11 X 23/690

Table 3. PC Card Command Active Time, tc(A), 16-Bit PCI Cycles

01 X 13/390

11 X 23/630

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Table 4. PC Card Address Hold Time, th(A), 8-Bit and 16-Bit PCI Cycles observed if programmed for zero wait state, 16-bit cycles) with a 33-MHz PCI clock.

Figure 5. PC Card Memory Cycle

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Figure 6. PC Card I/O Cycle Figure 7. Miscellaneous PC Card Delay Times

PCI-TO-CARDBUS CONTROLLER UNIT XCPS011 – DECEMBER 1997 25POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA PDV (S-PQFP-G208) PLASTIC QUAD FLATPACK 0,13 NOM 105 104 0,27 0,17 0,25 0,45 0,75 0,05 MIN Seating Plane 4087729/B 06/96 157 208 156 SQ SQ 28,05 29,90 30,10 27,95 25,50 TYP 1,60 MAX 0,08 0,50 M0,08 0°–7° Gage Plane 1,35 1,45 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MO-136

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