PCI1031

PCI1031 TI | Alldatasheet

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PCI-TO-PC CARD16 CONTROLLER UNIT SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C00683.3-V Core Logic With Universal PCI Interface Compatible and 3.3-V or 5-V PCI Signaling Environments /C0068Supports PCI Local Bus Specification 2.1 /C0068Mix-and-Match 5-V/3.3-V PC Card16 Cards /C0068Supports Two PC Card Slots With Hot Insertion and Removal /C00681995 PC Card Standard Compliant /C0068Low-Power Advanced Submicron CMOS Technology /C0068Uses Serial Interface to Texas Instruments (TI ) TPS2206 Dual Power Switch /C0068System Interrupts Can Be Programmed as PCI-Style or ISA IRQ-Style Interrupts /C0068ISA IRQ Interrupts Can Be Serialized Onto a Single IRQSER Pin /C0068Independent Read and Write Buffers for Each Direction /C0068Multifunction PCI Device With Separate Configuration Spaces for Each Socket /C0068Five PCI Memory Windows and Two I/O Windows Available to Each PC Card16 Socket /C0068Exchangeable Card Architecture (ExCA )-Compatible Registers Are Mapped in Memory and I/O Space /C0068TI Extension Registers Are Mapped in the PCI Configuration Space /C0068Intel 82365SL-DF Register Compatible /C0068Supports 16-Bit Distributed Direct Memory Access (DMA) on Both PC Card Sockets /C0068Supports PC/PCI DMA on Both PC Card Sockets /C0068Supports Zoom Video Mode /C0068Supports Ring Indicate /C0068Packaged in a 208-Pin Thin Plastic Quad Flatpack Recommended Operating Conditions for PC Cards A and B 90. . . . Table of Contents Copyright  1997, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Intel and MPIIX are trademarks of Intel Corp. PC Card is a trademark of Personal Computer Memory Card International Association (PCMCIA). TI is a trademark of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

PCI-TO-PC CARD16 CONTROLLER UNIT SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

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description

The TI PCI1031 is a high-performance PCI-to-PC Card16 controller that supports two independent PC Card sockets compliant with the1995 PC Card standard. The PCI1031 provides a set of features that makes it ideal for bridging between PCI and PC Cards in both notebook and desktop computers. The 1995 PC Card standard retains the 16-bit PC Card specification defined in PCMCIA release 2.1 and is capable of full 16-bit data transfers at 33 MHz. The PCI1031 supports any combination of 16-bit and PC Cards in its two sockets, powered at 3.3 V or 5 V, as required. The PCI1031 is compliant with the PCI local bus specification revision 2.1, and its PCI interface can act as either a PCI master device or a PCI slave device. The PCI bus mastering is initiated during 16-bit PC Card DMA transfers. All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI1031 is register compatible with the Intel 82365SL-DF PC Card interface controller. The PCI1031 internal datapath logic allows the host to access 8- and 16-bit cards using full 32-bit PCI cycles for maximum performance. Independent 32-bit write buffers allow fast-posted writes to improve system-bus utilization. An advanced CMOS process is used to achieve low system-power consumption while operating at PCI clock rates up to 33 MHz. Low-power modes allow the host power-management system to further reduce power consumption. All unused PCI1031 pins should be pulled high by a 43-kW resistor.

PCI-TO-PC CARD16 CONTROLLER UNIT SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 system block diagram – 16-bit PC Card interface A simplified system block diagram using the PCI1031 is provided below. The PCI950 IRQ deseralizer and the PCI930 zoomed video (ZV) switch are optional functions that can be used when the system requires that capability. The PCI interface includes all address/data and control signals for PCI protocol. The 68-pin PC Card interface includes all address/data and control signals for 16-bit (R2) protocols. When zoomed video (ZV) is enabled (in 16-bit PC Card mode) 23 of the 68 signals are redefined to support the ZV protocol. The interrupt interface includes terminals for parallel PCI, parallel ISA, and serialized PCI and ISA signaling. Other miscellaneous system interface terminals are available on the PCI1031 that include: /C0068Multifunction IRQ terminals /C0068SUSPEND , RI_OUT (power management control signals) /C0068SPKROUT. PCI Bus PCI1031 PCI950 IRQSER Deserializer IRQSER Interrupt Controller INTA INTB IRQ2–15 PCI930 ZV Switch23 PC Card Socket A TPS22xx Power Switch 3 PC Card Socket B External ZV Port VGA Controller Audio Sub-System Zoom Video Zoom Video 68 68 NOTE: The PC Card interface is 68 pins for CardBus and 16-bit PC Cards. In zoomed-video mode 23 pins are used for routing the zoomed video signals too the VGA controller.

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terminal assignments – PCI-to-PC Card (16 bit) CC C/BE2 A_D1 A_D7 B_IOWR B_D12 B_D11 B_CD1 GND AD9 AD8 C/BE0 AD7 AD6 AD5 GND B_D6 B_D7 B_D15 B_D3 B_D4 GND B_D5 B_A10 B_CE2 B_OE B_A11 B_A9 B_A17 B_A8 B_A19 B_A13 B_A14 B_A20 B_A16 B_A15 B_A23 B_A12 B_D14 B_IORD B_A18 B_WE B_A21 B_A22 IRQ7/PCDMAREQ IRQ10/CLKRUN IRQ11/PCDMAGNT IRQ9/IRQSER IRQ12 PCLK RSTIN GND AD30 AD28 AD31 AD26 AD27 AD25 AD24 C/BE3 IDSEL AD23 AD22 AD21 AD20 AD18 AD16 GND AD19 TRDY DEVSEL STOP PAR AD15 AD13 AD12 A_A9 A_A8 A_A17 A_IOWR A_A11 A_IORD A_CE2 A_A10 A_CE1 A_D15 A_D14 GND A_D6 A_D13 A_D5 A_D12 A_D4 A_D3 B_D10 B_D2 B_D1 B_D8 B_D0 B_BVD1(STSCHG/RI) B_CD2 B_WP(IOIS16) B_BVD2(SPKR) B_WAIT B_READY(IREQ) B_VS1 B_A3 B_A4 B_REG GND B_A6 158 157 160 159 162 161 164 163 166 165 168 167 170 169 172 171 174 173 176 175 178 177 180 179 182 181 184 183 186 185 188 187 190 189 192 191 194 193 196 195 198 197 200 199 202 201 204 203 206 205 208 207 103 104 101 102 100 A_OE B_D9 51 106 105 108 107 110 109 112 111 114 113 116 115 118 117 120 119 122 121 124 123 126 125 128 127 130 129 132 131 134 133 136 135 138 137 140 139 142 141 144 143 146 145 148 147 150 149 152 151 154 153 156

155 IRQ4/INTB

A_D10 A_D9 A_D2 A_D8 A_CD2 A_D0 A_BVD2(SPKR) A_BVD1(STSCHG/RI) A_WP(IOIS16) A_WAIT A_VS1 A_READY(IREQ) A_A4 A_A2 GND A_REG A_A25 A_A6 A_RESET A_A7 A_A12 A_A5 A_A15 A_A23 A_A16 A_A22 A_WE A_A21 AD29 AD17 FRAME IRDY C/BE1 AD14 Card A Card B PCI1031 CorePCI VCCB V CC V VCC VCCP VCC VCC A_VS2 A_INPACK AD4 A_A20 AD3 AD2 AD1 AD0 B_CE1 B_RESET B_A5 B_INPACK A_D11 A_A24 A_A3 A_A1 A_A0 GND IRQ14 V CC IRQ15/RI_OUT VCCP GNT REQ PERR SERR V CC A_CD1 B_A0 B_A1 B_A2 VCC GND AD10 AD11 DATA CLOCK LATCH VCCA VCC A_A14 A_A19 A_A13 A_A18 B_VS2 B_A25 B_A7 B_A24 GND V CC B_D13 PDV PACKAGE (TOP VIEW)

Table 1. Signal Names Sorted Alphabetically – 16-Bit PC Card SIGNAL NAME NO. SIGNAL NAME NO. SIGNAL NAME NO. SIGNAL NAME NO.

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Table 2. Signal Names Sorted by Terminal Number – 16-Bit PC Card

PCI-TO-PC CARD16 CONTROLLER UNIT SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions PCI system TERMINAL I/O FUNCTION NAME NO. TYPE FUNCTION PCLK 165 I PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled at the rising edge of PCLK. RSTIN 166 I PCI reset. When the RSTIN signal is asserted low, the PCI1031 forces all output buffers to the high-impedance state and resets all internal registers. When asserted, the PCI1031 is nonfunctional. After RSTIN is deasserted, the PCI1031 returns to the default state. When the PCI1031 SUSPEND mode is enabled, the device is protected from any RSTIN reset (i.e., the PCI1031 internal register contents are preserved). See power management. PCI address and data TERMINAL I/O FUNCTION NAME NO. TYPE FUNCTION AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 170 171 173 174 176 177 178 179 183 184 185 186 188 189 190 191 204 205 206 208 I/O Address/data bus. AD31–AD0 are the multiplexed PCI address and data bus. During the address phase of a PCI cycle, AD31–AD0 contain a 32-bit address or other destination information. During the data phase, AD31–AD0 contain data. C/BE3 C/BE2 C/BE1 C/BE0 180 192 203 I/O Bus commands and byte enables. C/BE3–C/BE0 are multiplexed on the same PCI terminals. During the address phase, C/BE3–C/BE0 define the bus command. During the data phase, C/BE3–C/BE0 are used as byte enables. The byte enables determine which byte lanes carry meaningful data. C/BE0 applies to byte 0 (AD7–AD0), C/BE1 applies to byte 1 (AD15–AD8), C/BE2 applies to byte 2 (AD23–AD16), and C/BE3 applies to byte 3 (AD31–AD24). PAR 202 I/O Parity. As a PCI target during PCI read cycles, or as PCI bus master during PCI write cycles, the PCI1031 calculates even parity across the AD and C/BE buses and outputs the results on PAR, delayed by one clock.

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Terminal Functions (Continued) PCI interface control TERMINAL I/O FUNCTION NAME NO. TYPE FUNCTION DEVSEL 197 I/O Device select. As a PCI target, the PCI1031 asserts DEVSEL to claim the current cycle. As a PCI master, the PCI1031 monitors DEVSEL until a target responds or a time-out occurs. FRAME 193 I/O Cycle frame. FRAME is driven by the current master to indicate the beginning and duration of an access. FRAME is low (asserted) to indicate that a bus transaction is beginning. While FRAME is asserted, data transfers continue. When FRAME is sampled high (deasserted), the transaction is in the final data phase. GNT 168 I Grant. GNT is driven by the PCI arbiter to grant the PCI1031 access to the PCI bus after the current data transaction is complete. If distributed DMA is not implemented, GNT must be pulled high with a 43-kW resistor. IDSEL 182 I Initialization device select. IDSEL selects the PCI1031 during configuration accesses. IDSEL can be connected to one of the upper 24 PCI address lines. IRDY 195 I/O Initiator ready. IRDY indicates the bus master’s ability to complete the current data phase of the transaction. IRDY is used with TRDY. A data phase is completed on any clock where both IRDY and TRDY are sampled low (asserted). During a write, IRDY indicates that valid data is present on AD31–AD0. During a read, IRDY indicates that the master is prepared to accept data. Wait cycles are inserted until both IRDY and TRDY are low (asserted) at the same time. IRDY is an output when the PCI1031 is the PCI bus master and an input when the PCI bus is the target. PERR 199 I/O Parity error. PERR is driven by the PCI target during a write to indicate that a data parity error has been detected. REQ 169 O Request. REQ asserted by the PCI1031 to request access to the PCI bus as a master. SERR 200 O System error. SERR pulsed from the PCI1031 indicates an address parity error has occurred. If SERR is not used, it must be pulled high with a 43-kW resistor. STOP 198 I/O Stop. STOP is driven by the current PCI target to request the master to stop the current transaction. TRDY 196 I/O Target ready. TRDY indicates the ability of the PCI1031 to complete the current data phase of the transaction. TRDY is used with IRDY. A data phase is completed on any clock where both TRDY and IRDY are sampled asserted. During a read, TRDY indicates that valid data is present on AD31–AD0. During a write, TRDY indicates that the PCI1031 is prepared to accept data. Wait cycles are inserted until both IRDY and TRDY are asserted together. TRDY is an output when the PCI1031 is the PCI target and an input when the PCI1031 is the PCI bus master. power supply TERMINAL FUNCTION NAME NO. FUNCTION GND 13, 22, 44, 75, 96, 129, 153, 167, 181, 194, 207Device ground terminals VCC 7, 31, 64, 86, 113, 143, 164, 175, 187, 201Power-supply terminals for core logic (3.3 V) VCCA 120 Power-supply terminal for PC Card A (5 V or 3.3 V) VCCB 38 Power-supply terminal for PC Card B (5 V or 3.3 V) VCCP 148, 172 Power-supply terminals for PCI interface (5 V or 3.3 V)

PCI-TO-PC CARD16 CONTROLLER UNIT SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) interrupt TERMINAL I/O FUNCTION NAME NO. TYPE FUNCTION IRQ3/INTA IRQ4/INTB 154 155 O Interrupt request 3 and interrupt request 4. IRQ3/INTA–IRQ4/INTB can be connected to either PCI or ISA interrupts. IRQ3/INTA–IRQ4/INTB are software configurable as IRQ3 or INTA and as IRQ4 or INTB. When configured for IRQ3 and IRQ4, IRQ3/INTA–IRQ4/INTB must be connected to the ISA IRQ programmable interrupt controller. When IRQ3/INTA–IRQ4/INTB are configured for INTA and INTB, IRQ3/INTA–IRQ4/INTB must be connected to available interrupts on the PCI bus. IRQ7/PCDMAREQ 157 O Interrupt request 7. IRQ7/PCDMAREQ is software configurable and is used by the PCI1031 to request PC/PCI DMA transfers from chipsets that support the PC/PCI DMA scheme. When IRQ7/PCDMAREQ is configured for PC/PCI DMA request (IRQ7), it must be connected to the appropriate request (REQ) pin on the Intel Mobile Triton PCI I/O accelerator (MPIIX ) (see PC/PCI DMA ). IRQ9/IRQSER 158 O I/O Interrupt request 9/serial IRQ. IRQ9/IRQSER is software configurable and indicates an interrupt request from a PC Card to the PCI1031. When IRQ9/IRQSER is configured for IRQ9, it must be connected to the system programmable interrupt controller. IRQSER allowa all IRQ signals to be serialized onto one pin. IRQ9/IRQSER is configured via bits 2–1 in the device control register of the TI extension registers (see device control register). IRQ10/CLKRUN 159 O Interrupt requests 10. IRQ10/CLKRUN is software configurable and is used by the PCI1031 to support the PCI CLKRUN protocol. When configured as CLKRUN by setting bit 0 in the system control register at offset 80h, IRQ10/CLKRUN is an open drain output (see system control register). IRQ11/PCDMAGNT 160 I/O Interrupt request 11. IRQ11/PCDMAGNT is software configurable and is used by the PCI1031 to accept a grant for PC/PCI DMA transfers from chipsets that support the PC/PCI DMA scheme. When IRQ11/PCDMAGNT is configured for PC/PCI DMA grant (IRQ11), it must be connected to the appropriate grant (GNT) pin on the Intel MPIIX controller (see PC/PCI DMA ). IRQ5 IRQ12 IRQ14 156 161 162 O Interrupt requests 5, 12, and 14. These signals are ISA interrupts. These terminals indicate an interrupt request from one of the PC Cards. The interrupt mode is selected in the device control register of the TI extension registers (see device control register). IRQ15/RI_OUT 163 I/O Interrupt request 15. IRQ15/RI_OUT indicates an interrupt request from one of the PC Cards. RI_OUT allows the RI input from the 16-bit PC Card to be output to the system. IRQ15/RI_OUT is configured in the card control register of the TI extension registers (see card control register). PC Card power switch TERMINAL I/O FUNCTION NAME NO. TYPE FUNCTION CLOCK 151 O Power switch clock. Information on the DATA line is sampled at the rising edge of CLOCK. The frequency of the clock is derived from dividing PCICLK by 36. The maximum frequency of CLOCK is 2 MHz (see TPS2206 PC Card power control interface). DATA 152 O Power switch data. DATA is used by the PCI1031 to serially communicate socket power control information. LATCH 150 O Power switch latch. LATCH is asserted by the PCI1031 to indicate to the PC Card power switch that the data on the DATA line is valid. speaker control TERMINAL I/O FUNCTION NAME NO. TYPE FUNCTION SPKROUT / SUSPEND 149 O Speaker. SPKROUT carries the digital audio signal from the PC Card. SUSPEND, when enabled, places the PCI1031 in PCI suspend/resume (see power management ). SPKROUT/SUSPEND is configured in the card control register (see card control register) of the TI extension registers.

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Terminal Functions (Continued) 16-bit PC Card address and data (slots A and B) TERMINAL NUMBER I/O FUNCTION NAME SLOT A † SLOT B ‡ TYPE FUNCTION A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 121 118 116 114 111 109 107 105 103 112 115 108 106 117 100 102 104 119 123 125 126 128 131 132 133 O PC Card address. 16-bit PC Card address lines. A25 is the most-significant bit. D15 D14 D13 D12 D11 D10 147 145 142 146 144 141 I/O PC Card data. 16-bit PC Card data lines. D15 is the most-significant bit. † Terminal name is preceded with A_. For example, the full name for terminal 121 is A_A25. ‡ Terminal name is preceded with B_. For example, the full name for terminal 55 is B_A25.

PCI-TO-PC CARD16 CONTROLLER UNIT SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997 11POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) 16-bit PC Card interface control signals (slots A and B) TERMINAL NUMBER I/O FUNCTION NAME SLOT A † SLOT B ‡ TYPE FUNCTION BVD1 (STSCHG /RI) 138 72 I Battery voltage detect 1. Generated by 16-bit memory PC Cards that include batteries. BVD1 is used with BVD2 as an indication of the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are kept high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and needs to be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost. See ExCA card status-change interrupt configuration register for enable bits. See ExCA card status-change register and ExCA interface status register for the status bits for this signal. Status change. STSCHG is used to alert the system to a change in the READY, write protect, or battery voltage dead condition of a 16-bit I/O PC Card. Ring indicate. RI is used by 16-bit modem cards to indicate ring detection. BVD2(SPKR ) 137 71 I Battery voltage detect 2. Generated by 16-bit memory PC Cards that include batteries. BVD2 is used with BVD1 as an indication of the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and needs to be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost. See ExCA card status-change interrupt configuration register for enable bits. See ExCA card status-change register and ExCA interface status register for the status bits for this signal. Speaker. SPKR is an optional binary audio signal available only when the card and socket have been configured for the 16-bit I/O interface. The audio signals from cards A and B can be combined by the PCI1031 and output on SPKROUT DMA request. BVD2 can be used as the DMA request signal during DMA operations to a 16-bit PC Card that supports DMA. If used, the PC Card asserts BVD2 to request a DMA operation. CD1 CD2 140 I PC Card detect 1 and PC Card detect 2. CD1 and CD2 are internally connected to ground on the PC Card. When a PC Card is inserted into a socket, CD1 and CD2 are pulled low. For signal status, see ExCA interface status register. CE1 CE2 O Card enable 1 and card enable 2. CE1 and CE2 enable even- and odd-numbered address bytes. CE1 enables even-numbered address bytes, and CE2 enables odd-numbered address bytes. INPACK 127 61 I Input acknowledge. INPACK is asserted by the PC Card when it can respond to an I/O read cycle at the current address. DMA request. INPACK can be used as the DMA request signal during DMA operations to a 16-bit PC Card that supports DMA. If used, the PC Card asserts INPACK to indicate a request for a DMA operation. IORD 99 33 O I/O read. IORD is asserted by the PCI1031 to enable 16-bit I/O PC Card data output during host I/O read cycles. DMA write. IORD is used as the DMA write strobe during DMA operations from a 16-bit PC Card that supports DMA. The PCI1031 asserts IORD during DMA transfers from the PC Card to host memory. IOWR 101 35 O I/O write. IOWR is driven low by the PCI1031 to strobe write data into 16-bit I/O PC Cards during host I/O write cycles. DMA read. IOWR is used as the DMA read strobe during DMA operations to a 16-bit PC Card that supports DMA. The PCI1031 asserts IOWR during DMA transfers from host memory to the PC Card. OE 98 32 O Output enable. OE is driven low by the PCI1031 to enable 16-bit memory PC Card data output during host memory read cycles. DMA terminal count. OE is used as terminal count (TC) during DMA operations to a 16-bit PC Card that supports DMA. The PCI1031 asserts OE to indicate TC for a DMA write operation. † Terminal name is preceded with A_. For example, the full name for terminal 138 is A_BVD1. ‡ Terminal name is preceded with B_. For example, the full name for terminal 72 is B_BVD1.

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Terminal Functions (Continued) 16-bit PC Card interface control signals (slots A and B) (continued) TERMINAL NUMBER I/O FUNCTION NAME SLOT A † SLOT B ‡ TYPE FUNCTION READY(IREQ ) 135 69 I Ready. The ready function is provided by READY when the 16-bit PC Card and the host socket are configured for the memory-only interface. READY is driven low by the 16-bit memory PC Cards to indicate that the memory card circuits are busy processing a previous write command. READY is driven high when the 16-bit memory PC Card is ready to accept a new data transfer command. Interrupt request. IREQ is asserted by a 16-bit I/O PC Card to indicate to the host that a device on the 16-bit I/O PC Card requires service by the host software. IREQ is high (deasserted) when no interrupt is requested. REG 130 63 O Attribute memory select. REG remains high for all common memory accesses. When REG is asserted, access is limited to attribute memory (OE or WE active) and to the I/O space (IORD or IOWR active). Attribute memory is a separately accessed section of card memory and is generally used to record card capacity and other configuration and attribute information. DMA acknowledge. REG is used as DMA acknowledge (DACK) during DMA operations to a 16-bit PC Card that supports DMA. The PCI1031 asserts REG to indicate a DMA operation. REG is used with the DMA read (IOWR) or DMA write (IORD) strobes to transfer data. RESET 124 58 O PC Card reset. RESET forces a hard reset to a 16-bit PC Card. WAIT 136 70 I Bus cycle wait. WAIT is driven by a 16-bit PC Card to delay the completion of (i.e., extend) the memory or I/O cycle in progress. WE 110 46 O Write enable. WE is used to strobe memory write data into 16-bit memory PC Cards. WE also is used for memory PC Cards that employ programmable memory technologies. DMA terminal count. WE is used as TC during DMA operations to a 16-bit PC Card that supports DMA. The PCI1031 asserts WE to indicate TC for a DMA read operation. WP(IOIS16) 139 73 I Write protect. WP applies to 16-bit memory PC Cards. WP reflects the status of the write-protect switch on 16-bit memory PC Cards. For 16-bit I/O cards, WP is used for the 16-bit port (IOIS16 function. The status of WP can be read from the ExCA interface status register. I/O is 16 bits. WP applies to 16-bit I/O PC Cards. IOIS16 is asserted by the 16-bit PC Card when the address on the bus corresponds to an address to which the 16-bit PC Card responds, and the I/O port that is addressed is capable of 16-bit accesses. DMA request. WP can be used as the DMA request signal during DMA operations to a 16-bit PC Card that supports DMA. If used, the PC Card asserts WP to request a DMA operation. VS1 VS2 134 122 I/O Voltage sense 1 and voltage sense 2. VS1 and VS2, when used together, determine the operating voltage of the 16-bit PC Card. DMA request. VS1 and VS2 can be used as the DMA request signal during DMA operations to a 16-bit PC Card that supports DMA. If used, the PC Card asserts VS1 and VS2 to indicate a for request a DMA operation. † Terminal name is preceded with A_. For example, the full name for terminal 135 is A_READY(IREQ). ‡ Terminal name is preceded with B_. For example, the full name for terminal 69 is B_READY(IREQ).

PCI-TO-PC CARD16 CONTROLLER UNIT SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997 13POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 architecture This section provides an overview of the PCI1031 PCI-to-PC Card/CardBus controller, followed by detailed descriptions of PCI and PC Card interfaces, the TPS2206 interface, and interrupt support. Both hardware protocols and software programming models are discussed. introduction to the PCI1031 The PCI1031 is a bridge between the PCI local bus and two PC Card sockets supporting 16-bit PC Cards, and is compliant with the PCI local bus specification revision 2.1 and PCMCIA’s 1995 PC Card standard. The PCI1031 PC Card interface recognizes and identifies PC Cards installed at power up or run-time. The PCI1031 includes support for 16-bit PC Card features such as multifunction cards, 3.3-V cards, and DMA, as well as backward compatibility to the PCMCIA release 2.1-compliant PC Cards. The PCI1031 core is powered at 3.3 V to provide low power dissipation, but can independently support either 3.3-V or 5-V signaling on the PCI and PC Card interfaces. Host software interacts with the PCI1031 through a variety of internal registers that provide status and control information about the PC Cards currently in use and the internal operation of the PCI1031 itself. These internal registers are accessed by application software either through the PCI configuration header, or through programmable windows mapped into PCI memory or I/O address space. The PCI1031 uses a windows format to pass cycles between PCI and PC Card address spaces. Host software must program the location and size of these windows when the PCI1031 or PC Card is initialized. The PCI1031 also communicates via a three-line serial protocol to the TI TPS2206 dual PCMCIA power switch. The TPS2206 switches V CC and VPP supply voltage to the two PC Card sockets independently. Host software has indirect control over the TPS2206 by writing to internal PCI1031 registers. The PCI1031 can notify the host system via interrupts when an event occurs that requires attention from the host. Such events are either card status-change (CSC) events or functional interrupts from a PC Card. CSC events occur within the PCI1031 or at the PC Card interface, and indicate a change in the status of the socket (i.e., card insertion or removal). Functional interrupts originate from the PC Card application and are passed from the card to the host system. Both CSC and functional interrupts can be individually masked and routed to a variety of system interrupts. The PCI1031 can signal the system interrupt controller via PCI-style interrupts, ISA IRQs, or with the serialized IRQ protocol. The following sections describe in greater detail how the PCI1031 interacts at an electrical, protocol, and software level at its PCI interface, PC Cards, TPS2206 PC Card power control, and interrupts.

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CCP terminals to the desired switching level. and write cycles to one of the three PCI address spaces: memory, I/O, and configuration address spaces. Table 3. PCI Command Definition

0000 Interrupt acknowledge

0001 Special cycle

0010 I/O read

0011 I/O write

0100 Reserved

0101 Reserved

0110 Memory read

0111 Memory write

1000 Reserved

1001 Reserved

1010 Configuration read

1011 Configuration write

1100 Memory read multiple

1101 Dual address cycle

1110 Memory read line

1111 Memory write and invalidate

also set this bit during device initialization.

PCI-TO-PC CARD16 CONTROLLER UNIT SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

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The PCI local bus specification defines an I/O address space accessed using 32-bit addresses, yielding a 4G-byte usable address space. The PCI1031 decodes PCI I/O cycles as a PCI target device only if host software has enabled it to do so (see bit 0 of the PCI command register). If so enabled, the PCI1031 positively decodes the address on the PCI address AD bus and claims the cycle if a hit is detected to a programmed I/O window. Such a window can be mapped either to internal PCI1031 registers or to PC Card address space. There are two instances where the PCI1031 maps internal registers to PCI I/O address space. The first is the legacy 16-bit PC Card index/data registers (used to access the ExCA registers), and the second is DMA socket registers (used to access registers in distributed DMA). In both cases, the locations of these windows are programmed by base address registers in PCI configuration space. The legacy 16-bit PC Card base address (see PC Card 16-bit I/F legacy-mode base address) is located at configuration offset 44h, and is common to both PCI1031 functions 0 and 1. This base address locates a 2-byte window in I/O space anywhere in the 32-bit I/O address space. The socket DMA base address register (see socket DMA register 1) is located at configuration offset 98h, and is separate and distinct for functions 0 and 1. This base address locates a 16-byte window in I/O space in the lower 64K bytes of PCI I/O address space. For a complete description of this base address register and the socket DMA registers, see socket DMA register 1 and DMA registers. The PCI1031 provides the ability for host software to program PCI I/O windows to PC Card address spaces. These windows provide the bounds upon which the PCI1031 positively decodes I/O cycles from PCI to a PC Card, and are the primary means for applications to communicate with PC Cards. See 16-bit PC Cards and windows, ExCA registers, and CardBus PC Cards and windows. PCI memory address space The PCI local bus specification also defines a memory address space accessed using 32-bit addresses, yielding a 4G-byte usable address space. The PCI1031 decodes PCI memory cycles as a PCI target device only if host software has enabled it to do so (see bit 1 of the PCI command register). If so enabled, the PCI1031 positively decodes the address on the PCI address AD bus and claims the cycle if a hit is detected to a programmed memory window. Such a window can be mapped either to internal PCI1031 registers or to PC Card address space. The only case where the PCI1031 maps internal registers to PCI memory address space is the CardBus/ExCA registers that are mapped into a 4K-byte window for each socket. The location of these windows is programmed by a base address register in PCI configuration space. The CardBus socket/ExCA base address (see CardBus socket registers/ExCA registers base address register) is located at configuration offset 10h and is separate and distinct from functions 0 and 1. Each base address locates a 4K-byte window in memory space anywhere in the 32-bit memory address space. For a description of this base address register and the CardBus socket registers, see CardBus socket registers/ExCA registers base address register. The PCI1031 enables host software to program PCI memory windows to PC Card address spaces. These windows provide the bounds on which the PCI1031 positively decodes memory cycles from PCI to a PC Card and are the primary means for applications to communicate with PC Cards (see 16-bit PC Cards and windows and ExCA registers). A memory read always disconnects after the first data phase. compliance to PCI local bus specification revision 2.1 The most significant additions to the PCI local bus specification revision 2.1 are the latency requirements on PCI peripherals. Minimum response times are specified for a PCI device to respond with valid data. These requirements are intended to improve throughput and reduce latencies on the PCI bus. The PCI1031 is fully compliant with these guidelines. Other additions to revision 2.1 of the PCI local bus specification include the subsystem ID and subsystem vendor ID registers in the PCI configuration header.

interface redefined for a synchronous, 32-bit bus environment patterned after PCI. must initiate upon card insertion into a cold, unpowered socket. this is defined in the 1995 PC Card standard and in Table 4. Table 4. PC Card Card Detect and Voltage Sense Connections

PCI-TO-PC CARD16 CONTROLLER UNIT SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

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PC Card insertion/removal and recognition (continued) Based on the information described in Table 4, the PCI1031 executes an algorithm upon card insertion that alternatively drives the VS1 and VS2 pins to low and high levels to determine which of the card types has been inserted. This process is completed without VCC ever being applied to the socket. Once the PCI1031 has successfully determined the card type and voltage requirements, it updates the appropriate status bits in the socket present state register (see socket present state register) and asserts a CSC interrupt to the host system. Host software must then read the CardBus socket registers to determine the card type and voltage requirements and respond accordingly. 16-bit PC Cards and windows The PCMCIA revision 1.0 defined the original 16-bit memory card, and the later PCMCIA revisions 2.0 and 2.1 defined the 16-bit I/O card. Both types of 16-bit PC Cards have the 16-bit datapaths and a 26-bit address bus defined. Status and control signals differ between the two card types. The PCI1031 fully supports both types of cards. The ExCA register set is implemented in the PCI1031, which provides the industry standard Intel 82365SL-DF programming model. The 16-bit memory cards can have two types of memory address space: attribute memory and common memory. The attribute memory address space contains the CIS, and common memory is the memory space used by the application. The CIS is defined by PCMCIA and contains a variety of information about the card capabilities and resource requirements. Host software reads and parses the CIS to set up the system resources to use the card application. Both attribute and common memory are accessed with 26-bit addresses, resulting in a total addressable memory address space of 64M bytes. The 16-bit I/O cards can possess attribute and common memory, but also have an I/O address space. This address space is accessed via 16-bit I/O addresses, resulting in a 64K-byte I/O address space. The PCI1031 provides a windowing mechanism to link the PCI address space to 16-bit PC Card address space. Both of these memory and I/O windows are programmed by host software in the ExCA registers. The PCI1031 provides up to five memory windows per socket and two I/O windows per socket. Once enabled, the PCI1031 positively decodes and claims bus cycles that fall within these windows. Bus cycles to the PC Card are then initiated to write data to the card (in the case of a PCI write cycle) or to read data from the card (in the case of a PCI read cycle). Memory and I/O windows to 16-bit PC Cards have several programmable options associated with them. Host software can choose among these options by setting the appropriate bits in the appropriate ExCA registers. These options include: /C0068Window start address /C0068Window end address /C0068Window offset address /C0068Page address (for 16-bit PC Card memory windows only) /C0068Attribute or common memory access (for 16-bit PC Card memory windows only) /C0068PC Card datapath width (8 bit or 16 bit) /C0068Wait state timing (ISA bus timing or minimum) /C0068Write protection (enable/disable writes to memory windows) The start, end, offset, and page address define the bounds of the memory window in PCI and PC Card memory address spaces. The page address is necessary to take into account the difference in addressable memory between PCI (4G bytes) and 16-bit PC Cards (64M bytes). The 8-bit page address appended to the 26-bit start and end addresses define the bounds of the window in PCI memory address space. When a PCI memory cycle is decoded and claimed, the PCI1031 adds the offset address to the PCI address before passing the lower 26 bits to the PC Card. The memory windows need not be aligned between the two address spaces.

PCI-TO-PC CARD16 CONTROLLER UNIT SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997 19POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ExCA registers The PCI1031 is fully register compatible with the Intel 82365SL-DF PC Card interface controller. The ExCA compatibility registers can be accessed indirectly via PCI I/O address space or directly via PCI memory address space. For I/O access, the PCI1031 uses the same index and data I/O port scheme introduced by Intel. This index/data window is located in PCI I/O space by the PC Card 16-bit I/F legacy base address (see PC Card 16-bit I/F legacy-mode base address), found at offset 44h in PCI configuration space. The PC Card 16-bit legacy-mode base address is shared by both sockets and the ExCA registers run contiguously from index 00h–3Fh for socket A and 40h–7Fh for socket B. Accesses to ExCA indices 80–FFh returns 0s when read. Writes have no effect. The compatibility registers can also be accessed directly through the CardBus socket/ExCA register window. This window in PCI memory address space is located by the CardBus socket registers/ExCA base address register (see CardBus socket registers/ExCA registers base address register), found at offset 10h in PCI configuration space. The ExCA compatibility registers are directly mapped into this memory window, starting at an offset of 800h from the bottom of this window. Each socket has a separate CardBus socket register/ExCA registers base address register for accessing the ExCA registers. ExCA I/O windows are accessed on word (16-bit) boundaries. The ExCA registers provide bits to control many 16-bit PC Card functions. These functions include: /C0068Explicit writeback/clear on read of interrupt flag mode selection /C0068PC Card CSC and functional interrupt control /C0068Interrupt mode select: level/edge interrupt modes /C0068PC Card socket status information /C0068ExCA registers configuration after PC Card removal – reset upon card removal or save the register values upon card removal /C0068Memory and I/O windows configuration for 16-bit PC Cards Table 5 classifies the basic functionality of each register in the ExCA register set. The functional classifications are: card status register, card control register, memory window, and I/O window. Some of the registers are classified as both card status and card control since some bits within the register provide status information and other bits provide card control. When a 16-bit PC Card is installed in a socket, the entire ExCA register set associated with that socket is enabled. Some status and control functions in the CardBus socket registers are maintained when a16-bit PC Card is present, such as the socket power control register. Software is expected to use either ExCA or CardBus socket registers to control socket power, but not both. The intent is to be fully backward compatible with present card and socket services, but take advantage of the easy access of some of the newly defined registers in the CardBus/ExCA socket registers.

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Table 5. ExCA Registers

Table 5. ExCA Registers (Continued) † The memory window page register is mapped by the CardBus socket register/ExCA register base address register into PCI memory space. in the system. References in this document to the TPS2206 apply identically to the TPS2202A device. The PCI1031 and TPS2206 communicate via a 3-line serial interface called P2C (PCMCIA peripheral control).

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Figure 3. Serial-Interface Timing switch; otherwise, the PCI1031 stops the clock in a logic low state. Table 6. TPS2206 Control Logic standards. The ExCA register set provides interrupt control for 16-bit PC Card functions. discussed in detail in the following sections, as well as any specific options to be configured by host software. traditional ISA IRQ signaling, serialized IRQ protocol, or PCI with ISA interrupts.

specially defined signals on the PC Card interface. Functional interrupts are generated by 16-bit I/O PC Cards. installed in the socket at any given time. The 16-bit interrupt sources differ between memory and I/O PC Cards. between card types upon card insertion. Table 7. PC Card Interrupt Events and Description memory PC Card to accept or provide data. an insertion or removal of a 16-bit // CardBus PC Card. during memory card data transfers. depend on a signal change at the PC Card interface, but rather the completion of applying power to the socket. is specific to the interrupt signaling method used and is discussed in the following sections.

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bits, the interrupt service routine can determine which action to take. Table 8. PC Card Interrupt Mask and Flag Registers PC Card-related interrupt flags. One is a write of 1 to the bit in question, and the other is a read from the register. card control register). Refer to the section on PCI interrupt signaling for details. All unused interrupt pins should be pulled high by a 43-kW resistor. Among the PCI1031 interrupt signaling schemes is the traditional ISA IRQ signaling, available in most x86 PCs. PC Card applications and several free IRQs for CSC routing. then writing the new value back to the respective PCI1031 register.

PCI-TO-PC CARD16 CONTROLLER UNIT SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997 25POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ISA IRQ interrupts (continued) 1. Set bits 2–1 of PCI configuration register 92h (function 0) to 01b for interrupt mode selection. 2. Write to the upper four bits of ExCA register 05h/45h/805h for desired CSC routing for each socket (note the restrictions placed on interrupt routing with ISA IRQ signaling; only ten IRQs are valid in this mode). 3. If a PC Card is installed in the socket and requires functional interrupts, write to the lower nibble of ExCA register 03h/43h/803h for desired functional interrupt routing for the socket (note the restrictions placed on interrupt routing with ISA IRQ signaling). 4. Using Table 9, write to the appropriate mask register bits to enable interrupt generation for desired events. 5. Upon card-removal events, host software should unroute any functional interrupts that were set for that socket. 6. Upon card-insertion events, host software should reconfigure the mask and routing registers to support the new card requirements. PCI interrupts NOTE: PCI interrupts can be used with ISA interrupts. All unused INTA and INTB lines should be pulled high by a 43-kW resistor. The PCI1031 also supports interrupt signaling compliant with the PCI local bus specification. Consistent with this specification, the PCI1031 can use one PCI interrupt for each of its functions: INTA is used for PC Card socket A interrupts, and INTB is used for socket B. These pins are on the PCI1031 at pins 154 and 155 and are dual-function pins with the ISA-mode interrupts IRQ3 and IRQ4. When the PCI1031 is configured for PCI interrupt signaling, these pins behave as open-drain PCI interrupts. Systems that prefer a single interrupt line from the PCI1031 can connect these two interrupt terminals together. PCI configuration register offset 91h must be written in order to route CSC and functional interrupts from each socket. The step-by-step series of events for host software to successfully configure the PCI1031 for PCI signaling follows. These steps assume that the system has powered up and RSTIN is high (deasserted). In cases where only selected bits of a register are to be modified, host software must leave the remaining register bits unchanged by reading the current contents of the register first, modifying the desired bits, then writing the new value back to the register. 1. Set bit 5 of PCI configuration register 91h (function 0) to a value of 1 (enabled). 2. Set bit 3 of PCI configuration register 91h (functions 0 and 1 separately) to route CSC interrupts to INTA (for socket A) or INTB (for socket B). 3. If a PC Card is installed in the socket and requires functional interrupts, write to bit 4 of the PCI Card control register 91h (for the socket) to route functional interrupts from the PC Card to INTA (for socket A) or INTB (for socket B). 4. Using Table 8, write to the appropriate mask register bits to enable interrupt generation for desired events. 5. Upon card-removal events, host software should disable any functional interrupts generation. 6. Upon card insertion events, host software should reconfigure the mask and routing registers to support the new card requirements.

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to eight clock periods). This allows the serial packet to retain coherence on either side of a PCI-to-PCI bridge. but can be extended to allow more sampling periods for platform-specific functions. Figure 4. Serial-Interrupt Timing – Start Cycle and IRQ Sampling Periods Figure 5. Serial-Interrupt Timing – Stop Cycle

PCI-TO-PC CARD16 CONTROLLER UNIT SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997 27POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 serialized IRQ signaling (continued) 1. Set bits 2–1 of PCI device control register 92h (function 0) to 10b. 2. Write to the upper nibble of ExCA register 05h/45h/805h for desired CSC routing for each socket (all 15 IRQs are available for routing when serialized IRQ signaling has been selected). 3. If a PC Card is installed in the socket and requires functional interrupts, write to the lower nibble of ExCA register 03h/43h/803h for desired functional interrupt routing for the socket. 4. Using Table 8, write to the appropriate mask register bits to enable interrupt generation for desired events. 5. On card-removal events, host software should unroute any functional interrupts that were set for that socket. 6. Upon card-insertion events, host software should reconfigure the mask and routing registers to support the new card requirements. PCI clock run The PCI1031 supports PCI clock run (CLKRUN ). CLKRUN is an optional signal that is used as an input to determine the status of CLK as an open-drain output to request the CLK to restart or to speed up. PCI CLKRUN is enabled by setting bit 0 in the system control register (see system control register). When the PCI clock resource manager informs the PCI1031 that the PCI clock is stopped or slowed, the PCI1031 ensures that no transactions are in progress for either of the two PC Card sockets before allowing the clock resource manager to stop or slow the PCI clock. CLKRUN shares the IRQ10 pin on the PCI1031. See system control register for information on configuring the clock run option. CLKRUN configuration Bits 1–0 in the TI extension registers at offset 80h are used to enable and configure CLKRUN. Bit 0 enables CLKRUN. Bit 1, when set, keeps the PCI clock running in response to a PCI CLKRUN deassertion (see system control register). conditions for stopping/slowing the PCI clock Before allowing the central resource to slow or stop the PCI clock, the following conditions are checked: /C0068The PCI CLKRUN enable bit is set and the KEEP CLOCK bit is cleared (see system control register, bit 1). /C0068Neither socket is in the process of powering up or powering down. /C0068The 16-bit resource managers are not busy. /C0068The PCI master is not busy. /C0068No socket interrogation is underway. /C0068No card interrupts are pending. conditions for restarting the PCI clock The PCI clock restarts when any PC Card is installed in a socket or removed from a socket. For 16-bit cards, if the PCI clock stops or slows, the PCI1031 requests that the clock be restarted under the following conditions: /C0068A 16-bit I/O card asserts IREQ. /C0068A 16-bit I/O card asserts STSCHG/RI. /C0068A 16-bit DMA card asserts DREQ.

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systems designed with the Intel MPIIX. cycles to host memory address space. Host software must program the PCI1031 socket DMA registers 0 and 1 to set up the socket for DMA transfers. applies to the PCI portion of DMA transfers and complies with the distributed DMA specification. and configures the DMA transfer process. Table 9. Socket DMA Register 1 31–16 R Reserved. Bits 31–16 are read only and return 0s when read. Writes have no effect. address space. The lower four bits are hardwired to 0, forcing the window to a natural 16-byte boundary. 3 R Nonlegacy extended addressing. This is not supported on the PCI1031 and always returns a 0.

0 R/W

signaling option, the datapath width, and enable the DMA register decode in I/O space. programmed. The DMA register programming model is shown in Table 10.

Table 10. DMA Registers only, and return 0s when read. Writes to reserved registers have no effect.

1. Set the proper DMA request (DREQ

) signal assignment in the PCI configuration, offset 94h (bits 1–0).

1. Set the proper data width of the DMA transfer in the PCI configuration, offset 98h (bits 2–1).
2. Enable I/O window decoding of the DMA registers by setting bit 0 in the PCI configuration offset 98h.

to the PCI bus again until the transfer count expires.

PCI-TO-PC CARD16 CONTROLLER UNIT SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

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DMA transfers (continued) PCI I/O read and write cycles to the DMA registers are accepted and serviced during DMA transfers. If, while a DMA transfer is in progress, the host resets the DMA channel, the PCI1031 asserts TC and ends the PC Card cycle(s). TC is indicated in the DMA status register. At the PC Card interface, the PCI1031 supports demand mode transfers. The PCI1031 asserts DACK the entire duration of the transfer unless DREQ is high (deasserted) before TC. There is no performance penalty for long wait states during this mode of operation as there is in the legacy ISA system, because the DMA channel is a dedicated resource localized at the PC Card socket. PC/PCI DMA The PC/PCI DMA protocol provides a way for legacy I/O devices to do DMA transfers on the PCI bus in systems equipped with the Intel MPIIX. The Intel MPIIX supports PC/PCI DMA expansion for docking station applications where I/O devices require DMA transfers between the docking station PCI bus or extended I/O bus and a PCI bus in the notebook docking computer. In the PC/PCI DMA protocol, the PCI1031 acts as a PCI slave device. The Intel MPIIX DMA controller uses request/grant pairs, REQ [A–B] and GNT[A–B], which are configured to support a PCI DMA slave device such as the PCI1031. The Intel MPIIX REQ and GNT pins correspond to the PCI1031 IRQ7 and IRQ11 pins, respectively. Under the PC/PCI protocol, a PCI DMA slave device requests a DMA transfer using a serialized protocol on REQ . The Intel MPIIX, as a bus master, arbitrates for the PCI bus. When the Intel MPIIX gets control of the PCI bus, it asserts GNT on the PCI1031 and, for the selected DMA channel, runs the DMA I/O cycles and memory cycles on the PCI bus. PC/PCI DMA is enabled for each PC Card16 slot by setting bit 19 in the respective system control register (see Table 16). On power up, bit 19 is cleared, disabling PC/PCI DMA. Bit 3 of each PCI1031 system control register is a global PC/PCI enable bit. When bit 3 is set, the PCI1031 can request a DMA transfer by asserting IRQ7 (REQ ) and encoding the channel request information using the serialized protocol. When the Intel MPIIX gets control of the PCI bus, it encodes the granted channel on the PCI1031 IRQ11 (GNT) pin. On power up, bit 3 is cleared and PC/PCI DMA is disabled. When the PCI1031 receives a GNT signal, it looks at the DMA I/O address to determine the type of transfer. The cycle types are as follows: DMA I/O ADDRESS DMA CYCLE TYPE TERMINAL COUNT PCI CYCLE TYPE 00h Normal 0 I/O read/write 04h Normal TC 1 I/O read/write C0h Verify 0 I/O read C4h Verify TC 1 I/O read

PCI-TO-PC CARD16 CONTROLLER UNIT SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997 31POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PC/PCI DMA (continued) To do PC/PCI DMA transfers, the following conditions must be met: /C0068Bit 3 in the system control register must be set to enable the PCI1031 to do PC/PCI DMA transfers. /C0068The desired DMA channel for each PC Card16 slot (slot A and slot B) must be configured via bits 18–16 in the respective system control register (see Table 16). The Intel MPIIX uses this channel to do the DMA transfers. The channels are configured as follows: BITS DMA CHANNEL 18 17 16 DMA CHANNEL 0 0 0 Channel 0 0 0 1 Channel 1 0 1 0 Channel 2 0 1 1 Channel 3 1 0 0 Channel 4 1 0 1 Channel 5 1 1 0 Channel 6 1 1 1 Channel 7 /C0068Each PC Card16 slot must be enabled by setting bit 19 of the respective system control register. DMA channels 0–3 are used for 8-bit DMA transfers and channels 5–7 are used for 16-bit DMA transfers. On power up, the system control register bits 18–16 default to 100 (channel 4). DMA channel 4 is used by PCI master devices to request the bus; hence, PC/PCI DMA is not the default mode. The REQ and GNT signal pairs can be configured to support slave devices on the primary bus (i.e., the same bus as the Intel MPIIX) or slave devices on a secondary bus such as a PCI-to-ISA bridge. The REQ/GNT pairs are configured by setting the PCI DMA expansion register (offset 088h and 089h, respectively). If the REQ/GNT pairs are configured to support a slave device on a secondary bus, the signals must be properly routed to the Intel MPIIX DMA controller, either through the docking station bridge chip or through the docking station connector. ring indicate When a 16-bit I/O PC Card is inserted into a socket, the PCI1031 can be configured to allow a ring detect signal to be passed from the PC Card to the system on the IRQ15/RI_OUT pin. This is accomplished by first enabling the RI_OUT function on IRQ15 by setting bit 7 of the card control register (see card control register) of the TI extension registers. Next, bit 7 of the ExCA interrupt and general control register (see ExCA interrupt and general control register) of the ExCA registers must be set to enable the RI input for the 16-bit I/O PC Card to support the RI function. When RI sees a low, it is passed through to the IRQ15/RI_OUT (see Figure 6). The status of the RI input is reflected in bit 0 of the card status-change register (see ExCA card status-change register) of the ExCA registers.

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Figure 6. Ring Indicate Enabled on PCI1031 supported by setting bit 6 of the card control register (see card control register) in the TI extension registers. still be used by the PCI1031 to access PC Card CIS registers for PC Card configuration (see Figure 7). Figure 7. Zoom-Video Implementation on the PCI1031

PCI-TO-PC CARD16 CONTROLLER UNIT SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997 33POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 power management The PCI1031 provides four methods of power management. These methods relate to the primary bus (PCI) and the secondary bus. Managing the PCI clock is the main method of conserving power on the PCI1031. PCI power management The PCI clock run feature is the primary method of power management on the PCI bus side of the PCI1031. To enable the PCI1031 to fit into the suspend and resume schemes of all the various chipsets, the PCI1031 implements SUSPEND that allows RSTIN (PCIRST) to be asserted as the system resumes, while preserving the state of the PCI1031 internal registers. PCI clock run The PCI1031 supports the PCI clock run protocol as defined in the PCI mobile design guide revision 1.0. When the system’s central resource signals the system to stop the PCI clock by driving CLKRUN high, the PCI1031 either signals that it is acceptable to stop the PCI clock by not driving CLKRUN or signals to the system to keep the clock running by pulling CLKRUN low. The PCI1031 CLKRUN is multiplexed on the IRQ10 interrupt line. The PCI1031 clock run feature is enabled by setting bit 0 in the system control register, 80h (see system control register). Bit 0 enables/disables the PCI clock run functionality of the multiplexed pin IRQ10/CLKRUN. Bit 1 of the system control register allows software to enable the PCI1031 keep clock running mode to prevent the system from stopping the PCI clock. When bit 1 of the system control register is set, the PCI1031 signals back to the system to keep the PCI clock running (not stop the clock). Figure 8 shows a diagram of the PCI bus clock states and the logic level of CLKRUN for each state. The PCI1031 signals the system to restart the clock when one of the following events occurs: /C0068A card is inserted or removed. The PCI1031 signals to start the PCI clock and generates a card status-change interrupt on the CSC interrupt routing. /C0068A functional interrupt is generated by a PC Card. The PCI1031 signals to start the PCI clock and generates a functional interrupt on the appropriate routing. /C0068A ring indicate (RI) signal is detected by PC Card16. The PCI1031 signals to start the PCI clock and a ring indicate output (RI_OUT) signal is provided to the system.

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Figure 8. Clock Run and Bus States can be pulled high or SPKROUT can be activated. The default state for SUSPEND is active. resistor on the pin to pull the line high so that an erroneous suspend mode does not occur.

Figure 9. PCI Reset and Suspend Mode When a 16-bit legacy PC Card is inserted into a socket, there are two options for minimizing power consumption. is set, the outputs on the PC Card socket are placed in the high-impedance state. Bit 7 is software controlled. state. When there is any activity on the socket, the outputs are automatically enabled. RESET line inactive, while the COE bit puts the RESET line in the high-impedance state. architecture specification revision 1.0, which, in turn, are common to the PCI local bus specification revision 2.1. ID, BIST, header type, latency timer, cache line size, interrupt pin, and interrupt line registers. specific to CardBus memory windows.

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configuration space, which locates a 4K-byte nonprefetchable memory window in PCI memory address space. has a separate CardBus socket register/ExCA registers base address register for accessing the ExCA registers. index of the desired ExCA register to the index register, and read or write the desired data to the data register. program nonoverlapping memory and I/O resources for each socket. Table 11. TI Extension Registers common to PCI functions 0 and 1. distributed DMA for a complete discussion of DMA support on the PCI1031.

Host software must program the PCI1031 socket DMA registers 0 and 1 to set up the socket for DMA transfers. interface and the PCI interface. The PCI1031 configuration header is shown in Table 12. Table 12. PCI1031 Configuration Header † One or more bits in the register are common to PCI functions 0 and 1. ‡ Unused registers are read only.

PCI-TO-PC CARD16 CONTROLLER UNIT SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

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Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name PCI vendor ID Type R R R R R R R R R R R R R R R R Default 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0 Register: PCI vendor ID Type: Read only Offset: 00h Default: 104Ch Description: This 16-bit value is allocated by the PCI special interest group (SIG) and identifies TI as the manufacturer of this device. The vendor ID assigned to TI is 104Ch. PCI device ID register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name PCI device ID Type R R R R R R R R R R R R R R R R Default 1 0 1 0 1 1 0 0 0 0 0 1 0 0 1 1 Register: PCI device ID Type: Read only Offset: 02h Default: AC13h Description: This 16-bit value is allocated by the vendor. The device ID for the PCI1031 is AC13h. PCI command register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name PCI command Type R R R R R R R R/W R R/W R R R R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: PCI command Type: Read only, read/write (see individual bit descriptions) Offset: 04h Default: 0000h Description: The PCI command register provides control over the PCI1031’s ability to generate and respond to PCI cycles. In its default state, or when 0000h is written, the PCI1031 can respond to PCI configuration cycles only; all other PCI functionality is disabled. The PCI1031 does not claim PCI cycles as a target, nor request access to the bus as an initiator in this state. Refer to Table 13 for a complete description of the register contents.

Table 13. PCI Command Register 15–10 R Reserved. Bits 15–10 are read only and return 0s when read. PCI1031 does not support fast back-to-back PCI cycles. Bit 9 is read only and returns 0s when read.

8 R/W

System error (SERR) enable. Bit 8 and bit 6 must be set for the PCI1031 to report address parity errors.

6 R/W

therefore, bit 4 is hardwired to 0. Bit 4 is read only and returns 0s when read. Writes to bit 4 have no effect.

2 R/W

1 R/W

Memory space control. Bit 1 controls whether or not a PCI device can claim cycles in PCI memory space. I/O space control. Bit 0 controls whether or not a PCI device can claim cycles in PCI I/O space. Table 14 for a complete description of the register contents.

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Table 14. PCI Status Register

15 R/W

0 = PCI1031 does not detect a parity error (default). 1 = PCI1031 detects a parity error.

14 R/W

0 = PCI1031 does not generate a system error on the SERR line (default). 1 = PCI1031 generates a system error on the SERR line.

13 R/W

0 = A bus initiator abort does not terminate a bus initiator’s transaction (default). 1 = A bus initiator abort terminates a bus initiator’s transaction.

12 R/W

Target abort status. A target abort terminates a PCI1031 bus master transaction. 0 = A target abort does not terminate a PCI1031 bus master transaction (default). 1 = A target abort terminates a bus master transaction.

11 R/W

Target abort status. The PCI1031 target abort terminates a bus master transaction. 0 = A PCI1031 target abort does not terminate a bus master transaction (default). 1 = A PCI1031 target abort terminates a bus master transaction. indicating a medium-speed device. 0 = No data parity errors occur (default). a. PERR is asserted by the bus initiator or the bus initiator observed PERR asserted. b. The agent that set the bit is the bus initiator during the transaction when the error occurred. c. Parity error response (bit 6 in the command register) is enabled. 7 R Fast back-to-back capable. The PCI1031 cannot accept fast back-to-back transactions; therefore, bit 7 is hardwired to 0. 6 R User-definable feature (UDF) support. The PCI1031 does not support the UDF option; therefore, bit 6 is hardwired to 0. 5 R 66 MHz capable. The PCI1031 operates at a maximum frequency of 33 MHz; therefore, bit 5 is hardwired to 0. 4–0 R Reserved. Bits 4–0 are read only alnd return 0s when read. Writes have no effect. Description: The PCI revision ID register is selected by TI and indicates the silicon revision.

PCI-TO-PC CARD16 CONTROLLER UNIT SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997 41POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI class code register Bit 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name PCI class code Byte Base Class Sub class Programming Interface Type R R R R R R R R R R R R R R R R R R R R R R R R Default 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 Register: PCI class code Type: Read only Offset: 09h Default: 060500h Description: The PCI class code indicates that the PCI1031 is a bridge device (06h), a PCMCIA bridge (05h), with 00h programming interface. cache line size register Bit 7 6 5 4 3 2 1 0 Name Cache line size Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register: Cache line size Type: Read/write, nonfunctional Offset: 0Ch Default: 00h Description: This register is nonfunctional. PCI latency timer register Bit 7 6 5 4 3 2 1 0 Name PCI latency timer Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 register: pci latency timer Type: Read/write, nonfunctional Offset: 0Dh Default: 00h Description: This register is nonfunctional. PCI header-type register Bit 7 6 5 4 3 2 1 0 Name PCI header type Type R R R R R R R R Default 1 0 0 0 0 0 1 0 Register: PCI header type Type: Read only Offset: 0Eh Default: 82h Description: The PCI header type register indicates that the PCI1031 uses a CardBus bridge configuration header. It also identifies the PCI1031 as a multifunction device.

PCI-TO-PC CARD16 CONTROLLER UNIT SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

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Register: BIST Type: Read only Offset: 0Fh Default: 00h Description: The PCI1031 does not support built-in self test (BIST); therefore, this register is considered reserved. The BIST register is read only and returns 0s when read. Writes to this register have no effect. CardBus socket registers/ExCA base-address register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name CardBus socket registers/ExCA base-address register Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name CardBus socket registers/ExCA base-address register Type R/W R/W R/W R/W R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: CardBus socket registers/ExCA base-address register Type: Read only, read/write Offset: 10h Default: 0000 0000h Description: This register points to the nonprefetchable memory window where the PCI1031 maps both the CardBus socket registers and the ExCA registers. The register is separated into two fields. Bits 31–12 are read/write and allow the CardBus socket registers/ExCA registers to be located anywhere in the 32-bit PCI I/O address space on 4K-byte boundaries. Bits 11–0 are read only and are hardwired to 0 to indicate that this register represents a memory base address. When software writes a value of all 1s to this register, the value read back is FFFF F000h, indicating that at least 4K bytes of memory address space are required. NOTE: ExCA status and control registers start at offset 000h and the 16-bit card registers begin at offset 800h. secondary status register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Secondary status Type R/W R/W R/W R/W R/W R R R/W R R R R R R R R Default 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 Register: Secondary status Type: Read only, read/write, not used Offset: 16h Default: 0200h Description: This register is read only and is not used. Reads return 0s, writes have no effect.

PCI-TO-PC CARD16 CONTROLLER UNIT SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997 43POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PCI bus number register Bit 7 6 5 4 3 2 1 0 Name PCI bus number Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register: PCI bus number Type: Read/write, nonfunctional Offset: 18h Default: 00h Description: This register is nonfunctional. CardBus bus number register Bit 7 6 5 4 3 2 1 0 Name CardBus bus number Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register: CardBus bus number Type: Read/write, nonfunctional Offset: 19h Default: 00h Description: This register is nonfunctional. subordinate bus number register Bit 7 6 5 4 3 2 1 0 Name Subordinate bus number Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register: Subordinate bus number Type: Read/write, nonfunctional Offset: 1Ah Default: 00h Description: This register is nonfunctional. CardBus latency timer register Bit 7 6 5 4 3 2 1 0 Name CardBus latency timer Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register: CardBus latency timer Type: Read/write, nonfunctional Offset: 1Bh Default: 00h Description: This register is nonfunctional.

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memory base registers 0, 1 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Memory base registers 0, 1 Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Memory base registers 0, 1 Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Memory base registers 0, 1 Type: Read only, nonfunctional Offset: 1Ch, 24h Default: 0000 0000h Description: The memory base registers are nonfunctional. memory limit registers 0, 1 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Memory limit registers 0, 1 Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Memory limit registers 0, 1 Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Memory limit registers 0, 1 Type: Read only Offset: 20h, 28h Default: 0000 0000h Description: The memory limit registers are nonfunctional. I/O base registers 0, 1 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name I/O base registers 0, 1 Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name I/O base registers 0, 1 Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: I/O base registers 0, 1 Type: Read only Offset: 2Ch, 34h Default: 0000 0000h Description: This register is not used.

PCI-TO-PC CARD16 CONTROLLER UNIT SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997 45POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 I/O limit registers 0, 1 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name I/O limit registers 0, 1 Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name I/O limit registers 0, 1 Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: I/O limit registers 0, 1 Type: Read only Offset: 30h, 38h Default: 0000 0000h Description: This register is not used. interrupt line register Bit 7 6 5 4 3 2 1 0 Name Interrupt line Type R/W R/W R/W R/W R/W R/W R/W R/W Default 1 1 1 1 1 1 1 1 Register: Interrupt line Type: Read/write Offset: 3Ch Default: FFh Description: The contents of this register default to the FFh (the unknown condition). interrupt pin register Bit 7 6 5 4 3 2 1 0 Name Interrupt pin Type R R R R R R R R Function 0 (socket A) default 0 0 0 0 0 0 0 1 Function 1 (socket B) default 0 0 0 0 0 0 1 0 Register: Interrupt pin Type: Read only Offset: 3Dh Default: 01h for function 0 (socket A) and 02h for function 1 (socket B) Description: This register is hardwired and writes to the register have no effect. The return values for the register are 01h for function 0 (socket A) and 02h for function 1 (socket B).

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complete description of the register contents. Table 15. Bridge Control Register 15–11 R Reserved. Bits 15–11 are read only and return 0s when read. Writes have no effect.

10 R/W

0 = Write posting is disabled (default). 1 = Write posting is enabled.

9 R/W Memory window 1 type (nonfunctional)

8 R/W Memory window 0 type (nonfunctional)

7 R/W

0 = Functional interrupts are routed to PCI interrupts (default). 1 = Functional interrupts are routed by ExCA registers.

6 R/W CardBus reset (nonfunctional)

5 R/W

4 R Reserved. Bit 4 is read only and returns 0, when read. Writes have no effect.

3 R/W

0 = Normal operation. Accesses to VGA addresses are forwarded (default). 1 = Accesses to VGA addresses are not forwarded. 2 R/W Reserved. Bit 2 is nonfunctional.

1 R/W SERR enable (nonfunctional)

0 R/W Parity error response enable (nonfunctional)

PCI-TO-PC CARD16 CONTROLLER UNIT SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997 47POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 subsystem vendor ID register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Subsystem vendor ID Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Subsystem vendor ID Type: Read/write Offset: 40h Default: 0000h Description: This register is read/write. subsystem ID register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Subsystem ID Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Subsystem ID Type: Read/write Offset: 42h Default: 0000h Description: This register is read/write. PC Card 16-bit I/F legacy-mode base address register Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name PC Card 16-bit I/F legacy-mode base address Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name PC Card 16-bit I/F legacy-mode base address Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Register: PC Card 16-bit I/F legacy-mode base address Type: Read only, read/write Offset: 44h Default: 0000 0001h Description: The PCI1031 supports the index/data scheme of accessing the ExCA registers through the use of the PC Card 16-bit I/F legacy-mode base-address register. An address written to this register becomes the address for the index register and the address+1 becomes the address for the data address. Using this access method, applications requiring index/data type ExCA access can be supported.

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the PCI1031. Refer to Table 16 for a complete description of the register contents. Table 16. System Control Register 31–27 R Reserved. Bits 31–27 are read only and return 0s when read.

26 R/W

0 = SMI interrupts are routed to IRQ2 (default). 1 = A card status-change interrupt is generated while the SMI interrupt bit is a 1.

25 R/W

0 = SMI interrupts are not active (default). 1 = SMI interrupts are active.

24 R/W

SMI interrupt mode enable. When enabled, SMI interrupts are generated when a write to the socket power control occurs. 0 = SMI interrupts are disabled (default). 1 = SMI interrupts are enabled. 23–22 R Reserved. Bits 23–22 are read only and return 0s when read.

21 R/W

0 = VCC protection for 16-bit PC Cards is enabled (default). 1 = VCC protection and Bad VCC Req for 16-bit PC Cards is disabled.

20 R/W

0 = Reduced zoom video is disabled (default). 1 = Reduced zoom video is enabled.

19 R/W

0 = PC/PCI DMA is disabled (default).

4 PCI master; not used (default)

15–14 R Reserved. Bits 15–14 are read only and return 0s when read. Socket activity status bit. When set, bit 13 indicates that a 16-bit card has been accessed by the PCI interface or DMA.

Table 16. System Control Register (Continued) 12 R Reserved. Bit 12 is read only and returns 1 when read. 7–6 R Reserved. Bits 7–6 are read only and return 0s when read. Writes have no effect. 0 = ExCA identification and revision register are read/write. 1 = ExCA identification and revision register are read only (default).

4 R/W CardBus data parity SERR signaling enable bit (nonfunctional)

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Description: This register displays the retry expiration status. The flags are cleared by writing a 1 to the bit. description of the register contents. Table 17. Retry Status Register

6 R/W CardBus retry timeout counter enable (nonfunctional)

5 R/W CardBus B retry expired status (nonfunctional)

4 R/W CardBus master B retry expired status (nonfunctional)

3 R/W CardBus A retry expired status (nonfunctional)

2 R/W CardBus master A retry expired status (nonfunctional)

0 R/W This bit is nonfunctional. description of the register contents.

Table 18. Card Control Register

4 R/W

Functional interrupt routing enable. If bit 5 is enabled, bit 4 routes the IREQ from card A (B) to the PCI interrupt INTA (INTB). 2 R Reserved. Bit 2 is read only and returns 0 when read. SpeakerOut/suspend enable. When set, bit 1 enables SPKR on the PC Card and routes it to SPKROUT on the PCI bus. configuration spaces. Refer to Table 19 for a complete description of the register contents. When bit 5 is set, the PCI1031 will not allow you to program the dual-voltage socket to 5 V.

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Table 19. Device Control Register 7 R Reserved. Bit 7 is read only and returns 0s when read. Only write a value of 0b to bit 7. 4 R/W Reserved. Bit 4 defaults to a 1. Only write 1 to bit 4. 3 R/W Reserved. For internal TI test purposes only; bit 3 must always write a 0. 0 R Reserved. For internal TI test purposes only. Table 20. Test Register 7–5 R Reserved. Bit 7–5 are read only and return 0s when read. Writes have no effect. 4 R/W Reserved. Bit 4 is for internal TI use only. Host software must always write 0 to this bit. CAUTION: Unpredictable behavior can result from setting bit 4 to 1.

3 R/W CardBus read buffer depth (nonfunctional)

2 R/W CardBus write buffer depth (nonfunctional)

1 R/W PCI read buffer depth (nonfunctional)

0 R/W PCI write buffer depth (nonfunctional)

complete description of the register contents. Table 21. Socket DMA Register 0 31–2 R Reserved. Bits 31–2 are read only and return 0s when read. Only write 0s to these bits. Description: This register provides control over the DMA registers and the PCI portion of DMA transfers.

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Table 22. Socket DMA Register 1 31–16 R Reserved. Bits 31–16 are read only and return 0s when read. DMA base address. Locates the socket’s DMA registers in PCI I/O space. This field represents a 16-bit PCI I/O address. The upper 16 bits of the address are hardwired to 0 forcing this window to within the lower 64K bytes of I/O address space. 3 R Nonlegacy extended addressing. This is not supported on the PCI1031 and always returns a 0. ExCA registers run contiguously from offset 00h–3Fh for socket A and 40h–7Fh for socket B (see Figure 11). Table 23 identifies each ExCA register and its respective ExCA offset and PCI configuration header address. communicated serially to the host interrupt controller through a common, wired-OR terminal on the PCI1031. to host interrupts. This set of registers includes those registers at ExCA offsets 803h and 805h. programmed in the ExCA registers described in this section. I/O windows have byte granularity.

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Table 23. ExCA Registers

Table 23. ExCA Registers (Continued)

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This entire register is read only when bit 5 of the system control register is set (see Table 16). Table 24. ExCA Identification and Revision Register (Index 00h) PCI1031 supports both I/O and memory 16-bit PC Cards. 5–4 R/W Reserved. Bits 5–4 can be used for Intel 82365SL-DF emulation.

Table 25 for a complete description of the register contents. Table 25. ExCA Interface Status Register (Index 01h) 7 R Reserved. Bit 7 is read only and returns 0 when read. 0 = VCC and VPP to the socket is turned off (default). 1 = VCC and VPP to the socket is turned on. 0 = PC Card is not ready for a data transfer. 1 = PC Card is ready for a data transfer. 0 = WP signal is 0. PC Card is read/write. 1 = WP signal is 1. PC Card is read only. 0 = CD2 signal is 1. No PC Card is inserted. 1 = CD2 signal is 0. PC Card is inserted. 0 = CD1 signal is 1. No PC Card is inserted. 1 = CD1 signal is 0. PC Card is inserted. 10 = Battery is low; warning. interface. In this case, bits 1–0 directly reflect the current state of these card outputs.

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on the socket interface. Refer to Table 26 for a complete description of the register contents. Table 26. ExCA Power Control Register (Index 02h) 0 = 16-bit PC Card outputs are disabled (default). 1 = 16-bit PC Card outputs are enabled. 6–5 R Reserved. Bits 6–5 are read only and return 0s when read. 2 R Reserved. Bit 2 is read only and returns 0 when read. VPP. Bits 1–0 set the VPP level applied to the socket. Changes to this socket are relayed to the TPS2206 power switch.

card types. Refer to Table 27 for a complete description of the register contents. Table 27. ExCA Interrupt and General Control Register (Index 03h) 0 = Ring indicate is disabled (default). 1 = Ring indicate is enabled. 0 = RESET signal is asserted (default). 1 = RESET signal is deasserted. 0 = Memory PC Card is installed (default). 1 = I/O PC Card is installed. † Valid when the serialized interrupt scheme is selected in the TI extension registers. There is no dedicated pin for these interrupts.

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interrupt service routine also is responsible for resetting the bits in this register. the ExCA card status-change register are reset by writing a 1 to the respective bit locations. complete description of the register contents. Table 28. ExCA Card Status-Change Register (Index 04h) 7–4 R Reserved. Bits 7–4 are read only and return 0s when read. When a 16-bit I/O card is installed, bit 2 is always 0. When a 16-bit I/O card is installed, bit 1 is always 0.

Table 29. ExCA Card Status-Change Interrupt Configuration Register (Index 05h) Ready enable. Bit 2 enables/disables a low-to-high transition on the PC Card READY signal to generate a host interrupt. † Valid when the serialized interrupt scheme is selected in the TI extension registers. There is no dedicated pin for these interrupts.

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Table 30 for a complete description of the register contents. Table 30. ExCA Address Window Enable Register (Index 06h) 5 R Reserved. Bit 5 is read only and returns 0 when read. Writes have no effect.

cycle timing. Refer to Table 31 for a complete description of the register contents. Table 31. ExCA 0 = 16-bit cycles have standard length (default). 1 = 16-bit cycles are extended by one equivalent ISA wait state. 0 = 8-bit cycles have standard length (default). 1 = 8-bit cycles are reduced to equivalent of three ISA cycles. 0 = Window data width is determined by I/O window 1 data sizing bit, bit 4 (default). 1 = Window data width is determined by IOIS16. 0 = Window data width is 8 bits (default). 1 = Window data width is 16 bits. 0 = 16-bit cycles have standard length (default). 1 = 16-bit cycles are extended by one equivalent ISA wait state. 0 = 8-bit cycles have standard length (default). 1 = 8-bit cycles are reduced to equivalent of three ISA cycles. 0 = Window data width is determined by I/O window 0 data-sizing bit, bit 0 (default). 1 = Window data width is determined by IOIS16. 0 = Window data width is 8 bits (default). 1 = Window data width is 16 bits.

PCI-TO-PC CARD16 CONTROLLER UNIT SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

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ExCA I/O window 0 and 1 start-address low-byte register (index 08h, 0Ch) Register: ExCA I/O window 0 start-address low byte Offset: CardBus socket address + 808h; Card A ExCA offset 08h Card B ExCA offset 48h Register: ExCA I/O window 1 start-address low byte Offset: CardBus socket address + 80Ch; Card A ExCA offset 0Ch Card B ExCA offset 4Ch Type: Read/write Default: 00h Size: One byte Description: These registers contain the low byte of the 16-bit I/O window start address for I/O windows 0 and 1. The eight bits of these registers correspond to the lower eight bits of the start address. ExCA I/O window 0 and 1 start-address high-byte register (index 09h, 0Dh) Register: ExCA I/O window 0 start-address high byte Offset: CardBus socket address + 809h; Card A ExCA offset 09h Card B ExCA offset 49h Register: ExCA I/O window 1 start-address high byte Offset: CardBus socket address + 80Dh; Card A ExCA offset 0Dh Card B ExCA offset 4Dh Type: Read/write Default: 00h Size: One byte Description: These registers contain the high byte of the 16-bit I/O window start address for I/O windows 0 and 1. The eight bits of these registers correspond to the upper eight bits of the start address. ExCA I/O window 0 and 1 end-address low-byte register (index 0Ah, 0Eh) Register: ExCA I/O window 0 end-address low byte Offset: CardBus socket address + 80Ah; Card A ExCA offset 0Ah Card B ExCA offset 4Ah Register: ExCA I/O window 1 end-address low byte Offset: CardBus socket address + 80Eh; Card A ExCA offset 0Eh Card B ExCA offset 4Eh Type: Read/write Default: 00h Size: One byte Description: These registers contain the low byte of the 16-bit I/O window end address for I/O windows 0 and 1. The eight bits of these registers correspond to the lower eight bits of the end address. ExCA I/O window 0 and 1 end-address high-byte register (index 0Bh, 0Fh) Register: ExCA I/O window 0 end-address high byte Offset: CardBus socket address + 80Bh; Card A ExCA offset 0Bh Card B ExCA offset 4Bh Register: ExCA I/O window 1 end-address high byte Offset: CardBus socket address + 80Fh; Card A ExCA offset 0Fh Card B ExCA offset 4Fh Type: Read/write Default: 00h Size: One byte Description: These registers contain the high byte of the 16-bit I/O window end address for I/O windows 0 and 1. The eight bits of these registers correspond to the upper eight bits of the end address.

PCI-TO-PC CARD16 CONTROLLER UNIT SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997 67POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ExCA memory window 0–4 start-address low-byte register (index 10h, 18h, 20h, 28h, 30h) Register: ExCA memory window 0 start-address low byte Offset: CardBus socket address + 810h; Card A ExCA offset 10h Card B ExCA offset 50h Register: ExCA memory window 1 start-address low byte Offset: CardBus socket address + 818h; Card A ExCA offset 18h Card B ExCA offset 58h Register: ExCA memory window 2 start-address low byte Offset: CardBus socket address + 820h; Card A ExCA offset 20h Card B ExCA offset 60h Register: ExCA memory window 3 start-address low byte Offset: CardBus socket address + 828h; Card A ExCA offset 28h Card B ExCA offset 68h Register: ExCA memory window 4 start-address low byte Offset: CardBus socket address + 830h; Card A ExCA offset 30h Card B ExCA offset 70h Type: Read/write Default: 00h Size: One byte Description: These registers contain the low byte of the memory window start address for memory windows 0, 1, 2, 3, and 4. The eight bits of these registers correspond to bits A19–A12 of the start address. ExCA memory window 0–4 start-address high-byte register (index 11h, 19h, 21h, 29h, 31h) Register: ExCA memory window 0 start-address high byte Offset: CardBus socket address + 811h; Card A ExCA offset 11h Card B ExCA offset 51h Register: ExCA memory window 1 start-address high byte Offset: CardBus socket address + 819h; Card A ExCA offset 19h Card B ExCA offset 59h Register: ExCA memory window 2 start-address high byte Offset: CardBus socket address + 821h; Card A ExCA offset 21h Card B ExCA offset 61h Register: ExCA memory window 3 start-address high byte Offset: CardBus socket address + 829h; Card A ExCA offset 29h Card B ExCA offset 69h Register: ExCA memory window 4 start-address high byte Offset: CardBus socket address + 831h; Card A ExCA offset 31h Card B ExCA offset 71h Type: Read/write (see individual bit descriptions) Default: 00h Size: One byte Description: These registers contain the high byte of the memory window start address for memory windows 0, 1, 2, 3, and 4. In addition, the memory window data width and wait states are set in this register. Refer to Table 32 for a complete description of the register contents.

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Table 32. ExCA Memory Window Start-Address High-Byte Register (Index 11h, 19h, 21h, 29h, 31h) 0 = Window data width is 8 bits (default). 1 = Window data width is 16 bits. 0 = 8- and 16-bit cycles have standard length (default). 1 = 8-bit cycles are reduced to equivalent of three ISA cycles. 16-bit cycles are reduced to equivalent of two ISA cycles. 5–4 R/W Scratch pad bits. Bits 5–4 are read/write and have no effect on memory window operation. 3–0 R/W Start-address high-byte. Bits 3–0 represent the upper address bits A23–A20 of the memory window start address.

windows 0, 1, 2, 3, and 4. In addition, the memory window wait states are set in this register. Refer to Table 33 for a complete description of the register contents. Table 33. ExCA Memory Window End-Address High-Byte Register (Index 13h, 1Bh, 23h, 2Bh, 33h) of wait states added is equal to the binary value of these two bits. 5–4 R Reserved. Bits 5–4 are read only and return 0s when read. Writes have no effect. 3–0 R/W End-address high-byte. Bits 3–0 represent the upper address bits A23–A20 of the memory window end address.

PCI-TO-PC CARD16 CONTROLLER UNIT SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

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ExCA memory window 0–4 offset-address low-byte register (index 14h, 1Ch, 24h, 2Ch, 34h) Register: ExCA memory window 0 offset-address low byte Offset: CardBus socket address + 814h; Card A ExCA offset 14h Card B ExCA offset 54h Register: ExCA memory window 1 offset-address low byte Offset: CardBus socket address + 81Ch; Card A ExCA offset 1Ch Card B ExCA offset 5Ch Register: ExCA memory window 2 offset-address low byte Offset: CardBus socket address + 824h; Card A ExCA offset 24h Card B ExCA offset 64h Register: ExCA memory window 3 offset-address low byte Offset: CardBus socket address + 82Ch; Card A ExCA offset 2Ch Card B ExCA offset 6Ch Register: ExCA memory window 4 offset-address low byte Offset: CardBus socket address + 834h; Card A ExCA offset 34h Card B ExCA offset 74h Type: Read/write Default: 00h Size: One byte Description: These registers contain the low byte of the memory window offset address for memory windows 0, 1, 2, 3, and 4. The eight bits of these registers correspond to bits A19–A12 of the offset address. ExCA memory window 0–4 offset-address high-byte register (index 15h, 1Dh, 25h, 2Dh, 35h) Register: ExCA memory window 0 offset-address high byte Offset: CardBus socket address + 815h; Card A ExCA offset 15h Card B ExCA offset 55h Register: ExCA memory window 1 offset-address high byte Offset: CardBus socket address + 81Dh; Card A ExCA offset 1Dh Card B ExCA offset 5Dh Register: ExCA memory window 2 offset-address high byte Offset: CardBus socket address + 825h; Card A ExCA offset 25h Card B ExCA offset 65h Register: ExCA memory window 3 offset-address high byte Offset: CardBus socket address + 82Dh; Card A ExCA offset 2Dh Card B ExCA offset 6Dh Register: ExCA memory window 4 offset-address high byte Offset: CardBus socket address + 835h; Card A ExCA offset 35h Card B ExCA offset 75h Type: Read only, read/write (see individual bit descriptions) Default: 00h Size: One byte Description: These registers contain the high byte of the memory window offset address for memory windows 0, 1, 2, 3, and 4. In addition, the memory window write protection and common/attribute memory configurations are set in this register. Refer to Table 34 for a complete description of the register contents.

Table 34. ExCA Memory Window Offset-Address High-Byte Register (Index 15h, 1Dh, 25h, 2Dh, 35h) 0 = Write operations are allowed (default). 1 = Write operations are not allowed. 0 = Memory window is mapped to common memory (default). 1 = Memory window is mapped to attribute memory. 5–0 R/W Offset-address high-byte. Bits 5–0 represent the upper address bits A25–A20 of the memory window offset address. Description: These registers contain the low byte of the I/O window offset address for I/O windows 0 and 1.

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for a complete description of the register contents. Table 35. ExCA Card Detect and General Control Register (Index 16h, 56h) 3–2 R Reserved. Bits 3–2 are read only and return 0s when read. 0 R Reserved. Bit 0 is read only and returns 0 when read.

complete description of the register contents. Table 36. ExCA Global Control Register (Index 1Eh) 7–5 R Reserved. Bits 7–5 are read only and return 0s when read. 0 = Host interrupt is in edge mode (default). 1 = Host interrupt is in level mode. 0 = Host interrupt is in edge mode (default). 1 = Host interrupt is in level mode. 0 = Host interrupt is in edge mode (default). 1 = Host interrupt is in level mode. 0 = Power-down mode is disabled (default). 1 = Power-down mode is enabled.

PCI-TO-PC CARD16 CONTROLLER UNIT SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

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ExCA memory window 0 page register Bit 7 6 5 4 3 2 1 0 Name ExCA memory window 0 page Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register: ExCA memory window 0 page Type: Read/write Offset: CardBus socket address + 840h Default: 00h Description: The upper eight bits (upper byte) of a PCI memory address are compared to the contents of this register when decoding addresses for 16-bit memory windows 0. By programming this register to a value other than zero, host software can locate 16-bit memory windows in any one of 256 16M-byte regions in the 4G-byte PCI address space. The default register values (00h) locate 16-bit memory windows in the first 16M bytes of address space. ExCA memory window 1 page register Bit 7 6 5 4 3 2 1 0 Name ExCA memory window 1 page Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register: ExCA memory window 1 page Type: Read/write Offset: CardBus socket address + 841h Default: 00h Description: The upper eight bits (upper byte) of a PCI memory address are compared to the contents of this register when decoding addresses for 16-bit memory windows 1. By programming this register to a value other than zero, host software can locate 16-bit memory windows in any one of 256 16M-byte regions in the 4G-byte PCI address space. The default register values (00h) locate 16-bit memory windows in the first 16M bytes of address space. ExCA memory window 2 page register Bit 7 6 5 4 3 2 1 0 Name ExCA memory window 2 page Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register: ExCA memory window 2 page Type: Read/write Offset: CardBus socket address + 842h Default: 00h Description: The upper eight bits (upper byte) of a PCI memory address are compared to the contents of this register when decoding addresses for 16-bit memory windows 2. By programming this register to a value other than zero, host software can locate 16-bit memory windows in any one of 256 16M-byte regions in the 4G-byte PCI address space. The default register values (00h) locate 16-bit memory windows in the first 16M bytes of address space.

PCI-TO-PC CARD16 CONTROLLER UNIT SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997 75POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ExCA memory window 3 page register Bit 7 6 5 4 3 2 1 0 Name ExCA memory window 3 page Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register: ExCA memory window 3 page Type: Read/write Offset: CardBus socket address + 843h Default: 00h Description: The upper eight bits (upper byte) of a PCI memory address are compared to the contents of this register when decoding addresses for 16-bit memory windows 3. By programming this register to a value other than zero, host software can locate 16-bit memory windows in any one of 256 16M-byte regions in the 4G-byte PCI address space. The default register values (00h) locate 16-bit memory windows in the first 16M bytes of address space. ExCA memory window 4 page register Bit 7 6 5 4 3 2 1 0 Name ExCA memory window 4 page Type R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Register: ExCA memory window 4 page Type: Read/write Offset: CardBus socket address + 844h Default: 00h Description: The upper eight bits (upper byte) of a PCI memory address are compared to the contents of this register when decoding addresses for 16-bit memory windows 4. By programming this register to a value other than zero, host software can locate 16-bit memory windows in any one of 256 16M-byte regions in the 4G-byte PCI address space. The default register values (00h) locate 16-bit memory windows in the first 16M bytes of address space. CardBus socket registers The PCMCIA CardBus specification requires a CardBus socket controller to provide five 32-bit registers that report and control the socket-specific functions. The PCI1031 provides the CardBus socket base address register (see CardBus socket registers/ExCA registers base address register) to locate these CardBus socket registers in PCI memory address space. Each socket has a separate CardBus socket register/ExCA registers base address register for accessing the CardBus socket registers (see Figure 12). This base address register is located at offset 10h in the PCI1031 configuration space. Table 37 illustrates the location of the socket registers in relation to the CardBus socket base address. The test register (see test register) is an extended register that provides control and status information related to power management. This register is described in detail in test register.

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Table 37. CardBus Socket Registers Figure 12. CardBus Socket/ExCA PCI Memory Access Method

Table 38. Socket Event Register 31–4 R Reserved. Bits 31–4 are read only and return 0s when read. of the CSTSCHG signal. Bit 0 is reset by writing a 1.

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Table 39. Socket Mask Register 31–4 R Reserved. Bits 31–4 are read only and return 0s when read. PowerCycle. Bit 3 masks the PowerCycle bit in the socket’s socket-event register from causing a status change interrupt. 0 = PowerCycle event does not cause a status-change interrupt (default). 1 = PowerCycle event causes a status-change interrupt. 00 = Card insertion/removal events do not cause a status-change interrupt (default). 11 = Card insertion/removal events cause a status-change interrupt. CSTSCHG. When reset, bit 0 masks the CSTSCHG from the CardBus PC Card from causing a status-change interrupt. 0 = CSTSCHG event does not cause a status-change interrupt (default). 1 = CSTSCHG event causes a status-change interrupt.

this register. Refer to Table 40 for a complete description of the register contents. Table 40. Socket Present State Register Y.Y V VCC ; therefore, bit 31 is always reset unless overridden by the socket force event register. Bit 31 is hardwired to 0. X.X V VCC ; therefore, bit 30 is always reset unless overridden by the socket force event register. Bit 30 is hardwired to 0. 0 = Socket cannot supply VCC = 3.3 V. 1 = Socket can supply VCC = 3.3 V (default). 0 = Socket cannot supply VCC = 5.0 V. 1 = Socket can supply VCC = 5.0 V (default). 27–14 R Reserved. Bits 27–14 are read only and return 0s when read. Writes have no effect. 0 = PC Card does not function at VCC = Y.Y V (default). 1 = PC Card functions at VCC = Y.Y V. 0 = PC Card does not function at VCC = X.X V (default). 1 = PC Card functions at VCC = X.X V. 0 = PC Card does not function at VCC = 3.3 V (default). 1 = PC Card functions at VCC = 3.3 V.

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Table 40. Socket Present State Register (Continued) 0 = PC Card does not function at VCC = 5.0 V (default). 1 = PC Card functions at VCC = 5.0 V. 0 = READY(IREQ) is low (default). The READY signal applies to 16-bit memory PC Cards. IREQ applies to 16-bit I/O PC Cards only. 0 = Socket is powered down (default). 1 = Socket has successfully powered up. 0 = CCD2 is low; PC Card may be present. 1 = CCD2 is high; no PC Card is present (default). 0 = CCD1 is low; PC Card may be present. 1 = CCD1 is high; no PC Card is present (default). 0 = CSTSCHG is low (deasserted) (default). 1 = CSTSCHG is high (asserted).

When writing to this register, always write to the CVSTEST bit. Table 41. Socket Force Event Register 31–15 R Reserved. Bits 31–15 are read only and return 0s when read. state register, and reenables the socket power control. 9 W BadVccReq. Writes to bit 9 cause the BadVccReq bit in the socket present state register to be written. 8 W DataLost. Writes to bit 8 cause the DataLost bit in the socket present state register to be written. 7 W NotACard. Writes to bit 7 cause the NotACard bit in the socket present state register to be written. 6 R Reserved. Bit 6 is read only and returns 0 when read. if a card is present in the socket. ignored if a card is present in the socket. socket present state register is unaffected by writes to bit 3. register is unaffected by writes to bit 2. register is unaffected by writes to bit 1. socket present state register is unaffected by writes to bit 0.

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Table 42 for a complete description of the register contents. Table 42. Socket Control Register 31–8 R Reserved. Bits 31–8 are read only and return 0s when read.

7 R/W Stop clock (nonfunctional)

3 R Reserved. Bit 3 is read only and returns 0 when read.

to Table 43 for a complete description of the register contents. Table 43. Test Register 31–26 R Reserved. Bits 31–26 are read only and return 0s when read.

25 R Socket access status (nonfunctional)

24 R Socket mode status bit (nonfunctional)

23–17 R Reserved. Bits 23–17 are read only and return 0s when read.

16 R/W CardBus PC Card clock control enable bit (nonfunctional)

15–1 R Reserved. Bits 15–1 are read only and return 0s when read.

0 R/W CardBus PC Card clock control bit (nonfunctional)

Table 44 are implemented as read only, and return 0s when read. Writes to reserved registers have no effect.

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Table 44. DMA Registers this register indicate the current memory address of a DMA transfer. presented on AD23–AD16 of the PCI bus during the address phase. disabled, the upper eight bits of this register are reserved and behave as a reserved register. transfers. When nonlegacy addressing mode is enabled, the full 24-bit address range is used.

the command register contents. Table 45. DMA Status Register mask register has no effect on these bits. the DMA channel. Bits 3–0 are reset when read or when the DMA channel is reset.

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Table 46. DMA Command Register high; therefore, bit 7 is reserved. active low; therefore, bit 6 is reserved. REQ signal and is granted use of the PCI bus. defined. Therefore, bit 3 is reserved in the PCI1031. therefore, bit 0 is reserved in the PCI1031. software requests for DMA transfers. This register is used in block mode only.

Description: The DMA mode register. Refer to Table 47 for a complete description of the register contents. Table 47. DMA Mode Register such as the PCI1031 do not require bits 1–0.

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the entire DMA channel to the socket and resets all registers to their default condition. double word to prevent inadvertent reset. used to mask the DMA channel. The PCI1031 sets the mask bit when the PC Card is removed. description of the register contents. Table 48. DMA Multichannel Mask Register 7–1 R Reserved. Bits 7–1 are read only and return 0s when read. the card. When cleared (or when reset), incoming DREQ assertions are serviced normally.

PCI-TO-PC CARD16 CONTROLLER UNIT SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997 89POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 absolute maximum ratings over operating temperature ranges (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Applies to external input and bidirectional buffers. VI > VCC does not apply to fail-safe terminals. 2. Applies to external output and bidirectional buffers. VO > VCC does not apply to fail-safe terminals. recommended operating conditions MIN NOM MAX UNIT tt Input transition (rise and fall) time CMOS compatible 1 4 ns TA Operating ambient temperature Commercial 0 25 70 °C TJ‡ Virtual junction temperature Commercial 0 25 115 °C ‡ These junction temperatures reflect simulation conditions. The customer is responsible for verifying junction temperature. recommended operating conditions for PCI interface OPERATION MIN NOM MAX UNIT VCC Core voltage Commercial 3.3 V 3 3.3 3.6 V VCCP PCI supply voltage Commercial 3.3 V 3 3.3 3.6 VVCCP PCI supply voltage Commercial 5 V 4.75 5 5.25 V VI Input voltage

3.3 V 0 VCCP VVI Input voltage

5 V 0 VCCP

V V § Output voltage

3.3 V 0 VCCP VVO § O utput voltage 5 V 0 VCCP

V ¶ CMOS com patible 3.3 V 0.5 VCCP VIH¶ High-level input voltage CMOS compatible

5 V 2 VIH gg

Fail safe# 3.3 V ¶ CMOS compatible 3.3 V 0.3 VCCP VIL¶ Low-level input voltage CMOS compatible 5 V 0.8 V Fail safe# 3.3 V 0.3 VCC § Applies to external output buffers ¶ Applies to external input and bidirectional buffers without hysteresis # Fail-safe pins are 16, 56, 68, 72, 74, 82, 122, 134, 138, 140, 149, and 152.

PCI-TO-PC CARD16 CONTROLLER UNIT SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

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recommended operating conditions for PC Cards A and B and miscellaneous inputs and outputs OPERATION MIN NOM MAX UNIT VCC(A/B) PC Card supply voltage Commercial 3.3 V 3 3.3 3.6 VVCC(A/B) PC C ard supply voltage Commercial 5 V 4.75 5 5.25 V VI Input voltage

3.3 V 0 VCC(A/B) VVI In ut voltage

5 V 0 VCC(A/B)

V VO † Output voltage

3.3 V 0 VCC(A/B) VVO † Out ut voltage

V CMOS compatible 3.3 V 0.475 VCC(A/B)¶ VIH‡ High-level input voltage 5 V 2.4 V Fail safe§ 3.3 V 0.475 VCC(A/B)¶ CMOS compatible 3.3 V 0.325 VCC(A/B)¶ VIL‡ Low-level input voltage 5 V 0.8 V Fail safe§ 3.3 V 0.325 VCC(A/B)¶ † Applies to external output buffers ‡ Applies to external input and bidirectional buffers without hysteresis § Fail-safe pins are 16, 56, 68, 72, 74, 82, 122, 134, 138, 140, 149, and 152. ¶ Meets TTL levels, VIH MIN =1.65 V and VIL MAX = 0.99 V

PCI-TO-PC CARD16 CONTROLLER UNIT SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997 91POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER SIDE OPERATION TEST CONDITIONS MIN MAX UNIT PCI 3.3 V IOH = –0.5 mA 0.9 VCC PCI 5 V IOH = –2 mA 2.4 VOH High-level output voltage† PC Card 3.3 V IOH = –0.15 mA 0.9 VCC V PC C ard 5 V IOH = –0.15 mA 2.4 MISC ‡ IOH = –4 mA 2.1 PCI 3.3 V IOL = 1.5 mA 0.1 VCCPCI 5 V IOL = 6 mA 0.55 VOL Low level output voltage PC Card 3.3 V IOL = 0.7 mA 0.1 VCC VVOL Low-level output voltage PC C ard 5 V IOL = 0.7 mA 0.55 V MISC IOL = 4 mA 0.5 SERR IOL = 12 mA 0.5 Fail safe 3.6 V VI = VCC ¶ 10 Inputpins

3.6 V VI = VCC ¶ 10

IIH High level input current§ Input pins

5.25 V VI = VCC ¶ 20

mAIIH High-level input current§ I/Opins# 3.6 V VI = VCC ¶ 10 mA I/O pins#

5.25 V VI = VCC ¶ 25

DATA VI = VCCP 270 IIL Low level input current§ Input pins VI = GND –1 mAIIL Low-level input current§ I/O pins VI = GND –10 mA † VOH is not tested on SERR (pin 200) due to open-drain output. ‡ MISC pins are 150, 151, 156, 157, 159, 160, 161, 162, 163. § IIL is not tested on DATA (pin 152) due to internal pulldown resistor, and IIH is not tested on SPKROUT (pin 149) due to internal pullup resistor. ¶ For PCI and MISC pins, VCC = VCCP . For card A/B, VCC = VCCA /VCCB , respectively. # For I/O pins, the input leakage current includes the off-state output current IOZ .

PCI-TO-PC CARD16 CONTROLLER UNIT SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997

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PCI clock/reset timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Figure 14 and Figure 15) ALTERNATE SYMBOL MIN MAX UNIT tc Cycle time, PCLK tcyc 30 /C0049ns twH Pulse duration, PCLK high thigh 11 ns twL Pulse duration, PCLK low tlow 11 ns Dv/Dt Slew rate, PCLK tr, tf 1 4 V/ns tw Pulse duration, RSTIN trst 1 ms tsu Setup time, PCLK active at end of RSTIN trst-clk 100 /C0109s PCI timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Note 3, Figure 13, and Figure 16) ALTERNATE SYMBOL TEST CONDITIONS MIN MAX UNIT t d Propagation delay time PCLK to shared signal valid delay time tval C L =5 0pF See Note 4 nstpd Propagation delay time PCLK to shared signal invalid delay time tinv C L = 50 pF, See Note 4 ns ten Enable time, high-impedance-to-active delay time from PCLK ton 2 ns tdis Disable time, active-to-high-impedance delay time from PCLK toff 28 ns tsu Setup time before PCLK valid tsu 7 ns th Hold time after PCLK high th 0 ns NOTES: 3. This data sheet uses the following conventions to describe time (t) intervals. The format is: tA, where subscript A indicates the type of dynamic parameter being represented. One of the following is used: tpd = propagation delay time, td = delay time, tsu = setup time, and th = hold time. 4. PCI shared signals are AD31–AD0, C/BE3–C/BE0, FRAME , TRDY, IRDY, STOP, IDSEL, DEVSEL, and PAR.

† C LOAD includes the typical load-circuit distributed capacitance. following characteristics: PRR = 1 MHz, ZO = 50 W , tr ≤ 6 ns, tf ≤ 6 ns. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. For tPLZ and tPHZ , VOL and VOH are measured values. Figure 13. Load Circuit and Voltage Waveforms

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2 V MIN Peak to Peak

Figure 14. PCLK Timing Waveform Figure 15. RSTIN Timing Waveforms Figure 16. Shared Signals Timing Waveforms

the Intel 82365SL-DF values. This ensures compatibility with existing software and maximizes throughput. cycles and nanoseconds for I/O and memory cycles. Table 49. PC Card Address Setup Time, t Table 50. PC Card Command Active Time, tc(A), 8-Bit PCI Cycles

01 X 23/690

11 X 23/690

Table 51. PC Card Command Active Time, tc(A), 16-Bit PCI Cycles

01 X 13/390

11 X 23/630

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Table 52. PC Card Address Hold Time, th(A), 8-Bit and 16-Bit PCI Cycles observed if programmed for zero wait state, 16-bit cycles) with a 33-MHz PCI clock.

Figure 17. PC Card Memory Cycle

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Figure 18. PC Card I/O Cycle Figure 19. Miscellaneous PC Card Delay Times

PCI-TO-PC CARD16 CONTROLLER UNIT SCPS008B – FEBRUARY 1996 – REVISED DECEMBER 1997 99POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA PDV (S–TQFP–G208) THIN PLASTIC QUAD FLATPACK 0,13 NOM 105 104 0,27 0,17 0,25 0,45 0,75 0,05 MIN Seating Plane 4087729/C 10/97 157 208 156 SQ SQ 28,05 29,90 30,10 27,95 25,50 TYP 1,60 MAX 0,08 0,50 M0,08 0°–7° Gage Plane 1,35 1,45 NOTES: D. All linear dimensions are in millimeters. E. This drawing is subject to change without notice. F. Falls within JEDEC MS-126

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