PCBFA80C39

NXP Semiconductors

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER August 1990

Manufacturer: NXP Semiconductors

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PCB80C39 PHILIPS | Alldatasheet

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Features

© &bit CPU, ROM, RAM, I/O ina single 40-pin package © PCB80C49: 2K x 8 ROM, 128 x 8 RAM © Internal counter/timer @ Internal oscillator, clock driver © Single-level interrupts: external and counter/timer @ 17 internal registers: accumulator, 16 addressable registers © Over 90 instructions: 70% single byte © All instructions: 1 or 2 cycles @ Easily expandable memory and |/O @ TTL compatible inputs and outputs. ® Single 5 V supply © Wide frequency operating range @ Low current consumption © Available with extended temperature ranges: (PCB version) Oto + 70°C (PCF version) —40 to + 85 °C (PCA version) —40 to + 110 °C © Frequency range: 1 to 15 MHz for all temperature ranges

APPLICATIONS

© Peripheral interfaces and controllers © Test and measurement instruments © Sequencers © Audio/video systems © Environmental control systems © Modems and data enciphering PACKAGE OUTLINES PCB/F/A80C39/C49P: 40-lead DIL; plastic (SOT 129). PCB/F/A80C39/C49WP: 44-lead PLCC; plastic leaded chip carrier (SOT187AA). ) August 1990 255

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Single-chip 8-bit CMOS microcontroller PCB80C39 PCB80C49 wo] U Tad vec xratt [2] Eg xrac2 [3] [oa] P27 at [a] 726 Hoy os mt (| [a5] 2a (elf) 1 [7] 1 1 1 Ee A EA [aa] a7 % [a] pe NT Oo f32] 2a ca Py men [a] PIs 3} [38] Ps RO Wa {o] PCBB0C39 pa 2 a mn ace Ga] Po8H066 FE) ng EW Lol [33] rs oso [2] fog} pr pi rcasocae Ey oat [ia] fa] en te LR peeeocss Eo fe 3 <n i mo EB 3] é [a] Sons iF Ee] Vop 09° Ce] 32] pi Og os Zw [| [5] mos" a z cos OF ta] os | 2? Gel 30] P10 a DB3 [29] Yoo g D6 [za] p22 Fa So fl pa FAP AAPA Asse vss Be [2 P20 SERERERERERB Fig. 2(a) Pinning diagram, DIL; for pin Fig. 2(b) Pinning diagram, PLCC. designation see next page. Where: n.c, = not connected. August 1990 2-57

designation pin no. function 0B0-DB7 12-19 BUS. Bidirectional I/O port that can be read or written using the RD and WR strobes. This port can also be statically latched. Contains the 8 lower order address bits during external memory access and receives the addressed instruction under control of PSEN. PSEN, ALE, RD and WR determine whether the access is an instruction fetch or a read/write access to external RAM. P10-P17 27-34 Port 1. 8-bit quasi-bidirectional 1/0 port (note 1). P20-P27 21-24, Port 2. 8-bit quasi-bidirectional I/O port (note 1). P20-P23 35-38 contain the 4 higher order address bits during an access of external program memory. PROG 25 Output strobe (active LOW) for I/O expander. To 1 Input pin sensed using the JTO and JNTO instructions. Clock output pin when designated as such by the ENTO CLK instruction. TI 39 Input pin sensed using the JT1 and JNT1 instructions. Can be designated as the timer/counter input by the STRT CNT instruction. INT 6 Interrupt input pin. When LOW causes an interrupt in the current program if external interrupt is enabled. Can also be used as an input, testable using the JNI instruction. Interruot is disabled during and after a RESET. RESET 4 Reset input pin used to initialize the microcontroller. Active LOW. During program verification the address is latched by a ‘0’ to ‘1’ transition on RESET and the data at the addressed location is output on BUS (note 2). ALE " ‘Address latch enable. Occurs once each machine cycle and is useful for timing and sampling. During external program or data memory access, ALE is used to strobe the address information multiplexed ‘on the DBO to DB7 outputs. RD 8 Read BUS. Active LOW strobe used to gate data onto BUS lines when reading from an external source. WR 10 Write BUS. Active LOW strobe used to write data from BUS lines to an external designation. EA 7 External access input. When HIGH, forces instruction fetch from external memory. PSEN 9 Program store enable. Active LOW strobe that occurs only during a fetch from external program memory. 5s 5 Single step input. Active LOW which is used with ALE to cause the microcontroller to execute a single instruction. Vop 26 RAM power supply, + 5 V during normal operation and power-down mode.

258 August 1990 \\ {

Single-chip 8-bit CMOS microcontroller PCB80C39 PCB80C49 designation pin no. function ee XTAL1 2 One side of crystal (or inductor) input for internal oscillator. Can also be used as an input for an external timing source (note 2), XTAL2 3 Other side of crystal. XTAL2 must be driven with the inverted signal of XTAL 1 when an external timing source of 11 < fgg <16 MHz is used. Vss 20 Ground. Veco 40 Mains power supply, +5 V during normal operation. Notes 1, Each port line can be designated as an input or an output. A line is designated as an input by first writing a logic 1 to the line. RESET sets all lines to logic 1. 2. Non-standard TTL Vi}. FUNCTIONAL DESCRIPTION Program memory (see Fig. 3) The resident program memory is: 2048 byte ROM § The PCB80C39 has no resident program memory. The total addressing capability is 4096 bytes. @% The program memory address space is divided into two 2048-bytes banks MBO and MB1. = The program memory is also divided into pages of 256 bytes for conditional branches, & There are three locations in program memory of special importance. These locations contain the first & instruction to be executed after one of three events. @ The three locations and their contents are: © tecation 0 — activation, then deactivation of the RESET line, location 3 — activation of the INT line when the external interrupt is enabled, location 7 — an overflow of the timer/counter if the T/C interrupt is enabled. Data memory (see Fig. 4) The resident data memory is: 128 byte RAM. All locations are indirectly addressable by either of two RAM pointer registers at locations 0 and 1. The first eight locations of RAM (0 to 7) are designated as working registers and are directly addressable by several instructions, By selecting register bank 1, RAM locations 24 to 31 become the working registers, replacing those in register bank 0 (0 to 7). RAM locations 8 to 23 are designated as the stack. Two locations (bytes) are used per CALL, allowing up to eight levels of subroutine nesting. Hf additional RAM is required, up to 256 bytes may be added and addressed directly using the MOVX instructions. If more RAM is required, an 1/O port can be used to select one (256 byte) bank of external memory at a time. TS August 1990 2.59

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Single-chip 8-bit CMOS microcontroller PCB80C39 PCB80C49 Program counter and stack The program counter (PC) is a 12-bit counter/register that points to the location from which the next instruction is to be fetched. When EA is ‘0’, the PC addresses an internal program memory. At the boundary of the internal program memory an automatic switch over to external memory is made. When EA is '1”, all the program is fetched from external ROM/EPROM. The total address space is 4K bytes. An interrupt or CALL to a subroutine causes the contents of the Program counter to be stored in one of the 8 register pairs of the program counter stack. The pair to be used is determined by a 3-bit stack pointer which is part of the program status word (PSW). Data RAM locations 8 to 23 are available as stack registers and are used to store the program counter and 4 bits of PSW. The stack pointer, when initialized to 000B, points to RAM locations 8 and 9. The first subroutine jump or interrupt results in the program counter contents being transferred to locations 8 and 9 of the RAM array. The stack Pointer is then incremented by one to point to locations 10 and 11 in anticipation of another CALL. Nesting of subroutines within subroutines can continue up to 8 times without overflowing the stack. If overflow does occur the deepest address stored (location 8 and 9) will be overwritten and lost since the stack pointer overflows from 111 to 000, It also underflows from 000 to 111, The end of a subroutine, which is signalled by a return instruction (RET or RETR), causes the stack pointer to be decremented and the contents of the resulting register pair to be transferred to the Program counter. Oscillator and clock << The PCB80C49 contains its own internal oscillator and clock driver. &__ Acrystal, inductor or external pulse generator determines the oscillator frequency (see Figs 5, 6 and 7).

2 The output of the oscillator is divided-by-three and is available at TO (pin 1) by executing the ENTO

CLK instruction. This CLK signal is divided-by-five to define a machine (instruction) cycle. It is i available at ALE (pin 11). a co} S ry Locmos eo cate Fa Heme, rans] a For quartz crystal \\ OP rane 1 to 18 MHz: C1 = C2=15 to 25 pF XTAL2 Hi 3 For ceramic resonators 3 c2 1 to 16 MHz: C1=C2=30°° pF 7209666. =10 7209664.2 (1) Including crystal-socket stray capacitance. Fig. 6 Driving from an external source. Fig. 5 Crystal oscillator mode. Typical values Test conditions at XTAL 1; are given, Crystal serial impedance should be Minimum HIGH (> 0,7 of Vec) and LOW <75 Q at 6 MHz and < 180 9 at 3,6 MHz. (< 0,13 of Vcc) times, should be at least 45% of a clock period, XTAL2 must be driven with the inverted signal of XTAL1 when an external timing source of 11 < foge < 15 MHz is used. AA, L(uH) | C(PF) | from c (MHz) He c 45 | 20 5,2 MTA 120 | 20 3,2 72047981 Fig. 7 LC oscillator mode. { August 1990 2-61

FUNCTIONAL DESCRIPTION (continued) Timer/event counter An internal counter is available which can count either external events or machine cycles (+ 32). The machine cycles are divided-by-32 before they are applied to the input of the 8-bit counter. External events are applied directly to the input of the counter. The maximum frequency that can be counted is one third of the machine cycle frequency. The minimum positive duty cycle that can be detected is 0,2 times the cycle period. The counter is under program control and can be made to generate an interrupt to the processor when it overflows, Interrupt An interrupt may be generated by either an external input (INT, pin 6) or the overflow of the internal timer/event counter, when enabled. In either case, the processor completes execution of the present instruction and then does a CALL to the interrupt service routine, After service, a RETR instruction restores the machine to the state it was prior to the interrupt. The external interrupt has priority over the internal interrupt. Input/output The PCB80CXX family has 27 1/O lines. These lines are arranged as three 8-line ports, which serve individually as either inputs, outputs or together as bidirectional ports, plus 3 ‘test’ inputs which can alter program sequences when tested by conditional jump instructions. Ports 1 and 2 Ports 1 and 2 are each 8-bits wide and have identical characteristics. Data written to these ports is statically latched and remains unchanged until rewritten. As input ports these lines are non-latching, e.g., inputs must be present until read by an input instruction. Inputs are fully TTL compatible and outputs will drive one standard TTL load. The lines of ports 1 and 2 are called quasi-bidirectional because of a special output circuit structure which allows each line to serve as an input, an output, or both even though outputs are statically latched. The circuit configuration is shown in Fig. 8. Each line has a unique high-impedance pull-up transistor TR3, this is turned on when the tine is pulled above 2 V by an external source or by writing a logic 1 to the port. This pull-up is sufficient to provide the source current for a TTL HIGH level, yet can be pulled LOW by a standard TTL gate, thus allowing the same pin to used for both input and output, When a logic 1 is written to a line, a second high impedance transistor TR2, pulls the line up to 5 V. To provide fast switching during a ‘0’ to ‘1’ transition, a relatively low-impedance transistor TR1 (approx. 750 $2) is switched on for 1/5 of a machine cycle whenever a ‘1’ is written to the line, Whenever a ‘0’ is written to the line, a low-impedance (approx. 250 2) transistor TR4, overcomes the weak light pull-up and provides TTL current sinking capability. Since the pull-down transistor TR4 is a low-impedance device, a ‘1’ must first be written to any line which is to be used as an input. RESET initializes all lines to the high impedance ‘1’ state. This structure allows input and output on the same pin and also allows a mixture of input lines and output lines on the same port. The quasi-bidirectional port in combination with the ANL and ORL logical instructions provide an efficient means for handling single line inputs and outputs within an 8-bit processor. 2-62 August 1990

Single-chip 8-bit CMOS microcontroller PCB80C39 PCB80C49 BUS BUS is a true bidirectional 8-bit port with associated input and output strobes, The BUS port can Operate in three different modes: as a latched 1/0 port, as a bidirectional bus port, or in an expanded system as a program memory address output port. If the bidirectional feature is not needed, BUS can serve as either a statically latched output port or non-latching input Port. Input and output lines on this Port cannot be mixed. The BUS port lines are either active HIGH, active LOW, or high impedance (floating). Asa static port, data is written and latched using the OUTL instruction and input using the INS in- struction. The INS and OUTL instructions generate pulses on the corresponding AD and WR output strobe lines; however, in the static port mode they are generally not used. As a bidirectional port, the MOVX instructions are used to read and write the port. A write to the port generates a pulse on the WR output line and output data is valid at the trailing edge of WR. A read of the port generates a pulse on the RD output line and input data must be valid at the trailing edge of AD. The latched mode (INS, OUTL) is intended for use in the single-chip configuration, where BUS is not being used as an expanded port. OUTL and MOVX instructions can be mixed if required. However, when using a MOVX instruction a previously latched output will be lost and BUS will be left in the high impedance state. INS does not put the BUS in a high impedance state. Therefore, in order to read an external byte (and not the previously latched value) using the INS instruction, it is necessary to follow an OUTL with a MOVX instruction to place BUS in a high impedance state. __ QUTL should never be used in a system with external program memory, since latching BUS may cause b3 the next instruction to be incorrectly fetched. a

5 Test (TO, T1) and INT inputs

= Three pins serve as inputs and are testable with the conditional jump instruction, These pins are TO, T1, S and INT and they allow inputs to cause program branches without the necessity to load an input port a7 __ into the accumulator. The TO, T1 and INT pins have other possible functions as well, a a ORL, ANL — vy aay weak pull-up cuk ° rR2 P 1/0 PIN = TR PORT q a 1a2 pulse input BUFFER rae8es1.4 Fig. 8 Quasi-bidirectional port structure. ) August 1990 263

FUNCTIONAL DESCRIPTION (continued) RESET input (see Fig. 10) ‘The RESET input provides a means to initialize the processor. This Schmitt-trigger input has an internal pull-up resistor. The combination of an external 47 kS resistor and a 1 uF capacitor provides a reset pulse of sufficient duration to guarantee that all circuitry is reset. If the reset pulse is generated otherwise, the RESET pin must be held at ground for at least 10 ms after the (0,13 Vcc) power supply is within tolerance, Only five machine cycles (2,5 us at 6 MHz) are required if power is already on and the oscillator has stabilized. Single step input (5S) Under control of the $5 line, the processor can be forced to execute one instruction and then towait until the single step switch is activated again. IDLE mode The PCB80CXX family is provided with a IDLE mode in which the internal oscillator, the internal timer and the external interrupt and counter are still functioning, while the status of following parts is maintained: RAM and register/Port 1 and 2/Bus. The IDLE mode is entered after execution of the IDLE instruction (opcode 1H). The IDLE mode is terminated by one of the two possible interrupts, if enabled, or a RESET signal. If an external interrupt terminates the IDLE mode, the next instruction that is executed is at location 3 of the program store, If a timer/counter interrupt terminates the IDLE mode, the next instruction is at location 7. The reset signal will terminate the IDLE mode, and also initialize the processor. Power-down mode In the PCBSOCXX family, power can be removed from all but the 64 x 8 bit and 128 x 8 bit data RAM array, for low power standby operation. In the power-down mode the contents of the data RAM are maintained. Vcc serves as the + 5 V supply pin for most of the circuitry, while the Vp pin supplies only the RAM array, In normal operation, both pins are at + 5 V. In standby, Vcc is at ground and Vpp is maintained at + 5 V. Applying RESET to the processor through the RESET pin inhibits any access to the RAM by the processor and guarantees that the RAM cannot be inadvertently altered when power is removed from Vec. Fig. 9 shows a typical power-down sequence. POWER (Vcc) processor \\ suppLy Vcc) tr oted I fl PoweR / an SUPPLY tou FAIL SIGNAL [LL_f_-__ normal power-on ‘ rot Sequence follows ESET | H : r a a deta save access to contina | | data RAM inhibit Set up time Data RAM inhibit for 7 clock periods 7287291.1 Fig. 9 Power-down sequence.

2.64 August 1990

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The PCB80CXX instruction set consists of over 90 one and two-byte instructions (see Table 2). Program code efficiency is high because: © working registers and program variables are stored in the RAM, which require only a single byte to address, © program memory is divided into pages of 256 bytes, which means that branch destination addresses require one byte. In addition to performing logical and arithmetic operations, the instruction set manipulates and tests both bits and bytes. A set of MOVE instructions operates indirectly upon either RAM or ROM, which permits efficient access of pointers and data tables. The indirect jump instruction performs a multi-way branch (up to 256) upon the content of the accumulator to addresses stored in a look-up table, The ‘decrement register and jump if not zero’ DJNZ instruction saves a byte every time it is used as opposed to using separate increment and test instructions. The on-chip counter enables either external events or time to be counted off-line from the main program. The PCB80CXX can either test the counter (under program control) or cause its overflow to generate an interrupt. These features are required for real-time applications. Instruction timing is shown in Table 3. Note: The OUTL, ANL and ORL instructions relating to BUS, are used with internal program memory only. 2-66 August 1990 {

Single-chip 8-bit CMOS microcontroller PCB80C39 PCB80C49 Table 1 Symbol definitions used in Table 2. symbol description A the accumulator AC the auxiliary carry flag addr program memory address (11-bits) Bb bit designation (b = 0-7) Bs the bank switch c carry flag CLK clock signal CNT event counter D nibble designation (4-bits) DBF program memory bank flip-flop data number or expression (8-bits) FO, F1 flags O and 1 i interrupt INT external interrupt P ‘in-page’ operation designation < Pp port designation (p = 1, 2 or 4~7) & Psw program status word e Rr register designation (r = 0, 1 or 0-7) Zz SP stack pointer s T timer 5 oF timer flag a 0,71 test 0 and 1 inputs S # immediate data prefix ue indirect address prefix $ current value of program counter + is replaced by o is exchanged with Notes to Table 2. 1. Instruction code designations r and p form the binary representation of the registers and ports involved. 2. The dot under the appropriate flag bit indicates that its content is subject to change by the instruction it appears in. 3. Numerical subscripts appearing in the FUNCTION column reference the specific bits affected. August 1990 2-67

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Single-chip 8-bit CMOS microcontroller PCB80C39 PCB80C49 RATINGS Limiting values in accordance with the Absolute Maximum System (IEC 134) Input, output current on any single pin lito - +10 mA Total power dissipation Prot - 05 w Storage temperature range Tstg 65 +150 °c Operating ambient temperature range PCB80C39/49 version Tamb 0 +70 °c PCF80C39/49 version Tamb —40 +85 °c PCA80C39/49 version Tamb —40 +110 | °C DC CHARACTERISTICS Vec = Vpp =5 V (+ 10%); Vsg = 0 V; Tamb = 0 to +70 °C (PCB80C39/49); —40 to +85 OC (PCF80C39/49); —40 to + 110 OC (PCAB0C39/49). All voltages with respect to Vgg unless otherwise specified. ‘ wn forse [ain m= [oe] é Supply voltage Voc = Vpp (note 2) Vec 45 155 v 5 | Supply current a operating foLk = 15 MHz lectIpp| — | 15 mA = IDLE mode feLk = 15 MHz NDLE - |6 mA S power down mode | Vop =2V:RESET=LOW | Ipp - |2 HA a a 2 | inputs Input voltage LOW all inputs except RESET; XTAL1; XTAL2 Vib -05| 018Vcc | Vv te 7e24016 tegetoa [TTT Ty (may ott Et YT BEBE 4a Ltt TT BEVanERED TA | lal eT | (1) Operational mode. =— Fig.13 Typical values of maximum supply ° 4 8 12 6 oscillator frequency (fogc) at Voc(max.) = tose (MHz) 5.5 V; Tamb = 0 to + 70°C. August 1990 279

DC CHARACTERISTICS (continued) Input voltage LOW RESET; XTAL1; XTAL2 Vint -0.5 0.13 Vcc | V Input voltage HIGH all inputs except RESET; XTAL1; XTAL2 (PCB80C39/49 version) Vink 04Vpp | Voc Vv (PCF/PCA80C39/49 version note 1) Vin 0.43 Vpp | Voc v Input voltage HIGH RESET; XTAL1; XTAL2 Vint 0.7Vpp | Vcc Vv Outputs Output voltage LOW BUS. lol =2mA VOL - 0.45 Vv Output voltage LOW RD; WR; PSEN; ALE | Io, = 1.8mA Vout - 0.45 v Output voltage LOW PROG lol =1mA Vor2 | - 0.45 v Output voltage LOW all other outputs loL= 1.6 mA VoLt3 | - 0.45 v Output voltage HIGH BUS —loH = 400 nA Vou 0.75 V¢c | - v Output voltage HIGH RD; WR; PSEN; ALE | —Iqy = 100 uA Vout | 0.75 Vcc | -— v Output voltage HIGH all other outputs —loH = 40 HA Vou2 | 0.75 Vec | - v Input leakage current INT; 11; EA without internal pull-up fu - 10 uA Vgs < Vi < Veco Input leakage current P10-P17; P20-P27; SS | with internal pull-up Nut = 500 uA (PCB80C39/49 version) Vg + 0.45 <V) <Vcoc PCF/PCA80C39/49 versions | —IjL1._ | — 600 BA Vsg + 0.45 <Vi< Voc 2-80 August 1990

Single-chip 8-bit CMOS microcontroller PCB80C39 PCB80C49 Input leakage current RESET (PCB80C39/49 version) “ltr | 20 | 300 | wA Vss < Vi < Vint (PCF /PCA80C39/49 version) Vsg < Vi <Vint -tir | 20 | 350 | uA Output leakage current BUS; TO at high impedance state Vgg+0.45 < Vi < Vcc tlo. | - 10 uA Notes to the DC characteristics 1. Levels are not fully compatible according to the TTL specification. 2. Note here that Vpp and Vg refer to pins 26 and 40, These pins are the RAM and processor power supplies respectively. t a Fd fo} g a Fe a | August 1990 281

Vec = Vpp = 5 V + 10%; Vgg = 0 V; Tamb (PCB version) = 0 to + 70 °C; note 1; Tamb (PCF version) = —40 to + 85 °C; note 1; Tamb (PCA version) = —40 to + 110 °C; note 1). See waveforms Figs 14, 15, 16, 17 and 18. parameter f (to) symbol 11. MHz unit (note 2) |_min. | max. | ALE pulse width 7/30tc¢_-170 tLe 150 - ns Address set-up time to ALE 2/15tg_-110 TAL 70 - ns Address hold time from ALE 1/15tg_—40 tla 50 - ns Control pulse width RD, WR 1/2te-200 tect 480 - ns Control pulse width PSEN 2/8t¢-200 tec2 350 - ns Data set-up time before WR 13/30tg-200 tow 390 - ns Data hold time after WR (note 3) 1/15tc_—-50 two 40 - ns Data hold time RD, PSEN 1/10tc_-30 tor t) 110 ns RD to data input 2/5tc¢_-170 tRp1 - 375 ns PSEN to data input 3/10tc_-170 tRp2 - 240 ns Address set-up time to WR 1/3t¢_—150 tAW 300 - ns Address set-up time_ ‘to data input (RD) 7/10tc_—250 taD1 - 730 ns Address set-up time __ to data input (PSEN) 1/2te_-220 tap2 - 460 ns Address floating to RD, WR 2/15tc_—40 taFci 140 - ns Address floating to PSEN 1/30tc_-40 taFc2 10 - ns ALE to control pulse RD, WR W/Stc_—75 tLAFCI 200 - ns ALE to control pulse PSEN 1/10te_-75 tLAFC2 60 - ns Control pulse to ALE RD, WR, PROG 1/15tc,-40 tcat 50 - ns Control pulse to ALE PSEN 4/15tc—40 toa2 320 - ns Port control set-up to PROG 1/10tc, 80 top 50 - ns 2-82 August 1990

Single-chip 8-bit CMOS microcontroller PCB80C39 PCB80C 49 AC CHARACTERISTICS (continued) Port control hold | to PROG 4/15tc,-260 tee 100 - ns PROG to time port 2 input must be valid 17/30t¢_—120 tpR - 650 ns Input data hold time from PROG 1/10teL | te lo 140 ns Output data set-up time 2/Stc¢,—-290 tpp | 250 - ns Output data hold time 1/10tg,-90 tep | 40 - ns PROG pulse width 7/10t¢_-250 tpp | 700 - ns Port 2 1/O data set-up time to ALE 4/15tc,—-200 tL 160 - ns Port 2 1/O data hold time to ALE 1/10tc,—-120 tp 15 - ns E Port output from ALE 3/10tg, +100 tpy - 510 ns OQ | Cycle time (fx TAL) x 15 tet | 1,36 15 us B | T0repetition rate 3/15teL toprR 270 - ns = Clock period (note 2) WfxTAL) tcy 90,9 1000 ns 5 | GZ Notes to AC characteristics @ 1. Control outputs: CL = 80 pF ° Bus outputs: C, = 150 pF. 2. f(t) assumes 50% duty cycle on XTAL1 and XTAL2; minimum frequency = 1 MHz; maximum frequency = 15 MHz for all versions. 3. Bus high-impedance load: 20 pF. tLaFci—| ALE j*——— tec tear tro 7287393 Fig.14 Read from external data memory August 1990 2.83

| —— toy wpe tear! wa I~ two >) tow + \\-—— taw 7207394 Fig.15 Write to external data memory. tey <> 5 1, ——+ J-— tLarc2—e| ALE l-—- tec2 — >| tca2 |e PSEN ae tla tor tal le oR |< tap2 Fig.16 Instruction fetch from external program memory. ALE toate) le tal A eg al PE tp) ‘ top EXPANDER PORT X)Procram counter wich |Xez0t0F23 oaTAYPonT contro) oureutoata _\\\\ ouTrut et [+ pk ——> EXPANDER PORT X) PROGRAM COUNTER HIGH [Xe2orraaoataXrontconrnonX KART) INPUT >| tec Le ool toe be <———- pp PROG | 7287998.2 Fig.17 Port 2 timing. 2-84 August 1990

Single-chip 8-bit CMOS microcontroller PCB80C39 PCB80C49 Fy g < fa a| |g g = s 2 Es < 2 Fy x a £ 5 8 2 5 we ES o a a t 2 a z & a = 2 g} |& 8] [8 3 8 z © 2 A F3 Es 3 nr cee August 1990 2-85

Product Information

PCBFA80C39 specifications and overview.

Summary

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER August 1990

Description

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER August 1990

Source title PCBFA80C39 Datasheet(PDF) - NXP Semiconductors

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