PCB9288

AD9288BSTZ-80 AD | Alldatasheet

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Technical content

8-Bit, 40/80/100 MSPS Dual A/D Converter AD9288 Rev. C Information furn ished by An alog D evices is believed to be accurate and reliable. However, n o resp onsibility is assume d b y A nalog De vices fo r its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or p atent rights of Analog De vices. Trademarks an d registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.

FEATURES

Dual 8-bit, 40 MSPS, 80 MSPS, and 100 MSPS ADC Low power: 90 mW at 100 MSPS per channel On-chip reference and track-and-hold

475 MHz analog bandwidth each channel

SNR = 47 dB @ 41 MHz

1 V p-p analog input range each channel

Single 3.0 V supply operation (2.7 V to 3.6 V) Standby mode for single-channel operation Twos complement or offset binary output mode Output data alignment mode Pin-compatible 10-bit upgrade available

APPLICATIONS

Battery-powered instruments Hand-held scopemeters Low cost digital oscilloscopes I and Q communications FUNCTIONAL BLOCK DIAGRAM 00585-001 AD9288 T/H REF T/H ADC OUTPUT REGISTER 8 8 8 8 OUTPUT REGISTER TIMING TIMING VDD SELECT 1 SELECT 2 DATA FORMAT SELECT D7B–D0B D7A–D0A VDDGNDVD ENCA ENCB AINA AINA AINB AINB REFINA REFOUT REFINB ADC Figure 1. GENERAL DESCRIPTION The AD9288 is a dual 8-bit monolithic sampling analog-to- digital converter with on-chip track-and-hold circuits. It is optimized for low cost, low power, small size, and ease of use. The product operates at a 100 MSPS conversion rate with outstanding dynamic performance over its full operating range. Each channel can be operated independently. The ADC requires only a single 3.0 V (2.7 V to 3.6 V) power supply and an Encode clock for full-performance operation. No external reference or driver components are required for many applications. The digital outputs are TTL/CMOS-compatible, and a separate output power supply pin supports interfacing with 3.3 V or 2.5 V logic. The Encode input is TTL/CMOS-compatible, and the 8-bit digital outputs can be operated from 3.0 V (2.5 V to 3.6 V) supplies. User-selectable options offer a combination of standby modes, digital data formats, and digital data timing schemes. In standby mode, the digital outputs are driven to a high impedance state. Fabricated on an advanced CMOS process, the AD9288 is available in a 48-lead surface-mount plastic package (7 mm × 7 mm, 1.4 mm LQFP) specified over the industrial temperature range (–40°C to +85°C). The AD9288 is pin-compatible with the 10-bit AD9218, facilitating future system migrations.

Rev. C | Page 2 of 24 TABLE OF CONTENTS

REVISION HISTORY

12/04—Rev. B to Rev. C 2/02—Rev. A to Rev. B 1/01—Rev. 0 to Rev. A 2/99—Revision 0: Initial Version

Rev. C | Page 3 of 24 SPECIFICATIONS VDD = 3.0 V; VD = 3.0 V , differential input; external reference, unless otherwise noted. Table 1. Test AD9288BST-100 AD9288BST-80 AD9288BST-40 Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit RESOLUTION 8 8 8 Bits DC ACCURACY Full VI 1.50 1.50 1.50 LSB Full VI 1.50 1.50 1.50 LSB No Missing Codes Full VI Guaranteed Guaranteed Guaranteed Gain Error1 25°C I –6 ± 2.5 +6 –6 ± 2.5 +6 –6 ± 2.5 +6 % FS Full VI –8 +8 –8 +8 –8 +8 % FS Gain Tempco1 Full VI 80 80 80 ppm/°C Gain Matching 25°C V ±1.5 ±1.5 ±1.5 % FS Voltage Matching 25°C V ±15 ±15 ±15 mV ANALOG INPUT Input Voltage Range (with Respect to AIN) Full V ±512 ±512 ±512 mV p-p Common-Mode Voltage Full V 0.3 × VD 0.3 × VD 0.3 × VD 0.3 × VD 0.3 × VD 0.3 × VD 0.3 × VD 0.3 × VD 0.3 × VD V Input Offset Voltage 25°C I –35 ±10 +35 –35 ± 10 +35 –35 ± 10 +35 mV Full VI –40 +40 –40 +40 –40 +40 mV Reference Tempco Full VI ± 130 ± 130 ± 130 ppm/°C Input Resistance 25°C I 7 10 13 7 10 13 7 10 13 kΩ Full VI 5 16 5 16 5 16 Input Capacitance 25°C V 2 2 2 pF Analog Bandwidth, Full Power 25°C V 475 475 475 MHz SWITCHING PERFORMANCE Maximum Conversion Rate Full VI 100 80 40 MSPS Minimum Conversion Rate 25°C IV 1 1 1 MSPS Encode Pulse Width High (tEH) 25°C IV 4.3 1000 5.0 1000 8.0 1000 ns Encode Pulse Width Low (tEL) 25°C IV 4.3 1000 5.0 1000 8.0 1000 ns Aperture Delay (tA) 25°C V 300 300 300 ps Aperture Uncertainty (Jitter) 25°C V 5 5 5 ps rms Output Valid Time (tV)2 Full VI 2 3.0 2 3.0 2 3.0 ns Output Propagation Delay (tPD)2 DIGITAL INPUTS Logic 1 Voltage Full VI 2.0 2.0 2.0 V Logic 0 Voltage Full VI 0.8 0.8 0.8 V Logic 1 Current Full VI ± 1 ± 1 ± 1 µA Logic 0 Current Full VI ± 1 ± 1 ± 1 µA Input Capacitance 25°C V 2.0 2.0 2.0 pF DIGITAL OUTPUTS3 Logic 1 Voltage Full VI 2.45 2.45 2.45 V Logic 0 Voltage Full VI 0.05 0.05 0.05 V POWER SUPPLY Power Dissipation4 Full VI 180 218 171 207 156 189 mW Standby Dissipation4, 5 Full VI 6 11 6 11 6 11 mW Power Supply Rejection Ratio (PSRR) 25°C I 8 20 8 20 8 20 mV/V

Rev. C | Page 4 of 24 Test AD9288BST-100 AD9288BST-80 AD9288BST-40 Parameter Temp Level Min Typ Max Min Typ Max Min Typ Max Unit DYNAMIC PERFORMANCE6 Transient Response 25°C V 2 2 2 ns Overvoltage Recovery Time 25°C V 2 2 2 ns Signal-to-Noise Ratio (SNR) (without Harmonics) fIN = 10.3 MHz 25°C I 47.5 47.5 44 47.5 dB fIN = 26 MHz 25°C I 47.5 44 47 dB fIN = 41 MHz 25°C I 44 47.0 dB Signal-to-Noise Ratio (SINAD) (with Harmonics) fIN = 10.3 MHz 25°C I 47 47 44 47 dB fIN = 26 MHz 25°C I 47 44 47 dB fIN = 41 MHz 25°C I 44 47 47 dB Effective Number of Bits fIN = 26 MHz 25°C I 7.5 7.0 7.5 Bits fIN = 41 MHz 25°C I 7.0 7.5 7.5 Bits Second Harmonic Distortion fIN = 10.3 MHz 25°C I 70 70 55 70 dBc fIN = 26 MHz 25°C I 70 55 70 dBc fIN = 41 MHz 25°C I 55 70 70 dBc Third Harmonic Distortion fIN = 10.3 MHz 25°C I 60 60 55 60 dBc fIN = 26 MHz 25°C I 60 55 60 dBc fIN = 41 MHz 25°C I 52 60 60 dBc Two-Tone Intermod Distortion (IMD) fIN = 10.3 MHz 25°C V 60 60 60 dBc 1 Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.25 V external reference). 2 tV and tPD are measured from the 1.5 V level of the Encode input to the 10%/90% levels of the digital outputs swing. The digital output load during test is not to exceed an ac load of 10 pF or a dc current of ±40 µA. 3 Digital supply current based on VDD = 3.0 V output drive with < 10 pF loading under dynamic test conditions. 4 Power dissipation measured under the following conditions: fS = 100 MSPS, analog input is –0.7 dBFS, both channels in operation. 5 Standby dissipation calculated with Encode clock in operation. 6 SNR/harmonics based on an analog input voltage of –0.7 dBFS referenced to a 1.024 V full-scale input range. EXPLANATION OF TEST LEVELS Level Description I 100% production tested. II 100% production tested at 25°C and sample tested at specified temperatures. III Sample tested only. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI 100% production tested at 25°C; guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices.

Figure 4. Data Align with Two Clock Sources (S1 = 1, S2 = 1) Channel Timing

Rev. C | Page 7 of 24 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating VD, VDD 4 V Analog Inputs –0.5 V to VD + 0.5 V Digital Inputs –0.5 V to VDD + 0.5 V VREF IN –0.5 V to VD + 0.5 V Digital Output Current 20 mA Operating Temperature –55°C to +125°C Storage Temperature –65°C to +150°C Maximum Junction Temperature 150°C Maximum Case Temperature 150°C Thermal Impedance θja 57°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions outside of those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Figure 5. Pin Configuration 2 AINA Analog Input for Channel A. 3 AINA Analog Input for Channel A (Complementary). 4 DFS Data Format Select. Offset binary output available if set low. Twos complement output available if set high. 5 REFINA Reference Voltage Input for Channel A. 6 REFOUT Internal Reference Voltage. 7 REFINB Reference Voltage Input for Channel B. 8 S1 User Select 1. Refer to Table 4. Tied with respect to VD. 9 S2 User Select 2. Refer to Table 4. Tied with respect to VD. 10 AINB Analog Input for Channel B (Complementary). 11 AINB Analog Input for Channel B. 14 ENCB Clock Input for Channel B. 17–24 D7B–D0 B Digital Output for Channel B. 37–44 D0A–D7 A Digital Output for Channel A. 47 ENC A Clock Input for Channel A.

Rev. C | Page 13 of 24 TERMINOLOGY Analog Bandwidth (Small Signal) The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between a 50% crossing of Encode and the instant at which the analog input is sampled. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Differential Nonlinearity The deviation of any code from an ideal 1 LSB step. Encode Pulse Width/Duty Cycle Pulse width high is the minimum amount of time that the Encode pulse should be left in Logic 1 state to achieve rated performance; pulse width low is the minimum time Encode pulse should be left in low state. At a given clock rate, these specs define an acceptable Encode duty cycle. Integral Nonlinearity The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a “best straight line” determined by a least square curve fit. Minimum Conversion Rate The Encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Maximum Conversion Rate The Encode rate at which parametric testing is performed. Output Propagation Delay The delay between a 50% crossing of Encode and the time when all output data bits are within valid logic levels. Power Supply Rejection Ratio The ratio of a change in input offset voltage to a change in power supply voltage. Signal-to-Noise-and-Distortion (SINAD) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral compo- nents, including harmonics but excluding dc. Signal-to-Noise Ratio (SNR) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious compo- nent may or may not be a harmonic. May be reported in dBc (i.e., degrades as signal level is lowered), or in dBFS (always related back to converter full scale). Two-Tone Intermodulation Distortion Rejection Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. May be reported in dBc (i.e., degrades as signal level is lowered), or in dBFS (always related back to converter full scale). Worst Harmonic The ratio of the rms value of either input tone to the rms value of the worst third order intermodulation product; reported in dBc.

(< 1 inch), minimizing on-chip noise at switching. clock source. The Encode input is fully TTL/CMOS-compatible. dynamic performance, impedance at AIN and AIN should match. voltage, which changes linearly. converter’s dynamic performance. Two pins are available for a combination of operational modes. from Channel B is 180° out of phase with respect to Channel A. same rising edge of the clock. Table 4. User-Selectable Options 0 0 Standby Both Channels A and B. 1 0 Normal Operation (Data Align Disabled).

Table 5. Bill of Materials

25.602.5453.0 Wieland

1 P2, P3 are implemented as one physical 80-pin connector SAMTEC TSW-140-08-L-D-RA. 2 AD9288/PCB populated with AD9288-100. 3 To use optional amp: place R22, R23, R30, R24, R16, R29, remove R4, R36.

Rev. C | Page 16 of 24 EVALUATION BOARD The AD9218/AD9288 customer evaluation board offers an easy way to test the AD9218 or the AD9288. The compatible pinout of the two parts facilitates the use of one PCB for testing either part. The PCB requires power supplies, a clock source, and a filtered analog source for most ADC testing required. POWER CONNECTOR Power is supplied to the board via a detachable 12-lead power strip. The minimum 3 V supplies required to run the board are VDD, VDL, and VDD. To allow the use of the optional amplifier path, ±5 V supplies are required. ANALOG INPUTS Each channel has an independent analog path that uses a wideband transformer to drive the ADC differentially from a single-ended sine source at the input SMAs. The transformer paths can be bypassed to allow the use of a dc-coupled path by using two AD8138 op amps with a simple board modification. The analog input should be band-pass filtered to remove any harmonics in the input signal and to minimize aliasing. VOLTAGE REFERENCE The AD9288 has an internal 1.25 V voltage reference; an external reference for each channel can be used instead by connecting two external voltage references at the power connector and setting jumpers at E18 and E19. The evaluation board is shipped configured for internal reference mode. CLOCKING Each channel can be clocked by a common clock input at SMA input ENCODE A/B. The channels can also be clocked independently by a simple board modification. The clock input should be a low jitter sine source for maximum performance. DATA OUTPUTS The data outputs are latched on-board by two 10-bit latches and drive an 8-pin connector which is compatible with the dual- channel FIFO board available from Analog Devices. This board, together with ADC analyzer software, can greatly simplify ADC testing. DATA FORMAT/GAIN The DFS/Gain pin can be biased for desired operation at the DFS jumper located at the S1, S2 jumpers. TIMING Timing on each channel can be controlled if needed on the PCB. Clock signals at the latches or the data ready signals that go to the output 80-pin connector can be inverted if required. Jumpers also allow for biasing of Pins S1 and S2 for power- down and timing alignment control.

Figure 26. PCB Schematic

Figure 27. PCB Schematic (Continued)

Rev. C | Page 20 of 24 TROUBLESHOOTING If the board does not seem to be working correctly, try the following:

• Verif y power at the IC pins.
• Check that all jumpers are in the correct position for the desired mode of operation.
• Verif y that VREF is at 1.23 V .
• Try running Encode clock and analog inputs at low speeds (20 MSPS/1 MHz) and monitor LCX821 outputs, DAC outputs, and ADC outputs for toggling. The AD9218/AD9288 evaluation board is provided as a design example for customers of Analog Devices, Inc. ADI makes no warranties, express, statutory, or implied, regarding merchantability or fitness for a particular purpose.

9.00 BSC

0.08 MAX

Figure 34. 48-Lead Low Profile Quad Flat Package [LQFP]

Rev. C | Page 22 of 24 NOTES

Rev. C | Page 23 of 24 NOTES

Rev. C | Page 24 of 24 NOTES © 2004 Analo g De vices, Inc. All rights reserve d. Tra demarks and registered tra demarks are the prop erty of their respective owners . C00585–0–12/04(C)