PCB80C31BH5-30WP

80C31 PHILIPS | Alldatasheet

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CMOS single-chip 8-bit microcontrollers Product specification 1996 Aug 16 INTEGRATED CIRCUITS IC20 Data Handbook

Philips Semiconductors Product specification 80C31/80C51/87C51CMOS single-chip 8-bit microcontrollers

21996 Aug 16 853–0169 17187

DESCRIPTION

The Philips 80C31/80C51/87C51 is a high-performance microcontroller fabricated with Philips high-density CMOS technology. The CMOS 8XC51 is functionally compatible with the NMOS 8031/8051 microcontrollers. The Philips CMOS technology combines the high speed and density characteristics of HMOS with the low power attributes of CMOS. Philips epitaxial substrate minimizes latch-up sensitivity. The 8XC51 contains a 4k × 8 ROM (80C51) EPROM (87C51), a 128 × 8 RAM, 32 I/O lines, two 16-bit counter/timers, a five-source, two-priority level nested interrupt structure, a serial I/O port for either multi-processor communications, I/O expansion or full duplex UART, and on-chip oscillator and clock circuits. In addition, the device has two software selectable modes of power reduction—idle mode and power-down mode. The idle mode freezes the CPU while allowing the RAM, timers, serial port, and interrupt system to continue functioning. The power-down mode saves the RAM contents but freezes the oscillator, causing all other chip functions to be inoperative.

FEATURES

• 8031/8051 compatible – 4k × 8 ROM (80C51) – 4k × 8 EPROM (87C51) – ROMless (80C31) – 128 × 8 RAM – Two 16-bit counter/timers – Full duplex serial channel – Boolean processor
• Memory addressing capability – 64k ROM and 64k RAM
• Power control modes: – Idle mode – Power-down mode
• CMOS and TTL compatible
• Five speed ranges at VCC = 5V – 12MHz – 16MHz – 24MHz – 33MHz
• Five package styles
• Extended temperature ranges
• OTP package available PIN CONFIGURATIONS 20 21 40P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 RST RxD/P3.0 TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 P1.7 WR /P3.6 RD /P3.7 XTAL2 XTAL1 VSS P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE/PROG EA /VPP P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VCC CERAMIC AND PLASTIC DUAL IN-LINE PACKAGE CERAMIC AND PLASTIC LEAD CHIP CARRIER 6 1 40 18 28 PLASTIC QUAD FLAT PACK 44 34 12 22 SU00001 SEE PAGE 3 FOR QFP AND LCC PIN FUNCTIONS.

Philips Semiconductors Product specification 80C31/80C51/87C51CMOS single-chip 8-bit microcontrollers

1996 Aug 16 3

CERAMIC AND PLASTIC LEADED CHIP CARRIER PIN FUNCTIONS LCC 6 1 40 18 28 Pin Function

1 NC*

2 P1.0 3 P1.1 4 P1.2 5 P1.3 6 P1.4 7 P1.5 8 P1.6 9 P1.7

10 RST

11 P3.0/RxD

12 NC*

13 P3.1/TxD 14 P3.2/INT0 15 P3.3/INT1 Pin Function 16 P3.4/T0 17 P3.5/T1 18 P3.6/WR 19 P3.7/RD

20 XTAL2

21 XTAL1

22 V SS

23 NC*

24 P2.0/A8 25 P2.1/A9 26 P2.2/A10 27 P2.3/A11 28 P2.4/A12 29 P2.5/A13 30 P2.6/A14 Pin Function 31 P2.7/A15

32 PSEN

33 ALE/PROG

34 NC*

35 EA /VPP

36 P0.7/AD7 37 P0.6/AD6 38 P0.5/AD5 39 P0.4/AD4 40 P0.3/AD3 41 P0.2/AD2 42 P0.1/AD1 43 P0.0/AD0

44 V CC

SU00002* DO NOT CONNECT PLASTIC QUAD FLAT PACK PIN FUNCTIONS Pin Function 1 P1.5 2 P1.6 3 P1.7

4 RST

5 P3.0/RxD

6 NC*

7 P3.1/TxD 8 P3.2/INT0 9 P3.3/INT1 10 P3.4/T0 11 P3.5/T1 12 P3.6/WR 13 P3.7/RD

14 XTAL2

15 XTAL1

16 V SS

17 NC*

18 P2.0/A8 19 P2.1/A9 20 P2.2/A10 21 P2.3/A11 22 P2.4/A12 23 P2.5/A13 24 P2.6/A14 25 P2.7/A15

26 PSEN

27 ALE/PROG

28 NC*

29 EA /VPP

30 P0.7/AD7 Pin Function 31 P0.6/AD6 32 P0.5/AD5 33 P0.4/AD4 34 P0.3/AD3 35 P0.2/AD2 36 P0.1/AD1 37 P0.0/AD0

38 V CC

39 NC*

40 P1.0 41 P1.1 42 P1.2 43 P.13 44 P1.4 PQFP 44 34 12 22 SU00003* DO NOT CONNECT LOGIC SYMBOL PORT 0PORT 1PORT 2 PORT 3 ADDRESS AND DATA BUS ADDRESS BUS SECONDARY FUNCTIONS RxD TxD INT0 INT1 WR RD RST EA /VPP PSEN ALE/PROG VSSVCC XTAL1 XTAL2 SU00004

Philips Semiconductors Product specification 80C31/80C51/87C51CMOS single-chip 8-bit microcontrollers

1996 Aug 16 4

ORDERING INFORMATION

SC87C51CCF40 0590B 0 to +70, Ceramic Dual In-line Package, UV3.5 to 12 SC87C51CCK44 1472A 0 to +70, Ceramic Leaded Chip Carrier, UV 3.5 to 12 SC87C51CCN40 SOT129-1 SC80C31BCCN40 SC80C51BCCN40 SOT129-1 0 to +70, Plastic Dual In-line Package, OTP3.5 to 12 SC87C51CCA44 SOT187-2 SC80C31BCCA44 SC80C51BCCA44 SOT187-2 0 to +70, Plastic Leaded Chip Carrier, OTP 3.5 to 12 SC87C51CCB44 SOT307-2 SC80C31BCCB44 SC80C51BCCB44 SOT307-2 0 to +70, Plastic Quad Flat Pack, OTP 3.5 to 12 SC87C51ACF40 0590B –40 to +85, Ceramic Dual In-line Package, UV3.5 to 12 SC87C51ACN40 SOT129-1 SC80C31BACN40 SC80C51BACN40 SOT129-1 –40 to +85, Plastic Dual In-line Package, OTP3.5 to 12 SC87C51ACA44 SOT187-2 SC80C31BACA44 SC80C51BACA44 SOT187-2 –40 to +85, Plastic Leaded Chip Carrier, OTP 3.5 to 12 SC87C51ACB44 SOT307-2 SC80C31BACB44 SC80C51BACB44 SOT307-2 –40 to +85, Plastic Quad Flat Pack, OTP3.5 to 12 SC87C51CGF40 0590B 0 to +70, Ceramic Dual In-line Package, UV3.5 to 16 SC87C51CGK44 1472A 0 to +70, Ceramic Leaded Chip Carrier, UV 3.5 to 16 SC87C51CGN40 SOT129-1 SC80C31BCGN40 SC80C51BCGN40 SOT129-1 0 to +70, Plastic Dual In-line Package, OTP3.5 to 16 SC87C51CGA44 SOT187-2 SC80C31BCGA44 SC80C51BCGA44 SOT187-2 0 to +70, Plastic Leaded Chip Carrier, OTP 3.5 to 16 SC87C51CGB44 SOT307-2 SC80C31BCGB44 SC80C51BCGB44 SOT307-2 0 to +70, Plastic Quad Flat Pack, OTP 3.5 to 16 SC87C51AGF40 0590B –40 to +85, Ceramic Dual In-line Package, UV3.5 to 16 SC87C51AGN40 SOT129-1 SC80C31BAGN40 SC80C51BAGN40 SOT129-1 –40 to +85, Plastic Dual In-line Package, OTP3.5 to 16 SC87C51AGA44 SOT187-2 SC80C31BAGA44 SC80C51BAGA44 SOT187-2 –40 to +85, Plastic Leaded Chip Carrier, OTP 3.5 to 16 SC87C51AGB44 SOT307-2 SC80C31BAGB44 SC80C51BAGB44 SOT307-2 –40 to +85, Plastic Quad Flat Pack, OTP3.5 to 16 SC87C51CPF40 0590B 0 to +70, Ceramic Dual In-line Package, UV3.5 to 24 SC87C51CPK44 1472A 0 to +70, Ceramic Leaded Chip Carrier, UV 3.5 to 24 SC87C51CPN40 SOT129-1 SC80C31BCPN40 SC80C51BCPN40 SOT129-1 0 to +70, Plastic Dual In-line Package, OTP3.5 to 24 SC87C51CPA44 SOT187-2 SC80C31BCPA44 SC80C51BCPA44 SOT187-2 0 to +70, Plastic Leaded Chip Carrier, OTP 3.5 to 24 SC87C51APF40 0590B –40 to +85, Ceramic Dual In-line Package, UV SC87C51APN40 SOT129-1 SC80C31BAPN40 SC80C51BAPN40 SOT129-1 –40 to +85, Plastic Dual In-line Package, OTP3.5 to 24 SC87C51APA44 SOT187-2 SC80C31BAPA44 SC80C51BAPA44 SOT187-2 –40 to +85, Plastic Leaded Chip Carrier, OTP 3.5 to 24 SC87C51CYF40 0590B 0 to +70, Ceramic Dual In-line Package, UV3.5 to 33 SC87C51CYK44 1472A 0 to +70, Ceramic Leaded Chip Carrier, UV 3.5 to 33 SC87C51CYN40 SOT129-1 SC80C31BCYN40 SC80C51BCYN40 SOT129-1 0 to +70, Plastic Dual In-line Package, OTP3.5 to 33 SC87C51CYA44 SOT187-2 SC80C31BCYA44 SC80C51BCYA44 SOT187-2 0 to +70, Plastic Leaded Chip Carrier, OTP 3.5 to 33 1. OTP = One Time Programmable EPROM. UV = UV Erasable EPROM 2. SOT311 replaced by SOT307-2.

Philips Semiconductors Product specification 80C31/80C51/87C51CMOS single-chip 8-bit microcontrollers

1996 Aug 16 5

ORDERING INFORMATION (Continued) PHILIPS ROMless (ORDER NUMBER) ROMless (MARKING NUMBER) ROM DRAWING NUMBER TEMPERATURE RANGE oC AND PACKAGE 1 Freq MHz PCB80C31-2 N PCB80C31BH2-12P PCB80C51BH-2P SOT129-1 0 to +70, Plastic Dual In-line Package, OTP0.5 to 12 PCB80C31-2 A PCB80C31BH2-12 WP PCB80C51BH-2WP SOT187-2 0 to +70, Plastic Leaded Chip Carrier, OTP 0.5 to 12 PCB80C31BH2-12H PCB80C51BH-2H SOT307-2 2 0 to +70, Plastic Quad Flat Pack, OTP 0.5 to 12 PCB80C31-3 N PCB80C31BH3-16P PCB80C51BH-3P SOT129-1 0 to +70, Plastic Dual In-line Package, OTP1.2 to 16 PCB80C31-3 A PCB80C31BH3-16 WP PCB80C51BH-3WP SOT187-2 0 to +70, Plastic Leaded Chip Carrier, OTP 1.2 to 16 PCB80C31BH3-16H PCB80C51BH-3H SOT307-2 2 0 to +70, Plastic Quad Flat Pack, OTP 1.2 to 16 PCF80C31-3 N PCF80C31BH3-16P PCF80C51BH-3P SOT129-1 –40 to +85, Plastic Dual In-line Package, OTP1.2 to 16 PCF80C31-3 A PCF80C31BH3-16 WP PCF80C51BH-3WP SOT187-2 –40 to +85, Plastic Leaded Chip Carrier, OTP 1.2 to 16 PCF80C31BH3-16H PCF80C51BH-3H SOT307-2 2 –40 to +85, Plastic Quad Flat Pack, OTP1.2 to 16 PCA80C31BH3-16P PCA80C51BH-3P SOT129-1 –40 to +125, Plastic Dual In-line Package1.2 to 16 PCA80C31BH3-16 WP PCA80C51BH-3WP SOT187-2 –40 to +125, Plastic Leaded Chip Carrier1.2 to 16 PCB80C31-4 N PCB80C31BH4-24P PCB80C51BH-4P SOT129-1 0 to +70, Plastic Dual In-line Package, OTP1.2 to 24 PCB80C31-4 A PCB80C31BH4-24 WP PCB80C51BH-4WP SOT187-2 0 to +70, Plastic Leaded Chip Carrier, OTP 1.2 to 24 PCB80C31BH4-24H PCB80C51BH-4H SOT307-2 2 0 to +70, Plastic Quad Flat Pack, OTP 1.2 to 24 PCF80C31-4 N PCF80C31BH4-24P PCF80C51BH-4P SOT129-1 –40 to +85, Plastic Dual In-line Package, OTP1.2 to 24 PCF80C31-4 A PCF80C31BH4-24 WP PCF80C51BH-4WP SOT187-2 –40 to +85, Plastic Leaded Chip Carrier, OTP 1.2 to 24 PCF80C31BH4-24H PCF80C51BH-4H SOT307-2 2 –40 to +85, Plastic Leaded Chip Carrier, OTP 1.2 to 24 PCB80C31-5 N PCB80C31BH5-30P PCB80C51BH-5P SOT129-1 0 to +70, Plastic Dual In-line Package 1.2 to 33 PCB80C31-5 A PCB80C31BH5-30 WP PCB80C51BH-5WP SOT187-2 0 to +70, Plastic Leaded Chip Carrier 1.2 to 33 PCB80C31-5 B PCB80C31BH5-30H PCB80C51BH-5H SOT307-2 2 0 to +70, Plastic Quad Flat Pack 1.2 to 33

Philips Semiconductors Product specification 80C31/80C51/87C51CMOS single-chip 8-bit microcontrollers

1996 Aug 16 6

INTERRUPT, SERIAL PORT AND TIMER BLOCKS SU00005

Philips Semiconductors Product specification 80C31/80C51/87C51CMOS single-chip 8-bit microcontrollers

1996 Aug 16 7

PIN NO. MNEMONIC DIP LCC QFP TYPE NAME AND FUNCTION VSS 20 22 16 I Ground: 0V reference. VCC 40 44 38 I Power Supply: This is the power supply voltage for normal, idle, and power-down operation. P0.0–0.7 39–32 43–36 37–30 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pull-ups when emitting 1s. Port 0 also outputs the code bytes during program verification in the 87C51. External pull-ups are required during program verification. 1–3 I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 1 also receives the low-order address byte during program memory verification. P2.0–P2.7 21–28 24–31 18–25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function register. 13–19 7–13 I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: IIL). Port 3 also serves the special features of the 80C51 family, as listed below: 10 11 5 I RxD (P3.0): Serial input port 11 13 7 O TxD (P3.1): Serial output port 12 14 8 I INT0 (P3.2): External interrupt 13 15 9 I INT1 (P3.3): External interrupt 14 16 10 I T0 (P3.4): Timer 0 external input 15 17 11 I T1 (P3.5): Timer 1 external input 16 18 12 O WR (P3.6): External data memory write strobe 17 19 13 O RD (P3.7): External data memory read strobe RST 9 10 4 I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VCC . ALE/PROG 30 33 27 I/O Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. This pin is also the program pulse input (PROG) during EPROM programming. PSEN 29 32 26 O Program Store Enable: The read strobe to external program memory. When the device is executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. EA /VPP 31 35 29 I External Access Enable/Programming Supply Voltage: EA must be externally held low to enable the device to fetch code from external program memory locations 0000H to 0FFFH. If EA is held high, the device executes from internal program memory unless the program counter contains an address greater than 0FFFH. This pin also receives the 12.75V programming supply voltage (VPP ) during EPROM programming. XTAL1 19 21 15 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. XTAL2 18 20 14 O Crystal 2: Output from the inverting oscillator amplifier.

1996 Aug 16 8

Table 1. 80C52/80C54/80C58 Special Function Registers # SFRs are modified from or added to the 80C51 SFRs.

1. Reset value depends on reset source.
2. Available only on SC80C51.

1996 Aug 16 9

oscillator, as shown in the logic symbol. the internal clock circuitry is through a divide-by-two flip-flop. the data sheet must be observed. machine cycles (24 oscillator periods), while the oscillator is running. milliseconds) plus two machine cycles. the same manner as a power-on reset. instruction to invoke power-down is the last instruction executed. Table 2. External Pin Status During Idle and Power-Down Modes

1. 64 byte ROM encryption key (SC80C51 only)
2. ROM security bits (SC80C51 only).
3. External MOVC is disabled, and

Security Bit 2: When programmed, this bit inhibits Verify User ROM.

Philips Semiconductors Product specification 80C31/80C51/87C51CMOS single-chip 8-bit microcontrollers

1996 Aug 16 10

Electrical Deviations from Commercial Specifications for Extended Temperature Range (87C51) DC and AC parameters not included here are the same as in the commercial temperature range table. DC ELECTRICAL CHARACTERISTICS Tamb = –40°C to +85°C, VCC = 5V ±10%, VSS = 0V (Philips North America SC87C51); For SC87C51 (33MHz only), Tamb = 0°C to +70°C, VCC = 5V ±5% Tamb = –40°C to +85°C, VCC = 5V ±10%, VSS = 0V (PCB80C31/51 and PCF80C31/51 Philips Parts Only) TEST LIMITS SYMBOL PARAMETER CONDITIONS MIN MAX UNIT VIL Input low voltage, except EA (Philips North America) –0.5 0.2VCC –0.15 V VIL Input low voltage, except EA (Philips) –0.5 0.2VCC –0.25 V VIL1 Input low voltage to EA –0.5 0.2VCC –0.45 V VIH Input high voltage, except XTAL1, RST 0.2VCC +1 VCC +0.5 V VIH1 Input high voltage to XTAL1, RST 0.7VCC +0.1 VCC +0.5 V IIL Logical 0 input current, ports 1, 2, 3 VIN = 0.45V –75 µA ITL Logical 1-to-0 transition current, ports 1, 2, 3 VIN = 2.0V –750 µA ICC Power supply current: VCC = 4.5–5.5VCC Active mode1 @ 16MHz (Philips PCB80C31/51, PCF80C31/51) 25 mA Active mode @ 12MHz (Philips North America SC87C51) 20 mA Idle mode2 @ 16MHz (Philips PCB80C31/51, PCF80C31/51) 6.5 mA Idle mode @ 12MHz (Philips North America SC87C51) 5 mA Power-down mode3 (Philips PCB80C31/51, PCF80C31/51) 75 µA Power-down mode (Philips North America SC87C51) 50 µA NOTES: 1. The operating supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10ns; VIL = VSS + 0.5V; VIH = VCC – 0.5V; XTAL2 not connected; EA = RST = Port 0 = VCC . 2. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10ns; VIL = VSS + 0.5V; VIH = VCC – 0.5V; XTAL2 not connected; EA = Port 0 = VCC ; RST = VSS. 3. The power-down current is measured with all output pins disconnected, XTAL2 not connected, EA = Port 0 = VCC ; RST = VSS. ABSOLUTE MAXIMUM RATINGS 1, 2, 3 PARAMETER RATING UNIT Operating temperature under bias 0 to +70 or –40 to +85 °C Storage temperature range –65 to +150 °C Voltage on EA/VPP pin to VSS 0 to +13.0 V Voltage on any other pin to VSS –0.5 to +6.5 V Maximum IOL per I/O pin 15 mA Power dissipation (based on package heat transfer limitations, not device power consumption)1.5 W NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted.

Philips Semiconductors Product specification 80C31/80C51/87C51CMOS single-chip 8-bit microcontrollers

1996 Aug 16 11

DC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5V ±20%, VSS = 0V (PCB80C31/51 and PCF80C31/51) (12, 16, and 24MHz versions) Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5V ±10%, VSS = 0V (87C51 12, 16, and 24MHz versions) (PCB80C31/51 33MHz version); For SC87C51 (33MHz only) Tamb = 0°C to +70°C, VCC = 5V ±5% TEST LIMITS SYMBOL PARAMETER CONDITIONS MIN TYPICAL 1 MAX UNIT VIL Input low voltage, except EA7 –0.5 0.2VCC –0.1 V VIL1 Input low voltage to EA7 0 0.2VCC –0.3 V VIH Input high voltage, except XTAL1, RST7 0.2VCC +0.9 VCC +0.5 V VIH1 Input high voltage, XTAL1, RST7 0.7VCC VCC +0.5 V VOL Output low voltage, ports 1, 2, 311 IOL = 1.6mA2 0.45 V VOL1 Output low voltage, port 0, ALE, PSEN11 IOL = 3.2mA2 0.45 V VOH Output high voltage, ports 1, 2, 3, ALE, PSEN3 IOH = –60µA, IOH = –25µA IOH = –10µA 2.4 0.75VCC 0.9VCC V V V VOH1 Output high voltage (port 0 in external bus mode)IOH = –800µA, IOH = –300µA IOH = –80µA 2.4 0.75VCC 0.9VCC V V V IIL Logical 0 input current, ports 1, 2, 37 VIN = 0.45V –50 µA ITL Logical 1-to-0 transition current, ports 1, 2, 37 See note 4 –650 µA ILI Input leakage current, port 0 VIN = VIL or VIH ±10 µA ICC Power supply current:7 Active mode @ 12MHz8 (Philips) Active mode @ 12MHz5 (Philips North America) Idle mode @ 12MHz9 (Philips) Idle mode @ 12MHz (Philips North America) Power-down mode 10 (Philips and Philips North America) See note 6 11.5 1.3 4.4 mA mA mA mA µA R RST Internal reset pull-down resistor (Philips North America) 50 300 kΩ (Philips) 50 150 kΩ C IO Pin capacitance12 10 pF NOTES: 1. Typical ratings are not guaranteed. The values listed are at room temperature, 5V. 2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOL s of ALE and ports 1 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no single output sinks more than 5mA and no more than two outputs exceed the test conditions. 3. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9VCC specification when the address bits are stabilizing. 4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2V. 5. ICCMAX at other frequencies (for Philips North America parts) is given by: Active mode: ICCMAX = 1.43 X FREQ + 1.90; 6. See Figures 9 through 12 for ICC test conditions. 7. For Philips North America parts when Tamb = –40°C to +85°C or Philips parts when Tamb = –40°C to +125°C, see DC Electrical Characteristics table on previous page. 8. The operating supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10ns; VIL = VSS + 0.5V; VIH = VCC – 0.5V; XTAL2 not connected; EA = RST = Port 0 = VCC . 9. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10ns; VIL = VSS + 0.5V; VIH = VCC – 0.5V; XTAL2 not connected; EA = Port 0 = VCC ; RST = VSS. 10.The power-down current is measured with all output pins disconnected, XTAL2 not connected, EA = Port 0 = VCC ; RST = VSS. 11.Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 15mA Maximum IOL per 8-bit port: 26mA Maximum IOL total for all outputs: 67mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 12.Pin capacitance for the ceramic DIP package is 15pF maximum.

Philips Semiconductors Product specification 80C31/80C51/87C51CMOS single-chip 8-bit microcontrollers

1996 Aug 16 12

DC ELECTRICAL CHARACTERISTICS FOR PHILIPS NORTH AMERICA DEVICES (SC80C31 AND SC80C51) Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5V ±10%; VSS = 0V SYMBOL PARAMETER TEST CONDITIONS LIMITS UNITSYMBOL PARAMETER TEST CONDITIONS MIN TYP 1 MAX UNIT VIH Input high voltage (ports 0, 1, 2, 3, EA) 0.2VCC +0.9 VCC +0.5 V VIH1 Input high voltage, XTAL1, RST 0.7VCC VCC +0.5 V VOL Output low voltage, ports 1, 2, 38 VCC = 4.5V IOL = 1.6mA2 0.4 V VOL1 Output low voltage, port 0, ALE, PSEN8, 7 VCC = 4.5V IOL = 3.2mA2 0.4 V VOH Output high voltage, ports 1, 2, 33 VCC = 4.5V IOH = –30µA VCC – 0.7 V VOH1 Output high voltage (port 0 in external bus mode), ALE 9, PSEN3 VCC = 4.5V IOH = –3.2mA VCC – 0.7 V IIL Logical 0 input current, ports 1, 2, 3 VIN = 0.4V –1 –50 µA ITL Logical 1-to-0 transition current, ports 1, 2, 36 VIN = 2.0V See note 4 –650 µA ILI Input leakage current, port 0 0.45 < VIN < VCC – 0.3 ±10 µA ICC Power supply current (see Figure 8): Active mode @ 16MHz5 Idle mode @ 16MHz5 Power-down mode See note 5 Tamb = 0 to +70°C Tamb = –40 to +85°C 11.5 1.3 µA µA µA µA R RST Internal reset pull-down resistor 40 225 kΩ C IO Pin capacitance10 (except EA) 15 pF NOTES: 1. Typical ratings are not guaranteed. The values listed are at room temperature, 5V. 2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOL s of ALE and ports 1 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no single output sinks more than 5mA and no more than two outputs exceed the test conditions. 3. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the (VCC –0.7) specification when the address bits are stabilizing. 4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2V. 5. See Figures 9 through 12 for ICC test conditions. Active Mode: ICC = 1.5 × FREQ + 8.0; Idle Mode: I CC = 0.14 × FREQ +2.31; See Figure 8. 6. This value applies to Tamb = 0°C to +70°C. For Tamb = –40°C to +85°C, ITL = –750µA. 7. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 8. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 15mA (*NOTE: This is 85 °C specification.) Maximum IOL per 8-bit port: 26mA Maximum total IOL for all outputs: 71mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 9. ALE is tested to VOH1 , except when ALE is off then VOH is the voltage specification. 10.Pin capacitance is characterized but not tested. Pin capacitance is less than 25pF. Pin capacitance of ceramic package is less than 15pF (except EA it is 25pF).

Philips Semiconductors Product specification 80C31/80C51/87C51CMOS single-chip 8-bit microcontrollers

1996 Aug 16 13

AC ELECTRICAL CHARACTERISTICS FOR SC87C51 12–33MHz PHILIPS NORTH AMERICA DEVICES Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5V ±10%, VSS = 0V (SC87C51 12, 16 and 24MHz versions); For SC87C51 (33MHz only) Tamb = = 0°C to +70°C, VCC = 5V ±5% VARIABLE CLOCK 3 SYMBOL FIGURE PARAMETER MIN MAX UNIT 1/tCLCL Oscillator frequency: Speed Versions SC87C51 C G P Y 3.5 3.5 3.5 3.5 MHz MHz MHz MHz tLHLL 1 ALE pulse width 2tCLCL –40 ns tAVLL 1 Address valid to ALE low tCLCL –13 ns tLLAX 1 Address hold after ALE low tCLCL –20 ns tLLIV 1 ALE low to valid instruction in 4tCLCL –65 ns tLLPL 1 ALE low to PSEN low tCLCL –13 ns tPLPH 1 PSEN pulse width 3tCLCL –20 ns tPLIV 1 PSEN low to valid instruction in 3tCLCL –45 ns tPXIX 1 Input instruction hold after PSEN 0 ns tPXIZ 1 Input instruction float after PSEN tCLCL –10 ns tAVIV 1 Address to valid instruction in 5tCLCL –55 ns tPLAZ 1 PSEN low to address float 10 ns Data Memory tRLRH 2, 3 RD pulse width 6tCLCL –100 ns tWLWH 2, 3 WR pulse width 6tCLCL –100 ns tRLDV 2, 3 RD low to valid data in 5tCLCL –90 ns tRHDX 2, 3 Data hold after RD 0 ns tRHDZ 2, 3 Data float after RD 2tCLCL –28 ns tLLDV 2, 3 ALE low to valid data in 8tCLCL –150 ns tAVDV 2, 3 Address to valid data in 9tCLCL –165 ns tLLWL 2, 3 ALE low to RD or WR low 3tCLCL –50 3tCLCL +50 ns tAVWL 2, 3 Address valid to WR low or RD low 4tCLCL –75 ns tQVWX 2, 3 Data valid to WR transition tCLCL –20 ns tWHQX 2, 3 Data hold after WR tCLCL –20 ns tRLAZ 2, 3 RD low to address float 0 ns tWHLH 2, 3 RD or WR high to ALE high tCLCL –20 tCLCL +25 ns External Clock tCHCX 5 High time 12 ns tCLCX 5 Low time 12 ns tCLCH 5 Rise time 20 ns tCHCL 5 Fall time 20 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. For all Philips North America speed versions only. 4. Interfacing the 87C51 to devices with float times up to 50ns is permitted. This limited bus contention will not cause damage to port 0 drivers.

Philips Semiconductors Product specification 80C31/80C51/87C51CMOS single-chip 8-bit microcontrollers

1996 Aug 16 14

AC ELECTRICAL CHARACTERISTICS FOR PHILIPS DEVICES Tamb = 0°C to +70°C, VCC = 5V ±20%, VSS = 0V (PCB80C31/51, PCF80C31/51)1, 2, 4, 5 VARIABLE CLOCK 3 SYMBOL FIGURE PARAMETER MIN MAX UNIT 1/tCLCL Oscillator frequency: Speed Versions PCB8031/51 –2 PCA/PCB/PCF80C31/51 –3 PCB/PCF80C31/51 –4 PCB/FB80C31/51 –5 0.5 1.2 1.2 1.2 MHz MHz MHz MHz tLHLL 1 ALE pulse width 2tCLCL –40 ns tAVLL 1 Address valid to ALE low tCLCL –25 ns tLLAX 1 Address hold after ALE low tCLCL –25 ns tLLIV 1 ALE low to valid instruction in 4tCLCL –65 ns tLLPL 1 ALE low to PSEN low tCLCL –25 ns tPLPH 1 PSEN pulse width 3tCLCL –45 ns tPLIV 1 PSEN low to valid instruction in 3tCLCL –60 ns tPXIX 1 Input instruction hold after PSEN 0 ns tPXIZ 1 Input instruction float after PSEN tCLCL –25 ns tAVIV 1 Address to valid instruction in 5tCLCL –80 ns tPLAZ 1 PSEN low to address float 10 ns Data Memory tRLRH 2, 3 RD pulse width 6tCLCL –100 ns tWLWH 2, 3 WR pulse width 6tCLCL –100 ns tRLDV 2, 3 RD low to valid data in 5tCLCL –90 ns tRHDX 2, 3 Data hold after RD 0 ns tRHDZ 2, 3 Data float after RD 2tCLCL –28 ns tLLDV 2, 3 ALE low to valid data in 8tCLCL –150 ns tAVDV 2, 3 Address to valid data in 9tCLCL –165 ns tLLWL 2, 3 ALE low to RD or WR low 3tCLCL –50 3tCLCL +50 ns tAVWL 2, 3 Address valid to WR low or RD low 4tCLCL –75 ns tQVWX 2, 3 Data valid to WR transition tCLCL –30 ns tWHQX 2, 3 Data hold after WR tCLCL –25 ns tRLAZ 2, 3 RD low to address float 0 ns tWHLH 2, 3 RD or WR high to ALE high tCLCL –25 tCLCL +25 ns External Clock tCHCX 5 High time 15 ns tCLCX 5 Low time 15 ns tCLCH 5 Rise time 20 ns tCHCL 5 Fall time 20 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. For all Philips speed versions only. 4. Interfacing the 80C31/51 to devices with float times up to 30ns is permitted. This limited bus contention will not cause damage to port 0 drivers. 5. VCC = 5V ±10% for 33MHz.

Philips Semiconductors Product specification 80C31/80C51/87C51CMOS single-chip 8-bit microcontrollers

1996 Aug 16 15

AC ELECTRICAL CHARACTERISTICS FOR PHILIPS NORTH AMERICA DEVICES (SC80C31 AND SC80C51) Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5V ±10%, VSS = 0V1, 2, 3 16MHz CLOCK VARIABLE CLOCK SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT 1/tCLCL 1 Oscillator frequency Speed versions : C, G 3.5 16 MHz tLHLL 1 ALE pulse width 85 2tCLCL –40 ns tAVLL 1 Address valid to ALE low 22 tCLCL –40 ns tLLAX 1 Address hold after ALE low 32 tCLCL –30 ns tLLIV 1 ALE low to valid instruction in 150 4tCLCL –100 ns tLLPL 1 ALE low to PSEN low 32 tCLCL –30 ns tPLPH 1 PSEN pulse width 142 3tCLCL –45 ns tPLIV 1 PSEN low to valid instruction in4 82 3tCLCL –105 ns tPXIX 1 Input instruction hold after PSEN 0 0 ns tPXIZ 1 Input instruction float after PSEN 37 tCLCL –25 ns tAVIV 1 Address to valid instruction in4 207 5tCLCL –105 ns tPLAZ 1 PSEN low to address float 10 10 ns Data Memory tRLRH 2, 3 RD pulse width 275 6tCLCL –100 ns tWLWH 2, 3 WR pulse width 275 6tCLCL –100 ns tRLDV 2, 3 RD low to valid data in 147 5tCLCL –165 ns tRHDX 2, 3 Data hold after RD 0 0 ns tRHDZ 2, 3 Data float after RD 65 2tCLCL –60 ns tLLDV 2, 3 ALE low to valid data in 350 8tCLCL –150 ns tAVDV 2, 3 Address to valid data in 397 9tCLCL –165 ns tLLWL 2, 3 ALE low to RD or WR low 137 239 3tCLCL –50 3tCLCL +50 ns tAVWL 2, 3 Address valid to WR low or RD low 122 4tCLCL –130 ns tQVWX 2, 3 Data valid to WR transition 13 tCLCL –50 ns tWHQX 2, 3 Data hold after WR 13 tCLCL –50 ns tQVWH 3 Data valid to WR high 287 7tCLCL –150 ns tRLAZ 2, 3 RD low to address float 0 0 ns tWHLH 2, 3 RD or WR high to ALE high 23 103 tCLCL –40 tCLCL +40 ns External Clock tCHCX 5 High time 20 20 tCLCL –tCLCX ns tCLCX 5 Low time 20 20 tCLCL –tCHCX ns tCLCH 5 Rise time 20 20 ns tCHCL 5 Fall time 20 20 ns Shift Register tXLXL 4 Serial port clock cycle time 750 12tCLCL ns tQVXH 4 Output data setup to clock rising edge 492 10tCLCL –133 ns tXHQX 4 Output data hold after clock rising edge 8 2tCLCL –117 ns tXHDX 4 Input data hold after clock rising edge 0 0 ns tXHDV 4 Clock rising edge to input data valid 492 10tCLCL –133 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. Interfacing the 80C31/51 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. 4. See application note AN457 for external memory interfacing.

Philips Semiconductors Product specification 80C31/80C51/87C51CMOS single-chip 8-bit microcontrollers

1996 Aug 16 16

AC ELECTRICAL CHARACTERISTICS FOR PHILIPS NORTH AMERICA DEVICES (SC80C31 AND SC80C51) Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5V ±10%, VSS = 0V1, 2, 3 24MHz CLOCK VARIABLE CLOCK 4 33MHz CLOCK SYMBOL FIGURE PARAMETER MIN MAX MIN MAX MIN MAX UNIT 1/tCLCL 1 Oscillator frequency Speed versions : P (24MHz) : Y (33MHz) 3.5 24 3.5 33 3.5 33 MHz tLHLL 1 ALE pulse width 43 2tCLCL –40 21 ns tAVLL 1 Address valid to ALE low 17 tCLCL –25 5 ns tLLAX 1 Address hold after ALE low 17 tCLCL –25 ns tLLIV 1 ALE low to valid instruction in 102 4tCLCL –65 55 ns tLLPL 1 ALE low to PSEN low 17 tCLCL –25 5 ns tPLPH 1 PSEN pulse width 80 3tCLCL –45 45 ns tPLIV 1 PSEN low to valid instruction in 65 3tCLCL –60 30 ns tPXIX 1 Input instruction hold after PSEN 0 0 0 ns tPXIZ 1 Input instruction float after PSEN 17 tCLCL –25 5 ns tAVIV 1 Address to valid instruction in 128 5tCLCL –80 70 ns tPLAZ 1 PSEN low to address float 10 10 10 ns Data Memory tRLRH 2, 3 RD pulse width 150 6tCLCL –100 82 ns tWLWH 2, 3 WR pulse width 150 6tCLCL –100 82 ns tRLDV 2, 3 RD low to valid data in 118 5tCLCL –90 60 ns tRHDX 2, 3 Data hold after RD 0 0 0 ns tRHDZ 2, 3 Data float after RD 55 2tCLCL –28 32 ns tLLDV 2, 3 ALE low to valid data in 183 8tCLCL –150 90 ns tAVDV 2, 3 Address to valid data in 210 9tCLCL –165 105 ns tLLWL 2, 3 ALE low to RD or WR low 75 175 3tCLCL –50 3tCLCL +50 40 140 ns tAVWL 2, 3 Address valid to WR low or RD low 92 4tCLCL –75 45 ns tQVWX 2, 3 Data valid to WR transition 12 tCLCL –30 0 ns tWHQX 2, 3 Data hold after WR 17 tCLCL –25 5 ns tQVWH 3 Data valid to WR high 162 7tCLCL –130 80 ns tRLAZ 2, 3 RD low to address float 0 0 0 ns tWHLH 2, 3 RD or WR high to ALE high 17 67 tCLCL –25 tCLCL +25 5 55 ns External Clock tCHCX 5 High time 17 17 tCLCL –tCLCX ns tCLCX 5 Low time 17 17 tCLCL –tCHCX ns tCLCH 5 Rise time 5 5 ns tCHCL 5 Fall time 5 5 ns Shift Register tXLXL 4 Serial port clock cycle time 505 12tCLCL 360 ns tQVXH 4 Output data setup to clock rising edge283 10tCLCL –133 167 ns tXHQX 4 Output data hold after clock rising edge3 2tCLCL –80 ns tXHDX 4 Input data hold after clock rising edge0 0 0 ns tXHDV 4 Clock rising edge to input data valid 283 10tCLCL –133 167 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. Interfacing the SC80C31/51 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. 4. Variable clock is specified for oscillator frequencies greater than 16MHz to 33MHz. For frequencies equal or less than 16MHz, see 16MHz “AC Electrial Characteristics”, page 15.

1996 Aug 16 17

Examples: tAVLL = Time for address valid to ALE low. tLLPL= Time for ALE low to PSEN low. Figure 1. External Program Memory Read Cycle Figure 2. External Data Memory Read Cycle

1996 Aug 16 18

Figure 3. External Data Memory Write Cycle Figure 4. Shift Register Mode Timing Figure 5. External Clock Drive

1996 Aug 16 19

AC inputs during testing are driven at VCC –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’. Timing measurements are made at VIH min for a logic ‘1’ and VIL max for a logic ‘0’. Figure 6. AC Testing Input/Output and begins to float when a 100mV change from the loaded VOH /VOL level occurs. IOH /IOL ≥ ±20mA. Figure 7. Float Waveform Figure 8. ICC vs. FREQ

1996 Aug 16 20

Figure 9. ICC Test Condition, Active Mode Figure 10. ICC Test Condition, Idle Mode Figure 11. Clock Signal Waveform for ICC Tests in Active and Idle Modes Figure 12. ICC Test Condition, Power Down Mode

1996 Aug 16 21

number of the ALE/PROG pulses. circuit configuration for normal program memory verification. Figure 13. Note that the 87C51 is running with a 4 to 6MHz device is executing internal address and program data transfers. low 25 times as shown in Figure 14. programmed, verification cycles will produce only encrypted data. encryption table itself cannot be read out. which satisfies the timing specifications, is suitable. light with wavelengths shorter than approximately 4,000 angstroms. (at 2537 angstroms) to an integrated dose of at least 15W-sec/cm2. Erasure leaves the array in an all 1s state. Table 3. EPROM Programming Modes

1. ‘0’ = Valid low for that pin, ‘1’ = valid high for that pin.
2. VCC = 5V±10% during programming and verification.
3. *ALE/PROG receives 25 programming pulses while VPP is held at 12.75V. Each programming pulse is low for 100µs (±10µs) and high for a

 Trademark phrase of Intel Corporation.

1996 Aug 16 22

Figure 13. Programming Configuration

25 PULSES

Figure 14. PROG Waveform

0 ENABLE

Figure 15. Program Verification

1996 Aug 16 23

• FOR PROGRAMMING VERIFICATION SEE FIGURE 13.

FOR VERIFICATION CONDITIONS SEE FIGURE 15. Figure 16. EPROM Programming and Verification

Philips Semiconductors Product specification 80C31/80C51/87C51CMOS single-chip 8-bit microcontrollers

1996 Aug 16 24

0590B 40-PIN (600 mils wide) CERAMIC DUAL IN-LINE (F) PACKAGE (WITH WINDOW (FA) PACKAGE) NOTES: 1. Controlling dimension: Inches. Millimeters are 2. Dimension and tolerancing per ANSI Y14. 5M-1982. 3. “T”, “D”, and “E” are reference datums on the body 4. These dimensions measured with the leads 5. Pin numbers start with Pin #1 and continue 6. Denotes window location for EPROM products. and include allowance for glass overrun and meniscus on the seal line, and lid to base mismatch. constrained to be perpendicular to plane T. counterclockwise to Pin #40 when viewed shown in parentheses. from the top. – D – PIN # 1 – E – 0.225 (5.72) MAX. 0.015 (0.38) 0.165 (4.19) 0.125 (3.18) 0.070 (1.78) 0.050 (1.27) – T – SEATING PLANE 0.620 (15.75) 0.590 (14.99) (NOTE 4) 0.598 (15.19) 0.571 (14.50) BSC 0.600 (15.24) 0.695 (17.65) 0.600 (15.24) (NOTE 4) 0.015 (0.38) 0.010 (0.25) 0.175 (4.45) 0.145 (3.68) 0.055 (1.40) 0.020 (0.51) 0.100 (2.54) BSC 2.087 (53.01) 2.038 (51.77) 0.098 (2.49) 0.040 (1.02) 0.098 (2.49) 0.040 (1.02) SEE NOTE 6 853–0590B 06688

Philips Semiconductors Product specification 80C31/80C51/87C51CMOS single-chip 8-bit microcontrollers

1996 Aug 16 25

1472A 44-PIN CERQUAD J-BEND (K) PACKAGE NOTES: 1. All dimensions and tolerances to conform 2. UV window is optional. 3. Dimensions do not include glass protrusion. Glass protrusion to be 0.005 inches maximum 4. Controlling dimension millimeters. 5. All dimensions and tolerances include lead trim offset and lead plating finish. 6. Backside solder relief is optional and dimensions are for reference only. 1.02 (0.040) X 45° 16.89 (0.665) 16.00 (0.630) 17.65 (0.695) 17.40 (0.685) CHAMFER 16.89 (0.665) 16.00 (0.630) 17.65 (0.695) 17.40 (0.685) on each side. to ANSI Y14.5–1982. 2 3 3 X 0.63 (0.025) R MIN. 3.05 (0.120) 2.29 (0.090) 4.83 (0.190) 3.94 (0.155) SEATING PLANE 0.38 (0.015) 0.51 (0.02) X 45° 17.65 (0.656) 17.40 (0.685) 1.27 (0.050) 12.7 (0.500) 8.13 (0.320) 7.37 (0.290) 40X 4.83 (0.190) 3.94 (0.155) SEATING PLANE 0.15 (0.006) MIN. 0.15 (0.006) 90 + 5 –10 ° ° 0.076 (0.003) MIN. DETAIL B mm/(inch) SEE DET AIL B SEE DET AIL A DETAIL A TYP. ALL SIDES mm/(inch) 1.52 (0.060) REF. SEATING PLANE 1.02 + 0.25 (0.040 + 0.010) BASE PLANE 45 TYP.

4 PLACES

1.27 (0.050) TYP. NOMINAL 8.13 (0.320) 7.37 (0.290) 853-1472A 05854

Philips Semiconductors Product specification 80C31/80C51/87C51CMOS single-chip 8-bit microcontrollers

1996 Aug 16 26

DIP40: plastic dual in-line package; 40 leads (600 mil) SOT129-1

Philips Semiconductors Product specification 80C31/80C51/87C51CMOS single-chip 8-bit microcontrollers

1996 Aug 16 27

PLCC44: plastic leaded chip carrier; 44 leads SOT187-2

Philips Semiconductors Product specification 80C31/80C51/87C51CMOS single-chip 8-bit microcontrollers

1996 Aug 16 28

QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2

Philips Semiconductors Product specification 80C31/80C51/87C51CMOS single-chip 8-bit microcontrollers

1996 Aug 16 29

Philips Semiconductors Product specification 80C31/80C51/87C51CMOS single-chip 8-bit microcontrollers Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Philips Semiconductors

811 East Arques Avenue

P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Preliminary Specification Product Specification Formative or in Design Preproduction Product Full Production This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation register eligible circuits under the Semiconductor Chip Protection Act.  Copyright Philips Electronics North America Corporation 1996 All rights reserved. Printed in U.S.A.