Interface

PCA2125TS

NXP Semiconductors

SPI Real-time clock/calendar Rev. 01-28 July 2008

Manufacturer: NXP Semiconductors

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are also available with the possibility to generate a wake-up signal on an interrupt pin. AEC Q100 qualiﬁed for automotive applications. Table 1. Ordering information

7.1 Pinning

7.2 Pin description

Table 3. Pin description

The ﬁrst two registers at addresses 00h and 01h (Control_1 and Control_2) are used as control registers.
Registers at addresses 02h to 08h (Seconds, Minutes, Hours, Days, Weekdays, Months, Y ears) are used as counters for the clock function. Seconds, minutes, hours, days, months and years are all coded in Binary Coded Decimal (BCD) format. When one of the RTC registers is read the contents of all counters are frozen. Therefore, faulty reading of the clock/calendar during a carry condition is prevented.
Registers at addresses 09h to 0Ch (Minute_alarm, Hour_alarm, Day_alarm, Weekday_alarm) deﬁne the alarm condition.
Register at address 0Dh (CLKOUT_control) deﬁnes the clock out mode.
Registers at addresses 0Eh and 0Fh (Timer_control and Countdown_timer) are used for the countdown timer function. The countdown timer has four selectable source clocks allowing for countdown periods in the range from less than 1 ms to more than 4 hours. There are also two pre-deﬁned timers which can be used to generate an interrupt once per second or once per minute. These are deﬁned in register Control_2 (01h).

8.1 Register overview

either bit-wise or standard binary. Table 4. Register overview

8.2 Reset

the oscillator pins OSCI or OSCO to ground. Table 5. Register reset value power-up and unchanged by subsequent resets.

32.768 kHz on pin CLKOUT active
Power-on reset override available to be set
24 hour mode is selected The SPI-bus is initialized whenever the chip enable pin CE is inactive (LOW).

8.2.1 Power-on reset override

has been built in to disable the POR and hence speed up the on-board test of the device. SPI-bus access. The override mode can be cleared by writing a logic 0 to bit POR_OVRD. Bit POR_OVRD must be set to logic 1 before a re-entry into the override mode is possible. accidental entry into the POR override mode. This is the recommended setting. Table 5. Register reset value …continued power-up and unchanged by subsequent resets.

8.3 Control registers

Table 6. Control_1 register (address 00h) bit description

5 STOP 0 RTC source clock runs

1 RTC divider chain ﬂip-ﬂops are asynchronously set

3 POR_OVRD 0 power-on reset override facility is disabled; set to

Table 7. Control_2 register (address 01h) bit description

6 SI 0 second interrupt is disabled

2 TF 0 no countdown timer interrupt generated -

0 TIE 0 no interrupt generated from the countdown timer

8.4 Time and date function

is used to simplify application use. An example is shown for register Minutes inTable8. [1] Hour mode is set by bit 12_24 in register Control_1. Table 8. BCD example Table 9. Register Seconds (address 02h) bit description

7 RF 0 clock integrity is guaranteed

Table 10. Register Minutes (address 03h) bit description Table 11. Register Hours (address 04h) bit description

5 AMPM 0 indicates AM

PCA2125_1 © NXP B.V. 2008. All rights reserved. which is exactly divisible by 4, including the year 00. [1] The weekday assignments can be re-deﬁned by the user. Table 12. Register Days (address 05h) bit description Table 13. Register Weekdays (address 06h) bit description Table 14. Weekday assignments Table 15. Register Months (address 07h) bit description Table 16. Month assignments

8.5 Alarm function

compared with the current minute, hour, day and weekday value. Table 17. Register Years (address 08h) bit description Table 16. Month assignments …continued

1 Hz tick

Table 18. Register Minute_alarm (address 09h) bit description

7 AEN_M 0 minute alarm is enabled

7 AEN_H 0 hour alarm is enabled

Table 20. Register Day_alarm (address 0Bh) bit description

7 AEN_D 0 day alarm is enabled

Table 21. Register Weekday_alarm (address 0Ch) bit description

7 AEN_W 0 weekday alarm is enabled

PCA2125_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 28 July 2008 12 of 36 NXP Semiconductors PCA2125 SPI Real-time clock/calendar Generation of interrupts from the alarm function is described inSection8.7.3.

8.5.1 Alarm ﬂag

When all enabled comparisons ﬁrst match, the alarm ﬂag bit AF is set. Bit AF will remain set until cleared by software. Once bit AF has been cleared it will only be set again when the time increments once more to match the alarm condition. Alarm registers which have their bit AENx at logic 1 are ignored. Figure8 shows an example for clearing bit AF , but leaving bit MSF and bit TF unaffected. The ﬂags are cleared by a write command, therefore bits 7, 6, 4, 1 and 0 must be written with their previous values. Repeatedly re-writing these bits has no inﬂuence on the functional behavior. Fig 7. Alarm function block diagram 001aaf902 WEEKDAY ALARM WEEKDAY AEN WEEKDAY TIME DAY ALARM DAY AEN DAY TIME HOUR ALARM HOUR AEN HOUR TIME MINUTE ALARM MINUTE AEN MINUTE TIME check now signal set alarm flag, AF MINUTE AEN = 1 example Example where only the minute alarm is used and no other interrupts are enabled. Fig 8. Alarm ﬂag timing 001aaf903 44 45 45minute alarm minutes counter AF INT when AIE = 1

8.6 Timer functions

which can be used to generate an interrupt once per second or once per minute. control the timer function and output.

8.6.1 Second and minute interrupt

Table 22. Flag location in register Control_2 Table 23. Example to clear only AF (bit 3) in register Control_2 Table 24. Register Timer_control (address 0Eh) bit description Table 25. Register Countdown_timer (address 0Fh) bit description

PCA2125_1 © NXP B.V. 2008. All rights reserved. pulse will still be generated. identify the source of the interrupt such as the minute/second or countdown timer. Bit TI_TP is set to logic 1 resulting in1⁄64 Hz wide interrupt pulse. Table 26. Effect of bits MI and SI onINT generation

8.6.2 Countdown timer function

1⁄60 Hz), and enables or disables the timer. [1] When not in use, bits CTD[1:0] must be set to1⁄60 Hz for power saving. will result in a corresponding deviation in timings. This is not applicable to interface timing. Table 27. Effect of bits MI and SI on bit MSF Table 28. Bits CTD1 and CTD0 for timer frequency selection and countdown timer

PCA2125_1 © NXP B.V. 2008. All rights reserved. loaded on subsequent timer periods. this mode selection and the interrupt output can be disabled with bit TIE. Table 29. First period delay for timer counter value n

4096 Hz n n + 1

64 Hz n n + 1

1 Hz (n − 1) +

8.6.3 Timer ﬂags

command, therefore bits 7, 6, 4, 1 and 0 must be written with their previous values. Repeatedly re-writing these bits has no inﬂuence on the functional behavior. Clearing the alarm ﬂag (bit AF) operates in exactly the same way; seeSection8.5.1.

8.7 Interrupt output

countdown timer and alarm function. status of the interrupt ﬂags (bits TF and MSF). Table 30. Flag location in register Control_2 Table 31. Example to clear only TF (bit 2) in register Control_2 Table 32. Example to clear only MSF (bit 5) in register Control_2 Table 33. Example to clear both TF and MSF (bits 2 and 5) in register Control_2

PCA2125_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 28 July 2008 18 of 36 NXP Semiconductors PCA2125 SPI Real-time clock/calendar Remark: Note that the interrupts from the three groups are wired-OR, meaning they will mask one another; seeFigure11.

8.7.1 Minute and second interrupts

The pulse generator for the minute/second interrupt operates from an internal 64 Hz clock and consequently generates a pulse of1⁄64 second duration. If the MSF ﬂag is clear before the end of theINT pulse, then theINT pulse is shortened. This allows the source of a system interrupt to be cleared immediately it is serviced i.e. the system does not have to wait for the completion of the pulse before continuing; see Figure12. Instructions for clearing MSF are given inSection8.6.3. When bits SI, MI, TIE and AIE are all disabled, pinINT will remain high-impedance. Fig 11. Interrupt scheme 001aaf907 SECONDS COUNTER SI MSF: MINUTE SECOND FLAG CLEAR SET PULSE GENERATOR 1 CLEAR TRIGGER TE SI MI MINUTES COUNTER COUNTDOWN COUNTER MI from interface: clear MSF to interface: read MSF AF: ALARM FLAG CLEAR SET to interface: read AF TF: TIMER CLEAR SET PULSE GENERATOR 2 CLEAR TRIGGER TIE INT from interface: clear TF from interface: clear AF set alarm flag, AF to interface: read TF TI_TP AIE

8.7.2 Countdown timer interrupts

Generation of interrupts from the countdown timer is controlled via bit TIE; seeTable7. [1] n = loaded countdown value. Timer stopped when n = 0. Figure13. Instructions for clearing TF are given inSection8.6.3. (1) Indicates normal duration ofINT pulse (bit TI_TP = 1). Table 34. INT operation (bit TI_TP = 1)

PCA2125_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 28 July 2008 20 of 36 NXP Semiconductors PCA2125 SPI Real-time clock/calendar The timing shown for clearing bit TF inFigure13 is also valid for the non-pulsed interrupt mode i.e. when bit TI_TP = 0, where the pulse can be shortened by setting bit TIE = 0.

8.7.3 Alarm interrupts

Generation of interrupts from the alarm function is controlled via bit AIE. If bit AIE is enabled, the INT pin follows the status of bit AF . Clearing bit AF will immediately clearINT. No pulse generation is possible for alarm interrupts; seeFigure14. (1) Indicates normal duration ofINT pulse (bit TI_TP = 1). Fig 13. Example of shortening theINT pulse by clearing the TF ﬂag 001aaf909 01countdown counter TF INT SCL instruction n CLEAR INSTRUCTION 8th clock (1) Example where only the minute alarm is used and no other interrupts are enabled. Fig 14. AF timing 001aaf910 minute counter minute alarm AF INT SCL instruction CLEAR INSTRUCTION 8th clock

8.8 Clock output

input to a charge pump, or for calibration of the oscillator. generation, all clock frequencies, except 32.768 kHz, have a duty cycle of 50 : 50. [1] Duty cycle deﬁnition: HIGH-level time (%) : LOW-level time (%).

8.9 External clock test mode

up test conditions and control the operation of the RTC. to 0. STOP must be cleared before the prescaler can operate again. on pin CLKOUT. Thereafter, every 64 positive edges will cause a 1 second increment. entering the test mode, no assumption as to the state of the prescaler can be made. Table 35. CLKOUT frequency selection

111 CLKOUT = LOW

PCA2125_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 28 July 2008 22 of 36 NXP Semiconductors PCA2125 SPI Real-time clock/calendar 1. Set EXT_TEST test mode (register Control_1, bit EXT_TEST = 1). 2. Set STOP (register Control_1, bit STOP = 1). 3. Clear STOP (register Control_1, bit STOP = 0). 4. Set time registers to desired value. 5. Apply 32 clock pulses to pin CLKOUT. 6. Read time registers to see the ﬁrst change. 7. Apply 64 clock pulses to pin CLKOUT. 8. Read time registers to see the second change. Repeat steps 7 and 8 for additional increments.

8.10 STOP bit function

The STOP bit function allows the accurate starting of the time circuits. The stop function will cause the upper part of the prescaler (F2 to F14) to be held at reset, thus no 1 Hz ticks will be generated. The time circuits can then be set and will not increment until the stop is released; see Figure15. Stop will not affect the output of 32768 Hz, 16384 Hz or 8192 Hz; seeSection8.8. The lower two stages of the prescaler (F0 and F1) are not reset and because the SPI-bus is asynchronous to the crystal oscillator, the accuracy of re-starting the time circuits will be between 0 and one 8192 Hz cycle; see Figure16. Fig 15. Stop bit functional diagram Fig 16. STOP bit release timing 001aaf911 OSC 32768 Hz 16384 Hz OSC STOP DETECTOR F0 F1 F13 RES F14 RES RES 2 Hz 512 Hz 16384 Hz 8192 Hz 0 µs to 122 µs

1 XX-0 0000 0000 0000 12:45:12 prescaler is reset; time circuits are frozen

1 XX-0 0000 0000 0000 08:00:00 prescaler is reset; time circuits are frozen

0 XX-0 0000 0000 0000 08:00:00 prescaler is now running

PCA2125_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 28 July 2008 25 of 36 NXP Semiconductors PCA2125 SPI Real-time clock/calendar InFigure20 the Months and Y ears registers are read. In this example, pins SDI and SDO are not connected together. In this conﬁguration, it is important that pin SDI is never left ﬂoating: it must always be driven either HIGH or LOW. If pin SDI is left open, high I DD currents will result. Fig 19. Serial bus write example 001aaf915 xxaddress counter CE SDI SCL 02 03 04 seconds data 45BCD minutes data 10BCDR/W addr 02HEX Fig 20. Serial bus read example 001aaf916 xxaddress counter CE SDO SDI SCL 07 08 09 months data 11BCD years data 06BCDR/W addr 07HEX

PCA2125_1 © NXP B.V. 2008. All rights reserved. [1] HBM: Human Body Model, according to JESD22-A114. [2] MM: Machine Model, according to JESD22-A115. [3] CDM: Charged-Device Model, according to JESD22-C101. [4] Latch-up testing, according to JESD78. Table 39. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).

PCA2125_1 © NXP B.V. 2008. All rights reserved. [1] For reliable oscillator start at power-up: VDD =V DD(min) + 0.3 V. [2] Timer source clock =1⁄60 Hz; voltage on pins CE, SDI and SCL at VDD or VSS . [1] Bus will be held up by bus capacitance; use RC time constant with application values. Table 40. Static characteristics …continued Table 41. Dynamic characteristics input voltage swing of VSS to VDD .

PCA2125_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 28 July 2008 29 of 36 NXP Semiconductors PCA2125 SPI Real-time clock/calendar Fig 22. SPI interface timing 001aag900 R/W SA2 RA0 b7 b6 b0 b7 b6 b0 b0b6b7SDI SDO SDO Hi Z Hi Z SDI SCL CE WRITE READ tw(CE) 80% 20% tclk(L) tf th(CE) trec(CE) tdis(SDO)td(R)SDO tt(SDI-SDO) tr th tsu tclk(H) tsu(CE)

13.1 Application diagram

13.2 Quartz frequency adjustment

Method 1: ﬁxed OSCI capacitor A ﬁxed capacitor can be used whose value can be determined by evaluating the average capacitance necessary for the application layout; seeFigure23. The frequency is best measured via the 32.768 kHz signal at pin CLKOUT available after power-on. The frequency tolerance depends on the quartz crystal tolerance, the capacitor tolerance and the device-to-device tolerance (on average±5 × 10 −6). An average deviation of±5 minutes per year can be easily achieved. 2. Method 2: OSCI trimmer Fast setting of a trimmer is possible using the 32.768 kHz signal at pin CLKOUT available after power-on. 3. Method 3: OSCO output Direct measurement of OSCO output (accounting for test probe capacitance). 14. Test information

14.1 Quality information

This product has been qualiﬁed in accordance with the Automotive Electronics Council (AEC) standard Q100 - Stress test qualiﬁcation for integrated circuits, and is suitable for use in automotive applications. The 1 farad capacitor is used as a standby and back-up supply. With the RTC in its minimum power conﬁguration i.e. timer off and CLKOUT off, the RTC can operate for several weeks. Fig 23. Application diagram 001aaf918 OSCI 1 F supercapacitor OSCO INT VSS VDD CLKOUT CE SCL SDI SDO PCA2125

PCA2125_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 28 July 2008 31 of 36 NXP Semiconductors PCA2125 SPI Real-time clock/calendar 15. Package outline Fig 24. Package outline SOT402-1 (TSSOP14) UNIT A 1 A 2 A 3 bp cD (1) E (2) (1)eH E LL p QZ ywv q REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.72 0.38 o o0.13 0.10.21 DIMENSIONS (mm are the original dimensions) Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 SOT402-1 MO-153 99-12-27 03-02-18 w M bp D Z e 0.25 14 8 q AA 1 A 2 Lp Q detail X L (A )3 H E E c v M A XA y 0 2.5 5 mm scale TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 A max. 1.1 pin 1 index

PCA2125_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 28 July 2008 32 of 36 NXP Semiconductors PCA2125 SPI Real-time clock/calendar 16. Handling information Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be completely safe you must take normal precautions appropriate to handling MOS devices; see JESD625-A and/or IEC61340-5. 17. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reﬂow soldering description”.

17.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high densities that come with increased miniaturization.

17.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:

Through-hole components
Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reﬂow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature proﬁle. Leaded packages, packages with solder balls, and leadless packages are all reﬂow solderable. Key characteristics in both wave and reﬂow soldering are:
Board speciﬁcations, including the board ﬁnish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering

17.3 Wave soldering

Key characteristics in wave soldering are:

Process issues, such as application of adhesive and ﬂux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave
Solder bath speciﬁcations, including temperature and impurities

17.4 Reﬂow soldering

Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to higher minimum peak temperatures (see Figure25) than a SnPb process, thus reducing the process window
Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board
Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classiﬁed in accordance with Table42 and43 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reﬂow soldering, seeFigure25.

Table 42. SnPb eutectic process (from J-STD-020C) Table 43. Lead-free process (from J-STD-020C)

PCA2125_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 28 July 2008 35 of 36 NXP Semiconductors PCA2125 SPI Real-time clock/calendar 19. Legal information 20. Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Deﬁnitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

20.1 Deﬁnitions

Draft —The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modiﬁcations or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet —A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the full data sheet shall prevail.

20.2 Disclaimers

General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes —NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation speciﬁcations and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use —NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications —Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the speciﬁed use without further testing or modiﬁcation. Limiting values —Stress above one or more limiting values (as deﬁned in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale —NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/proﬁle/terms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conﬂict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license —Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

20.3 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 21. Contact information For more information, please visit:http://www.nxp.com For sales ofﬁce addresses, please send an email to:salesaddresses@nxp.com Document status[1][2] Product status[3] Deﬁnition Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development. Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation. Product [short] data sheet Production This document contains the product speciﬁcation.

NXP Semiconductors PCA2125 SPI Real-time clock/calendar © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 28 July 2008 Document identifier: PCA2125_1 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 22. Contents

Product Information

PCA2125TS specifications and overview.

Summary

SPI Real-time clock/calendar Rev. 01-28 July 2008

Description

SPI Real-time clock/calendar Rev. 01-28 July 2008

Source title PCA2125TS Datasheet(PDF) - NXP Semiconductors

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