PC87364-XXX/VLA

PC87364 NSC | Alldatasheet

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www.national.com PC87364 128-Pin LPC SuperI/O with Extended Wake-Up and Protection Support PRELIMINARY January 10, 1999 PC87364 128-Pin LPC SuperI/O with Extended Wake-Up and Protection Support General Description The PC87364, a member of National Semiconductor’s 128- pin LPC SuperI/O family, introduces wake-up support for a wide range of wake-up events, and new hardware and sof- ware features to protect the system design. The PC87364 provides support for 51 GPIO ports, many with Assert IRQ/ SMI/PWUREQ capability. It is PC99 and ACPI compli- ant, and offers a single-chip solution to the most commonly used PC I/O peripherals. The PC87364 also incorporates: Fan Speed Control and Monitor (FSCM) for three fans, a Floppy Disk Controller (FDC), a Keyboard and Mouse Controller (KBC), a full IEEE

1284 Parallel Port, two enhanced Serial Ports (UARTs), one

with Infrared (IR) support, an ACCESS.bus ® Interface (ACB), System Wake-Up Control (SWC), General-Purpose Input/Output (GPIO) support for 51 ports, Interrupt Serializer for Parallel IRQs and an enhanced WATCHDOG timer. Outstanding Features

• Extended Wake-Up support, including legacy/ACPI power button support, direct power supply control in response to wake-up events, power-fail recovery
• Protection features, including I/O access lock, chassis hood lock/unlock, chassis intrusion detection, GPIO pin attribute lock and pin configuration lock
• Fan Speed Control and Monitor for three fans
• Serial IRQ support (15 options)
• Interrupt Serializer (11 Parallel IRQs to Serial IRQ)
• Bus interface, based on Intel’sLPC Interface Specifi- cationRevision 1.0, September 29th, 1997
• ACCESS.busInterface, SMBus physical layer compatible
• 51 GPIO Ports (39 standard, including 23 with Assert IRQ/SMI/PWUREQs interrupts; 12 VSB -powered)
• Blinking LEDs
• 128-pin PQFP Package Block Diagram System Wake-Up Serial Port 2 IEEE 1284 Wake-Up Parallel Port PortsKeyboard & Mouse I/FSCL ACCESS.bus Floppy Disk Controller Floppy Drive Interface Keyboard & Serial Infrared Interface Interface Control Events Bus Interface LPC Interface I/O

3 Control

Control & MonitorInterface Mouse Controller with IR GPIO Ports

3 Monitor

© 1999 National Semiconductor Corporation ACCESS.bus® is a registered trademark of Digital Equipment Corporation. I2C® is a registered trademark of Philips Corporation. IBM®, MicroChannel®, PC-AT® and PS/2® are registered trademarks of International Business Machines Corporation. Microsoft® and Windows® are registered trademarks of Microsoft Corporation. TRI-STATE® is a registered trademark of National Semiconductor Corporation. WATCHDOG‰ is a trademark of National Semiconductor Corporation. SMBus® is a registered trademark of Intel Corporation.

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Features

• Extended Wake-Up — Legacy and ACPI power button support — Direct power supply control in response to wake-up events — Power-fail recovery
• Protection — Chassis intrusion detection (CHASI, CHASO) — Chassis hood lock and unlock control — Access lock to I/O ports (XLOCK) — GPIO pin attribute lock — Pin configuration lock
• 51 General-Purpose I/O (GPIO) Ports — 39 standard, with Assert IRQ/SMI/PWUREQ for 23 ports — 12 VSB -powered — Programmable drive type for each output pin (open- drain, push-pull or output disable) — Programmable option for internal pull-up resistor on each input pin — Output lock option — Input debounce mechanism
• Fan Speed Control and Fan Speed Monitor (FSCM) — Supports different fan types — Speed monitoring for three fans ❏ Digital filtering of the tachometer input signal ❏ Alarm for fan slower than programmable thresh- old speed ❏ Alarm for fan stop — Three speed control lines with Pulse Width Modula- tion (PWM) ❏ Output signal in the range of 6 Hz to 93.75 KHz ❏ Duty cycle resolution of 1/256
• Interrupt Serializer — 11 Parallel IRQs to Serial IRQ — IRQ sharing with internal IRQs
• LPC System Interface — Synchronous cycles, up to 33 MHz bus clock — 8-bit I/O cycles — Up to four DMA channels — 8-bit DMA cycles — Basic read, write and DMA bus cycles are 13 clock cycles long
• PC99 and ACPI Compliant — PnP Configuration Register structure — Flexible resource allocation for all logical devices ❏ Relocatable base address ❏ 15 IRQ routing options ❏ 4 optional 8-bit DMA channels (where applicable)
• Floppy Disk Controller (FDC) — Programmable write protect — FM and MFM mode support — Enhanced mode command for three-mode Floppy Disk Drive (FDD) support — Perpendicular recording drive support for 2.88 MB — Burst and non-burst modes — Full support for IBM Tape Drive register (TDR) im- plementation of AT and PS/2 drive types — 16-byte FIFO — Software compatible with the PC8477, which con- tains a superset of the FDC functions in the microDP8473, the NEC microPD765A and the N82077 — High-performance, digital separator — Standard 5.25” and 3.5” FDD support
• Parallel Port — Software or hardware control — Enhanced Parallel Port (EPP) compatible with new version EPP 1.9 and IEEE 1284 compliant — EPP support for version EPP 1.7 of the Xircom spec- ification — EPP support as mode 4 of the Extended Capabilities Port (ECP) — IEEE 1284 compliant ECP , including level 2 — Selection of internal pull-up or pull-down resistor for Paper End (PE) pin — PCI bus utilization reduction by supporting a de- mand DMA mode mechanism and a DMA fairness mechanism — Protection circuit that prevents damage to the paral- lel port when a printer connected to it powers up or is operated at high voltages, even if the device is in power-down — Output buffers that can sink and source 14 mA
• Serial Port 1 (UART1) — Software compatible with the 16550A and the 16450 — Shadow register support for write-only bit monitoring — UART data rates up to 1.5 Mbaud
• Serial Port 2 with Infrared (UART2) — Software compatible with the 16550A and the 16450 — Shadow register support for write-only bit monitoring — UART data rates up to 1.5 Mbaud — HP-SIR — ASK-IR option of SHARP-IR — DASK-IR option of SHARP-IR — Consumer Remote Control supports RC-5, RC-6, NEC, RCA and RECS 80 — Non-standard DMA support− 1 or 2 channels — PnP dongle support

Features(Continued) www.national.com

• Keyboard and Mouse Controller (KBC) — 8-bit microcontroller — Software compatible with the 8042AH and PC87911 microcontrollers — 2 KB custom-designed program ROM — 256 bytes RAM for data — Five programmable dedicated open-drain I/O lines — Asynchronous access to two data registers and one status register during normal operation — Support for both interrupt and polling — 93 instructions — 8-bit timer/counter — Support for binary and BCD arithmetic — Operation at 8 MHz,12 MHz or 16 MHz (programma- ble option) — Can be customized by using the PC87323, which in- cludes a RAM-based KBC as a development plat- form for KBC code
• ACCESS.bus Interface (ACB) — Serial interface compatible with SMBus physical layer — Compatible with Philips’ I2C ® — ACB master and slave — Supports polling and interrupt controlled operation — Optional internal pull-up on SDA and SCL pins
• WATCHDOG Timer — Times out the system based on user-programmable time-out period — System power-down capability for power saving — User-defined trigger events to restart WATCHDOG — Optional routing of WATCHDOG output on IRQ and/or SMI lines
• System Wake-Up Control (SWC) — Power-up request upon detection of Keyboard, Mouse, RI1,RI2,RING activity and General-Pur- pose Input Events, as follows: ❏ Preprogrammed Keyboard or Mouse sequence ❏ External modem ring on serial port ❏ Ring pulse or pulse train on theRING input signal ❏ Preprogrammed CEIR address in a preselected standard (NEC, RCA or RC-5) ❏ General-Purpose Input Events ❏ IRQs of internal logical devices — Optional routing of power-up request on IRQ, SMI and/orPWBT OUT — Battery-backed event configuration — Programmable V SB -powered output for blinking LEDs (LED1, LED2) control
• Clock Sources — 48 MHz clock input — LPC clock, up to 33 MHz — On-chip low frequency clock generator for wake-up
• Power Supplies — 3.3V supply operation — Main (VDD ) — Standby (VSB ) — Battery backup (VBAT ) — All pins are 5V tolerant and back-drive protected, ex- cept LPC bus pins
• Strap Configuration — Base Address (BADDR) strap to determine the base address of the Index-Data register pair — Test strap to force the device into test mode (re- served for National Semiconductor use) — Power Supply and LED Configuration (PSLDC0,1) straps to determine the power suppy control func- tions and the V SB power-up defaults of LED2 — Power Supply On Polarity (PSONPOL) strap to set PSON active state and output type

4www.national.com Datasheet Revision Record Revision Date Status Comments September 1998 Draft 0.1 Specifcation subject to change without notice September 1998 Draft 0.2 Specifcation subject to change without notice October 1988 Draft 0.3 Specification subject to change without notice October 1998 Draft 0.4 Specification subject to change without notice January 1999 Preliminary 1.0 Specification subject to change without notice; Power Supply Control and LED sections in Chapter 2 are incomplete Item Topic Change/Correction Location

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1.0 Signal/Pin Connection and Description

2.0 Device Architecture and Configuration

Table of Contents(Continued) 6www.national.com

Table of Contents(Continued) 7 www.national.com 3.0 System Wake-Up Control (SWC)

3.4.7 Wake-Up Events Routing to

Table of Contents(Continued) 8www.national.com 4.0 Fan Speed Control 5.0 Fan Speed Monitor 6.0 General-Purpose Input/Output (GPIO) Port

Table of Contents(Continued) 9 www.national.com 7.0 WATCHDOG Timer (WDT) 8.0 ACCESS.bus Interface (ACB)

Table of Contents(Continued) 10www.national.com

9.0 Legacy Functional Blocks

10.0 Device Characteristics

Table of Contents(Continued) 11 www.national.com

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1.1 CONNECTION DIAGRAM

Plastic Quad Flatpack (PQFP), JEDEC xxx =Three character identifier for National data, and keyboard ROM and/or customer identification code 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 PC87364-xxx/VLA PD7 VSS VBAT MTR0 SLCT DIR STEP WD ATA DRATE0 TRK0 PE WGA TE RD ATA WP DENSEL INDEX GPIO17/DR1/IRSL3 100 101 102 103 104 105 106 107 108 GPIO43 GPIO42 VDD VSB PWUREQ GPIO16/MTR1/IRSL2 DR0 GPIO34/FANOUT2/ CHLOCK GPIO01/FANOUT1 GPIO47 GPIO46 GPIO45 BUSY_ W AIT HDSEL DSKCHG GPIO44 ACK ERR AFD_ DSTRB PD1 STB_ WRITE INIT PD6 PD5 PD4 PD3 SLIN_ASTRB PD2 VSS PD0 GPIO00/FANIN1 GPIO33/FANIN2/CHUNLOCK VDD VSS VDD VSS VDD CHASI Note 1. GPIOE1 GPIOE2/LED1 LAD1 LAD3 LAD2 LRESET LCLK LFRAME LAD0 LDRQ SERIRQ GPIO32/PIRQ15/P16/IRSL1 DTR1_BOUT1/BADDR RI1 DCD1 SOUT1/PSLDC0 DSR1 SIN1 R TS1/TEST CTS1 DTR2_BOUT2/PSONPOL RI2 DCD2 SOUT2/PSLDC1 DSR2 SIN2 R TS2 CTS2 GPIO13/SDA GPIO14/WDO KBDAT KBCLK MCLK MDAT KBRST/GPIO06 GA20/GPIO07 Order Number PC87364-xxx/VLA See NS Package Number VLA128A GPIO41 GPIOE3/LED2 GPIOE5/CHASO GPIO03/FANOUT0 GPIO02/FANIN0 GPIE6/IRRX2_IRSL0 GPIE7/IRRX1 GPO15/IRTX GPIO10/SMI GPIOE4/RING GPIO05/P17 GPIO04/P12 GPIO11/XLOCK GPIO12/SCL CLKIN GPIOE0 SLPS5 GPIO40 NC NC GPO37 GPO36 GPIO27/PIRQ11 GPIO25/PIRQ9 GPIO26/PIRQ10 GPIO24/PIRQ7 GPIO23/PIRQ6 GPIO21/PIRQ4 GPIO22/PIRQ5 GPIO20/PIRQ3 GPIO30/PIRQ12 GPIO31/PIRQ14 PSON /GPOS1 PWBT OUT/GPOS0 PWBTIN/GPIS2 SLPS3/GPIS3 NC Note 1. For correct operation, this pin must be tied to VSS when not used.

1.0 Signal/Pin Connection and Description(Continued)

1.2 BUFFER TYPES AND SIGNAL/PIN DIRECTORY

• MUX - Multiplexed, denoted by a slash (/) between pins in the diagram in Section 1.1. Pins are shared between two different functions. Each function is associated with different board connectivity, and normally, the function selection is determined by the board design and cannot be changed dynamically. The multiplexing options must be configured by the BIOS upon power-up, in order to comply with the board implementation.
• MM - Multiple Mode, denoted by an underscore (_) between pins in the diagram in Section 1.1. Pins have two or more modes of operation within the same function. These modes are associated with the same external (board) con- nectivity. Mode selection may be controlled by the device driver, through the registers of the functional block, and do not require a special BIOS setup upon power-up. These pins are not considered multiplexed pins from the SuperI/O configuration perspective. The mode selection method (registers and bits) as well as the signal specification in each mode, are described within the functional description of the relevant functional block.

Table 2. SIgnal/Pin Directory Table 1. Buffer Types

14www.national.com CHLOCK 1 Protection 1.4.11 O 12/12 14.2.9 MUX CHUNLOCK 128 Protection 1.4.11 O 12/12 14.2.9 MUX CLKIN 22 Clock 1.4.3 INT 10.2.5 CTS1 100 Serial Port 1 1.4.14 INTS 10.2.6 CTS2 108 Serial Port 2 1.4.14 INTS 10.2.6 DCD1 95 Serial Port 1 1.4.14 INTS 10.2.6 DCD2 103 Serial Port 2 1.4.14 INTS 10.2.6 DENSEL 75 FDC 1.4.5 O 2/12 10.2.8 DRA TE0 74 FDC 1.4.5 O 3/6 10.2.8 DSKCHG 60 FDC 1.4.5 INT 10.2.5 DSR1 96 Serial Port 1 1.4.14 INTS 10.2.6 DSR2 104 Serial Port 2 1.4.14 INTS 10.2.6 DSTRB See AFD_ DSTRB DTR1_BOUT1 101 Serial Port 1 1.4.14 O 3/6 10.2.8 MUX, MM DTR2_BOUT2 109 Serial Port 2 1.4.14 O 3/6 10.2.8 MUX, MM ERR 91 Parallel Port 1.4.11 INT 10.2.5 FANIN0 4 Fan Speed 1.4.4 INTS 10.2.6 MUX FANIN1 2 Fan Speed 1.4.4 INTS 10.2.6 MUX FANIN2 128 Fan Speed 1.4.4 INTS 14.2.6 MUX FANOUT0 5 Fan Speed 1.4.4 O 2/14 10.2.8 MUX FANOUT1 3 Fan Speed 1.4.4 O 2/14 10.2.8 MUX FANOUT2 1 Fan Speed 1.4.4 O 2/14 14.2.8 MUX GPIE6-7 58-59 System Wake-Up 1.4.16 INTS 10.2.6 MUX GPIO10 GPIO11-14 GPO15 GPIO16-17 53-56 69, 71 GPIO Port 1.4.7 IN GPIO30-33 GPIO34 125-128 Signal Pin(s) Functional Group DC Characteristics MUX Name Section Buffer Type Section

15 www.national.com GPIS2-3 35-36 System Wake-Up 1.4.16 INTS 10.2.6 MUX INDEX 73 FDC 1.4.5 INT 10.2.5 IRRX1 59 Infrared 1.4.8 INTS 10.2.6 MUX IRSL3 71 Infrared 1.4.8 INT 10.2.5 MUX IRTX 57 Infrared 1.4.8 O 6/12 10.2.8 MUX LED1, LED2 25, 26 System Wake-Up 1.4.16 O 12/12 10.2.8 MUX LCLK 11 Bus Interface 1.4.2 INPCI 10.2.2 LDRQ 13 Bus Interface 1.4.2 O PCI 10.2.7 LFRAME 14 Bus Interface 1.4.2 INPCI 10.2.2 LRESET 10 Bus Interface 1.4.2 INPCI 10.2.2 PD7-5 PD4-3, PD2, PD1 PD0 80-82 85-86 88, 90 Parallel Port 1.4.11 IN PE 77 Parallel Port 1.4.11 INT 10.2.5 PIRQ3-7 PIRQ9-12 PIRQ14-15 117-121 122-125 126-127 Bus Interface 1.4.2 IN TS 10.2.6 MUX Signal Pin(s) Functional Group DC Characteristics MUX Name Section Buffer Type Section

16www.national.com PSLDC0 99 Strap Configuration 1.4.15 INSTRP 10.2.4 MUX PSLDC1 107 Strap Configuration 1.4.15 INSTRP 10.2.4 MUX PSONPOL 109 Strap Configuration 1.4.15 INSTRP 10.2.4 MUX PWBTIN 35 System Wake-Up 1.4.16 INTS 10.2.6 MUX PWBT OUT 33 System Wake-Up 1.4.16 OD 12 10.2.9 MUX PWUREQ 32 System Wake-Up 1.4.16 OD 6 10.2.9 RD ATA 62 FDC 1.4.5 INT 10.2.5 RI1 102 Serial Port 1 1.4.14 INTS 10.2.6 RI2 110 Serial Port 2 1.4.14 INTS 10.2.6 RING 27 System Wake-Up 1.4.16 INTS 10.2.6 MUX RTS1 98 Serial Port 1 1.4.14 O 3/6 10.2.8 MUX RTS2 106 Serial Port 2 1.4.14 O 3/6 10.2.8 SIN1 97 Serial Port 1 1.4.14 INTS 10.2.6 SIN2 105 Serial Port 2 1.4.14 INTS 10.2.6 SLCT 76 Parallel Port 1.4.11 INT 10.2.5 SLPS3,5 36,37 System Wake-Up 1.4.16 INTS 10.2.6 MUX (SLPS3) SMI 21 Bus Interface 1.4.2 OD 12 10.2.9 MUX SOUT1 99 Serial Port 1 1.4.14 O 3/6 10.2.8 MUX SOUT2 107 Serial Port 2 1.4.14 O 3/6 10.2.8 MUX TEST 98 Strap Configuration 1.4.15 INSTRP 10.2.4 MUX TRK0 64 FDC 1.4.5 INT 10.2.5 VBAT 30 Power and Ground 1.4.12 INULR N/A VDD 20, 52, 83, 115 Power and Ground 1.4.12 PWR N/A VSB 31 Power and Ground 1.4.12 PWR N/A VSS 19, 51, 84, 116 Power and Ground 1.4.12 GND N/A W AIT See BUSY_ W AIT Signal Pin(s) Functional Group DC Characteristics MUX Name Section Buffer Type Section

17 www.national.com WP 63 FDC 1.4.5 INT 10.2.5 WRITE See STB_ WRITE XLOCK 53 Protection 1.4.11 INT 10.2.5 MUX Signal Pin(s) Functional Group DC Characteristics MUX Name Section Buffer Type Section

1.3 PIN MULTIPLEXING

can be chosen on one pin only per group. Table 3. Pin Multiplexing Configuration

1 GPIO34 I/O SIOCF2, Bits 1-0 = 00 FANOUT2 O SIOCF2, Bits 1-0 = 01

2 GPIO00 I/O SIOCF2, Bit 2 = 0 FANIN1 I SIOCF2, Bit 2 = 1

3 GPIO01 I/O SIOCF2, Bit 3 = 0 FANOUT1 O SIOCF2, Bit 3 = 1

4 GPIO02 I/O SIOCF2, Bit 4 = 0 FANIN0 I SIOCF2, Bit 4 = 1

5 GPIO03 I/O SIOCF2, Bit 5 = 0 FANOUT0 O SIOCF2, Bit 5 = 1

6 GPIO04 I/O SIOCF2, Bit 6 = 0 P12 I/O SIOCF2, Bit 6 = 1

7 GPIO05 I/O SIOCF2, Bit 7 = 0 P17 I/O SIOCF2, Bit 7 = 1

8 KBRST (P20) SIOCF3, Bit 0 = 1 GPIO06 I/O SIOCF3, Bit 0 = 0

9 GA20 (P21) SIOCF3, Bit 1 = 1 GPIO07 I/O SIOCF3, Bit 1 = 0

21 GPIO10 I/O SIOCF3, Bit 2 = 0

27 GPIOE4 I/O SIOCFA, Bits 5-4 = 00 RING I SIOCFA, Bits 5-4 = 01

28 GPIOE5 I/O SIOCFA, Bit 6 = 0 CHASO O SIOCFA, Bit 6 =1

53 GPIO11 I/O SIOCF3, Bit 4 = 0 XLOCK I SIOCF3, Bit 4 = 1

54 GPIO12 I/O SIOCF3, Bit 5 = 0 SCL I/O SIOCF3, Bit 5 = 1

55 GPIO13 I/O SIOCF3, Bit 5 = 0 SDA I/O SIOCF3, Bit 5 = 1

56 GPIO14 I/O SIOCF3, Bit 6 = 0

57 GPO15 O SIOCF3, Bit 7 = 0 IRTX O SIOCF3, Bit 7 = 1

58 GPIE6 I SIOCFB, Bit 0 = 0 IRRX2_IRSL0 I/O SIOCFB, Bit 0 = 1

59 GPIE7 I SIOCFB, Bit 1 = 0 IRRX1 I SIOCFB, Bit 1 = 1

69 GPIO16 I/O SIOCF4, Bits 1-0 = 00

71 GPIO17 I/O SIOCF4, Bits 3-2 = 00

117 GPIO20 I/O SIOCF4, Bits 4,P

19 www.national.com 123 GPIO26 I/O SIOCF4, Bits 4,PNote 1.=0 0 PIRQ10 I SIOCF4, Bits 4,P = X1 124 GPIO27 I/O SIOCF4, Bits 4,PNote 1.=0 0 PIRQ11 I SIOCF4, Bits 4,P = X1 125 GPIO30 I/O SIOCF4, Bits 5,PNote 1.=0 0 PIRQ12 I SIOCF4, Bits 5,P = X1 126 GPIO31 I/O SIOCF4, Bits 5,PNote 1.=0 0 PIRQ14 I SIOCF4, Bits 5,P = X1 127 GPIO32 I/O SIOCF4, Bits 7,6,PNote 1.= 000 P16 I/O SIOCF4, Bits 7,6,PNote 1.= 010 IRSL1 I/O SIOCF4, Bits 7,6,PNote 1.= 100 PIRQ15 I SIOCF4, Bits 7,6,PNote 1.= XX1

128 GPIO33 I/O SIOCF5, Bits 1-0 = 00 FANIN2 I SIOCF5, Bits 1-0 = 10

CHUNLOCK O SIOCF5, Bits 1-0 = 11 Note 1. The signal selected on each pin is determined during VSB power-up by the PSLDC0,1 straps. Note 2. P = SIOCF1, Bit 6 (Pins 117-127 Select PIRQ) Pin(s) Default Alternate Signal I/O Configuration Signal I/O Configuration

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1.4 DETAILED SIGNAL/PIN DESCRIPTIONS

This section describes all signals, organized in functional groups. 1.4.1 ACCESS.bus Interface (ACB)

1.4.2 Bus Interface

1.4.3 Clock

1.4.4 Fan Speed Control and Monitor (FSCM)

Signal Pin(s) I/O Buffer Type Power Well Description SCL 54 I/O INSM /OD6 VDD ACCESS.bus Clock Signal.An internal pull-up is optional, depending upon the ACCESS.bus configuration register. SDA 55 I/O INSM /OD6 VDD ACCESS.bus Data Signal.An internal pull-up is optional, depending upon the ACCESS.bus configuration register. Signal Pin(s) I/O Buffer Type Power Well Description LAD0-3 15-18 I/O INPCI/OPCI VDD LPC Address-Data.Multiplexed command, address bi- directional data and cycle status. LCLK 11 I INPCI VDD LPC Clock. Practically the PCI clock (up to 33 MHz) LDRQ 13 O O PCI VDD LPC DMA Request . Encoded DMA request for LPC I/F . LFRAME 14 I INPCI VDD LPC Frame . Low pulse indicates the beginning of new LPC cycle or termination of a broken cycle. LRESET 10 I INPCI VDD LPC Reset. Practically the PCI system reset. PIRQ3-7 PIRQ9-12 PIRQ14-15 117-121 122-125 126-127 I IN TS VDD Parallel Interrupt.Converts Parallel Port interrupts into Serial Interrupts by means of the Interrupt Serializer. SERIRQ 12 I/O INPCI/OPCI VDD Serial IRQ.The interrupt requests are serialized over a single pin, where each internal IRQ signal is delivered during a designated time slot. SMI 21 OD OD 12 VDD System Management Interrupt Signal Pin(s) I/O Buffer Type Power Well Description CLKIN 22 I INT VDD Clock In.48 MHz clock input. Signal Pin(s) I/O Buffer Type Power Well Description FANIN0 FANIN1 FANIN2 128 I IN TS VDD Fan Inputs.Used to feed the fan’s tachometer pulse to the Fan Speed Monitor. The rising edge indicates the completion of a half (or full) revolution of the fan. FANOUT0 FANOUT1 FANOUT2 O O 2/14 VDD Fan Outputs.Pulse Width Modulation (PWM) signals, used to control the speed of cooling fans by controlling the voltage supplied to the fan’s motor.

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1.4.5 Floppy Disk Controller (FDC)

Signal Pin(s) I/O Buffer Type Power Well Description DENSEL 75 O O 2/12 VDD Density Select.Indicates that a high FDC density data rate (500 Kbps or 1 Mbps) or a low density data rate (250 or 300 Kbps) is selected. DENSEL polarity is controlled by bit 5 of the FDC Configuration Register. DIR 68 O OD 12,O 2/12 VDD Direction.Determines the direction of the Floppy Disk Drive (FDD) head movement (active = step in, inactive = step out) during a seek operation. During reads or writes, DIR is inactive. DR0 70 O OD 12,O 2/12 VDD Drive Select 0.Decoded drive select output signal.DR0 is controlled by bit 0 of the Digital Output Register (DOR). DR1 71 O OD 12,O 2/12 VDD Drive Select 1.Decoded drive select output signal.DR0 is controlled by bit 1 of the Digital Output Register (DOR). DRATE0 74 O O 3/6 VDD Data Rate 0.Reflects the value of bit 0 of the Configuration Control Register (CCR) or the Data Rate Select Register (DSR), whichever was written to last. Output from the pin is push-pull buffered. DSKCHG 60 I INT VDD Disk Change.Indicates if the drive door has been opened. The state of this pin is stored in the Digital Input Register (DIR). This pin can also be configured as the RGATE data separator diagnostic input signal via the MODE command. HDSEL 61 O OD 12,O 2/12 VDD Head Select.Determines which side of the FDD is accessed. Active low selects side 1, inactive selects side 0. INDEX 73 I INT VDD Index.Indicates the beginning of an FDD track. MTR0 72 O OD 12,O 2/12 VDD Motor Select 0.Active low, motor enable line for drives 0, controlled by bits D7-4 of the Digital Output Register (DOR). MTR1 69 O OD 12,O 2/12 VDD Motor Select 1.Active low, motor enable lines for drives 1, controlled by bits D7-4 of the Digital Output Register (DOR). RD ATA6 2 I INT VDD Read Data.Raw serial input data stream read from the FDD. STEP 67 O OD 12,O 2/12 VDD Step.Issues pulses to the disk drive at a software programmable rate to move the head during a seek operation. TRK0 64 I INT VDD Track 0.Indicates to the controller that the head of the selected floppy disk drive is at track 0. WD ATA6 6 O OD 12,O 2/12 VDD Write Data. Carries out the pre-compensated serial data that is written to the floppy disk drive. Pre-compensation is software selectable. WGA TE 65 O OD 12,O 2/12 VDD Write Gate.Enables the write circuitry of the selected disk drive. WGATE is designed to prevent glitches during power up and power down. This prevents writing to the disk when power is cycled. WP 63 I INT VDD Write Protected.Indicates that the disk in the selected drive is write protected. A software programmable configuration bit (FDC configuration at Index F0h, Logical Device 0) can force an active write-protect indication to the FDC, regardless of the status of this pin.

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1.4.6 General-Purpose Input/Output (GPIO) Ports

1.4.7 Infrared (IR)

Signal Pin/s I/O Buffer Type Power Well Description GPIO00-07 2-9 I/O INTS / OD 6,O 3/6 VDD General-Purpose I/O Port 0, bits 0-7.Each pin is configured in- dependently as input or I/O, with or without static pull-up, and with either open-drain or push-pull output type. The port support inter- rupt assertion and each pin can be enabled or masked as an inter- rupt source. GPIO10 GPIO11-14 GPO15 GPIO16-17 53-56 69, 71 I/O IN TS / OD 6,O 3/6 VDD General-Purpose I/O Port 1, bits 0-7.Same as Port 0. Bit 5 is output only with low output as default. GPIO20-27 117-124 I/O INTS / OD 6,O 3/6 VDD General-Purpose I/O Port 2, bits 0-7.Similar to port 0, but without the interrupt assertion capability. GPIO30-33 GPIO34 GPO36-37 125-128 41-42 I/O IN TS / OD 6,O 3/6 VDD General-Purpose I/O Port 3, bits 0-4,6,7.Similar to port 0, but without the interrupt assertion capability. Bit 5 is not implemented. GPIO40-47 43-50 I/O IN TS / OD 6,O 3/6 VDD General-Purpose I/O Port 4, bits 0-7.Same as Port 0. Signal Pin/s I/O Buffer Type Power Well Description IRRX1 59 I INTS VDD ,V SB IR Receive 1.Primary input to receive serial data from the IR transceiver. Monitored during power-off for wake-up event detection. IRRX2_IRSL0 58 I/O IN TS /O3/6 VDD ,V SB IRRX2 - IR Receive 2.Auxiliary IR receiver input to support a second transceiver. Monitored during power-off for wake-up event detection. IRSL3-0 IR Select. Output are used to control the IR transceivers. Input for PnP identification of plug-in IR transceiver (dongle). After reset, the dual-function IRSLX pins wake up in input mode. After the ID is read by the IR driver, they may be put into output mode. The output mode is controlled by Serial Port 2. IRSL1 127 I/O IN T/O3/6 VDD IRSL2 69 I/O INT/O3/6 VDD IRSL3 71 I INT VDD IRTX 57 O O 6/12 VDD IR Transmit.IR serial output data.

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1.4.8 Keyboard and Mouse Controller (KBC)

1.4.9 Parallel Port

Signal Pin/s I/O Buffer Type Power Well Description GA20 9 I/O INT/OD2 VDD Gate A20.KBC gate A20 (P21) output. KBCLK 111 I/O INTS /OD14 VDD ,V SB Keyboard Clock.Transfers the keyboard clock between the SuperI/O chip and the external keyboard using the PS/2 protocol. This pin is driven by the internal, inverted KBC P26 signal, and is connected internally to the T0 signal of the KBC. External pull-up resistor to 5V is required (for PS/2 compliance). The pin is monitored for wake-up event detection. To enable the activity during power off, it must be pulled up to Keyboard and Mouse standby voltage. KBDAT 112 I/O IN TS /OD14 VDD ,V SB Keyboard Data.Transfers the keyboard data between the SuperI/O chip and the external keyboard using the PS/2 protocol. This pin is driven by the internal, inverted KBC P27 signal, and is connected internally to KBC P10. External pull-up resistor to 5V is required (for PS/2 compliance). The pin is monitored for wake-up event detection. To enable the activity during power off, it must be pulled up to Keyboard and Mouse standby voltage. KBRST 8 I/O IN T/OD2 VDD KBD Reset. Keyboard Reset (P20) output. MCLK 113 I/O INTS /OD14 VDD ,V SB Mouse Clock. Transfers the mouse clock between the SuperI/O chip and the external keyboard using the PS/2 protocol. This pin is driven by the internal, inverted KBC P23 signal, and is connected internally to KBC T1. External pull-up resistor to 5V is required (for PS/2 compliance). The pin is monitored for wake-up event detection. To enable the activity during power off, it must be pulled up to Keyboard and Mouse standby voltage. MDAT 114 I/O IN TS /OD14 VDD ,V SB Mouse Data. Transfers the mouse data between the SuperI/O chip and the external keyboard using the PS/2 protocol. This pin is driven by the internal, inverted KBC P22 signal, and is connected internally to KBC P11. External pull-up resistor to 5V is required (for PS/2 compliance). The pin is monitored for wake-up event detection. To enable the activity during power off, it must be pulled up to Keyboard and Mouse standby voltage. P12, P16, P17 6,127,

7 I/O IN

I/O Port.KBC open-drain signal for general-purpose input and output, controlled by KBC firmware. Signal Pin/s I/O Buffer Type Power Well Description ACK 79 I INT VDD Acknowledge. Pulsed low by the printer to indicate that it has received data from the Parallel Port. AFD_ DSTRB 93 O OD 14,O 14/14 VDD AFD - Automatic Feed.When low, instructs the printer to automatically feed a line after printing each line. This pin is in TRI-STATE after a 0 is loaded into the corresponding control register bit. An external 4.7 KΩ pull-up resistor should be attached to this pin. DSTRB - Data Strobe (EPP).Active low, used in EPP mode to denote a data cycle. When the cycle is aborted, DSTRB becomes inactive (high). BUSY_ W AIT 78 I INT VDD Busy. Set high by the printer when it cannot accept another character. Wait.In EPP mode, the Parallel Port device uses this active low signal to extend its access cycle. ERR 91 I INT VDD Error.Set active low by the printer when it detects an error.

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1.4.10 Power and Ground

INIT 89 O OD 14,O 14/14 VDD Initialize.When low, initializes the printer. This signal is in TRI-STATE after a 1 is loaded into the corresponding control register bit. Use an external 4.7 KΩ pull-up resistor. PD7-5 PD4-3, PD2, PD1 PD0 80-82 85-86 88, 90 I/O IN OD 14,O 14/14 VDD Parallel Port Data.Transfer data to and from the peripheral data bus and the appropriate Parallel Port data register. These signals have a high current drive capability. PE 77 I IN T VDD Paper End.Set high by the printer when it is out of paper. This pin has an internal weak pull-up or pull-down resistor. SLCT 76 I INT VDD Select.Set active high by the printer when the printer is selected. SLIN_ASTRB 87 O OD 14,O 14/14 VDD SLIN - Select Input.When low, selects the printer. This signal is in TRI-STATE after a 0 is loaded into the corresponding control register bit. Uses an external 4.7 KΩ pull-up resistor. ASTRB - Address Strobe (EPP).Active low, used in EPP mode to denote an address or data cycle. When the cycle is aborted, ASTRB becomes inactive (high). STB_ WRITE 94 O OD 14,O 14/14 VDD STB - Data Strobe.When low, Indicates to the printer that valid data is available at the printer port. This signal is in TRI- STATE after a 0 is loaded into the corresponding control register bit. An external 4.7 KΩ pull-up resistor should be employed. WRITE - Write Strobe.Active low, used in EPP mode to denote an address or data cycle. When the cycle is aborted, WRITE becomes inactive (high). Signal Pin/s I/O Buffer Type Power Well Description VBAT 30 I INULR - Battery Power Supply.Provides battery back-up to the System Wake-Up Control registers, when VSB is lost (power-fail). The pin is connected to the internal logic through a series resistor for UL protection. VDD 20, 52, 83, 115 I PWR - Main 3.3V Power Supply VSB 31 I PWR - Standby 3.3V Power Supply.Provides power to the Wake-Up Control circuitry, while the main power supply is turned off. VSS 19, 51, 84, 116 I GND - Ground Signal Pin/s I/O Buffer Type Power Well Description

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1.4.11 Protection

1.4.12 Serial Port 1 and Serial Port 2

Signal Pin(s) I/O Buffer Type Power Well Description CHASI 29 I INC VPP Chassis Intrusion Input.Any change of this pin sets the intrusion detection. For correct operation, this pin must be tied to V SS when it is not used. CHASO 28 O OD 6 VSB Chassis Intrusion Output.When low, indicates that an intrusion indication is set. CHLOCK 1 O O 12/12 VDD Chassis Hood Lock.When low, locks the chassis hood solenoid. CHUNLOCK 128 O O 12/12 VDD Chassis Hood Unlock.When low, unlocks the chassis hood solenoid. XLOCK 53 I INT VDD Access Lock. When low, this pin blocks read/write from/to the SuperI/O Configuration 6 (SIOCF6) register to prevent accidental access. Signal Pin/s I/O Buffer Type Power Well Description CTS1 CTS2 100

108 I INTS VDD

Clear to Send.When low, indicate that the modem or other data transfer device is ready to exchange data. DCD1 DCD2

103 I INTS VDD

Data Carrier Detected.When low, indicate that the modem or other data transfer device has detected the data carrier. DSR1 DSR2

104 I INTS VDD

Data Set Ready.When low, indicate that the data transfer device, e.g., modem, is ready to establish a communications link. DTR1_ BOUT1 DTR2_ BOUT2 101 109 O O 3/6 VDD Data Terminal Ready.When low, indicate to the modem or other data transfer device that the UART is ready to establish a communications link. After a system reset, these pins provide the DTR function and set these signals to inactive high. Loopback operation holds them inactive. Baud Output.Provides the associated serial channel baud rate generator output signal if test mode is selected, i.e., bit 7 of the EXCR1 Register is set. DTR1_BOUT1 is used also as BADDR. RI1 RI2 102

110 I INTS VDD ,V SB

Ring Indicator.When low, indicate that a telephone ring signal has been received by the modem. They are monitored during power-off for wake-up event detection. RTS1 RTS2

106 O O 3/6 VDD

Request to Send.When low, indicate to the modem or other data transfer device that the corresponding UART is ready to exchange data. A system reset sets these signals to inactive high, and loopback operation holds them inactive. RTS1 is used also as TEST. SIN1 SIN2

105 I INTS VDD

Serial Input.Receive composite serial data from the communications link (peripheral device, modem or other data transfer device). SOUT1 SOUT2

107 O O

Serial Output.Send composite serial data to the communications link (peripheral device, modem or other data transfer device). These signals are set active high after a system reset.

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1.4.13 Strap Configuration

1.4.14 System Wake-Up Control

Signal Pin/s I/O Buffer Type Power Well Description BADDR 101 I INSTRP VDD Base Address.Sampled by the trailing edge of the system reset to determine the base address of the configuration Index-Data register pair. During reset, it is pulled down by internal 30Kohm resistor. If no pull-up resistor is connected, it is sampled low, setting the Index-Data pair at 2Eh-2Fh. Connecting a 10K external pull-up resistor to V DD would make it sample high, setting the Index-Data pair at 4Eh-4Fh. PSLDC0 PSLDC1

107 I INSTRP VSB

Note 1. Note 1.Make sure that the Serial Port driver is back-drive protected. Power Supply and LED Configuration.If no pull-up resistor is connected to these pins, pins 33-35 and 37 function as PWBT OUT, PSON, PWBTIN and SLPS5 respectively. Connecting a 10K external pull-up resistor to VSB causes these pins to function as GPOS0, GPOS1, GPIS2, respectively. PSONPOL 109 I INSTRP VSB Note 1. Power Supply On Polarity.If no pull-up resistor is connected to this pin, PSON is set active low with open-drain output. Connecting a 10K external pull-up resistor to V SB causes PSON to be set to active high with push-pull output. TEST 98 I INSTRP VDD Test.If sampled high on the trailing edge of system reset, this signal forces the device into test mode. This pin is for National Semiconductor use only, and should be left unconnected. Signal Pin/s I/O Buffer Type Power Well Description LED1 LED2

26 O O

LED. VSB -powered pins with programmable outputs, each of which can be used to produce a 0, 0.25, 0.5, 1, 4 Hz waveform for LED control. GPIE6-7 58-59 I INTS VSB General-Purpose Input Event GPIOE0-5 23-28 I/O INTS / OD 6,O 3/6 VSB General-Purpose I/O Event.VSB -powered pins. GPIS2-3 35-36 I INTS VSB General-Purpose Input Standby.VSB -powered pins. GPOS0-1 33-34 O OD 6,O 3/6 VSB General-Purpose Output Standby.VSB -powered pins. PSON 34 O O 4,O D12 VSB Power Supply On.Active level (low or high via PSONPOL strap) instructs the main power supply to turn the power on. PSON output signal is open-drain when active low and push-pull when active high. PWBTIN 35 I INTS VSB Power Button In.Active (low) level indicates a user request to turn the power on or off. This pin has an internal Schmidt-trigger input buffer and debouce protection of at least 16 mS. PWBT OUT 33 O OD 12 VSB Power Button Out.Active (low) level serves as output to the chipset power button input. PWUREQ 32 O OD 6 VSB Power-Up Request.Active (low) level indicates that wake-up event has occurred, and causes the chipset to turn the power supply on, or to exit its current sleep state. The open-drain output must be pulled up to V SB in order to function during power-off.

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1.4.15 WATCHDOG Timer (WDT)

Telephone Line Ring.Detection of a pulse train on theRING pin is a wake-up event that can activate the power-up request PWUREQ). The pin has a Schmidt-trigger input buffer, powered by VSB . SLPS3 36 I INTS VSB Sleep State 3, 4 or 5.Input from this pin is assumed to be driven by the system’s ACPI controller to indicate the system’s power state. SLPS5 37 I INTS VSB Sleep State 4 or 5.Input from this pin is assumed to be driven by the system’s ACPI controller to indicate the system’s power state. Signal Pin/s I/O Buffer Type Power Well Description WDO 56 O OD 6,O 3/6 VDD WATCHDOG Out. Low level indicates that the WATCHDOG Timer has reached its time-out period without being retriggered. The output type and an optional pull-up are configurable. Signal Pin/s I/O Buffer Type Power Well Description

1.5 INTERNAL PULL-UP AND PULL-DOWN RESISTORS

for the values of each resistor type. Table 4. Internal Pull-Up and Pull-Down Resistors

25 Programmable

29 www.national.com System Wake-Up Control (SWC) GPIE6-7 58-59 PU 25 Programmable GPIOE0-5 23-28 PU 25 Programmable GPIS2-3 35-36 PU 100 PSON/GPOS1 34 PU 100 PWBTIN 35 PU 50 PWBT OUT 33 PU 100 RING 27 PU 25 WATCHDOG Timer (WDT) WDO 56 PU1 Programmable Signal Pin/s Type Comments

2.0 Device Architecture and Configuration

mation, including special implementation of generic blocks, system interface and device configuration.

2.1 OVERVIEW

LPC Interface Specification, Revision 1.0. configurable through the configuration registers and distributed to the functional blocks through special control signals.

2.2 CONFIGURATION STRUCTURE AND ACCESS

The configuration structure is comprised of a set of banked registers which are accessed via a pair of specialized registers.

2.2.1 The Index-Data Register Pair

Access to the SuperI/O configuration registers is via an Index-Data register pair, using only two system I/O byte locations. the BADDR pin. Table 5 shows the selected base addresses as a function of BADDR. Table 5. BADDR Strapping Options figuration register file, and holds the index of the configuration register that is currently accessible via the Data register. Reading the Index register returns the last value written to it (or the default of 00h after reset). actually accesses the configuration register that is currently pointed to by the Index register.

2.0 Device Architecture and Configuration(Continued)

Figure 1. PC87364 Detailed Block Diagram

2.2.2 Banked Logical Device Registers Structure

values of the PC87364 functional blocks. register, within the logical device currently selected by the LDN register. Figure 2. Structure of the Standard Configuration Register File Table 6. Logical Device Number (LDN) Assignments returns 04h (indicating no DMA channel is active). The configuration registers are accessible immediately after reset.

2.2.3 Standard Logical Device Configuration Register Definitions

• All registers are read/write.
• All reserved bits return 0 on reads, except where noted otherwise. They must not be modified as it may cause un- predictable results. Use read-modify-write to prevent the values of reserved bits from being changed during write.
• Write only registers should not use read-modify-write during updates.

Table 7. Standard Control Registers Table 8. Logical Device Activate Register Table 9. I/O Space Configuration Registers Indicates selected I/O lower limit address bits 15-8 for I/O Descriptor 0. Indicates selected I/O lower limit address bits 7-0 for I/O Descriptor 0. Indicates selected I/O lower limit address bits 15-8 for I/O Descriptor 1. Indicates selected I/O lower limit address bits 7-0 for I/O Descriptor 1.

Table 10. Interrupt Configuration Registers Table 11. DMA Configuration Registers Table 12. Special Logical Device Configuration Registers Indicates selected interrupt number. assertion triggers a wake-up event. IRQ2, etc. (up to IRQ15). IRQ0 is not a valid interrupt selection. channel in case of using more than one DMA channel). value of 0 selects DMA channel 0, 1 selects channel 1, etc. A value of 4 indicates that no DMA channel is active. The values 5-7 are reserved. DMA channel in case of using more than one DMA channel). value of 0 selects DMA channel 0, 1 selects channel 1, etc. A value of 4 indicates that no DMA channel is active. The values 5-7 are reserved. Configuration Special (vendor-defined) configuration options.

2.2.4 Standard Configuration Registers

Figure 3. Configuration Register Map ment and the selection of pin multiplexing options. For details, see Section 2.8. A subset of these registers is implemented for each logical device. See functional block description in the following sections.

36www.national.com Control The only implemented control register for each logical device is the Activate register at index 30h. Bit 0 of the Activate reg- ister controls the activation of the associated function block. Activation of the block enables access to the block’s registers, and attaches its system resources, which are unused as long as the block is not activated. Other effects may apply, on a function-specific basis (such as clock enable and active pinout signaling). Standard Configuration The standard configuration registers are used to manage the PnP resource allocation to the functional blocks. The I/O port base address descriptor 0 is a pair of registers at Index 60-61h, holding the (first or only) 16-bit base address for the register set of the functional block. An optional 16-bit second base-address (descriptor 1) at index 62-63h is used for logical devices with more than one continuous register set. Interrupt Number and Wake-Up on IRQ Enable (index 70h) and IRQ Type Select (index 71h) allocate an IRQ line to the block and control its type. DMA Channel Select 0 (index 74h) allocates a DMA channel to the block, where applicable. DMA Channel Select 1 (index 75h) allocates a second DMA channel, where applicable. Special Configuration The vendor-defined registers, starting at index F0h, are used to control function-specific parameters such as operation modes, power saving modes, pin TRI-STATE, clock rate selection, and non-standard extensions to generic functions.

2.2.5 Default Configuration Setup

The default configuration setup of the PC87364 can include four reset types, described below. See specific register descrip- tions for the bits affected by each reset type.

• Software Reset This reset is enabled by bit 1 of the SIOCF1 register, which resets all logical devices. A software reset also resets most bits in the SuperI/O control and configuration registers (see Section 2.8 for the bits not affected). This reset does not affect register bits that are locked for write access.
• Hardware Reset This reset is activated by the assertion of theLRESET input. It resets all logical devices, with the exception of the System Wake-Up Control (SWC). It also resets all SuperI/O control and configuration registers, except for those that are battery- backed.
• VPP Power-Up Reset This reset is activated when either VSB or VBAT is powered up after both have been off. VPP is an internal voltage which is a combination of VSB and VBAT .VPP is taken from VSB if VSB is greater than the minimum (Min) value defined in the Device Characteristicschapter; otherwise, VBAT is used as the VPP source. This reset resets all registers whose values are retained by VPP .
• VSB Power-Up Reset This is an internally generated reset that resets the SWC, excluding those SWC registers whose values are retained by VPP . This reset is activated after VSB is powered up. In event of a hardware reset, the PC87364 wakes up with the following default configuration setup: — The configuration base address is 2Eh or 4Eh, according to the BADDR strap pin value, as shown in Table 5. — The Keyboard Controller (KBC) is active and all other logical devices are disabled, with the exception of the SWC which remains functional but whose registers cannot be accessed. — All multiplexed GPIO pins, except for pins whose function is controlled by battery-backed registers and pins 8 and 9 (which are controlled by bits 1 and 0 of the SIOCF3 register) are configured as GPIO pins, with an internal static pull- up (default direction is input). In event of either a hardware or a software reset, the PC87364 wakes up with the following default configuration setup: — The legacy devices are assigned with their legacy system resource allocation. — The National proprietary functions are not assigned with any default resources and the default values of their base addresses are all 00h.

2.2.6 Power States

The following terminology is used in this document to describe the various possible power states:

• Power On Both VSB and VDD are active.
• Power Off V SB is active and VDD is inactive.

• Power Fail Both VSB and VDD are inactive. Note: The following state is illegal: VDD active and VSB inactive.

2.2.7 Address Decoding

blocks. However, the number of configurable bits in the base address registers varies for each logical device. 7FXh only (bits 11-15 are forced to 0). The Parallel Port base address is limited to the I/O address range of 00h to 3F8h. The addresses of the non-legacy logical devices are configurable within the full 16-bit address range (up to FFFXh). of the base address register for each logical device.

2.3 INTERRUPT SERIALIZER

only parallel IRQ in a system which supports only serial IRQs. Figure 4 shows the interrupt serialization mechanism. Figure 4. Interrupt Serialization Mechanism Serializer, where they are translated into serial data and transmitted over the SERIRQ bus. an IRQ slot, the corresponding internal IRQ signal is a logic AND of all IRQ sources. When an IRQ slot is exclusively used by a PIRQ pin, each transition sensed on this PIRQ pin is translated into a new value. ment during slot “n” of the SERIRQ bus.

38www.national.com The Interrupt Serializer is controlled by bit 6, Pins 117-127 Select PIRQ, of SuperI/O Configuration 1 register. When this bit is set to 0 (default), the Interrupt Serializer is disabled. When it is set to 1, the Interrupt Serializer is enabled, and each PIRQn input function is selected on its associated pin. The PIRQn input value is then routed to the Interrupt Serializer as the IRQ value to be driven onto IRQ slot “n” when at least one of the following conditions is true:

• Slot “n” is not selected by any internal IRQ source.
• Slot “n” is selected by an internal IRQ source which is set for sharing (low polarity). Otherwise, the IRQ value driven onto IRQ slot “n” is the value of any internal IRQ that is selected.

2.4 PROTECTION

The PC87364 provides features to protect the PC at mechanical and software levels. At the mechanical level, the device can detect intrusion to the chassis of the PC. It can also control the solenoids that lock and unlock the chassis. At the hardware level, the device can disable I/O port access. This protects system integrity by enabling the primary oper- ating software to prevent other unwanted I/O operations by other software. At the software level, the device can be locked to protect configuration bits or alteration of the hardware configuration of the device, as well as internal GPIO settings and several types of configuration settings. All protection mechanisms can optionally be used.

2.4.1 Chassis Intrusion Detection

The Chassis Intrusion Detection mechanism is based on the state of pin 29, CHASI. This pin reflects the status of an external switch that indicates the PC chassis state. Bits 4,5 of the SIOCFB register monitor this pin, and provide two types of information. Bit 4 reports a previously detected chassis intrusion, defined as any kind of transition on the CHASI pin. Bit 5 reflects the momentary value of the CHASI pin. For further details on the SIOCFB register, see Section 2.8.10. To prevent the CHASI pin from detecting a false chassis intrusion, it is implemented with an internal noise filter. A chassis intrusion event can be reported to the host system by either software or hardware. When using software, the sys- tem must read the SIOCFB register to check if an intrusion event has occurred. When using hardware, the device provides the following means for indicating chassis intrusion:

• Dedicated output (CHASO)
• SMI assertion. To use theCHASO function, it must first be selected by setting bit 6 of the SIOCFA register to 1. Thereafter, whenever a chassis intrusion is detected, theCHASO pin reflects the value of bit 4 of the SIOCFB register. When bit 4 of this register is set to 1, theCHASO pin is asserted (driven low). It is deasserted when this bit is cleared. To use theSMI assertion, it must either be selected on its pin or routed to interrupt request channel 2. To selectSMI on its pin, set bit 2 of the SIOCF3 register to 1 (for further details, see Section 2.8.4). To route the SMI signal to interrupt request channel 2, set bit 4 of the SIOCF5 register to 1 (for further details, see Section 2.8.6). In addition, the chassis intrusion event must be routed to the SMI signal by setting bit 5 of the SIOCF8 register to 1 (for further details, see Section 2.8.8). Thereafter, whenever a chassis intrusion is detected, theSMI signal reflects bit 4 of the SIOCFB register. When bit 4 of this register is set to 1, theSMI signal and the selected target indication are asserted (driven low). TheSMI signal is deasserted when this bit 4 is cleared.

2.4.2 Chassis Lock and Unlock

The Chassis Lock and Unlock mechanism is based on the output functions of pin 1,CHLOCK, and pin 128,CHUNLOCK, as well as the values of bits 2, 3 of the SIOCF5 register. A lock operation is defined as the assertion of CHLOCK for approx- imately the next 0.75 seconds, and an unlock operation as the assertion of CHUNLOCK for the same duration of time. To use this mechanism, CHLOCK and CHUNLOCK must first be selected on their respective pins. To selectCHLOCK, write 10 to bits 1-0 of the SIOCF2 register. To selectCHUNLOCK, write 10 to bits 1-0 of the SIOCF5 register. The CHLOCK and CHUNLOCK functions can then be operated using bits 2 and 3 of the SIOCF5 register. Bit 3 of the SIOCF5 register determines if the operation to be performed will be lock or unlock. When set to 0, unlock is se- lected; when set to 1, lock is selected. Writing to bit 2 of the SIOCF5 register initiates the operation set by bit 3, and reflects the status of the lock/unlock mecha- nism. Before initiating any lock/unlock operation, bit 2 must be verified to be 0. This indicates that the lock/unlock mechanism is idle, and can be used to perform a new operation. When bit 3 is set to the desired value and bit 2 is verified to be 0, bit 2 can be set to 1 to initiate the operation determined by bit 3.

39 www.national.com When bit 2 of the SIOCF5 register is set to 1, it causes the appropriate output function, eitherCHLOCK or CHUNLOCK, to be asserted for a duration of 0.75 second. Then, this output function is deasserted. During the time the output function is asserted, and for an additional 0.25 second afterwards, bit 2 of the SIOCF5 register returns 1 on reads, and no action can be initiated. This protection mechanism prevents lock/unlock operations from being performed at short intervals to protect the mechanical lock/unlock mechanism.

2.4.3 Access Lock to I/O Ports

Locking access to the I/O ports of the device is based on the SIOCF6 register (for details, see Section 2.7.7). This protection feature is implemented for the following logical devices:

• FDC (Logical Device 0)
• Parallel Port (Logical Device 1)
• Serial Port 2 (Logical Device 2)
• Serial Port 1 (Logical Device 3)
• ACB (Logical Device 8) Each one of these logical devices has an associated bit in the SIOCF6 register. When one of these bits is set, the associated logical device is completely disabled. For example, when bit 0 of the SIOCF6 register is set to 1, the FDC is disabled. To lock access to the I/O ports, the SIOCF6 register must be set to read only. This can be done by either software or hard- ware. By software, set bit 7 of the SIOCF6 register to 1. This bit can only be cleared (read/write enabled) by a hardware reset. Alternatively, use theXLOCK input hardware-based function to set the SIOCF6 register to read only. First, selectXLOCK on its pin, pin 53, by setting bit 4 of the SIOCF3 register to 1.XLOCK can then can be used to control the SIOCF6 register, as follows:
• When XLOCK is driven high, the SIOCF6 register is read/write.
• When XLOCK is driven low, the SIOCF6 register is read only.

2.4.4 Pin Configuration Lock

To lock the pin configuration of the PC87364 in order to prevent unwanted changes to hardware configuration, set bit 7 of the SIOCF1 register to 1. Setting this bit causes all function select configuration bits, including those that are battery backed, to become read only bits. This bit can only be cleared by a hardware reset.

2.4.5 GPIO Pin Function Lock

The PC87364 is capable of locking the attributes of each GPIO or Standby GPIO pin. The following attributes can be locked:

• Output enable
• Output type
• Static pull-up
• Driven data. GPIO pins are locked per pin by setting the Lock bit in the appropriate GPIO Pin Configuration register. When the Lock bit is set, the configuration of the associated GPIO pin can only be released by a hardware reset. Standby GPIO pins are locked in the same manner by setting the Lock bit in the appropriate Standby GPIO Pin Configuration registers. However, once a Standby GPIO pin is locked, its locked attributes can only be released with a VSB power-up reset.

2.5 POWER SUPPLY CONTROL (PSC)

The PC87364 includes hardware that can be used to ease the system’s control over the computer’s power supply. This hard- ware is implemented as a state machine that determines the required state of the power supply based on several input sig- nals, and also connects to the system’s ACPI controller to share information about the system’s power state via specific interface signals. The PSC uses the pin functions SLPS3, SLPS5, PWBTIN, PWBTOUT and PSON. These functions are optional on their respective pins and must be selected to enable the PSC by setting the values of the PSLDC0,1 strap pins (see Table 14). Once enabled, the PSC can be operated in one of two modes, according to the value of bit 0 (Power Button Mode) of the SIOCFD register:

• ACPI mode
• Legacy mode

input signal. The polarity of PSON is set by the PSONPOL strap. the Crowbar mechanism, see “Crowbar Condition” below.

• PWBTIN is pulsed.
• A wake-up event, that is routed toPWBT OUT. A wake-up event that is routed to the power button output can causePWBTOUT to be pulsed in ACPI mode if one of the following conditions is met:
• SLPS5 is active.
• Enable Power Button Pulse on S3 (bit 3) of the SWC WK_CFG register is set to 1. However, when in ACPI mode,PWBTIN and PWBTOUT activity has no effect on the PSON output. The power button mech- anism can have an indirect effect on PSON only ifPWBTOUT is connected to the power button input of the ACPI controller, thus affecting theSLPS3 signal. Legacy Mode When the PSC is operated in Legacy mode (bit 0 of the SIOCFD register is set to 0), the PC87364 controls the system’s power supply. In this mode, the PSON output signal is set by the PC87364 according to the following factors: the state of input signals, the state of the power supply lines, power button activity and certain configuration bits. Although the ACPI con- troller does not control the system’s power supply, it tracks the system’s power state. For this purpose, the PC87364 ma- nipulates the PWBTOUT so that the ACPI controller is always synchronized with the actual state of the PSON output. This synchronization mechanism assumes thatPWBTOUT is connected to the power button input of the ACPI controller. See a schematic state diagram of the Legacy PSC mechanism in Figure 4.

Figure 5. Legacy Power Supply Control State Diagram

checks if Resume to Last PSON state is enabled. synchronization pulse is generated when the PSC is in Synchronize ACPI state.

• IfSLPS3 is low (active, state OFF), the PSC enters OFF state.
• IfSLPS3 is high (inactive, state ON), the PSC enters ON state. SinceSLPS3 reflects the state of the ACPI controller, the PSC actually resumes the current state of the ACPI controller. After entering either ON or OFF states, PSC moves between these two states on the following conditions:
• A falling edge onPWBT OUT (generated internally) changes the state from ON to OFF or vice versa.
• A Software Power Supply Off command, writing 1 to Power Supply Off (bit 1) of the SIOCFD register, changes the state from ON to OFF . Since many wake-up events can activate thePWBTOUT signal, these events can actually cause the PSC to change its state from OFF to ON, thus activating the PSON output. As in ACPI mode, the Crowbar protection mechanism is also active in Legacy mode. However, in this mode, when a Crowbar condition is detected, the PSC returns to OFF state, thus inactivating the PSON output. Also, to synchronize the APCI con- troller, the PWBTOUT is pulsed to bring it to the correct state. Table 13 summarizes the bit states that affect PSON VSB power-up default state.

Table 13. PSON VSB Power-Up Default State special crowbar mechanism is included in the PSC logic. deactivated and the PSC makes sure that the ACPI state of the system is changed to OFF. SIOCFD register. For further details, refer to the description of this register in Section 2.8.12.

0 X Same as

2.6 LED OPERATION AND STATES

register. The polarity of both LEDs is determined by LED Polarity Control (bit 7) of the SIOCFD register. tures such as power and error indication. 2 on LED operation that override the above rules. Table 14. Hardware Modes 1 and 2 Effect on LED Operation

2.7 POWER SUPPLY CONTROL AND LED CONFIGURATION

SB power-up reset. Table 15 describes how they affect the chip configuration. Table 15. PSLDC0,1 Configuration Options

2.8 REGISTER TYPE ABBREVIATIONS

• R/W = Read/Write
• R = Read from a specific address returns the value of a specific register. Write to the same address is to a different register.
• W=W r i t e
• RO = Read Only
• R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect. Mode System State LED1 LED2 Hardware 1 (SIOCFB, bits 3-2=01) VSB power-up reset Off 1 Hz blink, 50% duty cycle Power off (VSB ,n oVDD ) Software-controlled 1 Hz blink, 50% duty cycle Hardware 2 (SIOCFB, bits 3-2=10) ACPI mode and Sleep State 3 Software-controlled Software-controlled ACPI mode, Sleep State 5, bit 6 = 1 in SIOCFC register and Power Supply Control enabled Software-controlled Software-controlled ACPI mode, any other configuration Off Off Legacy mode and power off (no V DD ) Off Off PSLDC0 (Pin 99) PSLDC1 (Pin 107) Power Supply Control LED2 0 0 Enabled (default) Not selected (default) 0 1 Disabled Selected 1 0 Disabled Not selected 1 1 Enabled Selected

2.9 SUPERI/O CONFIGURATION REGISTERS

• 2Eh). See Table 16 for a summary and directory of these registers.

Table 16. SuperI/O Configuration Registers

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2.9.1 SuperI/O ID Register (SID)

This register contains the identity number of the chip. The PC87364 is identified by the value E4h. Location: Index 20h Type: RO

2.9.2 SuperI/O Configuration 1 Register (SIOCF1)

Location: Index 21h Type: R/W B i t 76543210 Name Chip ID Reset 11100100 B i t 76543210 Name Pin Function Select Lock Pins 117-127 Function Select Number of DMA Wait States Number of I/O Wait States SW Reset Global Device Enable Reset 00010001 Bit Description 7 Pin Function Select Lock. This bit determines if the bits (located in the SIOCF1, 2, 3, 4, 5, A and B registers) that select pin functions are read only or read/write. When set to 1, this bit can only be cleared by a hardware reset. 0: Bits are R/W. 1: Bits are RO. 6 Pins 117-127 Function Select. 0: Pins 117-127 function set by SIOCF4 (default) 1: Pins 117-127 are PIRQ3-7, 9, 11-12, 14-15 5-4 Number of DMA Wait States. Bits 5 4 Number 0 0 Reserved 0 1 Two (default) 1 0 Six 1 1 Twelve 3-2 Number of I/O Wait States. Bits 3 2 Number 0 0 Zero (default) 0 1 Two 1 0 Six 1 1 Twelve 1 SW Reset . Read always returns 0. 0: Ignored (default) 1: Resets all the logical devices that are reset by hardware reset (with the exception of the lock bits), and resets the registers of the SWC 0 Global Device Enable.This bit controls the function enable of all the PC87364 logical devices, except System Wake-Up Control (SWC). With the exception of SWC, it allows all logical devices to be disabled simultaneously by writing to a single bit. 0: All logical devices in the PC87364 are disabled, except SWC 1: Each logical device is enabled according to its Activate register (Index 30h) (default)

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2.9.3 SuperI/O Configuration 2 Register (SIOCF2)

Location: Index 22h Type: R/W B i t 7654 3 210 Name Pin 7 Function Select Pin 6 Function Select Pin 5 Function Select Pin 4 Function Select Pin 3 Function Select Pin 2 Function Select Pin 1 Function Select Reset 0000 0 000 Bit Description 7 Pin 7 Function Select. 0: GPIO05 (default) 1: P17 6 Pin 6 Function Select. 0: GPIO04 (default) 1: P12 5 Pin 5 Function Select. 0: GPIO03 (default) 1: FANOUT0 4 Pin 4 Function Select. 0: GPIO02 (default) 1: FANIN0 3 Pin 3 Function Select. 0: GPIO01 (default) 1: FANOUT1 2 Pin 2 Function Select. 0: GPIO00 (default) 1: FANIN1 1-0 Pin 1 Function Select. Bits 1 0 Function 0 0 GPIO34 (default) 0 1 FANOUT2 1 0 CHLOCK 1 1 Reserved

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2.9.4 SuperI/O Configuration 3 Register (SIOCF3)

Location: Index 23h Type: R/W B i t 76 5 43210 Name Pin 57 Function Select Pin 56 Function Select Pins 54, 55 Function Select Pin 53 Function Select Reserved Pin 21 Function Select Pin 9 Function Select Pin 8 Function Select Reset 0 0 0 00011 Bit Description 7 Pin 57 Function Select. 0: GPO15 (default) 1: IRTX 6 Pin 56 Function Select. 0: GPIO14 (default) WDO 5 Pins 54, 55 Function Select. 0: GPIO12/GPIO13 (default) 1: SCL/SDA 4 Pin 53 Function Select. 0: GPIO11 (default) XLOCK

3 Reserved

2 Pin 21 Function Select. 0: GPIO10 (default) SMI 1 Pin 9 Function Select. 0: GPIO07 1: GA20 (P21) (default) 0 Pin 8 Function Select. 0: GPIO06 1: KBRST (P20) (default)

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2.9.5 SuperI/O Configuration 4 Register (SIOCF4)

Location: Index 24h Type: Varies per bit * Bit 6, Pins 117-127 Select PIRQ, of the SIOCF1 register B i t 76543210 Name Pin 127 Function Select Pins 125,126 Function Select PIns 117-124 Function Select Pin 71 Function Select Pin 69 Function Select Reset 00000000 Bit Description 7-6 Pin 127 Function Select.This is a R/W bit. Bits 7 6 P* Function 0 0 0 GPIO32 (default) 0 1 0 P16 1 0 0 IRSL1 X X 1 PIRQ15 5 Pins 125,126 Function Select.This is a RO bit. Bits

5 P* Function

0 0 GPIO30,31 (default) 1 0 Reserved X 1 PIRQ12,14 4 Pins 117-124 Function Select.This is a RO bit. Bits

4 P* Function

0 0 GPIO20-27 (default) 1 0 Reserved X 1 PIRQ3-7,9-11 3-2 Pin 71 Function Select.This is a R/W bit. Bits 3 2 Function 0 0 GPIO17 (default) 0 1 DR1 1 0 IRSL3 1 1 Reserved 1-0 Pin 69 Function Select.This is a R/W bit. Bits 1 0 Function 0 0 GPIO16 (default) 0 1 MTR1 1 0 IRSL2 1 1 Reserved

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2.9.6 SuperI/O Configuration 5 Register (SIOCF5)

Location: Index 25h Type: Varies per bit B i t 76543210 Name Reserved SMI to IRQ2 Enable Chassis Hood Lock Chassis Hood Ac- tion/Status Pin 128 Function Select Reset 00000000 Bit Description 7-5 Reserved 4 SMI to IRQ2 Enable.This is a R/W bit. 0: Disabled (default) 1: Enabled 3 Chassis Hood Lock.This is a R/W bit. 0: Unlock (default) 1: Lock 2 Chassis Hood Action/Status.This is a R/W bit. Writing 1 operates the lock/unlock function determined by bit 3 of this register. Writing 0 deactivates an action in progress. Before setting this bit, the software must verify that it is set to 0. 0: Inactive/Ready (default) 1: Activate/Busy 1-0 Pin 128 Function Select.This is a R/W bit. Bits 1 0 Function 0 0 GPIO33 (default) 0 1 FANIN2 1 0 CHUNLOCK 1 1 Reserved

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2.9.7 SuperI/O Configuration 6 Register (SIOCF6)

Write access to this register can be inhibited by either assertingXLOCK when it is selected on pin 53, or by setting bit 7 of this register. Activation of each logical device (bits 0-4) is also affected by bit 0 of the logical device Activate register, index 30h and bit 0 of the SIOCF1 register. Location: Index 26h Type: R/W

2.9.8 SuperI/O Revision ID Register (SRID)

This register contains the identity number of the chip revision. SRID is incremented on each revision. Location: Index 27h Type: RO B i t 76543210 Name SIOCF6 Software Lock General-Purpose Scratch ACB Disable Serial Port 1 Disable Serial Port 2 Disable Parallel Port Disable FDC Disable Reset 00000000 Bit Description 7 SIOCF6 Software Lock.Once this bit is set to 1 by software, it can be cleared only by hardware reset. 0: Write access to bits 0-6 of this register is controlled by XLOCK (default) 1: Bits 0-6 of this register are RO 6-5 General-Purpose Scratch

4 ACB Disable

0: Enabled (default) 1: Disabled

3 Serial Port 1 Disable

0: Enabled (default) 1: Disabled

2 Serial Port 2 Disable

0: Enabled (default) 1: Disabled

1 Parallel Port Disable

0: Enabled (default) 1: Disabled

0 FDC Disable

0: Enabled (default) 1: Disabled

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2.9.9 SuperI/O Configuration 8 Register (SIOCF8)

Location: Index 28h Type: R/W B i t 76 5 43210 Name Reserved CHASO to SMI Enable Mouse IRQ to SMI Enable KBD IRQ to SMI Enable KBD P12 to SMI Enable GPI toSMI Enable WDO to SMI Enable Reset 0 0 0 00000 Bit Description 7-6 Reserved

5 CHASO to SMI Enable

0: Disabled (default) 1: Enabled:

4 Mouse IRQ to

0: Disabled (default) 1: Enabled

3 KBD IRQ to

0: Disabled (default) 1: Enabled

2 KBD P12 to

0: Disabled (default) 1: Enabled

1 GPI to

0: Disabled (default) 1: Enabled WDO to SMI Enable 0: Disabled (default) 1: Enabled

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2.9.10 SuperI/O Configuration A Register (SIOCFA)

This is a battery-backed register. Location: Index 2Ah Type: Varies per bit B i t 76543210 Name Pins 33-37 Function Select Pin 28 Function Select PIn 27 Function Select Pin 26 Function Select Pin 25 Function Select Pin 24 Function Select Reset Strap 0000000 Bit Description Pins 33-37 Function Select.This is a RO bit. The function of the pin selected is determined during V SB power-up by the PSLDC0.1 straps.0:PWBT OUT, PSON, PWBTIN, SLPS3, SLPS5 1: GPOS0, GPOS1, GPIS2, GPIS3,SLPS5 6 Pin 28 Function Select.This is a R/W bit. 0: GPIOE5 (default at VPP power-up reset) 1:CHASO 5-4 PIn 27 Function Select.This is a R/W bit. Bits 5 4 Function 0 0 GPIOE4 (default at VPP power-up reset) 0 1 RING Other Reserved 3 Pin 26 Function Select.This is a R/W bit. 0: GPIOE3 (default at VPP power-up reset) 1: LED2 2-1 Pin 25 Function Select.This is a R/W bit. Bits 2 1 Function 0 0 GPIOE2 (default at VPP power-up reset) 0 1 LED1 Other Reserved 0 Pin 24 Function Select.This is a RO bit. 0: GPIOE1 (default at V PP power-up reset) 1: Reserved

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2.9.11 SuperI/O Configuration B Register (SIOCFB)

This is a battery-backed register. Location: Index 2Bh Type: Varies per bit Bit 7 6 5 4 3 2 1 0 Name Reserved Intrusion Level Intrusion Status LED Mode Control Pin 59 Function Select Pin 58 Function Select Reset 0 0 X 1 0 0 0 0 Bit Description 7-6 Reserved 5 Intrusion Level.This is a RO bit, which reflects the value of pin 29 (CHASI), either 0 or 1. 4 Intrusion Status.Write 0 to this bit to clear it. 0: No intrusion 1: Intrusion detected (default at V PP power-up reset) 3-2 LED Mode Control.This is a R/W bit. Bits 3 2 Function 0 0 Software mode (default at VPP power-up reset) 0 1 Hardware mode 1 (default when power supply control is disabled by PSLDC0,1 straps) 1 0 Hardware mode 2 1 1 Reserved 1 Pin 59 Function Select.This is a R/W bit. 0: GPIE7 (default at V PP power-up reset) 1: IRRX1 0 Pin 58 Function Select.This is a R/W bit. 0: GPIE6 (default at VPP power-up reset) 1: IRRX2_IRSL0

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2.9.12 SuperI/O Configuration C Register (SIOCFC)

This is a battery-backed register. Location: Index 2Ch Type: R/W B i t 76543210 Name LED Configura- tion Power LED Status in S4 or S5 LED2 Blink Rate LED1 Blink Rate Reset 00000000 Bit Description

7 LED Configuration

0: One dual-colored LED (default at V PP power-up reset) 1: Two LEDs 6 Power LED Status in S4 or S5.This bit is active only when hardware mode 2 is selected (bits 2-3 in the SIOCFB register). 0: Turn off (default at VDD power off) 1: Unchanged 5-3 LED2 Blink Rate Bits 5 4 3 Rate Duty Cycle (Hz) 0 0 0 Off Always low 0 0 1 0.25 12.5% 0 1 0 0.5 25% 0 1 1 1 50% Note 1. 1 0 0 2 50% 1 0 1 3 50% 1 1 0 4 50% 1 1 1 On Always high (default at V PP power-up reset) Note 1. When hardware mode 1 is selected, this rate will be set when VSB is powered up or when VDD becomes inactive while VSB is active. 2-0 LED1 Blink Rate Bits 2 1 0 Rate Duty Cycle (Hz) 0 0 0 Off Always low (default at VPP power-up reset) 0 0 1 0.25 12.5% 0 1 0 0.5 25% 0 1 1 1 50% 1 0 0 2 50% 1 0 1 3 50% 1 1 0 4 50% 1 1 1 On Always high

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2.9.13 SuperI/O Configuration D Register (SIOCFD)

This is a battery-backed register. Location: Index 2Dh Type: Varies per bit B i t 76543210 Name LED Polarity Control Last PSON State PSON Polarity Crowbar Timeout Resume Last PSON State Power Supply Off Power Button Mode Reset 0 0 Strap 11000 Bit Description 7 LED Polarity Control.This is a R/W bit. It determines if the LED outputs are active high or active low when they are lit. 0: Active high (default at VSB power-up reset) 1: Active low 6 Last Power Supply On State.This is a RO bit. When operating in Legacy mode (bit 0 of this register is set to 0), this bit reflects the state of the PSON pin sampled during the last power failure (no VSB ), regardless of the polarity of PSON. 0: Off 1: On 5 Power Supply On Polarity.This is a RO bit.The polarity of PSON is determined during VSB power-up by the PSONPOL strap. 4-3 Crowbar Timeout.This is a R/W bit. Bits 5 4 Value (Seconds) 0 0 0.5 to 0.75 0 1 1.0 to 1.25 1 0 1.25 to 1.5 1 1 2.0 to 2.25 (default at V PP power-up reset) 2 Resume Last Power Supply On State.This is a R/W bit. When it is set to 1, PSON resumes its last state, sampled during the last power failure, after power returns. When this bit is set to 0, the PSON state is determined by the SLPS3 state. 0:SLPS3 (default at VPP power-up reset) 1: Last PSON state. For correct operation, the system’s ACPI controller must be configured to resume to OFF . This enables the power supply control logic to know the state of the chipset ACPI state machine after power failure (no V DD and VSB ). 1 Power Supply Off.This is a R/W bit. It always returns 0 when read. When using Legacy mode (bit 0 is set to 0) and setting this bit to 1, this bit inactivates the PSON output, thereby shutting off the power supply. 0: No action (default at VPP power-up reset) 1: Inactivate PSON in Legacy mode 0 Power Button Mode. This is a R/W bit. 0: Legacy (default at VSB power-up reset) 1: ACPI

2.10 FLOPPY DISK CONTROLLER (FDC) CONFIGURATION

2.10.1 General Description

• FM and MFM modes are supported. To select either mode, set bit 6 of the first command byte when writing to/read- ing from a diskette, where: 0 = FM mode 1 = MFM mode
• A logic 1 is returned for all floating (TRI-STATE) FDC register bits upon LPC I/O read cycles. Exceptions to standard FDC support include:
• Automatic media sense is not supported (MSEN0-1 pins are not implemented)
• DRATE1 is not supported. Table 17 lists the FDC functional block registers.

Table 17. FDC Registers

2.10.2 Logical Device 0 (FDC) Configuration

Table 18 lists the Configuration registers which affect the FDC. Only the last two registers (F0h and F1h) are described here. Table 18. FDC Configuration Registers Note 1. This is the 8-byte aligned FDC base address.

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2.10.3 FDC Configuration Register

This register is reset by hardware to 24h. Location: Index F0h Type: R/W B i t 76543210 Name Reserved TDR Register Mode DENSEL Polarity Control Reserved Write Protect PC-AT or PS/2 Drive Mode Select Reserved TRI-STATE Control Reset 00100100 Required 0 0 Bit Description 7 Reserved. Must be 0.

6 TDR Register Mode

0: PC-AT compatible drive mode; i.e., bits 7-2 of the TDR are 111111b (default) 1: Enhanced drive mode

5 DENSEL Polarity Control

0: Active low for 500 Kbps or 1 Mbps data rates 1: Active high for 500 Kbps or 1 Mbps data rates (default) 4 Reserved.Must be 0. 3 Write Protect.This bit allows forcing of write protect functionality by software. When set, writes to the floppy disk drive are disabled. This effect is identical to WP when it is active. 0: Write protected according toWP signal (default) 1: Write protected regardless of value ofWP signal

2 PC-AT or PS/2 Drive Mode Select

0: PS/2 drive mode 1: PC-AT drive mode (default)

1 Reserved

0 TRI-STATE Control.When enabled and the device is inactive, the logical device output pins are in TRI-STATE. 0: Disabled (default) 1: Enabled

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2.10.4 Drive ID Register

This read/write register is reset by hardware to 00h. This register controls bits 5 and 4 of the TDR register in the Enhanced mode. Location: Index F1h Type: R/W Usage Hints:Some BIOS implementations support automatic media sense FDDs, in which case bit 5 of the TDR register in the Enhanced mode is interpreted as valid media sense when it is cleared to 0. If drive 0 and/or drive 1 do not support automatic media sense, bits 1 and/or 3 of the Drive ID register should be set to 1 respectively (to indicate non-valid media sense) when the corresponding drive is selected and the Drive ID bit is reflected on bit 5 of the TDR register in the Enhanced mode. B i t 76543210 Name Reserved Drive 1 ID Drive 0 ID Reset 00000000 Bit Description 7-4 Reserved 3-2 Drive 1 ID.When drive 1 is accessed, these bits are reflected on bits 5-4 of the TDR register, respectively. 1-0 Drive 0 ID.When drive 0 is accessed, these bits are reflected on bits 5-4 of the TDR register, respectively.

2.11 PARALLEL PORT CONFIGURATION

2.11.1 General Description

• A group of 21 registers at first level offset, sharing 14 entries. Three of this registers (at offsets 403h, 404h and 405h) are used only in the Extended ECP mode.
• A group of four registers, used only in the Extended ECP mode, accessed by a second level offset. The desired mode is selected by the ECR runtime register (offset 402h). The selected mode determines which runtime reg- isters are used and which address bits are used for the base address. See Tables 19 and 20 for a listing of all registers, their offset addresses, and the associated modes.

Table 19. Parallel Port Registers at First Level Offset Table 20. Parallel Port Registers at Second Level Offset

2.11.2 Logical Device 1 (PP) Configuration

Table 21. Parallel Port Configuration Registers

2.11.3 Parallel Port Configuration Register

This register is reset by hardware to F2h. Mode 4 (EPP) or when using the Extended registers, bit 2 (A2) should also be 0b. interrupt) in all other modes.

4 Extended Register Access

0: Registers at base (address) + 403h, base + 404h and base + 405h are not accessible (reads and writes are ignored). time configuration within the Parallel Port address space. 0: Parallel port clock disabled. ECP modes and EPP time-out are not functional when the logical device is active. 1: Parallel port clock enabled. All operation modes are functional when the logical device is active (default). 0 TRI-STATE Control.When enabled and the device is inactive, the logical device output pins are in TRI-STATE.

2.12 SERIAL PORT 2 CONFIGURATION

2.12.1 General Description

Serial Port 2 includes IR functionality as described in the Serial Port 2 with IR chapter.

2.12.2 Logical Device 2 (SP2) Configuration

Table 22. Serial Port 2 Configuration Registers

2.12.3 Serial Port 2 Configuration Register

This register is reset by hardware to 02h. 7 Bank Select Enable. Enables bank switching for Serial Port 2. 0: All attempts to access the extended registers in Serial Port 2 are ignored (default). 1: Enables bank switching for Serial Port 2. the Serial Port 2 logical device. 0: No transfer in progress (default). Serial Port 2 clock enabled. Serial Port 2 is functional when the logical device is active (default). 0 TRI-STATE Control. When enabled and the device is inactive, the logical device output pins are in TRI-STATE. One exception is the IRTX pin, which is driven to 0 when Serial Port 2 is inactive and is not affected by this bit.

2.13 SERIAL PORT 1 CONFIGURATION

2.13.1 Logical Device 3 (SP1) Configuration

Table 23. Serial Port 1 Configuration Registers

2.13.2 Serial Port 1 Configuration Register

This register is reset by hardware to 02h. 7 Bank Select Enable. Enables bank switching for Serial Port 1. the Serial Port 1 logical device. 0: No transfer in progress (default). Serial Port 1 clock enabled. Serial Port 1 is functional when the logical device is active (default). 0 TRI-STATE Control. When enabled and the device is inactive, the logical device output pins are in TRI-STATE.

2.14 SYSTEM WAKE-UP CONTROL (SWC) CONFIGURATION

2.14.1 Logical Device 4 (SWC) Configuration

Table 24. System Wake-Up Control (SWC) Configuration Registers

2.15 KEYBOARD AND MOUSE CONTROLLER (KBC) CONFIGURATION

2.15.1 General Description

troller (Logical Device 5) and a Keyboard controller (Logical Device 6). and Mouse interfaces are implemented as bi-directional, open-drain pins. Their internal connections are shown in Figure 5. P23, P26, P27, T0 and T1 are used to implement the Keyboard and Mouse interface. Internal pull-ups are implemented only on P12, P16 and P17. ware, except for the type and number, which are affected by configuration registers (see Section 2.14.2 25). latched in the output registers of the ports.

1. Set the appropriate port bit to issue an interrupt request.

Figure 6. Keyboard and Mouse Interfaces

2.15.2 Logical Devices 5 and 6 (Mouse and Keyboard) Configuration

Table 25. Mouse Configuration Registers Table 26. Keyboard Configuration Registers

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2.15.3 KBC Configuration Register

This register is reset by hardware to 40h. Location: Index F0h Type: R/W Usage Hints: 1. To change the clock frequency of the KBC, perform the following: a. Disable the KBC logical devices. b. Change the frequency setting. c. Enable the KBC logical devices. 2. Before swapping between the KBD and Mouse interface pins, disable the KBC logical devices and both pin sets. After swapping, the software should issue a synchronization command to the KBD and mouse through the KBC to regain syn- chronization with these devices. B i t 76543210 Name KBC Clock Source Reserved Swap Reserved TRI-STATE Control Reset 01000000 Required 0 Bit Description 7-6 KBC Clock Source.The clock source can be changed only when the KBC is inactive (disabled). Bits 7 6 Source 0 0 8 MHz 0 1 12 MHz (default) 1 0 16 MHz 1 1 Reserved 5-4 Reserved 3 Swap. This bit swaps between the KBD and Mouse interface pins. 0: KBCLK and KBDAT are KBD interface; MCLK and MDAT are Mouse interface (default) 1: KBCLK and KBDAT are Mouse interface, MCLK and MDAT are KBD interface 2-1 Reserved 0 TRI-STATE Control. If KBD is inactive (disabled) when this bit is set, the KBD pins (KBCLK and KBDAT) are in TRI- STATE. If Mouse is inactive (disabled) when this bit is set, the Mouse pins (MCLK and MDAT) are in TRI-STATE. 0: Disabled (default) 1: Enabled

2.16 GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORTS CONFIGURATION

2.16.1 General Description

PWUREQ signals. With the exception of bit 5 which is output only, port 1 pins are also I/O with full event detection capability. as shown in Table 27. The GPIO base address is 16-byte aligned. Address bits 3-0 are used to indicate the register offset. Table 27. Runtime Registers in GPIO Address Space

2.16.2 Implementation

• They each have two runtime registers for basic functionality: GPDO2/3 and GPDI2/3. Event detection registers GPEVEN2/3 and GPEVST2/3 are not available.
• Only bits 3-0 are implemented in the GPIO Pin Configuration registers of ports 2 and 3. Bits 6-4, associated with the event detection functionality, are reserved.
• The value of GPO36 and GPO37 is multiplied byLRESET, and therefore these signals are driven low whenLRESET is active. Offset Mnemonic Register Name Port Type 00h GPDO0 GPIO Data Out 0 0 R/W 01h GPDI0 GPIO Data In 0 RO 02h GPEVEN0 GPIO Event Enable 0 R/W 03h GPEVST0 GPIO Event Status 0 R/W1C 04h GPDO1 GPIO Data Out 1 1 R/W 05h GPDI1 GPIO Data In 1 RO 06h GPEVEN1 GPIO Event Enable 1 R/W 07h GPEVST1 GPIO Event Status 1 R/W1C 08h GPDO2 Data Out 2 2 R/W 09h GPDI2 Data In 2 RO 0Ah GPDO3 Data Out 3 3 R/W 0Bh GPDI3 Data In 3 RO 0Ch GPDO4 GPIO Data Out 4 4 R/W 0Dh GPDI4 GPIO Data In 4 RO 0Eh GPEVEN4 GPIO Event Enable 4 R/W 0Fh GPEVST4 GPIO Event Status 4 R/W1C

2.16.3 Logical Device 7 (GPIO) Configuration

Table 28 lists the configuration registers which affect the GPIO. Only the last three registers (F0h - F2h) are described here. Table 28. GPIO Configuration Register Figure shows the organization of these registers. Figure 7. Organization of GPIO Pin Registers

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2.16.4 GPIO Pin Select Register

This register selects the GPIO pin (port number and bit number) to be configured (i.e., which register is accessed via the GPIO Pin Configuration register). It is reset by hardware to 00h. Location: Index F0h Type: R/W B i t 76543210 Name Reserved Port Select Reserved Pin Select Reset 00000000 Bit Description

7 Reserved

6-4 Port Select.These bits select the GPIO port to be configured: 000: Port 0 (default) 001, 010, 011,100: Binary value of port numbers 1-4 respectively. All other values are reserved. 2-0 Pin Select.These bits select the GPIO pin to be configured in the selected port:

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2.16.5 GPIO Pin Configuration Register

This register reflects, for both read and write, the register currently selected by the GPIO Pin Select register. All the GPIO Pin registers that are accessed via this register have a common bit structure, as shown below. This register is reset by hard- ware to 44h, except for ports 2 and 3, that are reset to 04h. Location: Index F1h Type: R/W Ports: 0,1 and 4 (with event detection capability) Ports 2 and 3 (without event detection capability) B i t 76543210 Name Reserved Event Debounce Enable Event Polarity Event Type Lock Pull-Up Control Output Type Output Enable Reset 01000100 B i t 76543210 Name Reserved Lock Pull-Up Control Output Type Output Enable Reset 00000100 Bit Description 6 Event Debounce Enable.(Ports 0,1 and 4 with event detection capability). Enables transferring the signal only after a predetermined debouncing period of time. 0: Disabled 1: Enabled (default) Reserved. (Ports 2 and 3). Always 0. 5 Event Polarity.(Ports 0,1 and 4 with event detection capability). This bit defines the polarity of the signal that issues an interrupt from the corresponding GPIO pin (falling/low or rising/high). 0: Falling edge or low level input (default) 1: Rising edge or high level input Reserved. (Ports 2 and 3). Always 0. 4 Event Type.(Ports 0,1 and 4 with event detection capability). This bit defines the type of the signal that issues an interrupt from the corresponding GPIO pin (edge or level). 0: Edge input (default) 1: Level input Reserved. (Ports 2 and 3). Always 0. 3 Lock. This bit locks the corresponding GPIO pin. Once this bit is set to 1 by software, it can only be cleared to 0 by system reset or power-off. Pin multiplexing is functional until the Multiplexing Lock bit is 1 (bit 7 of SuperI/O Configuration 3 register, SIOCF3). 0: No effect (default) 1: Direction, output type, pull-up and output value locked 2 Pull-Up Control. This bit is used to enable/disable the internal pull-up capability of the corresponding GPIO pin. It supports open-drain output signals with internal pull-ups and TTL input signals 0: Disabled 1: Enabled (default) 1 Output Type.This bit controls the output buffer type (open-drain or push-pull) of the corresponding GPIO pin. 0: Open-drain (default) 1: Push-pull 0 Output Enable.This bit indicates the GPIO pin output state. It has no effect on the input path. 0: TRI-STATE (default) 1: Output enabled

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2.16.6 GPIO Event Routing Register

This register enables the routing of the GPIO event to IRQ,SMI and/orPWUREQ signals. It is implemented only for ports 0,1 and 4 which have event detection capability. This register is reset by hardware to 00h. Location: Index F2h Type: R/W B i t 76543210 Name Reserved Enable PWUREQ Routing Enable SMI Routing Enable IRQ Routing Reset 00000001 Bit Description 7-3 Reserved

2 Enable PWUREQ Routing

0: Disabled (default) 1: Enabled

1 Enable

0: Disabled (default) 1: Enabled

0 Enable IRQ Routing

0: Disabled 1: Enabled (default)

2.17.1 General Description

The six runtime registers are shown below. Table 29. ACB Runtime Registers

2.17.2 Logical Device 8 (ACB) Configuration

Table 30. ACB Configuration Registers

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2.17.3 ACB Configuration Register

This register is reset by hardware to 00h. Location: Index F0h Type: R/W B i t 76543210 Name Reserved Internal Pull-Up Enable Reserved Reset 00000000 Bit Description 7-3 Reserved

2 Internal Pull-Up Enable

0: No internal pull-up resistors on SCL and SDA (default) 1: Internal pull-up resistors on SCL and SDA 1-0 Reserved

2.18 FAN SPEED CONTROL AND MONITOR (FSCM) CONFIGURATION

2.18.1 General Description

0-3 are used to indicate the register offset. Table 31. Runtime Registers in FSCM Address Space

2.18.2 Logical Device 9 (FSCM) Configuration

Table 32. FSCM Configuration Registers

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2.18.3 Fan Speed Control and Monitor Configuration 1 Register

This register is reset by hardware to 00h. Location: Index F0h Type: R/W B i t 76543210 Name Fan Speed Invert 1 Enable Fan Speed Control 1 Enable Fan Speed Monitor 1 Enable Fan Speed Invert 0 Enable Fan Speed Control 0 Enable Fan Speed Monitor 0 Enable Reserved TRI-STATE Control Reset 00000000 Bit Description

7 Fan Speed Invert 1 Enable

0: Disabled (default) 1: Enabled

6 Fan Speed Control 1 Enable

0: Disabled (default) 1: Enabled

5 Fan Speed Monitor 1 Enable

0: Disabled (default) 1: Enabled

4 Fan Speed Invert 0 Enable

0: Disabled (default) 1: Enabled

3 Fan Speed Control 0 Enable

0: Disabled (default) 1: Enabled

2 Fan Speed Monitor 0 Enable

0: Disabled (default) 1: Enabled 0 TRI-STATE Control.When enabled and the device is inactive, the logical device output pins are in TRI-STATE. 0: Disabled (default) 1: Enabled

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2.18.4 Fan Speed Control and Monitor Configuration 2 Register

This register is reset by hardware to 00h. Location: Index F1h Type: R/W B i t 76543210 Name Reserved Fan Speed Invert 2 Enable Fan Speed Control 2 Enable Fan Speed Monitor 2 Enablel Reset 00000000 Bit Description 7-3 Reserved

2 Fan Speed Invert 2 Enable

0: Disabled (default) 1: Enabled

1 Fan Speed Control 2 Enable

0: Disabled (default) 1: Enabled

0 Fan Speed Monitor 2 Enable

0: Disabled (default) 1: Enabled

2.19 WATCHDOG TIMER (WDT) CONFIGURATION

2.19.1 Logical Device 10 (WDT) Configuration

Table 33 lists the configuration registers which affect the WATCHDOG Timer. Only the last register (F0h) is described here. Table 33. WDT Configuration Registers

2.19.2 WATCHDOG Timer Configuration Register

This register is reset by hardware to 02h.

1 Power Mode Control

WATCHDOG Timer clock disabled. (unlike Active bit in Index 30h that also prevents access to WATCHDOG Timer registers). WATCHDOG Timer clock enabled. WATCHDOG Timer is functional when the logical device is active (default). 0 TRI-STATE Control.When enabled and the device is inactive, the logical device output pins are in TRI-STATE.

3.0 System Wake-Up Control (SWC)

3.1 OVERVIEW

• Modem ring (RI1 andRI2 pins)
• Telephone ring (RING input pin)
• Keyboard activity or specific programmable key sequence
• Mouse activity or specific programmable sequence of clicks and movements
• Programmable Consumer Electronics IR (CEIR) address
• Wake-up on module IRQs for FDC, Parallel Port, Serial Ports 1 and 2, Mouse, KBC, ACB, Fan Speed Control and Monitor (FSCM) and WATCHDOG Timer (WDT)
• Eight VSB -powered, general-purpose input events (via GPIOE0-5 and GPIE6-7)
• 23 VDD -powered, GPIO-triggered events (via GPIO00-07, GPIO10-14, GPIO16-17 and GPIO40-47)
• Software event. The SWC notifies the device when any of these events occur by asserting one or more of the following output pins:
• Power-Up Request (PWUREQ)
• System Management Interrupt (SMI)
• Interrupt Request (via SERIRQ)
• Power Button (PWBT OUT) Figure 7 shows the block diagram of the SWC.

Figure 7. SWC Block Diagram

3.0 System Wake-Up Control (SWC)(Continued)

powered by VSB . These pins can be used to perform various tasks while VSB is present and VDD is not.

3.2 FUNCTIONAL DESCRIPTION

to determine the wake-up criteria, including the CEIR address and the keyboard sequence. Two Wake-Up Events Status registers (WK_STSn) hold a Status bit for each of the 16 events. 8 show the routing scheme of detected wake-up events to the various means of system notification. Figure 8. Wake-Up Events Routing Scheme or route it to an interrupt request channel via the device’s configuration registers.

Figure 9. Wake-Up Mode Control (Extension) Mechanism

• SLPS5 is active (the system is in Sleep State 5), or
• Legacy Power Button is enabled, or
• Power Button operation in Sleep State 3 is enabled. The two latter conditions are determined by device configuration registers. (Refer to theDevice Architecture and Configura- tion chapter.) In addition to monitoring various system events, the SWC operates several general-purpose I/O (GPIO) pins powered by VSB . Four runtime data registers (SB_GPDOn and SB_GPDIn) hold a Data Out bit and a Data In bit for each VSB powered GPIO pin. In addition, each GPIO pin has a dedicated configuration register that controls its characteristics. These configu- ration registers are accessed via a set of Standby GPIO Pin Select and Pin Configuration registers (SBGPSEL and SBG- PCFG). For a detailed description of the V SB powered GPIO pins, see Section 3.4.30. The SWC logic is powered by VSB . The SWC control and configuration registers are battery backed, powered by VPP . The setup of the wake-up events, including programmable sequences, is retained throughout power failures (no VSB ) as long as the battery is connected. VPP is taken from VSB if VSB is greater than the minimum (Min) value defined in theDevice Char- acteristics chapter; otherwise, VBAT is used as the VPP source. Hardware reset does not affect these registers. They are reset only by software reset or power-up of VPP .

3.3 EVENT DETECTION

3.3.1 Modem Ring

Port 2, respectively, and can be used as wake-up events.

3.3.2 Telephone Ring

78www.national.com The RING pulse-train detection is achieved by monitoring the falling edges onRING in time slots of 62.5 msec (a 16 Hz cycle). A positive detection occurs if falling edges ofRING are detected in three consecutive time slots, following a time slot in which noRING falling edge is detected. This detection method guarantees the detection of aRING pulse-train with fre- quencies higher than 16 Hz. It filters out (does not detect) pulses of less than 10 Hz, and may detect pulses between 10 Hz to 16 Hz.

3.3.3 Keyboard and Mouse Activity

The detection of either any activity or a specific predetermined keyboard or mouse activity can be used as a wake-up event. The keyboard wake-up detection can be programmed to detect:

• Any keystroke
• A specific programmable sequence of up to eight alphanumeric keystrokes
• Any programmable sequence of up to 8 bytes of data received from the keyboard. The mouse wake-up detection can be programmed to detect either any mouse click or movement, or a specific programma- ble click (left or right) or double-clicks. The keyboard or mouse event detection operates independently of the KBC (which is powered down with the rest of the system).

3.3.4 CEIR Address

A CEIR transmission received on an IRRX pin in a pre-selected standard (NEC, RCA or RC-5) is matched against a pro- grammable CEIR address. Detection of matching can be used as a wake-up event. Whenever an IR signal is detected, the receiver immediately enters the active state. When this happens, the receiver keeps sampling the IR input signal and generates a bit string where a logic 1 indicates an idle condition and a logic 0 indicates the presence of IR energy. The received bit string is de-serialized and assembled into 8-bit characters. The expected CEIR protocol of the received signal should be configured through bits 5,4 at the CEIR Wake-Up Control reg- ister (see Section 3.4.22). The CEIR Wake-Up Address register (IRWAD) holds the unique address to be compared with the address contained in the incoming CEIR message. If CEIR is enabled (bit 0 of the IRWCR register is 1) and an address match occurs, then the CEIR Event Status bit of the WK_STS0 register is set to 1 (see Section 3.4.2). The CEIR Address Shift register holds the received address which is compared with the address contained in the IRWAD. The comparison is affected also by the CEIR Wake-Up Address Mask register (IRWAM) in which each bit determines wheth- er to ignore the corresponding bit in the IRWAD. If CEIR routing to interrupt request is enabled, the assigned SWC interrupt request may be used to indicate that a complete address has been received. To get this interrupt when the address is completely received, the IRWAM should be written with FFh. Once the interrupt is received, the value of the address can be read from the ADSR register. Another parameter that is used to determine whether a CEIR signal is to be considered valid is the bit cell time width. There are four time ranges for the different protocols and carrier frequencies. Four pairs of registers define the low and high limits of each time range. (See Sections 3.4.29 through for more details regarding the recommended values for each protocol.) The CEIR address detection operates independently of the serial port with the IR (which is powered down with the rest of the system).

3.3.5 Standby General-Purpose Input Events

A general-purpose event is defined as the detection of falling edge, rising edge, low level or high level on a specific signal. Each signal’s event is configurable via software. GPIOE0-5 and GPIE6-7 may trigger a system notification by any of the means mentioned in Section 3.1. A debouncer of 16 ms is enabled (default) on each event. It may be disabled by software.

3.3.6 GPIO-Triggered Events

A GPIO-triggered event is defined as the detection of falling edge, rising edge, low level or high level on a specific GPIO signal whose status bit is routed to PWUREQ. Each signal’s event is configurable via software in the GPIO logical device configuration registers. GPIO00-07, GPIO10-14, GPIO16-17 and GPIO40-47 may trigger a system notification only by PWUREQ. Other means of system notification triggered by GPIOs are available via the GPIO logical device configuration registers. A debouncer of 16 ms is enabled (default) on each event. It may be disabled by software. All GPIO pins are powered by V DD , and therefore can cause an assertion ofPWUREQ only when V DD is present.

3.3.7 Software Event

A software event is defined as writing 1 to the Software Event Status bit of the WK_STS0 register. Once this bit is set to 1, it has the same effect as any other Event Status bit. Since WK_STS0 is accessible only when VDD is present, the Software Event can be activated only when VDD is present.

3.3.8 Module IRQ Wake-Up Event

FDC, Parallel Port, Serial Ports 1 and 2, Mouse, KBC, ACB and Fan Speed Control and Monitor (FSCM). bination of all IRQ signals of the logical devices for which wake-up on IRQ is enabled.

3.4 SWC REGISTERS

• Bank 0 holds the Keyboard/Mouse Control registers.
• Bank 1 holds the CEIR Control registers.
• Bank 2 holds the Event Routing Configuration and Wake-Up Extension Control registers.
• Bank 3 holds the Standby General-Purpose I/O (GPIO) Pins Configuration registers. The active bank is selected through the Configuration Bank Select field (bits 1-0) in the Wake-Up Configuration register (WK_CFG). See Section 3.4.6. As a programming aid, the registers are described in this chapter according to the following functional groupings:
• General status, enable, configuration and routing registers
• Extension enable registers
• PS/2 event configuration registers
• CEIR event configuration registers
• Standby GPIO configuration and control registers The following abbreviations are used to indicate the Register Type:
• R/W = Read/Write
• R = Read from a specific address returns the value of a specific register. Write to the same address is to a different register.
• W=W r i t e
• RO = Read Only
• R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.

3.4.1 SWC Register Map

The following tables list the SWC registers. For the SWC register bitmap, see Section 3.5. Table 36. Banks 0, 1, 2 and 3 - The Common Control and Status Register Map

Table 37. Bank 0 - PS/2 Keyboard/Mouse Wake-Up Configuration and Control Register Map Table 38. Bank 1 - CEIR Wake-Up Configuration and Control Register Map Table 39. Bank 2 - Event Routing Configuration Register Map

Table 40. Bank 3 - Standby GPIO Pin Configuration Register Map

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3.4.2 Wake-Up Events Status Register 0 (WK_STS0)

This register is set to 00h on power-up of VPP, VSB or software reset. It indicates which of the corresponding eight wake-up events have occurred. Writing 1 to a bit clears it to 0. Writing 0 has no effect. Bit 6 of this register has a special type, as described in the table below. Location: Offset 00h Type: R/W1C B i t 76543210 Name Module IRQ Event Status Software Event Status GPIO Event Status CEIR Event Status Mouse Event Status KBD Event Status RI2 Event Status RI1 Event Status Reset 00000000 Bit Description 7 Module IRQ Event Status.This sticky bit shows the status of the module IRQ event detection. 0: Event not active (default) 1: Event active 6 Software Event Status. Writing 1 to this bit inverts its value. 0: Event not active (default) 1: Event active 5 GPIO Event Status.This sticky bit shows the status of the V DD GPIO event detection. 0: Event not detected (default) 1: Event detected

4 CEIR Event Status

0: Event not detected (default) 1: Event detected

3 Mouse Event Status

0: Event not detected (default) 1: Event detected

2 KBD Event Status

0: Event not detected (default) 1: Event detected RI2 Event Status 0: Event not detected (default) 1: Event detected RI1 Event Status 0: Event not detected (default) 1: Event detected

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3.4.3 Wake-Up Events Status Register (WK_STS1)

This register is set to 00h on power-up of VPP, VSB or software reset. It indicates which of the corresponding eight wake-up events have occurred. Writing 1 to a bit clears it to 0. Writing 0 has no effect. Location: Offset 01h Type: R/W1C B i t 76543210 Name GPIE7 Event Status GPIE6 Event Status GPIE5 Event Status GPIE4/ RING Event Status GPIE3 Event Status GPIE2 Event Status GPIE1 Event Status GPIE0 Event Status Reset 00000000 Bit Description

7 GPIE7 Event Status

0: Event not detected (default) 1: Event detected

6 GPIE6 Event Status

0: Event not detected (default) 1: Event detected

5 GPIE5 Event Status

0: Event not detected (default) 1: Event detected

4 GPIE4/

RING Event Status.This sticky bit shows the status of either GPIE4 orRING event detection, according to the function currently selected on pin 27. 0: Event not detected (default) 1: Event detected

3 GPIE3 Event Status

0: Event not detected (default) 1: Event detected

2 GPIE2 Event Status

0: Event not detected (default) 1: Event detected

1 GPIE1 Event Status

0: Event not detected (default) 1: Event detected

0 GPIE0 Event Status

0: Event not detected (default) 1: Event detected

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3.4.4 Wake-Up Events Enable Register (WK_EN0)

This register is set to 00h on power-up of VPP or software reset. Detected wake-up events that are enabled activate the PWUREQ signal. Location: Offset 02h Type: R/W B i t 76543210 Name Module IRQ Event Enable Software Event Enable GPIO Event Enable CEIR Event Enable Mouse Event Enable KBD Event Enable RI2 Event Enable RI1 Event Enable Reset 00000000 Bit Description

7 Module IRQ Event Enable

0: Disabled (default) 1: Enabled

6 Software Event Enable

0: Disabled (default) 1: Enabled

5 GPIO Event Enable

0: Disabled (default) 1: Enabled

4 CEIR Event Enable

0: Disabled (default) 1: Enabled

3 Mouse Event Enable

0: Disabled (default) 1: Enabled

2 KBD Event Enable

0: Disabled (default) 1: Enabled RI2 Event Enable 0: Disabled (default) 1: Enabled RI1 Event Enable 0: Disabled (default) 1: Enabled

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3.4.5 Wake-Up Events Enable Register 1 (WK_EN1)

This register is set to 00h on power-up of VPP or software reset. Detected wake-up events that are enabled activate the PWUREQ signal. Location: Offset 03h Type: R/W B i t 76543210 Name GPIE7 Event Enable GPIE6 Event Enable GPIE5 Event Enable GPIE4/ RING Event Enable GPIE3 Event Enable GPIE2 Event Enable GPIE1 Event Enable GPIE0 Event Enable Reset 00000000 Bit Description

7 GPIE7 Event Enable

0: Disabled (default) 1: Enabled

6 GPIE6 Event Enable

0: Disabled (default) 1: Enabled

5 GPIE5 Event Enable

0: Disabled (default) 1: Enabled 0: Disabled (default) 1: Enabled

3 GPIE3 Event Enable

0: Disabled (default) 1: Enabled.

2 GPIE2 Event Enable

0: Disabled (default) 1: Enabled

1 GPIE1 Event Enable

0: Disabled (default) 1: Enabled

0 GPIE0 Event Enable

0: Disabled (default) 1: Enabled

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3.4.6 Wake-Up Configuration Register (WK_CFG)

This register is set to 00h on power-up of VPP or software reset. It enables access to CEIR registers, keyboard/mouse reg- isters, Event Routing Control registers or Standby GPIO registers. Location: Offset 04h Type: R/W B i t 76543210 Name Reserved Enable Power Button Pulse on S3 Swap KBC Inputs Configuration Bank Select Reset 00000000 Required 0 0 Bit Description 7-4 Reserved

3 Enable Power Button Pulse on S3

0: Disabled (default) 1: Enabled

2 Swap KBC Inputs

0: No swapping (default) 1: KBD (KBCLK, KBDAT) and Mouse (MCLK, MDAT) inputs swapped 1-0 Configuration Bank Select Bits 1 0 Bank Register 0 0 0 Keyboard/Mouse 0 1 1 CEIR 1 0 2 Event Routing, Wake-Up Extension 1 1 3 Standby GPIO

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3.4.7 Wake-Up Events Routing toSMI Enable Register 0 (WK_SMIEN0)

This register is set to 00h on power-up of VPP or software reset. It controls the routing of detected wake-up events to the SMI signal. Detected wake-up events that are enabled activate theSMI signal regardless of the value of the WK_EN0 reg- ister. Location: Bank 2, Offset 13h Type: R/W B i t 76543210 Name Reserved Software Event to SMI Enable Reserved CEIR Event to SMI Enable Mouse Event to SMI Enable KBD Event to SMI Enable RI2 Event to SMI Enable RI1 Event to SMI Enable Reset 00000000 Bit Description

6 Software Event to SMI Enable

0: Disabled (default) 1: Enabled

5 Reserved

4 CEIR Event to

0: Disabled (default) 1: Enabled

3 Mouse Event to

0: Disabled (default) 1: Enabled

2 KBD Event to

0: Disabled (default) 1: Enabled RI2 Event toSMI Enable 0: Disabled (default) 1: Enabled RI1 Event toSMI Enable 0: Disabled (default) 1: Enabled

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3.4.8 Wake-Up Events Routing toSMI Enable Register 1 (WK_SMIEN1)

This register is set to 00h on power-up of VPP or software reset. It controls the routing of detected wake-up events to the SMI signal. Detected wake-up events that are enabled activate theSMI signal regardless of the value of the WK_EN1 reg- ister. Location: Bank 2, Offset 14h Type: R/W B i t 76543210 Name GPIE7 Event to SMI Enable GPIE6 Event to SMI Enable GPIE5 Event to SMI Enable GPIE4/ RING Event to SMI Enable GPIE3 Event to SMI Enable GPIE2 Event to SMI Enable GPIE1 Event to SMI Enable GPIE0 Event to SMI Enable Reset 00000000 Bit Description

7 GPIE7 Event toSMI Enable

0: Disabled (default) 1: Enabled

6 GPIE6 Event to

0: Disabled (default) 1: Enabled

5 GPIE5 Event to

0: Disabled (default) 1: Enabled 0: Disabled (default) 1: Enabled

3 GPIE3 Event to

0: Disabled (default) 1: Enabled.

2 GPIE2 Event to

0: Disabled (default) 1: Enabled

1 GPIE1 Event to

0: Disabled (default) 1: Enabled

0 GPIE0 Event to

0: Disabled (default) 1: Enabled

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3.4.9 Wake-Up Events Routing to IRQ Enable Register 0 (WK_IRQEN0)

This register is set to 00h on power-up of VPP or software reset. It controls the routing of detected wake-up events to the assigned SWC interrupt request (IRQ) channel. Detected wake-up events that are enabled activate the assigned IRQ chan- nel regardless of the value of the WK_EN0 register. Location: Bank 2, Offset 15h Type: R/W B i t 76543210 Name Reserved Software Event to IRQ Enable Reserved CEIR Event to IRQ Enable Mouse Event to IRQ Enable KBD Event to IRQ Enable RI2 Event to IRQ Enable RI1 Event to IRQ Enable Reset 00000000 Bit Description

6 Software Event to IRQ Enable

0: Disabled (default) 1: Enabled

4 CEIR Event to IRQ Enable

0: Disabled (default) 1: Enabled

3 Mouse Event to IRQ Enable

0: Disabled (default) 1: Enabled

2 KBD Event to IRQ Enable

0: Disabled (default) 1: Enabled. RI2 Event to IRQ Enable 0: Disabled (default) 1: Enabled RI1 Event to IRQ Enable 0: Disabled (default) 1: Enabled

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3.4.10 Wake-Up Events Routing to IRQ Enable Register 1 (WK_IRQEN1)

This register is set to 00h on power-up of VPP or software reset. It controls the routing of detected wake-up events to the assigned SWC IRQ channel. Detected wake-up events that are enabled activate the IRQ signal regardless of the value of the WK_EN1 register. Location: Bank 2, Offset 16h Type: R/W B i t 76543210 Name GPIE7 Event to IRQ Enable GPIE6 Event to IRQ Enable GPIE5 Event to IRQ Enable GPIE4/ RING Event to IRQ Enable GPIE3 Event to IRQ Enable GPIE2 Event to IRQ Enable GPIE1 Event to IRQ Enable GPIE0 Event to IRQ Enable Reset 00000000 Bit Description

7 GPIE7 Event to IRQ Enable

0: Disabled (default) 1: Enabled

6 GPIE6 Event to IRQ Enable

0: Disabled (default) 1: Enabled

5 GPIOE5 Event to IRQ Enable

0: Disabled (default) 1: Enabled 0: Disabled (default) 1: Enabled

3 GPIE3 Event to IRQ Enable

0: Disabled (default) 1: Enabled.

2 GPIE2 Event to IRQ Enable

0: Disabled (default) 1: Enabled

1 GPIE1 Event to IRQ Enable

0: Disabled (default) 1: Enabled

0 GPIE0 Event to IRQ Enable

0: Disabled (default) 1: Enabled

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3.4.11 Wake-Up Extension 1 Enable Register 0 (WK_X1EN0)

This register is set to 1Fh on power-up of VPP or software reset. It controls the routing of raw wake-up events to event de- tectors while VDD is present. Wake-up events that are enabled are routed to their event detectors while VDD is present. Location: Bank 2, Offset 17h Type: R/W B i t 76543210 Name Reserved CEIR Event Ex. 1 Enable Mouse Event Ex. 1 Enable KBD Event Ex. 1 Enable RI2 Event Ex. 1 Enable RI1 Event Ex.1 Enable Reset 00011111 Bit Description 7-5 Reserved

4 CEIR Event Extension 1 Enable

0: Disabled 1: Enabled (default)

3 Mouse Event Extension 1 Enable

0: Disabled 1: Enabled (default)

2 KBD Event Extension 1 Enable

0: Disabled 1: Enabled (default) RI2 Event Extension 1 Enable 0: Disabled 1: Enabled (default) RI1 Event Extension 1 Enable 0: Disabled 1: Enabled (default)

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3.4.12 Wake-Up Extension 1 Enable Register 1 (WK_X1EN1)

This register is set to FFh on power-up of VPP or software reset. It controls the routing of raw wake-up events to event de- tectors while VDD is present. Wake-up events that are enabled are routed to their event detectors while VDD is present. Location: Bank 2, Offset 18h Type: R/W B i t 76543210 Name GPIE7 Event Ex. 1 Enable GPIE6 Event Ex. 1 Enable GPIE5 Event Ex. 1 Enable GPIE4/ RING Event Ex. 1 Enable GPIE3 Event Ex. 1 Enable GPIE2 Event Ex. 1 Enable GPIE1 Event Ex. 1 Enable GPIE0 Event Ex. 1 Enable Reset 11111111 Bit Description

7 GPIE7 Event Extension 1 Enable

0: Disabled 1: Enabled (default)

6 GPIE6 Event Extension 1 Enable

0: Disabled 1: Enabled (default)

5 GPIE5 Event Extension 1 Enable

0: Disabled 1: Enabled (default) RING Event Extension 1 Enable 0: Disabled 1: Enabled (default)

3 GPIE3 Event Extension 1 Enable

0: Disabled 1: Enabled (default)

2 GPIE2 Event Extension 1 Enable

0: Disabled 1: Enabled (default)

1 GPIE1 Event Extension 1 Enable

0: Disabled 1: Enabled (default)

0 GPIE0 Event Extension 1 Enable

0: Disabled 1: Enabled (default)

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3.4.13 Wake-Up Extension 2 Enable Register 0 (WK_X2EN0)

This register is set to 1Fh on power-up of VPP or software reset. It controls the routing of raw wake-up events to event de- tectors while VDD is not present. Wake-up events that are enabled are routed to their event detectors while VDD is not present. Location: Bank 2, Offset 19h Type: R/W B i t 76543210 Name Reserved CEIR Event Ex. 2 Enable Mouse Event Ex. 2 Enable KBD Event Ex. 2 Enable RI2 Event Ex. 2 Enable RI1 Event Ex. 2 Enable Reset 00011111 Bit Description 7-5 Reserved

4 CEIR Event Extension 2 Enable

0: Disabled 1: Enabled (default)

3 Mouse Event Extension 2 Enable

0: Disabled 1: Enabled (default)

2 KBD Event Extension 2 Enable

0: Disabled 1: Enabled (default) RI2 Event Extension 2 Enable 0: Disabled 1: Enabled (default) RI1 Event Extension 2 Enable 0: Disabled 1: Enabled (default)

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3.4.14 Wake-Up Extension 2 Enable Register 1 (WK_X2EN1)

This register is set to FFh on power-up of VPP or software reset. It controls the routing of raw wake-up events to event de- tectors while VDD is not present. Wake-up events that are enabled are routed to their event detectors while VDD is not present. Location: Bank 2, Offset 1Ah Type: R/W B i t 76543210 Name GPIE7 Event Ex. 2 Enable GPIE6 Event Ex. 2 Enable GPIE5 Event Ex. 2 Enable GPIE4/ RING Event Ex. 2 Enable GPIE3 Event Ex. 2 Enable GPIE2 Event Ex. 2 Enable GPIE1 Event Ex. 2 Enable GPIE0 Event Ex. 2 Enable Reset 11111111 Bit Description

7 GPIE7 Event Extension 2 Enable

0: Disabled 1: Enabled (default)

6 GPIE6 Event Extension 2 Enable

0: Disabled 1: Enabled (default)

5 GPIE5 Event Extension 2 Enable

0: Disabled 1: Enabled (default) RING Event Extension 2 Enable 0: Disabled 1: Enabled (default)

3 GPIE3 Event Extension 2 Enable

0: Disabled 1: Enabled (default)

2 GPIE2 Event Extension 2 Enable

0: Disabled 1: Enabled (default)

1 GPIE1 Event Extension 2 Enable

0: Disabled 1: Enabled (default)

0 GPIE0 Event Extension 2 Enable

0: Disabled 1: Enabled (default)

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3.4.15 Wake-Up Extension 3 Enable Register 0 (WK_X3EN0)

This register is set to 00h on power-up of VPP or software reset. It controls the routing of raw wake-up events to the Power Button pulse generator. Wake-up events that are enabled are routed to the Power Button pulse generator. Location: Bank 2, Offset 1Bh Type: R/W B i t 76543210 Name Reserved CEIR Event Ex. 3 Enable Mouse Event Ex. 3 Enable KBD Event Ex. 3 Enable RI2 Event Ex. 3 Enable RI1 Event Ex. 3 Enable Reset 00000000 Bit Description 7-5 Reserved

4 CEIR Event Extension 3 Enable

0: Disabled (default) 1: Enabled

3 Mouse Event Extension 3 Enable

0: Disabled (default) 1: Enabled

2 KBD Event Extension 3 Enable

0: Disabled (default) 1: Enabled RI2 Event Extension 3 Enable 0: Disabled (default) 1: Enabled RI1 Event Extension 3 Enable 0: Disabled (default) 1: Enabled

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3.4.16 Wake-Up Extension 3 Enable Register 1 (WK_X3EN1)

This register is set to 00h on power-up of VPP or software reset. It controls the routing of raw wake-up events to the Power Button pulse generator. Wake-up events that are enabled are routed to the Power Button pulse generator. Location: Bank 2, Offset 1Ch Type: R/W B i t 76543210 Name GPIE7 Event Ex. 3 Enable GPIE6 Event Ex. 3 Enable GPIE5 Event Ex. 3 Enable GPIE3/ RING Event Ex. 3 Enable GPIE3 Event Ex. 3 Enable GPIE2 Event Ex. 3 Enable GPIE1 Event Ex. 3 Enable GPIE0 Event Ex. 3 Enable Reset 00000000 Bit Description

7 GPIE7 Event Extension 3 Enable

0: Disabled (default) 1: Enabled

6 GPIE6 Event Extension 3 Enable

0: Disabled (default) 1: Enabled

5 GPIE5 Event Extension 3 Enable

0: Disabled (default) 1: Enabled RING Event Extension 3 Enable 0: Disabled (default) 1: Enabled

3 GPIE3 Event Extension 3 Enable

0: Disabled (default) 1: Enabled

2 GPIE2 Event Extension 3 Enable

0: Disabled (default) 1: Enabled

1 GPIE1 Event Extension 3 Enable

0: Disabled (default) 1: Enabled

0 GPIE0 Event Extension 3 Enable

0: Disabled (default) 1: Enabled

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3.4.17 PS/2 Keyboard and Mouse Wake-Up Events

The SWC can be configured to detect any predetermined PS/2 keyboard or mouse activity. The detection mechanisms for keyboard and mouse events are independent. Therefore, they can be operated simulta- neously with no interference. Since both mechanisms are implemented by hardware which is independent of the device’s keyboard controller, the keyboard controller itself need not be activated to detect either keyboard or mouse events. Keyboard Wake-Up Events The keyboard wake-up detection mechanism can be programmed to detect:

• Any keystroke
• A specific programmable sequence of up to eight alphanumeric keystrokes (Password mode)
• Any programmable sequence of up to 8 bytes of data received from the keyboard (Special Key Sequence mode). To program the keyboard wake-up detection mechanism to wake-up on any keystroke, perform the following sequence: 1. Put the wake-up mechansim in Special Key Sequence mode by setting bits 3-0 of the PS2CTL register to 0001b. 2. Set the PS2KEY0 and PS2KEY1 registers to 00h. This forces the wake-up detection mechanism to ignore the values of incoming data, thus causing it to wake-up on any keystroke. In Password mode, the Make and Break bytes transmitted by the keyboard are discarded, and only the scan codes are com- pared against those programmed in the PS2KEYn registers. To simplify the detection mechanism, only keys with a scan code of 1 byte can be included in the sequence to be detected. To program the keyboard wake-up detection mechanism to operate in Password mode, proceed as follows: 1. Set bits 3-0 of the PS2CTL register with a value that indicates the desired number of keystrokes in the sequence. The programmed value should be the number of keystrokes + 7. For example, to wake-up on a sequence of two keys, set bits 3-0 to 9h. 2. Program the appropriate subset of the PS2KEY0-PS2KEY7 registers, in sequential order, with the scan codes of the keys in the sequence. For example, if there are three keys in the sequence and the scan codes of these keys are 05h (first), 50h (second) and 44h (third), program PS2KEY0 to 05h, PS2KEY1 to 50h and PS2KEY2 to 44h (the scan codes are only examples). In Special Key Sequence mode, all the bytes transmitted by the keyboard are compared against the ones programmed in the PS2KEYn registers. These include also the Make and Break bytes. This mode enables the detection of any sequence of keystrokes, including also keys such as Shift and Alt. To program the keyboard wake-up detection mechanism to operate in Special Key Sequence mode, proceed as follows: 1. Set bits 3-0 of the PS2CTL register to a value that indicates the desired number of keystrokes in the sequence. The pro- grammed value should be the number of keystrokes + 1. For example, to wake-up on a sequence of three received bytes, set bits 3-0 of PS2CTL to 2h. 2. Program the appropriate subset of the PS2KEY0-PS2KEY7 registers, in sequential order, with the values of the data bytes that comprise the sequence. For example, if the number of bytes in the sequence is four, and the values of these bytes are E0h (first), 5Bh (second), E0h (third) and DBh (fourth), program PS2KEY0 to E0h, PS2KEY1 to 5Bh, PS2KEY2 to E0h and PS2KEY3 to DBh (the byte values are only examples). Mouse Wake-Up Events The mouse wake-up detection mechanism can be programmed to detect either any mouse click or movement, or a specific programmable click (left or right) or double-click. To program this mechanism to wake-up on a specific event, set bits 6-4 of the PS2CTL register to the required value, ac- cording to the description of these bits in Section 3.4.18.

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3.4.18 PS/2 Protocol Control Register (PS2CTL)

This register is set to 00h on power-up of VPP or software reset. It configures the PS/2 keyboard and mouse wake-up fea- tures. Before changing bits 6-4 or 3-0, clear them to 0 and then write the new value. Location: Bank 0, Offset 13h Type: R/W

3.4.19 Keyboard Data Shift Register (KDSR)

This register is set to 00h on power-up of V PP or software reset. It stores the keyboard data shifted in from the keyboard during transmission, only when keyboard wake-up detection is enabled. Location: Bank 0, Offset 16h Type: RO B i t 76543210 Name Disable Parity Check Mouse Wake-Up Configuration Keyboard Wake-Up Configuration Reset 00000000 Bit Description

7 Disable Parity Check

0: Enabled (default) 1: Disabled 6-4 Mouse Wake-Up Configuration Bits 6 5 4 Configuration 0 0 0 Disable mouse wake-up detection 0 0 1 Wake-up on any mouse movement or button click 0 1 0 Wake-up on left button click 0 1 1 Wake-up on left button double-click 1 0 0 Wake-up on right button click 1 0 1 Wake-up on right button double-click 1 1 0 Wake-up on any button single-click (left, right or middle) 1 1 1 Wake-up on any button double-click (left, right or middle) 3-0 Keyboard Wake-Up Configuration Bits 3 2 1 0 Configuration 0 0 0 0 Disable keyboard wake-up detection 0 0 0 1 to Special key sequence 2-8 PS/2 scan codes, “Make” and “Break” (including Shift and Alt keys) 0 1 1 1 1 0 0 0 to Password enabled with 1-8 keys “Make” code (excluding Shift and Alt keys) 1 1 1 1 B i t 76543210 Name Keyboard Data Reset 00000000

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3.4.20 Mouse Data Shift Register (MDSR)

This register is set to 00h on power-up of VSB or software reset. It stores the mouse data shifted in from the mouse during transmission, only when mouse wake-up detection is enabled. Location: Bank 0, Offset 17h Type: RO

3.4.21 PS/2 Keyboard Key Data Registers (PS2KEY0 - PS2KEY7)

Eight registers (PS2KEY0-PS2KEY7) store the scan codes for the password or key sequence of the keyboard wake-up fea- ture, as follows:

• PS2KEY0 register stores the scan code for the first key in the password/key sequence.
• PS2KEY1 register stores the scan code for the second key in the password/key sequence.
• PS2KEY2 - PS2KEY7 registers store the scan codes for the third to eighth keys in the password/key sequence. When one of these registers is set to 00h, it indicates that the value of the corresponding scan code byte is ignored (not compared). These registers are set to 00h on power-up of VPP or software reset. Location: Bank 0, Offset 18h-1Fh Type: R/W B i t 76543210 Name Reserved Mouse Data Reset 00000000 B i t 76543210 Name Scan Code of Keys 0-7 Reset 00000000

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3.4.22 CEIR Wake-Up Control Register (IRWCR)

This register is set to 00h on power-up of VPP or software reset. Location: Bank 1, Offset 13h Type: R/W B i t 76543210 Name Reserved CEIR Protocol Select Select IRRX2 Input Invert IRRXn Input Reserved CEIR Enable Reset 00000000 Bit Description 7-6 Reserved 5-4 CEIR Protocol Select Bits 5 4 Protocol 0 0 RC5 (default) 0 1 NEC/RCA

1 X Reserved

3 Select IRRX2 Input.Selects the IRRX input. 0: IRRX1 (default) 1: IRRX2

2 Invert IRRXn Input

0: Not inverted (default) 1: Inverted 1 Reserved.

0 CEIR Enable

0: CEIR is disabled. Registers are maintained, but CEIR Event Status bit (of WK0_STS) does not reflect CEIR events. (Unlike the CEIR Event Enable bit of WK0_EN that does not affect the CEIR Event Status bit.) (default) 1: CEIR is enabled

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3.4.23 CEIR Wake-Up Address Register (IRWAD)

This register holds the unique address to be compared with the address contained in the incoming CEIR message. If CEIR is enabled (bit 0 of the IRWCR register is 1) and an address match occurs, then bit 5 of the WK0_STS register is set to 1 (see Section 3.4.2). This register is set to 00h on power-up of V PP or software reset. Location: Bank 1, Offset 15h Type: R/W

3.4.24 CEIR Wake-Up Address Mask Register (IRWAM)

Each bit in this register determines whether the corresponding bit in the IRWAD register is enabled in the address compar- ison. Bits 5, 6 and 7 must be set to 1 if the RC-5 protocol is selected. This register is set to E0h on power-up of V PP or software reset. Location: Bank 1, Offset 16h Type: R/W B i t 76543210 Name CEIR Wake-Up Address Reset 00000000 B i t 76543210 Name CEIR Wake-Up Address Mask Reset 11100000 Bit Description 7-0 CEIR Wake-Up Address Mask. If the corresponding bit is 0, the address bit is not masked (enabled for compare). If the corresponding bit is 1, the address bit is masked (ignored during compare).

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3.4.25 CEIR Address Shift Register (ADSR)

This register holds the received address to be compared with the address contained in the IRWAD register. This register is set to 00h on power-up of VPP or software reset. Location: Bank 1, Offset 17h Type: RO

3.4.26 CEIR Wake-Up Range 0 Registers

These registers define the low and high limits of time range 0. The values are represented in units of 0.1 msec. For the RC-5 protocol, the bit cell width must fall within this range for the cell to be considered valid. The nominal cell width is 1.778 msec for a 36 KHz carrier. IRWTR0L and IRWTR0H should be set to 10h and 14h respectively (default). For the NEC protocol, the time distance between two consecutive CEIR pulses that encodes a bit value of 0 must fall within this range. The nominal distance for a 0 is 1.125 msec for a 38 KHz carrier. IRWTR0L and IRWTR0H should be set to 09h and 0Dh respectively. IRWTR0L Register This register is set to 10h on power-up of V PP or software reset. Location: Bank 1, Offset 18h Type: R/W IRWTR0H Register This register is set to 14h on power-up of V PP or software reset. Location: Bank 1, Offset 19h Type: R/W B i t 76543210 Name CEIR Address Reset 00000000 B i t 76543210 Name Reserved CEIR Pulse Change, Range 0, Low Limit Reset 00010000 B i t 76543210 Name Reserved CEIR Pulse Change, Range 0, High Limit Reset 00010100

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3.4.27 CEIR Wake-Up Range 1 Registers

These registers define the low and high limits of time range 1. The values are represented in units of 0.1 msec. For the RC-5 protocol, the pulse width defining a half-bit cell must fall within this range in order for the cell to be considered valid. The nominal pulse width is 0.889 for a 38 KHz carrier. IRWTR1L and IRWTR1H should be set to 07h and 0Bh respectively (de- fault). For the NEC protocol, the time between two consecutive CEIR pulses that encodes a bit value of 1 must fall within this range. The nominal time for a 1 is 2.25 msec for a 36 KHz carrier. IRWTR1L and IRWTR1H should be set to 14h and 19h respectively. IRWTR1L Register This register is set to 07h on power-up of V PP or software reset. Location: Bank 1, Offset 1Ah Type: R/W IRWTR1H Register This register is set to 0Bh on power-up of V PP or software reset. Location: Bank 1, Offset 1Bh Type: R/W

3.4.28 CEIR Wake-Up Range 2 Registers

These registers define the low and high limits of time range 2. The values are represented in units of 0.1 msec. These reg- isters are not used when the RC-5 protocol is selected. For the NEC protocol, the header pulse width must fall within this range in order for the header to be considered valid. The nominal value is 9 msec for a 38 KHzcarrier.IRWTR2L and IRWTR2H should be set to 50h and 64h respectively (default). IRWTR2L Register This register is set to 50h on power-up of V pp or software reset. Location: Bank 1, Offset 1Ch Type: R/W IRWTR2H Register This register is set to 64h on power-up of V pp or software reset. Location: Bank 1, Offset 1Dh Type: R/W B i t 76543210 Name Reserved CEIR Pulse Change, Range 1, Low Limit Reset 00000111 B i t 76543210 Name Reserved CEIR Pulse Change, Range 1, High Limit Reset 00001011 B i t 76543210 Name CEIR Pulse Change, Range 2, Low Limit Reset 01010000 B i t 76543210 Name CEIR Pulse Change, Range 2, High Limit Reset 01100100

3.4.29 CEIR Wake-Up Range 3 Registers

isters are not used when the RC-5 protocol is selected. nominal value is 4.5 msec for a 36 KHzcarrier.IRWTR3L and IRWTR3H should be set to 28h and 32h respectively (default). This register is set to 28h on power-up of Vpp or software reset. are represented in hexadecimal code where the units are of 0.1 msec. Table 41. Time Range Limits for CEIR Protocols

3.4.30 Standby General-Purpose I/O (SBGPIO) Register Overview

• GPIOE0-5 are GPIO pins.
• GPIE6,7 and GPIS2,3 are GPI pins.
• GPOS0,1 are GPO pins. For programming convenience, these pins are associated with two SBGPIO ports. Specifically, GPIE0-5 and GPIE6,7 are associated with bits 0 to 7 of SBGPIO port 0, respectively , and GPOS0,1 and GPIS2,3 are associated with bits 0 to 3 of SBGPIO port 1, respectively. Table 42 provides a summary of the SBGPIO pin-to-port assignment and pin types.

Table 42. SBGPIO Pin Types and Associated Port

• Software capability to manipulate and read pin levels
• Controllable system notification by several means based on the pin level or level transition
• Ability to capture and manipulate events and their associated status
• Back-drive protected pins. SBGPIO port operation is associated with two sets of registers:
• Pin configuration registers, mapped in the SWC register bank 3. These registers are used to statically set up the log- ical behavior of each pin. There is one 8-bit register for each SBGPIO pin.
• Two 8-bit runtime registers: SBGPIO Data Out (SBGPDO) and SBGPIO Data In (SBGPDI). These registers are mapped in the SWC device I/O space (determined by the base address registers in the SWC Device Configuration). They are used to manipulate and/or read the pin values. Each runtime register corresponds to the 8-pin port de- scribed above (see Table 42). Each SBGPIO pin is associated with up to six configuration bits and the corresponding bit slice of the two runtime registers, as shown in Figure 10. The SBGPIO port has basic as well as enhanced functionality. Basic functionality includes the manipulation and reading of the SBGPIO pins, as described in Section . Enhanced functionality includes event detection, as described in Event Detec- tion. Pin(s) Port Type Event Detection GPIOE0-5 0 I/O Y es GPIE6,7 0 I Y es GPOS0,1 1 O No GPIS2,3 1 I No

Figure 10. SBGPIO Port Architecture and SBGPDI. The configuration and operation of a single pin (pin n in port X) is shown in Figure 11. Figure 11. SBGPIO Basic Functionality

8 SBGPIO Pin Configuration

• Pin Direction - Controlled by Output Enable (bit 0)
• Output Type - Push-pull vs. open-drain. It is controlled by Output Type (bit 1) by enabling/disabling the pull-up portion of the output buffer.
• Weak Static Pull-up - May be added to any type of port (input, open-drain or totem pole). It is controlled by Pull-Up Control (bit 2).
• Pin Lock - A GPIO pin may be locked to prevent any changes in the output value and/or the output characteristics. The lock is controlled by Lock (bit 3). It disables writes to the SBGPDO register bits, and to bits 0-3 of the Standby GPIO Pin Configuration register (Including the Lock bit itself). Once locked, it can be released by hardware reset only. Operation The value that is written to the SBGPDO register is driven to the pin, if the output is enabled. Reading from the SBGPDO register returns its contents, regardless of the pin value or the port configuration. The SBGPDI register is a read-only register. Reading from the SBGPDI register returns the pin value, regardless of what is driving it (the port itself, configured as an output port, or the external device when the port is configured as an input port). Writing to this register is ignored. Activation of the SBGPIO port is controlled by the same external, device-specific configuration bit (or a combination of bits) that control the activation of the SWC. When the SWC logical device is inactive, access to both the SBGPDI and SBGPDO registers is disabled. However, there is no change in the port configuration and in the SBGPDO value, and hence there is no effect on the outputs of the pins. Event Detection The enhanced SBGPIO port supports input event detection. This functionality is based on three configuration bits. The con- figuration and operation of the event detection capability is shown in Figure 12. An SWC status register reflects the status of each input event. SWC configuration registers determine the effect of each input event on the various means of system notification available in the SWC.

Figure 12. Event Detection

108www.national.com Event Configuration Each pin in the SBGPIO port is a potential input event source. The event detection can trigger a system notification upon predeter- mined behavior of the source pin. The SBGPIO Pin Configuration register determines the event detection trigger type for the system notification.

• Event Type and Polarity - Two trigger types of event detection are supported: edge and level. An edge event may be detected upon a source pin transition either from high to low or low to high. A level event may be detected when the source pin is in active level. The trigger type is determined by Event Type (bit 4). The direction of the transition (for edge) or the polarity of the active level (for level) is determined by Event Polarity (bit 5).
• Event Debounce Enable - The input signal can be debounced for about 15 msec before entering the detector. The signal state is transferred to the detector only after a debouncing period during which the signal has no transitions, to ensure that the signal is stable. The debouncer adds 15 msec delay to both assertion and de-assertion of the event pending indicator. Therefore, when working with a level event and system notification by either SMI or IRQ, it is recommended to disable the debounce if the delay in theSMI/IRQ de-assertion is not acceptable. The debounce is controlled by Event Debounce Enable (bit 6 of the SBGPIO Pin Configuration register).

3.4.31 Standby GPIO Pin Select Register (SBGPSEL)

This register selects the GPIOE/GPIE pin (port number and pin number) to be configured (the register accessed by the Standby GPIO Pin Configuration register). This register is reset to 00h on VPP power-up or software reset. When port 0 is selected, bits 2-0 select between pins GPIE7,6 and GPIOE5-0. When port 1 is selected, bits 2-0 select be- tween pins GPOS0 and GPOS1. Pins GPIS2 and GPIS3 are input only and require no configuration. Location: Bank 3, Offset 13h Type: R/W B i t 76543210 Name Reserved Port Select Reserved Pin Select Reset 00000000 Bit Description 7-5 Reserved 4 Port Select.This bit selects the GPIO port to be configured. 0: Port 0 (default) 1: Port 1 2-0 Pin Select. These bits select the GPIO pin to be configured in the selected port.

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3.4.32 Standby GPIO Pin Configuration Register (SBGPCFG)

This is a group of twelve configuration registers. Eight are identical for GPIOE and GPIE, two are identical for GPOS, and . two are identical for GPIS. Each GPIOE/GPIE register is associated with one GPIOE/GPIE pin, and each GPOS and GPIS register is associated with one GPOS or GPIS pin. The entire set is mapped to the same address. The mapping scheme is based on the Standby GPIO Pin Select (SBGPSEL) register that functions as an index register, and the specific Standby GPIO Pin Configuration register that reflects the configuration of the currently selected pin. Bits 0-3 are applicable only for pins GPIOE0-5 and GPOS0,1. Bits 4-6 are applicable for all GPIOE/GPIE pins. Location: Bank 3, Offset 14h Type: R/W (bit 3 is set only) For GPIOE and GPIE: For GPOS: For GPIS: B i t 76543210 Name Reserved Event Debounce Enable Event Polarity Event Type Lock Pull-Up Control Output Type Output Enable Reset 01000100 B i t 76543210 Name Reserved Lock Pull-Up Control Output Type Output Enable Reset 00000101 B i t 76543210 Name Reserved Reset 00000000 Bit Description

7 Reserved (for GPOS and GPIS, bits 7-4 and 7-0 are reserved, respectively)

6 Event Debounce Enable

0: Disabled 1: Enabled (default) 5 Event Polarity.This bit defines the polarity of the signal that causes a detection of an event from the corresponding GPIO pin. 0: Falling edge or low level input (default) 1: Rising edge or high level input 4 Event Type.This bit defines the signal type that causes a detection of an event from the corresponding GPIO pin. 0: Edge input (default) 1: Level input 3 Lock. This bit locks bits 2-0 of this register. These bits are associated with the GPIO pin currently selected by the SBGPSEL register. Once this bit is set to 1 by software, it can only be cleared to 0 by V SB power-up reset. 0: No effect (default at VSB power-up reset) 1: Direction, output type, pull-up and output value locked

110www.national.com 2 Pull-Up Control.This bit is used to enable/disable the internal pull-up capability of the corresponding GPIO pin. It supports open-drain output signals with internal pull-ups and TTL input signals. 0: Disabled 1: Enabled (default) 1 Output Type.This bit controls the output buffer type (open-drain or totem pole) of the corresponding GPIO pin. 0: Open-drain (default) 1: Push-pull 0 Output Enable.For GPOS, this is a R/O bit. It indicates the GPOS pin output state, and is always 1. For GPIOE and GPIE, this bit indicates the GPIO pin output state. It has no effect on input. 0: TRI-STATE (default for GPIOE/GPIE) 1: Output enabled (default for GPOS) Bit Description

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3.4.33 Standby GPIOE/GPIE Data Out Register 0 (SB_GPDO0)

This register is set to 3Fh on VPP power-up or software reset, only when the Lock bit of the SBGPCFG register is set to 0. It determines the value to be driven on the GPIOE pins when configured as outputs. Location: Offset 08h Type: R/W

3.4.34 Standby GPIOE/GPIE Data In Register 0 (SB_GPDI0)

This register reflects the values of the GPIE7-6 and GPIOE5-0 pins. Write to this register is ignored. Location: Offset 09h Type: RO B i t 76543210 Name Reserved Data Out Reset 00111111 Bit Description 7-6 Reserved Data Out.Bits 5-0 correspond to pins GPIOE5-0 respectively. The value of each bit determines the value driven on the corresponding GPIOE pin when its output buffer is enabled. Writing to the bit latches the written data unless the bit is locked by the corresponding GPIOE Configuration Lock bit. Reading the bit returns its value, regardless of the pin value and configuration. 0: Corresponding pin level low when output enabled 1: Corresponding pin level high (according to buffer type and static pull-up selection) when output enabled B i t 76543210 Name Data In Reset XXXXXXXX Bit Description Data In.Bits 7-0 correspond to pins GPIE7-6 and GPIOE5-0 respectively. Reading each bit returns the value of the corresponding GPIE/GPIOE pin regardless of the pin configuration and the SB0_GPDO register value. 0: Corresponding pin level low 1: Corresponding pin level high

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3.4.35 Standby GPOS Data Out Register 1 (SB_GPDO1)

This register is set to 03h on VPP power-up or software reset, only when the Lock bit of the SBGPCFG register is set to 0 . It determines the value to be driven on the GPSO0,1 pins. Location: Offset 0Ah Type: R/W

3.4.36 Standby GPIS Data In Register 1 (SB_GPDI1)

This register reflects the values of the GPOS0,1 and GPIS2,3 pins. Write to this register is ignored. Location: Offset 0Bh Type: RO B i t 76543210 Name Reserved Data Out Reset 00000011 Bit Description 7-2 Reserved 1-0 Data Out.Bits 1-0 correspond to pins GPOS1-0 respectively. The value of each bit determines the value driven on the corresponding GPOS pin when its output buffer is enabled. Writing to the bit latches the written data unless the bit is locked by the corresponding GPOS Configuration Lock bit. Reading the bit returns its value, regardless of the pin value and configuration. 0: Corresponding pin level low 1: Corresponding pin level high (according to buffer type and static pull-up selection) B i t 76543210 Name Reserved Data In Reset XXXXXXXX Bit Description 7-4 Reserved 3-0 Data In.Reading each bit returns the value of the corresponding GPOS/GPIS pin. 0: Corresponding pin level low 1: Corresponding pin level high

3.5 SWC REGISTER BITMAP

Table 43. Banks 0 and 1 - The Common Register Bitmap Table 44. Bank 0 - PS/2 Keyboard/Mouse Wake-Up Configuration and Control Registers Bitmap Table 45. Bank 1 - CEIR Wake-Up Configuration and Control Registers Bitmap

Table 46. Bank 2 - Event Routing Control Registers Bitmap

115 www.national.com 1Bh WK_X3EN0 Reserved CEIR Event Ex.

3 Enable

Event Ex. Event Ex. 3 Enable RI2 Event Ex. 3 Enable RI1 Event Ex. 3 Enable 1Ch WK_X3EN1 GPIE7 Event Ex. 3 Enable GPIE6 Event Ex. 3 Enable GPIE5 Event Ex. 3 Enable GPIE4/ RING Event Ex. 3 Enable GPIE3 Event Ex. 3 Enable GPIE2 Event Ex. 3 Enable GPIE1 Event Ex. 3 Enable GPIE0 Event Ex. 3 Enable 1Dh- 1Fh Reserved

116www.national.com Bank 3 - Standby General-Purpose I/O Configuration Registers Bitmap Register Bits Offset Mnemonic 7 6 5 4 3 2 1 0 13h SBGPSEL Reserved Port Select Reserved Pin Select 14h SBGPCFG Reserved Event Debounce Enable Event Polarity Event Type Lock Pull-Up Control Output Type Output Enable 15h- 1Fh Reserved

4.0 Fan Speed Control

4.1 OVERVIEW

Architecture and Configuration chapter. input without any external circuitry. Figure 13. Fan Speed Control - System Configuration

4.2 FUNCTIONAL DESCRIPTION

Duty Cycle register (FCDCR), used to determine the duty cycle of the FANOUT between 0 to 100%. ternal configuration bit, in which case the FANOUT duty cycle is ([256-FCDCR]/256)*100. The default selection of 24 MHz input clock allows a programmable FANOUT frequency in the range of 756 Hz to 93.75 KHz. For lower frequencies, selecting the 200 KHz input clock allows a frequency range of 6 Hz to 781 Hz. See Figure 14. Warning! The contents of the FCPSR register must not be changed when the Fan Speed Control is enabled.

24 MHz

Figure 14. PWM Generator (FANOUT)

200 KHz

1 FANOUT

4.0 Fan Speed Control(Continued)

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4.3 FAN SPEED CONTROL REGISTERS

The following abbreviations are used to indicate the Register Type:

• R/W = Read/Write
• R = Read from a specific address returns the value of a specific register. Write to the same address is to a different register.
• W=W r i t e
• RO = Read Only
• R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.

4.3.1 Fan Speed Control Register Map

4.3.2 Fan Speed Control Pre-Scale Register (FCPSR)

Location: Device specific Type: R/W Offset Mnemonic Register Name Type Section Device specificNote 1. Note 1. The location of this register is defined in theDevice Architecture and Configuration chapter. FCPSR Fan Speed Control Pre-Scale R/W 4.3.2 Device specificNote 1. FCDCR Fan Speed Control Duty Cycle R/W 4.3.3 B i t 76543210 Name Clock Select Pre-Scale Value Reset 00000000 Bit Description 7 Clock Select.This bit selects the input clock for the clock divider. 0: 24 MHz 1: 200 KHz 6-0 Pre-Scale Value.The clock divider for the input clock (24 MHz or 200 KHz) is Pre-Scale Value + 1. Writing 0000000b to these bits transfers the input clock directly to the counter. The maximum clock divider is 124 (7Bh +1). These bits must not be programmed with the values 7Ch, 7Dh, 7Eh and 7Fh as this may produce unpredictable results. The contents of this register should not be changed when the corresponding Fan Speed Control Enable bit of the Fan Speed Control Configuration register is 1 (see Device Architecture and Configurationchapter) as this may produce unpredictable results.

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4.3.3 Fan Speed Control Duty Cycle Register (FCDCR)

Location: Device specific Type: R/W

4.4 FAN SPEED CONTROL BITMAP

7-0 Duty Cycle.The binary value of this 8-bit field determines the number of clock cycles, out of a 256-cycle period, during which the PWM output is high (while FANOUT is either equal to or the inverse of the PWM output, depending on the Inverse FANOUT configuration bit). 00h: PWM output is continuously low 01h - FEh: PWM output is high for [Duty Cycle Value] clock cycles and low for [256-Duty Cycle Value] clock cycles FFh: PWM output is continuously high Register Bits Offset Mnemonic 76543210 Device specific Note 1. Note 1. The location of this register is defined in theDevice Architecture and Configuration chapter. FCPSR Clock Select Pre-Scale Value Device specific Note 1. FCDCR Duty Cycle Value

5.0 Fan Speed Monitor

5.1 OVERVIEW

Architecture and Configuration chapter. indicates whether the speed is just below the threshold or inefficiently low to consider the fan stopped. Figure 15 shows the basic system configuration of the Fan Speed Monitor. Figure 15. Fan Speed Monitor - System Configuration

5.2 FUNCTIONAL DESCRIPTION

Speed Monitor through the FANIN input pin. Measuring the time between these pulses is the basis for speed monitoring. 16 is a general block diagram of the Fan Speed Monitor. Speed Ready bit is set to 1. Upon reading FMSPR, the Speed Ready bit of the FMCSR is cleared to 0. register value is lower than the threshold. NCBTP value that generated the interrupt remains available for the interrupt handler. If the counter passes FFh, the Overflow bit is set to 1, the FMSPR register is cleared, and the interrupt is asserted, if enabled. The Overflow bit is cleared to 0 when it is written with 1, after which speed measurement resumes. µsec. This filter can be by-passed when setting bit 4 of the FMCSR register to 1.

5.0 Fan Speed Monitor(Continued)

Figure 16. Fan Speed Monitor

5.3 FAN SPEED MONITOR REGISTERS

to operate) without causing system alert.

• Over Threshold. A status bit that indicates that the NCBTP has exceeded the threshold (the speed has dropped below the allowed minimum).
• Overflow. A status bit that indicates that the NCBTP is higher than FFh. With a proper input clock selection, this means that the speed is inefficiently low and is considered stopped.
• Speed Ready. A status bit that indicates that new, valid data has been loaded into the FMSPR register.
• Clock Select. A 2-bit control field that selects the counter clock rate as either 2 KHz, 4 KHz, 8 KHz or 16 KHz. The following abbreviations are used to indicate the Register Type:
• R/W = Read/Write
• R = Read from a specific address returns the value of a specific register. Write to the same address is to a different register.
• W=W r i t e
• RO = Read Only
• R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.

5.3.1 Fan Speed Monitor Register Map

Note 1. The location of this register is defined in theDevice Architecture and Configuration chapter.

16 Khz

8 Khz

4 Khz

2 Khz

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5.3.2 Fan Monitor Threshold Register (FMTHR)

This 8-bit register contains the programmable threshold for the fan. This threshold is the maximum number of clock cycles between consecutive tachometer pulses (frequencies of 16, 8, 4 or 2 KHz). It represents the minimum fan speed permitted in the system. If the period between consecutive tachometer pulses is greater than the threshold, an interrupt (if enabled) is issued. After reset, the value of FMTHR is FFh. This register should not be changed when the corresponding Fan Monitor Enable bit is set to 1 (enabled), since this may cause unpredictable results. Location: Device specific Type: R/W

5.3.3 Fan Monitor Speed Register (FMSPR)

This read-only 8-bit register holds the speed reading, represented by number of clock cycles between consecutive tachom- eter pulses. For details, refer to Section 5.2. When the Speed Ready bit of the FMCSR register is 1, FMSPR holds valid data that has not yet been read. It is cleared to 00h upon any of the following conditions:

• System reset
• Fan Monitor Enable bit is set to 0
• Overflow bit is set to 1. Location: Device specific Type: RO

5.3.4 Fan Monitor Control and Status Register (FMCSR)

Location: Device specific Type: Varies per bit B i t 76543210 Name Threshold Value Reset 11111111 B i t 76543210 Name Fan Speed Reading Reset 00000000 B i t 76543210 Name Reserved Clock Select Filter Disable Interrupt Enable Overflow Over Threshold Speed Ready Reset 00100000

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5.4 FAN SPEED MONITOR BITMAP

6-5 R/W Clock Select.Selects the clock source provided to the counter. These bits must not be changed when the corresponding Fan Monitor Enable bit is 1 (enabled). 00: 16 KHz 01: 8 KHz (default) 10: 4 KHz 11: 2 KHz 4 R/W Filter Disable. When this bit is set to 1, the digital filter is disabled. When it is cleared, the filter is enabled. This bit should not be changed when the corresponding Fan Monitor Enable bit is 1 (enabled) to avoid unpredictable results. 0: Digital filter enabled (default) 1: Digital filter disabled 3 R/W Interrupt Enable. This bit controls the assertion of overflow interrupt and Over Threshold interrupt. 0: Interrupt disabled (default) 1: Interrupt enabled. Interrupt is asserted when an Over Threshold bit, Overflow bit or both are set to 1. 2 R/W1C Overflow . Indicates that the counter has passed FFh, and the fan speed is inefficiently slow; i.e., slower than 60∗ f/(256∗ n). Writing 1 to this bit clears it to 0. 0: No overflow occurred since the last time this bit was cleared (by reset or by writing 1) 1: Counter passed FFh 1 R/W1C Over Threshold. Indicates that the value loaded into the FMSPR register upon detection of the rising edge of the FANIN pulse exceeded the threshold value. 0: FMSPR register value did not exceed the threshold since the last time this bit was cleared (by reset or by writing 1) 1: FMSPR register value exceeded the threshold 0R O Speed Ready. This bit indicates that the speed register holds new (not yet read) and valid data. It is set to 1 on each rising edge of the FANIN input (starting from the second one) if the Over Threshold bit is 0. It is cleared to 0 whenever the speed register is read, or when the Overflow bit is set. 0: No new valid data in the FMSPR register (data is either invalid or has already been read) 1: FMSPR register loaded with new and valid data Register Bits Offset Mnemonic 7 6 5 43210 Device specific Note 1. Note 1. The location of this register is defined in theDevice Architecture and Configuration chapter. FMTHR Threshold Value Device specific Note 1. FMSPR Fan Speed Reading Device specific Note 1. FMCSR Reserved Clock Select Filter Disable Interrupt Enable Overflow Over Threshold Speed Ready

6.0 General-Purpose Input/Output (GPIO) Port

This chapter describes one 8-bit port. A device may include a combination of several ports with different implementations. For the device specific implementation, see theDevice Architecture and Configuration chapter.

6.1 OVERVIEW

• Software capability to manipulate and read pin levels
• Controllable system notification by several means based on the pin level or level transition
• Ability to capture and manipulate events and their associated status
• Back-drive protected pins. GPIO port operation is associated with two sets of registers:
• Pin Configuration registers, mapped in the Device Configuration space. These registers are used to statically set up the logical behavior of each pin. There are two 8-bit register for each GPIO pin.
• Four 8-bit runtime registers: GPIO Data Out (GPDO), GPIO Data In (GPDI), GPIO Event Enable (GPEVEN) and GPIO Event Status (GPEVST). These registers are mapped in the GPIO device IO space (which is determined by the base address registers in the GPIO Device Configuration). They are used to manipulate and/or read the pin val- ues, and to control and handle system notification. Each runtime register corresponds to the 8-pin port, such that bit n in each one of the four registers is associated with GPIOXn pin, where X is the port number. Each GPIO pin is associated with ten configuration bits and the corresponding bit slice of the four runtime registers, as shown in Figure 17. The functionality of the GPIO port is divided into basic functionality that includes the manipulation and reading of the GPIO pins, and enhanced functionality. The basic functionality is described in Section 6.2. The enhanced functionality which in- cludes the event detection and system notification is described in Section 6.3.

Figure 17. GPIO Port Architecture

8 GPCFG

8 GPEVR

6.0 General-Purpose Input/Output (GPIO) Port(Continued)

6.2 BASIC FUNCTIONALITY

GPDI. The configuration and operation of a single pin GPIOXn (pin n in port X) is shown in Figure 18. Figure 18. GPIO Basic Functionality

6.2.1 Configuration Options

• Port Direction - Controlled by the Output Enable bit (bit 0)
• Output Type - Push-pull vs. open-drain. It is controlled by Output Buffer Type (bit 1) by enabling/disabling the pull-up portion of the output buffer.
• Weak Static Pull-up - May be added to any type of port (input, open-drain or push-pull). It is controlled by Pull-Up Control (bit 2).
• Pin Lock - GPIO pin may be locked to prevent any changes in the output value and/or the output characteristics. The lock is controlled by Lock (bit 3). It disables writes to the GPDO register bits, and to bits 0-3 of the GPCFG register (In- cluding the Lock bit itself). Once locked, it can be released by hardware reset only.

6.2.2 Operation

the external device when the port is configured as an input port). Writing to this register is ignored. port configuration and in the GPDO value, and hence there is no effect on the outputs of the pins.

6.3 EVENT HANDLING AND SYSTEM NOTIFICATION

capability is shown in Figure 19. The operation of system notification is illustrated in Figure 20. Figure 19. Event Detection

6.3.1 Event Configuration

the active level (for level) is determined by Event Polarity (bit 5 of the GPCFG register).

6.3.2 System Notification

• Interrupt Request (via the device’s Bus Interface)
• System Management Interrupt (SMI, via the device’s Bus Interface)
• Power-Up Request (PWUREQ, via the System Wake-Up Control) The system notification for each GPIO pin is controlled by the corresponding bits in the GPEVEN and GPEVR registers. System notification by a GPIO pin is enabled if the corresponding bit of the GPEVEN register is set to 1. The corresponding bits in the GPEVR register select which means of system notification the detected event is routed to. The event routing mechanism is described in Figure 20. Event Enable Event Polarity Detected Enabled Events GPIO Pins Input Debouncer Event Internal Bus Pin Level =1 R/W 1 to ClearStatus Rising Edge or Rising Edge Detector from other High Level =1 GPIO Pin Configuration Register Event Type Event Debounce Enable R/W Bit 6 Bit 5 Bit 4 Indicator Pending

Figure 20. GPIO Event Routing Mechanism falling edge).Active levelrefers to the GPIO pin level that matches the Event Polarity bit (1 for high level and 0 for low level). bit settings. Writing 1 to the Status bit clears it to 0. Writing 0 is ignored.

• The Event Type is level and the pin is in active level, or
• The Event Type is edge and the corresponding bit of the GPST register is set. The target means of system notification is asserted if at least one GPIO pin is in event pending state. The selection of the target means of system notification is determined by the GPEVR register. If IRQ is selected as one of the means for the system notification, the specific IRQ line is determined by the IRQ selection procedure of the device configura- tion. The assertion of any means of system notification is blocked when the GPIO functional block is deactivated. If the output of a GPIO pin is enabled, it may be put in event pending state by the software when writing to the GPDO register. An pending edge event may be cleared by clearing the corresponding GPST bit. However, a level event source may not be released by software (except for disabling the source), as long as the pin is in active level. When level event is used, it is recommended to disable the input debouncer. Upon de-activation of the GPIO port, the GPST register is cleared and access to both the GPST and GPEVEN registers is disabled. All system notification means including the target IRQ line are detached from the GPIO and de-asserted. Before enabling any system notification, it is recommended to set the desired event configuration, and then verify that the status registers are cleared.

6.4 GPIO PORT REGISTERS

• R/W = Read/Write
• R = Read from a specific address returns the value of a specific register. Write to the same address is to a different register.
• W=W r i t e
• RO = Read Only
• R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect. Event Pending Indicator SMI IRQ Event Routing Logic PWUREQ Enable Enable IRQ GPIO Pin Event Routing Register Bit 2 Bit 1 Bit 0 Routed Events from other GPIO PinsRouting RoutingRouting PWUREQ Enable SMI

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6.4.1 GPIO Pin Configuration (GPCFG) Register

This is a group of eight identical configuration registers, each of which is associated with one GPIO pin. The entire set is mapped to the PnP configuration space. The mapping scheme is based on the GPSEL register that functions as an index register, and the specific GPCFG register that reflects the configuration of the currently selected pin. For details on the GPSEL register, refer to the Device Architecture and Configuration chapter. Bits 4-6 are applicable only for the enhanced GPIO port with event detection support. In the basic port. these bits are re- served, return 0 on read and have no effect on port functionality. Location: Device specific Type: R/W (bit 3 is set only) B i t 76543210 Name Reserved Event Debounce Enable Event Polarity Event Type Lock Pull-Up Control Output Type Output Enable Reset 01000100 Bit Description 0: Disabled 1: Enabled (default) 5 Event Polarity.This bit defines the polarity of the signal that causes a detection of an event from the corresponding GPIO pin (falling/low or rising/high). 0: Falling edge or low level input (default) 1: Rising edge or high level input 4 Event Type.This bit defines the signal type that causes a detection of an event from the corresponding GPIO pin. 0: Edge input (default) 1: Level input 3 Lock. This bit locks the corresponding GPIO pin. Once this bit is set to 1 by software, it can only be cleared to 0 by system reset or power-off. Pin multiplexing is functional until the Multiplexing Lock bit is 1. (Refer to the Device Architecture and Configurationchapter.) 0: No effect (default) 1: Direction, output type, pull-up and output value locked 2 Pull-Up Control. This bit is used to enable/disable the internal pull-up capability of the corresponding GPIO pin. It supports open-drain output signals with internal pull-ups and TTL input signals 0: Disabled 1: Enabled (default) 1 Output Type.This bit controls the output buffer type (open-drain or push-pull) of the corresponding GPIO pin. 0: Open-drain (default) 1: Push-pull 0 Output Enable.This bit indicates the GPIO pin output state. It has no effect on input. 0: TRI-STATE (default) 1: Output enabled

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6.4.2 GPIO Pin Event Routing (GPEVR) Register

This is a group of eight identical configuration registers, each of which is associated with one GPIO pin. The entire set is mapped to the PnP configuration space. The mapping scheme is based on the GPSEL register that functions as an index register, and the specific GPER register that reflects the routing configuration of the currently selected pin. For details on the GPSEL register, refer to the Device Architecture and Configuration chapter. This set of registers is applicable only for the enhanced GPIO port with event detection support. In the basic port this register set is reserved, returns 0 on read and has no effect on port functionality. Location: Device specific Type: R/W

6.4.3 GPIO Port Runtime Register Map

2 GPIO Event toPWUREQ Enable . This bit is used to enable/disable the routing of the corresponding GPIO detected event toPWUREQ. 0: Disabled (default) 1: Enabled

1 GPIO Event to

SMI Enable.This bit is used to enable/disable the routing of the corresponding GPIO detected event toSMI. 0: Disabled (default) 1: Enabled 0 GPIO Event to IRQ Enable.This bit is used to enable/disable the routing of the corresponding GPIO detected event to IRQ. 0: Disabled 1: Enabled (default) Offset Mnemonic Register Name Type Section Device specific Note 1. Note 1. The location of this register is defined in theDevice Architecture and Configuration chapter in Section 2.15.1. GPDO GPIO Data Out R/W 6.4.4 Device specificNote 1. GPDI GPIO Data In RO 6.4.5 Device specificNote 1. GPEVEN GPIO Event Enable R/W 6.4.6 Device specificNote 1. GPEVST GPIO Event Status R/W1C 6.4.7

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6.4.4 GPIO Data Out Register (GPDO)

Location: Device specific Type: R/W

6.4.5 GPIO Data In Register (GPDI)

Location: Device specific Type: RO B i t 76543210 Name Data Out Reset 11111111 Bit Description Data Out.Bits 7-0 correspond to pins 7-0 respectively. The value of each bit determines the value driven on the corresponding GPIO pin when its output buffer is enabled. Writing to the bit latches the written data unless the bit is locked by the GPCFG register Lock bit. Reading the bit returns its value, regardless of the pin value and configuration. 0: Corresponding pin driven to low when output enabled 1: Corresponding pin driven or released to high (according to buffer type and static pull-up selection) when output enabled B i t 76543210 Name Data In Reset XXXXXXXX Bit Description Data In.Bits 7-0 correspond to pins 7-0 respectively. Reading each bit returns the value of the corresponding GPIO pin, regardless of the pin configuration and the GPDO register value. Write is ignored. 0: Corresponding pin level low 1: Corresponding pin level high

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6.4.6 GPIO Event Enable Register (GPEVEN)

Location: Device specific Type: R/W

6.4.7 GPIO Event Status Register (GPEVST)

Location: Device specific Type: R/W1C B i t 76543210 Name Event Enable Reset 00000000 Bit Description Event Enable.Bits 7-0 correspond to pins 7-0 respectively. Each bit enables system notification triggering by the corresponding GPIO pin. The bit has no effect on the corresponding Status bit in the GPST register. 0: IRQ generation by corresponding GPIO pin masked 1: IRQ generation by corresponding GPIO pin enabled B i t 76543210 Name Status Reset 00000000 Bit Description Status.Bits 7-0 correspond to pins 7-0 respectively. Each bit is an edge detector that is set to 1 by the hardware upon detection of an active edge (i.e. edge that matches the IRQ Polarity bit) on the corresponding GPIO pin. This edge detection is independent of the Event Type or the Event Enable bit in the GPEVEN register. However, the bit may reflect the event status for enabled, edge-trigger event sources. Writing 1 to the Status bit clears it to 0. 0: No active edge detected since last cleared 1: Active edge detected

7.0 WATCHDOG Timer (WDT)

7.1 OVERVIEW

tion of system events for a predefined period of time (1 to 255 minutes). able on a status bit that can be read by the host. This chapter describes the generic WATCHDOG Timer functional block. A device may include a different implementation. Device Architecture and Configuration chapter.

7.2 FUNCTIONAL DESCRIPTION

WDO pin and indicates that the timeout period has expired. Figure 21 shows the functionality of the WATCHDOG Timer. (pulled low) and theWDO Status bit is cleared to 0. value is written, a new countdown starts as described above. If 00h is written, the timer is deactivated.

• Reset,
• Activating the WATCHDOG Timer or
• Writing to the WDTO register. The WDO output is asserted (low) and theWDO status is set to zero (active) when the counter reaches zero. When an IRQ is assigned to the WATCHDOG Timer (through the WATCHDOG Timer device configuration), the selected IRQ level is active as long as theWDO status bit is low (active).

Figure 21. WATCHDOG Timer Functional Diagram

7.0 WATCHDOG Timer (WDT) (Continued)

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7.3 WATCHDOG TIMER REGISTERS

The WATCHDOG Timer registers at offsets 00h-02h relative to the WATCHDOG base address, are shown in the following register map. The base address is defined by designated registers in the WATCHDOG Timer device configuration register set. The following abbreviations are used to indicate the Register Type:

• R/W = Read/Write
• R = Read from a specific address returns the value of a specific register. Write to the same address is to a different register.
• W=W r i t e
• RO = Read Only
• R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.

7.3.1 WATCHDOG Timer Register Map

7.3.2 WATCHDOG Timeout Register (WDTO)

This register holds the programmable timeout period, between 1 and 255 minutes. Writing to this register de-asserts the WDO output and sets theWDO status bit to 1 (inactive). Additionally, writing to this register is interpreted as a command for starting or stopping the WATCHDOG Timer, according to the data written. If a non-zero value is written, the timer is activated (countdown starts). If a non-zero value is written when the counter is running, the timer is immediately reloaded with the new value and starts counting down from the new value. If 00h is written, the timer and its outputs are de-activated. Location: Offset 00h Type: R/W Offset Mnemonic Register Name Type Section 00h WDTO WATCHDOG Timeout R/W 7.3.2 01h WDMSK WATCHDOG Mask R/W 7.3.3 02h WDST WATCHDOG Status RO 7.3.4 03h Reserved B i t 76543210 Name Programmed Timeout Period Reset 00000000 Bit Description 7-0 Programmed Timeout Period.These bits hold the binary value of the timeout period in minutes (1 to 255). A value of 00h halts the counter and forces the outputs to inactive levels. A device reset clears the register to 00h. 00h: Timer and WDO outputs inactive 01h-FFh: Programmed timeout period (in minutes)

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7.3.3 WATCHDOG Mask Register (WDMSK)

This register is used to determine which system events (IRQ) are enabled as WATCHDOG Timer trigger events. An enabled IRQ event becomes a trigger event that causes the timer to reload the WDTO and restart the countdown. This register enables or masks the trigger events that restart the WATCHDOG timer. Location: Offset 01h Type: R/W B i t 7654 3 2 10 Name Reserved Serial Port 2 IRQ Trigger Enable Serial Port 1 IRQ Trigger Enable Mouse IRQ Trigger Enable KBD IRQ Trigger Enable Reset 0000 0 0 00 Bit Description 7-4 Reserved 3 Serial Port 2 IRQ Trigger Enable.This bit enables the IRQ assigned to Serial Port 2 to trigger WATCHDOG Timer reloading. 0: Serial Port 2 IRQ not a trigger event 1: An active Serial Port 2 IRQ enabled as a trigger event 2 Serial Port 1 IRQ Trigger Enable.This bit enables the IRQ assigned to Serial Port 1 to trigger WATCHDOG Timer reloading. 0: Serial Port 1 IRQ not a trigger event 1: An active Serial Port 1 IRQ enabled as a trigger event 1 Mouse IRQ Trigger Enable.This bit enables the IRQ assigned to the Mouse to trigger WATCHDOG Timer reloading. 0: Mouse IRQ not a trigger event 1: An active Mouse IRQ enabled as a trigger event 0 KBD IRQ Trigger Enable.This bit enables the IRQ assigned to the Keyboard to trigger reloading of the WATCHDOG timer. 0: Keyboard IRQ not a trigger event 1: An active Keyboard IRQ enabled as a trigger event

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7.3.4 WATCHDOG Status Register (WDST)

This register holds the WATCHDOG Timer status, which reflects the value of theWDO pin and indicates that the timeout period has expired. On reset or on WATCHDOG Timer activation, this register is initialized to 01h. Location: Offset 02h Type: RO

7.4 WATCHDOG TIMER REGISTER BITMAP

0 WDO Value. This bit reflects the value of theWDO signal (even ifWDO is not configured for output). 0:WDO active 1:WDO inactive (default) Register Bits Offset Mnemonic 7 6 5 4 3 2 1 0 00h WDTO Programmed Timeout Period 01h WDMSK Reserved Serial Port 2 IRQ Trigger Enable Serial Port 1 IRQ Trigger Enable Mouse IRQ Trigger Enable KBD IRQ Trigger Enable 02h WDST Reserved WDO Value

ers, ADC, DAC, clock chips and peripheral drivers. Device Architecture and Configuration chapter.

8.1 OVERVIEW

to a positive supply via an internal or external pull-up resistor, and remain high even when the bus is idle. Each IC has a unique address and can operate as a transmitter or a receiver (though some peripherals are only receivers). tiator and clock generator) relationship is unchanged, even though their transmitter/receiver functions are reversed.

8.2 FUNCTIONAL DESCRIPTION

8.2.1 Data Transactions

using the synchronous serial clock. Acknowledge signal must follow. The following sections provide further details of this process. allowing the software to handle this bit.

8.2.2 Start and Stop Conditions

another device to be accessed, or a change in the direction of data transfer. Figure 22. Bit Transfer

8.2.3 Acknowledge (ACK) Cycle

signal sent by the receiving device (see Figure 24). Figure 23. Start and Stop Conditions Figure 24. ACCESS.bus Data Transaction Figure 25. ACCESS.bus Acknowledge Cycle

8.2.4 Acknowledge after Every Byte Rule

1. When the master is the receiver, it must indicate to the transmitter the end of data by not acknowledging (negative ac-

(generated by the master), but the SDA line is not pulled down.

1. When the receiver is full, otherwise occupied, or a problem has occurred, it sends a negative acknowledge to indicate

that it cannot accept additional data bytes.

8.2.5 Addressing Transfer Formats

being addressed. The slave device should send an acknowledge signal on the SDA line once it recognizes its address. ends the transaction of SDA (see Figure 26). device acts either as a transmitter or a receiver.

8.2.6 Arbitration on the Bus

sampled on the SDA line differs from the value driven by the device. (An exception to this rule is SDA while receiving data. with the shortest clock high period. to slave mode and continue to sample SDA to check if it is being addressed by the winning master on the bus. Figure 26. A Complete ACCESS.bus Data Transaction

8.0 ACCESS.bus Interface (ACB)(Continued) 139 www.national.com

8.2.7 Master Mode

An ACCESS.bus transaction starts with a master device requesting bus mastership. It asserts a Start Condition, followed by the address of the device it wants to access. If this transaction is successfully completed, the software may assume that the device has become the bus master. For the device to become the bus master, the software should perform the following steps: 1. Configure the INTEN bit of the ACBCTL1 register to the desired operation mode (Polling or Interrupt) and set the START bit of this register. This causes the ACB to issue a Start Condition on the ACCESS.bus when the ACCESS.bus becomes free (BB bit of the ACBCST register is cleared, or other conditions that can delay start). It then stalls the bus by holding SCL low. 2. If a bus conflict is detected (i.e., another device pulls down the SCL signal), the BER bit of the ACBST register is set. 3. If there is no bus conflict, the MASTER bit of the ACBST register and the SCAST of the ACBST register are set. 4. If the INTEN bit of the ACBCTL1 register is set and either the BER or SDAST bit of the ACBST register is set, an interrupt is issued. Sending the Address Byte When the device is the active master of the ACCESS.bus (the MASTER bit of the ACBST register is set), it can send the address on the bus. The address sent should not be the device’s own address, as defined by the ADDR bit of the ACBADDR register if the SAEN bit of this register is set, nor should it be the global call address if the GCMTCH bit of the ACBCST register is set. To send the address byte, use the following sequence: 1. For a receive transaction where the software wants only one byte of data, it should set the ACB bit of the ACBCTL1 Registe. If only an address needs to be sent or if the device requires stall for some other reason, set the STASTRE bit of the ACBCTL1 register. 2. Write the address byte (7-bit target device address) and the direction bit to the ACBSDA register. This causes the ACB to generate a transaction. At the end of this transaction, the acknowledge bit received is copied to the NEGACK bit of the ACBST register. During the transaction, the SDA and SCL lines are continuously checked for conflict with other de- vices. If a conflict is detected, the transaction is aborted, the BER bit of the ACBST register is set and the MASTER bit of this register is cleared. 3. If the STASTRE bit of the ACBCTL1 register is set and the transaction was successfully completed (i.e., both the BER and NEGACK bits of the ACBST register are cleared), the STASTR bit is set. In this case, the ACB stalls any further ACCESS.bus operations (i.e., holds SCL low). If the INTEN bit of the ACBCTL1 register is set, it also sends an interrupt request to the host. 4. If the requested direction is transmit and the start transaction was completed successfully (i.e., neither the NEGACK nor the BER bit of the ACBST register is set, and no other master has accessed the device), the SDAST bit of the ACBST register is set to indicate that the ACB awaits attention. 5. If the requested direction is receive, the start transaction was completed successfully and the STASTRE bit of the ACBCTL1 register is cleared, the ACB starts receiving the first byte automatically. 6. Check that both the BER and NEGACK bits of the ACBST register are cleared. If the INTEN bit of the ACBCTL1 register is set, an interrupt is generated when either the BER or NEGACK bit of the ACBST register is set. Master Transmit After becoming the bus master, the device can start transmitting data on the ACCESS.bus. To transmit a byte in an interrupt or polling controlled operation, the software should: 1. Check that both the BER and NEGACK bits of the ACBST register are cleared, and that the SDAST bit of the ACBST register is set. If the STASTRE bit of the ACBCTL1 register is set, also check that the STASTR bit of the ACBST register is cleared (and clear it if required). 2. Write the data byte to be transmitted to the ACBSDA register. When either the NEGACK or BER bit of the ACBST register is set, an interrupt is generated. When the slave responds with a negative acknowledge, the NEGACK bit of the ACBST register is set and the SDAST bit of the ACBST register remains cleared. In this case, if the INTEN bit of the ACBCTL1 register is set, an interrupt is issued.

8.0 ACCESS.bus Interface (ACB)(Continued) 140www.national.com Master Receive After becoming the bus master, the device can start receiving data on the ACCESS.bus. To receive a byte in an interrupt or polling operation, the software should: 1. Check that the SDAST bit of the ACBST register is set and that the BER bit is cleared. If the STASTRE bit of the ACBCTL1 register is set, also check that the STASTRE bit of the ACBST register is cleared (and clear it if required). 2. Set the ACK bit of the ACBCTL1 register to 1, if the next byte is the last byte that should be read. This causes a negative acknowledge to be sent. 3. Read the data byte from the ACBSDA register. Before receiving the last byte of data, set the ACK bit of the ACBCTL1 register. Master Stop To end a transaction, set the STOP bit of the ACBCTL1 register before clearing the current stall flag (i.e., the SDAST, NEGACK or STASTR bit of the ACBST register). This causes the ACB to send a Stop Condition immediately, and to clear the STOP bit of the ACBCTL1 register. A Stop Condition may be issued only when the device is the active bus master (the MASTER bit of the ACBST register is set). Master Bus Stall The ACB can stall the ACCESS.bus between transfers while waiting for the host response. The ACCESS.bus is stalled by holding the SCL signal low after the acknowledge cycle. Note that this is interpreted as the beginning of the following bus operation. The user must make sure that the next operation is prepared before the flag that causes the bus stall is cleared. The flags that can cause a bus stall in master mode are:

• Negative acknowledge after sending a byte (NEGACK bit of the ACBST register =1).
• SDAST bit of the ACBST register =1.
• STASTRE bit of the ACBCTL1 register =1, after a successful start (STASTR bit of the ACBST register =1). Repeated Start A repeated start is performed when the device is already the bus master (MASTER bit of the ACBST register is set). In this case, the ACCESS.bus is stalled and the ACB awaits host handling due to the following states in the ACBST register: neg- ative acknowledge (NEGACK bit =1), empty buffer (SDAST bit =1) and/or a stall after start (STASTR bit =1). For a repeated start: 1. Set the START bit of the ACBCTL1 register =1. 2. In master receive mode, read the last data item from ACBSDA. 3. Follow the address send sequence, as described in “Sending the Address Byte”. 4. If the ACB was awaiting handling (STASTR bit of the ACBST register =1), clear it only after writing the requested address and direction to ACBSDA. Master Error Detection The ACB detects illegal Start or Stop Conditions (i.e., a Start or Stop Condition within the data transfer, or the acknowledge cycle) and a conflict on the data lines of the ACCESS.bus. If an illegal condition is detected, BER is set, and master mode is exited (MASTER bit of the ACBST. register is cleared). Bus Idle Error Recovery When a request to become the active bus master or a restart operation fails, the BER bit of the ACBST register is set to indicate the error. In some cases, both the device and the other device may identify the failure and leave the bus idle. In this case, the start sequence may be incomplete and the ACCESS.bus may remain deadlocked. To recover from deadlock, use the following sequence: 1. Clear the BER and BB bits of the ACBCST register. 2. Wait for a timeout period to check that there is no other active master on the bus (the BB bit remains cleared). 3. Disable, and re-enable the ACB to put it in the non-addressed slave mode. This completely resets the functional block. At this point, some of the slaves may not identify the bus error. To recover, the ACB becomes the bus master: it asserts a Start Condition, sends an address byte, then asserts a Stop Condition which synchronizes all the slaves.

8.0 ACCESS.bus Interface (ACB)(Continued) 141 www.national.com

8.2.8 Slave Mode

A slave device waits in idle mode for a master to initiate a bus transaction. Whenever the ACB is enabled and it is not acting as a master (the MASTER bit of the ACBST register is cleared), it acts as a slave device. Once a Start Condition on the bus is detected, the device checks whether the address sent by the current master matches either:

• The ADDR bit value of the ACBADDR register, if the SAEN bit =1, or
• The general call address if the GCMEN bit of the ACBCTL1 register =1. This match is checked even when the MASTER bit is set. If a bus conflict (on SDA or SCL) is detected, the BER bit of the ACBST register is set, the MASTER bit is cleared and the device continues to search the received message for a match. If an address match or a global match is detected: 1. The device asserts its SDA pin during the acknowledge cycle. 2. The MATCH bit of the ACBCST register and the NMATCH bit of the ACBST register are set. If the XMIT bit of the ACBST register is set (slave transmit mode), the SDAST bit of the ACBST register is set to indicate that the buffer is empty. 3. If the INTEN bit of the ACBCTL1 register is set, an interrupt is generated the NMINTE bit is also set. 4. The software then reads the XMIT bit of the ACBST register to identify the direction requested by the master device. It clears the NMATCH bit of the ACBST Registe so future byte transfers are identified as data bytes. Slave Receive and Transmit Slave receive and transmit are performed after a match is detected and the data transfer direction is identified. After a byte transfer, the ACB extends the acknowledge clock until the software reads or writes the ACBSDA register. The receive and transmit sequences are identical to those used in the master routine. Slave Bus Stall When operating as a slave, the device stalls the ACCESS.bus by extending the first clock cycle of a transaction in the fol- lowing cases:
• SDAST bit of the ACBST register is set.
• NMATCH bit of the ACBST register and NMINTE bit of the ACBCTL1 register are set. Slave Error Detection The ACB detects illegal Start and Stop Conditions on the ACCESS.bus (i.e., a Start or Stop Condition within the data transfer or the acknowledge cycle). When this occurs, the BER bit is set and MATCH and GMATCH are cleared, setting the ACB as an unaddressed slave.

8.2.9 Configuration

The SDA and SCL are open-drain signals. The device permits the user to define whether to enable or disable the internal pull-up of each of these signals. ACB Clock Frequency The ACB permits the user to set the clock frequency for the ACCESS.bus clock. The clock is set by the the SCLFRQ field of the ACBCTL2 register, which determines the SCL clock period used by the device. This clock low period may be extended by stall periods initiated by the ACB or by another ACCESS.bus device. In case of a conflict with another bus master, a short- er clock high period may be forced by the other bus master until the conflict is resolved.

8.0 ACCESS.bus Interface (ACB)(Continued) 142www.national.com

8.3 ACB REGISTERS

The following abbreviations are used to indicate the Register Type:

• R/W = Read/Write
• R = Read from a specific address returns the value of a specific register. Write to the same address is to a different register.
• W=W r i t e
• RO = Read Only
• R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.

8.3.1 ACB Register Map

8.3.2 ACB Serial Data Register (ACBSDA)

This shift register is used to transmit and receive data. The most significant bit is transmitted (received) first, and the least significant bit is transmitted (received) last. Reading or writing to the ACBSDA register is allowed only when the SDAST bit of the ACBST register is set, or for repeated starts after setting the START bit. An attempt to access this register under other conditions may produce unpredictable results. Location: Offset 00h Type: R/W Offset Mnemonic Register Name Type Section 00h ACBSDA ACB Serial Data R/W 8.3.2 01h ACBST ACB Status Varies per bit 8.3.3 02h ACBCST ACB Control Status Varies per bit 8.3.4 03h ACBCTL1 ACB Control 1 R/W 8.3.5 04h ACBADDR ACB Own Address R/W 8.3.6 05h ACBCTL2 ACB Control 2 R/W 8.3.7 B i t 76543210 Name ACB Serial Data Reset

8.0 ACCESS.bus Interface (ACB)(Continued) 143 www.national.com

8.3.3 ACB Status Register (ACBST)

This register maintains the current ACB status. On reset, and when the ACB is disabled, ACBST is cleared (00h). Location: Offset 01h Type: Varies per bit B i t 76543210 Name SLVSTP SDAST BER NEGACK STASTR NMATCH MASTER XMIT Reset 00000000 Bit Type Description 7 R/W1C SLVSTP (Slave Stop). Writing 0 to SLVSTP is ignored. 0: Writing 1 or ACB disabled 1: Stop Condition detected after a slave transfer in which MATCH or GCMATCH was set 6R O SDAST (SDA Status) 0: Reading from the ACBSDA register during a receive, or when writing to it during a transmit. When ACBCTL1.START is set, reading the ACBSDA register does not clear SDAST. This enables ACB to send a repeated start in master receive mode. 1: SDA Data register awaiting data (transmit - master or slave) or holds data that should be read (receive - master or slave). 5 R/W1C BER (Bus Error). Writing 0 to BER is ignored. 0: Writing 1 or ACB disabled 1: Start or Stop Condition detected during data transfer (i.e., Start or Stop Condition during the transfer of bits 2 through 8 and acknowledge cycle), or when an arbitration problem is detected. 4 R/W1C NEGACK (Negative Acknowledge) . Writing 0 to NEGACK is ignored. 0: Writing 1 or ACB disabled 1: Transmission not acknowledged on the ninth clock (In this case, SDAST is not set) 3 R/W1C STASTR (Stall After Start). Writing 0 to STASTR is ignored. 0: Writing 1 or ACB disabled 1: Address sent successfully (i.e., a Start Condition sent without a bus error, or Negative Acknowledge), if ACBCTL1.STASTRE is set. This bit is ignored in slave mode. When STASTR is set, it stalls the ACCESS.bus by pulling down the SCL line, and suspends any further action on the bus (e.g., receive of first byte in master receive mode). In addition, if ACBCTL1.INTEN is set, it also causes the ACB to send an interrupt. 2 R/W1C NMATCH (New Match ). Writing 0 to NMATCH is ignored. If ACBCTL1.INTEN is set, an interrupt is sent when this bit is set. 0: Software writes 1 to this bit 1: Address byte follows a Start Condition or a repeated start, causing a match or a global-call match. 1R O Master 0: Arbitration loss (BER is set) or recognition of a Stop Condition 1: Bus master request succeeded and master mode active 0R O XMIT (Transmit). Direction bit. 0: Master/slave transmit mode not active 1: Master/slave transmit mode active

8.0 ACCESS.bus Interface (ACB)(Continued) 144www.national.com

8.3.4 ACB Control Status Register (ACBCST)

This register configures and controls the ACB functional block. It maintains the current ACB status and controls several ACB functions. On reset and when the ACB is disabled, the non-reserved bits of ACBCST are cleared. Location: Offset 02h Type: Varies per bit B i t 76543210 Name Reserved TGSCL TSDA GCMTCH MATCH BB BUSY Reset 0 0 0 X 0000 Bit Type Description 7-6 Reserved 5 R/W TGSCL (Toggle SCL Line). Enables toggling the SCL line during error recovery. 0: Clock toggle completed 1: When the SDA line is low, writing 1 to this bit toggles the SCL line for one cycle. Writing 1 to TGSCL while SDA is high is ignored. 4R O TSDA (Test SDA Line). This bit reads the current value of the SDA line. It can be used while recovering from an error condition in which the SDA line is constantly pulled low by an out-of-sync slave. Data written to this bit is ignored. 3R O GCMTCH (Global Call Match) 0: Start Condition or repeated Start and a Stop Condition (including illegal Start or Stop Condition) 1: In slave mode, ACBCTL1.GCMEN is set and the address byte (the first byte transferred after a Start Condition) is 00h. 2R O MATCH (Address Match ) 0: Start Condition or repeated Start and a Stop Condition (including illegal Start or Stop Condition) 1: ACBADDR.SAEN is set and the first 7 bits of the address byte (the first byte transferred after a Start Condition) match the 7-bit address in the ACBADDR register.

1 R/W1C BB (Bus Busy)

0: Writing 1, ACB disabled, or Stop Condition detected 1: Bus active (a low level on either SDA or SCL), or Start Condition 0R O Busy. This bit should always be written 0. This bit indicates the period between detecting a Start Condition and completing receipt of the address byte. After this, the ACB is either free or enters slave mode. 0: Completion of any state below or ACB disabled 1: ACB is in one of the following states: — Generating a Start Condition — Master mode (ACBST.MASTER is set) — Slave mode (ACBCST.MATCH or ACBCST.GCMTCH set).

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8.3.5 ACB Control Register 1 (ACBCTL1)

Location: Offset 03h Type: R/W B i t 76543210 Name STASTRE NMINTE GCMEN ACK Reserved INTEN STOP START Reset 00000000 Bit Description

7 STASTRE (Stall After Start Enable)

0: When cleared, ACBST.STASTR can not be set. However, if ACBST.STASTR is set, clearing STASTRE will not clear ACBST.STASTR. 1: Stall after start mechanism enabled, and ACB stalls the bus after the address byte

6 NMINTE (New Match Interrupt Enable)

0: No interrupt issued on a new match 1: Interrupt issued on a new match only if ACBCTL1.INTEN set

5 GCMEN (Global Call Match Enable)

0: ACB not responding to global call 1: Global call match enabled 4 Receive Acknowledge. This bit is ignored in transmit mode. When the device acts as a receiver (slave or master), this bit holds the stop transmitting instruction that is transmitted during the next acknowledge cycle. 0: Cleared after acknowledge cycle 1: Negative acknowledge issued on next received byte

2 Interrupt Enable

0: ACB interrupt disabled 1: ACB interrupt enabled. An interrupt is generated in response to one of the following events: — Detection of an address match (ACBST.NMATCH=1) and NMINTE=1 — Receipt of Bus Error (ACBST.BER=1) — Receipt of Negative Acknowledge after sending a byte (ACBST.NEGACK=1) — Acknowledge of each transaction (same as the hardware set of the ACBST.SDAST bit) — In master mode if ACBCTL1.STASTRE=1, after a successful start (ACBST.STASTR=1) — Detection of a Stop Condition while in slave mode (ACBST.SLVSTP=1).

1 Stop

0: Automatically cleared after STOP issued 1: Setting this bit in master mode generates a Stop Condition to complete or abort current message transfer 0 Start. Set this bit only when in master mode or when requesting master mode. 0: Cleared after Start Condition sent or Bus Error (ACBST.BER=1) detected 1: Single or repeated Start Condition generated on the ACCESS.bus. If the device is not the active master of the bus (ACBST.MASTER=0), setting START generates a Start Condition when the ACCESS.bus becomes free (ACBCST.BB=0). An address transmission sequence should then be performed. If the device is the active master of the bus (ACBST.MASTER=1), setting START and then writing to the ACBSDA register generates a Start Condition. If a transmission is already in progress, a repeated Start Condition is generated. This condition can be used to switch the direction of the data flow between the master and the slave, or to choose another slave device without separating them with a Stop Condition.

8.0 ACCESS.bus Interface (ACB)(Continued) 146www.national.com

8.3.6 ACB Own Address Register (ACBADDR)

This is a byte-wide register that holds the ACB ACCESS.bus address. The reset value of this register is undefined. Location: Offset 04h Type: R/W

8.3.7 ACB Control Register 2 (ACBCTL2)

This register enables/disables the functional block and determines the ACB clock rate. Location: Offset 05h Type: R/W B i t 76543210 Name SAEN ADDR Reset Bit Description

7 SAEN (Slave Address Enable)

0: ACB does not check for an address match with ADDR field 1: ADDR field holds a valid address and enables the match of ADDR to an incoming address byte 6-0 ADDR (Own Address). These bits hold the 7-bit device address. When in slave mode, the first 7 bits received after a Start Condition are compared with this field (first bit received is compared with bit 6, and the last bit with bit 0). If the address field matches the received data and SAEN (bit 7) is 1, a match is declared. B i t 76543210 Name SCLFRQ ENABLE Reset 0 0000000 Bit Description 7-1 SCLFRQ (SCL Frequency ). This field defines the SCL period (low and high time) when the device serves as a bus master. The clock low and high times are defined as follows: t SCLl =tSCLh = 2*SCLFRQ*tCLK where tCLK is the module input clock cycle, as defined in theDevice Architecture and Configurationchapter. SCLFRQ can be programmed to values in the range of 00010002 (810) through 11111112 (12710). Using any other value has unpredictable results.

0 Enable

0: ACB disabled, ACBCTL1, ACBST and ACBCST cleared, and clocks halted 1: ACB enabled

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8.4 ACB REGISTER BITMAP

00h ACBSDA ACB Serial Data 01h ACBST SLVSTP SDAST BER NEGACK STASTR NMATCH MASTER XMIT 02h ACBCST Reserved TGSCL TSDA GCMTCH MATCH BB BUSY 03h ACBCTL1 STASTRE NMINTE GCMEN ACK Reserved INTEN STOP START 04h ACBADDR SAEN ADDR 05h ACBCTL2 SCLFRQ ENABLE

8.0 ACCESS.bus Interface (ACB)(Continued) 148www.national.com

149 www.national.com This chapter briefly describes the following blocks that provide legacy device functions:

• Keyboard and Mouse Controller (KBC)
• Floppy Disk Controller (FDC)
• Parallel Port
• Serial Port 1 (SP1), UART Functionality for both Serial Port 1 and Serial Port 2
• Serial Port 2 (SP2), Infrared Functionality The description of each Legacy block includes the sections listed below. For more information about legacy blocks, contact your National representative.
• General Description
• Register Map table(s)
• Bitmap table(s). The register maps in this chapter use the following abbreviations for Type:
• R/W = Read/Write
• R = Read from a specific address returns the value of a specific register. Write to the same address is to a different register.
• W=W r i t e
• RO = Read Only
• R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.

9.1 KEYBOARD AND MOUSE CONTROLLER (KBC)

9.1.1 General Description

The KBC is implemented physically as a single hardware module and houses two separate logical devices: a Mouse con- troller and a Keyboard controller. The KBC is functionally equivalent to the industry standard 8042A Keyboard controller, which may serve as a detailed tech- nical reference for the KBC.

9.1.2 KBC Register Map

9.1.3 KBC Bitmap Summary

Offset Mnemonic Register Name Type 00h DBBOUT Read KBC Data R DBBIN Write KBC Data W 04h STATUS Read Status R DBBIN Write KBC Command W Register Bits Offset Mnemonic 76543210 00h DBBOUT KBC Data Bits (For Read cycles) DBBIN KBC Data Bits (For Write cycles) 04h STATUS General Purpose Flags F1 F0 IBF OBF DBBIN KBC Command Bits (For Write cycles)

9.0 Legacy Functional Blocks(Continued)

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9.2 FLOPPY DISK CONTROLLER (FDC)

9.2.1 General Description

The generic FDC is a standard FDC with a digital data separator, and is DP8473 and N82077 software compatible. The FDC is implemented in this device as follows:

• FM and MFM modes are supported. To select either mode, set bit 6 of the first command byte when writing to/read- ing from a diskette, where: 0 = FM mode 1 = MFM mode
• Automatic media sense is not supported (MSEN0-1 pins are not implemented).
• DRATE1 is not supported.
• A logic 1 is returned for all floating (TRI-STATE) FDC register bits upon LPC I/O read cycles.

9.2.2 FDC Register Map

Offset Mnemonic Register Name Type 00h SRA Status A RO 01h SRB Status B RO 02h DOR Digital Output R/W 03h TDR Tape Drive R/W 04h MSR Main Status R DSR Data Rate Select W 05h FIFO Data (FIFO) R/W 06h Reserved 07h DIR Digital Input R CCR Configuration Control W

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9.2.3 FDC Bitmap Summary

The FDC supports two system operation modes: PC-AT mode and PS/2 mode (MicroChannel systems). Unless specifically indicated otherwise, all fields in all registers are valid in both drive modes. Register Bits Offset Mnemonic 76543210 00h SRA Note 1. Note 1. Applicable only in PS/2 Mode IRQ Pending Reserved Step TRK0 Head Se- lect INDEX WP Head Direction 01h SRB Note 1. Reserved Drive Select 0 Status WD ATA RD ATA WGA TE MTR1 MTR0 02h DOR Motor Enable 3 Motor Enable 2 Motor Enable 1 Motor Enable 0 DMAEN Reset Controller Drive Select 03h TDR Reserved Tape Drive Select 1,0 TDR Note 2. Note 2. Applicable only in Enhanced TDR Mode Reserved Drive ID Information Logical Drive Exchange Tape Drive Select 1,0 04h MSR RQM Data I/O Direction Non-DMA Execution Command in Progress Drive 3 Busy Drive 2 Busy Drive 1 Busy Drive 0 Busy DSR Software Reset Low Power Reserved Precompensation Delay Select Data Transfer Rate Select 05h FIFO Data Bits 07h DIRNote 3. Note 3. Applicable only in PC-AT Compatible Mode DSKCHG Reserved DIRNote 1. DSKCHG Reserved DRATE 1,0 Status High Density 07h CCR Reserved DRATE1,0

9.3 PARALLEL PORT

9.3.1 General Description

Bidirectional (known also as PS/2), FIFO, EPP (known also as Mode 4) and ECP (with an optional Extended ECP mode).

9.3.2 Parallel Port Register Map

level offset registers are available only when base address is 8-byte aligned. Table 47. Parallel Port Register Map for First Level Offset

765 Type

001 R/W

Table 48. Parallel Port Register Map for Second Level Offset

9.3.3 Parallel Port Bitmap Summary

The Parallel Port functional block bitmaps are grouped according to first and second level offsets. Table 49. Parallel Port Bitmap Summary for First Level Offset

Table 50. Parallel Port Bitmap Summary for Second Level Offset

9.4 UART FUNCTIONALITY (SP1 AND SP2)

9.4.1 General Description

9.4.2 UART Mode Register Bank Overview

Figure 27. UART Mode Register Bank Architecture

16550 Banks

9.4.3 SP1 and SP2 Register Maps for UART Functionality

Table 51. Bank 0 Register Map Table 52. Bank Selection Encoding Table 53. Bank 1 Register Map

Table 54. Bank 2 Register Map Table 55. Bank 3 Register Map

9.4.4 SP1 and SP2 Bitmap Summary for UART Functionality

Table 56. Bank 0 Bitmap Note 5. When bit 7 of this register is set to 1, bits 6-0 of BSR select the bank, as shown in Table 52.

Table 57. Bank 1 Bitmap Table 58. Bank 2 Bitmap Table 59. Bank 3 Bitmap

9.5 IR FUNCTIONALITY (SP2)

9.5.1 General Description

are described in Section 9.4. The IR functional block provides advanced, versatile serial communications features with IR capabilities. handle high-speed full duplex UART based applications.

9.5.2 IR Mode Register Bank Overview

to all banks. See Figure 28. Figure 28. SP2 Register Bank Architecture

9.5.3 SP2 Register Map for IR Functionality

Table 60. Bank 4 Register Map Table 61. Bank 5 Register Map Table 62. Bank 6 Register Map Table 63. Bank 7 Register Map

9.5.4 SP2 Bitmap Summary for IR Functionality

Table 64. Bank 4 Bitmap Table 65. Bank 5 Bitmap Table 66. Bank 6 Bitmap

Table 67. Bank 7 Bitmap

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10.0 Device Characteristics

10.1 GENERAL DC ELECTRICAL CHARACTERISTICS

10.1.1 Recommended Operating Conditions

10.1.2 Absolute Maximum Ratings

Absolute maximum ratings are values beyond which damage to the device may occur. Unless otherwise specified, all volt- ages are relative to ground.

10.1.3 Capacitance

TA = 25°C, f = 1 MHz Symbol Parameter Min Typ Max Unit VDD Supply Voltage 3.0 3.3 3.6 V VSB Standby Voltage 3.0 3.3 3.6 V VBAT Battery Backup Supply Voltage 2.4 3.0 3.6 V TA Operating Temperature 0 +70 °C Symbol Parameter Conditions Min Max Unit VDD Supply Voltage −0.5 +6.5 V VI Input Voltage −0.5 V DD + 0.5 V VO Output Voltage −0.5 V DD + 0.5 V TSTG Storage Temperature −65 +165 °C PD Power Dissipation 1W TL Lead Temperature Soldering (10 s) +260 °C ESD Tolerance C ZAP = 100 pF R ZAP = 1.5 KΩ Note 1. Note 1. Value based on test complying with RAI-5-048-RA human body model ESD testing. 2000 V Symbol Parameter Min Typ Max Unit C IN Input Pin Capacitance 57 p F C IN1 Clock Input Capacitance 5 8 12 pF C IO I/O Pin Capacitance 10 12 pF C O Output Pin Capacitance 68 p F

10.0 Device Characteristics(Continued)

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10.1.4 Power Consumption under Recommended Operating Conditions

10.2 DC CHARACTERISTICS OF PINS, BY I/O BUFFER TYPES

The following tables summarize the DC characteristics of all device pins described in theSignal/Pin Connection and De- scriptionchapter. The characteristics describe the general I/O buffer types defined in Table 1. For exceptions, refer to Sec-

10.2.1 Input, CMOS Compatible

Symbol: INC 10.2.2 Input, PCI 3.3V Symbol: INPCI Symbol Parameter Conditions Typ Max Unit ICC VDD Average Main Supply CurrentVIL = 0.5 V, VIH = 2.4 V No Load 32 50 mA ICCLP VDD Quiescent Main Supply Current in Low Power Mode VIL =V SS ,V IH =V DD No Load 1.3 1.7 mA ISB VSB Average Main Supply CurrentVIL = 0.5 V, VIH = 2.4 V No Load 15 mA ISBLP VSB Quiescent Main Supply Current in Low Power Mode VIL =V SS ,V IH =V SB V No Load 3m A IBAT VBAT Battery Supply Current VDD ,V SB =0V , VBAT =3V 250 nA Symbol Parameter Conditions Min Max Unit VIH Input High Voltage 0.7 VDD 5.5Note 1. Note 1. Not tested. Guaranteed by design. V VIL Input Low Voltage −0.5 Note 1.

0.3 VDD V

VIN =V DD 50 nA VIN =V SS −50 nA Symbol Parameter Conditions Min Max Unit VIH Input High Voltage 0.5VDD VDD + 0.5 V VIL Input Low Voltage -0.5 0.3V DD V lIL Note 1. Note 1. Input leakage currents include hi-Z output leakage for all bidirectional buffers with TRI-STATE outputs. Input Leakage Current 0<V in<V DD ±10 µA

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10.2.3 Input, SMBus Compatible

Symbol: INSM

10.2.4 Input, Strap Pin

Symbol: INSTRP

10.2.5 Input, TTL Compatible

Symbol: INT

10.2.6 Input, TTL Compatible with Schmitt Trigger

Symbol: INTS Symbol Parameter Conditions Min Max Unit VIH Input High Voltage 1.4 5.5Note 1. Note 1. Not tested. Guaranteed by design. V VIL Input Low Voltage −0.5 Note 1. 0.8 V IIL Input Leakage Current VIN =V DD 10 µA VIN =V SS −10 µA Symbol Parameter Conditions Min Max Unit VIH Input High Voltage 0.6VDD Note 1. 5.5Note 1. Note 1. Not tested. Guaranteed by design. V IIL Input Leakage Current During Reset: VIN =V DD 150 µA VIN =V SS −10 µA Symbol Parameter Conditions Min Max Unit VIH Input High Voltage 2.0 5.5Note 1. Note 1. Not tested. Guaranteed by design. V VIL Input Low Voltage −0.5Note 1. 0.8 V IIL Input Leakage Current VIN =V DD 10 µA VIN =V SS −10 µA Symbol Parameter Conditions Min Max Unit VIH Input High Voltage 2.0 5.5Note 1. Note 1. Not tested. Guaranteed by design. V VIL Input Low Voltage −0.5 Note 1. 0.8 V IIL Input Leakage Current VIN =V DD 10 µA VIN =V SS −10 µA VH Input Hysteresis 250 mV

167 www.national.com 10.2.7 Output, PCI 3.3V Symbol: O PCI

10.2.8 Output, Totem-Pole Buffer

Symbol: O p/n Output, Totem-Pole buffer that is capable of sourcingp mA and sinkingn mA

10.2.9 Output, Open-Drain Buffer

Symbol: OD n Output, Open-Drain output buffer, capable of sinkingn mA. Output from these signals is open-drain and cannot be forced high.

10.2.10 Exceptions

1. All pins are back-drive protected, except for the output pins with PCI Buffer Type. 2. The following pins have a static pull-up resistor and therefore may have input leakage current (when VIN =V SS ) of about (-)160µA:ACK, AFD_ DSTRB, ERR, GPIO40-37, GPIO30-34,GPIO36-37, GPIO20-27, GPIO10-17, , GPIO00-07,INIT, P12, P16, P17, PE,SLIN_ASTRB, STB_ WRITE 3. The following pins have a static pull-down resistor and therefore may have input leakage current (when VIN =V DD )o f about 130µA: BUSY_W AIT, PE, SLCT 4. Output from SLCT, BUSY_WAIT (and PE if bit 2 of PP Confg0 Register is “0”) is open-drain in all SPP modes, except in SPP Compatible mode when the setup mode is ECP-based FIFO and bit 4 of the Control2 parallel port register is 1. Otherwise, output from these signals is level 2. External 4.7 KW pull-up resistors should be used. 5. Output from ACK, ERR (and PE if bit 2 of PP Confg0 Register is set to 1) is open-drain in all SPP modes, except in SPP Compatible mode when the setup mode is ECP-based FIFO and bit 4 of the Control2 parallel port register is set to 1. Otherwise, output from these signals is level 2. External 4.7 KW pull-up resistors should be used. 6. Output from STB, AFD, INIT,SLIN is open-drain in all SPP modes, except in SPP Compatible mode when the setup mode is ECP-based (FIFO). Otherwise, output from these signals is level 2. External 4.7 KΩ pull-up resistors should be used. 7. Output from PD7-0 is open-drain in all SPP modes, except in SPP Compatible mode when the setup mode is ECP-based (FIFO) and bit 4 of the Control2 parallel port register is 1. Otherwise, output from these signals is Level 2. External 4.7 KΩ pull-up resistors should be used. 8. I OH is valid for a GPIO pin only when it is not configured as open-drain. 9. P12, P16 and P17 are driven high for about 100 ns after a low-to-high transition, during which it is capable of sourcing 2 mA. Symbol Parameter Conditions Min Max Unit VOH Output High Voltage lout = -500µA 0.9V DD V VOL Output Low Voltage lout =1500 µA 0.1 V DD V Symbol Parameter Conditions Min Max Unit VOH Output High Voltage IOH = −p mA 2.4 V VOL Output Low Voltage IOL = n mA 0.4 V Symbol Parameter Conditions Min Max Unit VOL Output Low Voltage IOL = n mA 0.4 V

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10.3 INTERNAL RESISTORS

10.3.1 Pull-Up Resistor

Symbol: PU nn.

10.3.2 Pull-Down Resistor

Symbol: PD nn. Symbol Parameter Conditions Typical Min Max Unit R PU Pull-up equivalent resistance VDD = 3.3V nn nn -30% nn+30% K Ω Symbol Parameter Conditions Typical Min Max Unit R PD Pull-down equivalent resistance VDD = 3.3V nn nn -30% nn+30% K Ω

10.4 AC ELECTRICAL CHARACTERISTICS

10.4.1 AC Test Conditions

Figure 29. AC Test Conditions, TA =0 °Ct o7 0°C, VDD = 5.0 V±10%

1. CL = 100 pF for all output except OPCI, and CL= 50pF for outputs of type OPCI, this includes jig and scope capacitance.
2. S1 = Open for push-pull output pins.

S1 = VDD for high impedance to active low and active low to high impedance measurements. S1 = GND for high impedance to active high and active high to high impedance measurements. R L = 1.0KΩ forµP interface pins.

1. For the FDC open-drive interface pins, S1 = VDD and RL = 150Ω .

10.4.2 Clock Timing

48 MHz

tCH Clock High Pulse WidthNote 1. Note 1. Not tested. Guaranteed by design.

0.8 Test Points

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10.4.3 LCLK and LRESET

Symbol Parameter Min Max Units tCYC Note 1. Note 1. The PCI may have any clock frequency between nominal DC and 33 MHz. Device operational parameters at frequencies under 16 MHz may be guaranteed by design rather than by testing. The clock frequency may be changed at any time during the operation of the system as long as the clock edges remain “clean” (monotonic) and the minimum cycle and high and low times are not violated. The clock may only be stopped in a low state. LCLK Cycle Time 30 ns t HIGH LCLK High Time 11 ns tLOW LCLK Low Time 11 ns - LCLK Slew RateNote 2. Note 2. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum peak-to- peak portion of the clock wavering as shown below. 1 4 V/ns LRESET Slew RateNote 3. Note 3. The minimumLRESET slew rate applies only to the rising (de- assertion) edge of the reset signal, and ensures that system noise cannot render an otherwise a monotonic signal to appear to bounce in the switching range. 50 mV/ns

0.6 VDD

0.2 VDD

0.5 VDD

0.4 VDD

0.3 VDD

0.4 VDD p-to-p

(minimum) tHIGH tLOW

3.3 V Clock

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10.4.4 LPC and SERIRQ Signals

Symbol Figure Description Reference Conditions Min Max Unit tVAL Output Output Valid Delay After RE CLK 11 ns tON Output Float to Active Delay After RE CLK 2 ns tOFF Output Active to Float Delay After RE CLK 28 ns tSU Input Input Setup Time Before RE CLK 7 ns tHI Input Input Hold Time After RE CLK 0 ns LCLK LPC Signals/ SERIRQ tON Output tVAL tOFF LCLK LPC Signals/ SERIRQ tSU tHI Input Valid Input

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10.4.5 Serial Port, Sharp-IR, SIR and Consumer Remote Control Timing

Symbol Parameter Conditions Min Max Unit tBT Single Bit Time in Serial Port and Sharp-IR Transmitter tBTN − 25 Note 1. Note 1. tBTN is the nominal bit time in Serial Port, Sharp-IR, SIR and Consumer Remote Control modes. It is determined by the setting of the Baud Generator Divisor registers tBTN +2 5 ns Receiver tBTN − 2% t BTN +2 % ns tCMW Modulation Signal Pulse Width in Sharp-IR and Consumer Remote Control Transmitter tCWN − 25 Note 2. Note 2. tCWN is the nominal pulse width of the modulation signal for Sharp-IR and Consumer Remote Control modes. It is determined by the MCPW field (bits 7-5) of the IRTXMC registerand the TXHSC bit (bit 2) of the RCCFG register t CWN +2 5 ns Receiver 500 ns tCMP Modulation Signal Period in Sharp-IR and Consumer Remote Control Transmitter tCPN − 25 Note 3. Note 3. tCPN is the nominal period of the modulation signal for Sharp-IR and Consumer Remote Control modes. It is determined by the MCFR field (bits 4-0) of the IRTXMC registerand the TXHSC bit (bit 2) of the RCCFG register. t CPN +2 5 ns Receiver tMMIN Note 4. Note 4. tMMIN and tMMAX define the time range within which the period of the incoming subcarrier signal has to fall in order for the signal to be accepted by the receiver. These time values are determined by the contents of the IRRXDC register and the setting of the RXHSC bit (bit 5) of the RCCFG register t MMAX Note 4. ns tSPW SIR Signal Pulse Width Transmitter, Variable (3/16)xt BTN − 15 Note 1. (3/16)xt BTN + 15 Note 1. ns Transmitter, Fixed 1.48 1.78 µs Receiver 1 µs SDRT SIR Data Rate Tolerance. % of Nominal Data Rate. Transmitter ± 0.87% Receiver ± 2.0% tSJT SIR Leading Edge Jitter. % of Nominal Bit Duration. Transmitter ± 2.5% Receiver ± 6.5% Serial Port tCMW tCMP Sharp-IR Consumer Remote Control tBT SIR tSPW

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10.4.6 Modem Control Timing

10.4.7 FDC Write Data Timing

Symbol Parameter Min Max Unit tHL RI2,1 High to Low Transition 10 ns tLH RI2,1 Low to High Transition 10 ns tSIM Delay to Set IRQ from Modem Input 40 ns Symbol Parameter Min Max Unit tHDH HDSEL Hold fromWGA TE InactiveNote 1. Note 1. Not tested. Guaranteed by design. 100 µs tHDS HDSEL Setup toWGA TE ActiveNote 1. 100 µs tWDW Write Data Pulse Width See tDRP ,tICP and tWDW values in table below Data Rate tDRP tICP tICP Nominal t WDW tWDW Minimum Unit

1 Mbps 1000 6xt CP

Note 1. Note 1. tCP is the clock period defined in theLCLK and LRESET section of this chapter. 125 2 x t ICP 250 ns

500 Kbps 2000 6xt CP

Note 1. 125 2 x t ICP 250 ns

300 Kbps 3333 1 0xtCP

Note 1. 208 2 x t ICP 375 ns

250 Kbps 4000 1 2xtCP

Note 1. 250 2 x t ICP 500 ns CTS, DSR, DCD INTERRUPT (Read MSR) RI tSIM tSIM tSIM tHL tLH (Read MSR) tHDS tHDH tWDW HDSEL WGATE WDATA

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10.4.8 FDC Drive Control Timing

10.4.9 FDC Read Data Timing

Symbol Parameter Min Max Unit tDST DIR Setup toSTEP ActiveNote 1. Note 1. Not tested. Guaranteed by design. 6 µs tIW Index Pulse Width 100 ns tSTD DIR Hold fromSTEP Inactive tSTR ms tSTP STEP Active High Pulse WidthNote 1. 8 µs tSTR STEP Rate TimeNote 1. 0.5 ms Symbol Parameter Min Max Unit tRDW Read Data Pulse Width 50 ns tIW tSTP tDST tSTR tSTD DIR STEP INDEX tRDW RDATA

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10.4.10 Standard Parallel Port Timing

10.4.11 Enhanced Parallel Port Timing

Symbol Parameter Conditions Typ Max Unit tPDH Port Data Hold These times are system dependent and are therefore not tested. 500 ns tPDS Port Data Setup These times are system dependent and are therefore not tested. 500 ns tSW Strobe Width These times are system dependent and are therefore not tested. 500 ns Symbol Parameter Min Max EPP 1.7 EPP 1.9 Unit tWW19a WRITE Active fromW AIT Low 45 ✔ ns tWW19ia WRITE Inactive fromW AIT Low 45 ✔ ns tWST19a DSTRB or ASTRB Active fromW AIT Low 65 ✔ ns tWEST DSTRB or ASTRB Active afterWRITE Active 10 ✔✔ ns tWPDH PD7-0 Hold afterWRITE Inactive 0 ✔✔ ns tWPDS PD7-0 Valid afterWRITE Active 15 ✔✔ ns tEPDW PD7-0 Valid Width 80 ✔✔ ns tEPDH PD7-0 Hold afterDSTRB or ASTRB Inactive 0 ✔✔ ns tPDS tPDH tSW BUSY ACK PD7-0 STB WRITE DSTRB ASTRB PD7-0 WAIT Valid tWW19ia tWPDH tEPDH tEPDW or tWW19a tWST19a tWPDS tWEST tWST19a

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10.4.12 Extended Capabilities Port (ECP) Timing

Symbol Parameter Min Max Unit tECDSF Data Setup beforeSTB Active 0n s tECDHF Data Hold after BUSY Inactive 0n s tECLHF BUSY Active afterSTB Active 75 ns tECHHF STB Inactive after BUSY Active 01 s tECHLF BUSY Inactive afterSTB Active 03 5 m s tECLLF STB Active after BUSY Inactive 0n s Symbol Parameter Min Max Unit tECDSR Data Setup beforeACK Active 0n s tECDHR Data Hold afterAFD Active 0n s tECLHR AFD Inactive afterACK Active 75 ns tECHHR ACK Inactive afterAFD Inactive 03 5 m s tECHLR AFD Active afterACK Inactive 01 s tECLLR ACK Active afterAFD Active 0n s PD7-0 STB BUSY tECHHF tECHLF tECLLF tECDSF tECLHF tECDHF AFD PD7-0 ACK AFD tECHHB tECHLB tECLLB tECDSB tECLHB tECDHB BUSY

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10.4.13 Chassis Lock/Unlock Timing

Symbol Parameter Min Max Unit tCLPW Chassis Lock Pulse WidthNote 1. Note 1. Not tested. Guaranteed by design. 0.75 sec tCULPW Chassis Unlock Pulse WidthNote 1. 0.75 sec tCLRCV Chassis Lock RecoveryNote 1. 0.25 sec tCULRCV Chassis Unlock RecoveryNote 1. 0.25 sec tCLRCV, tCULRCVtCLPW, tCULPW CHLOCK CHUNLOCK

PC87364 128-Pin LPC SuperI/O with Extended Wake-Up and Protection Support Physical Dimensions All dimensions are in millimeters. Plastic Quad Flatpack (PQFP), JEDEC Order Number PC87364-xxx/VLA LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Corporation Fax: 1-800-737-7018 Email: support@nsc.com Tel: 1-800-272-9959 National Semiconductor Europe Fax: (+49) 0-180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: (+49) 0-180-530 85 85 English Tel: (+49) 0-180-532 78 32 National Semiconductor Asia Pacific Customer Response Group Fax: 65-250-4466 Email: sea.support@nsc.com Tel: 65-254-4466 National Semiconductor Japan Ltd. Fax: 81-3-5620-6179 Tel: 81-3-5620-6175 www.national.com National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.