PC8374L

PC8374L NSC | Alldatasheet

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PC8374L SensorPathTM SuperI/O with Glue Functions www.national.com Preliminary May 2004 Revision 1.1 PC8374L SensorPathTM SuperI/O with Glue Functions General Description The National Semiconductor PC8374L Advanced I/O prod- uct is a member of the PC837x SuperI/O family. All PC837x devices are highly integrated and are pin and software com- patible, thus providing drop-in interchangeability and enabling a variety of assembly options using only a single motherboard and BIOS. PC8374L integration allows for a smaller system board size and saves on total system cost. The PC8374L includes legacy SuperI/O functions, system glue functions, health monitoring and control, commonly used functions such as GPIO, and ACPI-compliant Power Management support. The PC8374L integrates miscellaneous analog and digital system glue functions to reduce the number of discrete components required. The host communicates with the functions integrated in the PC8374L device through an LPC Bus Interface. The PC8374L extended wake-up support complements the ACPI controller in the chipset. The System Wake-Up Control (SWC) module, powered by VSB3, supports a flexible wake- up mechanism. The PC8374L supports both I/O and memory mapping of module registers and enables building legacy-free systems. Outstanding Features ■SensorPath interface to LMxx sensor devices for system health support ■Fan monitor and control ■Heceta6-compatible register set, accessible via the LPC interface and SMBus ■Glue functions to complement the South Bridge func- tionality ■VSB3-powered Power Management with 19 wake-up sources ■Controls three LED indicators ■16 GPIO ports with a variety of wake-up options ■I/O-mapped and memory-mapped registers ■Legacy modules: Parallel Port, Floppy Disk Controller (FDC), two Serial Ports, Slow InfraRed Port and a Key- board and Mouse Controller (KBC) ■LPC interface, based on Intel’s LPC Interface Specifica- tion Revision 1.1, August 2002 ■PC01 Revision 1.0 and Advanced Configuration and Power Interface (ACPI) Specification Revision 2.0 compliant ■128-pin PQFP package Block Diagram LMxx Sensors SensorPathTM I/F Drv Drv LPC Bus South Bridge Serial Interfaces Parallel Port Interfaces Floppy Drive Interface PS/2 Interfaces KBC Ports Infrared Interface GPIO Ports PC8374L Drv Tacho PWM LEDs Power Supply Reset Logic Power Management VBAT SMBus I/F System BIOS National Semiconductor and TRI-STATE are registered trademarks of National Semiconductor Corporation. SensorPath is a trademark of National Semiconductor Corporation. All other brand or product names are trademarks or registered trademarks of their respective holders. © 2004 National Semiconductor Corporation Winbond Electronics Corp. Advanced PC Product Center

www.national.com Revision 1.1 PC8374L

Features

■SensorPath interface to sensors optimizes digital/analog partitioning — Simplifies board design and routing — Supports distributed sensors and centralized control — Health monitoring is self-contained and requires minimal host attention — Faster boot time — Off loads SMBus, and enables ASF compliance ■Fan Monitor and Control — Three PWM-based fan controls — Four 16-bit resolution tachometer inputs — Software or local temperature feedback control Heceta6-compatible register set accessible via the LPC interface and SMBus — Supports the following combinations of LMxx devices: LM96011 and optional LM95010 LM96012 LM96010 — SimultaneousreadsupportviaLPCinterfaceandSMBus Glue Functions ■Generates the power-related signals: — Main Power good — Power distribution control (for switching between Main and Standby regulators) — Resume reset (Master Reset) according to the 5V standby supply status — Main power supply turn on (PS_ON) ■Voltage translation between 2.5V or 3.3V levels (DDC) and 5V levels (VGA) for the SMBus serial clock and data signals ■Isolation circuitry for the SMBus serial clock and data signals ■Buffers PCI_RESET to generate two reset output signals ■Buffers PCI_RESET to generate IDE reset output. ■Generates “highest active supply” reference voltage — Based on 3.3V and 5V Main supplies — Based on 3.3V and 5V Standby supplies ■High-current LED driver control for Hard Disk Drive activity indication ■Software selectable alternative functionality, through pin multiplexing General-Purpose I/O (GPIO) Ports ■All 16 GPIO ports powered by VSB3 ■Each pin individually configured as input or output ■Programmable features for each output pin: — Drive type (open-drain, push-pull or TRI-STATE) — TRI-STATE on detection of falling VDD3 for VSB3-powered pins driving VDD-supplied devices ■Programmable option for internal pull-up resistor on each input pin (some with internal pull-down resistor option) ■Lock option for the configuration and data of each output pin ■15 GPIO ports generate IRQ/SIOPME for wake-up events; each GPIO has separate: — Enable control of event status routing to IRQ — EnablecontrolofeventstatusroutingtoSIOPME(viaSWC) — Polarity and edge/level selection Programmable debouncing Power Management ■Supports ACPI Specification Revision 2.0b, July 27, 2000 ■System Wake-Up Control (SWC) — Optional routing of events to generate SCI (SIOPME) on detection of: Keyboard or Mouse events Ring Indication RI on each of the two serial ports General-Purpose Input Events from 15 GPIO pins IRQs of the Keyboard and Mouse Controller IRQs of the other internal modules — Optional routing of the SCI (SIOPME) to generate IRQ (SERIRQ) — Implements the GPE1_BLK of the ACPI General Pur- pose (Generic) Register blocks with “child” events — VSB3-powered event detection and event-logic configuration ■Enhanced Power Management (PM), including: — Special configuration registers for power down — Low-leakage pins — Low-power CMOS technology — Ability to disable all modules — High-current LED drivers control (two LEDs) for power status indication with: Standard blinking, controlled by software Advanced blinking, controlled by power supply status, sleep state or software Special blinking, controlled by power supply sta- tus, sleep state and software bit — VBAT-powered indication of the Main power supply state before an AC power failure ■Keyboard Events — Wake-up on any key — Supports programmable 8-byte sequence “Pass- word” or “Special Keys” for Power Management — Simultaneous recognition of three programmable keys (sequences): “Power”, “Sleep” and “Resume” — Wake-up on mouse movement and/or button click Bus Interface ■LPC Bus Interface — Based on Intel’s LPC Interface Specification Revi- sion 1.1, August 2002 — I/O, Memory and 8-bit Firmware Memory read and write cycles — Up to four 8-bit DMA channels — Serial IRQ (SERIRQ) — Supports registers memory and I/O mapping Winbond Electronics Corp. Advanced PC Product Center

Features (Continued) www.national.com Revision 1.1 PC8374L ■Configuration Control — PnP Configuration Register structure — PC01 Specification Revision 1.0, 1999-2000 compliant — Base Address strap (BADDR) to setup the address of the Index-Data register pair (defaults to 2Eh/2Fh) — Flexible resource allocation for all logical devices: Relocatable base address

15 IRQ routing options to serial IRQ

Up to four optional 8-bit DMA channels — Configurable feature sets: Software selectable VSB3-powered pin multiplexing Legacy Modules ■Serial Ports 1 and 2 — Software-compatible with the NS16550A and NS16450 — Support shadow register for write-only bit monitoring — Data rates up to 1.5 Mbaud ■Serial Infrared Port (SIR) — Software compatible with the 16550A and the 16450 — Shadow register support for write-only bit monitoring — HP-SIR — ASK-IR option of SHARP-IR — DASK-IR option of SHARP-IR — Consumer Remote Control supports RC-5, RC-6, NEC, RCA and RECS 80 ■IEEE 1284-compliant Parallel Port — ECP, with Level 2 (14 mA sink and source output buffers) — Software or hardware control — Enhanced Parallel Port (EPP) compatible with EPP 1.7 and EPP 1.9 — Supports EPP as mode 4 of the Extended Control Register (ECR) — Selection of internal pull-up or pull-down resistor for Paper End (PE) pin — Supports a demand DMA mode mechanism and a DMA fairness mechanism for improved bus utilization — Protection circuit that prevents damage to the parallel port when a printer connected to it is pow- ered up or is operated at high voltages (in both cases, even if the PC8374L is in power-down state) ■Floppy Disk Controller (FDC) — Software compatible with the PC8477 (the PC8477 contains a superset of the FDC functions in the µDP8473, NEC µPD765A/B and N82077 devices) — Error-free handling of data overrun and underrun — Programmable write protect — Supports FM and MFM modes — Supports Enhanced mode command for three-mode Floppy Disk Drive (FDD) — Perpendicular recording drive support for 2.88 MBytes — Burst (16-byte FIFO) and Non-Burst modes — Full support for IBM Tape Drive Register (TDR) im- plementation of AT and PS/2 drive types — High-performance digital separator — Supports fast tape drives (2 Mbps) and standard tape drives (1 Mbps, 500 Kbps and 250 Kbps) ■Keyboard and Mouse Controller (KBC) — 8-bit microcontroller, software compatible with 8042AH and PC87911 — Standard interface (60h, 64h, IRQ1 and IRQ12) — Supports two external swapable PS/2 interfaces for keyboard and mouse — Programmable, dedicated quasi-bidirectional I/O lines (GA20/P21, KBRST/P20) Clocking, Supply, and Package Information ■Clocks — LPC (PCI) clock input (up to 33 MHz) — On-chip Clock Generator: Generates 48 MHz clock Generates 32.768 KHz internal clock VSB3 powered Based on the 14.31818 MHz clock input ■Protection — All pins are 5V tolerant and back-drive protected (except LPC bus pins) — High ESD protection of all the pins — Pin multiplexing selection lock — Configuration register lock ■Testability — XOR tree structure Includes all the pins (except supply, analog and not connected pins) Selected at power-up by strap input (TEST) — TRI-STATE pins, selected at power-up by strap input (TRIS) ■Power Supply — 3.3V supply operation — Separate pin pairs for main (VDD3) and standby (VSB3) power supplies — Backup battery input (VBAT) for SWC indications — Low standby power consumption — Very low power consumption from backup battery (less than 0.5 µA) ■Package — 128-pin PQFP Winbond Electronics Corp. Advanced PC Product Center

www.national.com Revision1.1 PC8374L Revision Record Revision Date Status Comments March 17, 2003 Draft Revision 0.03 First Draft of Arch. Spec. April 15, 2003 Draft Revision 0.1 Add Serial InfraRed Port Update all sections June 7, 2003 Draft Revision 0.3 Change Clock generator and CLOCKCF register Add Heceta6 Emulation module and complementing configuration registers: H6_SMBCF, SIOCFB, and its logical device (LDN=08h) configuration registers Define ETC (Enhanced Thermal Control) behavior Change DC spec of GPIOE10-13 Add INTS2 buffer type Correct LPCPD timing Correct LPC tVAL Rename the following functions: GPO24 to GPO41, GPIOE25 to GPIOE24, GPIOE26 to GPIOE25, GPIOE27 to GPIOE26 Change in GPCFG2 register Correct memory map support for SWC Typos and clarifications June 22, 2003 Draft Revision 0.5 Rename Port Angeles 3 to PC87374L Rename 3V_DDCSCL, 3V_DDCSDA to CC_DDCSCL, CC_DDCSDA Support 2.5V SMBus on CC_DDCSnn pins Update Clock Domains Section, changes in CLOCKCF register, High-Frequency Clock Timing, Low-Frequency Clock Timing SIOCFB register is changed to be powered by VBAT Register 61h for LDN=08h: H6_LPC_EMUL is changed Hecteta6 Emulation: changed Table 62, changed Tachometer Reading registers Changed FMC Registers: FT_CTL, FT_LOW, FT_HYST and FT_RNG Change SOUT2 buffer type to O4/8 Added XOR Tree delay Update AC spec: VSB Power-Up reset, VDD Power-Up reset, Main Power Good, Resume Reset, PS_ON Add Power Consumption numbers Add SMBus timing, InfraRed Port timing Typos and clarifications August 2, 2003 Draft Revision 0.6 Remove HMC and FMC modules Remove SCK_BJT_GATE, LPCPD, GPIOE15, GPIOE26-20, GPIO37-30, GPO41-40 signals Pins 52, 102, 123 are NC (Not Connected) Allow multiple pin locations for GPIO signals and rename pins with GPIOs, change default PU/PD, allow routing of a GPIOE input to a GPIO output Removed SIOCFB register SIOCF4[2:1], CLOCKCF[0] are reserved, change in SIOCF3[1:0], SIOCF4[5:3] Change drive capability of GPIOE00 (on pin 118) and GPIOE07 (on pin 128) Change PWRGD_3V functionality Rename PC87374L to PC8374L Rename Heceta 6 Emulation to Health Management H6_SCL and H6_SDA pins renamed to HMSCL and HMSDA pins, respectively VBAT pin should be connected to VSB3 (and not VSS), when battery backup features are unused LED mode selection is not dependent on VBAT existence Typos and clarifications Winbond Electronics Corp. Advanced PC Product Center

(Continued) Revision 1.1 www.national.com PC8374L August 12, 2003 Draft Revision 0.7 Change PWRGD_3V functionality Add details to SERIAL PORT 2 (SP2) WITH INFRARED Section Change in HMSMBCF register Typos and clarifications Health Management: Added support for more LMxx devices - see overview Section 9.2.2 - added a table of temp channel association. New HM registers: Status Register 3-4, Monitoring Control, Extended FANPWM Control 1-2, Tachometer Monitoring Control, Channels Vdd configuration, Temp Critical Limit Zone1- 3,Temp Zone1-3 Gain and Offset Correction. New HM LPC registers:HMINT_STS3, HMINT_EN#, HMSENS_STS3, HMS_EN1-3, SMI/SCI_ROUT. Functional description updated. Temp Reading registers updated. October 13, 2003 Draft Revision 0.8 Maximum PWM duty cycle, Fans setting time to the maximum duty cycle, Changed default mode of LED control Correct Table 3 on page 18 Rename LMxx sensor device Removed FPRST Changed reset value of FANTACH registers to FF Changed reset value of FANOFF to 1 Added Package Thermal Information Typos and clarifications November 20, 2003 Preliminary Revision 0.9

• Changes to the Health Management Chapter
• Device Characteristics: Minimum value of tCH, tCL reduced to 20 ns
• Typos and Clarifications February 3, 2004 Preliminary Revision 1.0
• Added LM sensor devices
• Changed VBAT external capacitor requirement to 1 µF
• Typos and Clarifications May 2004 Preliminary Revision 1.1
• Glue Functions: Removed 2.5V voltage divider circuit for SM- Bus Voltage Translation system diagram
• Typos and Clarifications Revision Date Status Comments Winbond Electronics Corp. Advanced PC Product Center

www.national.com Revision1.1 PC8374L Table of Contents Revision Record 1.0 Signal/Pin Connection and Description 1.1 1.2 1.3 1.4 1.4.1 1.4.2 1.4.3 1.4.4 1.4.5 1.4.6 1.4.7 1.4.8 1.4.9 1.4.10 1.4.11 1.4.12 1.4.13 1.5 2.0 Power, Reset and Clocks 2.1 2.1.1 2.1.2 2.1.3 2.2 2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.3 2.3.1 2.3.2 2.3.3 2.4 2.4.1 2.4.2 3.0 Device Architecture and Configuration 3.1 3.2 Winbond Electronics Corp. Advanced PC Product Center

Table of Contents (Continued) Revision 1.1 www.national.com PC8374L 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 3.3 3.3.1 3.3.2 3.4 3.5 3.5.1 3.5.2 3.5.3 3.5.4 3.5.5 3.5.6 3.5.7 3.6 3.7 3.7.1 3.7.2 3.7.3 3.7.4 3.7.5 3.7.6 3.7.7 3.7.8 3.7.9 3.7.10 3.7.11 3.7.12 3.8 3.8.1 3.8.2 3.8.3 3.8.4 3.9 3.9.1 3.9.2 3.9.3 3.9.4 3.10 3.10.1 3.10.2 Winbond Electronics Corp. Advanced PC Product Center

Table of Contents (Continued) www.national.com Revision1.1 PC8374L 3.10.3 3.11 3.11.1 3.11.2 3.11.3 3.12 3.12.1 3.12.2 3.13 3.13.1 3.13.2 3.13.3 3.14 3.14.1 3.14.2 3.14.3 3.14.4 3.14.5 3.14.6 3.14.7 3.15 3.15.1 3.15.2 3.15.3 4.0 System Wake-Up Control (SWC) 4.1 4.2 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 4.3.7 4.3.8 4.3.9 4.3.10 Winbond Electronics Corp. Advanced PC Product Center

Table of Contents (Continued) Revision 1.1 www.national.com PC8374L 4.3.11 4.4 4.4.1 4.4.2 4.4.3 4.4.4 4.4.5 4.4.6 4.4.7 4.4.8 4.4.9 4.4.10 4.4.11 4.5 5.0 LPC Bus Interface 5.1 5.2 5.3 6.0 General-Purpose Input/Output (GPIO) Ports 6.1 6.2 6.2.1 6.2.2 6.3 6.3.1 6.3.2 6.4 6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 6.4.6 6.4.7 7.0 Glue Functions 7.1 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.2.6 Winbond Electronics Corp. Advanced PC Product Center

Table of Contents (Continued) www.national.com Revision1.1 PC8374L 7.2.7 7.2.8 7.2.9 8.0 Health Management (HM) 8.1 8.2 8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 8.2.6 8.2.7 8.2.8 8.2.9 8.2.10 8.2.11 8.3 8.3.1 8.3.2 8.4 8.4.1 8.4.2 8.4.3 8.4.4 8.4.5 8.4.6 8.4.7 8.4.8 8.4.9 8.4.10 8.4.11 8.4.12 8.4.13 8.4.14 8.4.15 8.4.16 8.5 9.0 Legacy Functional Blocks 9.1 9.1.1 9.1.2 9.2 9.2.1 Winbond Electronics Corp. Advanced PC Product Center

Table of Contents (Continued) Revision 1.1 www.national.com PC8374L 9.2.2 9.2.3 9.3 9.3.1 9.3.2 9.3.3 9.3.4 9.4 9.4.1 9.4.2 9.4.3 9.4.4 9.5 9.5.1 9.5.2 9.5.3 9.6 9.6.1 9.6.2 9.6.3

10.0 Device Characteristics

10.1 10.1.1 10.1.2 10.1.3 10.1.4 10.1.5 10.2 10.2.1 10.2.2 10.2.3 10.2.4 10.2.5 10.2.6 10.2.7 10.2.8 10.2.9 10.3 10.3.1 10.3.2 Winbond Electronics Corp. Advanced PC Product Center

Table of Contents (Continued) www.national.com Revision1.1 PC8374L 10.4 10.4.1 10.4.2 10.4.3 10.4.4 10.4.5 10.4.6 10.4.7 10.4.8 10.4.9 10.5 Winbond Electronics Corp. Advanced PC Product Center

www.national.com Revision 1.1 PC8374L 1.0 Signal/Pin Connection and Description

1.1 CONNECTION DIAGRAM

BUSY_WAIT ACK PD7 PD6 GPO12/RTS2/SOUT2/VddStrap1 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 TRK0 CTS1 VSB3 SECONDARY_HD PRIMARY_HD HD_LED IDE_RSTDRV BKFD_CUT CLOCKI14 LAD2 VDD3 PCIRST_OUT VSB5 100 101 102 103 104 105 106 107 108 WDATA VDD3 RI1 SCSI GA20 KBRST VSS VSS LAD3 LATCHED_BF_CUT VSB3 GRN_LED PWRGD_PS SLP_S3 SLP_S5 RSMRST VDD3 PWRGD_3V CPU_PRESENT MTR0 INDEX RDATA WP WGATE DENSEL VSS DSKCHG HDSEL VSS DTR_BOUT1/XOR_OUT/BADDR YLW_LED SIOPME VSS VCORF VBAT GPIOE16 GPIOE05/FANPWM3 VSS VSB3 GPIOE01/FANTACH3 GPIOE03/FANPWM1 GPIOE04/FANPWM2 SER_IRQ GPIOE07/FANTACH2 GPIOE06/FANTACH1 CC_DDCSCL/GPIOE13 5V_DDCSCL/GPIOE11 DSR1 RTS1/TRIS DRATE0 PCI_CLK LFRAME LDRQ STEP DCD1 AFD_DSTRB STB_WRITE DIR DR0 LAD0 ERR LAD1 VDD3 INIT SLIN_ASTRB VSS PCI_RESET CC_DDCSDA/GPIOE12 128-Pin PQFP (Top View) GPIOE03/DSR2/SIN2 GPIOE07/IRTX/DCD2 GPIOE06/IRRX/DTR_BOUT2 GPIOE05/DCD2/CTS2 GPO13/DTR_BOUTPC8374L2/RTS2/Vdd GPIOE04/CTS2/DSR2 NC GPIOE02/SOUT2/IRRX GPIOE01/SIN2/RI2 GPIOE00/RI2/IRTX GPIO15 GPIOE14 GPIOE00/SWD MCLK MDAT KBCLK KBDAT PC8374L PS_ON GPIOE13 GPIOE17 NC PCIRST_OUT2/GPIOE12 REF5V GPIOE02/FANTACH4 5V_DDCSDA/GPIOE10 SMB1_SCL SMB1_SDA HMSCL/SMB2_SCL HMSDA/SMB2_SDA SOUT1/TEST SIN1 GPO11/VsbStrap1/ REF5V_STBY Note: ’xxx’ stands for the following Keyboard Controller Microcodes: IBW - for AMI IBU - for Intel IBM - for IBM ICG - for Dell ICK - for Phoenix Plastic Quad Flatpack (PQFP), JEDEC Order Number PC8374L0xxx/VLA Winbond Electronics Corp. Advanced PC Product Center

1.0 Signal/Pin Connection and Description (Continued)

www.national.com Revision1.1 PC8374L Pin Pin Name Pin Pin Name Pin Pin Name Pin Pin Name MCLK SLCT CLOCKI14 VCORF MDAT PE HD_LED VBAT KBCLK BUSY_WAIT PRIMARY_HD SIOPME KBDAT ACK SECONDARY_HD 100 GPIOE16 GA20 PD7 SCSI 101 GPIOE14 VDD3 PD6 REF5V 102 NC KBRST PD5 VSB5 103 GPIOE00/SWD VSS PD4 REF5V_STBY 104 GPIOE01/FANTACH3 DSKCHG PD3 PCIRST_OUT 105 FANTACH4/GPIOE02 HDSEL PD2 PCIRST_OUT2/GPIOE12 106 GPIOE03/FANPWM1 RDATA PD1 GPIOE13 107 VSB3 WP PD0 VSB3 108 GPIOE04/FANPWM2 TRK0 ERR BKFD_CUT 109 GPIOE05/FANPWM3 WGATE VSS VSS 110 VSS WDATA SLIN_ASTRB LATCHED_BF_CUT 111 GPIOE06/FANTACH1 STEP INIT GPIOE17 112 GPIOE07/FANTACH2 DIR VDD3 PS_ON 113 CC_DDCSCL/GPIOE13 DR0 AFD_DSTRB PWRGD_PS 114 5V_DDCSCL/GPIOE11 MTR0 STB_WRITE CPU_PRESENT 115 CC_DDCSDA/GPIOE12 INDEX SMI PWRGD_3V 116 5V_DDCSDA/GPIOE10 DRATE0 SER_IRQ SLP_S3 117 GPO11/VsbStrap1 DENSEL LDRQ SLP_S5 118 GPIOE00/RI2/IRTX DCD1 PCI_CLK SMB1_SCL 119 GPIOE01/SIN2/RI2 DSR1 LFRAME SMB2_SCL/HMSCL 120 GPIOE02/SOUT2/IRRX SIN1 LAD3 SMB1_SDA 121 GPIOE03/DSR2/SIN2 RTS1/TRIS VSS SMB2_SDA/HMSDA 122 GPO12/RTS2/SOUT2/ VddStrap1 SOUT1/TEST LAD2 GPIO15 123 NC CTS1 VDD3 RSMRST 124 GPIOE04/CTS2/DSR2 VSS LAD1 VSB3 125 GPO13/DTR_BOUT2/ RTS2/VddStrap2 DTR_BOUT1/BADDR/ XOR_OUT LAD0 GRN_LED 126 GPIOE05/DCD2/CTS2 VDD3 PCI_RESET YLW_LED 127 GPIOE06/IRRX/ DTR_BOUT2 RI1 IDE_RSTDRV VSS 128 GPIOE07/IRTX/DCD2 Winbond Electronics Corp. Advanced PC Product Center

Revision 1.1 www.national.com PC8374L

1.2 BUFFER TYPES AND SIGNAL/PIN DIRECTORY

The signal DC characteristics of the pins described in Section 1.4 on page 21 are denoted by buffer type symbols, which are defined in Table 1 and described in further detail in Section 10.2 on page 213. Table 1. Buffer Types

Description

Input, TTL compatible INTS Input, TTL compatible, with 250 mV Schmitt Trigger INTS2 Input, TTL compatible, with 200 mV Schmitt Trigger INTS4 Input, TTL compatible, with 400 mV Schmitt Trigger INPCI Input, PCI 3.3V compatible INSM Input, SMBus compatible INULR Input, power, resistor protected (not characterized) AI Input, analog (0-5.5V tolerant) Op/n Output, TTL/CMOS compatible, push-pull buffer capable of sourcing p mA and sinking n mA ODn Output, TTL/CMOS compatible, open-drain buffer capable of sinking n mA OPCI Output, PCI 3.3V compatible, AO Output, analog (0-5.5V tolerant) SWSM Input/Output switch, SMBus compatible PWR Power pin GND Ground pin Winbond Electronics Corp. Advanced PC Product Center

1.3 PIN MULTIPLEXING

Table 2 shows only multiplexed pins, their associated functional blocks and the configuration bits for the selection of the multiplexed options used in the PC8374L. Table 2. Pin Multiplexing Configuration

1. VSB strap input. Reserved for National use.
2. VDD strap input. Reserved for National use.

Table 2. Pin Multiplexing Configuration (Continued)

Table 3. GPIO Selection on Pins

Table 3. GPIO Selection on Pins (Continued)

Revision 1.1 www.national.com PC8374L

1.4 DETAILED SIGNAL/PIN DESCRIPTIONS

This section describes all signals of the PC8374L device. The signals are organized by functional group. 1.4.1 LPC Interface 1.4.2 Serial Port 1 and Serial Port 2 (UART1 and UART2) Signal Pin(s) I/O Buffer Type Power Well 57, 59, 61-62 I/O INPCI/OPCI VDD3 LPC Address-Data. Multiplexed command, address bi-directional data and cycle status. PCI_CLK I INPCI VDD3 LPC Clock. PCI clock used for the LPC bus (up to 33 MHz). LFRAME I INPCI VDD3 LPC Frame. Low pulse indicates the beginning of a new LPC cycle or termination of a broken cycle. LDRQ O OPCI VDD3 LPC DMA Request. Encoded DMA request for LPC interface. PCI_RESET I INPCI VDD3 LPC Reset. PCI system reset used for the LPC bus (Hardware Reset). SER_IRQ I/O INPCI/OPCI VDD3 Serial IRQ. The interrupt requests are serialized over a single pin, where each IRQ level is delivered during a designated time slot. SMI O OD6 VDD3 System Management Interrupt. Active (low) level indicates that an SMI occurred. External pull-up resistor to VDD3 is required. Signal Pin(s) I/O Buffer Type Power Well I INTS VDD3 Clear to Send. When low, indicates that the modem or other data transfer device is ready to exchange data. CTS2 124 or 126 I INTS VDD3 DCD1 I INTS VDD3 Data Carrier Detected. When low, indicates that the modem or other data transfer device has detected the data carrier. DCD2 126 or 128 I INTS VDD3 DSR1 I INTS VDD3 Data Set Ready. When low, indicates that the data transfer device, e.g., modem, is ready to establish a communications link. DSR2 121 or 124 I INTS VDD3 DTR_BOUT1 30 O O4/8 VDD3 Data Terminal Ready. When low, indicates to the modem or other data transfer device that the corresponding UART is ready to establish a communications link. After a system reset, these pins provide the DTR function and set these signals to inactive high. Baud Output. Provides the associated serial channel baud rate generator output signal if test mode is selected, i.e., bit 7 of EXCR1 register is set. DTR_BOUT2 125 or 127 O O4/8 VDD3 RI1 I INTS VDD3 Ring Indicator. When low, indicates that a telephone ring signal was received by the modem. These pins are monitored during VDD power-off for wake-up event detection. RI2 118 or 119 I INTS VDD3 RTS1 O O4/8 VDD3 Request to Send. When low, indicates to the modem or other data transfer device that the corresponding UART device is ready to exchange data. A system reset sets these signals to inactive high. RTS2 122 or 125 O O4/8 VDD3 SIN1 I INTS VDD3 Serial Input. Receives composite serial data from the communications link (peripheral device, modem or other data transfer device). SIN2 119 or 121 I INTS VDD3 Winbond Electronics Corp. Advanced PC Product Center

www.national.com Revision1.1 PC8374L 1.4.3 InfraRed Port 1.4.4 Parallel Port SOUT1 O O4/8 VDD3 Serial Output. Sends composite serial data to the communications link (peripheral device, modem or other data transfer device). These signals are set active high after a system reset. SOUT2 120 or 122 O O4/8 VDD3 Signal Pin(s) I/O Buffer Type Power Well I INTS VDD3 InfraRed Receive. InfraRed serial input data. IRTX 128 or 118 O O6/12 VDD3 InfraRed Transmit. InfraRed serial output data. Signal Pin(s) I/O Buffer Type Power Well I INT VDD3 Acknowledge. Pulsed low by the printer to indicate that it has received data from the parallel port. AFD_DSTRB 50 O OD14, O14/14 VDD3 AFD - Automatic Feed. When low, instructs the printer to automatically feed a line after printing each line. This pin is in TRI-STATE after a 0 is loaded into the corresponding control register bit. An external 4.7 KΩpull-up resistor must be connected to this pin. DSTRB - Data Strobe (EPP). Active low; used in EPP mode to denote a data cycle. When the cycle is aborted, DSTRB becomes inactive (high). BUSY_WAIT I INT VDD3 Busy. Set high by the printer when it cannot accept another character. Wait. In EPP mode, the parallel port device uses this active low signal to extend its access cycle. ERR I INT VDD3 Error. Set active low by the printer when it detects an error. INIT O OD14, O14/14 VDD3 Initialize. When low, initializes the printer. This signal is in TRI-STATE after a 1 is loaded into the corresponding control register bit. An external 4.7 KΩpull-up resistor must be connected to this pin. PD7-0 37-44 I/O INT/O14/14 VDD3 Parallel Port Data. Transfers data to and from the peripheral data bus and the appropriate parallel port data register. These signals have a high current drive capability. PE I INT VDD3 Paper End. Set high by the printer when it is out of paper. This pin has an internal weak pull-up or pull-down resistor. SLCT I INT VDD3 Select. Set active high by the printer when the printer is selected. SLIN_ASTRB 47 O OD14, O14/14 VDD3 SLIN - Select Input. When low, selects the printer. This signal is in TRI-STATE after a 0 is loaded into the corresponding control register bit. An external 4.7 KΩpull-up resistor must be connected to this pin. ASTRB - Address Strobe (EPP). Active low, used in EPP mode to denote an address cycle. When the cycle is aborted, ASTRB becomes inactive (high). Signal Pin(s) I/O Buffer Type Power Well Winbond Electronics Corp. Advanced PC Product Center

Revision 1.1 www.national.com PC8374L 1.4.5 Floppy Disk Controller (FDC) STB_WRITE O OD14, O14/14 VDD3 STB - Data Strobe. When low, Indicates to the printer that valid data is available at the printer port. This signal is in TRI- STATE after a 0 is loaded into the corresponding control register bit. An external 4.7 KΩpull-up resistor must be connected to this pin. WRITE - Write Strobe. Active low, used in EPP mode to denote an address or data write cycle. When the cycle is aborted, WRITE becomes inactive (high). Signal Pin(s) I/O Buffer Type Power Well O OD12 O6/12 VDD3 Density Select. Indicates that a high FDC density data rate (500 Kbps, 1 Mbps or 2 Mbps) or a low density data rate (250 or 300 Kbps) is selected. DIR O OD12 O6/12 VDD3 Direction. Determines the direction of the Floppy Disk Drive (FDD) head movement (active = step in; inactive = step out) during a seek operation. DR0 O OD12 O6/12 VDD3 Drive Select. Active low signal controlled by bit 0 of the Digital Output Register (DOR). DRATE0 O OD12 O6/12 VDD3 Data Rate. Reflects the value of bit 0 of either Configuration Control Register (CCR) or Data Rate Select Register (DSR), whichever was written to last. DSKCHG I INTS VDD3 Disk Change. Indicates that the drive door was opened. HDSEL O OD12 O6/12 VDD3 Head Select. Selects which side of the FDD is accessed. Active (low) selects side 1; inactive selects side 0. INDEX I INTS VDD3 Index. Indicates the beginning of an FDD track. MTR0 O OD12 O6/12 VDD3 Motor Select. Active low motor enable signal for drive 0, controlled by bit D4 of the Digital Output Register (DOR). RDATA I INTS VDD3 Read Data. Raw serial input data stream read from the FDD. STEP O OD12 O6/12 VDD3 Step. Issues pulses to the disk drive at a software programmable rate to move the head during a seek operation. TRK0 I INTS VDD3 Track 0. Indicates to the controller that the head of the selected floppy disk drive is at track 0. WDATA O OD12 O6/12 VDD3 Write Data. Carries out the pre-compensated serial data that is written to the FDD. Pre-compensation is software selectable. WGATE O OD12 O6/12 VDD3 Write Gate. Enables the write circuitry of the selected FDD. WGATE is designed to prevent glitches during power-up and power-down. This prevents writing to the disk when power is cycled. WP I INTS VDD3 Write Protected. Indicates that the disk in the selected drive is write protected. Signal Pin(s) I/O Buffer Type Power Well Winbond Electronics Corp. Advanced PC Product Center

www.national.com Revision1.1 PC8374L 1.4.6 Keyboard and Mouse Controller (KBC) 1.4.7 General-Purpose I/O (GPIO) Signal Pin(s) I/O Buffer Type Power Well Keyboard Clock. Keyboard clock signal. External pull-up resistor is required for PS/2 compliance. This pin is monitored during VDD3 power-off for wake-up event detection. KBDAT I/O INTS/OD14 VDD3 Keyboard Data. Keyboard data signal. External pull-up resistor is required for PS/2 compliance. This pin is monitored during VDD3 power-off for wake-up event detection. MCLK I/O INTS/OD14 VDD3 Mouse Clock. Mouse clock signal. External pull-up resistor is required for PS/2 compliance. This pin is monitored during VDD3 power-off for wake-up event detection. MDAT I/O INTS/OD14 VDD3 Mouse Data. Mouse data signal. External pull-up resistor is required for PS/2 compliance. This pin is monitored during VDD3 power-off for wake-up event detection. KBRST I/O INT/OD8, O4/8 VDD3 KBD Reset. Keyboard reset (P20) quasi-bidirectional output. GA20 I/O INT/OD8, O4/8 VDD3 Gate A20. KBC gate A20 (P21) quasi-bidirectional output. Signal Pin(s) I/O Buffer Type Power Well OD8, O4/8 VSB3 General-Purpose I/O Ports. Each pin is configured independently as input or I/O, with or without static pull-up (and some also with or without static pull-down) and with either open-drain or push-pull output type. These pins have event detection capability to generate a wake-up event or an interrupt. Note: If GPIOE12 is configured (on pin 74) make sure that the pin’s default function does not interfere with the circuit connected to the GPIO. Failure to do so may result in irreversible damage to the chip. 118 INTS/ OD12, O6/12 VDD3 GPIOE01-06 104-106, 108-109, 111 INTS/ OD8, O4/8 VSB3 119-121, 124, 126-127 VDD3 GPIOE07 112 INTS/ OD8, O4/8 VSB3 128 INTS/ OD12, O6/12 VDD3 GPIOE10-13 116, 114, 115, 113 INTS2/ OD6, O3/6 VSB3 GPIOE12-13 74-75 INTS/ OD8, O4/8 GPIOE14, GPIOE16-17 101, 100, 80 GPIO15 INTS/ OD8, O4/8 General-Purpose I/O Port. This pin is configured independently as input or I/O with or without static pull-up and with either open-drain or push-pull output type. GPO11 117 O OD8, O4/8 General-Purpose Output Port. This pin is configured independently as output, with or without static pull-up and with either open-drain or push-pull output type. GPO12-13 122, 125 VDD3 Winbond Electronics Corp. Advanced PC Product Center

Revision 1.1 www.national.com PC8374L 1.4.8 Health Management (HM) 1.4.9 System Wake-Up Control (SWC) Signal Pin(s) I/O Buffer Type Power Well SensorPath Data. Bidirectional, SensorPath Data interface signal to LMxx sensor device(s). An internal pull-up for this pin is optional. HMSCL I/O INSM/OD6 VSB3 Health Management SMBus Serial Clock. Serial clock signal. External pull-up resistor is required. HMSDA I/O INSM/OD6 VSB3 Health Management SMBus Serial Data. Serial data signal. External pull-up resistor is required. FANTACH1-4 111-112, 104-105 I INTS VDD3 Fan Inputs. Used to feed the fan’s tachometer pulse to the Fan Speed Monitor. FANPWM1-3 106, 108-109 O OD12,O6/12 VDD3 Fan Outputs. Pulse Width Modulation (PWM) signals, used to control the speed of cooling fans by controlling the voltage supplied to the fan motors. Signal Pin(s) I/O Buffer Type Power Well 103-106, 108-109, 111-112 I INTS VSB3 Wake-Up Inputs. Generates a wake-up event. These pins have programmable debouncing. When the pin is not used, the internal pull-up resistor must be enabled to allow the pin to be left not connected. 118-121, 124, 126-128 VDD3 GPIOE10-13 116, 114, 115, 113 INTS2 VSB3 GPIOE12-13 74-75 INTS GPIOE14, GPIOE16-17 101, 100, 80 RI1 RI2 32, 118 or 119 I INTS VSB3 Ring Indicator Wake-Up. When low, generates a wake-up event, indicating that a telephone ring signal was received by the modem. KBCLK I INTS VSB3 Keyboard Clock Wake-Up. Generates a wake-up event when a specific keyboard sequence is detected. KBDAT I INTS VSB3 Keyboard Data Wake-Up. Generates a wake-up event when a specific keyboard sequence is detected. MCLK I INTS VSB3 Mouse Clock Wake-Up. Generates a wake-up event when a specific mouse action is detected. MDAT I INTS VSB3 Mouse Data Wake-Up. Generates a wake-up event when a specific mouse action is detected. SIOPME O OD8, O4/8 VSB3 Power Management Event (SCI). Active level indicates that a wake-up event occurred, causing the system to exit its current sleep state. This signal has programmable polarity (default is active low). SLP_S3, SLP_S5 85, I INTS4 VSB3 Sleep States 3 to 5. Active (low) level indicates the system is in one of the sleep states S3 or S5. These signals are generated by an external ACPI controller. YLW_LED, GRN_LED 95, O OD24 VSB3 Power LEDs. Yellow and green LED drivers. Each indicates the Main power status or blinks under software control. Winbond Electronics Corp. Advanced PC Product Center

www.national.com Revision1.1 PC8374L

1.4.10 Clock

1.4.11 Glue Functions

Pin(s) I/O Buffer Type Power Well I INTS VDD3 High-Frequency Clock Input. 14.31818 MHz clock for the on- chip, 48 MHz Clock Generator (for the Legacy modules). Signal Pin(s) I/O Buffer Type Power Well O AO VSB3 Main Highest Active Supply, Reference Output. Reference voltage equal to the highest voltage between VDD5 and VDD3. External pull-up resistor to VDD5 is required. REF5V_STBY O AO VSB3 Standby Highest Active Supply, Reference Output. Reference voltage equal to the highest voltage between VSB5 and VSB3. External pull-up resistor to VSB5 is required. PS_ON O OD6 VSB3 Main Power Supply On/Off Control. Active (low) level turns the main power supply (VDD) on. External pull-up resistor to VSB5 is required. PWRGD_PS I INTS4 VSB3 Power Good Signal from the Power Supply. Active level indicates the Main power supply voltage is valid. PWRGD_3V O O3/6 VSB3 Power Good Output. Active level indicates: Main supply voltage is valid and the system is in a higher than S3 sleep state. CPU_PRESENT I INTS4 VSB3 CPU Present. Active (low) level indicates a processor is currently plugged in. BKFD_CUT O OD6 VSB3 Backfeed-Cut Control. Power distribution control (when switching between main and standby regulators) for system transition into and out of the S3 sleep state. External pull-up resistor to VSB5 is required. LATCHED_BF_ CUT O O14/14 VSB3 Latched Backfeed-Cut. Power distribution control (when switching between main and standby regulators) for system transition into and out of the S5 sleep state. VSB5 I AI VSB3 Standby 5V Power Supply. Used for Resume Reset generation (Range: 0-5.5V, Backdrive protected). RSMRST O O3/6 VSB3 Resume Reset. Power-Up reset signal based on the VSB5 supply voltage. PRIMARY_HD I INTS4 VDD3 Primary Drive. Active (low) level indicates that the primary IDE drive is active. SECONDARY_HD 68 I INTS4 VDD3 Secondary Drive. Active (low) level indicates that the secondary IDE drive is active. SCSI I INTS4 VDD3 SCSI Drive. Active (low) level indicates that the SCSI drive is active. HD_LED O OD12 VDD3 Hard Drive LED. Red LED driver. When low, indicates that at least one drive is active. CC_DDCSCL 113 I/O SWSM VSB3 Chipset Cluster (2.5V or 3.3V) Level DDC Serial Clock. SMBus serial clock signal with 2.5V or 3.3V logic levels for Data Display Channel (DDC) interface. External pull-up resistor to VDD3 or 2.5V is required. 5V_DDCSCL 114 I/O SWSM VSB3 5V Level DDC Serial Clock. SMBus serial clock signal with 5V logic levels for VGA monitor interface. External pull-up resistor to VDD5 is required. Winbond Electronics Corp. Advanced PC Product Center

Revision 1.1 www.national.com PC8374L CC_DDCSDA 115 I/O SWSM VSB3 Chipset Cluster (2.5V or 3.3V) Level DDC Serial Data. SMBus serial data signal with 2.5V or 3.3V logic levels for DDC interface. External pull-up resistor to VDD3 or 2.5V is required. 5V_DDCSDA 116 I/O SWSM VSB3 5V Level DDC Serial Data. SMBus serial data signal with 5V logic levels for VGA monitor interface. External pull-up resistor to VDD5 is required. SMB1_SCL I/O SWSM VSB3 Bus 1 Serial Clock. Serial clock signal of SMBus 1 (3.3V logic levels). External pull-up resistor to the 3.3V supply is required. SMB2_SCL I/O SWSM VSB3 Bus 2 Serial Clock. Serial clock signal of SMBus 2 (3.3V logic levels). External pull-up resistor to the 3.3V supply is required. SMB1_SDA I/O SWSM VSB3 Bus 1 Serial Data. Serial data signal of SMBus 1 (3.3V logic levels). External pull-up resistor to the 3.3V supply is required. SMB2_SDA I/O SWSM VSB3 Bus 2 Serial Data. Serial data signal of SMBus 2 (3.3V logic levels). External pull-up resistor to the 3.3V supply is required. PCIRST_OUT O O14/14 VSB3 PCI Reset Output. PCI system reset. PCIRST_OUT is a buffered copy of PCI_RESET when VDD3 is on, and it is held at low level when VDD3 is off. PCIRST_OUT2 O O14/14 VSB3 PCI Reset Output 2. PCI system reset (same behavior as PCIRST_OUT above). IDE_RSTDRV O OD6 VDD3 IDE Reset Output. IDE drive reset. IDE_RSTDRV is a buffered copy of PCI_RESET when VDD3 is on, and it is floating when VDD3 is off. Signal Pin(s) I/O Buffer Type Power Well Winbond Electronics Corp. Advanced PC Product Center

www.national.com Revision1.1 PC8374L

1.4.12 Configuration Straps and Testing

1.4.13 Power and Ground

Pin(s) I/O Buffer Type Power Well I INTS VDD3 Base Address. Sampled at VDD Power-Up reset to determine the base address of the configuration Index-Data register pair, as follows: – No pull-down resistor (default) - 2Eh-2Fh – 10 KΩ1 external pull-down resistor - 4Eh-4Fh The external pull-down resistor must be connected to VSS. 1. Because the strap function is multiplexed with the Serial Port pins, a CMOS transceiver device is recommended for Serial Port functionality; in this case, the value of the external pull-down resistor is 10 KΩ. If, however, a TTL transceiver device is used, the value of the external pull-down resistor must be 470Ω, and since the Serial Port pins are not able to drive this load, the external pull-down resistor must be disconnected tEPLV after VDD3 power-up (see “VDD Power-Up Reset” on page 221). VsbStrap1 117 I INTS VSB3 Vsb Strap 1. Reserved strap input function for National use. VddStrap1 122 I INTS VDD3 Vdd Strap 1. Reserved strap input function for National use. VddStrap2 125 I INTS VDD3 Vdd Strap 2. General-Purpose strap input function. TRIS I INTS VDD3 TRI-STATE Device. Sampled at VDD Power-Up reset to force the device to float all its output and I/O pins, as follows: – No pull-down resistor (default) - normal pin operation – 10 KΩ1 external pull-down resistor - floating device pins The external pull-down resistor must be connected to VSS. When TRIS is set to 0 (by an external pull-down resistor), TEST must be 1 (left unconnected). TEST I INTS VDD3 XOR Tree Test Mode. Sampled at VDD Power-Up reset to force the device pins into a XOR tree configuration, as follows: – No pull-down resistor (default) - normal device operation – 10 KΩ1 external pull-down resistor - pins configured as XOR tree. When TEST is set to 0 (by an external pull-down resistor), TRIS must be 1 (left unconnected). XOR_OUT O O4/8 VDD3 XOR Tree Output. All the device pins (except not connected pins, power type and analog type pins) are internally connected in a XOR tree structure. Signal Pin(s) I/O Buffer Type Power Well 8, 29, 46, 58, 78, 96, 110 I GND Ground. Ground connection for both core logic and I/O buffers, for the Main, Standby and Battery power supplies. VDD3 6, 31, 49, 60 I PWR Main 3.3V Power Supply. Powers the I/O buffers of the legacy peripherals and the LPC interface. VSB3 76, 93, 107 I PWR Standby 3.3V Power Supply. Powers the I/O buffers of the GPIO ports, SWC, Glue Functions, Health Management and the on-chip Core power converter. VCORF I/O PWR On-Chip Core Power Converter Filter. On-chip Core power converter output. An external 1 µF ceramic filter capacitor must be connected between this pin and VSS. Winbond Electronics Corp. Advanced PC Product Center

Revision 1.1 www.national.com PC8374L VBAT I INULR Battery Power Supply. When VSB3 is off, this supply provides battery back-up to some of the SWC registers. When the functions powered by VBAT are not used, the VBAT pin must be connected to VSB3. The pin is connected to the internal logic through a series resistor for UL-compliant protection. VSB5 I PWR Standby 5V Power Supply. Used for Resume Reset generation in the Glue Logic. Signal Pin(s) I/O Buffer Type Power Well Winbond Electronics Corp. Advanced PC Product Center

1.5 INTERNAL PULL-UP AND PULL-DOWN RESISTORS

for those signals indicated as “Programmable”. See Section 10.3 on page 218 for the values of each resistor type. Table 4. Internal Pull-Up and Pull-Down Resistors

1. Default at reset: enabled.
2. Enabled only when the OD6 buffer type is selected (OD6 is the default at reset).
3. Alternate function at reset: enabled.
4. Default at reset: PD enabled.
5. Default at reset: disabled.
6. Alternate function at reset: disabled.
7. Active only during VDD Power-Up reset.
8. Active only during VSB Power-Up reset.

Table 4. Internal Pull-Up and Pull-Down Resistors (Continued)

www.national.com Revision1.1 PC8374L 2.0 Power, Reset and Clocks

2.1 POWER

2.1.1 Power Planes The PC8374L device has four power planes (wells), as shown in the table below: For correct operation, VSB3 must be applied before VDD3. The battery backup voltage (VBAT) powers some of the SWC functions and Health Management configuration even when the VSB3 voltage is absent due to either power failure or disconnection of the external AC input power. When the functions powered by VBAT are not used, the VBAT pin must be connected to VSB3. To meet the UL standard requirements, a series resistor (RUL) is implemented. 2.1.2 Power States The PC8374L device has four power states:

• Battery Fail - Backup power plane is powered off (VBAT is inactive). This power state applies only to the SWC functions and Health Management configuration powered by VBAT.
• Power Fail - Main, Standby and Core power planes are powered off (VDD3, VSB3 and VCORF are inactive).
• Power Off - Main power plane is powered off; the Standby and Core power planes are on (VDD3 is inactive; VSB3 and VCORF are active).
• Power On - Main, Standby and Core power planes are powered on (VDD3, VSB3 and VCORF are active). The following power state is illegal:
• The Main power plane is powered on and the Standby and Core power planes are off (i.e., VDD3 is active; VSB and VCORF are inactive). Operation is not guaranteed; however, at power-on/off, the device may temporarily enter this power state due to the different rise/fall times of the VDD3 and VSB3 power supplies. Table 6 summarizes the power states described above.

Table 5. Power Planes Powers the I/O buffers for the external signals1 of the Legacy modules (Serial Ports, InfraRed Port, Parallel Port, FDC, KBC), on-chip High-Frequency Clock Generator and the LPC interface, including the buffered reset outputs 1. See the tables in Section 1.4 (pages 21−28), specifically the Power Well column. VDD3 VSS Standby Powers the I/O buffers for the external signals1 of the GPIO ports, SWC, Health Management, Glue Functions and the on-chip Core power converter VSB3 VSS Core Powers the internal (core) logic of all the device modules VCORF 2. VCORF is generated from VSB3 by an on-chip power converter. VSS Backup3 3. Bits powered by VBAT are functional when VSB3 is on, regardless of the state of VBAT power. How- ever, if VBAT fails, the value of these bits remains valid only as long as VSB3 is on. Powers some of the SWC functions and Health Management configuration VBAT VSS Winbond Electronics Corp. Advanced PC Product Center

2.0 Power, Reset and Clocks (Continued)

PC8374L device, the VBAT pin must be connected to VSB3. VDD3, VSB3, VCORF and VBAT use a common ground return marked VSS. To obtain the best performance, bear in mind the following recommendations. Table 6. Power States and Related Power Planes

1. VCORF is generated from VSB3; therefore, both voltages are on or off at approximately the same time.
2. This power state applies only to the SWC functions and Health Management configuration pow-
3. Operation is not guaranteed and register data may be corrupted. However, at power-on/off, the

Figure 1. Power State Transitions after VSB3 is turned off (Power Fail).

• The ground return (VSS) pins
• The decoupling capacitors of the Main power supply (VDD3) pins
• The decoupling capacitors of the Standby power supply (VSB3) pins
• The decoupling capacitor of the Standby 5V supply (VSB5) pin
• The decoupling capacitor of the on-chip Core power converter (VCORF) pin
• The decoupling capacitor of the Backup battery (VBAT) pin Note that a low-impedance ground layer also improves noise isolation. Decoupling Capacitors. The following decoupling capacitors must be used in order to reduce EMI and ground bounce:
• Main power supply (VDD3): Place one capacitor of 0.1 µF on each VDD3-VSS pin pair as close to the pin as possible. In addition, place one 10−47 µF tantalum capacitor on the common net as close to the chip as possible.
• Standby power supply (VSB3): Place one capacitor of 0.1 µF on each VSB3-VSS pin pair as close to the pin as possible. In addition, place one 10−47 µF tantalum capacitor on the common net as close to the chip as possible.
• Standby 5V supply (VSB5): Place one capacitor of 0.1 µF on the VSB5-VSS pin pair as close to the pin as possible.
• On-chip Core power converter (VCORF): Place one 1 µF ceramic capacitor on the VCORF-VSS pin pair as close to the pin as possible.
• Backup battery (VBAT): Place one capacitor of 0.1 µF on the VBAT pin as close to the pin as possible.

Figure 2. Decoupling Capacitors Connection

2.2 RESET SOURCES AND TYPES

• VBAT Power-Up Reset - activated when VBAT is powered up, if VSB3 is off.
• VSB Power-Up Reset - activated when VSB3 is powered up.
• VDD Power-Up Reset - activated when VDD3 is powered up.
• Hardware Reset - activated when the PCI_RESET input is asserted (low).
• Software Reset - triggered by SWRST bit in SIOCF1 register (see Section 3.7.5 on page 54); SWRST bit is set by the host through the LPC interface. VDD3 0.1 µF 0.1 µF 0.1 µF 0.1 µF VSS VDD3 VDD3 VDD3 VSS VSS VSS 10-47 µF Main 3.3V VSB3 VSS VSB3 VSB3 VSS VSS 0.1 µF 0.1 µF 0.1 µF 110 107 10-47 µF Standby 3.3V 1 µF VCORF VSB5 0.1 µF Standby 5V Backup 0.1 µF VBAT Battery PC8374L Winbond Electronics Corp. Advanced PC Product Center

Revision 1.1 www.national.com PC8374L Unless otherwise noted, reset references throughout the modules of the PC8374L devices default to the following resets:

• For VBAT-retained functions (some SWC, Health Management configuration): VBAT Power-Up reset (within the limita- tions described in Section 2.2.1).
• For VSB3-powered functions (GPIO ports, SWC, Health Management, Glue Functions and some Configuration Control): VSB Power-Up reset (within the limitations described in Section 2.2.2).
• For VDD3-powered functions (Legacy modules, LPC, on-chip Clock Generator and some Configuration Control): VDD Power-Up reset, Hardware Reset or Software Reset (within the limitations described in Sections 2.2.3, 2.2.4 and 2.2.5). The following sections detail the sources and effects of the various PC8374L resets. 2.2.1 VBAT Power-Up Reset VBAT Power-Up reset is generated by an internal circuit when VBAT power is applied, if VSB3 is off. An active VBAT Power- Up reset signal is generated following a rise in the VBAT until the level of the VBAT power higher than VBATLOW is detected (see Section 10.1.5 on page 213). A VBAT Power-Up reset is generated independently of the state of the VDD3 power supply. When VBAT Power-Up reset is active, it resets the registers whose values are retained by VBAT (some of the SWC, Health Management configuration). 2.2.2 VSB Power-Up Reset VSB Power-Up reset is generated by an internal circuit when VSB3 power is applied. The VSB Power-Up reset time (tIRST) lasts either 17 cycles of the 32 KHz clock domain or until the PCI_RESET signal is de-asserted, whichever occurs first. Ex- ternal devices must wait at least tIRST before accessing the PC8374L device. Note that the 32 KHz clock domain starts toggling t32KW + t32KVAL after VSB3 power-up. This delay must be added to the 17 clock cycles (see “Low-Frequency Clock Timing” on page 223). VSB Power-Up reset performs the actions listed below and all the actions performed by VDD Power-Up reset (see Section 2.2.3). Note that VDD3 must be active during VSB3 power-up for all VDD Power-Up reset actions to be performed:
• Puts pins with VSB3 strap options into TRI-STATE and enables their internal pull-up resistors
• Samples the logic levels of the VSB3 strap pins
• Samples the levels of the VBAT power pin
• Activates the relevant circuits in SWC according to the level of the VBAT power pin
• Loads default values to the VBAT-powered bits, if VBAT is off
• Resets all lock bits in configuration registers, Health Management and SWC
• Loads default values to VDDLOAD bits in the GPIO configuration registers
• Loads default values to the VSB3-powered bits in the configuration registers, SWC, Health Management and GPIO
• Sets up the pull-up or pull-down option and the default source for the VSB3-powered multiplexed output pins 2.2.3 VDD Power-Up Reset VDD Power-Up reset is generated by an internal circuit when VDD3 power is turned on. VDD Power-Up reset time (tIRST) lasts until the PCI_RESET signal is de-asserted. The Hardware reset (PCI_RESET) must be asserted for a minimum of 10 ms to ensure that the PC8374L device operates correctly. External devices must wait at least tIRST before accessing the PC8374L. If the host processor accesses the PC8374L during this time, the PC8374L LPC interface ignores the transaction (that is, it does not return a SYNC handshake). VDD3 Power-Up reset performs the following actions:
• Puts pins with strap options into TRI-STATE and enables their internal pull-up resistors
• Samples the logic levels of the strap pins
• Executes all the actions performed by the Hardware reset (see Section 2.2.4) 2.2.4 Hardware Reset Hardware reset is activated by the assertion (low) of the PCI_RESET input while VDD3 is “good”. When VDD3 power is off, the PC8374L device ignores the level of the PCI_RESET input. However, the PCIRST_OUT and PCIRST_OUT2 outputs reflect the PCI_RESET input and thus are active (low). In addition, the Hardware reset (PCI_RESET) must be asserted after VSB power-up, as described in Section 2.2.2. Winbond Electronics Corp. Advanced PC Product Center

• Resets all lock bits in configuration registers, Health Management and SWC
• Sets up the pull-up or pull-down option and the default source for the VDD3-powered multiplexed output pins
• Executes all the actions performed by the Software reset (see Section 2.2.5) 2.2.5 Software Reset The Software reset is triggered by the host setting SWRST bit in SIOCF1 register (see Section 3.7.5 on page 54) via the LPC interface. The Host Software reset performs the following actions:
• Loads default values to the VDD3-powered unlocked bits in the Configuration Control.
• Loads default values to the VSB3-powered unlocked GPIO Configuration and Data bits for those GPIO ports with VDDLOAD = 1. VDDLOAD bit is not affected.
• Resets all the VDD3-powered logical devices.
• Loads default values to all the VDD3-powered module registers, unless explicitly specified otherwise.

2.3 CLOCK DOMAINS

Table 7 shows the PC8374L clock domains. clock domains are active only when the VDD3 power supply is on. a certain time after first VDD3 power-up following VSB3 power-up, and they remain active as long as VSB3 exists. 32 KHz clock domain is active when the VSB3 power supply is on. page 224) before the end of the VDD Power-Up reset (see Section 2.2.3).

48 MHz Domain

on page 59) to be set before it enables the Legacy functions (Serial Ports, InfraRed Port, Parallel Port, FDC, KBC). Glue are functional on VSB3 power up. Table 7. Clock Domains of the PC8374L

48 MHz

360 KHz

32 KHz

32.768 KHz

(maximum). When only VSB3 exists, tolerance (long term deviation) of the output clock is ± 10%.

2.4 TESTABILITY SUPPORT

• In-Circuit Testing (ICT)
• XOR Tree Testing 2.4.1 ICT The In-Circuit Testing (ICT) technique, also known as “bed-of-nails”, injects logic patterns to the input pins of the devices mounted on the tested board. It then checks their outputs for the correct logic levels. The PC8374L supports this testing technique by floating (putting in TRI-STATE) all the device pins. This prevents “back- driving” the PC8374L pins by the ICT tester when a device normally controlled by PC8374L is tested (device inputs are driv- en by the ICT tester). To enter TRI-STATE mode, the TRIS pin must be pulled low (by a 10 KΩresistor to VSS), and the TEST pin must be left unconnected after both VDD3 and VSB3 power supplies are turned on. In addition, the PCI_RESET pin must be held low for at least 10 ms (see “VSB Power-Up Reset” on page 219 and “VDD Power-Up Reset” on page 221). After PCI_RESET is de- asserted, all the device output and I/O pins are floated (put in TRI-STATE); exceptions to this are the power supply pins (VDD3, VSB3, VSS, VCORF, VBAT), analog pins (VSB5, REF5V, REF5V_STBY), RSMRST, which do not float in TRI-STATE mode. 2.4.2 XOR Tree Testing When the PC8374L device is mounted on a board, it can be tested using the XOR Tree technique. This test also checks the correct connection of the device pins to the board. To enter XOR Tree mode, the TEST pin must be pulled low (by a 10 KΩresistor to VSS), and the TRIS pin must be left unconnected after both VDD3 and VSB3 power supplies are turned on. In addition, the PCI_RESET pin must be held low for at least 10 ms (see “VSB Power-Up Reset” on page 219 and “VDD Power-Up Reset” on page 221). After PCI_RESET is de- asserted, the device pins (including the PCI_RESET, TRIS and TEST pins) are connected in a XOR Tree configuration and are isolated from the internal PC8374L functions. In XOR Tree mode, all PC8374L device pins are configured as inputs, except the last pin in the tree, which is the XOR_OUT output. The buffer type of the input pins participating in the XOR tree, is INT (Input, TTL compatible), regardless of the buffer type of these pins in normal device operation mode (see Section 1.4 on page 21). The input pins are chained through XOR gates, as shown in Figure 3. The power supply pins (VDD3, VSB3, VSS, VCORF, VBAT), the analog pins (VSB5, REF5V, REF5V_STBY, RSMRST) and the not connected pins (NC) are excluded from the XOR tree.

Figure 3. XOR Tree (Simplified Diagram) and 28, and ends with pin 30 (XOR_OUT). The maximum propagation delay through the XOR tree, from pin 32 to XOR_OUT is 200 ns.

device specific information, including specific implementation of generic blocks, system interface and device configuration.

3.1 OVERVIEW

set of configuration registers. 8-bit Memory Firmware Read/Write, and 8-bit DMA transactions of the LPC bus (see Section 5.2 on page 109). al blocks through special control signals.

3.2 CONFIGURATION STRUCTURE AND ACCESS

The configuration structure is based on a set of banked registers that are accessed via a pair of specialized registers. Access to the PC8374L configuration registers is via an Index-Data register pair, using only two system I/O byte locations. the BADDR pin. Table 8 shows the selected base addresses as a function of BADDR. configuration register file and holds the index of the configuration register that is currently accessible via the Data register. Reading the Index register returns the last value written to it (or the default of 00h after reset). actually accesses the configuration register that is currently pointed to by the Index register. values of the PC8374L functional blocks. Any value not listed is reserved. register and pointed to by the Index register. Table 8. BADDR Strapping Options

3.0 Device Architecture and Configuration (Continued)

Figure 4. Structure of Standard Configuration Register File which returns 04h (indicating no DMA channel). The configuration registers are accessible immediately after reset.

• All registers are read/write.
• All reserved bits return 0 on reads, except where noted otherwise. To prevent unpredictable results, do not modify these bits. Use read-modify-write to prevent the values of reserved bits from being changed during write.
• Write-only registers must not use read-modify-write during updates.

Table 9. Logical Device Number (LDN) Assignments

www.national.com Revision1.1 PC8374L Table 10. Standard General Configuration Registers This register selects the current logical device. See Table 9 for valid numbers. All other values are reserved. 10h Memory Mapping Control Enables the memory mapping of the device and configuration registers. 12h Memory Base Address 1 Indicates selected Memory Base address bits 23-16. 13h Memory Base Address 2 Indicates selected Memory Base address bits 31-24. 20h-2Fh PC8374L Configuration PC8374L configuration registers and ID registers. Table 11. Logical Device Activate Register Bits 7-1: Reserved Bit 0: Logical device activation control (see Section 3.3 on page 48) 0: Disabled 1: Enabled Table 12. Memory Space Configuration Registers Controls the mapping of a logical device to I/O or to memory when MEMEN bit in MEMMAP register is set to 1 (see Section 3.7.1 on page 52). Bit 0: Logical device mapping control (see Section 3.3 on page 48) 0: Logical device is mapped to I/O space (default) 1: Logical device is mapped to Memory space Bits 7-1: Reserved Table 13. I/O Space Configuration Registers Address Bits 15−8 Descriptor 0 Indicates selected I/O lower limit address bits 15−8 for I/O Descriptor 0. 61h I/O Port Base Address Bits 7−0 Descriptor 0 Indicates selected I/O lower limit address bits 7−0 for I/O Descriptor 0. 62h I/O Port Base Address Bits 15−8 Descriptor 1 Indicates selected I/O lower limit address bits 15−8 for I/O Descriptor 1. 63h I/O Port Base Address Bits 7−0 Descriptor 1 Indicates selected I/O lower limit address bits 7−0 for I/O Descriptor 1. Winbond Electronics Corp. Advanced PC Product Center

Revision 1.1 www.national.com PC8374L Table 14. Interrupt Configuration Registers Indicates selected interrupt number. Bits 7-5: Reserved. Bit 4: Enables a Power Management event (SIOPME) from the IRQ of the logical device. When enabled, IRQ assertion sets the respective XXX_IRQ_STS bit (XXX is MOD, MS or KBD) in the GPE1_STS_3 register (see Section 4.4.7 on page 103). 0: Disabled (default) 1: Enabled Note: If the BIOS routine that sets IRQ does not use a Read-Modify-Write se- quence, it might reset bit 4. To ensure that the system wakes up, the BIOS must set bit 4 before the system goes to sleep. Bits 3-0: These bits select the interrupt number. A value of 1 selects IRQ1. A value of 15 selects IRQ15. IRQ0 is not a valid interrupt selection and represents no interrupt selection. Note: Avoid selecting the same interrupt number (except 0) for different Logical Devices, as it causes the PC8374L device to behave unpredictably. 71h Interrupt Request Type Select Indicates the type and polarity of the interrupt request number selected in the previous register. If a logical device supports only one type of interrupt, the corresponding bit is read-only. Bits 7-2: Reserved. Bit 1: Polarity of interrupt request selected in previous register 0: Low polarity 1: High polarity Bit 0: Type of interrupt request selected in previous register 0: Edge 1: Level Table 15. DMA Configuration Registers Indicates selected DMA channel for DMA 0 of the logical device (0 is the first DMA channel if more than one DMA channel is used). Bits 7-3: Reserved. Bits 2-0: These select the DMA channel for DMA 0. The valid choices are 3-0, where: - A value of 0 selects DMA channel 0, 1 selects channel 1, etc. - A value of 4 indicates that no DMA channel is active. - The values 5-7 are reserved. Note: Avoid selecting the same DMA channel (except 4) for different logical devic- es, as it causes the PC8374L device to behave unpredictably. 75h DMA Channel Select 1 Indicates selected DMA channel for DMA 1 of the logical device (1 is the second DMA channel if more than one DMA channel is used). Bits 7-3: Reserved. Bits 2-0: These select the DMA channel for DMA 1. The valid choices are 3-0, where: - A value of 0 selects DMA channel 0, 1 selects channel 1, etc. - A value of 4 indicates that no DMA channel is active. - The values 5−7 are reserved. Note: Avoid selecting the same DMA channel (except 4) for different logical devic- es, as it causes the PC8374L device to behave unpredictably. Winbond Electronics Corp. Advanced PC Product Center

www.national.com Revision1.1 PC8374L 3.2.4 Standard Configuration Registers Figure 5. Configuration Register Map Table 16. Special Logical Device Configuration Registers Configuration Special (vendor-defined) configuration options. SuperI/O Configuration Registers Logical Device Control and one per Logical Device Configuration Registers - Index Register Name 07h Logical Device Number 10h Memory Space Configuration 12h-13h Memory Base Address (MEM_BASE) 20h SuperI/O ID 21h SuperI/O Configuration 1 22h SuperI/O Configuration 2 23h SuperI/O Configuration 3 24h SuperI/O Configuration 4 25h Reserved 26h SuperI/O Configuration 6 27h SuperI/O Revision ID 28h Reserved 29h Clock Generator Control Health Management SMBus Configuration 2Bh-2Dh Reserved 2Eh-2Fh Reserved exclusively for National use 30h Logical Device Control (Activate) 50h Memory Base Descriptor 60h I/O Base Address Descriptor 0 Bits 15-8 61h I/O Base Address Descriptor 0 Bits 7-0 62h I/O Base Address Descriptor 1 Bits 15-8 63h I/O Base Address Descriptor 1 Bits 7-0 70h Interrupt Number and Wake-Up on IRQ Enable 71h IRQ Type Select 74h DMA Channel Select 0 75h DMA Channel Select 1 F0h-FFh Vendor-Defined Logical Device Configuration (some are optional) Winbond Electronics Corp. Advanced PC Product Center

Revision 1.1 www.national.com PC8374L SuperI/O Configuration Registers The PC8374L SuperI/O configuration registers at indexes 20h (SuperI/O ID) and 27h (SuperI/O Revision ID) are used for part identification. The other configuration registers are used for global power management and selecting pin multiplexing options. For details, see Section 3.7 on page 52. Logical Device Control and Configuration Registers A subset of these registers is implemented for each logical device. See the functional block descriptions in the following sec- tions. Control Registers The only implemented control register for each logical device is the Activate register at index 30h. Bit 0 of the Activate register controls the activation of the associated functional block. Activation enables access to the functional block’s runtime registers and attaches its system resources, which are unassigned as long as it is not activated. Other effects may apply on a function-specific basis (such as clock enable and active pinout signaling). Access to the configuration register of the logical device is enabled even when the logical device is not activated. Standard Configuration Registers The standard configuration registers manage the PnP resource allocation to the functional blocks. The I/O port base address descriptor 0 is a pair of registers at Index 60−61h that hold the first 16-bit base address for the register set of the functional block. An optional 16-bit second base-address (descriptor 1) at index 62−63h is used for logical devices with more than one continuous register set. Interrupt Number and Wake-Up on IRQ Enable (index 70h) and IRQ Type Select (index 71h) allocate an IRQ line to the block and control its type. DMA Channel Select 0 (index 74h) allocates a DMA channel to the block, where applicable. DMA Channel Select 1 (index 75h) allocates a second DMA channel, where applicable. Vendor-Defined Logical Device Configuration Register The vendor-defined logical device registers start at index F0h and control function-specific parameters such as operation modes, power saving modes, pin TRI-STATE, clock rate selection and non-standard extensions to generic functions. 3.2.5 Default Configuration Setup The default configuration setup of the PC8374L device is determined by the four reset types described in Section 2.2 on page 34. See the specific register descriptions for the bits affected by each reset source. In the event of a VSB3 Power-Up reset, the following default configuration is set up:

• All lock bits in the configuration registers are reset (the protected bits are unlocked).
• All the unlocked bits in the configuration registers powered by the VSB3 plane are reset to their default values. In the event of a VDD3 Power-Up (also induced by VSB3 Power-Up reset) or Hardware reset, the PC8374L device wakes up with the following default configuration setup:
• The configuration base address is 2Eh or 4Eh, according to the BADDR strap pin value, as shown in Table 8 on page 38.
• All lock bits in the configuration registers are reset (the protected bits are unlocked).
• All the actions performed by the Software reset are executed. If a Software reset occurs, the PC8374L device wakes up with the following default configuration setup:
• All the unlocked bits in the configuration registers powered by the VDD3 plane are reset to their default values.
• All logical devices are disabled (the Activation bit is reset) and the VSB3-powered logical devices (GPIO, SWC, and Health Management) remain functional but their registers cannot be accessed by the host.
• Standard configuration registers of all logical devices are set to their default values.
• National Semiconductor proprietary functions are not assigned with any default resources, and the default values of their base addresses are all 00h.
• All Legacy devices (Serial Ports, InfraRed Port, Parallel Port, Floppy Disk Controller, and Keyboard and Mouse Control- ler) are reset. Default values are loaded into the Legacy module runtime registers. Winbond Electronics Corp. Advanced PC Product Center

The PC8374L device configuration registers and Logical Device registers can be mapped to either I/O or memory space. memory base descriptor at I/O index 50h. used for mapping of PC8374L device registers; this allows the PC8374L device a linear address space with total of 64K. selector with the physical address defined in MEMADR1 and MEMADR2 registers, and a maximum size of 64K. each Logical Device that is organized as one bank. vices that are organized in banks. for Write 1-to-Clear or Read-to-Clear registers. and-play configuration, but they are not functionally identical. Table 19. Logical Device Number (LDN) Assignment for Memory Space Mapping Table 17. PC8374L Register Memory Address Table 18. PC8374L Register Memory Address to Logical Device with Register Banks

used as bit 27 of MEM_BASE, which is the most significant bit of the FWH address. Figure 6. PC8374L Memory Address Map Figure 7 shows the memory address map of Logical Devices with register banks. memory physical addresses of these registers. Table 20. Memory Physical Addresses of Device Configuration Registers

Figure 7. Logical Device Memory Map with Register Banks Figure 8. Control and Configuration Memory Map

Table 21. Memory Physical Addresses of Logical Device Configuration Registers

3.3 MODULE CONTROL

Module control is performed primarily through the Activation bit (bit 0 of index 30h) of each logical device. each module can be controlled by the host.

• Activation bit (bit 0) in index 30h of the Standard configuration registers (see Section 3.2.3 on page 39)
• Fast Disable bit in SIOCF6 register; for the FDC, Parallel Port and Serial Port (1 and 2) / InfraRed Port modules only (see Section 3.7.9 on page 57)
• Global Enable bit (GLOBEN) in SIOCF1 register (see Section 3.7.5 on page 54) A module is enabled only if all of these bits are set to their “enable” value. When a module is disabled, the following takes place:
• The host system resources of the logical device (IRQ, DMA and runtime address range) are unassigned.
• Access to the standard- and device-specific Logical Device configuration registers through the LPC bus remains enabled.
• Access to the module’s runtime registers through the LPC bus is disabled (transactions are ignored; SYNC cycle is not generated). Note that disabling a VDD3-powered module (FDC, Parallel Port, Serial Ports, InfraRed Port, KBC) stops the module’s inter- nal clock to lower the power consumption; as a result, the module is not functional. VSB-powered modules remain functional. 3.3.2 Floating Module Output The pins of the Legacy modules (Serial Ports, Parallel Port, Floppy Disk Controller, Keyboard and Mouse Controller) can be floated. When the TRI-STATE Control bit (bit 0) is set in the specific module configuration register (at index F0h of the specific Logical Device in the configuration space) and the module is disabled (see Section 3.3.1), the module output signals are floated and the I/O signals are configured as inputs (note that the logic level at the inputs is ignored by the module, which is disabled). Figure 9 shows the control mechanism for floating the pins of a Legacy module.

Figure 9. Control of Floating Legacy Module Pins

1. Wherever the bit is implemented

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3.4 INTERNAL ADDRESS DECODING

A full 16-bit address decoding is applied when accessing the configuration I/O space as well as the registers of the functional blocks. However, the number of configurable bits in the base address registers varies for each logical device. The lower 1, 2, 3, 4 or 5 address bits are decoded in the functional block to determine the offset of the accessed register within the logical device’s I/O range of 2, 4, 8, 16 or 32 bytes, respectively. The rest of the bits are matched with the base address register to decode the entire I/O range allocated to the logical device. Therefore, the lower bits of the base address register are forced to 0 (read-only), and the base address is forced to be 2, 4, 8, 16 or 32 byte-aligned, according to the size of the I/O range. The base address of the FDC, Serial Port 1, Serial Port 2, InfraRed Port, and KBC are limited to the I/O address range of 00h to 7FXh only (bits 15-11 are forced to 0). The Parallel Port base address is limited to the I/O address range of 00h to 3F8h. The addresses of all of the non-legacy logical devices, including the Health Management, SWC and GPIO, are con- figurable within the full 16-bit address range (up to FFFXh). In some special cases, other address bits are used for internal decoding (such as bit 2 in the KBC and bit 10 in the Parallel Port). The KBC has two I/O base addresses with some implied dependency between them. For more details, see the de- scription of the base address register for each logical device. Winbond Electronics Corp. Advanced PC Product Center

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3.5 PROTECTION

The PC8374L device provides features to protect the hardware configuration from changes made by application software running on the host. The protection is activated by the software setting a “sticky” lock bit. Each lock bit protects a group of configuration bits lo- cated either in the same register or in different registers. When the lock bit is set, the lock bit and all the protected bits be- come read-only and cannot be further modified by the host through the LPC bus. All the lock bits are reset by Power-Up reset, thus unlocking the protected configuration bits. The bit locking protection mechanism is optional. The protected groups of configuration bits are described below. 3.5.1 Multiplexed Pins Configuration Lock Protects the configuration of all the multiplexed device pins. Lock bit: LOCKMCF in SIOCF1 register (Device Configuration). Protected bits: LOCKMCF and IOWAIT in SIOCF1 register, and all bits in SIOCF2, SIOCF3 and SIOCF4 registers (Device Configuration). 3.5.2 GPIO Ports Configuration Lock Protects the configuration (but not the data) of all the GPIO Ports. Lock bit: LOCKGCF in SIOCF1 register (Device Configuration). Protected bits for each GPIO Port:LOCKGCF in SIOCF1 register, and all bits in GPCFG1 (except LOCKCFP bit), GPEVR, GPCFG2 and GPMODE registers (Device Configuration). 3.5.3 Fast Disable Configuration Lock Protects the Fast Disable bits for all the Legacy modules. Lock bit: LOCKFDS in SIOCF6 register (Device Configuration). Protected bits: All bits in SIOCF6 register (except General-Purpose Scratch bits) and GLOBEN bit in SIOCF1 register (Device Configuration). 3.5.4 Clock Control Lock Protects the Clock Generator control bits. Lock bit: LOCK in CLOCKCF register (Device Configuration). Protected bits: All bits in CLOCKCF register (Device Configuration). 3.5.5 GPIO Port Lock Protects the configuration and data of all the GPIO Ports. Lock bit: LOCKCFP in GPCFG1 register, for each GPIO Port (Device Configuration). Protected bits for each GPIO Port: LOCKCFP, PDNCTL, PUPCTL, OUTTYPE and OUTENA in GPCFG1 register; all bits in GPCFG2 register (Device Configuration); the corresponding bit (to the port pin) in GPDO and GPDIO registers (GPIO Ports). 3.5.6 Health Management Configuration Lock Protects the configuration of the Health Management module. Lock bit: LOCKHCF in HMCFG1 register (Device Configuration). Protected bits: All bits in HMCFG1 register (including LOCKHCF bit itself) (Device Configuration). 3.5.7 SWC Configuration Lock Protects the configuration of the SWC module, including the Keyboard and Mouse wake-up configuration. Lock bit: LOCKSCF in SWC_CTL register (System Wake-Up Control). Protected bits: BLINK and GRN_YLW bits in SLEDCTL register; all bits in SWC_CTL, ALEDCTL, LEDBLNK, XLEDCTL, KBDWKCTL, PS2CTL andPS2KEY0−7 registers (System Wake-Up Control). Winbond Electronics Corp. Advanced PC Product Center

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3.6 REGISTER TYPE ABBREVIATIONS

The following abbreviations are used to indicate the Register Type:

• R/W = Read/Write. = Read from register (data written to this address is sent to a different register). = Write (see above).
• RO = Read-only.
• WO = Write-only. Reading from the bit returns 0.
• R/WC = Read/Write any value to Clear. Writing any value to a bit clears it to 0.
• R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.
• R/W1S = Read/Write 1 to Set. Writing 1 to a bit sets its value to 1. Writing 0 has no effect. In the registers below, use one of the following methods to handle the reserved bits:
• Write 0 to reserved bits, unless another “required value” is specified. This method can be used for registers contain- ing bits of all types.
• Use read-modify-write to preserve the values of the reserved bits. This method can be used only for registers con- taining bits of R/W, RO, R/W1C and R/W1S types. Winbond Electronics Corp. Advanced PC Product Center

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3.7 PC8374L CONFIGURATION REGISTERS

This section describes the PC8374L configuration and ID registers (i.e., registers with first level indexes in the range of 10h−2Fh). 3.7.1 Memory Mapping Control Register (MEMMAP) Power Well: VDD3 Location: Index 10h Type: Varies per bit Bit Name MEMEN LOCKMEM Reserved BIODIS LDMEMEN CFGMEMEN Reset Bit Type MEMEN (Memory Mapping Enable). When set to 1, enables memory mapping. MEMADR1 and MEMADR2 registers must be configured before this bit is set to 1. 0: Memory mapping is disabled (default) 1: Memory mapping is enabled R/W1S LOCKMEM (Lock Memory Mapping Configuration). When set to 1, locks the configuration registers of memory mapping: MEMMAP, MEMADR1 and MEMADR2. Once set, the bit can be cleared only by VDD3 Power-Up reset. 0: R/W bits are enabled for write (default) 1: All bits of MEMMAP, MEMADR1 and MEMADR2 registers are RO 5-3 Reserved. R/W or RO BIODIS (I/O Base Address Disable). When set to 1, disables selected 2Eh/2Fh or 4Eh/4Fh addresses acknowledged on LPC, and prevents any I/O transaction to PC8374L device. The bit disables the PC8374L 2Eh/2Fh or 4Eh/4Fh I/O mapping only when MEMEN, LDMEMEN and CFGMEMEN bits are all set to 1. 0: The 2Eh/2Fh or 4Eh/4Fh I/O mapping is enabled (default) 1: The 2Eh/2Fh or 4Eh/4Fh I/O mapping is disabled R/W or RO LDMEMEN (Enable Memory Mapping of Logical Devices Configuration Registers). When set to 1, enables the memory mapping of Logical Devices Configuration registers (I/O index 30h-FFh). When cleared, all Logical Devices Configuration registers are I/O mapped. The bit enables memory mapping only when MEMEN bit is set to 1. 0: All Logical Devices Configuration registers are I/O mapped (default) 1: All Logical Devices Configuration registers are Memory mapped Note: When this bit is 1 (and MEMEN is 1), I/O mapping of the Logical Devices Configuration registers is still enabled (in addition to the memory mapping) when BIODIS is 0 or CFGMEMEN is 0. R/W or RO CFGMEMEN (Enable Memory Mapping of Control and Configuration Registers). When set to 1, enables the memory mapping of device control and configuration registers (I/O index 10h-2Fh). When cleared, the device control and configuration registers are I/O mapped. The bit enables memory mapping only when MEMEN bit is set to 1. 0: All control and configuration registers are I/O mapped (default). 1: All control and configuration registers are Memory mapped. Note: When this bit is 1 (and MEMEN is 1), I/O mapping of the device control and configuration regis- ters is still enabled (in addition to the memory mapping) when BIODIS is 0 or LDMEMEN is 0. Winbond Electronics Corp. Advanced PC Product Center

Revision 1.1 www.national.com PC8374L 3.7.2 Memory Base Address Register 1 (MEMADR1) Power Well: VDD3 Location: Index 12h Type: R/W or RO 3.7.3 Memory Base Address Register 2 (MEMADR2) Power Well: VDD3 Location: Index 13h Type: R/W or RO 3.7.4 SuperI/O ID Register (SID) This register contains the identity number of the device family. The PC8374L family is identified by the value F1. Power Well: VSB3 Location: Index 20h Type: RO Bit Name Memory Base Address 1 Reset Bit Memory Base Address 1. This register indicates selected Memory Base address bits 23-16. Bit Name TYPESEL MEMFWHID Memory Base Address 2 Reset Bit TYPESEL (Transaction Type Select). Selects the transaction type decoded for memory addresses. For address decoding of the Memory Base address, bit 31 value is 1 regardless of TYPESEL value, thus limiting the Memory Base Address to high 2G memory space. 0: Transactions type is LPC Memory Read/Write (default) 1: Transactions type is LPC FWH Memory Read/Write 6-3 MEMFWHID (Memory FWH ID). When TYPESEL is 0: Indicates selected Memory Base address bits 30-27. When TYPESEL is 1: indicates the IDSEL of the Firmware Memory transactions to which the PC8374L re- sponds. The least significant bit of this field is also used as Memory Base address bit 27. 2-0 Memory Base Address 2. Indicates selected Memory Base address bits 26-24. Bit Name Family ID Reset Bit 7−0 Family ID. Identifies a family of devices with similar functionality but with different implemented options. Winbond Electronics Corp. Advanced PC Product Center

www.national.com Revision1.1 PC8374L 3.7.5 SuperI/O Configuration 1 Register (SIOCF1) Power Well: VDD3 Location: Index 21h Type: Varies per bit Bit Name LOCKMCF LOCKGCF Reserved IOWAIT SWRST GLOBEN Reset Bit Type R/W1S LOCKMCF (Lock Multiplexing Configuration). When set to 1, locks itself, IOWAIT field in SIOCF1 register, and registers SIOCF2, SIOCF3 and SIOCF4 by disabling writing to all bits in these registers. Once set, the bit can be cleared by Hardware reset. 0: R/W bits are enabled for write (default) 1: All bits are RO R/W1S LOCKGCF (Lock GPIO Pins Configuration). When set to 1,locks the configuration registers of all GPIO pins (see Section 3.14.2 on page 74) by disabling writes to all their bits (including the LOCKGCF bit itself). The locked registers include the GPCFG1 (except LOCKCFP bit), GPEVR, GPCFG2 and GPMODE registers of all GPIO pins. Once set, this bit can be cleared by Hardware reset. 0: R/W bits are enabled for write (default) 1: All bits are RO 5-4 Reserved. 3-2 R/W or RO IOWAIT (Number of I/O Wait States). Sets the number of wait states for I/O transactions through the LPC bus. Bits 3 2 Number of Wait States 0 0: 0 (default) 0 1: 1 0: 1 1: R/W SWRST (Software Reset). When set to 1, triggers the Software reset sequence (see Section 2.2.5 on page 36), after which it returns to 0. Read always returns 0. The bit is not influenced by the value of LOCKMCF. 0: Inactive (default) 1: Trigger the Software reset sequence R/W or RO GLOBEN (Global Device Enable). Enables the disabling of all logical devices by changing a single bit (to 0). In addition, when the bit is set to 1, it enables the operation of all the logical devices of the PC8374L, as long as the logical device is itself enabled (see Table 9 on page 39). The behavior of the different devices is explained in Section 3.3 on page 48. 0: All logical devices in the PC8374L device are forced to be disabled and their resources are released. 1: Enables each PC8374L logical device that is itself enabled (default); see Section 3.3.1 on page 48. Winbond Electronics Corp. Advanced PC Product Center

Revision 1.1 www.national.com PC8374L 3.7.6 SuperI/O Configuration 2 Register (SIOCF2) Power Well: VSB3 Location: Index 22h Type: R/W or RO Bit Name PMEPOL PMETYPE TACH2EN TACH1EN Reserved TACH4EN TACH3EN GPIO03EN Reset Bit PMEPOL (SIOPME Polarity). Selects the polarity of the SIOPME signal. 0: SIOPME is active low (default) 1: SIOPME is active high PMETYPE (SIOPME Buffer Type). Selects the output buffer type of the SIOPME pin. 0: Output is open-drain and the pull-up resistor is enabled (default) 1: Output is push-pull (the pull-up resistor is disabled) TACH2EN (FANTACH2 Multiplex Control). Selects the function connected to pin GPIOE07/FANTACH2. 0: GPIOE07 port: GPIO (default) 1: FANTACH2: Health Management For correct selection of the GPIO on this pin, also see Table 3 on page 18. TACH1EN (FANTACH1 Multiplex Control). Selects the function connected to pin GPIOE06/FANTACH1. 0: GPIOE06 port: GPIO (default) 1: FANTACH1: Health Management For correct selection of the GPIO on this pin, also see Table 3 on page 18. Reserved. TACH4EN (FANTACH4 Multiplex Control). Selects the function connected to the GPIOE02/FANTACH4 pin. 0: GPIOE02 port: GPIO (default) 1: FANTACH4: Health Management For correct selection of the GPIO on this pin, also see Table 3 on page 18. TACH3EN (FANTACH3 Multiplex Control). Selects the function connected to the GPIOE01/FANTACH3 pin. 0: GPIOE01 port: GPIO (default) 1: FANTACH3: Health Management For correct selection of the GPIO on this pin, also see Table 3 on page 18. GPIO03EN (GPIOE10-GPIOE13 Multiplex Control). Selects the functions connected to pins 113-116. 0: 5V_DDCSDA, 5V_DDCSCL, CC_DDCSDA, CC_DDCSCL: Glue Functions (default) 1: GPIOE10-GPIOE13 ports: GPIO For correct selection of GPIOs on these pins, also see Table 3 on page 18. Winbond Electronics Corp. Advanced PC Product Center

www.national.com Revision1.1 PC8374L 3.7.7 SuperI/O Configuration 3 Register (SIOCF3) Power Well: Varies per bit Location: Index 23h Type: R/W or RO Bit Name PWM3EN PWM2EN PWM1EN Reserved 373COMP SP2EN IREN Reset Power Well VBAT 1. See Sections 2.1 and 2.2 VBAT VBAT VSB3 VBAT VSB3 VSB3 VSB3 Bit PWM3EN (FANPWM3 Multiplex Control). Selects the function connected to the GPIOE05/FANPWM3 pin. 0: GPIOE05 port: GPIO (default) 1: FANPWM3: Health Management For correct selection of this GPIO on this pin, also see Table 3 on page 18. PWM2EN (FANPWM2 Multiplex Control). Selects the function connected to the GPIOE04/FANPWM2 pin. 0: GPIOE04 port: GPIO (default) 1: FANPWM2: Health Management For correct selection of this GPIO on this pin, also see Table 3 on page 18. PWM1EN (FANPWM1 Multiplex Control). Selects the function connected to the GPIOE03/FANPWM1 pin. 0: GPIOE03 port: GPIO (default) 1: FANPWM1: Health Management For correct selection of this GPIO on this pin, also see Table 3 on page 18. 4-3 Reserved. 373COMP (PC87373 Compatibility Mode). Selects Serial Port 2 and InfraRed Port pinout. Signal Name 373COMP Pinout Bit = 0 Bit = 1 RI2 118 119 SIN2 119 121 SOUT2 120 122 DSR2 121 124 RTS2 122 125 CTS2 124 126 DTR_BOUT2 125 127 DCD2 126 128 IRRX 127 120 IRTX 128 118 SP2EN (Serial Port 2 Multiplex Control). Selects either GPIO or Serial Port 2. 0: Selects the following GPIO signals: GPIOE01, GPIOE03, GPO12, GPIOE04, GPO13, GPIOE05 and: — when 373COMP bit = 0: GPIOE00, GPIOE02 — when 373COMP bit = 1: GPIOE06, GPIOE07 1: Selects Serial Port 2 signals For correct selection of GPIOs on these pins, also see Table 3 on page 18. IREN (InfraRed Multiplex Control). Selects InfraRed Port or GPIO. 0: GPIOE02, GPIOE00 (when 373COMP bit is 1) or GPIOE06, GPIOE07 (when 373COMP bit is 0) (default) 1: IRRX, IRTX signals For correct selection of GPIOs on these pins, also see Table 3 on page 18. Winbond Electronics Corp. Advanced PC Product Center

Revision 1.1 www.national.com PC8374L 3.7.8 SuperI/O Configuration 4 Register (SIOCF4) Power Well: VSB3 Location: Index 24h Type: R/W or RO 3.7.9 SuperI/O Configuration 6 Register (SIOCF6) This register provides a fast way to disable one or more modules without having to access the Activate register of each (see Section 3.3.1 on page 48). Power Well: VDD3 Location: Index 26h Type: Varies per bit Bit Name nSWD Reserved nPCIRSTO2 Reserved VddStrap2 Reset Bit nSWD (SingleWire Data Multiplex Control). Selects SWD or GPIO. 0: SWD: Health Management (default) 1: GPIOE00 For correct selection of the GPIO on this pin, also see Table 3 on page 18. Reserved. Must be written with 1 to have GPIO or FANTACH4 functionality on pin 105. Reserved. nPCIRSTO2 (PCI Reset Out 2 Multiplex Control). Selects PCIRST_OUT2 or GPIO. 0: PCIRST_OUT2: Glue Functions (default) 1: GPIOE12 For correct selection of the GPIO on this pin, also see Table 3 on page 18. Note: When using GPIOE12, check that its respective default function fits the system usage of this GPIO. Fail- ing to do so may result in irreversible damage to the chip. 3-1 Reserved. VddStrap2. VddStrap2 strap pin Status. Read-Only bit. The bit holds the sampled VddStrap2 pin value at VDD3 power up. Bit Name LOCKFDS General-Purpose Scratch Reserved SER1DIS SER2DIS PARPDIS FDCDIS Reset Bit Type R/W1S LOCKFDS (Lock Fast Disable Configuration). When set to 1, locks itself, SER1DIS, SER2DIS, PARPDIS and FDCDIS bits in this register and GLOBEN bit in SIOCF1 register by disabling writing to all of these bits. Once set, this bit can be cleared by Hardware reset. 0: R/W bits are enabled for write (default) 1: All bits (except bits 6-5) are RO 6-5 R/W General-Purpose Scratch. Reserved. Winbond Electronics Corp. Advanced PC Product Center

www.national.com Revision1.1 PC8374L

3.7.10 SuperI/O Revision ID Register (SRID)

This register contains the ID number of the specific family member (Chip ID) and the chip revision number (Chip Rev). The PC8374L is identified by the value ‘000’. The Chip Rev is incremented on each revision. Power Well: VSB3 Location: Index 27h Type: RO R/W or RO SER1DIS (Serial Port 1 Disable). When set to 1, forces the Serial Port 1 module to be disabled (and its resources released) regardless of the actual setting of its Activation bit (index 30). 0: Enabled or Disabled, according to Activation bit (default) 1: Disabled R/W or RO SER2DIS (Serial Port 2 Disable). When set to 1, forces the Serial Port 2 with InfraRed Port module to be disabled (and its resources released) regardless of the actual setting of its Activation bit (index 30). 0: Enabled or Disabled, according to Activation bit (default) 1: Disabled R/W or RO PARPDIS (Parallel Port Disable). When set to 1, forces the Parallel Port module to be disabled (and its resources released) regardless of the actual setting of its Activation bit (index 30). 0: Enabled or Disabled, according to Activation bit (default) 1: Disabled R/W or RO FDCDIS (Floppy Disk Controller Disable). When set to 1, forces the Floppy Disk Controller module to be disabled (and its resources released) regardless of the actual setting of its Activation bit (index 30). 0: Enabled or Disabled, according to Activation bit (default) 1: Disabled Bit Name Chip ID Chip Rev Reset X X X X X Bit Chip ID. Identifies a specific device of a family. 4-0 Chip Rev. Identifies the device revision. Bit Type Winbond Electronics Corp. Advanced PC Product Center

Revision 1.1 www.national.com PC8374L

3.7.11 Clock Generator Control Register (CLOCKCF)

Power Well: Varies per bit Location: Index 29h Type: Varies per bit 3.7.12 Health Management SMBus Configuration (HMSMBCF) Register This register may be written only once. All eight bits must be updated in a single write operation, after which the data in the register becomes read-only. The register is reset only by VSB Power-Up reset following battery loss. The write lock is re- leased on any VSB Power-Up reset. Power Well: Location: Index 2Ah Type: R/W or RO Bit Name LOCK Reserved CKVALID Reserved Reset Power Well VSB3 VSB3 VSB3 VSB3 VSB3 VSB3 VSB3 VBAT 1. See Sections 2.1 and 2.2 Bit Type R/W1S LOCK (Lock Enable). When set to 1, locks the configuration register CLOCKCF by disabling writing to all its bits (including to the LOCK bit itself). Once set, this bit can be cleared by Hardware reset. 0: The R/W bits are enabled for write (default) 1: All the bits are RO 6-5 Reserved. RO CKVALID (Valid Clock Generator, Clock Status). Indicates the status of the on-chip Clock Generator and controls the generator output clock signal. The PC8374L modules residing on the 48 MHz clock domain may be enabled (see Section 3.3.1 on page 48) only after this bit is read high (generator clock is valid). 0: On first VDD3 power-up (after VSB3 power-up): Generator output clock frozen (default); On any other VDD3 power-up: only 48 MHz clock domain frozen (default). 1: All generator output clocks active (stable and toggling). 3-0 Reserved. Reserved. Must be written with 1. Bit Name Reserved HM_SMBSADD Reset Bit Reserved. 6-0 HM_SMBSADD (Health Management SMBus Slave Address). Defines the slave address on the HM SMBus for the PC8374L. This address, once programmed by the host, is preserved as long as the V power is active. The 7-bit slave address is used to access the Health Management module of the PC8374L. A non-zero value read from this field indicates that HM_SMBSADD contains a valid slave address. Section 8.4.1 on page 142 VBAT (See Sections 2.1 and 2.2) Winbond Electronics Corp. Advanced PC Product Center

3.8 FLOPPY DISK CONTROLLER (FDC) CONFIGURATION

• FM and MFM modes are supported.
• A logic 1 is returned during LPC I/O read cycles by all register bits reflecting the state of floating (TRI-STATE) FDC pins. Exceptions to standard FDC are:
• Automatic media sense using MSEN0 and MSEN1 signals is not supported.
• DRATE1 is not supported.
• DR1 is not supported.
• MTR1 is not supported. The FDC functional block registers are shown in Section 9.1 on page 192. All of these registers are VDD3 powered. 3.8.2 Logical Device 0 (FDC) Configuration Table 22 lists the configuration registers that affect the FDC. Only the last two registers (F0h and F1h) are described here. See Section 3.2.3 on page 39 for descriptions of the other configuration registers. All of these registers are VDD3 powered.

Table 22. FDC Configuration Register Activate (see Section 3.3.1 on page 48). Base Address MSB register. Bits 7-3 (for A15-11) are read-only, ‘00000’. Base Address LSB register. Bits 2 and 0 (for A2 and A0) are read-only, ‘00’. Interrupt Number and Wake-Up on IRQ Enable register. Interrupt Type. Bit 1 is read/write; other bits are read-only. Report no second DMA assignment. FDC Configuration register (mirror of the register at index F0h).

Revision 1.1 www.national.com PC8374L 3.8.3 FDC Configuration Register This register is reset to 24h. Power Well: VDD3 Location: Indexes F0h and F8h Type: R/W Bit Name Reserved TDR Register Mode DENSEL Polarity Control FDC 2Mbps Enable Write Protect PC-AT or PS/2 Drive Mode Select Reserved TRI-STATE Control Reset Bit Type Reserved. R/W TDR Register Mode. 0: PC-AT-Compatible Drive mode; i.e., bits 7-2 of the TDR are ‘111111’ (default) 1: Enhanced Drive mode R/W DENSEL Polarity Control. 0: Active low for 500 Kbps or 1 or 2 Mbps data rates 1: Active high for 500 Kbps or 1 or 2 Mbps data rates (default) R/W FDC 2Mbps Enable. Is set only when a 2 Mbps drive is used. 0: 2 Mbps disabled and the FDC clock is 24 MHz (default) 1: 2 Mbps enabled and the FDC clock is 48 MHz R/W Write Protect. Enables forcing of write protect functionality by software. When set, writes to the floppy disk drive are disabled. This effect is identical to an active WP signal. 0: Write protected according to WP signal (default) 1: Write protected regardless of value of WP signal R/W PC-AT or PS/2 Drive Mode Select. 0: PS/2 Drive mode 1: PC-AT Drive mode (default) Reserved. R/W TRI-STATE Control. When this bit is set to 1 and the logical device is inactive, the logical device output pins are in TRI-STATE (see Section 3.3.2 on page 48). 0: Normal outputs (default) 1: TRI-STATE outputs when the logical device is inactive Winbond Electronics Corp. Advanced PC Product Center

www.national.com Revision1.1 PC8374L 3.8.4 Drive ID Register This register is reset to 00h. This register controls bits 5 and 4 of the TDR register in Enhanced mode. Power Well: VDD3 Location: Index F1h Type: R/W Usage Hints: Some BIOS implementations support FDDs with automatic media sense; in this case, bit 5 of TDR register in Enhanced mode is interpreted as valid media sense when it is cleared to 0. If drive 0 and/or drive 1 do not support automatic media sense, bits 1 and/or 3 of the Drive ID register must be set to 1 (to indicate non-valid media sense). When Drive 0 or Drive 1 is selected, the Drive ID bit is reflected on bit 5 of TDR register in Enhanced mode. Bit Name Reserved Drive 0 ID Reset Bit Reserved. 1-0 Drive 0 ID. When drive 0 is accessed, these bits are reflected on bits 5-4 of the TDR register, respectively. Winbond Electronics Corp. Advanced PC Product Center

3.9 PARALLEL PORT (PP) CONFIGURATION

• A group of 21 registers at first level offset, sharing 14 entries. Three of these registers (at offsets 403h, 404h and 405h) are used only in Extended ECP mode.
• A group of four registers, used only in Extended ECP mode, is accessed by a second level offset. The desired mode is selected by the ECR runtime register (offset 402h). The selected mode determines which runtime reg- isters are used and which address bits are used for the base address. The Parallel Port functional block registers are shown in Section 9.2 on page 194. All of these registers are VDD3 powered. 3.9.2 Logical Device 1 (PP) Configuration Table 23 lists the configuration registers that affect the Parallel Port. Only the last register (F0h) is described here. See Section 3.2.3 on page 39 for descriptions of the other configuration registers. All of these registers are VDD3 powered.

Table 23. Parallel Port Configuration Registers Activate (see Section 3.3.1 on page 48). mode 4 (EPP) or when using Extended registers, bit 2 (A2) must also be ‘0’. Interrupt Number and Wake-Up on IRQ Enable register.

• Bit 1 is a read/write bit.

cleared (edge interrupt) in all other modes. Report no second DMA assignment. Parallel Port Standard Configuration register. Parallel Port Modified Configuration register.

www.national.com Revision1.1 PC8374L 3.9.3 Parallel Port Standard Configuration Register This register is reset to F2h. Power Well: VDD3 Location: Index F0h Type: R/W Bit Name Parallel Port Mode Select Extended Register Access Reserved Power Mode Control TRI-STATE Control Reset Bit Parallel Port Mode Select. The mode selected by writing to these bits is reflected by bits 3-0 in the Parallel Port Modified Configuration Register (see Section 3.9.4 on page 65). Bits 7 6 5 Mode 0 0 0: SPP-Compatible mode. PD7-0 are always output signals 0 0 1: SPP Extended mode. PD7-0 direction is controlled by software 0 1 0: EPP 1.7 mode 0 1 1: EPP 1.9 mode 1 0 0: ECP mode (IEEE1284 register set), with no support for EPP mode 1 0 1: Reserved 1 1 0: Reserved 1 1 1: ECP mode (IEEE1284 register set), with EPP mode selectable as mode “100” (default) Selection of EPP 1.7 or 1.9 in ECP mode “100” is controlled by bit 4 of the Control2 configuration register of the Parallel Port at offset 02h. Note: Before setting bits 7-5, enable the Parallel Port and set CTR/DCR (at base address + 2) to C4h. Extended Register Access. 0: Registers at base (address) + 403h, base + 404h and base + 405h are not accessible (reads and writes are ignored) 1: Registers at base (address) + 403h, base + 404h and base + 405h are accessible. This option supports runtime configuration within the Parallel Port address space (default). 3-2 Reserved. Power Mode Control. When the logical device is active: 0: Parallel Port clock disabled. ECP modes and EPP time-out are not functional when the logical device is active. Registers are maintained. 1: Parallel Port clock enabled. All operation modes are functional when the logical device is active (default). TRI-STATE Control. When this bit is set to 1 and the logical device is inactive, the logical device output pins are in TRI-STATE (see Section 3.3.2 on page 48). 0: Normal outputs (default) 1: TRI-STATE outputs when the logical device is inactive Winbond Electronics Corp. Advanced PC Product Center

Revision 1.1 www.national.com PC8374L 3.9.4 Parallel Port Modified Configuration Register This register is reset to 07h. Power Well: VDD3 Location: Index F8h Type: R/W Bit Name Reserved Parallel Port Mode Select Reset Bit Reserved. 3-0 Parallel Port Mode Select. The mode selected by writing to these bits is reflected by bits 7-5 in the Parallel Port Standard Configuration Register (see Section 3.9.3 on page 64). Bits 3 2 1 0 Mode 0 0 0 1: SPP Extended mode. PD7-0 direction is controlled by software 0 0 1 0: EPP 1.9 mode 0 1 0 0: ECP mode (IEEE1284 register set), with no support for EPP mode 1 0 0 0: SPP-Compatible mode. PD7-0 are always output signals 0 1 1 1: ECP mode (IEEE1284 register set), with EPP mode selectable as mode “0100” (default) 1 0 1 0: EPP 1.7 mode Other: Reserved (writing a reserved value causes unpredictable behavior of the Parallel Port) Selection of EPP 1.7 or 1.9 in ECP mode “0100” is controlled by bit 4 of Control2 configuration register of the Parallel Port at offset 02h. Note: Before setting bits 3-0, enable the Parallel Port and set CTR/DCR (at base address + 2) to C4h. Winbond Electronics Corp. Advanced PC Product Center

3.10 SERIAL PORT 2 WITH INFRARED CONFIGURATION

3.10.1 General Description

Serial Port 2 provides UART functionality by supporting serial data communication with remote peripheral device or modem. The functional blocks can function as a standard 16450 or 16550 or as an Extended UART. of these registers are VDD3 powered.

3.10.2 Logical Device 2 (SP2) Configuration

Section 3.2.3 on page 39 for descriptions of the other configuration registers. All of these registers are VDD3 powered. Table 24. Serial Port 2 with InfraRed Port Configuration Registers Activate (see Section 3.3.1 on page 48). Base Address MSB register. Bits 7-3 (for A15-11) are read-only, 00000b. Base Address LSB register. Bit 2-0 (for A2-0) are read-only, 000b. Interrupt Number and Wake-Up on IRQ Enable register. Interrupt Type. Bit 1 is R/W; other bits are read-only. DMA Channel Select 0 (RX_DMA). DMA Channel Select 1 (TX_DMA). F0h Serial Port 2 Configuration 1 register.

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3.10.3 Serial Port 2 Configuration 1 Register

This register is reset to 02h. Power Well: VDD Location: Index F0h Type: R/W Bit Name Bank Select Enable Reserved Busy Indicator Power Mode Control TRI-STATE Control Reset Bit Bank Select Enable. Enables bank switching for Serial Port 2. 0: All attempts to access the extended registers in Serial Port 2 are ignored (default) 1: Enables bank switching for Serial Port 2 6-3 Reserved. Busy Indicator. This read-only bit can be used by power management software to decide when to power-down the Serial Port 2 logical device. 0: No transfer in progress (default) 1: Transfer in progress Power Mode Control. The logical device can be active in two modes: 0: Low Power mode: When the logical device is active in Low Power mode, - The Serial Port 2 clock is disabled. - The output signals are set to their default states. - The RI input signal can be programed to generate an interrupt. - Registers are maintained (unlike the activation bit in Index 30h, which also prevents access to Serial Port 2 registers). 1: Normal Power mode: When the logical device is active in Normal Power mode, - Serial Port 2 clock enabled. - Serial Port 2 is functional when the logical device is active (default). TRI-STATE Control. When this bit is set to 1 and the logical device is inactive, the logical device output pins are in TRI-STATE (see Section 3.3.2 on page 48). Exception to this is the IRTX pin, which is driven to 0 when InfraRed is inactive and is not affected by this bit. 0: Normal outputs (default) 1: TRI-STATE outputs when the logical device is inactive Winbond Electronics Corp. Advanced PC Product Center

3.11 SERIAL PORT 1 CONFIGURATION

3.11.1 General Description

dem. The functional blocks can function as a standard 16450 or 16550 or as an Extended UART.

3.11.2 Logical Device 3 (SP1) Configuration

Section 3.2.3 on page 39 for descriptions of the other configuration registers. All of these registers are VDD3 powered. Table 25. Serial Port 1 Configuration Registers Activate (see Section 3.3.1 on page 48). Base Address MSB register. Bits 7-3 (for A15-11) are read-only, ‘00000’. Base Address LSB register. Bits 2-0 (for A2-0) are read-only, ‘000’. Interrupt Number and Wake-Up on IRQ Enable register. Interrupt Type. Bit 1 is R/W; other bits are read-only. F0h Serial Port 1 Configuration register.

Revision 1.1 www.national.com PC8374L

3.11.3 Serial Port 1 Configuration Register

This register is reset to 02h. Power Well: VDD3 Location: Index F0h Type: R/W Bit Name Bank Select Enable Reserved Busy Indicator Power Mode Control TRI-STATE Control Reset Bit Bank Select Enable. Enables bank switching for Serial Port 1. 0: All attempts to access the extended registers in Serial Port 1 are ignored (default) 1: Enables bank switching for Serial Port 1 6-3 Reserved. Busy Indicator. This read-only bit can be used by power management software to decide when to power down the Serial Port 1 logical device. 0: No transfer in progress (default) 1: Transfer in progress Power Mode Control. The logical device can be active in two modes: 0: Low Power mode: When the logical device is active in Low Power mode, - The Serial Port 1 clock is disabled. - The output signals are set to their default states. - The RI input signal can be programed to generate an interrupt. - Registers are maintained (unlike the activation bit in Index 30h, which also prevents access to the Serial Port 1 registers). 1: Normal Power mode: When the logical device is active in Normal Power mode, - Serial Port 1 clock enabled. - Serial Port 1 is functional when the logical device is active (default). TRI-STATE Control. When this bit is set to 1 and the logical device is inactive, the logical device output pins are in TRI-STATE (see Section 3.3.2 on page 48). 0: Normal outputs (default) 1: TRI-STATE outputs when the logical device is inactive Winbond Electronics Corp. Advanced PC Product Center

3.12 SYSTEM WAKE-UP CONTROL (SWC) CONFIGURATION

3.12.1 General Description

Section 4.1 on page 81). Its registers are VSB3 powered.

3.12.2 Logical Device 4 (SWC) Configuration

these registers. All of these registers are VDD3 powered. Table 26. System Wake-Up Control (SWC) Configuration Registers

1. The logical device runtime registers are maintained and all wake-up detection mechanisms are functional.

SWC Base Address MSB register. SWC Base Address LSB register. Bits 3-0 (for A3-0) are read-only, ‘0000’. GPE1_BLK Base Address MSB register. GPE1_BLK Base Address LSB register. Bits 3-0 (for A3-0) are read-only, ‘0000’. Interrupt Type. Bit 1 is read/write. Other bits are read-only.

3.13 KEYBOARD AND MOUSE CONTROLLER (KBC) CONFIGURATION

3.13.1 General Description

tailed technical references for the KBC.

3.13.2 Logical Devices 5 and 6 (Mouse and Keyboard) Configuration

either the Mouse logical device (5) or the Keyboard logical device (6) is activated (by setting the activation bit at index 30h). Configuration register (F0h), which is both VDD3 and VSB3 powered. Table 27. Mouse Configuration Registers Enable register (index 70h) are not asserted. Mouse Interrupt Number and Wake-Up on IRQ Enable register. Mouse Interrupt Type. Bits 1,0 are read/write; other bits are read-only. Table 28. Keyboard Configuration Registers IRQ Enable register (index 70h) are not asserted. Base Address MSB register. Bits 7-3 (for A15-11) are read-only, ‘00000’. Base Address LSB register. Bits 2-0 (for A2-0) are read-only, ‘000’. Command Base Address LSB. Bits 2-0 (for A2-0) are read-only, ‘100’. KBD Interrupt Number and Wake-Up on IRQ Enable register. KBD Interrupt Type. Bits 1,0 are read/write; others are read-only.

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3.13.3 KBC Configuration Register

This register is reset to 40h. Power Well: VDD3 and VSB3 (see Note 1) Location: Index F0h Type: R/W Usage Hints: 1. To change the clock frequency of the KBC: a. Disable the KBC logical devices. b. Change the frequency setting. Enable the KBC logical devices. 2. Before swapping between the Keyboard and Mouse Interface pins, disable the KBC logical devices and their pins. After swapping, the software must issue a synchronization command to the Keyboard and Mouse through the KBC to regain synchronization with these devices. Bit Name KBC Clock Source Reserved SWAP1 1. This bit is powered from the VSB3 well and is reset by VSB3 Power-Up reset. Reserved TRI-STATE Control Reset Bit KBC Clock Source. The clock source can be changed only when the KBC is inactive (disabled). Bits 7 6 Source 0 0:

8 MHz

0 1:

12 MHz (default)

1 0:

16 MHz

1 1: Reserved 5-4 Reserved. SWAP (Swap Keyboard and Mouse Inputs). When this bit is set, the keyboard signals (KBCLK and KBDAT) are swapped with the mouse signals (MCLK and MDAT). This bit is used both by the KBC module and by the Key- board/Mouse Wake-Up Detector in the SWC module. The bit is reset to the default value by VSB3 Power-Up reset only. 0: No swapping (default) 1: Swaps the keyboard and mouse signals 2-1 Reserved. TRI-STATE Control. When this bit is set, the Keyboard pins (KBCLK, KBDAT) and the Mouse pins (MCLK, MDAT) are in TRI-STATE (see Section 3.3.2 on page 48), if both the Keyboard and the Mouse logical devices are inactive. 0: Normal outputs (default) 1: TRI-STATE outputs when the Keyboard and the Mouse logical devices are inactive Winbond Electronics Corp. Advanced PC Product Center

3.14 GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORTS CONFIGURATION

3.14.1 General Description

• Port 0 contains eight GPIOE pins (i.e., GPIO pins with event detection).
• Port 1 contains seven GPIOE pin and one GPIO pin. The two ports (excluding GPIO15) have full event detection capability, enabling them to trigger an IRQ and/or SMI. In addi- tion, through the SWC functional block, they can trigger the SIOPME signal. A configuration option to route GPIOE16 input to GPIOE11 (or GPO11) output is supported. When enabled, GPIOE11 out- puts the data appearing on GPIOE16, ignoring its data output register. For proper operation, GPIOE11 and GPIOE16 need both to be configured correctly. Undefined results otherwise. The runtime registers associated with the ports are arranged in the GPIO address space as shown in Table 29. Each GPIO port with wake-up event detection capability has five runtime registers. The GPIO base address is 32-byte aligned. Address bits 4-0 are used to indicate the register offset. The runtime registers implemented in the PC8374L devices are shown in Table 29. All of these registers are VSB3 powered.

Table 29. Runtime Registers in GPIO Address Space

3.14.2 Logical Device 7 (GPIO) Configuration

registers are powered by VDD3; however, the specific configuration registers are powered by VSB3. Figure 10. Organization of GPIO Pin Registers GPCFG1-2, GPEVR and GPMODE Table 30. GPIO Configuration Register Activate (see Section 3.2.3 on page 39). Base Address LSB register. Bits 4-0 (for A4-0) are read-only, ‘00000’. Interrupt Number and Wake-Up on IRQ Enable register. Interrupt Type. Bit 1 is read/write. Other bits are read-only. GPIO Pin Select register (GPSEL). GPIO Pin Configuration register 1 (GPCFG1). GPIO Pin Event Routing register (GPEVR). GPIO Pin Configuration register 2 (GPCFG2). GPIO Mode Select register (GPMODE).

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3.14.3 GPIO Pin Select Register (GPSEL)

This register selects the GPIO pin (port number and bit number) to be configured (i.e., which register is accessed via the GPIO pin configuration registers). GPSEL is reset to 00h. Power Well: VSB3 Location: Index F0h Type: R/W

3.14.4 GPIO Pin Configuration Register 1 (GPCFG1)

This register reflects, for both read and write, the register currently selected by the GPIO Pin Select register. All of the GPIO pin configuration registers have a common bit structure, as shown below. Power Well: VSB3 Location: Index F1h Type: Varies per bit Ports 0 to 1 (With Wake-Up Event Detection Capability) Bit Name Reserved PORTSEL Reserved PINSEL Reset Bit Reserved. 6-4 PORTSEL (Port Select). Selects the GPIO port to be configured: Bits 6 5 4 Mode 0 0 0: Port 0 (default) 0 0 1: Port 1 010-111: Reserved Reserved. 2-0 PINSEL (Pin Select). Selects the GPIO pin of the selected port to be configured: Bits 2 1 0 Mode 0 0 0: Pin 0 (default) 001-111: Binary value of pin numbers 1-7, respectively Bit Name PDNCTL EVDBNC EVPOL EVTYPE LOCKCFP PUPCTL OUTTYPE OUTENA Reset see Table 31 see Table 31 Bit Type PDNCTL (Pull-Down Control). Controls the internal pull-down resistor of the selected GPIO pin (see Section 6.2 on page 111). 0: Disabled (for default value, see Table 31) 1: Enabled (for default value, see Table 31) Undefined results when both the PDNCTL bit and the PUPCTL bit are set to 1. Winbond Electronics Corp. Advanced PC Product Center

www.national.com Revision1.1 PC8374L Table 31. Reset Values for PUPCTL and PDNCTL Bits selected GPIO pin (see Section 6.3 on page 113). GPIO pin (see Section 6.3 on page 113). in GPDO and GPDIO registers. Once set, this bit can be cleared by Hardware reset. Undefined results when both the PDNCTL bit and the PUPCTL bit are set to 1. Winbond Electronics Corp. Advanced PC Product Center

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3.14.5 GPIO Event Routing Register (GPEVR)

This register reflects, for both read and write, the register currently selected by the GPIO Pin Select register. It enables the routing of the GPIO event (see Section 6.3.2 on page 114) to an IRQ and/or SMI signal. It is implemented for Ports 0 to 1, which have wake-up event detection capability. GPEVR is reset to 00h. Power Well: VSB3 Location: Index F2h Type: R/W or RO

3.14.6 GPIO Pin Configuration Register 2 (GPCFG2)

This register reflects, for both read and write, the register currently selected by the GPIO Pin Select register. It controls the connection of the GPIO pin to a VDD-powered load. Power Well: VSB3 Location: Index F3h Type: R/W or RO Table 32. Reset Values for VDDLOAD Bit Reserved. EV2SMI (Event to SMI Routing). Controls the routing of the event from the selected GPIO pin to SMI (see Section 6.3.2 on page 114). 0: Disabled (default) 1: Enabled EV2IRQ (Event to IRQ Routing). Controls the routing of the event from the selected GPIO pin to IRQ (see Section 6.3.2 on page 114). 0: Disabled (default) 1: Enabled Bit Name Reserved VDDLOAD Reserved Reset see Table 32 Bit Reserved. VDDLOAD (VDD3-Powered Load). Indicates that the selected GPIO pin is connected to a device powered by VDD3. When this bit is 1, the input and output buffers (including the internal pull-up/pull-down) of the selected GPIO pin are disabled whenever VDD3 power to the PC8374L device falls below a certain value (see Section 10.1.5 on page 213). 0: GPIO pin connected to a VSB3-powered load (default): The configuration and data of the GPIO pin are reset by VSB3 Power-Up reset (see Section 2.2 on page 34). 1: GPIO pin connected to a VDD3-powered load: The configuration (excepting the VDDLOAD bit) and data of the GPIO pin are reset by VDD Power-Up reset, Hardware reset or Software reset (see Section 2.2 on page 34). 3-0 Reserved. GP(I)O(E)nn 01-07 11-12 13-17 VDDLOAD Winbond Electronics Corp. Advanced PC Product Center

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3.14.7 GPIO Mode Select Register (GPMODE)

This register controls the operation mode of the GPIO runtime registers (see Section 6.1 on page 110). GPMODE is reset to 01h. It also enables routing of GPIOE16 input to GPIOE11 (or GPO11) output. Power Well: VSB3 Location: Index F8h Type: R/W or RO Bit Name GPIN2GPO Reserved SEPDIO Reset Bit GPIN2GPO. Route GPIOE16 input pin to GPIOE11 (or GPO11) output pin. 0: Routing disabled (default) 1: Routing enabled 6-1 Reserved. SEPDIO (Separate Data I/O Select). Selects the operation mode of the GPIO runtime registers by controlling the GPDO, GPEVEN and GPEVST runtime registers to read-only. 0: Common Data I/O mode (GPDO, GPEVEN and GPEVST registers are read-only, and data written to them is ignored) 1: Separate Data I/O mode (default) Winbond Electronics Corp. Advanced PC Product Center

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3.15 HEALTH MANAGEMENT (HM) CONFIGURATION

3.15.1 General Description

3.15.2 Logical Device 8 (HM) Configuration

Table 33 lists the configuration registers that affect the Health Management Module. See Section 3.2.3 on page 39 for a detailed description of these registers. The standard configuration registers are powered by VDD3; however, the specific con- figuration registers are powered by VSB3.

3.15.3 Health Management Configuration Register 1 (HMCFG1)

This register is reset to 01h. Power Well: Varies per bit Location: Index F0h Type: Varies per bit Note: The FANOUTx_INV bits are configurable via the HM module runtime registers. Table 33. Health Management (HM) Configuration Registers

1. The logical device runtime registers are maintained and all sensor monitoring mechanisms are functional.

HM_LPC Base Address MSB register. HM_LPC Base Address LSB register. Bits 3-0 (for A3-0) are read-only, ‘0000’. Interrupt Type. Bit 1 is read/write. Other bits are read-only. Health Management Configuration register 1 (HMCFG1). R/W1S LOCKHCF (Lock Health Management Configuration). When set to 1, locks the bits of HMCFG1 register (including LOCKHCF bit itself) by disabling writing to them. Once set, this bit can be cleared by Hardware reset. 0: R/W bits are enabled for write (default) 1: All bits are RO Winbond Electronics Corp. Advanced PC Product Center

www.national.com Revision1.1 PC8374L R/W or RO FANOUT2_OTYPE (FANOUT2 Output Type). Controls the output buffer type of the FANPWM3 output. 0: Push-pull (default) 1: Open-drain RO FANOUT2_INV (FANOUT2 Output Invert). When this bit is set to 1, the signal at the FANPWM3 output is inverted. 0: Normal signal (default) 1: Inverted signal R/W or RO FANOUT1_OTYPE (FANOUT1 Output Type). Controls the output buffer type of the FANPWM2 output. 0: Push-pull (default) 1: Open-drain RO FANOUT1_INV (FANOUT1 Output Invert). When this bit is set to 1, the signal at the FANPWM2 output is inverted. 0: Normal signal (default) 1: Inverted signal R/W or RO FANOUT0_OTYPE (FANOUT0 Output Type). Controls the output buffer type of the FANPWM1 output. 0: Push-pull (default) 1: Open-drain RO FANOUT0_INV (FANOUT0 Output Invert). When this bit is set to 1, the signal at the FANPWM1 output is inverted. 0: Normal signal (default) 1: Inverted signal R/W or RO INT_PU_EN (Internal Pull-Up Enable). Controls the internal pull-up resistors on the SWD signal. 0: Disabled 1: Enabled (default) Bit Type Winbond Electronics Corp. Advanced PC Product Center

www.national.com Revision 1.1 PC8374L 4.0 System Wake-Up Control (SWC)

4.1 OVERVIEW

The System Wake-Up Control (SWC) supports the ACPI Specification, Revision 2.0, Feb. 2, 1999. The SWC functional block receives external events from the system; it also receives internal events from the functional blocks of the PC8374L device. Based on these events, the SWC generates the Power Management SCI interrupt (SIOPME) and the system interrupt (IRQ). In addition, it controls two LED indicators. The SWC receives the following external events:

• 15 VSB-powered General-Purpose Input/Output events (GPIOE17-16, GPIOE14-10 and GPIOE07-00).
• Modem Ring events (RI1 and RI2).
• Mouse movement and button pressing events (via MCLK and MDAT).
• Advanced key pressing events from the Keyboard (via KBCLK and KBDAT). The SWC receives the following internal events:
• Keyboard and Mouse interrupt event (IRQ).
• Module interrupt (IRQ) event from the Legacy functional blocks (FDC, Parallel Port, Serial Ports 1 and 2 and InfraRed Port) and Health Management.
• Fan alarm from the Health Management module
• Alarms from the Health Management module The SWC implements the ACPI generic register group (General-Purpose Event 1 group) with “child” events. The SWC generates the Power Management Event signal (the ACPI interrupt, SIOPME) and the system interrupt (IRQ) based on the external and internal events and on the routing information written into the General-Purpose Event 1 register group. The ACPI-compatible SCI interrupt (SIOPME) and the system interrupt (IRQ) are independent of the current sleep state. The SWC receives sleep state information via the SLP_S3 and SLP_S5 pins from an external ACPI controller and receives power supply status information via PWRGD_PS pin from the system power supply. In addition, the SWC controls two LED indicators. The Standard LED Control option is used to provide blinking or constantly lit LEDs. The Advanced LED Control option provides programmable blink based on the current sleep state information or on the status of the VSB3 and VDD3 power supplies. The Special LED Control option provides blinking or constantly lit LEDs, based on the current sleep state information or on the status of the Main Power Supply and on a software controlled bit. The SWC includes the Last Power State Special Power Management function. This function saves the system power state when an AC power failure occurs. The SWC module is powered by the VSB3 and VBAT planes (see Section 2.1.1 on page 32). However, during Power Fail state (i.e., when only VBAT is present), the module functions (event detection, output generation and LEDs control) are dis- abled and only the VBAT-powered Last Power State function is active. Figure 11 shows the simplified block diagram of the SWC functional block. Winbond Electronics Corp. Advanced PC Product Center

4.0 System Wake-Up Control (SWC) (Continued)

Figure 11. SWC Block Diagram

4.2 FUNCTIONAL DESCRIPTION

after the reset but can be disabled by software. The debouncing time is longer than 16 ms. status bit is set when an event of the programed type (edge or level) is detected. plemented in the SWC module (see Figures 12 and 13). (caused by the pin multiplexing switch) from generating a wake-up event.

Figure 12. GPIO Events VSB3, which works independently of the Serial Port 1 or Serial Port 2 modules (powered by VDD3). Section 4.4.6 on page 102). The status bit is cleared only when the software writes 1 to it. dently of the Keyboard Controller module (powered by VDD3). PS2CTL register to the required value (see Section 4.3.8 on page 97). status bit is cleared only when the software writes 1 to it.

www.national.com Revision1.1 PC8374L Keyboard Wake-Up Events Keyboard wake-up events are also detected by the Keyboard/Mouse Wake-Up Detector, which monitors the KBCLK and KBDAT signals. Since the detection mechanisms for keyboard and mouse events are independent, they can be operated simultaneously. Moreover, the Keyboard signals may be swapped with the Mouse signals, by setting SWAP bit in KBC Con- figuration register (see Section 3.13.3 on page 72). The Keyboard/Mouse Wake-Up Detector is powered by VSB3 and works independently of the Keyboard Controller module (powered by VDD3). The keyboard event detection mechanism can be programed to detect:

• Any keystroke (Fast Any-Key or Special Key Sequence modes).
• A specific programmable sequence of up to eight alphanumeric keystrokes (Password mode).
• Any programmable sequence of up to eight bytes of data received from the keyboard (Special Key Sequence mode).
• Up to three programmable Power Management keys concurrently available, each including a sequence of up to three bytes of data received from the keyboard (Power Management Keys mode). The Keyboard/Mouse Wake-Up Detector has four operation modes:
• Fast Any-Key mode
• Password mode
• Special Key Sequence mode
• Power Management Keys mode Up to eight Keyboard Data registers (PS2KEY0-7) are used to define which keyboard data string generates an event. Since the same set of registers is used by three of the four operation modes, only one mode can be selected at a time. For modes involving more than one keystroke, the maximum delay allowed between pressing two consecutive keys is 4 sec- onds. A longer delay is interpreted by the Wake-Up Detector as the beginning of a new sequence of keystrokes, which caus- es the present sequence to be discarded. In all operation modes, pressing a wrong key requires a recovery time of 4 seconds, before a new (correct) sequence may be recognized. Fast Any-Key Mode. In this mode, pressing any key on the keyboard is identified as a keyboard event and, as a result, KBD_ANYK_STS bit in GPE1_STS_2 register is set (see Section 4.4.6 on page 102). The status bit is cleared only when the software writes 1 to it. The key data contained in the PS2KEY0-7 registers is ignored. To program the Keyboard/Mouse Wake-Up Detector to operate in Fast Any-Key mode, set KBDMODE field in KBDWKCTL register to ‘01’ (see Section 4.3.7 on page 96). Password Mode. In this mode, the “Break” bytes transmitted by the keyboard are discarded, and only the “Make” keystroke bytes are compared with those programed in the PS2KEY0-7 registers. If the two sets are identical, a keyboard event that sets KBD_EVT1_STS bit in GPE1_STS_2 register is detected (see Section 4.4.6 on page 102). The status bit is cleared only when the software writes 1 to it. Only keys with a “Make” keystroke data of one byte can be included in the sequence to be detected. To program the Keyboard/Mouse Wake-Up Detector to operate in Password mode: 1. Set KBDMODE field in KBDWKCTL register to ‘00’ (see Section 4.3.7 on page 96). 2. Set KBEVCFG field in PS2CTL register to a value that indicates the desired number of alphanumeric keystrokes in the sequence. The programed value = the number of keystrokes + 7. For example, to detect a sequence of two keys, set KBEVCFG to 09h. 3. Program the appropriate subset of the PS2KEY0-7 registers, in sequential order, with the “Make” data bytes of the keys in the sequence. For example, if there are three keys in the sequence and the “Make” keystroke data of these keys are 05h (first), 50h (second) and 44h (third), program PS2KEY0 to 05h, PS2KEY1 to 50h and PS2KEY2 to 44h (the scan codes are only examples). Special Key Sequence Mode. In this mode, all the bytes transmitted by the keyboard (including “Make” and “Break” bytes) are compared with those programed in the PS2KEY0-7 registers. If the two sets are identical, a keyboard event is detected, as explained in Password Mode, above. Special Key Sequence mode enables the detection of any sequence of keystrokes, including “Shift”, “Alt” and “Ctl” keys. To program the Keyboard/Mouse Wake-Up Detector to operate in Special Key Se- quence mode: 1. Set KBDMODE field in KBDWKCTL register to ‘00’ (see Section 4.3.7 on page 96). 2. Set KBEVCFG field in PS2CTL register to a value that indicates the total number of bytes (“Make” and “Break”) in the se- quence, minus 1 (i.e., the programed value = the number of bytes - 1). For example, to detect a sequence of three received 3. Program the appropriate subset of the PS2KEY0-7 registers, in sequential order, with the data bytes that comprise the sequence. For example, if the number of bytes in the sequence is four, and the values of these bytes are E0h (first), 5Bh (second), E0h (third) and DBh (fourth), program PS2KEY0 to E0h, PS2KEY1 to 5Bh, PS2KEY2 to E0h and PS2KEY3 to DBh (the byte values are only examples). Winbond Electronics Corp. Advanced PC Product Center

Revision 1.1 www.national.com PC8374L Special Key Sequence mode also enables detection of any single keystroke. To program the Keyboard/Mouse Wake-Up Detector to wake-up on any single keystroke: 1. Set KBDMODE field in KBDWKCTL register to ‘00’ (see Section 4.3.7 on page 96). 2. Set KBEVCFG field in PS2CTL register to ‘0001’. 3. Program the PS2KEY0 and PS2KEY1 registers to 00h. This forces the detector to ignore the values of incoming data, thus causing it to detect a keyboard event caused by a single keystroke. Power Management Mode. In this mode, the PS2KEY0-7 register bank is divided into three groups of registers: PS2KEY0-2, PS2KEY3-5 and PS2KEY6-7. Each group can be programed with different data bytes, allowing the bytes trans- mitted by the keyboard to be compared simultaneously with three keystroke sequences. If the bytes transmitted by the key- board (including Make and Break) are identical to the data bytes in one register group, the related keyboard event is detected. The detection of Keyboard Event 1 (data in PS2KEY0-2) sets KBD_EVT1_STS bit; the detection of Keyboard Event 2 (data in PS2KEY3-5) sets KBD_EVT2_STS bit; the detection of Keyboard Event 3 (data in PS2KEY6-7) sets KBD_EVT3_STS bit. All three status bits are in GPE1_STS_2 register (see Section 4.4.6 on page 102). Each status bit is cleared only when the software writes 1 to the bit. This mode enables the detection of any sequence of keys. To program the Keyboard/Mouse Wake-Up Detector to operate in Power Management Keys mode, proceed as follows: 1. Set KBDMODE field in KBDWKCTL register to ‘10’ (see Section 4.3.7 on page 96). 2. Set each event configuration field (EVT1CFG, EVT2CFG and EVT3CFG) in KBDWKCTL register to a value that indi- cates the desired number of keystroke data bytes (“Make” and “Break” bytes) in the sequence, for each event. For ex- ample, to detect a sequence of two received bytes, set EVTxCFG to 02h. 3. Program each group of the PS2KEY0-7 registers, in sequential order, with the data bytes of the keys in the sequence for each event. Event Generation. Keyboard event detection from KBCLK and KBDAT is enabled, for event generation, tEWIV after VSB3 power is on (see “Wake-Up Inputs at VSB3 Power Switching” on page 236). This prevents the detection of false Keyboard events during VSB3 power-On transitions. Usage Hints: 1. After changing the operation mode of the Keyboard/Mouse Wake-Up Detector, clear the KBD_EVT3_STS, KBD_EVT2_STS, KBD_EVT1_STS, and KBD_ANYK_STS status bits in GPE1_STS_2 register (see Section 4.4.6 on page 102). 2. If a byte sequence that is a “subset” of the byte sequence of another (“superset”) Power Management key event is used, the “superset” Power Management key event will never be detected. (The subset sequence has fewer bytes, set by EVTxCFG fields in KBDWKCTL register, than the superset sequence; however, the bytes contained in the subset se- quence, as programed in the PS2KEY0-7 registers, are identical to the respective bytes of the superset sequence.) 4.2.2 Internal Events Keyboard and Mouse IRQ Events Keyboard and Mouse IRQ events are detected when either the Keyboard IRQ or Mouse IRQ is asserted. To enable the IRQ of a logical device to generate an IRQ event, the associated Enable bit (bit 4 of the configuration register at index 70h; see Section 3.2.3 on page 39) must be set to 1. Since the Keyboard Controller (KBC) functional block is pow- ered by VDD3, a Keyboard or Mouse IRQ event can occur only when VDD3 is present. An active (level-type) Keyboard IRQ event sets KBD_IRQ_STS status bit; an active Mouse IRQ event sets MS_IRQ_STS status bit. Both status bits are in GPE1_STS_3 register (see Section 4.4.7 on page 103). A status bit is cleared only when the software writes 1 to it. If the IRQ event is active when software writes 1 to the status bit, the status bit remains set. The ROM code used for the Keyboard Controller generates active high Keyboard and Mouse interrupts, which are used by the SWC module. Module IRQ Event A Module IRQ event is detected when one of the Legacy modules (FDC, Parallel Port, Serial Ports 1 and 2. InfraRed Port), or Health Management module — asserts its IRQ. To enable the IRQ of a logical device to generate an IRQ event, the associated Enable bit (bit 4 of the configuration register at index 70h; see Section 3.2.3 on page 39) must be set to 1. This bit is cleared when VDD3 is not present. MOD_IRQ_STS status bit in GPE1_STS_3 register is set by an IRQ that is asserted by one of the Legacy modules or the Health Management module (see Section 4.4.7 on page 103). The status bit is cleared only when the software writes 1 to it. If the Module IRQ event is active when software writes 1 to the status bit, the bit remains set. When VDD3 is not present, the events from the FDC and Serial Ports 1 and 2 are blocked from the status bit. When VSB3 is not present, the event from the HM module is blocked from the status bit. Winbond Electronics Corp. Advanced PC Product Center

bit is updated only when the software writes 1 to it. the logic levels of the SLP_S3 and SLP_S5 pins. The SCI (SIOPME) pin is the Power Management interrupt defined by ACPI. All external and internal events are exclusively processed by the SWC to generate the Power Management interrupt, SCI. cause the assertion of the SCI interrupt only when PME_EN bit in GPE1_EN register is set (see Section 4.4.3 on page 100). The SCI interrupt is independent of the system sleep state. pin can be configured as either push-pull or open-drain, to allow sharing with external SCI interrupt sources. Figure 13 shows SCI generation. Figure 13. SCI Generation Number register, located at index 70h in the SWC Configuration (see Section 3.12.2 on page 70). Table 34. SLP_S3, SLP_S5 Decoding

two regular LEDs or one dual-color LED. The LEDs can be connected to PC8374L using one of the configurations shown in Figure 14. Figure 14. LED Connection Configurations The LED pins are named GRN_LED (Green LED) and YLW_LED (Yellow LED), although other LED colors can be used.

• Standard LED control: On/Off and Blink controlled by software or by S5 sleep state
• Advanced LED control: On/Off and Blink controlled by software, by S3 or S5 sleep states, or by the VDD3 power sup- ply status
• Special LED control: On/Off and Blink controlled by software, by S3 or S5 sleep states or by the Main power supply status via the PWRGD_PS signal From the base address of the SWC registers, the register for Standard LED Control is located at offset 00h, the two registers for Advanced LED Control are located at offsets 02h and 03h, and the register for Special LED Control is located at offset 02h (see Section 4.3.1 on page 90). The active control registers are selected by LED_OPT field. The blink rate and duty cycle of all LED control options are based on a clock, which is obtained by dividing the frequency of the 32 KHz clock domain. Standard LED Control In this mode, two regular LEDs must be connected to the GRN_LED and the YLW_LED pins, according to configuration “b” (Active High) in Figure 14. In this option, LED operation is controlled by the bits of SLEDCTL register (at offset 00h; see Section 4.3.2 on page 91) and by the SLP_S5 pin. When the system is in sleep state S5 (SLP_S5 = 0), both LEDs are off. GRN_YLW bit selects the active LED (on or blinking) of the two; the other LED is off. BLINK bit selects the operation mode of the active LED as either con- stantly on or blinking at 0.667 Hz with a duty cycle of 41.7% (on time percent of the blink cycle). Table 37 on page 91 shows the states of the GRN_LED and YLW_LED pins. The LEDs are connected according to config- uration “b” (see Figure 14); therefore, a LED is on when the pin is floated and off when the pin is at low level (0). Advanced LED Control In the Advanced LED control option, one dual-color LED or two regular LEDs can be connected to the GRN_LED and the YLW_LED pins, using any of the configurations shown in Figure 14. LEDCFG and LEDPOL bits in ALEDCTL register (at offset 02h; see Section 4.3.4 on page 93) must be set to reflect the connection configuration of the LEDs. LEDCFG bit selects either configurations “a” and “b” (two regular LEDs are connected between each pin and ground or VSUPP) or configuration “c” (one dual-color LED is connected between the GRN_LED and YLW_LED pins). LEDPOL bit se- lects the polarity of the On state at both pins (GRN_LED and YLW_LED). Table 35, shows the value of LEDCFG and LED- POL bits for each LED connection configuration in Figure 14, and also the state of the GRN_LED and YLW_LED pins for which the LED(s) are On. a. Active Low LED VSUP R Pin LED VSUP R Pin LED VSUP R Pin Pin VSUP R b. Active High c. Dual-Color GRN_LED YLW_LED GRN YLW Winbond Electronics Corp. Advanced PC Product Center

• ‘00’ – The behavior of the GRN_LED and YLW_LED pins is controlled solely by software by the setting of the GRNBLNK and YLWBLNK fields.
• ‘01’ – The behavior of the GRN_LED and YLW_LED pins is controlled by the status of the VDD3 supply and by software. In the Power Off state (VDD3 off), the GRN_LED behaves according to the setting of the GRNBLNK field, but the YLW_LED blinks at a 1 Hz rate with a 50% duty cycle; In the Power On state (VDD3 on), each LED behaves according to the setting of its xxxBLNK field.
• ‘10’ – The behavior of the GRN_LED and YLW_LED pins is controlled by the S5 sleep state and by software. In S5 sleep state, both LEDs are off; In S3 - S0 sleep states, each LED behaves according to the setting of its xxxBLNK field.
• ‘11’ – The behavior of the GRN_LED and YLW_LED pins is controlled by the status of the VDD3 supply and by software. In the Power Off state (VDD3 off), both LEDs are off; In Power On state (VDD3 on), each LED behaves according to the setting of its xxxBLNK field. The status of the VDD3 power supply is detected by internal circuits, which identify the Power Off and Power On states (see Section 2.1.2 on page 32). The current system sleep state is decoded from the levels of the SLP_S3 and SLP_S5 pins (see Section 4.2.3 on page 86). Only sleep state S5 is relevant. The GRNBLNK and YLWBLNK fields in LEDBLNK register (at offset 03h; see Section 4.3.6 on page 95) control the On/Off state or the blinking rate of the GRN_LED and YLW_LED pins, respectively. For each LED pin, a different blink rate can be selected. Different blink rates can also be selected for the dual-color LED mode (LEDCFG = 0). Special LED Control Special LED control is the default LED control option. In the Special LED control option, configuration “b” or “c” in Figure 14 can be used. In this option, LED operation is controlled by the bits of XLEDCTL register (at offset 02h; see Section 4.3.5 on page 94) and by the SLP_S3, SLP_S5 and PWRGD_PS pins. When the system is in sleep state S5 (SLP_S5 = 0), both LEDs are off. When the system is in sleep state S3 (SLP_S3 = 0) or S1 (SLP_S1 bit is set), the green LED blinks and the yellow LED is off. The green and yellow LED operation is reversed when the system is in the working state (S0) and the Main power supply is not functional (PWRGD_PS = 0). When the system is in working state (S0) and the Main power supply is within the spec- ified limits, SW_CTL bit selects the active LED (On) of the two, and the other LED is turned off. The blinking rate of the LEDs is 1 Hz with a duty cycle of 50%. Table 39 on page 94 shows the states of the GRN_LED and YLW_LED pins. The LEDs are connected according to config- uration “b” (see Figure 14 on page 87); therefore, a LED is On when the pin is floated; it is Off when the pin is at low level (0).

Table 35. LEDs “On” Polarity as a Function of LEDCFG and LEDPOL

Revision 1.1 www.national.com PC8374L 4.2.6 Special Power Management Functions Last Power State Last Power State function saves the system power state when an AC power failure occurs. When either the VDD3 or VSB3 power supply falls below the minimum limit, the SWC samples the value of the SLP_S3 signal. If SLP_S3 is sampled low, this indicates an orderly shutdown of the Main supply through the S3-S5 sleep states; however, if SLP_S3 is sampled high, this indicates a Power Fail condition, caused either by turning off the mechanical switch (G2 state) or by an AC power failure. The sampled value is powered by the VBAT backup supply, which preserves its value throughout the Power Fail condition when both VDD3 and VSB3 supplies are off (see Section 2.1.2 on page 32) and until AC power returns. When the system exits Power Fail (i.e., when VSB3 power is back on), this read-only bit serves as a snapshot of the system state before the power was turned off. The level of the SLP_S3 signal is sampled in LAST_PWR_STATE read-only bit in SWC_CTL register (see Section 4.3.3 on page 92). In case of a power failure, both VDD and VSB power supplies fall simultaneously. Therefore, the power failure is detected either by VDD3 falling below VDD3OFF, or by VSB3 falling below VSB3OFF, whichever occurs first. The LAST_PWR_STATE bit is reset to 0 at VBAT power-up (see Section 2.2.1 on page 35). Backup Battery Status This function detects the status of the backup battery (VBAT). When the battery voltage is below the specification (VBAT < VBATLOW), GOOD_BAT and LAST_PWR_STATE bits in SWC_CTL register (see Section 4.3.3 on page 92) are reset. In this case, the value of LAST_PWR_STATE bit is incorrect and must be ignored. If the battery voltage is within specified limits (VBAT > VBATLOW), GOOD_BAT bit is set when either the VDD3 or the VSB3 power supply falls below the minimum limit. Winbond Electronics Corp. Advanced PC Product Center

4.3 SWC REGISTERS

60h-61h in the SWC Logical Device configuration.

• R/W = Read/Write. = Read from register (data written to this address is sent to a different register). = Write (see above).
• RO = Read-only.
• WO = Write-only. Reading from the bit returns 0.
• R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.
• R/W1S = Read/Write 1 to Set. Writing 1 to a bit sets its value to 1. Writing 0 has no effect. 4.3.1 SWC Register Map The following table lists the SWC registers. For the SWC register bitmap, see Section 4.5 on page 107. The SWC registers are VSB3 powered.

Table 36. SWC Register Map

1. Selected by LED_OPT field in SWC_CTL register.

Revision 1.1 www.national.com PC8374L 4.3.2 Standard LED Control Register (SLEDCTL) This register configures the standard LED control of the two LEDs connected to pins GRN_LED and YLW_LED of the PC8374L device. It is reset to 03h. Power Well: VSB3 Location: Offset 00h, when LED_OPT = 01 in the SWC_CTL register Type: R/W or RO Bit Name Reserved BLINK GRN_YLW Reset Bit Reserved. BLINK (LEDs Blink Control). Controls the operation mode (either blinking or constantly on) of the LED selected by GRN_YLW bit. Blinking rate is 0.667 Hz with a duty cycle of 41.7%. When the system is in sleep state S5, both LEDs are forced off regardless of BLINK and GRN_YLW bit values; see Table 37. 0: Selected LED blinking 1: Selected LED constantly on (default) GRN_YLW (Green-Yellow LED Select). Selects which of the two LEDs (GRN_LED or YLW_LED) is active. The LED which is not active is off; see Table 37. 0: Yellow LED (connected to YLW_LED pin) selected 1: Green LED (connected to GRN_LED pin) selected (default) Table 37. GRN_LED and YLW_LED States

1. SLP_S5 = 0: System is in sleep state S5.
2. X is either logic “0” or logic “1”.

www.national.com Revision1.1 PC8374L 4.3.3 SWC Miscellaneous Control Register (SWC_CTL) This register contains control and status bits for the SWC module. Its reset value depends on the power well of each bit. Power Well: Varies per bit Location: Offset 01h Type: Varies per bit Bit Name LOCKSCF Reserved GOOD_ BAT Reserved LAST_PWR _STATE LED_OPT Reset Power Well VSB3 VBAT VBAT VBAT Bit Type R/W1S LOCKSCF (Lock SWC Configuration). When set to 1, locks the BLINK and GRN_YLW bits in SLEDCTL register, and all bits of SWC_CTL, ALEDCTL, LEDBLNK, XLEDCTL, KBDWKCTL, PS2CTL and PS2KEY0−7 registers by disabling writing to them (including to the LOCKSCF bit itself). Once set, this bit can be cleared by Hardware reset. 0: R/W bits are enabled for write (default) 1: All bits are RO Reserved. RO GOOD_BAT (Battery Good Status). Indicates the status of the VBAT backup power. The bit is powered by the VBAT backup supply and its value is:

• Reset at any time, if VBAT < VBATLOW
• Set when either VDD3 or VSB3 power supply falls below the minimum limit, if VBAT > VBATLOW When the bit is ‘0’, the value of the LAST_PWR_STATE bit is incorrect and must be ignored. 0: Backup battery low, or not connected (VBAT < VBATLOW) 1: Backup battery good (VBAT > VBATLOW) 4-3 Reserved. RO LAST_PWR_STATE (Last Power State). Samples the value of the SLP_S3 signal when a power failure occurs. It is powered by the VBAT backup supply, thus preserving its value during a Power Fail condition (see Section 2.1.2 on page 32). After the AC power returns, reading from this bit returns the value of the SLP_S3 signal at the time the power failure occurred. The value of this bit must be ignored when GOOD_BAT bit is 0. Writing to this bit is ignored. At VBAT Power-Up reset, LAST_PWR_STATE bit is reset to 0. 0: Orderly system shutdown - Main power off by S3 or S5 sleep states (default) 1: Forced system shutdown - Main power off by Mechanical off (G2 state) or by AC power failure 1-0 R/W or RO LED_OPT (LED Control Option Select). Selects the Advanced, Standard or Special LED control option for the two power LEDs (yellow and green). Bits 1 0 LED Control Option Advanced: LEDs controlled by the ALEDCTL and LEDBLNK registers at offsets 02h and 03h, respectively Standard: LEDs controlled by SLEDCTL register at offset 00h Special: LEDs controlled by XLEDCTL register at offset 02h (default) Reserved Winbond Electronics Corp. Advanced PC Product Center

Revision 1.1 www.national.com PC8374L 4.3.4 Advanced LED Control Register (ALEDCTL) This register configures the advanced LED control of the two LEDs connected to pins GRN_LED and YLW_LED of the PC8374L device. It is reset to 00h. Power Well: VSB3 Location: Offset 02h, when LED_OPT = 00 in the SWC_CTL register Type: R/W or RO Bit Name Reserved LEDCFG LEDPOL Reserved LEDMOD Reset Bit Reserved. LEDCFG (LED Configuration). Enables the use of either two regular LEDs, connected to the GRN_LED and YLW_LED pins or one dual-colored LED, connected between the two pins (see Figure 14 on page 87). 0: One dual-colored LED (default) 1: Two regular LEDs LEDPOL (LED Polarity). Determines the polarity of GRN_LED and YLW_LED outputs. An active output, according to this bit setting, turns the LED on. For the dual-colored LED configuration, changing the polarity reverses the LED colors. The configurations described here apply to the “two regular LEDs” option only; see Table 35 on page 88). 0: Active high: for connection configuration “b” in Figure 14 on page 87 (default) 1: Active low: for connection configuration “a” in Figure 14 on page 87 3-2 Reserved. 1-0 LEDMOD (LED Operation Mode). These bits control the operation mode of GRN_LED and YLW_LED in each power state. Table 38 shows the behavior of the two LED outputs as a function of the system power state. Table 38. GRN_LED and YLW_LED as a Function of the Power State

1. See Section 2.1.2 on page 32.
2. See Section 4.2.3 on page 86.
3. In this table, X is “Irrelevant”.
4. Controlled by the value of GRNBLNK in the LEDBLNK register.
5. Controlled by the value of YLWBLNK in the LEDBLNK register.
6. Blink rate is 1 Hz with a duty cycle of 50%.

www.national.com Revision1.1 PC8374L 4.3.5 Special LED Control Register (XLEDCTL) This register configures the Special LED Control of the two LEDs connected to pins GRN_LED and YLW_LED of the PC8374L device. It is reset to 00h. Power Well: VDD3 Location: Offset 02h, when LED_OPT = 10 in SWC_CTL register Type: R/W or RO Bit Name Reserved SLP_S1 SW_CTL Reset Bit Reserved. SLP_S1 (Sleep State S1 Select). When set to 1 by the software, indicates that the system will enter an S1 sleep state. The value of this bit controls the operation mode of GRN_LED and YLW_LED, as shown in Table 39. 0: System in working state (S0), or in S3-S5 sleep states (default) 1: System in S1 sleep state SW_CTL (Software LEDs Control). Controls the operation mode of GRN_LED and YLW_LED, as shown in Table 39. 0: Normal (default) 1: Bit set by software Table 39. Special control of the GRN_LED and YLW_LED

1. In this table, X is either logic “1” or logic “0”.
2. Blink rate is 1 Hz with a duty cycle of 50%.

Revision 1.1 www.national.com PC8374L 4.3.6 LED Blink Control Register (LEDBLNK) This register controls the advanced blinking rate of the two LEDs connected to pins GRN_LED and YLW_LED of the PC8374L device. It is reset to 70h. Power Well: VSB3 Location: Offset 03h, when LED_OPT = 00 in the SWC_CTL register Type: R/W Bit Name Reserved GRNBLNK Reserved YLWBLNK Reset Bit Reserved. 6-4 GRNBLNK (Green LED Blink Rate). These bits control the blinking rate of GRN_LED output. Bits 6 5 4 Rate (Hz) Duty Cycle 0 0 0: Off Always inactive 0 0 1: 0.25 12.5% 0 1 0: 0.5 25% 0 1 1: 50% 1 0 0: 50% 1 0 1: 50% 1 1 0: 50% 1 1 1: On Always active (default) Reserved. 2-0 YLWBLNK (Yellow LED Blink Rate). These bits control the blinking rate of YLW_LED output. Bits 2 1 0 Rate (Hz) Duty Cycle 0 0 0: Off Always inactive (default) 0 0 1: 0.25 12.5% 0 1 0: 0.5 25% 0 1 1: 50% 1 0 0: 50% 1 0 1: 50% 1 1 0: 50% 1 1 1: On Always active Winbond Electronics Corp. Advanced PC Product Center

www.national.com Revision1.1 PC8374L 4.3.7 Keyboard Wake-Up Control Register (KBDWKCTL) This register configures the keyboard events detected by the Keyboard/Mouse Wake-Up Detector. It is reset to 40h. Power Well: VSB3 Location: Offset 04h Type: R/W or RO Bit Name KBDMODE EVT3CFG EVT2CFG EVT1CFG Reset Bit KBDMODE (Keyboard Mode Select). Selects one of the keyboard wake-up modes for the Keyboard/Mouse Wake-Up Detector. Bits 7 6 Keyboard Wake-Up Mode 0 0: Special Key Sequence or Password: Configured by bits 3-0 of PS2CTL register 0 1: Fast Any-Key: Indicates that any key was pressed on the keyboard (default) 1 0: Power Management Keys: Configured by bits 5-0 of KBDWKCTL register 1 1: Reserved 5-4 EVT3CFG (Keyboard Event 3 Configuration). These bits configure the keyboard data sequence for Keyboard Event 3, which indicates that “PM Key 3” was pressed on the keyboard. The setting of the EVT3CFG field is relevant only if the Keyboard/Mouse Wake-Up Detector is in Power Management Keys mode (KBDMODE = 10). The keyboard data sequence used to detect Keyboard Event 3 is stored in registers PS2KEY6-7, starting with PS2KEY6. Bits 5 4 Sequence Length 0 0: 0 bytes: Keyboard Event 3 disabled (default) 0 1: 1 byte: PS2KEY6 1 0: 2 bytes: PS2KEY6, PS2KEY7 1 1: Reserved 3-2 EVT2CFG (Keyboard Event 2 Configuration). These bits configure the keyboard data sequence for Keyboard Event 2, which indicates that “PM Key 2” was pressed on the keyboard. The setting of the EVT2CFG field is relevant only if the Keyboard/Mouse Wake-Up Detector is in Power Management Keys mode (KBDMODE = 10). The keyboard data sequence used to detect Keyboard Event 2 is stored in registers PS2KEY3-5, starting with PS2KEY3. Bits 3 2 Sequence Length 0 0: 0 bytes: Keyboard Event 2 disabled (default) 0 1: 1 byte: PS2KEY3 1 0: 2 bytes: PS2KEY3, PS2KEY4 1 1: 3 bytes: PS2KEY3, PS2KEY4, PS2KEY5 1-0 EVT1CFG (Keyboard Event 1 Configuration). These bits configure the keyboard data sequence for Keyboard Event 1, which indicates that “PM Key 1” was pressed on the keyboard. The setting of the EVT1CFG field is relevant only if the Keyboard/Mouse Wake-Up Detector is in Power Management Keys mode (KBDMODE = 10). The keyboard data sequence used to detect Keyboard Event 1 is stored in registers PS2KEY0-2, starting with PS2KEY0. Bits 1 0 Sequence Length 0 0: 0 bytes: Keyboard Event 1 disabled (default) 0 1: 1 byte: PS2KEY0 1 0: 2 bytes: PS2KEY0, PS2KEY1 1 1: 3 bytes: PS2KEY0, PS2KEY1, PS2KEY2 Winbond Electronics Corp. Advanced PC Product Center

Revision 1.1 www.national.com PC8374L 4.3.8 PS2 Protocol Control Register (PS2CTL) This register configures the keyboard and mouse events detected by the Keyboard/Mouse Wake-Up Detector. It is reset to 10h. Power Well: VSB3 Location: Offset 05h Type: R/W or RO Bit Name DISPAR MSEVCFG KBEVCFG Reset Bit DISPAR (Disable Parity Check). This controls the parity checking of the keyboard and mouse data by the Keyboard/Mouse Wake-Up Detector. 0: Enable parity check (default) 1: Disable parity check 6-4 MSEVCFG (Mouse Event Configuration). These bits configure the mouse data sequence for the Mouse event. Before setting them to a new value, these bits must be cleared by writing a value of ‘000’. Bits 6 5 4 Event Configuration 0 0 0: Disable mouse wake-up detection 0 0 1: Wake-up on any mouse movement or button click (default) 0 1 0: Wake-up on left button click 0 1 1: Wake-up on left button double-click 1 0 0: Wake-up on right button click 1 0 1: Wake-up on right button double-click 1 1 0: Wake-up on any button single-click (left, right or middle) 1 1 1: Wake-up on any button double-click (left, right or middle) 3-0 KBEVCFG (Keyboard Event Configuration). These bits configure the keyboard data sequence for the Keyboard event indicating that any key or key sequence was pressed on the keyboard. The setting of the KBEVCFG field is relevant only if the Keyboard/Mouse Wake-Up Detector is in either Special Key Sequence or Password mode (KBDMODE = 00). The keyboard data sequence used to detect a Keyboard Event is stored in registers PS2KEY0-7, starting with PS2KEY0. Before setting them to a new value, the KBEVCFG field must be cleared by writing a value of ‘0000’. Bits 3 2 1 0 Event Configuration 0 0 0 0: Disable keyboard wake-up detection (default) 0 0 0 1 to 0 1 1 1 1 0 0 0 to 1 1 1 1 Special Key Sequence mode consisting of from two to eight PS/2 data bytes, “Make” and “Break” codes (including Shift and Alt keys) Password Enabled mode with consisting of from one to eight keys “Make” code (excluding Shift and Alt keys) Winbond Electronics Corp. Advanced PC Product Center

www.national.com Revision1.1 PC8374L 4.3.9 Keyboard Data Shift Register (KDSR) When keyboard wake-up detection is enabled, this register stores the keyboard data shifted in from the keyboard during data transmission. It is reset to 00h. Power Well: VSB3 Location: Offset 06h Type: RO

4.3.10 Mouse Data Shift Register (MDSR)

When mouse wake-up detection is enabled, this register stores the mouse data shifted in from the mouse during data transmission. It is reset to 00h. Power Well: VSB3 Location: Offset 07h (offset in PC8741x = 17h) Type: RO

4.3.11 PS2 Keyboard Key Data 0 to 7 Registers (PS2KEY0-7)

These eight registers (PS2KEY0-7) store the data bytes for Special Key Sequence or Password mode (KBDMODE = 00) or for Power Management Keys mode (KBDMODE = 10) of the Keyboard/Mouse Wake-Up Detector. In Special Key Sequence or in Password modes, the keyboard data is stored as follows:

• PS2KEY0 register stores the data byte for the first key in the sequence.
• PS2KEY1 register stores the data byte for the second key in the sequence.
• PS2KEY2-7 registers store data bytes for the third to eighth key in the sequence. For keyboard data storage in Power Management Keys mode, see Section 4.3.7 on page 96. When one of these registers is set to 00h, it indicates that the value of the corresponding data byte is ignored (i.e., it is not compared with the keyboard data). These registers are reset to 00h. Power Well: VSB3 Location: Offset 08h to 0Fh Type: R/W, RO Bit Name Keyboard Data Reset Bit

Keyboard Data. Bit Name Reserved Mouse Data Reset Bit Reserved. 2-0 Mouse Data. Bit Name Data Byte of Key Reset Bit Data Byte of Key. Winbond Electronics Corp. Advanced PC Product Center

4.4 ACPI REGISTERS

• R/W = Read/Write. = Read from register (data written to this address is sent to a different register). = Write (see above).
• RO = Read-only.
• WO = Write-only. Reading from the bit returns 0.
• R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.
• R/W1S = Read/Write 1 to Set. Writing 1 to a bit sets its value to 1. Writing 0 has no effect. 4.4.1 ACPI Register Map The following table lists the ACPI registers. All of these registers are VSB3 powered.

Table 40. ACPI Register Map

www.national.com 100 Revision1.1 PC8374L 4.4.2 General-Purpose Status 1 Register (GPE1_STS) This register contains the global Power Management Event status bit. This register belongs to the General-Purpose Event 1 register group of the ACPI generic-feature space registers. The status bit behaves according to the Sticky Status Bit definition in the ACPI Specification (i.e., the bit is set when the level of the hardware signal is high and is only cleared by the software writing 1 to it). Power Well: VSB3 Location: Offset 00h Type: R/W1C 4.4.3 General-Purpose Enable 1 Register (GPE1_EN) This register contains the global Power Management Event enable bit. This register belongs to the General-Purpose Event 1 register group of the ACPI generic-feature space registers. It is reset to 00h. The enable bit behaves according to the Enable Bit definition in the ACPI Specification (i.e., the bit can be read or written by software). Power Well: VSB3 Location: Offset 04h Type: R/W Bit Name Reserved PME_STS Reset Bit Reserved. PME_STS (Power Management Event Status). Indicates that an enabled Power Management event has occurred. The bit is set if at least one enabled event (in GPE1_EN_0 to GPE1_EN_3 registers) is active (in GPE1_STS_0 to GPE1_STS_3 registers). The bit can be reset by writing 1 only if all the enabled events are inactive. 0: Inactive (default) 1: At least one enabled “child” event was active since this bit was last cleared Bit Name Reserved PME_EN Reset Bit Reserved. PME_EN (Power Management Event Enable). Controls SCI (SIOPME) generation by a set PME_STS bit. If this bit is set, a set PME_STS bit in GPE1_STS register generates an SCI interrupt. 0: Disable SCI (default) 1: Enable SCI generation by a set PME_STS bit Winbond Electronics Corp. Advanced PC Product Center

Revision 1.1 101 www.national.com PC8374L 4.4.4 General-Purpose Status 1 Register 0 (GPE1_STS_0) This register contains “child” events 0-7 of the GPE1_STS register. The status bits behave according to the Sticky Status Bit definition in the ACPI Specification (i.e., the bit is set when the hardware signal is high and is only cleared by the software writing 1 to it). Power Well: VSB3 Location: Offset 08h Type: R/W1C 4.4.5 General-Purpose Status 1 Register 1 (GPE1_STS_1) This register contains “child” events 8-15 of the GPE1_STS register. The status bits behave according to the Sticky Status Bit definition in the ACPI Specification (i.e., the bit is set when the hardware signal is high and is only cleared by the software writing 1 to it). Power Well: VSB3 Location: Offset 09h Type: R/W1C Bit Name GPIOE07 _STS GPIOE06 _STS GPIOE05 _STS GPIOE04 _STS GPIOE03 _STS GPIOE02 _STS GPIOE01 _STS GPIOE00 _STS Reset Bit GPIOE07_STS (GPIOE07 Event Status). Indicates that an active event has been detected at pin 7 of GPIOE Port 0. The event has programmable polarity and the debounce option (see Section 6.3 on page 113). The bit is set by an active level at the GPIOE07 pin. Writing 1 clears this bit; writing 0 is ignored. 0: Inactive since last cleared (default) 1: An active event has occurred 6-0 GPIOE06_STS to GPIOE00_STS (GPIOE06 to GPIOE00 Event Status). Same as above for pins 6-0 of GPIOE Port 0. Bit Name GPIOE17 _STS GPIOE16_ STS Reserved GPIOE14 _STS GPIOE13 _STS GPIOE12 _STS GPIOE11 _STS GPIOE10 _STS Reset Bit GPIOE17_STS (GPIOE17 Event Status). Indicates that an active event has been detected at pin 7 of GPIOE Port 1. The event has programmable polarity and the debounce option (see Section 6.3 on page 113). The bit is set by an active level at the GPIOE17 pin. Writing 1 clears this bit; writing 0 is ignored. 0: Inactive since last cleared (default) 1: An active event has occurred GPIOE16_STS (GPIOE16 Event Status). Same as above for pin 6 of GPIOE Port 1. Reserved. 4-0 GPIOE14_STS to GPIOE10_STS (GPIOE14 to GPIOE10 Event Status). Same as above for pins 4-0 of GPIOE Port 1. Winbond Electronics Corp. Advanced PC Product Center

www.national.com 102 Revision1.1 PC8374L 4.4.6 General-Purpose Status 1 Register 2 (GPE1_STS_2) This register contains “child” events 16-23 of the GPE1_STS register. The status bits behave according to the Sticky status bit definition in the ACPI Specification (i.e., the bit is set when the level of the hardware signal is high and is only cleared by the software writing 1 to it). Power Well: VSB3 Location: Offset 0Ah Type: R/W1C Bit Name KBD_EVT3 _STS KBD_EVT2 _STS KBD_EVT1 _STS MS_EVT _STS KBD_ANYK _STS RI1_EVT _STS RI2_EVT _STS Reserved Reset Bit KBD_EVT3_STS (Keyboard Event 3 Status). Indicates that “PM Key 3” was pressed and that the event was identified by the Keyboard/Mouse Wake-Up Detector. The bit is set only if the Keyboard/Mouse Wake-Up Detector is in Power Management Keys mode (see Section 4.3.7 on page 96). Writing 1 clears this bit; writing 0 is ignored. 0: Inactive since last cleared (default) 1: The “PM Key 3” key was pressed on the keyboard KBD_EVT2_STS (Keyboard Event 2 Status). Indicates that “PM Key 2” was pressed and that the event was identified by the Keyboard/Mouse Wake-Up Detector. The bit is set only if the Keyboard/Mouse Wake-Up Detector is in Power Management Keys mode (see Section 4.3.7 on page 96). Writing 1 clears this bit; writing 0 is ignored. 0: Inactive since last cleared (default) 1: The “PM Key 2” key was pressed on the keyboard KBD_EVT1_STS (Keyboard Event 1 Status). Indicates that a keyboard event occurred and was identified by the Keyboard/Mouse Wake-Up Detector. The event type depends on the selected operation mode for the

• Pressing any key or a sequence of special keys in Special Key Sequence mode
• Pressing a sequence of keys in Password mode
• Pressing the “PM Key 1” in Power Management Keys mode Writing 1 clears this bit; writing 0 is ignored. 0: Inactive since last cleared (default) 1: A keyboard event occurred MS_EVT_STS (Mouse Event Status). Indicates that a mouse event occurred and was identified by the Keyboard/Mouse Wake-Up Detector (see Section 4.3.8 on page 97). Writing 1 clears this bit; writing 0 is ignored. 0: Inactive since last cleared (default) 1: A mouse event occurred KBD_ANYK_STS (Keyboard Any-Key Status). Indicates that a key was pressed and that the event was identified by the Keyboard/Mouse Wake-Up Detector. The bit is set only if the Keyboard/Mouse Wake-Up Detector is in Fast Any-Key mode (see Section 4.3.7 on page 96). Writing 1 clears this bit; writing 0 is ignored. 0: Inactive since last cleared (default) 1: A keyboard event occurred RI1_EVT_STS (RI1 Event Status). Indicates that a telephone ring signal was received at Serial Port 1 and the event was identified by the RI Wake-Up Detector. The bit is set by a high-to-low transition at the RI1 pin (see Section 4.2.1 on page 82). Writing 1 clears this bit; writing 0 is ignored. 0: Inactive since last cleared (default) 1: A telephone ring signal was received at Serial Port 1 Winbond Electronics Corp. Advanced PC Product Center

Revision 1.1 103 www.national.com PC8374L 4.4.7 General-Purpose Status 1 Register 3 (GPE1_STS_3) This register contains “child” events 24-31 of the GPE1_STS register. The status bits behave according to the Sticky Status Bit definition in the ACPI Specification (i.e., the bit is set when the level of the hardware signal is high and is only cleared by the software writing 1 to it). Power Well: VSB3 Location: Offset 0Bh Type: R/W1C RI2_EVT_STS (RI2 Event Status). Indicates that a telephone ring signal was received at Serial Port 2 and the event was identified by the RI Wake-Up Detector. The bit is set by a high-to-low transition at the RI2 pin (see Section 4.2.1 on page 82). Writing 1 clears this bit; writing 0 is ignored. 0: Inactive since last cleared (default) 1: A telephone ring signal was received at Serial Port 2 Reserved. Bit Name Reserved HM_STS MOD_IRQ _STS MS_IRQ _STS KBD_IRQ _STS Reserved Reset Bit Reserved. HM_STS (HM Alarm Status). Is set if an event enabled for SCI generation was detected by the Health Management module. For the list of events and routing to SWC module (to the HM_STS bit) see “SCI and SMI Events Routing” in the “Events Notification” section. Writing 1 clears this bit; writing 0 is ignored. 0: Inactive since last cleared (default) 1: An enabled event was detected by the Health Management module MOD_IRQ_STS (Modules IRQ Event Status). Indicates that an IRQ was generated by one of the Legacy modules (FDC, Parallel Port, Serial Ports 1 and 2, InfraRed Port), or Health Management module. The bit is set only if the IRQ is enabled for wake-up (bit 4 of the Standard configuration register at index 70h) and the related module is active; see Section 3.2.3 on page 39. Writing 1 clears this bit; writing 0 is ignored. 0: Inactive since last cleared (default) 1: An enabled IRQ (from one of the Legacy or Health Management modules) is active MS_IRQ_STS (Mouse IRQ Event Status). Indicates that an IRQ was generated by the mouse interface section of the KBC module. The bit is set only if the IRQ is enabled for wake-up (bit 4 of the Mouse Logical Device configuration register at index 70h) and the KBC module is active (see Section 3.2.3 on page 39). Writing 1 clears this bit; writing 0 is ignored. 0: Inactive since last cleared (default) 1: An enabled IRQ from the mouse interface section of the KBC module is active KBD_IRQ_STS (Keyboard IRQ Event Status). Indicates that an IRQ was generated by the keyboard interface section of the KBC module. The bit is set only if the IRQ is enabled for wake-up (bit 4 of the Keyboard Logical Device configuration register at index 70h) and the KBC module is active (see Section 3.2.3 on page 39). Writing 1 clears this bit; writing 0 is ignored. 0: Inactive since last cleared (default) 1: An enabled IRQ from the keyboard interface section of the KBC module is active 1-0 Reserved. Bit Winbond Electronics Corp. Advanced PC Product Center

www.national.com 104 Revision1.1 PC8374L 4.4.8 General-Purpose Enable 1 Register 0 (GPE1_EN_0) This register contains “child” events 0-7 of the GPE1_EN register. The enable bits behave according to the Enable Bit definition in the ACPI Specification (i.e., the bit can be read or written by software). Power Well: VSB3 Location: Offset 0Ch Type: R/W 4.4.9 General-Purpose Enable 1 Register 1 (GPE1_EN_1) This register contains “child” events 8-15 of the GPE1_EN register. The enable bits behave according to the Enable Bit definition in the ACPI Specification (i.e., the bit can be read or written by software). Power Well: VSB3 Location: Offset 0Dh Type: R/W Bit Name GPIOE07 _EN GPIOE06 _EN GPIOE05 _EN GPIOE04 _EN GPIOE03 _EN GPIOE02 _EN GPIOE01 _EN GPIOE00 _EN Reset Bit GPIOE07_EN (GPIOE07 Event Enable). Enables an active event at pin 7 of GPIOE Port 0 to set PME_STS bit in GPE1_STS register. 0: Disable event (default) 1: Enable event to set PME_STS 6-0 GPIOE06_EN to GPIOE00_EN (GPIOE06 to GPIOE00 Event Enable). Same as above for pins 6-0 of GPIOE Port 0. Bit Name GPIOE17 _EN GPIOE16 _EN Reserved GPIOE14 _EN GPIOE13 _EN GPIOE12 _EN GPIOE11 _EN GPIOE10 _EN Reset Bit GPIOE17_EN (GPIOE17 Event Enable). Enables an active event at pin 7 of GPIOE Port 1 to set PME_STS bit in GPE1_STS register. 0: Disable event (default) 1: Enable event to set PME_STS GPIOE16_EN (GPIOE16 Event Enable). Same as above for pin 6 of GPIOE Port 1. Reserved. 4-0 GPIOE14_EN to GPIOE10_EN (GPIOE14 to GPIOE10 Event Enable). Same as above for pins 4-0 of GPIOE Port 1. Winbond Electronics Corp. Advanced PC Product Center

Revision 1.1 105 www.national.com PC8374L

4.4.10 General-Purpose Enable 1 Register 2 (GPE1_EN_2)

This register contains “child” events 16-23 of the GPE1_EN register. The enable bits behave according to the Enable Bit definition in the ACPI Specification (i.e., the bit can be read or written by software). Power Well: VSB3 Location: Offset 0Eh Type: R/W Bit Name KBD_EVT3 _EN KBD_EVT2 _EN KBD_EVT1 _EN MS_EVT _EN KBD_ANYK _EN RI1_EVT _EN RI2_EVT _EN Reserved Reset Bit KBD_EVT3_EN (Keyboard Event 3 Enable). Enables the event of pressing “PM Key 3” (on the keyboard) to set PME_STS bit in GPE1_STS register. 0: Disable event (default) 1: Enable event of pressing the “PM Key 3” on the keyboard to set PME_STS KBD_EVT2_EN (Keyboard Event 2 Enable). Enables the event of pressing “PM Key 2” (on the keyboard) to set PME_STS bit in GPE1_STS register. 0: Disable event (default) 1: Enable event of pressing the “PM Key 2” on the keyboard to set PME_STS KBD_EVT1_EN (Keyboard Event 1 Enable). Enables the event of pressing any key, key sequence or “PM Key 1” (on the keyboard) to set PME_STS bit in GPE1_STS register. 0: Disable event (default) 1: Enable event of pressing a sequence of keys or the “PM Key 1” on the keyboard to set PME_STS MS_EVT_EN (Mouse Event Enable). Enables a mouse event identified by the Keyboard/Mouse Wake-Up Detector to set PME_STS bit in GPE1_STS register. 0: Disable event (default) 1: Enable event of mouse event identified by the Keyboard/Mouse Wake-Up Detector to set PME_STS KBD_ANYK_EN (Keyboard Any-Key Enable). Enables the event of pressing any key (on the keyboard) to set PME_STS bit in GPE1_STS register. 0: Disable event (default) 1: Enable event of pressing any key on the keyboard to set PME_STS RI1_EVT_EN (RI1 Event Enable). Enables a telephone ring, received at Serial Port 1 and identified by the RI Wake-Up Detector, to set PME_STS bit in GPE1_STS register. 0: Disable event (default) 1: Enable event of telephone ring event received at Serial Port 1 to set PME_STS RI2_EVT_EN (RI2 Event Enable). Enables a telephone ring, received at Serial Port 2 and identified by the RI Wake-Up Detector, to set PME_STS bit in GPE1_STS register. 0: Disable event (default) 1: Enable event of telephone ring event received at Serial Port 2 to set PME_STS Reserved. Winbond Electronics Corp. Advanced PC Product Center

www.national.com 106 Revision1.1 PC8374L

4.4.11 General-Purpose Enable 1 Register 3 (GPE1_EN_3)

This register contains “child” events 24-31 of the GPE1_EN register. The enable bits behave according to the Enable Bit definition in the ACPI Specification (i.e., the bit can be read or written by software). Power Well: VSB3 Location: Offset 0Fh Type: R/W Bit Name Reserved HM_EN MOD_IRQ _EN MS_IRQ _EN KBD_IRQ _EN Reserved Reset Bit Reserved. HM_EN (HM Alarm Enable). Enables an alarm condition detected by the Health Management (HM) module to set the PME_STS bit in GPE_STS register. 0: Disable event (default) 1: Enable event from an alarm condition detected by the HM module to set PME_STS MOD_IRQ_EN (Modules IRQ Event Enable). Enables an active IRQ from one of the Legacy modules, Health Management module to set the PME_STS bit in GPE_STS register. 0: Disable event (default) 1: Enable event of an active IRQ to set PME_STS MS_IRQ_EN (Mouse IRQ Event Enable). Enables an IRQ generated by the mouse interface section of the KBC module to set the PME_STS bit in GPE_STS register. 0: Disable event (default) 1: Enable event of an IRQ generated by the mouse interface section of the KBC module to set PME_STS KBD_IRQ_EN (Keyboard IRQ Event Enable). Enables an IRQ generated by the keyboard interface section of the KBC module to set the PME_STS bit in GPE_STS register. 0: Disable event (default) 1: Enable event of an IRQ generated by the keyboard interface section of the KBC module to set PME_STS 1-0 Reserved. Winbond Electronics Corp. Advanced PC Product Center

4.5 SYSTEM WAKE-UP CONTROL REGISTER BITMAP

Table 41. SWC Register Map with Base Address at Index 60h, 61h

Table 42. ACPI Register Map with Base Address at Index 62h, 63h

www.national.com Revision 1.1 PC8374L 5.0 LPC Bus Interface With the exception of the Glue Functions, the host can access all the functional blocks of the PC8374L device through the LPC bus.

5.1 OVERVIEW

The LPC host interface supports I/O Read and Write, Memory Read and Write, 8-bit Firmware Memory Read and Write, and 8-bit DMA transactions, as defined in Intel’s LPC Interface Specification, Revision 1.1.

5.2 LPC TRANSACTIONS

The LPC interface of the PC8374L device responds to the following LPC transactions:

• I/O read and write cycles
• Memory read and write cycles
• 8-bit Firmware Memory read and write
• 8-bit DMA read and write cycles
• DMA request

5.3 INTERRUPT SERIALIZER

The Interrupt Serializer translates parallel interrupt request (PIRQ) signals received from internal IRQ sources into serial in- terrupt request data transmitted over the SERIRQ bus. This enables devices that support only parallel IRQs to be integrated into a system that supports only serial IRQs like the LPC bus. Each internal IRQ is fed into a Mapping, Enable and Polarity Control block, which maps the IRQ to its associated IRQ num- bers (see Table 14 on page 41). The resulting IRQs are then fed into the Interrupt Serializer, where they are translated into serial data and then transmitted over the SERIRQ bus. Each interrupt number is assigned a time slot in the SERIRQ frame. Different IRQ sources in the PC8374L device cannot share the same interrupt number and thus cannot share the same time slot in the SERIRQ frame. When a transition is detected on an IRQ source, the new value of the IRQ source is transmitted over the SERIRQ bus during the corresponding IRQ slot. For example, when a transition on the Serial Port IRQ is detected, the new value of the Serial Port IRQ is transmitted during time slot n of the SERIRQ bus. Winbond Electronics Corp. Advanced PC Product Center

This chapter describes one 8-bit port. A device may include a combination of several ports with different implementations. For device specific implementation, see Section 3.14 on page 73.

6.1 OVERVIEW

• Software capability to control and read pin levels.
• Flexible system notification by several means, based on the pin level or level transition.
• Ability to capture and route events and their associated status.
• Back-drive protected pins. GPIO port operation is associated with two sets of registers:
• Pin Configuration registers mapped in the Device Configuration space. These registers are used to configure the logical behavior of each pin. There are two or three registers for each GPIO pin: GPIO Pin Configuration registers 1 and 2 (GPCFG1, GPCFG2) and the GPIO Pin Event Routing register (GPEVR).
• Four 8-bit runtime registers: GPIO Data Out (GPDO), GPIO Data In (GPDI), GPIO Event Enable (GPEVEN) and GPIO Event Status (GPEVST). These registers are mapped in the GPIO device I/O space (which is determined by the base address registers in the GPIO Device Configuration). They are used to control and/or read the pin values and to handle system notification. Each runtime register corresponds to the 8-pin port, such that bit ‘n’ in each one of the four registers is associated with GPIOXn pin, where ‘X’ is the port number.
• An additional optional runtime register: GPIO Data In/Out (GPDIO). This register is also mapped in the GPIO device I/O space, but at a separate location from the above group of four runtime registers. It contains the same data-out value as the GPDO register and the same data-in value as the GPDI register. Each GPIO pin is associated with configuration bits and the corresponding bit slice of the four runtime registers, as shown in Figure 15.

Figure 15. GPIO Port Architecture

8 GPCFG

8 GPEVR

6.0 General-Purpose Input/Output (GPIO) Ports (Continued)

• Basic functionality: Includes configuration of, writing to and reading from the GPIO pins (described in Section 6.2)
• Enhanced functionality: Includes wake-up event detection and system notification (described in Section 6.3) In addition, the GPIO port can be operated in one of the following modes:
• Separate Data I/O: Separate registers are available for Data In (GPDI) and for Data Out (GPDO) in addition to the Data In/Out register (GPDIO) and to the enhanced functionality registers (GPEVST and GPEVEN).
• Common Data I/O: Only the Data In/Out register (GPDIO) is available.

6.2 BASIC FUNCTIONALITY

Figure 16. GPIO Basic Functionality

• Port Direction: Controlled by Output Enable (bit 0).
• Output Type: Push-pull vs. open-drain; it is controlled by Output Buffer Type (bit 1) by enabling/disabling the upper tran- sistor of the output buffer.
• Static Pull-Up: May be added to any type of port (input, open-drain or push-pull). It is controlled by Pull-Up Control (bit 2)
• Pin Lock: GPIO pin may be locked to prevent any changes in the output value and/or the output configuration. The lock is controlled by bit 3. It disables writes to GPDO and GPDIO registers bits, to bits 7, 3−0 of GPCFG1 register (including the Lock bit itself) and to bit 4 of GPCFG2 register. Pin Data Out Data In Output Enable Output Lock Type Static Pull-Up Push-Pull =1 Pull-Up Control Read-only Read/Write (Bit 3) (Bit 2) (Bit 1) (Bit 0) Lock Lock Lock (GPCFG1) LPC Bus Pin (GPDI) (GPDO) Lock VDD-Powered Load (Bit 4) Lock (GPCFG2) No_Vdd GPIO Pin Configuration Registers 1 and 2 Winbond Electronics Corp. Advanced PC Product Center

www.national.com 112 Revision1.1 PC8374L The GPCFG2 register controls the Load Protection configuration option:

• VDD-Powered Load: Disables the Output Buffer (if enabled), the Static Pull-Up (if enabled), the Static Pull-Down (if en- abled) and the Input Buffer if the specific GPIO pin is connected to a VDD-powered device and VDD3 power to the PC8374L is not present (No_Vdd). This function is controlled by the VDD-powered Load bit (bit 4). 6.2.2 Operation If the output is enabled, the value that is written to the GPDO or GPDIO registers is driven to the pin. Reading from the GPDO register returns its contents regardless of the actual pin value or the port configuration. The GPDI register is a read-only register. Reading from the GPDI register returns the actual pin value regardless of its source (the port itself or an external device). Writing to this register is ignored. Reading from the GPDIO register returns the actual pin value regardless of its source. Activation of the GPIO module is controlled by device-specific configuration bits. When this module is inactive, access through the LPC bus to the runtime registers (GPDI, GPDO and GPDIO) is disabled; however, there is no change in the GPDO and GPDIO values and therefore there is no effect on the outputs of the pins. The configuration and data registers of each GPIO pin are reset according to the setting of VDDLOAD bit in GPCFG2 reg- ister (see Section 3.14.6 on page 77). Winbond Electronics Corp. Advanced PC Product Center

6.3 EVENT HANDLING AND SYSTEM NOTIFICATION

detection capability is shown in Figure 17. System notification is described in Section 6.3.2. Figure 17. Event Detection mined behavior of the source pin. The GPCFG1 register determines the event detection trigger type for system notification. signal state is transferred to the event detector only after a debouncing period during which the signal has no transitions. cator (IRQ, SMI, SCI). The debounce is controlled by Event Debounce Enable (bit 6 of GPCFG1 register). tion either from high to low or low to high. A level event may be detected when the source pin is either at high or low level. polarity of the active level (for level) is determined by Event Polarity (bit 5 of GPCFG1 register). of the GPEVEN register setting. Writing 1 to the Status bit clears it to 0. Writing 0 is ignored. the corresponding bit in GPEVEN register is set.

• Interrupt Request (via the Interrupt Serializer in the LPC Bus Interface).
• System Management Interrupt (SMI). The system notification for each GPIO pin is controlled by the corresponding bit in GPEVEN register together with the bits of GPEVR register. System notification by a GPIO pin is enabled if the corresponding bit of GPEVEN register is set to 1. The bits of the GPEVR register select the means of system notification (IRQ, SMI) that the detected GPIO event is routed to. The event routing mechanism is shown in Figure 18.

Figure 18. GPIO Event Routing Mechanism for System Notification The system notification to the target is asserted if at least one GPIO pin is in event pending state. is disabled either when the GPIO functional block is deactivated or when VDD3 power is off. The assertion of SMI is independent of the activation of the GPIO functional block. also recommended to disable the input debouncer. from the GPIO and de-asserted. of the VSB-powered GPIO pins (VDDLOAD = 0) are not affected. status registers are cleared.

6.4 GPIO PORT REGISTERS

• R/W = Read/Write. = Read from register (data written to this address is sent to a different register). = Write (see above).
• RO = Read-only.
• WO = Write-only. Reading from the bit returns 0.
• R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.
• R/W1S = Read/Write 1 to Set. Writing 1 to a bit sets its value to 1. Writing 0 has no effect. 6.4.1 GPIO Pin Configuration Registers Structure For each GPIO Port, there is a group of eight identical sets of configuration registers. Each set is associated with one GPIO pin. The entire group is mapped to the PnP configuration space. The mapping scheme is based on the GPSEL register (see Section 3.14.3 on page 75), which functions as an index register for the pin, and the selected GPCFG1, GPEVR and GPCFG2 registers, which reflect the configuration of the currently selected pin (see Table 43). All of these registers are VSB3 powered. 6.4.2 GPIO Port Runtime Register Map All of these registers are VSB3 powered.

Table 43. GPIO Configuration Registers Table 44. GPIO Port Runtime Register Map

1. See Section 3.14.7 on page 78.
2. The location of this register is defined in Section 3.14.1 on page 73.
3. The data read from this register after reset is undefined.

www.national.com 116 Revision1.1 PC8374L 6.4.3 GPIO Data Out Register (GPDO) Power Well: VSB3 Location: Device specific Type: R/W or RO 6.4.4 GPIO Data In Register (GPDI) Power Well: VSB3 Location: Device specific Type: RO 6.4.5 GPIO Event Enable Register (GPEVEN) Power Well: VSB3 Location: Device specific Type: R/W or RO Bit Name DATAOUT Reset Bit DATAOUT (Data Out). Bits 7-0 correspond to pins 7-0 of the specific Port. The value of each bit determines the value driven on the corresponding GPIO pin when its output buffer is enabled. Writing to the bit latches the written data unless the bit is locked by the GPCFG register Lock bit. Reading the bit returns its value regardless of the pin value and configuration. 0: Corresponding pin driven to low 1: Corresponding pin driven or released (according to buffer type selection) to high (default) Bit Name DATAIN Reset X X X X X X X X Bit DATAIN (Data In). Bits 7-0 correspond to pins 7-0 of the specific Port. Reading each bit returns the value of the corresponding GPIO pin. Pin configuration and the GPDO register value may influence the pin value. Write is ignored. 0: Corresponding pin level low 1: Corresponding pin level high Bit Name EVTENA Reset Bit EVTENA (Event Enable). Bits 7-0 correspond to pins 7-0 of the specific Port. Each bit enables system notification by the corresponding GPIO pin. The bit has no effect on the corresponding Status bit in GPEVST register. 0: Event pending by corresponding GPIO pin masked 1: Event pending by corresponding GPIO pin enabled Winbond Electronics Corp. Advanced PC Product Center

Revision 1.1 117 www.national.com PC8374L 6.4.6 GPIO Event Status Register (GPEVST) Power Well: VSB3 Location: Device specific Type: R/W1C or RO 6.4.7 GPIO Data In/Out Register (GPDIO) Power Well: VSB3 Location: Device specific Type: R/W Bit Name EVTSTAT Reset Bit 7−0 EVTSTAT (Event Status). Bits 7−0 correspond to pins 7−0 of the specific Port. The setting of each bit is independent of the Event Enable bit in GPEVEN register. An active event sets the Status bit, which may be cleared only by software writing 1 to the bit. 0: No active edge or level detected since last cleared 1: Active edge or level detected Bit Name DATAINOUT Reset Write Reset Read X X X X X X X X Bit DATAINOUT (Data In/Out). Bits 7-0 correspond to pins 7-0 of the specific Port. The value of each bit determines the value driven on the corresponding GPIO pin when its output buffer is enabled. Writing to the bit latches the written data unless the bit is locked by the GPCFG register Lock bit. Reading each bit returns the value of the corresponding GPIO pin. Pin configuration and the data-out value may influence the pin value. 0: Corresponding pin driven to low; pin level read low. 1: Corresponding pin driven or released (according to buffer type selection) to high; pin level read high (default). Winbond Electronics Corp. Advanced PC Product Center

This chapter describes the glue functions integrated in the PC8374L device.

7.1 OVERVIEW

• Power-related functions: — Highest active Main supply reference (REF5V) — Highest active Standby supply reference (REF5V_STBY) — Resume reset (RSMRST) — Main power good (PWRGD_3V) — Power distribution control (BKFD_CUT, LATCHED_BF_CUT) — Main power supply control (PS_ON)
• Miscellaneous functions: — Hard-disk LED indicator control (HD_LED)
• SMBus support functions: — SMBus voltage translation (CC_DDCSCL, CC_DDCSDA, 5V_DDCSCL, 5V_DDCSDA) — SMBus isolation (SMB1_SCL, SMB1_SDA, SMB2_SCL, SMB2_SDA) Each function is described in the following sections.

7.2 FUNCTIONAL DESCRIPTION

• One part tracks the VDD3 supply voltage and is implemented in the PC8374L device.
• One part tracks the VDD5 supply voltage and is implemented by an external resistor connected to the VDD5 power supply. Figure 19 shows a simplified diagram of the circuit that generates the REF5V analog output signal

Figure 19. REF5 Generation (Simplified Diagram)

7.0 Glue Functions (Continued)

• If VA > VB, then VDD3 > VDD5; the switch is closed, and the output voltage VREF5V = VDD3.
• If VA < VB, then VDD3 < VDD5; the switch is open, and the output voltage VREF5V = VDD5, through the external 1 KΩ resistor, is connected to the VDD5 power supply. The internal circuit is powered from the VDD3 supply. For VDD3 < VSO, switch “S” is open; therefore, the VREF5V output tracks only the VDD5 supply. Figure 20 shows REF5 output in four cases of VDD3 and VDD5 ramp up and ramp down.

Figure 20. REF5 as a Function of VDD3 and VDD5 “Highest Active Main and Standby Supply Reference” on page 232. Table 45. REF5V DC Characteristics

1. Not tested. Guaranteed by characterization.

• One part tracks the VSB3 supply voltage and is implemented in the PC8374L device.
• One part tracks the VSB5 supply voltage and is implemented by an external resistor connected to the VSB5 power supply. Figure 21 shows a simplified diagram of the circuit that generates the REF5V_STBY analog output signal

Figure 21. REF5_STBY Generation (Simplified Diagram)

• If VA > VB, then VSB3 > VSB5; the switch is closed and the output voltage VREF5V_STBY = VSB3
• If VA < VB, then VSB3 < VSB5; the switch is open and the output voltage VREF5V_STBY= VSB5, through the external 1 KΩresistor, is connected to the VSB5 power supply The internal circuit is powered from the VSB3 supply. For VSB3 < VSO, switch “S” is open; therefore, the VREF5V_STBY output tracks only the VSB5 supply. Figure 22 shows the behavior of the REF5V_STBY output in four cases of VSB3 and VSB5 ramp up and ramp down. VSB5 1 KΩ Pin VSB3 REF5V_STBY A B Comp S 0.1-1 µF PC8374L Winbond Electronics Corp. Advanced PC Product Center

Figure 22. REF5_STBY as a Function of VSB3 and VSB5 see “Highest Active Main and Standby Supply Reference” on page 232. Table 46. REF5V_STBY DC Characteristics

1. Not tested. Guaranteed by characterization.

resume power well (powered by the VSB3 or VSB5 supplies).

• When VSB5 rises above VTRIP, the RSMRST signal switches from low to high after a tRD delay.
• When VSB5 falls below VTRIP, the RSMRST signal switches from high to low after a tFD5 delay.
• When a glitch shorter than tGA (the time VSB5 is below VTRIP) occurs at the VSB5 input, the RSMRST signal is not guaranteed to react (remains high). The Resume Reset circuit is powered by the VSB3 supply. When the VSB5 supply voltage is active, the circuit compares the VSB3 power supply voltage with the threshold value (VSB3ON or VSB3OFF); see Section 10.1.5 on page 213. As a result, the RSMRST active low output signal is generated, as follows:
• When VSB3 rises above VSB3ON, the RSMRST signal switches from low to high after a tRD delay.
• When VSB3 falls below VSB3OFF, the RSMRST signal switches from high to low after a tFD3 delay.
• When a glitch shorter than tGA (the time VSB3 is below VSB3OFF) occurs at the VSB3 input, the RSMRST signal is not guaranteed to react (remains high). When the VSB3 power supply is off, the RSMRST output is at low level (active) having an internal impedance of ZOFF. The delays in RSMRST switching, generated by the Resume Reset circuit, are independent of the toggling of any of the clock domains of the PC8374L device. Figure 23 shows the behavior of the RSMRST output at VSB3 and VSB5 switching.

Figure 23. RSMRST at VSB5 and VSB3 Switching

shows a simplified diagram of the circuit that generates the PWRGD_3V signal. Figure 24. PWRGD_3V Generation (Simplified Diagram) For the AC characteristics, see “Main Power Good” on page 234. This function generates the BKFD_CUT and the LATCHED_BF_CUT power distribution control signals. system is not in one of the S3 to S5 sleep states (SLP_S3 = high).

• Rising edge of BKFD_CUT while the system is not in S5 sleep state (SLP_S5 = high) sets LATCHED_BF_CUT to high.
• Falling edge of BKFD_CUT while the system is not in S5 sleep state (SLP_S5 = high) resets LATCHED_BF_CUT to low.
• When the system is in S5 sleep state (SLP_S5 = low), LATCHED_BF_CUT is reset to low. Figure 25 shows a simplified diagram of the circuit that generates the BKFD_CUT and the LATCHED_BF_CUT signals.

Table 47. Resume Reset Circuit DC Characteristics

1. Not tested. Guaranteed by characterization.

Figure 25. BKFD_CUT and LATCHED_BF_CUT Generation (Simplified Diagram) For the AC characteristics, see “Power Distribution Control” on page 234. This function generates the PS_ON signal, which turns the Main power supply on and off.

• The processor is currently inserted in its socket (CPU_PRESENT = low).
• The system is not in one of the S3 to S5 sleep states (SLP_S3 = high).
• None of the conditions for ETC exists (see Section 8.2.10 on page 139).
• If an ETC event has occurred, the system has gone through one of the S3 to S5 sleep states (rising edge on SLP_S3). Figure 26 shows a simplified diagram of the circuit that generates the PS_ON signal. Figure 26. PS_ON Generation (Simplified Diagram) For the AC characteristics, see “Main Power Supply Control” on page 235. 1 KΩ BKFD_CUT VSB5 Pin Reset (BKFD_CUT) SLP_S5 LATCHED_BF_CUT Pin SLP_S3 PWRGD_PS R-S Flip-Flop Set Q Detector Detector 22 KΩ PS_ON VSB5 Pin SLP_S3 CPU_PRESENT Detector Reset R-S Flip-Flop Set Q ETC event from HM Winbond Electronics Corp. Advanced PC Product Center

Revision 1.1 125 www.national.com PC8374L 7.2.7 Hard-Disk LED Indicator Control This function generates the HD_LED signal, which controls the Hard Drive, red LED indicator. The Hard Drive LED is turned on by an active low HD_LED signal, generated when at least one of the PRIMARY_HD or SECONDARY_HD or SCSI pins is active (low). Figure 27 shows a simplified diagram of the circuit that generates the HD_LED signal. Figure 27. HD_LED Generation (Simplified Diagram) 7.2.8 SMBus Voltage Translation This function performs “passive” level translation between the VDD3-powered (or 2.5V-powered) CC_DDCSCL and CC_DDCSDA signals and the VDD5-powered 5V_DDCSCL and 5V_DDCSDA signals, respectively, for interfacing the Data Display Channel. The signals connected to the CC_DDCSCL, CC_DDCSDA, 5V_DDCSCL and 5V_DDCSDA pins are compatible with Intel's SMBus (Specification Rev 1.1, Dec. 11, 1998) two-wire synchronous serial interface specifications. The CC_DDCSCL and 5V_DDCSCL pins are connected through a switch. This switch is controlled by a Level Translation Control circuit, according to the voltage levels at the CC_DDCSCL and 5V_DDCSCL pins (for the DC characteristics, see Section 10.2.12 on page 216):

• For VIN < VISC at either pin, the switch is closed; therefore, both pins (CC_DDCSCL, and 5V_DDCSCL) are held at low level.
• For VIN > VISO at both pins, the switch is open; therefore, each pin is pulled up to high level by the external resistor connected to VDD3 or VDD25 (2.5V Main Power) (for the CC_DDCSCL pin) and to VDD5 (for the 5V_DDCSCL pin). In addition, when the VDD3 power is off, the switch is open, regardless of the voltage levels at the CC_DDCSCL and 5V_DDCSCL pins. The CC_DDCSDA and 5V_DDCSDA pins are connected through a similar level translation circuit and behave like CC_DDCSCL and 5V_DDCSCL. Figure 28 shows simplified a diagram of the circuit that performs SMBus voltage translation. Figure 28. SMBus Voltage Translation for VDD3 Tolerant Chipset Cluster (Simplified Diagram) 220 Ω HD_LED VDD3 Pin SCSI PRIMARY_HD LED SECONDARY_HD 2.2 KΩ 5V_DDCSnn VDD5 Pin 4.7 KΩ CC_DDCSnn VDD3 or VDD25 Pin Snn = SCL or SDA S Level Control Translation Winbond Electronics Corp. Advanced PC Product Center

ed to Standby power, if the other serial bus is connected to the Main power and the Main power is off. (Specification Rev 1.1, Dec. 11, 1998) two-wire synchronous serial interface specifications.

• For VIN < VISC at either pin, the switch is closed; therefore, both pins (SMB1_SCL, and SMB2_SCL) are held at low level.
• For VIN > VISO at both pins, the switch is open; therefore, each pin is pulled up to high level by the external resistor connected to VSUP1 (for the SMB1_SCL pin) and to VSUP2 (for the SMB2_SCL pin). In addition, when the Main power supply voltage is not valid (PWRGD_PS = low), the switch is forced open and the unpow- ered SMBx_SCL signal is disconnected from the powered SMBx_SCL signal (x is either 1 or 2). This isolation between the two signals prevents the loading of the powered SMBx_SCL signal by the unpowered SMBx_SCL signal. The SMB1_SDA and SMB2_SDA pins are connected through a similar level isolation circuit and behave like SMB1_SCL and SMB2_SCL. Figure 29 shows a simplified diagram of the circuit that performs SMBus isolation.

Figure 29. SMBus Isolation (Simplified Diagram) For the AC characteristics, see “SMBus Voltage Translation and Isolation Timing” on page 235.

www.national.com Revision 1.1 PC8374L 8.0 Health Management (HM)

8.1 OVERVIEW

The PC8374L Health Management module (“HM”) is the digital component of the System Health Monitor and Control func- tion. The analog component of this function is implemented by external LMxx Sensor devices. Communication between the HM and an external LMxx Sensor is automatic (i.e., there is no need for user intervention/configuration) via the SensorPath bus, working in asynchronous mode. The HM monitors three temperature channels, five voltage channels, and four tachometer channels. In addition, it generates three FANPWM fan drive control signals. The temperature data, together with the tachometer data, can be used to control the FANPWM signals. The HM automatically reads temperature and voltage data from an LMxx Sensor device. It then compares the data to the limit data set in the Limit registers and sets the corresponding status bits. Access to the HM is possible through a dedicated SMBus interface (HMSMBus with HMSCL and HMSDA pins) or through the LPC interface. The HM can automatically use one of the following four LMxx device options to supply temperature and voltage inputs: LM96011 provides two temperature channels (one remote diode, one ambient) and five voltage channels LM96011+LM95010 provides three temperature channels (one remote diode, two ambient) and five voltage channels LM96010 provides three temperature channels (two remote diode, one ambient) and five voltage channels LM96012 provides three temperature channels (two remote diode, one ambient) and no voltage channels Note: When the LM96011, LM96010 or LM96012 is used, it should be strapped as device number 1. When the LM95010 is used, it should be strapped as device number 2. Figure 30 on page 128 shows the HM Block Diagram.

8.2 FUNCTIONAL DESCRIPTION

The HM functions are: Sensor Monitoring (voltage channels and temperature channels monitoring) Fan monitoring (fan speed measurements) Fan control (driving fans) 8.2.1 Health Management Module Access The HM can be accessed either through the LPC Bus or through a dedicated SMBus (HMSMBus). For access through the HMSMBus, the HM responds to SMBus transactions addressed according to the SMBus slave ad- dress set by the HM SMBus Configuration register (see Section 3.7.12 on page 59). For the SMBus transaction protocols, see Section 8.3 on page 140. Access through the LPC Bus is done through the HM LPC Access registers. For more details see Section 8.4 on page 141. Simultaneous write accesses through the LPC Bus and SMBus may cause unpredictable results. However, for simultaneous read accesses, consistency is retained (except for the 16-bit measurement data registers, such as Fan Tachometer Reading 1-3 MSB/LSB). 8.2.2 SensorPath Bus The HM communicates with the LMxx Sensor devices via the SensorPath bus. The HM is the bus master on the SensorPath bus and supports asynchronous mode. The SensorPath bus uses timing encoding based on a 360 KHz internal clock to provide the following types of bit signals over the bus (the HM supports all five types): Data Bit 0 Data Bit 1 Start Bit Attention Request Reset Winbond Electronics Corp. Advanced PC Product Center

8.0 Health Management (HM) (Continued)

Figure 30. Health Management Block Diagram

3 Temperature

5 Voltage and

Note 1: The filter is only for Temperature channels.

3 Fan Control

4 Fan Tachometer

the SensorPath bus. Following this, the HM is ready to respond to “attention requests” from an LMxx Sensor device. ingly (see Section 8.2.10 on page 139). request by initiating a read transaction on the SensorPath bus. Status register. The HM checks BER bit in response to each attention request to determine the cause of the request. The HM initiates read/write transactions on the SensorPath bus and supports data fields of up to 32 bits. as a 2’s complement, left-aligned, 8-bit data byte in the Temperature Reading Zone1-3 registers. on the setting of the ZONEn_RANGE bit in the Monitor Control Register (see Section 8.5.54 on page 176). Section 8.5.54 on page 176). The rise time of the filter (0% to 95% of the incoming temperature change) is 673 ms. value of 80h must not be used as a limit value. temperature data exceeds a limit (high, low or critical). Table 48. Temperature Channels per LMxx Device

www.national.com 130 Revision1.1 PC8374L For Low/High Limit: Whenever the temperature data changes state, the associated ZONEn_EV bit in the HM Interrupt Status Register 1 is set (see Section 8.4.4 on page 143). ZONEn_EV can be enabled by the associated ZONEn_EN bit in the HM Interrupt Enable Register 1 (see Section 8.4.6 on page 145) to create an IRQ. ZONEn_EV can also be enabled by the associ- ated xxx_EN bit in the HM SMI/SCI Enable Register 1 (see Section 8.4.13 on page 150) to create an SMI or SCI interrupt. For Critical Limit: Whenever the temperature data changes state, the associated CRITn_EV bit in the HM Interrupt Status Register 3 is set (see Section 8.4.10 on page 149). CRITn_EV can be enabled by the associated CRITn_EN bit in the HM In- terrupt Enable Register 3 (see Section 8.4.11 on page 149) to create an IRQ. CRITn_EV can also be enabled by the associated xxx_EN bit in the HM SMI/SCI Enable Register 3 (see Section 8.4.15 on page 152) to create an SMI or SCI interrupt. A hysteresis of 4°C can be applied to the limit checking by setting the TEMP_HYST bit in the Monitoring Control register (see Section 8.5.54 on page 176) to 1. Each of the Temperature channels can be configured as a “VDD Channel” (see Section 8.5.55 on page 177). Temperature Zone1 is configured by default as a VDD channel. When VDD3 supply is off, all channels that are configured as VDD channels are disabled. Monitoring for these channels is disabled and all the status bits are reset to 0, including the event bits in the with the channel critical limits (CRITn_STS), which are not reset when the VDD3 supply is off. Channels that are configured as VDD channels are enabled 182 ms after the VDD3 supply is turned back on. 8.2.4 Voltage Monitoring Voltage is monitored for five different voltage channels: 2.5V, Vccp (2.25V), 3.3V, 5V and 12V. The voltage data is updated and stored as an unsigned 8-bit value in the Voltage Reading registers. The data represents a relative value. Nominal volt- age value (2.5V for the 2.5V monitoring, 2.25V for Vccp, etc.) is represented by C0h which is 3/4 full-scale (full scale being FFh). The voltage data is compared with configurable low and high limits contained in the Voltage Low Limit and Voltage High Limit registers, respectively. The data format in the limit registers is the same as in the voltage data registers. Whenever the voltage data exceeds a limit, an xxx_ERR status bit is set in Status Register 1 and Status Register 2 (see Section 8.5.23 on page 164 to Section 8.5.24), and an xxx_STS bit in the HM Sensor Status Register 1 and HM Sensor Voltage data is considered to be in a “Good” state when the data does not exceed any limit. A “Fail” state is when the voltage data exceeds a limit. Whenever the voltage data changes state, the associated xxx_EV bit in the HM Interrupt Status Reg- to create an IRQ by the associated xxx_EN bit in the HM Interrupt Enable Register 1 and HM Interrupt Enable Register 2 by the associated xxx_EN bit in the HM SMI/SCI Enable Register 1 and HM SMI/SCI Enable Register 2 (see Section 8.4.13 on page 150 and Section 8.4.14). A hysteresis, which is the value of the Voltage Limit register (High or Low) LSBit multiplied by 4 (see Section 8.5.54 on page 176), can be applied to the limit checking by setting the VOLT_HYST bit in the Monitoring Control register to 1. Each of the Voltage channels can be configured as a “VDD Channel” (see Section 8.5.55 on page 177). Vccp is configured by default as a VDD channel. Whenever VDD3 supply is off, the channels configured as VDD channels are disabled. Monitor- ing for these channels is disabled, and all the status bits are reset to 0, including the event bits in the HM Interrupt Status tween 91 ms and 182 ms after the VDD3 supply is turned back on. 8.2.5 Device Enumeration and HM Channel Association The three enumeration and HM channel association stages are done in the following order: 1. Device enumeration 2. Extended device enumeration 3. HM channel association The ready bit in the configuration register (see Section 8.5.22 on page 163) is set to 0 (not-ready) during all three stages. In any stage, if a SensorPath transaction fails on three successive attempts, the HM assumes a communication error with the LMxx Sensor device occurred and proceeds accordingly (see Section 8.2.10 on page 139). Device Enumeration The HM, after VSB3 power-up but before it is ready to respond to attention requests, performs device enumeration to identify the LMxx Sensor devices currently connected to the SensorPath bus. To enumerate the LMxx Sensor devices, the HM reads the Device Number register first from device number 1 and then from device number 2. Note that a read transaction that returns device number=0h indicates a non-existent device number. If the device enumeration fails to detect any LMxx Sensor device connected to the SensorPath bus, the HM ignores any attention requests generated on the SensorPath bus. Winbond Electronics Corp. Advanced PC Product Center

1. If device number 1 exists, the HM reads the device’s LM Device ID register and compares it to the LM96011 Device ID

value (24h), LM96010 Device ID value (22h) or LM96012 Device ID value (23h). LMxx Sensor device occurred and proceeds accordingly (see Section 8.2.10 on page 139).

1. If device number 2 exists, the HM reads the device’s LM Device ID register and compares it to the LM95010 Device ID

in“HM Channel Association”, below. HM Channels are associated with the LMxx sensors according to Table 49 to Table 51. The appropriate option is determined by the results of the extended device enumeration. Table 49. LMxx Sensor Association with HM Channels for LM96011 or LM96011+LM95010 Table 50. LMxx Sensor Association with HM Channels for LM96010

1. Applicable if the optional LM95010 device exists.

Table 51. LMxx Sensor Association with HM Channels for LM96012 bus. If the LM96011 device is connected, an LM95010 device can also be connected (this is optional). The HM automatically reads the data from the sensors.

• Function 1 is enabled by setting to 1 EnF1 bit in the Device Control Register (location 0101b).
• Function 2 is enabled by setting to 1 EnF2 bit in the Device Control Register (location 0101b).
• Attention request for function number 1 sensors is enabled by setting ATE bit in Temperature Control reg- ister to 1 (location 1010b).
• Temperature sensors SN0 and SN1 are enabled by setting EnS0 and EnS1 in Temperature Control reg- ister to 1 (location 1010b).
• Attention request for function number 2 sensors is enabled by setting ATE bit in Voltage Control register to 1 (location 10010b).
• Voltage sensors SN0, SN1, SN2, SN3 and SN4 are enabled by setting EN0, EN1, EN2, EN3 and EN4 in Voltage Control register to 1 (location 10010b). LM95010:
• Function 1 is enabled by setting to 1 EnF1 bit in the Device Control Register (location 0101b).
• Attention request for function number 1 sensor is enabled by setting ATE bit in Temperature Control reg- ister to 1 (location 1010b).
• Temperature sensors SN0 is enabled by setting EnS0 in Temperature Control register to 1 (location 1010b). LM96010:
• Function 1 is enabled by setting to 1 EnF1 bit in the Device Control Register (location 0101b).
• Function 2 is enabled by setting to 1 EnF2 bit in the Device Control Register (location 0101b).
• Attention request for function number 1 sensors is enabled by setting ATE bit in Temperature Control reg- ister to 1 (location 1010b).
• Temperature sensors SN0, SN1 and SN2 are enabled by setting EnS0, EnS1 and EnS2 in Temperature Control register to 1 (location 1010b).
• Attention request for function number 2 sensors is enabled by setting ATE bit in Voltage Control register to 1 (location 10010b).
• Voltage sensors SN0, SN1, SN2, SN3 and SN4 are enabled by setting EN0, EN1, EN2, EN3 and EN4 in Voltage Control register to 1 (location 10010b). LM96012:
• Function 1 is enabled by setting to 1 EnF1 bit in the Device Control Register (location 0101b).
• Attention request for function number 1 sensors is enabled by setting ATE bit in Temperature Control reg- ister to 1 (location 1010b).
• Temperature sensors SN0, SN1 and SN2 are enabled by setting EnS0, EnS1 and EnS2 in Temperature Control register to 1 (location 1010b). Winbond Electronics Corp. Advanced PC Product Center

Revision 1.1 133 www.national.com PC8374L On each LMxx Sensor device scanned, the HM performs the following operations: 1. Reads the “Device Status Register” (Location: 00100b). SF1-3 bits indicate which function requires “attention”. 2. For each LMxx Sensor device function for which an SFx bit is set, the following occurs: a. HM reads the contents of the Readout register (Location: FuncBase + 001b). b. HM performs temperature sensor processing, as follows: If EF bit in Readout register is 1, the HM sets to 1 the RD_Fault bit in Status Register 2 (see Section 8.5.24 on page 165) and also sets RD_STS in the HM Sensor Status Register 2 (see Section 8.4.9 on page 148) and RD_EV in the HM Interrupt Status Register 2 (see Section 8.4.5 on page 144). In addition, the temperature data is set to 80h and stored in the associated HM channel register. ii. The Readout data is compared with the relevant limits. This step is bypassed if a “sensor error” condition exists. iii. The data is stored in the associated HM channel register. HM performs voltage sensor processing, as follows: The Readout data is compared with the relevant limits. ii. The resulting data is stored in the associated HM channel register. If a “time-out error” (see “Time-Out Function” below) is detected in an HM channel, the following takes place: 1. The HM aborts the current scanning of the sensors. 2. The SensorPath bus is reset. 3. All the LMxx devices are reset (by writing 1 to the Reset bit in each Device Control Register (location 0101b). 4. Device enumeration and HM channel association are performed. 5. SensorPath device setting is performed. 6. Sensor scanning is restarted on receipt of a new attention request. Time-Out Function This function detects either a fatal failure in the LMxx Sensor device or a problem in the SensorPath bus. The maximum time delay (from the previous channel data update) is 728 ms. A new channel data update must occur within this time delay. If a time-out error is detected in device number 1, the HM assumes a communication error with the LMxx Sensor device occurred and proceeds accordingly (see Section 8.2.10 on page 139). 8.2.7 Fan Speed Monitoring Fan speed is monitored for four different tachometer inputs. The tachometer data is updated every 1 sec and stored as an unsigned 16-bit value in the Fan Tachometer Reading registers (two registers for each tachometer). The data represents the number of 11.111 µs periods (90 KHz) between full fan revolutions. To calculate this value to RPM: (speed in RPM) = 60*90000/(tachometer data) The HM support monitoring of fans that produce either two tachometer pulses per full revolution or one pulse per fan revo- lution. Configuration is via the TPPRn bit in the Tachometer Monitoring Control register; see Section 8.5.61 on page 180. The speed measurement can be made in either of two modes: Independent of any FANPWM output. The measurement is performed during either one or two tachometer cycles (a tachometer cycle is the period between two consecutive pulses generated by the Fan), according to TPPRn bit in Ta- chometer Monitoring Control register. The measurement time cannot exceed 1 sec. This mode gives an accurate measurement if the FANPWMn signal does not affect the FANTACHn signal. When an associated FANPWM output is at “On” level. The “On” level of the FANPWM signal can be extended to 1/2, one or two tachometer cycles, according to TPPRn bit in Tachometer Monitoring Control register. The “On” level extension can- not exceed 51.2 ms. This mode gives an accurate measurement even if the FANPWMn signal interferes with the FAN- TACHn signal; however, as the fan accelerates during the “On” level extension, it generates more noise than mode 1. The mode is configured by the FANn_MODE field in the Tach Mode register (see Section 8.5.60 on page 180). The ASSOCn field in the Tach PWM Association register (see Section 8.5.62 on page 181) associates tachometer measurement with a FANPWM output. To prevent false Fans Force-On generation, if a Tachometer measurement is not associated with any FANPWM, set the corresponding field in the Tach PWM Association register to 11b. The tachometer data is compared with a configurable low limit contained in the Fan Tachometer Low Limit registers (two registers for each tachometer input). The data format in the limit registers is the same as in the tachometer data registers. In addition, the tachometer data and the number of tachometer cycles (the number of edges of the FANTACHn signal) de- tected during the measurement time are used to identify a fan stalled condition (see Table 52). Winbond Electronics Corp. Advanced PC Product Center

• Either a fan stalled condition or a low speed condition. (This option is recommended for Manual and Constantly On fan control; see “Control Modes” in Section 8.2.8.)
• A fan stalled condition only. (This is recommended for Automatic fan control if SPIN_END bit in associated Extended FANPWM Control register is set to 0; in this case, the setting of the Fan Tachometer Low Limit register indicates the fan speed at which the spin-up is ended, and not the low limit for the fan speed; see Section 8.5.85 on page 190.) Whenever a fan failure is detected, the FANn_STALL status bit in the Status Register 2 (see Section 8.5.24 on page 165) and the FANn_STS bit in the HM Sensor Status Register 2 (see Section 8.4.9 on page 148) are both set to 1. A state is associated with the fan condition: a “Good” state is when neither condition for fan failure occurs; a “Fail” state is when at least one condition for fan failure occurs. Whenever the fan state changes, the FANn_EV bit in the HM Interrupt Status Reg- ister 2 is set (see Section 8.4.5 on page 144). FANn_EV can be enabled to create an IRQ by the associated FANn_EN bit in the HM Interrupt Enable Register 2 (see Section 8.4.7 on page 146). FANn_EV can also be enabled to create an SMI or SCI interrupt by the associated xxx_EN bit in the HM SMI/SCI Enable Register 2 (see Section 8.4.13 on page 150). All status bits and event flags are cleared and fan speed monitoring is disabled while the VDD3 power supply is off. 8.2.8 Fan Speed Control The HM controls fan speeds by creating three FANPWMn outputs. Each output is a Pulse Width Modulation signal that can be used to drive at least one fan. Fan speed control is active only while the VDD3 power supply is on. Start-Up After VDD Power-Up reset, the FANPWM outputs are kept at 0% duty cycle until one of the following occurs: Two seconds elapse from the time that VDD3 exists. In this case, the fans are set to the value contained in the asso- START bit of the Configuration registers is set (see Section 8.5.22 on page 163). In this case, the FANPWM outputs are controlled according to the FANPWMn Control Configuration registers (see Section 8.5.76 on page 187 to Section 8.5.78). Control Modes Fan speed can be controlled using one of four modes, chosen by the MODE field in the FANPWMn Control Configuration registers (see Section 8.5.76 on page 187 to Section 8.5.78): Disabled - The fan is stopped. Constantly On - The Fan duty cycle is set to the value contained in the associated FANPWMn MAX Duty register. Manual - The Fan speed is set by writing the required duty cycle to the FANPWM ‘n’ Current Duty register; see cycle created by the HM. During spin-up, these registers return either 0 or the target duty cycle (according to the SPIN_DUTY bit in the Extended FANPWM Control 1 register). Automatic - The FANPWM output is controlled by temperature data of one or more temperature zones (the MODE field also selects the temperature zones for each FANPWM output). In Automatic mode: — The HM implements a linear transfer function between the temperature data of the associated zones and the duty cycle of the FANPWM output. The translation between temperature and duty cycle is done in two stages. In the first stage the temperature is translated to unsigned normalized temperature (see Figure 31 on page 135). In the second stage the normalized temperature is translated to a duty cycle value (see Figure 32 on page 135). The use of the normalized temperature is essential if more than one temperature zone supplies temperature information for control- ling the fans.

Table 52. Minimum Equivalent Fan Speed for Fan Failure Conditions

1 PPR

100 RPM

2 PPR

1300 RPM

650 RPM

— If the temperature rises above the low limit, and the FANPWM is at 0% duty cycle, a spin-up process takes place. MAX Duty register (MAX_PWM field). the FANPWM output duty cycle and thus to prevent spurious speed changes of the fans (which cause unpleasant noise). field in Min/Off, Spike Smoothing 1-2 registers (see Section 8.5.74 on page 186). Figure 31. Temperature Normalization Figure 32. Automatic Fan Control Algorithm

www.national.com 136 Revision1.1 PC8374L Fan Force-On Conditions In addition to setting the Constantly On fan mode option via the MODE field in the FANPWMn Control Configuration regis- ters, the duty cycle of each FANPWM output is forced to the value contained in the associated FANPWMn MAX Duty register in one of the following conditions: If the value in one of the temperature zones is above the value in its associated Zone ‘n’ Absolute Temperature Limit. If the FANPWM output is in automatic mode, and a communication error with the device containing the associated temperature zone sensor is detected. If the FANPWM output is in automatic mode and one of the following occurs: — The fan is associated with Temperature Zone1, and a Remote Diode Fault is detected. — The fan is associated with Temperature Zone3, an LM96010 or LM96012 device is used, and a Remote Diode Fault is detected. — The Temperature Reading Zone ‘n’ register of its associated Temperature Zone, holds a value of 80h (temperature measurement error). If a fan failure is detected, and the fan was neither stopped by configuration (i.e., disabled) nor is spinning-up. Note: For fans that are not connected or that do not have a tachometer output, make sure the related FANTACHn input is not associated with any FANPWMn output by setting the respective ASSOCn field in the Tach PWM Association register to ‘11’. Speed Change Modes For each FANPWMn output, in all four modes, the speed changes in one of two ways, as configured by the SPD_CHGn bit in the Extended FANPWM Control Register 2 (see Section 8.5.86 on page 191): Hard speed-change: The FANPWM duty cycle is updated in one immediate step. Soft speed-change: The FANPWM duty cycle is changed in steps of 3.125% duty-cycle until the new duty-cycle is reached. Changes between 0% and the minimum duty cycle (as defined in the FANPWMn Minimum registers) is done in one immediate step (when the fan is stopping or spinning-up). The step duration is determined by the STEP_LEN field in the Extended Control Configuration register. Figures 33 and 34 show a soft speed-change example. There are two ways to end the spin-up process (configured by the SPIN_END bit in the Extended FANPWM Control Con- figuration register: Time: The spin-up process is ended after the time period defined in the SPIN field in the FANPWMn Control Config- uration Register Speed or time: The spin-up process is ended after the time period defined in the SPIN field in the FANPWMn Control Configuration Register or after the fan speed value (in the Fan Tachometer Reading ‘n’ LSB and MSB registers) is either equal to or higher than the value in Fan Tachometer ‘n’ Low Limit LSB and MSB registers, whichever occurs first. Note that the FSTLMD bit in the associated Extended FANPWM Control register (see Section 8.5.85 on page 190) must be set to 1. When the spin-up process ends, the FANPWM duty cycle is set to one of the following values: The value set in FANPWMn Current Duty register, in Manual Fan Control mode The value generated from the current normalized temperature by the automatic algorithm, in Automatic Fan Control mode (this value is updated in the FANPWMn Current Duty register) The value set in FANPWMn MAX Duty register, in Continuously On mode When a speed-change follows the spin-up, the speed-change mode depends on the relation between the duty-cycle at the end of the spin-up (“spin-end DC”) and the current duty-cycle that was generated by the automatic algorithm (PWM_DUTY field): If PWM_DUTY > spin-end DC, either a hard or a soft speed-change (according to the setting of SPD_CHNGn bit in Extended FANPWM Control Register 2) is performed between the values of spin-end DC and PWM_DUTY. If PWM_DUTY < spin-end DC, a hard speed-change (one step) is performed between the values of spin-end DC and PWM_DUTY. Winbond Electronics Corp. Advanced PC Product Center

Figure 33. Soft Spin-Up and Soft Speed-Up Example Figure 34. Soft Slow-Down and Soft Stop Example in the respective FANOUTn_INV bit in the HMCFG1 register (see Section 3.15.3 on page 79), which is read-only.

the SMBus. Reading the register re-enables status bit updating with the current event state. Figure 35. Event Notification for SMBus Device 2 (LM95010) communication changes state between working and not-working (DEV2_EV). Device 1 (LM96011 or LM96010 or LM96012) Remote Diode fault changes state between no-fault and fault (RD_EV). Tachometer inputs change state between fans running and failed (FAN4_EV-FAN1_EV). Temperature zones change state between below and above the critical limit (CRIT3_EV-CRIT1_EV). Temperature zones change state between working within limits and exceeding limits (ZONE3_EV-ZONE1_EV). Note that whenever a state changes these LPC event status bits are set. ter, 12V_EV of HMINT_STS2 register. event status bit. The SMI and SCI are generated via the SWC module.

Figure 36. Event Notification for LPC signal turns off the Main power supply (VDD3) via the PS_ON pin. A communication error with Device 1 (LM96011 or LM96010 or LM96012) occurs. A major SensorPath Bus failure is detected. The ETC is enabled by the ETC_EN bit in the Enhanced Thermal Control Register (see Section 8.5.59 on page 179).

8.2.11 General Configuration

Disable SMBus write access to the HM registers (SMBR bit). Lock some of the configuration registers (LOCK bit). Start command for the monitoring functions and FANPWM control functions (START).

www.national.com 140 Revision1.1 PC8374L When the START bit in Configuration register is 0, sensor monitoring is disabled. However, following VSB3 power-up, and after the READY bit becomes 1, Temperature Zone1 is monitored regardless of the state of the START bit. If the temperature data of Temperature Zone1 is above the default value of the Temperature Critical Limit Zone1 register (+110°C), ETC is asserted turning the Main power supply off. In addition, the CRIT1_ERR bit in Status Register 3 is set to 1. This feature protects the CPU from overheating at VSB3 power-up before the HM is configured by the software for the first time. The LOCK_LIM bit in the Monitoring Control Register (see Section 8.5.54 on page 176) can lock the Limit registers.

8.3 HM SMBUS ACCESS

This section describes the SMBus transactions protocol used by the HM (see also Section 8.2.1 on page 127). 8.3.1 Write Transaction This transaction writes a byte of data to an HM register. The specific register is accessed using an 8-bit offset address. 8.3.2 Read Transaction This transaction reads a byte of data from an HM register. The specific register is accessed using an 8-bit offset address. This transaction is executed in two stages: 1. The master executes an SMBus write transaction, which conveys the Offset Address information to the HM. During this stage, the data is read from the specific register into a read buffer. This stage has no Stop condition. 2. Following a Restart condition, the master executes an SMBus read transaction. During this stage the data is transferred from the read buffer to the master. P Slave Address Offset Address Data (S.A, Write) (OA7-OA0) (Command) S A A A = Start condition = ACK by slave S A = Stop condition P P Slave Address Data (S.A, Write) (Command) S A A N = Start condition = Restart condition S = Stop condition P Slave Address (S.A, Read) R A = ACK by slave A R A = ACK by master N = NACK by master Offset Address Winbond Electronics Corp. Advanced PC Product Center

8.4 HM LPC ACCESS REGISTERS

configuration (see Section 3.15 on page 79). = Write-Only. Reading from the bit returns 0. R/W1C =Read/Write 1 to Clear. Writing 1 to a bit clears it. Writing 0 has no effect.

1. Poll HMSTS.BUSY bit until it is 0.
2. Write the address (index) of the target HM register to HMADDR register.
3. Write the data value to HMDATA register. In response HMSTS.BUSY is set.
4. The transaction is completed when HMSTS.BUSY returns to 0.
5. Poll HMSTS.BUSY bit until it is 0.
6. Write the address (index) of the target HM register to HADDR register.
7. Poll HMSTS.BUSY bit until it is 0.

Table 53. HM LPC Access Registers

www.national.com 142 Revision1.1 PC8374L 8.4.1 HM Address Register (HMADDR) Power Well: VDD3 Location: Offset 00h Type: R/W 8.4.2 HM Data Register (HMDATA) Power Well: VDD3 Location: Offset 01h Type: R/W 8.4.3 HM Status and Command Register (HMSTS) Power Well: VDD3 Location: Offset 02h Type: Varies per bit Bit Name ADDR Reset Bit ADDR. Address of the HM register to be accessed (valid addresses appear in the address column in Table 54 on page 153). An exception are the Status Register 1-3 (addresses 41h, 42h and 73h respectively), which are disabled for access by LPC bus (reserved). Read access to reserved or undefined registers (not a valid address) returns 0. Write access to reserved or undefined registers is ignored. ADDR field can be updated only when the BUSY bit in HMSTS register (see Section 8.4.3 on page 142) is 0; oth- erwise, the transaction will have unpredictable results Bit Name DATA Reset Bit DATA. Data to be read or written from/to the accessed HM register, whose address is ADDR in HMADDR register. Writing to this register automatically triggers the access to the HM register. Writing the DATA field while the BUSY bit in HMSTS register is 1 is ignored; reading the DATA field while the BUSY bit is 1 returns unpredictable data. Bit Name Reserved START_RD BUSY Reset Bit Type Reserved. WO START_RD. Writing 1 to this bit initiates a read access from the HM register with address HMADDR.AD- DR. Writing 1 to START_RD is allowed only when BUSY bit is 0; otherwise, the write can have unpredict- able results. RO BUSY. HM Interface busy. 0: HMDATA register contains valid read data or HM is ready for write access 1: HM is busy Winbond Electronics Corp. Advanced PC Product Center

Revision 1.1 143 www.national.com PC8374L 8.4.4 HM Interrupt Status Register 1 (HMINT_STS1) Event status register 1. Power Well: VSB3 Location: Offset 03h Type: R/W1C Bit Name Reserved ZONE3_EV ZONE2_EV ZONE1_EV 5V_EV 3.3V_EV Vccp_EV 2.5V_EV Reset Bit Reserved. ZONE3_EV. Is set to 1 when a Temperature Zone3 monitoring event occurs. 0: No state change from the last time this bit was cleared (default) 1: Temperature changed state from the last time this bit was cleared ZONE2_EV. Is set to 1 when a Temperature Zone2 monitoring event occurs. 0: No state change from the last time this bit was cleared (default) 1: Temperature changed state from the last time this bit was cleared ZONE1_EV. Is set to 1 when a Temperature Zone1 monitoring event occurs. 0: No state change from the last time this bit was cleared (default) 1: Temperature changed state from the last time this bit was cleared 5V_EV. Is set to 1 when a 5V input voltage monitoring event occurs. 0: No state change from the last time this bit was cleared (default) 1: Voltage changed state from the last time this bit was cleared 3.3V_EV. Is set to 1 when a 3.3V input voltage monitoring event occurs. 0: No state change from the last time this bit was cleared (default) 1: Voltage changed state from the last time this bit was cleared Vccp_EV. Is set to 1 when a Vccp input voltage monitoring event occurs. 0: No state change from the last time this bit was cleared (default) 1: Voltage changed state from the last time this bit was cleared 2.5V_EV. Is set to 1 when a 2.5V input voltage monitoring event occurs. 0: No state change from the last time this bit was cleared (default) 1: Voltage changed state from the last time this bit was cleared Winbond Electronics Corp. Advanced PC Product Center

www.national.com 144 Revision1.1 PC8374L 8.4.5 HM Interrupt Status Register 2 (HMINT_STS2) Event status register 2. Power Well: VSB3 Location: Offset 04h Type: R/W1C Bit Name DEV2_EV RD_EV FAN4_EV FAN3_EV FAN2_EV FAN1_EV DEV1_EV 12V_EV Reset Bit DEV2_EV (Device 2 Event). Is set to 1 when a communication event with the optional LM95010 device occurs. 0: No communication event occurred since the last time this bit was cleared (default) 1: Communication event occurred RD_EV (Remote Diode Event). Is set to 1 when a physical connection event on one of the Remote Diodes of the Temperature Zones occurs (For LM96011: Zone1; for LM96010 or LM96012: Zone1 or Zone3). 0: No Remote Diode event occurred since the last time this bit was cleared (default) 1: Remote Diode physical connection event occurred FAN4_EV. Is set to 1 when a Fan Tachometer Reading 4 monitoring event occurs. 0: No fan state change from the last time this bit was cleared (default) 1: Fan changed state from the last time this bit was cleared FAN3_EV. Is set to 1 when a Fan Tachometer Reading 3 monitoring event occurs. 0: No fan state change from the last time this bit was cleared (default) 1: Fan changed state from the last time this bit was cleared FAN2_EV. Is set to 1 when a Fan Tachometer Reading 2 monitoring event occurs. 0: No fan state change from the last time this bit was cleared (default) 1: Fan changed state from the last time this bit was cleared FAN1_EV. Is set to 1 when a Fan Tachometer Reading 1 monitoring event occurs. 0: No fan state change from the last time this bit was cleared (default) 1: Fan changed state from the last time this bit was cleared DEV1_EV (Device 1 Event). Is set to 1 when a communication event with the LM96011, LM96010 or LM96012 occurs. 0: No communication event occurred since the last time this bit was cleared (default) 1: Communication event occurred 12V_EV. Is set to 1 when a 12V input voltage monitoring event occurs. 0: No state change from the last time this bit was cleared (default) 1: Voltage changed state from the last time this bit was cleared Winbond Electronics Corp. Advanced PC Product Center

Revision 1.1 145 www.national.com PC8374L 8.4.6 HM Interrupt Enable Register 1 (HMINT_EN1) Interrupt enable register 1. Power Well: VDD3 Location: Offset 05h Type: R/W Bit Name Reserved ZONE3_EN ZONE2_EN ZONE1_EN 5V_EN 3.3V_EN Vccp_EN 2.5V_EN Reset Bit Reserved. ZONE3_EN. When set to 1, enables IRQ generation on setting of ZONE3_EV of HMINT_STS1 register. Disable IRQ (default) 1: Enable IRQ ZONE2_EN. When set to 1, enables IRQ generation on setting of ZONE2_EV of HMINT_STS1 register. 0: Disable IRQ (default) 1: Enable IRQ ZONE1_EN. When set to 1, enables IRQ generation on setting of ZONE1_EV of HMINT_STS1 register. 0: Disable IRQ (default) 1: Enable IRQ 5V_EN. When set to 1, enables IRQ generation on setting of 5V_EV of HMINT_STS1 register. 0: Disable IRQ (default) 1: Enable IRQ 3.3V_EN. When set to 1, enables IRQ generation on setting of 3.3V_EV of HMINT_STS1 register. 0: Disable IRQ (default) 1: Enable IRQ Vccp_EN. When set to 1, enables IRQ generation on setting of Vccp_EV of HMINT_STS1 register. 0: Disable IRQ (default) 1: Enable IRQ 2.5V_EN. When set to 1, enables IRQ generation on setting of 2.5V_EV of HMINT_STS1 register. 0: Disable IRQ (default) 1: Enable IRQ Winbond Electronics Corp. Advanced PC Product Center

www.national.com 146 Revision1.1 PC8374L 8.4.7 HM Interrupt Enable Register 2 (HMINT_EN2) Interrupt enable register 2. Power Well: VDD3 Location: Offset 06h Type: R/W Bit Name DEV2_EN RD_EN FAN4_EN FAN3_EN FAN2_EN FAN1_En DEV1_EN 12V_EN Reset Bit DEV2_EN. When set to 1, enables IRQ generation on setting of DEV2_EV of HMINT_STS2 register. 0: Disable IRQ (default) 1: Enable IRQ RD_EN. When set to 1, enables IRQ generation on setting of RD_EV of HMINT_STS2 register. 0: Disable IRQ (default) 1: Enable IRQ FAN4_EN. When set to 1, enables IRQ generation on setting of FAN4_EV of HMINT_STS2 register. 0: Disable IRQ (default) 1: Enable IRQ FAN3_EN. When set to 1, enables IRQ generation on setting of FAN3_EV of HMINT_STS2 register. 0: Disable IRQ (default) 1: Enable IRQ FAN2_EN. When set to 1, enables IRQ generation on setting of FAN2_EV of HMINT_STS2 register. 0: Disable IRQ (default) 1: Enable IRQ FAN1_EN. When set to 1, enables IRQ generation on setting of FAN1_EV of HMINT_STS2 register. 0: Disable IRQ (default) 1: Enable IRQ DEV1_EN. When set to 1, enables IRQ generation on setting of DEV1_EV of HMINT_STS2 register. 0: Disable IRQ (default) 1: Enable IRQ 12V_EN. When set to 1, enables IRQ generation on setting of 12V_EV of HMINT_STS2 register. 0: Disable IRQ (default) 1: Enable IRQ Winbond Electronics Corp. Advanced PC Product Center

Revision 1.1 147 www.national.com PC8374L 8.4.8 HM Sensor Status Register 1 (HMSENS_STS1) Sensor status register 1. Note: All status bits in this register are reset when START bit of the Configuration register is reset. Power Well: VSB3 Location: Offset 07h Type: RO Bit Name Reserved ZONE3_STS ZONE2_STS ZONE1_STS 5V_STS 3.3V_STS Vccp_STS 2.5V_STS Reset Bit Reserved. ZONE3_STS. Is set to 1 when the temperature of Temperature Zone3 exceeds the limits. 0: Temperature does not exceed any respective limit (default) 1: Temperature exceeds a respective limit ZONE2_STS. Is set to 1 when the temperature of Temperature Zone2 exceeds the limits. 0: Temperature does not exceed any respective limit (default) 1: Temperature exceeds a respective limit ZONE1_STS. Is set to 1 when the temperature of Temperature Zone1 exceeds the limits. 0: Temperature does not exceed any respective limit (default) 1: Temperature exceeds a respective limit 5V_STS. Is set to 1 when 5V input voltage exceeds the limits. 0: Voltage does not exceed any respective limit (default) 1: Voltage exceeds a respective limit 3.3V_STS. Is set to 1 when 3.3V input voltage exceeds the limits. 0: Voltage does not exceed any respective limit (default) 1: Voltage exceeds a respective limit Vccp_STS. Is set to 1 when Vccp input voltage exceeds the limits. 0: Voltage does not exceed any respective limit (default) 1: Voltage exceeds a respective limit 2.5V_STS. Is set to 1 when 2.5V input voltage exceeds the limits. 0: Voltage does not exceed any respective limit (default) 1: Voltage exceeds a respective limit Winbond Electronics Corp. Advanced PC Product Center

www.national.com 148 Revision1.1 PC8374L 8.4.9 HM Sensor Status Register 2 (HMSENS_STS2) Sensor status register 2. Note: All status bits in this register are reset when START bit of the Configuration register is reset. Power Well: VSB3 Location: Offset 08h Type: RO Bit Name DEV2_STS RD_STS FAN4_STS FAN3_STS FAN2_STS FAN1_STS DEV1_STS 12V_STS Reset Bit DEV2_STS. Is set to 1 when a communication problem with the optional LM95010 device exists. 0: The optional LM95010 device does not exist or exists with valid communication (default) 1: A communication problem with LM95010 RD_STS. Is set to 1 when there is a physical connection fault in one of the Remote Diodes of the Temperature Zones occur (for LM96011: Zone1; for LM96010 or LM96012: Zone1 or Zone3). 0: Proper connection of Remote Diode (default) 1: Remote Diode connection fault FAN4_STS. Is set to 1 when Fan 4 is either stalled or running at low speed (according to the FSTLMD bit in the associated Extended FANPWM Control register; see Section 8.5.85 on page 190). 0: Fan operating normally (default) 1: Fan is either stalled or running at low speed FAN3_STS. Is set to 1 when Fan 3 is either stalled or running at low speed (according to the FSTLMD bit in the associated Extended FANPWM Control register). 0: Fan operating normally (default) 1: Fan is either stalled or running at low speed FAN2_STS. Is set to 1 when Fan 2 is either stalled or running at low speed (according to the FSTLMD bit in the associated Extended FANPWM Control register). 0: Fan operating normally (default) 1: Fan is either stalled or running at low speed FAN1_STS. Is set to 1 when Fan 1 is either stalled or running at low speed (according to the FSTLMD bit in the associated Extended FANPWM Control register). 0: Fan operating normally (default) 1: Fan is either stalled or running at low speed DEV1_STS. Is set to 1 when a communication problem with the LM96011, LM96010 or LM96012 device exists. 0: Communication with LM96011, LM96010 or LM96012 is functional (default) 1: Communication problem with LM96011, LM96010 or LM96012 12V_STS. Is set to 1 when 12V input voltage exceeds the limits. 0: Voltage not does not exceed any respective limit (default) 1: Voltage exceeds a respective limit Winbond Electronics Corp. Advanced PC Product Center

Revision 1.1 149 www.national.com PC8374L

8.4.10 HM Interrupt Status Register 3 (HMINT_STS3)

Event status register 3. Note: All status bits in this register are reset when START bit of the Configuration register is reset. Power Well: VSB3 Location: Offset 09h Type: R/W1C

8.4.11 HM Interrupt Enable Register 3(HMINT_EN3)

Interrupt enable register 3. Power Well: VDD3 Location: Offset 0Ah Type: R/W Bit Name Reserved CRIT3_EV CRIT2_EV CRIT1_EV Reset Bit Reserved. CRIT3_EV. Is set to 1 when a Temperature Zone3 critical monitoring event occurs. 0: No critical temperature state change from the last time this bit was cleared (default) 1: Critical temperature state changed from the last time this bit was cleared CRIT2_EV. Is set to 1 when a Temperature Zone2 critical monitoring event occurs. 0: No critical temperature state change from the last time this bit was cleared (default) 1: Critical temperature state changed from the last time this bit was cleared CRIT1_EV. Is set to 1 when a Temperature Zone1 critical monitoring event occurs. 0: No critical temperature state change from the last time this bit was cleared (default) 1: Critical temperature state changed from the last time this bit was cleared Bit Name Reserved CRIT3_EN CRIT2_EN CRIT1_EN Reset Bit Reserved. CRIT3_EN. When set to 1, enables IRQ generation on setting of CRIT3_EV of HMINT_STS3 register. 0: Disable IRQ (default) 1: Enable IRQ CRIT2_EN. When set to 1, enables IRQ generation on setting of CRIT2_EV of HMINT_STS3 register. 0: Disable IRQ (default) 1: Enable IRQ CRIT1_EN. When set to 1, enables IRQ generation on setting of CRIT1_EV of HMINT_STS3 register. 0: Disable IRQ (default) 1: Enable IRQ Winbond Electronics Corp. Advanced PC Product Center

www.national.com 150 Revision1.1 PC8374L

8.4.12 HM Sensor Status Register 3 (HMSENS_STS3)

Sensor status register 1. Power Well: VSB3 Location: Offset 0Bh Type: RO

8.4.13 HM SMI/SCI Enable Register 1 (HMS_EN1)

SMI/SCI Interrupt enable register 1. Power Well: VSB3 Location: Offset 0Ch Type: R/W Bit Name Reserved CRIT3_STS CRIT2_STS CRIT1_STS Reset Bit Reserved. CRIT3_STS. Is set to 1 when Temperature Zone3 temperature exceeds the critical limit. 0: Temperature does not exceed critical limit (default) 1: Temperature exceeds critical limit CRIT2_STS. Is set to 1 when Temperature Zone2 temperature exceeds the critical limit. 0: Temperature does not exceed critical limit (default) 1: Temperature exceeds critical limit CRIT1_STS. Is set to 1 when Temperature Zone1 temperature exceeds the critical limit. 0: Temperature does not exceed critical limit (default) 1: Temperature exceeds critical limit Bit Name Reserved ZONE3_EN ZONE2_EN ZONE1_EN 5V_EN 3.3V_EN Vccp_EN 2.5V_EN Reset Bit Reserved. ZONE3_EN. When set to 1, enables SMI/SCI generation on setting of ZONE3_EV of HMINT_STS1 register. 0: Disable SMI/SCI (default) 1: Enable SMI/SCI ZONE2_EN. When set to 1, enables SMI/SCI generation on setting of ZONE2_EV of HMINT_STS1 register. 0: Disable SMI/SCI (default) 1: Enable SMI/SCI ZONE1_EN. When set to 1, enables SMI/SCI generation on setting of ZONE1_EV of HMINT_STS1 register. 0: Disable SMI/SCI (default) 1: Enable SMI/SCI 5V_EN. When set to 1, enables SMI/SCI generation on setting of 5V_EV of HMINT_STS1 register. 0: Disable SMI/SCI (default) 1: Enable SMI/SCI Winbond Electronics Corp. Advanced PC Product Center

Revision 1.1 151 www.national.com PC8374L

8.4.14 HM SMI/SCI Enable Register 2 (HMS_EN2)

SMI/SCI enable register 2. Power Well: VSB3 Location: Offset 0Dh Type: R/W 3.3V_EN. When set to 1, enables SMI/SCI generation on setting of 3.3V_EV of HMINT_STS1 register. 0: Disable SMI/SCI (default) 1: Enable IRSMI/SCIQ Vccp_EN. When set to 1, enables SMI/SCI generation on setting of Vccp_EV of HMINT_STS1 register. 0: Disable SMI/SCI (default) 1: Enable SMI/SCI 2.5V_EN. When set to 1, enables SMI/SCI generation on setting of 2.5V_EV of HMINT_STS1 register. 0: Disable SMI/SCI (default) 1: Enable SMI/SCI Bit Name DEV2_EN RD_EN FAN4_EN FAN3_EN FAN2_EN FAN1_En DEV1_EN 12V_EN Reset Bit DEV2_EN. When set to 1, enables SMI/SCI generation on setting of DEV2_EV of HMINT_STS2 register. 0: Disable SMI/SCI (default) 1: Enable SMI/SCI RD_EN. When set to 1, enables SMI/SCI generation on setting of RD_EV of HMINT_STS2 register. 0: Disable SMI/SCI (default) 1: Enable SMI/SCI FAN4_EN. When set to 1, enables SMI/SCI generation on setting of FAN4_EV of HMINT_STS2 register. 0: Disable SMI/SCI (default) 1: Enable SMI/SCI FAN3_EN. When set to 1, enables SMI/SCI generation on setting of FAN3_EV of HMINT_STS2 register. 0: Disable SMI/SCI (default) 1: Enable SMI/SCI FAN2_EN. When set to 1, enables SMI/SCI generation on setting of FAN2_EV of HMINT_STS2 register. 0: Disable SMI/SCI (default) 1: Enable SMI/SCI FAN1_EN. When set to 1, enables SMI/SCI generation on setting of FAN1_EV of HMINT_STS2 register. 0: Disable SMI/SCI (default) 1: Enable SMI/SCI DEV1_EN. When set to 1, enables SMI/SCI generation on setting of DEV1_EV of HMINT_STS2 register. 0: Disable SMI/SCI (default) 1: Enable SMI/SCI 12V_EN. When set to 1, enables SMI/SCI generation on setting of 12V_EV of HMINT_STS2 register. 0: Disable SMI/SCI (default) 1: Enable SMI/SCI Bit Winbond Electronics Corp. Advanced PC Product Center

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8.4.15 HM SMI/SCI Enable Register 3(HMS_EN3)

SMI/SCI enable register 1. Power Well: VSB3 Location: Offset 0Eh Type: R/W

8.4.16 Events to SMI/SCI Routing Register (SMI/SCI_ROUT)

Power Well: VSB3 Location: 0Fh Type: R/W Bit Name Reserved CRIT3_EN CRIT2_EN CRIT1_EN Reset Bit Reserved. CRIT3_EN. When set to 1, enables SMI/SCI generation on setting of CRIT3_EV of HMINT_STS3 register. 0: Disable SMI/SCI (default) 1: Enable SMI/SCI CRIT2_EN. When set to 1, enables SMI/SCI generation on setting of CRIT2_EV of HMINT_STS3 register. 0: Disable SMI/SCI (default) 1: Enable SMI/SCI CRIT1_EN. When set to 1, enables SMI/SCI generation on setting of CRIT1_EV of HMINT_STS3 register. 0: Disable SMI/SCI (default) 1: Enable SMI/SCI Bit Name Reserved CRIT_EV_ 2SMI/SCI LIMIT_EV_ 2SMI/SCI Reset Bit Reserved. CRIT_EV_2SMI/SCI (Critical Events to SMI or SCI). Enables critical events to generate an SMI or SCI interrupt for the following events when the respective bits in the HMS_EN1-3 registers are set: FAN1-4_EV, RD_EV, DEV1_EV, DEV2_EV of HMINT_STS2 register, CRIT1-3_EV of HMINT_STS3 register. 0: SMI is generated 1: SCI (SIOPME) is generated LIMIT_EV_2SMI/SCI (Limit Events to SMI or SCI). Enables limit events to generate an SMI or SCI interrupt for the following events when the respective bits in the HMS_EN1-3 registers are set: 2.5V_EV, Vccp_EV, 3.3V_EV, 5V_EV, ZONE1-3_EV of HMINT_STS1 register, 12V_EV of HMINT_STS2. 0: SMI is generated 1: SCI (SIOPME) is generated Winbond Electronics Corp. Advanced PC Product Center

8.5 HEALTH MANAGEMENT REGISTERS

The HM registers implement health monitoring and control functionality. Reads to reserved and undefined registers return 0. Writes to reserved and undefined registers are ignored. Register 1-3 (address 41h, 42h and 73h respectively) are not accessible from LPC. All these registers are VSB3 powered and thus are reset by VSB Power-Up reset. Table 54. Health Management Registers

www.national.com 154 Revision1.1 PC8374L 49h Voltage High Limit 3.3V R/W or RO2 8.5.32 4Ah Voltage Low Limit 5V R/W or RO2 8.5.33 4Bh Voltage High Limit 5V R/W or RO2 8.5.34 4Ch Voltage Low Limit 12V R/W or RO2 8.5.35 4Dh Voltage High Limit 12V R/W or RO2 8.5.36 4Eh Temperature Low Limit Zone1 R/W or RO2 8.5.37 4Fh Temperature High Limit Zone1 R/W or RO2 8.5.38 50h Temperature Low Limit Zone2 R/W or RO2 8.5.39 51h Temperature High Limit Zone2 R/W or RO2 8.5.40 52h Temperature Low Limit Zone3 R/W or RO2 8.5.41 53h Temperature High Limit Zone3 R/W or RO2 8.5.42 54h Fan Tachometer1 Low Limit LSB R/W or RO2 8.5.43 55h Fan Tachometer1 Low Limit MSB R/W or RO2 8.5.44 56h Fan Tachometer2 Low Limit LSB R/W or RO2 8.5.45 57h Fan Tachometer2 Low Limit MSB R/W or RO2 8.5.46 58h Fan Tachometer3 Low Limit LSB R/W or RO2 8.5.47 59h Fan Tachometer3 Low Limit MSB R/W or RO2 8.5.48 5Ah Fan Tachometer4 Low Limit LSB R/W or RO2 8.5.49 5Bh Fan Tachometer4 Low Limit MSB R/W or RO2 8.5.50 5Ch FANPWM1 Control Configuration R/W or RO3 8.5.76 5Dh FANPWM2 Control Configuration R/W or RO3 8.5.77 5Eh FANPWM3 Control Configuration R/W or RO3 8.5.78 5Fh Zone1 Auto Speed Range and FANPWM1 Frequency R/W or RO3 8.5.71 60h Zone2 Auto Speed Range and FANPWM2 Frequency R/W or RO3 8.5.72 61h Zone3 Auto Speed Range and FANPWM3 Frequency R/W or RO3 8.5.73 62h Min/Off, Spike Smoothing 1 R/W or RO3 8.5.74 63h Min/Off, Spike Smoothing 2 R/W or RO3 8.5.75 64h FANPWM1 Minimum R/W or RO3 8.5.79 65h FANPWM2 Minimum R/W or RO3 8.5.80 66h FANPWM3 Minimum R/W or RO3 8.5.81 67h Zone1 Temperature Limit R/W or RO3 8.5.63 68h Zone2 Temperature Limit R/W or RO3 8.5.64 69h Zone3 Temperature Limit R/W or RO3 8.5.65 Address Register Name Type Section Winbond Electronics Corp. Advanced PC Product Center

Revision 1.1 155 www.national.com PC8374L 6Ah Zone1 Absolute Temperature Limit R/W or RO3 8.5.66 6Bh Zone2 Absolute Temperature Limit R/W or RO3 8.5.67 6Ch Zone3 Absolute Temperature Limit R/W or RO3 8.5.68 6Dh Zone1, Zone2 Hysteresis R/W or RO3 8.5.69 6Eh Zone3 Hysteresis R/W or RO3 8.5.70 6Fh Tach PWM Association R/W 8.5.62 70h FANPWM1 Maximum Duty R/W or RO3 8.5.82 71h FANPWM2 Maximum Duty R/W or RO3 8.5.83 72h FANPWM3 Maximum Duty R/W or RO3 8.5.84 73h Status Register 3 RO 8.5.25 74h Status Register 4 RO 8.5.26 75h Monitoring Control R/W or RO3 8.5.54 76h Extended FANPWM Control 1 R/W or RO3 8.5.85 77h Extended FANPWM Control 2 R/W or RO3 8.5.86 78h Tachometer Monitoring Control R/W or RO3 8.5.61 79h Channels VDD Configuration R/W or RO3 8.5.55 7Ah Temperature Critical Limit Zone1 R/W or RO2 8.5.51 7Bh Temperature Critical Limit Zone1 R/W or RO2 8.5.52 7Ch Temperature Critical Limit Zone2 R/W or RO2 8.5.53 7Dh Temperature Zone1 Gain and Offset Correction R/W or RO3 8.5.56 7Eh Temperature Zone2 Gain and Offset Correction R/W or RO3 8.5.57 7Fh Temperature Zone3 Gain and Offset Correction R/W or RO3 8.5.58 80h Enhanced Thermal Control R/W or RO3 8.5.59 81h-FFh Reserved 1. Read-only, when fan control is not in manual mode. 2. Locked by the LOCK_LIM bit in the Monitoring Control register. 3. Locked by the LOCK bit in the Configuration register. Address Register Name Type Section Winbond Electronics Corp. Advanced PC Product Center

www.national.com 156 Revision1.1 PC8374L 8.5.1 Voltage Reading 2.5V Reflects current voltage of 2.5V monitoring. Location: 20h Type: RO 8.5.2 Voltage Reading Vccp Reflects current voltage of Vccp monitoring. Location: 21h Type: RO 8.5.3 Voltage Reading 3.3V Reflects current voltage of 3.3V monitoring. Location: 22h Type: RO Bit Name VOLT_DATA Reset Bit VOLT_DATA. The high byte of the voltage data measured by the associated LMxx Sensor device. The data is interpreted as a left-aligned positive value: MSBit of the LMxx Voltage Readout register maps to bit 7 of VOLT_DATA field. Bit Name VOLT_DATA Reset Bit VOLT_DATA. The high byte of the voltage data measured by the associated LMxx Sensor device. The data is interpreted as a left-aligned positive value: MSBit of the LMxx Voltage Readout register maps to bit 7 of VOLT_DATA field. Bit Name VOLT_DATA Reset Bit VOLT_DATA. The high byte of the voltage data measured by the associated LMxx Sensor device. The data is interpreted as a left-aligned positive value: MSBit of the LMxx Voltage Readout register maps to bit 7 of VOLT_DATA field. Winbond Electronics Corp. Advanced PC Product Center

Revision 1.1 157 www.national.com PC8374L 8.5.4 Voltage Reading 5V Reflects current voltage of 5V monitoring. Location: 23h Type: RO 8.5.5 Voltage Reading 12V Reflects current voltage of 12V monitoring. Location: 24h Type: RO 8.5.6 Temperature Reading Zone1 Reflects current Zone1 temperature. Location: 25h Type: RO Bit Name VOLT_DATA Reset Bit VOLT_DATA. The high byte of the voltage data measured by the associated LMxx Sensor device. The data is interpreted as a left-aligned positive value: MSBit of the LMxx Voltage Readout register maps to bit 7 of VOLT_DATA field. Bit Name VOLT_DATA Reset Bit VOLT_DATA. The high byte of the voltage data measured by the associated LMxx Sensor device. The data is interpreted as a left-aligned positive value: MSBit of the LMxx Voltage Readout register maps to bit 7 of VOLT_DATA field. Bit Name TEMP_DATA Reset Bit TEMP_DATA. The high byte of the Temperature Zone1 data measured by the associated LMxx Sensor device. The data is converted to a left-aligned 2’s complement value. The value represented in this register is dependent on the setting of the ZONE1_RANGE bit in the Monitor Control Register (see Section 8.5.54 on page 176). If ZONE1_RANGE is 0 the LSBit of this register represents a value of 1°C (temperature values are between -127°C (81h) and +127°C (7Fh)). If ZONE1_RANGE bit is 1 the LSBit of this register represents a value of 2°C (temperature values are between -254°C (81h) and +254°C (7Fh)). A value of 80h represents a sensor error. Notes: 1. TEMP_DATA is obtained by translating the Temperature Readout register data from the LMxx Sensor device, according to the algorithm shown in Figure 37 on page 158. Limit checking is done only after the temperature data has been modified (if necessary). 2. The temperature data can be low-pass filtered by setting the TEMP_FILT bit in the Monitoring Control register (see Section 8.5.54 on page 176). Winbond Electronics Corp. Advanced PC Product Center

Figure 37. Temperature Data Translation from LMxx Device to HM Temperature Zone Registers

Revision 1.1 159 www.national.com PC8374L 8.5.7 Temperature Reading Zone2 Reflects current Zone2 temperature. Location: 26h Type: RO 8.5.8 Temperature Reading Zone3 Reflects current Zone3 temperature. Location: 27h Type: RO 8.5.9 Fan Tachometer Reading 1 LSB Contains the number of 90 KHz clock cycles during a full fan revolution, LSB byte. Location: 28h Type: RO Bit Name TEMP_DATA Reset Bit TEMP_DATA. Same as TEMP_DATA of Temperature Reading Zone1 register, but for Zone2. Bit Name TEMP_DATA Reset Bit TEMP_DATA. Same as TEMP_DATA of Temperature Reading Zone1 register, but for Zone3. Also, if only an LM96011 device is connected to the SensorPath Bus and an optional LM95010 device is not present, this field shows a value of 80h. Bit Name TACH_LOW Reset Bit TACH_LOW. The low byte of 90 KHz clock cycles during a full fan revolution of Fan Tachometer 1. If the fan is not spinning, the fan is spinning-up or there is a speed measurement error, the value returned in the MSByte and LSByte, together, is FFFFh. Note that correct results depend on using fans that produce two tachometer pulses per full revolution or one pulse per fan revolution (configured by the TPPR1 bit in the Tachometer Monitoring Control register; see Section 8.5.61 on page 180). Whenever TACH_LOW register is read, the high byte of the tachometer Reading (TACH_HIGH) is latched to save the current fan speed value until TACH_HIGH register is read. Therefore, TACH_LOW must be read first and TACH_HIGH must be read immediately after. Note that internally, only one latch is used for all fan tachometer readings. The two bytes of a tachometer data must be read before reading the next tachometer data; otherwise, the read data may be incorrect. The fan speed data is updated every 1s. Winbond Electronics Corp. Advanced PC Product Center

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8.5.10 Fan Tachometer Reading 1 MSB

Contains the number of 90 KHz clock cycles during a full fan revolution, MSB byte. Location: 29h Type: RO

8.5.11 Fan Tachometer Reading 2 LSB

Contains the number of 90 KHz clock cycles during a full fan revolution, LSB byte. Location: 2Ah Type: RO

8.5.12 Fan Tachometer Reading 2 MSB

Contains the number of 90 KHz clock cycles during a full fan revolution, MSB byte. Location: 2Bh Type: RO

8.5.13 Fan Tachometer Reading 3 LSB

Contains the number of 90 KHz clock cycles during a full fan revolution, LSB byte. Location: 2Ch Type: RO Bit Name TACH_HIGH Reset Bit TACH_HIGH. The high byte of 90 KHz clock cycles during a full fan revolution of Fan Tachometer 1. If the fan is not spinning or there is a speed measurement error, the value returned in the MSByte and LSByte, together, is FFFFh. Bit Name TACH_LOW Reset Bit TACH_LOW. Same as TACH_LOW of Fan Tachometer Reading 1 LSB register, but for Fan Tachometer 2. Bit Name TACH_HIGH Reset Bit TACH_HIGH. Same as TACH_HIGH of Fan Tachometer Reading 1 MSB register, but for Fan Tachometer 2. Bit Name TACH_LOW Reset Bit TACH_LOW. Same as TACH_LOW of Fan Tachometer Reading 1 LSB register, but for Fan Tachometer 3. Winbond Electronics Corp. Advanced PC Product Center

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8.5.14 Fan Tachometer Reading 3 MSB

Contains the number of 90 KHz clock cycles during a full fan revolution, MSB byte. Location: 2Dh Type: RO

8.5.15 Fan Tachometer Reading 4 LSB

Contains the number of 90 KHz clock cycles during a full fan revolution, LSB byte. Location: 2Eh Type: RO

8.5.16 Fan Tachometer Reading 4 MSB

Contains the number of 90 KHz clock cycles during a full fan revolution, MSB byte. Location: 2Fh Type: RO

8.5.17 FANPWM1 Current Duty

Current FANPWM1 duty cycle. Location: 30h Type: R/W or RO (Becomes read-only when FANPWM1 Configuration is not set for manual mode.) Bit Name TACH_HIGH Reset Bit TACH_HIGH. Same as TACH_HIGH of Fan Tachometer Reading 1 MSB register, but for Fan Tachometer 3. Bit Name TACH_LOW Reset Bit TACH_LOW. Same as TACH_LOW of Fan Tachometer Reading 1 LSB register, but for Fan Tachometer 4. Bit Name TACH_HIGH Reset Bit TACH_HIGH. Same as TACH_HIGH of Fan Tachometer Reading 1 MSB register, but for Fan Tachometer 4. Bit Name PWM_DUTY Reset Winbond Electronics Corp. Advanced PC Product Center

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8.5.18 FANPWM2 Current Duty

Current FANPWM2 duty cycle. Location: 31h Type: R/W or RO (Becomes read-only when FANPWM2 Configuration is not set for manual mode.)

8.5.19 FANPWM3 Current Duty

Current FANPWM3 duty cycle. Location: 32h Type: R/W or RO (Becomes read-only when FANPWM3 Configuration is not set for manual mode.)

8.5.20 Company ID

Company identification number. Location: 3Eh Type: RO Bit PWM_DUTY. Holds the current value of the duty cycle of the associated FANPWM signal. The behavior of this field depends on the FANPWM Control Configuration register: In Manual mode, PWM_DUTY field is R/W: the value written selects the duty cycle of the FANPWM output. In all other modes, PWM_DUTY field is RO: its value indicates the current duty cycle of the FANPWM out- put. During spin-up PWM_DUTY field is 0. A value of 00h represents 0% duty cycle; a value of FFh represents 100% duty cycle. Bit Name PWM_DUTY Reset Bit PWM_DUTY. Same as PWM_DUTY of FANPWM1 Current Duty register, but for FANPWM2. Bit Name PWM_DUTY Reset Bit PWM_DUTY. Same as PWM_DUTY of FANPWM1 Current Duty register, but for FANPWM3. Bit Name COMP_ID Reset Bit COMP_ID. Company identification number: 01h. Winbond Electronics Corp. Advanced PC Product Center

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8.5.21 Version

Version and stepping identifiers. Location: 3Fh Type: RO

8.5.22 Configuration

Configuration register. Location: 40h Type: Varies per bit Bit Name VER STEP Reset Bit VER. HM version. 3-0 STEP. HM version stepping. For A0 stepping, the value is 1000b; for A1 it is 1001b; for A2 it is 1010b, etc. Bit Name Reserved SMBR OVRID READY LOCK START Reset Bit Type Reserved. R/W SMBR (SMBus Read). When set to 1, access through the SMBus is read-only. This bit can be set only through the LPC Bus. It is read-only for access through the SMBus. 0: Full SMBus access to the HM registers (default) 1: Read-only SMBus access to the HM registers R/W OVRID (Override FANPWM Configuration). When set to 1, all FANPWM outputs are set to the value contained in the MAX_PWM field of the associated FANPWMn MAX Duty registers (see Section 8.5.82 on page 189 to Section 8.5.84) regardless of LOCK bit. 0: FANPWM outputs are controlled by Fan Control Configuration register; see Section 8.5.76 on page 187 to Section 8.5.78 (default) 1: FANPWM outputs are set to MAX_PWM duty cycle RO READY. Is set to 1 when the HM is ready for operation. While Ready is 0 Health monitoring and Fan control functions are disabled. 0: The HM is reset or initializing (default) 1: The HM is enabled and ready for operation R/W or RO LOCK. When set to 1, locks itself and the following HM registers: FANPWM1-3 Control Configuration, Fan1-3 Auto Speed Range and PWM Frequency, Min/Off Spike Smoothing 1-2, FANPWM1-3 Minimum, Zone1-Zone3 Temperature Limit, Zone1-Zone3 Absolute temperature Limit, Zone1, Zone2, Zone3 Hysteresis, Extended FANPWM Control 1, Extended FANPWM Control 2, Monitoring Control, Tachometer Monitoring Control, Channels VDD Configuration, Temperature Zones1-3 Gain and Offset Correction, FANPWM1-3 Maximum Duty. This bit is reset by Hardware reset. 0: All R/W HM registers are enabled for write (default) 1: Specified HM registers are RO Winbond Electronics Corp. Advanced PC Product Center

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8.5.23 Status Register 1

Event status register 1. This register is accessible only through SMBus. Note: All status bits in this register are reset when START bit of the Configuration register is reset. Location: 41h Type: RO R/W START. When this bit is reset to 0, monitoring and FANPWM output control functions based on the limit and parameter registers are disabled, and all status bits in Status Registers 1,2 and 3 are cleared. In this case, all registers not locked by LOCK can be modified, but they do not affect the Health monitor and control functions of the HM. START bit is always writable regardless of LOCK bit. When this bit is set to 1, Monitoring and FANPWM output control functions based on limit and parameter registers are enabled. START bit is reset to 0 by a VSB Power-Up reset. Then, HM performs the following: After READY bit becomes 1, Temperature Zone1 is monitored (although START bit is 0). If a temper- ature above +110°C is detected, ETC is asserted (see Section 8.2.10 on page 139), which turns the Main power supply off. The FANPWM outputs are at 0% duty cycle; they are set to a different value after either of the follow- ing occurs: — Two seconds elapsed since the VDD3 power has been turned on (FANPWM outputs are set to the value contained in the associated FANPWMn MAX Duty registers) — START bit is set to 1 Bit Name STAT_REG2 _ERR ZONE3_ERR ZONE2_ERR ZONE1_ERR 5V_ERR 3.3V_ERR Vccp_ERR 2.5V_ERR Reset Bit STAT_REG2_ERR. Is set to 1 if one of the bits in Status Register 2 is set. Once set, the bit is cleared only after the Status Register 2 is read and then, the Status Register 1 is read. 0: No event is set in Interrupt Status Register 2 (default) 1: At least one of the event bits in Status Register 2 is set ZONE3_ERR. Is set to 1 when Zone3 temperature is less than the limit set in the corresponding Low Temp register (see Section 8.5.41 on page 172) or greater than the limit set in the corresponding High Temp register (see Section 8.5.42 on page 172). Once set, the bit is updated again only after this register is read. 0: Temperature does not exceed any respective (default) 1: Temperature exceeds a respective limit ZONE2_ERR. Is set to 1 when Zone2 temperature is less than the limit set in the corresponding Low Temp register (see Section 8.5.39 on page 171) or greater than the limit set in the corresponding High Temp register (see Section 8.5.40 on page 172). Once set, the bit is updated again only after this register is read. 0: Temperature does not exceed any respective limit (default) 1: Temperature exceeds a respective limit ZONE1_ERR. Is set to 1 when Zone1 temperature is less than the limit set in the corresponding Low Temp register (see Section 8.5.37 on page 171) or greater than the limit set in the corresponding High Temp register (see Section 8.5.38 on page 171). Once set, the bit is updated again only after this register is read. 0: Temperature does not exceed any respective limit (default) 1: Temperature exceeds a respective limit Bit Type Winbond Electronics Corp. Advanced PC Product Center

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8.5.24 Status Register 2

Event status register 2.This register is accessible only through the SMBus. Note: All status bits in this register are reset when START bit of the Configuration register is reset. Location: 42h Type: RO 5V_ERR. Is set to 1 when 5V input voltage is less than the limit set in the corresponding Low Limit register (see Section 8.5.33 on page 169) or greater than the limit set in the corresponding High Limit register (see Section 8.5.34 on page 170). Once set, the bit is updated again only after this register is read. 0: Voltage does not exceed any respective limit (default) 1: Voltage exceeds a respective limit 3.3V_ERR. Is set to 1 when 3.3V input voltage is less than the limit set in the corresponding Low Limit register (see Section 8.5.31 on page 169) or greater than the limit set in the corresponding High Limit register (see Section 8.5.32 on page 169). Once set, the bit is updated again only after this register is read. 0: Voltage does not exceed any respective limit (default) 1: Voltage exceeds a respective limit Vccp_ERR. Is set to 1 when Vccp input voltage is less than the limit set in the corresponding Low Limit register (see Section 8.5.29 on page 168) or greater than the limit set in the corresponding High Limit register (see Section 8.5.30 on page 168). Once set, the bit is updated again only after this register is read. 0: Voltage does not exceed any respective limit (default) 1: Voltage exceeds a respective limit 2.5V_ERR. Is set to 1 when 2.5V input voltage is less than the limit set in the corresponding Low Limit register (see Section 8.5.27 on page 167) or greater than the limit set in the corresponding High Limit register (see Section 8.5.28 on page 168). Once set, the bit is updated again only after this register is read. 0: Voltage does not exceed any respective limit (default) 1: Voltage exceeds a respective limit Bit Name DEV2_Fault RD_Fault FAN4_ STALL FAN3_ STALL FAN2 STALL FAN1_ STALL DEV1_Fault 12V_ERR Reset Bit DEV2_Fault (Device 2 Fault). Is set to 1 when a communication problem with the optional LM95010 device occurs. Once set, the bit is updated again only after this register is read. 0: The optional LM95010 device does not exist or exists with valid communication (default) 1: A communication problem with LM95010 RD_Fault (Remote Diode Fault). Is set to 1 when there is a physical connection fault in one of the Remote Diodes of the Temperature Zones occur (for LM96011: Zone1; for LM96010 or LM96012: Zone1 or Zone3). Once set, the bit is updated again only after this register is read. 0: Proper connection of Remote Diode (default) 1: Remote Diode connection fault FAN4_STALL. Is set to 1 when Fan 4 is either stalled or running at low speed (according to the FSTLMD bit in the associated Extended FANPWM Control register; see Section 8.5.85 on page 190). Once set, the bit is updated again only after this register is read. 0: Fan operating normally (default) 1: Fan is either stalled or running at low speed Bit Winbond Electronics Corp. Advanced PC Product Center

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8.5.25 Status Register 3

Event status register 3. This register is accessible only through SMBus. Note: All status bits in this register are reset when START bit of the Configuration register is reset. Location: 73h Type: RO FAN3_STALL. Is set to 1 when Fan 3 is either stalled or running at low speed (according to the FSTLMD bit in the associated Extended FANPWM Control register; see Section 8.5.85 on page 190). Once set, the bit is updated again only after this register is read. 0: Fan operating normally (default) 1: Fan is either stalled or running at low speed FAN2_STALL. Is set to 1 when Fan 2 is either stalled or running at low speed (according to the FSTLMD bit in the associated Extended FANPWM Control register; see Section 8.5.85 on page 190). Once set, the bit is updated again only after this register is read. 0: Fan operating normally (default) 1: Fan is either stalled or running at low speed FAN1_STALL. Is set to 1 when Fan 1 is either stalled or running at low speed (according to the FSTLMD bit in the associated Extended FANPWM Control register; see Section 8.5.85 on page 190). Once set, the bit is updated again only after this register is read. 0: Fan operating normally (default) 1: Fan is either stalled or running at low speed DEV1_Fault (Device 1 Fault). Is set to 1 when a communication problem with the LM96011, LM96010 or LM96012 device occurs. Once set, the bit is updated again only after this register is read. 0: Communication with LM96011/LM96010/LM96012 is functional (default) 1: Communication problem with LM96011/LM96010/LM96012 12V_ERR. Is set to 1 when 12V input voltage is less than the limit set in the corresponding Low Limit register (see Section 8.5.35 on page 170) or greater than the limit set in the corresponding High Limit register (see Section 8.5.36 on page 170). Once set, the bit is updated again only after this register is read. 0: Voltage does not exceed any respective limit (default) 1: Voltage exceeds a respective limit Bit Name Reserved CRIT3_ERR CRIT2_ERR CRIT1_ERR Reset Bit Reserved. CRIT3_ERR. Is set to 1 when Zone3 temperature is more than the limit set in the corresponding Temperature Critical Limit register (see Section 8.5.53 on page 175). Once set, the bit is updated again only after this register is read. 0: Temperature does not exceed the critical limit (default) 1: Temperature exceeds the critical limit CRIT2_ERR. Is set to 1 when Zone2 temperature is more than the limit set in the corresponding Temperature Critical Limit register (see Section 8.5.52 on page 175). Once set, the bit is updated again only after this register is read. 0: Temperature does not exceed the critical limit (default) 1: Temperature exceeds the critical limit Bit Winbond Electronics Corp. Advanced PC Product Center

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8.5.26 Status Register 4

Location: 74h Type: RO 8.5.27 Voltage Low Limit 2.5V Voltage low limit for 2.5V voltage monitoring. Location: 44h Type: R/W or RO (Becomes read-only when LOCK_LIM bit in the Monitoring Control register is set.) CRIT1_ERR. Is set to 1 when Zone1 temperature is more than the limit set in the corresponding Temperature Critical Limit register (see Section 8.5.51 on page 175). Once set, the bit is updated again only after this register is read. 0: Temperature does not exceed the critical limit (default) 1: Temperature exceeds the critical limit Bit Name Reserved FAN4_OFF FAN3_OFF FAN2_OFF FAN1_OFF Reset Bit Reserved. FAN4_OFF. When set, this bit indicates for Fan Tachometer 4 that the associated FANPWM signal (see Section 8.5.62 on page 181) driving the fan is in one of the following states: Fan turned off: The Duty Cycle of the associated FANPWM output is 0% Fan spinning-up: The rotational speed of the fan driven by the associated FANPWM output is increasing from 0 Fan stopping: The rotational speed of the fan driven by the associated FANPWM output is decreasing to 0 When FAN4_OFF bit is set, Fan Tachometer 4 registers are set to FFFFh, and the following bits are set to 0: FAN4_STALL status bit of Status Register 2 (see Section 8.5.24 on page 165), and FAN4_STS of HM Sensor Status Register 2 (see Section 8.4.9 on page 148). When FAN4_OFF bit returns to 0, the status bits and Fan Tachometer registers are released (can be updated). 0: Fan rotating 1: Fan off, spinning-up or stopping (default) 2-0 FAN3_OFF - FAN1_OFF. Same as FAN4_OFF for Fan Tachometer 3-1. Bit Name LOW_LIMIT Reset Bit LOW_LIMIT. The low limit value to which the associated voltage input data is compared. If the voltage input data is lower than LOW_LIMIT, the corresponding bits in the HM Interrupt Status register, HM Sensor Status Register and Status Register are updated/set (see Section 8.4.4 on page 143, Section 8.4.8 on page 147, and Section 8.5.23 on page 164). Bit Winbond Electronics Corp. Advanced PC Product Center

www.national.com 168 Revision1.1 PC8374L 8.5.28 Voltage High Limit 2.5V Voltage high limit for 2.5V voltage monitoring. Location: 45h Type: R/W or RO (Becomes read-only when LOCK_LIM bit in the Monitoring Control register is set.)

8.5.29 Voltage Low Limit Vccp

Voltage low limit for Vccp voltage monitoring. Location: 46h Type: R/W or RO (Becomes read-only when LOCK_LIM bit in the Monitoring Control register is set.)

8.5.30 Voltage High Limit Vccp

Voltage high limit for Vccp voltage monitoring. Location: 47h Type: R/W or RO (Becomes read-only when LOCK_LIM bit in the Monitoring Control register is set.) Bit Name HIGH_LIMIT Reset Bit HIGH_LIMIT. The high limit value to which the associated voltage input data is compared. If the voltage input data is higher than HIGH_LIMIT, the corresponding bits in the HM Interrupt Status register, HM Sensor Status Register and Status Register are updated/set (see Section 8.4.4 on page 143, Section 8.4.8 on page 147, and Section 8.5.23 on page 164). Bit Name LOW_LIMIT Reset Bit LOW_LIMIT. The low limit value to which the associated voltage input data is compared. If the voltage input data is lower than LOW_LIMIT, the corresponding bits in the HM Interrupt Status register, HM Sensor Status Register and Status Register are updated/set (see Section 8.4.4 on page 143, Section 8.4.8 on page 147, and Section 8.5.23 on page 164). Bit Name HIGH_LIMIT Reset Bit HIGH_LIMIT. The high limit value to which the associated voltage input data is compared. If the voltage input data is higher than HIGH_LIMIT, the corresponding bits in the HM Interrupt Status register, HM Sensor Status Register and Status Register are updated/set (see Section 8.4.4 on page 143, Section 8.4.8 on page 147, and Section 8.5.23 on page 164). Winbond Electronics Corp. Advanced PC Product Center

Revision 1.1 169 www.national.com PC8374L 8.5.31 Voltage Low Limit 3.3V Voltage low limit for 3.3V voltage monitoring. Location: 48h Type: R/W or RO (Becomes read-only when LOCK_LIM bit in the Monitoring Control register is set.) 8.5.32 Voltage High Limit 3.3V Voltage high limit for 3.3V voltage monitoring. Location: 49h Type: R/W or RO (Becomes read-only when LOCK_LIM bit in the Monitoring Control register is set.)

8.5.33 Voltage Low Limit 5V

Voltage low limit for 5V voltage monitoring. Location: 4Ah Type: R/W or RO (Becomes read-only when LOCK_LIM bit in the Monitoring Control register is set.) Bit Name LOW_LIMIT Reset Bit LOW_LIMIT. The low limit value to which the associated voltage input data is compared. If the voltage input data is lower than LOW_LIMIT, the corresponding bits in the HM Interrupt Status register, HM Sensor Status Register and Status Register are updated/set (see Section 8.4.4 on page 143, Section 8.4.8 on page 147, and Section 8.5.23 on page 164). Bit Name HIGH_LIMIT Reset Bit HIGH_LIMIT. The high limit value to which the associated voltage input data is compared. If the voltage input data is higher than HIGH_LIMIT, the corresponding bits in the HM Interrupt Status register, HM Sensor Status Register and Status Register are updated/set (see Section 8.4.4 on page 143, Section 8.4.8 on page 147, and Section 8.5.23 on page 164). Bit Name LOW_LIMIT Reset Bit LOW_LIMIT. The low limit value to which the associated voltage input data is compared. If the voltage input data is lower than LOW_LIMIT, the corresponding bits in the HM Interrupt Status register, HM Sensor Status Register and Status Register are updated/set (see Section 8.4.4 on page 143, Section 8.4.8 on page 147, and Section 8.5.23 on page 164). Winbond Electronics Corp. Advanced PC Product Center

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8.5.34 Voltage High Limit 5V

Voltage high limit for 5V voltage monitoring. Location: 4Bh Type: R/W or RO (Becomes read-only when LOCK_LIM bit in the Monitoring Control register is set.)

8.5.35 Voltage Low Limit 12V

Voltage low limit for 12V voltage monitoring. Location: 4Ch Type: R/W or RO (Becomes read-only when LOCK_LIM bit in the Monitoring Control register is set.)

8.5.36 Voltage High Limit 12V

Voltage high limit for 12V voltage monitoring. Location: 4Dh Type: R/W or RO (Becomes read-only when LOCK_LIM bit in the Monitoring Control register is set.) Bit Name HIGH_LIMIT Reset Bit HIGH_LIMIT. The high limit value to which the associated voltage input data is compared. If the voltage input data is higher than HIGH_LIMIT, the corresponding bits in the HM Interrupt Status register, HM Sensor Status Register and Status Register are updated/set (see Section 8.4.4 on page 143, Section 8.4.8 on page 147, and Section 8.5.23 on page 164). Bit Name LOW_LIMIT Reset Bit LOW_LIMIT. The low limit value to which the associated voltage input data is compared. If the voltage input data is lower than LOW_LIMIT, the corresponding bits in the HM Interrupt Status register, HM Sensor Status Register and Status Register are updated/set (see Section 8.4.5 on page 144, Section 8.4.9 on page 148, and Section 8.5.24 on page 165). Bit Name HIGH_LIMIT Reset Bit HIGH_LIMIT. The high limit value to which the associated voltage input data is compared. If the voltage input data is higher than HIGH_LIMIT, the corresponding bits in the HM Interrupt Status register, HM Sensor Status Register and Status Register are updated/set (see Section 8.4.5 on page 144, Section 8.4.9 on page 148, and Section 8.5.24 on page 165). Winbond Electronics Corp. Advanced PC Product Center

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8.5.37 Temperature Low Limit Zone1

Temperature low limit for Zone1 temperature monitoring. Location: 4Eh Type: R/W or RO (Becomes read-only when LOCK_LIM bit in the Monitoring Control register is set.)

8.5.38 Temperature High Limit Zone1

Temperature high limit for Zone1 temperature monitoring. Location: 4Fh Type: R/W or RO (Becomes read-only when LOCK_LIM bit in the Monitoring Control register is set.)

8.5.39 Temperature Low Limit Zone2

Temperature low limit for Zone2 temperature monitoring. Location: 50h Type: R/W or RO (Becomes read-only when LOCK_LIM bit in the Monitoring Control register is set.) Bit Name LOW_LIMIT Reset Bit LOW_LIMIT. The low limit value to which the associated temperature input data is compared. If the temperature input data is lower than LOW_LIMIT, the corresponding bits in the HM Interrupt Status register, HM Sensor Status Register and Status Register are updated/set (see Section 8.4.5 on page 144, Section 8.4.9 on page 148, and Section 8.5.24 on page 165). LOW_LIMIT format is the same as the format of the corresponding Temperature Reading Zone1 register (see Section 37 on page 158). This format is dependent on the setting of the ZONE1_RANGE bit in the Monitor Control Register (see Section 8.5.54 on page 176). The default value is 81h (-127°C for 1°C resolution, -254°C for 2°C resolution). Note: A value of 80h must not be used. Bit Name HIGH_LIMIT Reset Bit HIGH_LIMIT. The high limit value to which the associated temperature input data is compared. If the temperature input data is higher than HIGH_LIMIT, the corresponding bits in the HM Interrupt Status register, HM Sensor Status Register and Status Register are updated/set (see Section 8.4.5 on page 144, Section 8.4.9 on page 148, and Section 8.5.24 on page 165). HIGH_LIMIT format is the same as the format of the corresponding Temperature Reading Zone1 register (see Section 37 on page 158). This format is dependent on the setting of the ZONE1_RANGE bit in the Monitor Control Register (see Section 8.5.54 on page 176). The default value is 7Fh (127°C for 1°C resolution, 254°C for 2°C resolution). Note: A value of 80h must not be used. Bit Name LOW_LIMIT Reset Bit LOW_LIMIT. Same as LOW_LIMIT in Temperature Low Limit Zone1, but for Temperature Zone2. Winbond Electronics Corp. Advanced PC Product Center

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8.5.40 Temperature High Limit Zone2

Temperature high limit for Zone2 temperature monitoring. Location: 51h Type: R/W or RO (Becomes read-only when LOCK_LIM bit in the Monitoring Control register is set.)

8.5.41 Temperature Low Limit Zone3

Temperature low limit for Zone3 temperature monitoring. Location: 52h Type: R/W or RO (Becomes read-only when LOCK_LIM bit in the Monitoring Control register is set.)

8.5.42 Temperature High Limit Zone3

Temperature high limit for Zone3 temperature monitoring. Location: 53h Type: R/W or RO (Becomes read-only when LOCK_LIM bit in the Monitoring Control register is set.) Bit Name HIGH_LIMIT Reset Bit HIGH_LIMIT. Same as HIGH_LIMIT in Temperature Low Limit Zone1, but for Temperature Zone2. Bit Name LOW_LIMIT Reset Bit LOW_LIMIT. Same as LOW_LIMIT in Temperature Low Limit Zone1, but for Temperature Zone3. Bit Name HIGH_LIMIT Reset Bit HIGH_LIMIT. Same as HIGH_LIMIT in Temperature Low Limit Zone1, but for Temperature Zone3. Winbond Electronics Corp. Advanced PC Product Center

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8.5.43 Fan Tachometer1 Low Limit LSB

LSB of lowest permitted fan speed value. Location: 54h Type: R/W or RO (Becomes read-only when LOCK_LIM bit in the Monitoring Control register is set.)

8.5.44 Fan Tachometer1 Low Limit MSB

LSB of lowest permitted fan speed value. Location: 55h Type: R/W or RO (Becomes read-only when LOCK_LIM bit in the Monitoring Control register is set.)

8.5.45 Fan Tachometer2 Low Limit LSB

LSB of lowest permitted fan speed value. Location: 56h Type: R/W or RO (Becomes read-only when LOCK_LIM bit in the Monitoring Control register is set.) Bit Name FAN_MIN_LSB Reset Bit FAN_MIN_LSB. Contains the low byte of the Fan Tachometer value, which indicates the lowest permitted fan speed value setting. If the number of clock cycles counted in one fan revolution is higher than the Fan Tachometer value (FAN_MIN_LSB and FAN_MIN_MSB), the associated FANn_xxx bits in the HM Interrupt Status register, HM Sensor Status Register and Status Register are set to 1 (see Section 8.4.5 on page 144, Tachometer Low Limit value is FFFFh. If the associated FANPWM output is set to Automatic fan control and if the SPIN_END bit in related Extended FANPWM Control register is set to 0, the Fan Tachometer Low Limit registers (FAN_MIN_LSB and FAN_MIN_MSB) indicate the fan speed at which the spin-up is ended (see Section 8.5.85 on page 190). In this case, a fan speed below the set value does not set the FANn_xxx bits to 1; a fan speed above the set value indicates the end of spin-up process (see “Speed Change Modes” on page 136). The two LSBits of this field are irrelevant and can be set to any value. For correct operation when writing a new value to the Low Limit registers, the Limit LSB register must be written before the Limit MSB register. Note that internally, only one latch is used for all Limit writing. The two bytes of a tachometer limit must be written before writing the next tachometer limit; otherwise, the written data may be incorrect. Bit Name FAN_MIN_MSB Reset Bit FAN_MIN_MSB. Contains the high byte of the Fan Tachometer value which indicates either the lowest permitted fan speed value setting or the fan speed at which the spin-up is ended. Bit Name FAN_MIN_LSB Reset Bit FAN_MIN_LSB. Same as FAN_MIN_LSB of Fan Tachometer1 Low Limit LSB register, but for Fan Tachometer 2. Winbond Electronics Corp. Advanced PC Product Center

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8.5.46 Fan Tachometer2 Low Limit MSB

LSB of lowest permitted fan speed value. Location: 57h Type: R/W or RO (Becomes read-only when LOCK_LIM bit in the Monitoring Control register is set.)

8.5.47 Fan Tachometer3 Low Limit LSB

LSB of lowest permitted fan speed value. Location: 58h Type: R/W or RO (Becomes read-only when LOCK_LIM bit in the Monitoring Control register is set.)

8.5.48 Fan Tachometer3 Low Limit MSB

LSB of lowest permitted fan speed value. Location: 59h Type: R/W or RO (Becomes read-only when LOCK_LIM bit in the Monitoring Control register is set.)

8.5.49 Fan Tachometer4 Low Limit LSB

LSB of lowest permitted fan speed value. Location: 5Ah Type: R/W or RO (Becomes read-only when LOCK_LIM bit in the Monitoring Control register is set.) Bit Name FAN_MIN_MSB Reset Bit FAN_MIN_MSB. Same as FAN_MIN_MSB of Fan Tachometer1 Low Limit LSB register, but for Fan Tachometer 2. Bit Name FAN_MIN_LSB Reset Bit FAN_MIN_LSB. Same as FAN_MIN_LSB of Fan Tachometer1 Low Limit LSB register, but for Fan Tachometer 3. Bit Name FAN_MIN_MSB Reset Bit FAN_MIN_MSB. Same as FAN_MIN_MSB of Fan Tachometer1 Low Limit LSB register, but for Fan Tachometer 3. Bit Name FAN_MIN_LSB Reset Bit FAN_MIN_LSB. Same as FAN_MIN_LSB of Fan Tachometer1 Low Limit LSB register, but for Fan Tachometer 4. Winbond Electronics Corp. Advanced PC Product Center

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8.5.50 Fan Tachometer4 Low Limit MSB

LSB of lowest permitted fan speed value. Location: 5Bh Type: R/W or RO (Becomes read-only when LOCK_LIM bit in the Monitoring Control register is set.)

8.5.51 Temperature Critical Limit Zone1

Temperature critical limit for Zone1 temperature monitoring. Location: 7Ah Type: R/W or RO (Becomes read-only when LOCK_LIM bit in the Monitoring Control register is set.)

8.5.52 Temperature Critical Limit Zone2

Temperature critical limit for Zone2 temperature monitoring. Location: 7Bh Type: R/W or RO (Becomes read-only when LOCK_LIM bit in the Monitoring Control register is set.)

8.5.53 Temperature Critical Limit Zone3

Temperature critical limit for Zone3 temperature monitoring. Location: 7Ch Type: R/W or RO (Becomes read-only when LOCK_LIM bit in the Monitoring Control register is set.) Bit Name FAN_MIN_MSB Reset Bit FAN_MIN_MSB. Same as FAN_MIN_MSB of Fan Tachometer1 Low Limit LSB register, but for Fan Tachometer 4. Bit Name CRIT_LIMIT Reset Bit CRIT_LIMIT. The critical limit value to which the associated temperature input data is compared. If the temperature input data is higher than CRIT_LIMIT the corresponding bits in the HM Interrupt Status register, HM Sensor Status Register and Status Register are updated/set (see Section 8.4.10 on page 149, Section 8.4.12 on page 150, and Section 8.5.25 on page 166). CRIT_LIMIT format is the same as the format of the corresponding Temperature Reading Zone1 register (note that this format is configurable). The default value is 6Eh (110°C for 1°C resolution, 220°C for 2°C resolution). Bit Name CRIT_LIMIT Reset Bit CRIT_LIMIT. Same as CRIT_LIMIT in Temperature Critical Limit Zone1, but for Temperature Zone2. Bit Name CRIT_LIMIT Reset Bit CRIT_LIMIT. Same as CRIT_LIMIT in Temperature Critical Limit Zone1, but for Temperature Zone3. Winbond Electronics Corp. Advanced PC Product Center

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8.5.54 Monitoring Control

Location: 75h Type: R/W or RO (Becomes read-only when LOCK bit in the Configuration register is set.) Bit Name LOCK_LIM VOLT_HYST TEMP_HYST Reserved TEMP_FILT ZONE3_ RANGE ZONE2_ RANGE ZONE1_ RANGE Reset Bit LOCK_LIM. When set to 1, locks itself and the following HM Limit registers: Voltage Low Limit (2.5V, Vccp, 3.3V, 5V, 12V), Voltage High Limit (2.5V, Vccp, 3.3V, 5V, 12V), Temperature Low Limit Zone1-3, Temperature High Limit Zone1-3, Fan Tachometer1-4 Low Limit LSB, Fan Tachometer1-4 Low Limit MSB, Temperature Critical Limit Zone1-3. This bit is reset by Hardware reset. 0: All R/W HM Limit registers are enabled for write (default) 1: Specified HM Limit registers are RO VOLT_HYST (Voltage Channels, Hysteresis). Selects whether hysteresis is used when the voltage data in Voltage Reading registers is compared with the Voltage Low Limit and Voltage High Limit registers. 0: No hysteresis (default) 1: The hysteresis is equal to the LSBit multiplied by 4 of the (High or Low) Voltage Limit register TEMP_HYST (Temperature Channels, Hysteresis). Selects whether hysteresis is used when the temperature data in Temperature Reading registers is compared with the Temperature Low Limit, Temperature High Limit and Temperature Critical Limit registers. Temperature hysteresis value is independent on the setting of the ZONE1_RANGE bit (bit 0, below). 0: No hysteresis (default) 1: Hysteresis of 4°C Reserved. TEMP_FILT (Temperature Data Filter). Selects whether a low-pass filter is applied to the temperature data read from the LMxx Sensor device. If this bit is 1, the temperature data is filtered before it is stored in the Temperature Reading Zone ‘n’ register. 0: No filter (default) 1: A low-pass filter with 673 ms rise time (0% to 95% of the incoming temperature change) is applied to the tem- perature channels ZONE3_RANGE. Configures the temperature range shown in the Temperature Reading Zone3 register. The LSBit of the LMxx temperature MSByte represents a value of 2°C. When ZONE3_RANGE is 0, the LMxx temperature data is truncated to -127°C<=value<=127°C, with the LSB of the Temperature Reading register representing a value of 1°C. When ZONE3_RANGE is 1, the LMxx MSByte is translated to the Temperature Reading registers and represents a value such that -255°C<=value<=255°C, with the LSBit having a value of 2°C (see Figure 37 on page 158). Note: This bit is not relevant when an LM95010 device is used. 0: 1°C resolution for Temperature Reading register (default) 1: 2°C resolution for Temperature Reading register ZONE2_RANGE. Same as ZONE3_RANGE, but for Zone2. This bit is always relevant (i.e., it is not dependent on the LMxx device used). ZONE1_RANGE. Same as ZONE3_RANGE, but for Zone1. This bit is always relevant (i.e., it is not dependent on the LMxx device used). Winbond Electronics Corp. Advanced PC Product Center

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8.5.55 Channel VDD Configuration

Location: 79h Type: R/W or RO (Becomes read-only when LOCK bit in the Configuration register is set.) Bit Name ZONE3_VDD ZONE2_VDD ZONE1_VDD 12V_VDD 5V_VDD 3.3V_VDD Vccp_VDD 2.5V_VDD Reset Bit ZONE3_VDD. Is set to 1 to configure Zone3 Temperature Channel as a VDD channel. In this case, when the VDD3 supply is off, monitoring of this channel is disabled and all the status bits are reset to 0 (except for the flags asso- ciated with the channel’s critical limit). Monitoring is enabled and status bits are released, 182 ms after the VDD3 supply is turned back on. 0: Channel is not a VDD channel (default) 1: Channel is a VDD channel ZONE2_VDD. Is set to 1 to configure Zone2 Temperature Channel as a VDD channel. In this case, when the VDD3 supply is off, monitoring of this channel is disabled and all the status bits are reset to 0 (except for the flags asso- ciated with the channel’s critical limit). Monitoring is enabled and status bits are released, 182 ms after the VDD3 supply is turned back on. 0: Channel is not a VDD channel (default) 1: Channel is a VDD channel ZONE1_VDD. Is set to 1 to configure Zone1 Temperature Channel as a VDD channel. In this case, when the VDD3 supply is off, monitoring of this channel is disabled and all the status bits are reset to 0 (except for the flags asso- ciated with the channel’s critical limit). Monitoring is enabled and status bits are released, 182 ms after the VDD3 supply is turned back on. 0: Channel is not a VDD channel 1: Channel is a VDD channel (default) 12V_VDD. Is set to 1 to configure 12V Voltage Channel as a VDD channel. In this case, when the VDD3 supply is off, monitoring of this channel is disabled and all the status bits are reset to 0. Monitoring is enabled and status bits are released, 182 ms after the VDD3 supply is turned back on. 0: Channel is not a VDD channel (default) 1: Channel is a VDD channel 5V_VDD. Is set to 1 to configure 5V Voltage Channel as a VDD channel. In this case, when the VDD3 supply is off, monitoring of this channel is disabled and all the status bits are reset to 0. Monitoring is enabled and status bits are released, 182 ms after the VDD3 supply is turned back on. 0: Channel is not a VDD channel (default) 1: Channel is a VDD channel 3.3V_VDD. Is set to 1 to configure 3.3V Voltage Channel as a VDD channel. In this case, when the VDD3 supply is off, monitoring of this channel is disabled and all the status bits are reset to 0. Monitoring is enabled and status bits are released, 182 ms after the VDD3 supply is turned back on. 0: Channel is not a VDD channel (default) 1: Channel is a VDD channel Vccp_VDD. Is set to 1 to configure Vccp Voltage Channel as a VDD channel. In this case, when the VDD3 supply is off, monitoring of this channel is disabled and all the status bits are reset to 0. Monitoring is enabled and status bits are released, 182 ms after the VDD3 supply is turned back on. 0: Channel is not a VDD channel. 1: Channel is a VDD channel (default) 2.5V_VDD. Is set to 1 to configure 2.5V Voltage Channel as a VDD channel. In this case, when the VDD3 supply is off, monitoring of this channel is disabled and all the status bits are reset to 0. Monitoring is enabled and status bits are released, 182 ms after the VDD3 supply is turned back on. 0: Channel is not a VDD channel (default) 1: Channel is a VDD channel Winbond Electronics Corp. Advanced PC Product Center

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8.5.56 Temperature Zone1 Gain and Offset Correction

Temperature gain and offset correction for Zone1 temperature monitoring. Location: 7Dh Type: R/W (Becomes read-only when LOCK bit in the Configuration register is set.)

8.5.57 Temperature Zone2 Gain and Offset Correction

Temperature gain and offset correction for Zone2 temperature monitoring. Location: 7Eh Type: R/W (Becomes read-only when LOCK bit in the Configuration register is set.) Bit Name GAIN Reserved OFFSET Reset Bit GAIN (Gain Correction). Controls the gain correction applied to Zone1 temperature data. The incoming temperature data (after format modification, see Section 8.5.6 on page 157) is gain-corrected by multiplying by the gain correction value. Bits 7 6 Gain Correction Value 0 1: 1.0078125 dec. (1.0000001b) 0 0: (no gain correction - default) 1 1: 0.9921875 dec. (0.1111111b) 1 0: 0.9843750 dec. (0.1111110b) In case of a sensor connection error (for Remote Diode sensor only), the incoming temperature data is not correct- ed according to GAIN field (the temperature data is set to 80h). 5-4 Reserved. 3-0 OFFSET (Offset Correction). Contains the offset correction value that is added (with sign) to the Zone1 temperature data. The incoming temperature data (after format modification, see Section 8.5.6 on page 157) is offset-corrected. The binary value of OFFSET field is interpreted as 4-bit, 2’s complement value, with a resolution of 1°C/LSBit. The incoming temperature data is not corrected according to OFFSET field (i.e., the temperature data is set to 80h) if a sensor connection error occurs (for Remote Diode sensor only). Bits 3-0 Offset Value (for Sensor Types ‘01’ and ‘10’) 7h: +7°C 6h: +6°C . . . . 1h: +1°C 0h: 0°C (no offset correction - default) Fh: −1°C . . . . 9h: −7°C 8h: −8°C Bit Name GAIN Reserved OFFSET Reset Winbond Electronics Corp. Advanced PC Product Center

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8.5.58 Temperature Zone3 Gain and Offset Correction

Temperature gain and offset correction for Zone3 temperature monitoring. Location: 7Fh Type: R/W (Becomes read-only when LOCK bit in the Configuration register is set.)

8.5.59 Enhanced Thermal Control Register

Location: 80h Type: R/W (Becomes read-only when LOCK bit in the Configuration register is set.) Bit GAIN (Gain Correction). Same as GAIN in Temperature Zone1 Gain and Offset Correction register, but for Temperature Zone2. 5-4 Reserved. 3-0 OFFSET (Offset Correction). Same as OFFSET in Temperature Zone1 Gain and Offset Correction register, but for Temperature Zone2. Bit Name GAIN Reserved OFFSET Reset Bit GAIN (Gain Correction). Same as GAIN in Temperature Zone1 Gain and Offset Correction register, but for Temperature Zone3. 5-4 Reserved. 3-0 OFFSET (Offset Correction). Same as OFFSET in Temperature Zone1 Gain and Offset Correction register, but for Temperature Zone3. Bit Name Reserved ETC_EN Reset Bit ETC_EN. When set to 1, the ETC internal signal is asserted if one of the following conditions is true: The temperature data value in Temperature Zone1 is higher than the critical limit set in the Temperature Crit- ical Limit Zone1 register. A communication error with Device 1 (LM96011 or LM96010 or LM96012) occurs. A major SensorPath Bus failure is detected. An asserted ETC signal turns off the Main power supply (via the Glue module). The resulting ETC signal is disabled when the VDD3 power is off and remains disabled until both of the following conditions are met: The delay time (182 ms) for enabling VDD channels (see Section 8.5.55 on page 177) after VDD3 power is turned on, has elapsed. The temperature data in Temperature Zone1 was updated with a new value by the LMxx Sensor device If the temperature data from Device 1 (LM96011 or LM96010 or LM96012) is not updated for 728 ms after VDD3 power is on (see “Time-Out Function” on page 133), the HM assumes a communication error with the LMxx Sensor device occurred and asserts ETC. 0: Disable assertion of ETC 1: Enable assertion of ETC (default) Winbond Electronics Corp. Advanced PC Product Center

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8.5.60 Tach Mode

Location: 43h Type: R/W Table 55. Fan Monitoring Configuration

8.5.61 Tachometer Monitoring Control

Reserved. 3-0 FAN4_MODE-FAN1_MODE. Sets Fan4-Fan1 monitoring mode according to Table 55. FANn_MODE Measurements performed independently of any FANPWM output (default). Each measurement lasts one or two tachometer cycles, according to TPPR bit in Tachometer Monitoring Control register. Measurements performed when the associated1 FANPWM is at “On” level. The “On” level of the FANPWM signal can be extended to 1/2, one or two tachometer cycles, according to TPPR bit. A successful measurement requires only 1/2 a tachometer cycle. 1. See Tach PWM Association Register in Section 8.5.62 on page 181. Bit Name Reserved TPPR4 TPPR3 TPPR2 TPPR1 Reset Bit Reserved. TPPR4 (Tachometer Pulses Per Revolution 4). Selects the number of pulses per fan revolution generated by FANTACH4 (and thus the division factor for the normalization of the fan speed data in the Fan Tachometer Reading 4 registers). 0: Two pulses per revolution (default) 1: One pulse per revolution TPPR3 (Tachometer Pulses Per Revolution 3). Same as TPPR4, but for FANTACH3. TPPR2 (Tachometer Pulses Per Revolution 2). Same as TPPR4, but for FANTACH2. TPPR1 (Tachometer Pulses Per Revolution 1). Same as TPPR4, but for FANTACH1. Winbond Electronics Corp. Advanced PC Product Center

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8.5.62 Tach PWM Association

Location: 6Fh Type: R/W Table 56. Fan Monitoring Association

8.5.63 Zone1 Temperature Limit

ASSOC4. Sets FANTACH4 monitoring association with a PWM output according to Table 56 (default 10b). 5-4 ASSOC3. Sets FANTACH3 monitoring association with a PWM output according to Table 56 (default 10b). 3-2 ASSOC2. Sets FANTACH2 monitoring association with a PWM output according to Table 56 (default 01b). 1-0 ASSOC1. Sets FANTACH1 monitoring association with a PWM output according to Table 56 (default 00b). ASSOC Meaning Measurements associated with FANPWM1 Measurements associated with FANPWM2 Measurements associated with FANPWM3 FANTACH is not associated with any FANPWM1 1. Use this value for the fans that are not connected or that do not have tachom- eter output. Bit Name ZTEMP_LOW Reset Bit ZTEMP_LOW. Selects the temperature value for the low limit of the area in which the generated FANPWM duty cycle is proportional to the zone temperature. When the associated temperature equals this limit the fan is turned on (if it is not on already). When the temperature exceeds this limit, the fan speed will increase linearly as a function of temperature over the range defined in the associated Zone1 Auto Speed Range and FANPWM1 Frequency register (see Section 8.5.71 on page 183). The format of ZTEMP_LOW field is 8-bit left-aligned 2’s complement value with the LSB being 1°C or 2°C, according to the setting of the ZONE1_RANGE bit in the Monitor Control Register (see Section 8.5.54 on page 176). Valid values for this field are: 81h (-127°C) to 7Fh (+127°C) for 1°C resolution, and 81h (-254°C) to 7Fh (+254°C) for 2°C resolution. A value of 80h is invalid. Winbond Electronics Corp. Advanced PC Product Center

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8.5.64 Zone2 Temperature Limit

Location: 68h Type: R/W or RO (Becomes read-only when LOCK bit in the Configuration register is set.)

8.5.65 Zone3 Temperature Limit

Location: 69h Type: R/W or RO (Becomes read-only when LOCK bit in the Configuration register is set.)

8.5.66 Zone1 Absolute Temperature Limit

Location: 6Ah Type: R/W or RO (Becomes read-only when LOCK bit in the Configuration register is set.)

8.5.67 Zone2 Absolute Temperature Limit

Location: 6Bh Type: R/W or RO (Becomes read-only when LOCK bit in the Configuration register is set.) Bit Name ZTEMP_LOW Reset Bit ZTEMP_LOW. Same as ZTEMP_LOW in Zone1 Temperature Limit register, but for Zone2. Bit Name ZTEMP_LOW Reset Bit ZTEMP_LOW. Same as ZTEMP_LOW in Zone1 Temperature Limit register, but for Zone3. Bit Name ZTEMP_ABS Reset Bit ZTEMP_ABS. Selects the temperature value for the absolute limit. When the associated zone temperature is above the absolute limit, the duty cycle of all the FANPWM outputs is forced to full on (i.e., the value contained in the FANPWM1 MAX Duty register). When the zone temperature returns below the absolute limit, an 8°C hysteresis is provided. ZTEMP_ABS format is the same as the format of the corresponding Temperature Reading Zone1 register (see Section 8.5.6 on page 157). This format is dependent on the setting of the ZONE1_RANGE bit in the Monitor Control Register (see Section 8.5.54 on page 176). The default value is 64h (100°C for 1°C resolution, 200°C for 2°C reso- lution). Valid values for this field are from 81h to 7Fh. A value of 80h disables the Absolute Limit. Bit Name ZTEMP_ABS Reset Bit ZTEMP_ABS. Same as ZTEMP_ABS in Zone1 Absolute Temperature Limit register, but for Zone2. Winbond Electronics Corp. Advanced PC Product Center

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8.5.68 Zone3 Absolute Temperature Limit

Location: 6Ch Type: R/W or RO (Becomes read-only when LOCK bit in the Configuration register is set.)

8.5.69 Zone1, Zone2 Hysteresis

Location: 6Dh Type: R/W or RO (Becomes read-only when LOCK bit in the Configuration register is set.)

8.5.70 Zone3 Hysteresis

Location: 6Eh Type: R/W or RO (Becomes read-only when LOCK bit in the Configuration register is set.)

8.5.71 Zone1 Auto Speed Range and FANPWM1 Frequency

Location: 5Fh Type: R/W or RO (Becomes read-only when LOCK bit in the Configuration register is set.) Bit Name ZTEMP_ABS Reset Bit ZTEMP_ABS. Same as ZTEMP_ABS in Zone1 Absolute Temperature Limit register, but for Zone3. Bit Name HYST1 HYST2 Reset Bit HYST1. Selects the temperature value of the hysteresis used to process the associated zone temperature when the temperature is lower than the low limit set in Zone1 Temperature Limit register. If the temperature falls from above the Limit to below it, the fan remains at the minimum FANPWM duty cycle until the temperature has fallen an hysteresis amount below the Limit. Value 0d: No hysteresis 1d-15d: Hysteresis of 1°C to 15°C (default = 4°C) 3-0 HYST2. Same as HYST1, but for Zone2. Bit Name HYST3 Reserved Reset Bit HYST3. Same as HYST1 in Zone1, Zone2 Hysteresis register, but for Zone3. 3-0 Reserved. Bit Name RANGE FREQ Reset Winbond Electronics Corp. Advanced PC Product Center

www.national.com 184 Revision1.1 PC8374L Bit Range. Sets temperature range over which the associated FANPWM duty cycle is changed linearly as a function of temperature. The lower temperature limit of this range is determined, according to the Min/Off bit in the associated Min/Off, Spike Smoothing register, either by the associated Zone Temperature Limit (see Section 8.5.63 on page 181) whose the duty cycle is 0 or by the value in the associated FANPWM Minimum Duty. The upper temperature limit of this range is “Zone Temperature Limit” + Range. At this limit, the duty cycle is the value contained in the FANPWM1 MAX Duty register. The range is set according to Table 57. 3-0 FREQ. Sets FANPWM frequency selection according to Table 58. Winbond Electronics Corp. Advanced PC Product Center

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8.5.72 Zone2 Auto Speed Range and FANPWM2 Frequency

Location: 60h Type: R/W or RO (Becomes read-only when LOCK bit in the Configuration register is set.)

8.5.73 Zone3 Auto Speed Range and FANPWM3 Frequency

Location: 61h Type: R/W or RO (Becomes read-only when LOCK bit in the Configuration register is set.) Table 57. Range Configuration Table 58. PWM Configuration

38 Hz (default)

23.5 KHz

26.8 KHz

31.2 KHz

37.5 KHz

47 KHz

Range. Same as Range in Zone1 Auto Speed Range and FANPWM2 Frequency register, but for Zone2. 3-0 FREQ. Sets FANPWM frequency selection according to Table 58 on page 185. Bit Name RANGE FREQ Reset Bit Range. Same as Range in Zone1 Auto Speed Range and FANPWM2 Frequency register, but for Zone3. 3-0 FREQ. Sets FANPWM frequency selection according to Table 58 on page 185. Winbond Electronics Corp. Advanced PC Product Center

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8.5.74 Min/Off, Spike Smoothing 1

Location: 62h Type: R/W or RO (Becomes read-only when LOCK bit in the Configuration register is set.) Table 59. Temperature Filtering Configuration

8.5.75 Min/Off, Spike Smoothing 2

MIN_EN3. Enables using Minimum PWM Duty Cycle 3 (see Section 8.5.81 on page 189) for FANPWM3 when the measured temperature falls below the Zone ‘n’ Temperature Limit register. 0: FANPWM duty cycle at 0% when the temperature is below limit (default) 1: FANPWM duty cycle at Minimum PWM Duty Cycle when the temperature is below limit MIN_EN2. Enables using Minimum PWM Duty Cycle 2 (see Section 8.5.80 on page 189) for FANPWM2 when the measured temperature falls below the Zone ‘n’ Temperature Limit register. 0: FANPWM duty cycle at 0% when the temperature is below limit (default) 1: FANPWM duty cycle at Minimum PWM Duty Cycle when the temperature is below limit MIN_EN1. Enables using Minimum PWM Duty Cycle 1 (see Section 8.5.79 on page 189) for FANPWM1 when the measured temperature falls below the Zone ‘n’ Temperature Limit register. 0: FANPWM duty cycle at 0% when the temperature is below limit (default) 1: FANPWM duty cycle at Minimum PWM Duty Cycle when the temperature is below limit Reserved. FILT1_EN. Enable temperature filtering for Zone1. 2-0 TEMP_FILT1. Sets temperature low-pass filtering for temperature input to FANPWM1 Duty Cycle generator according to Table 59 on page 186. Filter rise time is from 0% to 95% of the input temperature change. This field may be changed only when the START bit in Configuration register is set to 0. TEMP_FILT Rise Time [sec] ‘000’ 24.4(default) ‘001’ 13.8 ‘010’ 8.4 ‘011’ 6.4 ‘100’ 3.6 ‘101’ 1.4 ‘110’ 1.0 ‘111’ 0.62 Bit Name FILT2_EN TEMP_FILT2 FILT3_EN TEMP_FILT3 Reset Bit FILT2_EN. Enable temperature filtering for Zone2. Winbond Electronics Corp. Advanced PC Product Center

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8.5.76 FANPWM1 Control Configuration

Location: 5Ch Type: Varies per bit (The R/W bits become read-only when LOCK bit in the Configuration register is set.) Table 60. Fan Operating Mode Configuration changed only when the START bit in Configuration register is set to 0. FILT3_EN. Enable temperature filtering for Zone3. changed only when the START bit in Configuration register is set to 0. MODE. Sets fan operation mode and temperature zone association according to Table 60. In Auto Mode the FANPWM duty cycle is controlled by the temperature data supplied by the associated Zone or by the hottest of the associated Zones. In Manual Mode the FANPWM is controlled by the contents of the associated PWM Current Duty Register. WO INV (FANPWM1 Output Invert). Sets polarity of FANPWM1 output signal. The value of INV is reflected by the respective (read-only) FANOUTn_INV bit in the HMCFG1 register (see Section 3.15.3 on page 79). INV bit is write-only; reading it returns an unpredictable value. 0: Normal signal - 100% duty cycle represents a high-level signal (default) 1: Inverted signal - 100% duty cycle represents a low-level signal 3-0 R/W or RO SPIN. Sets maximum spin-up time according to Table 61. During spin-up, the FANPWM duty cycle is the value contained in the associated FANPWMn MAX Duty register. MODE Meaning ‘000’ FANPWM on Zone1 auto ‘001’ FANPWM on Zone2 auto ‘010’ FANPWM on Zone3 auto ‘011’ FANPWM always on full (default) ‘100’ FANPWM disabled ‘101’ FANPWM controlled by hottest of zones 2,3 ‘110’ FANPWM controlled by hottest of zones 1,2,3 ‘111’ FANPWM manually controlled Bit Winbond Electronics Corp. Advanced PC Product Center

www.national.com 188 Revision1.1 PC8374L Table 61. Spin-Up Configuration

8.5.77 FANPWM2 Control Configuration

8.5.78 FANPWM3 Control Configuration

MODE. Same as MODE in FANPWM1 Control Configuration register, but for FANPWM2. WO INV (FANPWM2 Output Invert). Same as INV in FANPWM1 Control Configuration register, but for FANPWM2. 3-0 R/W or RO SPIN. Same as SPIN in FANPWM1 Control Configuration register, but for FANPWM2. Bit Name MODE INV SPIN Reset Bit Type MODE. Same as MODE in FANPWM1 Control Configuration register, but for FANPWM3. WO INV (FANPWM3 Output Invert). Same as INV in FANPWM1 Control Configuration register, but for FANPWM3. 3-0 R/W or RO SPIN. Same as SPIN in FANPWM1 Control Configuration register, but for FANPWM3. Winbond Electronics Corp. Advanced PC Product Center

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8.5.79 FANPWM1 Minimum

Location: 64h Type: R/W or RO (Becomes read-only when LOCK bit in the Configuration register is set.)

8.5.80 FANPWM2 Minimum

Location: 65h Type: R/W or RO (Becomes read-only when LOCK bit in the Configuration register is set.)

8.5.81 FANPWM3 Minimum

Location: 66h Type: R/W or RO (Becomes read-only when LOCK bit in the Configuration register is set.)

8.5.82 FANPWM1 Maximum Duty

FANPWM1 maximum duty cycle. Location: 70h Type: R/W or RO (Becomes read-only when LOCK bit in the Configuration register is set.) Bit Name PWM_MIN Reset Bit PWM_MIN. Holds the value of the minimum duty cycle of the FANPWM signal. This value is used to generate the FANPWM output in Automatic mode if the zone temperature is lower than the low limit set in the associated Zone Temperature Limit register and the associated MIN_EN bit in the associated Min/Off, Spike Smoothing register is set to 1. The default is 80h=50% duty cycle. Bit Name PWM_MIN Reset Bit PWM_MIN. Same as PWM_MIN in FANPWM1 Minimum register, but for FANPWM2. Bit Name PWM_MIN Reset Bit PWM_MIN. Same as PWM_MIN in FANPWM1 Minimum register, but for FANPWM3. Bit Name MAX_PWM Reset Bit MAX_PWM. Holds the maximum allowed duty-cycle for the associated FANPWM signal. It affects all modes except manual mode (in manual mode, the maximum allowed duty-cycle is always 100%). A value of 01h represents 0.4% duty cycle, a value of FFh represents 100% duty cycle. The value 00h is reserved. The default is 100% duty-cycle. Note: After START bit in the Configuration register is set, changes to this register take effect only when the FANPWM1 duty cycle is updated. Winbond Electronics Corp. Advanced PC Product Center

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8.5.83 FANPWM2 Maximum Duty

FANPWM2 maximum duty cycle. Location: 71h Type: R/W or RO (Becomes read-only when LOCK bit in the Configuration register is set.)

8.5.84 FANPWM3 Maximum Duty

FANPWM3 maximum duty cycle. Location: 72h Type: R/W or RO (Becomes read-only when LOCK bit in the Configuration register is set.)

8.5.85 Extended FANPWM Control 1

Location: 76h Type: R/W or RO (Becomes read-only when LOCK bit in the Configuration register is set.) Bit Name MAX_PWM Reset Bit MAX_PWM. Same as MAX_PWM of FANPWM1 Maximum Duty register, but for FANPWM2. Bit Name MAX_PWM Reset Bit MAX_PWM. Same as MAX_PWM of FANPWM1 Maximum Duty register, but for FANPWM3. Bit Name Reserved FSTLMD SPIN_END SPIN_DUTY STEP_LEN Reset Bit Reserved. FSTLMD (FAN_STALL Mode). Selects the fan conditions causing the detection of a fan failure, which sets both the FANn_STALL status bit in the Status Register 2 (see Section 8.5.24 on page 165), and the FANn_STS bit in the HM Sensor Status Register 2 (see Section 8.4.9 on page 148) to 1. 0: Either a fan stalled condition or a low speed condition, whichever occurs first (default) 1: A fan stalled condition only Winbond Electronics Corp. Advanced PC Product Center

Revision 1.1 191 www.national.com PC8374L

8.5.86 Extended FANPWM Control 2

Location: 77h Type: R/W or RO (Becomes read-only when LOCK bit in the Configuration register is set.) SPIN_END (Spin-Up End Select). Selects the condition used by the HM to end the spin-up process. When the condition is met, the spin-up process ends and the FANPWM duty cycle is set to one of the following values: The value set in FANPWMn Current Duty register, in Manual Fan Control mode The value generated from the current normalized temperature by the automatic algorithm, in Automatic Fan Control mode (this value is updated in the FANPWMn Current Duty register) The value set in FANPWMn MAX Duty register, in Continuously On mode The conditions are: 0: Whichever occurs first: either the spin-up time (set in SPIN field in the FANPWMn Control Configuration regis- ter) has ended or the current fan speed is equal to or higher than either the minimum value of all the associated Fan Tachometer ‘n’ Low Limit (LSB and MSB) registers. 1: Spin-up time has ended (default). SPIN_DUTY. Determines the value shown in the FANPWM1-3 Current Duty registers (see Section 8.5.17 on page 161 to Section 8.5.19) during spin-up. 0: FANPWMn Current Duty registers show 0 during spin-up (default) 1: FANPWMn Current Duty registers show the target duty cycle during spin-up 3-0 STEP_LEN. The step length used for soft speed-change of the FANPWM duty-cycle (the steps performed above the minimum duty cycle value). 00h: Reserved 01h - 0Fh: The duration of a “soft” step equals the STEP_LEN value, multiplied by 22.75 ms (default is 08h=182 ms) Bit Name Reserved SPD_CHG3 SPD_CHG2 SPD_CHG1 Reset Bit Reserved. SPD_CHG3. Sets the speed-change mode for FANPWM3 output for all fan control modes. 0: Hard speed change - the speed change is done in one single and immediate step (default) 1: Soft speed change - speed change is done in steps of 3.125% duty-cycle Note: Speed change between a duty-cycle of 0% and the minimum duty-cycle (which is defined in the FANPWM3 Minimum register) is done in one immediate step. SPD_CHG2. Same as SPD_CHG3 for FANPWM2. SPD_CHG1. Same as SPD_CHG3 for FANPWM1. Bit Winbond Electronics Corp. Advanced PC Product Center

www.national.com 192 Revision1.1 PC8374L 9.0 Legacy Functional Blocks This chapter briefly describes the following blocks, which provide legacy device functions:

• Floppy Disk Controller (FDC)
• Parallel Port (PP)
• Serial Port1 and 2 (SP1 and SP2)
• Keyboard and Mouse Controller (KBC) For details on the general implementation of each legacy block, see the SuperI/O Legacy Functional Blocks Datasheet. The register maps in this chapter use the following abbreviations for Type:
• R/W = Read/Write. = Read from register (write to the same address is to a different register). = Write (see above).
• RO = Read-only.
• WO = Write-only. Reading from the bit returns 0.
• R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.
• R/W1S = Read/Write 1 to Set. Writing 1 to a bit sets its value to 1. Writing 0 has no effect.

9.1 FLOPPY DISK CONTROLLER (FDC)

9.1.1 General Description The generic FDC is a standard FDC with a digital data separator; it is software compatible with the µDP8473 and N82077. The PC8374L FDC supports 14 of the 17 standard FDC signals described in the generic Floppy Disk Controller (FDC) chap- ter, including:

• FDC supports FM and MFM modes. To select either mode, set bit 6 of the first command byte when writing to/reading from a diskette, where: — 0 = FM mode — 1 = MFM mode
• A logic 1 is returned during LPC I/O read cycles by all register bits, reflecting the state of floating (TRI-STATE) FDC pins. Exceptions to standard FDC are:
• Automatic media sense using MSEN0 and MSEN1 signals is not supported.
• DRATE1 is not supported.
• DR1 is not supported.
• MTR1 is not supported. Winbond Electronics Corp. Advanced PC Product Center

9.0 Legacy Functional Blocks (Continued)

Table 62 lists the FDC functional block registers. All registers are VDD3 powered. fields in all registers are valid in both operation modes. Table 62. FDC Register Map

1. From the 8-byte aligned FDC base address.

Table 63. FDC Bitmap Summary

1. Applicable only in PS/2 Mode.
2. Applicable only in Enhanced TDR Mode.
3. Applicable only in PC-AT Compatible Mode.

9.2 PARALLEL PORT

• Compatibility (known also as Standard or SPP)
• Bi-directional (known also as PS/2)
• FIFO
• EPP (known also as Mode 4)
• ECP (with an optional Extended ECP mode) 9.2.2 Parallel Port Register Map The Parallel Port includes two groups of runtime registers, as follows:
• A group of 21 registers at first level offset, sharing 14 entries. Three of these registers (at offsets 403h, 404h and 405h) are used only in Extended ECP mode.
• A group of four registers, used only in Extended ECP mode, accessed by a second level offset. EPP and second level offset registers are available only when the base address is 8-byte aligned. The desired mode is selected by the ECR runtime register (offset 402h). The selected mode determines which runtime reg- isters and which address bits are used for the base address. See Tables 64 and 65 for a listing of all registers, their offset addresses and the associated modes. All registers are VDD3 powered.

Table 64. Parallel Port Registers at First Level Offset

1. These registers are extended to the standard IEEE1284 registers. They are

(see Section 3.9.3 on page 64).

The Parallel Port functional block bitmaps are grouped according to first and second level offsets. Table 65. Parallel Port Registers at Second Level Offset Table 66. Parallel Port Bitmap Summary for First Level Offset

9.3 SERIAL PORT 1 (SP1)

• 16450-Compatible mode (Standard 16450)
• 16550-Compatible mode (Standard 16550)
• Extended mode Extended mode provides advanced functionality for the UART. The Serial Port provides receive and transmit channels that can operate concurrently in full-duplex mode. It performs all functions required to conduct parallel data interchange with the system and composite serial data exchange with the external data channel, including:
• Format conversion between the internal parallel data format and the external programmable composite serial format
• Serial data timing generation and recognition
• Parallel data interchange with the system using a choice of bidirectional data transfer mechanisms
• Status monitoring for all phases of communication activity
• Complete MODEM-control capability. Existing 16550-based legacy software is completely and transparently supported. Module organization and specific fallback mechanisms switch the module to 16550-Compatible mode on reset or when initialized by 16550 software. 9.3.2 Register Bank Overview Four register banks, each containing eight registers, control Serial Port operation. All registers use the same 8-byte address space to indicate offsets 00h through 07h. The active bank must be selected by the software. The register bank organization enables access to the banks as required for activation of all module modes, while maintaining transparent compatibility with 16450 or 16550 software. The Bank Selection register (BSR) selects the active bank and is common to all banks as shown in Figure 38. Therefore, each bank defines seven new registers. The default bank selection after system reset is 0.

Table 67. Parallel Port Bitmap Summary for Second Level Offset

Figure 38. Register Bank Architecture Table 68. Bank 0 Register Map

16550 Banks

Table 69. Bank 1 Register Map Table 70. Bank 2 Register Map Table 71. Bank 3 Register Map

Table 72. Bank 0 Bitmap Table 73. Bank 1 Bitmap

9.4 SERIAL PORT 2 (SP2)

IR. For device specific implementation, see Device Architecture and Configuration in the datasheet of the relevant device. anisms switch the Serial Port to 16550-Compatible mode on reset, or when initialized by 16550 software. speed, full duplex, UART based applications. space to indicate offsets 00h-07h. The active bank must be selected by the software. transparent compatibility with 16450 or 16550 software. defines seven new registers. The default bank selection after system reset is 0. Table 74. Bank 2 Bitmap Table 75. Bank 3 Bitmap

Figure 39. SP2 Register Bank Architecture banks 4-7 control and configure the IR modes only. Table 76. Register Bank Summary

• R/W = Read/Write
• R = Read from a specific address returns the value of a specific register. Write to the same address is to a different register.
• W = Write
• RO = Read-Only
• R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect. Bank UART Mode IR Mode Main Functions Global Control and Status Legacy Bank Alternative Baud Generator Divisor, Extended Control and Status Module Revision ID and Shadow registers IR mode setup IR Control IR Physical Layer Configuration CEIR and Optical Transceiver Configuration BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7 Offset 07h Offset 06h Offset 05h Offset 04h LCR/BSR Offset 02h Offset 01h Offset 00h Common Register Throughout All Banks IR Special Banks (Banks 4-7) Winbond Electronics Corp. Advanced PC Product Center

Table 77. Bank 0 Register Map Table 78. Bank 1 Register Map Table 79. Bank 2 Register Map

Table 80. Bank 3 Register Map Table 81. Bank 4 Register Map Table 82. Bank 5 Register Map Table 83. Bank 6 Register Map Table 84. Bank 7 Register Map

Table 85. Bank 0 Bitmap Table 86. Bank 1 Bitmap

Table 87. Bank 2 Bitmap Table 88. Bank 3 Bitmap Table 89. Bank 4 Bitmap Table 90. Bank 5 Bitmap

9.5 SERIAL PORT 2 (SP2) WITH INFRARED

Compatible mode, or Extended mode. anisms switch the Serial Port to 16550-Compatible mode on reset, or when initialized by 16550 software. space to indicate offsets 00h through 07h. The active bank must be selected by the software. transparent compatibility with 16450 or 16550 software. defines seven new registers. Table 91. Bank 6 Bitmap Table 92. Bank 7 Bitmap

The default bank selection after system reset is 0. Figure 40. Register Bank Architecture banks 4-7 control and configure the IR modes only. Table 93. Register Bank Summary All registers are VDD3 powered. Table 94. Bank 0 Register Map

Table 95. Bank Selection Encoding Table 96. Bank 1 Register Map

Table 97. Bank 2 Register Map Table 98. Bank 3 Register Map Table 99. Bank 4 Register Map Table 100. Bank 5 Register Map Table 101. Bank 6 Register Map

standard 8042AH keyboard controller. The 8042AH datasheet can be used as a detailed technical reference for the KBC. P23, P26, P27, T0 and T1 are used to implement the keyboard and mouse interface. ware, except for the IRQ type and number, which are set by configuration registers (see Section 3.2.3 on page 39). latched in the output registers of the ports.

1. Set the appropriate port bit to issue an interrupt request.

Table 102. Bank 7 Register Map

Figure 41. Keyboard and Mouse Interfaces All registers are VDD3 powered. Table 103. KBC Register Map Table 104. KBC Bitmap Summary

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10.1 GENERAL DC ELECTRICAL CHARACTERISTICS

10.1.1 Recommended Operating Conditions

10.1.2 Absolute Maximum Ratings

Absolute maximum ratings are values beyond which damage to the device may occur. Unless otherwise specified, all volt- ages are relative to ground (VSS).

10.1.3 Capacitance

3.0 3.3 3.6 V VSB3 Standby 3V Supply Voltage 3.0 3.3 3.6 V VBAT Battery Backup Supply Voltage 2.4 3.0 3.6 V TA Operating Temperature +70 Symbol Parameter Conditions Min Max Unit VSUP Supply Voltage1 1. VSUP is VDD3, VSB3. −0.5 +4.1 V VI Input Voltage All other pins −0.5 5.5 V LAD3-0, LFRAME, SERIRQ −0.5 VDD3 + 0.5 V VO Output Voltage All other pins −0.5 5.5 V LAD3-0, LDRQ, SERIRQ −0.5 VDD3 + 0.5 V TSTG Storage Temperature −65 +165 PD Power Dissipation W TL Lead Temperature Soldering (10 s) +260 ESD Tolerance CZAP = 100 pF RZAP = 1.5 KΩ2 2. Value based on test complying with RAI-5-048-RA human body model ESD testing. 2000 V Symbol Parameter Conditions Min2 Typ1 1. TA = 25°C; f = 1 MHz. Max2 2. Not tested. Guaranteed by characterization. Unit CIN Input Pin Capacitance pF CINC LPC Clock Input Capacitance PCI_CLK pF CPCI LPC Pin Capacitance LAD3-0, LFRAME, PCI_RESET, SERIRQ, LDRQ pF CIO I/O Pin Capacitance pF CO Output Pin Capacitance pF Winbond Electronics Corp. Advanced PC Product Center

10.0 Device Characteristics (Continued)

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10.1.4 Power Consumption under Recommended Operating Conditions

10.1.5 Voltage Thresholds

10.2 DC CHARACTERISTICS OF PINS, BY I/O BUFFER TYPES

The following tables summarize the DC characteristics of all device pins described in Section 1.2 on page 15. The characteristics describe the general I/O buffer types defined in Table 1 on page 15. For exceptions, refer to Section 10.2.13 on page 217. The DC characteristics of the LPC interface meet the PCI Local Bus Specification (Rev 2.2 December 18, 1998) for 3.3V DC signaling.

10.2.1 Input, TTL Compatible

Symbol: INT Symbol Parameter Conditions1 1. All parameters specified for 0°C ≤ TA ≤ 70°C; VDD3 and VSB3 = 3.3V ±10% unless otherwise specified. Typ Max2 2. Not tested. Guaranteed by characterization. Unit IDD3 VDD3 Average Supply Current VIL = 0.5V, VIH = 2.4V, No Load mA IDD3LP VDD3 Quiescent Supply Current in Low Power Mode3 3. All the modules disabled; no LPC bus activity. VIL = VSS, VIH = VDD3, No Load 0.5 0.8 mA ISB3 VSB3 Average Supply Current VIL = 0.5V, VIH = 2.4V, No Load mA ISB3LP VSB3 Quiescent Supply Current in Low Power Mode3 VIL = VSS, VIH = VSB3, No Load TBD mA IBAT VBAT Battery Supply Current VDD3, VSB3 = 0V, VBAT = 3V 0.2 0.4 µA Symbol Parameter1 1. All parameters specified for 0°C ≤ TA ≤ 70°C. Min2 2. Not tested. Guaranteed by characterization. Typ Max2 Unit VDD3ON VDD3 Detected as Power-on 2.3 2.6 2.9 V VDD3OFF VDD3 Detected as Power-off 2.1 2.5 2.8 V VSB3ON VSB3 Detected as Power-on 2.3 2.6 2.9 V VSB3OFF VSB3 Detected as Power-off 2.1 2.5 2.8 V VBATLOW VBAT Detected as “Low” 2.3 V Symbol Parameter Conditions Min Max Unit VIH Input High Voltage 2.0 5.51 1. Not tested. Guaranteed by design. V VIL Input Low Voltage −0.51 0.8 V IIL 2. Input leakage current includes the output leakage of the bi-directional buffers with TRI-STATE outputs. Input Leakage Current 0 < VIN < VSUP 3. VSUP is VDD3 or VSB3 according to the input power well. µA Winbond Electronics Corp. Advanced PC Product Center

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10.2.2 Input, TTL Compatible, with Schmitt Trigger

Symbol: INTS

10.2.3 Input, TTL Compatible, with 200 mV Schmitt Trigger

Symbol: INTS2

10.2.4 Input, TTL Compatible, with 400 mV Schmitt Trigger

Symbol: INTS4 Symbol Parameter Conditions Min Max Unit VIH Input High Voltage 2.0 5.51 1. Not tested. Guaranteed by design. V VIL Input Low Voltage −0.51 0.8 V VHY Input Hysteresis 2502 2. Not tested. Guaranteed by characterization. mV IIL 3. Input leakage current includes the output leakage of the bi-directional buffers with TRI-STATE outputs. Input Leakage Current 0 < VIN < VSUP 4. VSUP is VDD3 or VSB3 according to the input power well. µA Symbol Parameter Conditions Min Max Unit VIH Input High Voltage 2.0 5.51 1. Not tested. Guaranteed by design. V VIL Input Low Voltage −0.51 0.8 V VHY Input Hysteresis 2002 2. Not tested. Guaranteed by characterization. mV IIL 3. Input leakage current includes the output leakage of the bi-directional buffers with TRI-STATE outputs. Input Leakage Current 0 < VIN < VSUP 4. VSUP is VDD3 or VSB3 according to the input power well. µA Symbol Parameter Conditions Min Max Unit VIH Input High Voltage 2.0 5.51 1. Not tested. Guaranteed by design. V VIL Input Low Voltage −0.51 0.8 V VHY Input Hysteresis 4002 2. Not tested. Guaranteed by characterization. mV IIL 3. Input leakage current includes the output leakage of the bi-directional buffers with TRI-STATE outputs. Input Leakage Current 0 < VIN < VSUP 4. VSUP is VDD3 or VSB3 according to the input power well. µA Winbond Electronics Corp. Advanced PC Product Center

Revision 1.1 215 www.national.com PC8374L 10.2.5 Input, PCI 3.3V Compatible Symbol: INPCI

10.2.6 Input, SMBus Compatible

Symbol: INSM

10.2.7 Analog Input

Symbol: AI

10.2.8 Output, TTL/CMOS Compatible, Push-Pull Buffer

Symbol: Op/n Output, TTL/CMOS Compatible, rail-to-rail push-pull buffer that is capable of sourcing p mA and sinking n mA Symbol Parameter Conditions Min Max Unit VIH Input High Voltage

0.5 VDD

VDD + 0.51 1. Not tested. Guaranteed by design. V VIL Input Low Voltage −0.51

0.3 VDD

V lIL 2. Input leakage current includes the output leakage of the bi-directional buffers with TRI-STATE outputs. Input Leakage Current 0 < VIN < VDD3 µA Symbol Parameter Conditions Min Max Unit VIH Input High Voltage 1.4 5.51 1. Not tested. Guaranteed by design. V VIL Input Low Voltage −0.51 0.8 V IIL 2. Input leakage current includes the output leakage of the bidirectional buffers with TRI-STATE outputs. Input Leakage Current 0 < VIN < VSB µA Symbol Parameter Conditions Min Max Unit VIR Input Voltage Range 5.51 1. Not tested. Guaranteed by characterization. V lIL Input Leakage Current VIN = VIR 300 µA Symbol Parameter Conditions Min Max Unit VOH Output High Voltage IOH = −p mA 2.4 V IOH = −50 µA VSUP −0.21 1. VSUP is VDD3 or VSB3 according to the output power well. V VOL Output Low Voltage IOL = n mA 0.4 V IOL = 50 µA 0.2 V Winbond Electronics Corp. Advanced PC Product Center

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10.2.9 Output, TTL/CMOS Compatible, Open-Drain Buffer

Symbol: ODn Output, TTL/CMOS-compatible open-drain output buffer capable of sinking n mA. Output from these signals is open- drain and is never forced high. 10.2.10 Output, PCI 3.3V Compatible Symbol: OPCI 10.2.11 Analog Output Symbol: AO 10.2.12 Input/Output Switch, SMBus Compatible Symbol: SWSM Symbol Parameter Conditions Min Max Unit VOL Output Low Voltage IOL = n mA 0.4 V IOL = 50 µA 0.2 V Symbol Parameter Conditions Min Max Unit VOH Output High Voltage lout = −500 µA

0.9 VDD3

V VOL Output Low Voltage lout = 1500 µA

0.1 VDD3

V Symbol Parameter Conditions Min Max Unit VOR Output Voltage Range 5.51 1. Not tested. Guaranteed by characterization. V VOD Output Drive Voltage lout = −3.6 mA VSUP 2 −150 mV 2. VSUP is VDD3 or VSB3 according to the pin power well. lOL Output Leakage Current VOUT = VOR, VSUP < VOUT µA Symbol Parameter Conditions Min Max Unit VDRP Pin-to-Pin Voltage Drop ISW = ±3 mA, Switch Closed 1501 1. Not tested. Guaranteed by characterization. mV VISC Input Voltage for Switch Closed ISW = ±3 mA 1.51 V VISO Input Voltage for Switch Open ISW = ±20 µA 2.25 V IIL Input Leakage Current VISO < VIN < 5.5V ±201 µA Winbond Electronics Corp. Advanced PC Product Center

Revision 1.1 217 www.national.com PC8374L 10.2.13 Exceptions 1. All pins are 5V tolerant except for the output pins with PCI (OPCI) buffer types. 2. All pins are back-drive protected except for the output pins with PCI (OPCI) buffer types. 3. The following pins have an internal static pull-up resistor (when enabled) and therefore may have leakage current from VSUP (when VIN = 0): SWD, ACK, AFD_DSTRB, ERR, INIT, PE, SLIN_ASTRB, STB_WRITE, KBRST, GA20, SIOPME, GPIOE00-07, GPIOE10-17, GPO11-13 PWRGD_PS, CPU_PRESENT, PRIMARY_HD, SECONDARY_HD, SCSI. 4. The following pins have an internal static pull-down resistor (when enabled) and therefore may have leakage current to VSS (when VIN = VSUP): BUSY_WAIT, PE and SLCT, GPIOE14, GPIOE00 (on pin 118), GPIOE07 (on pin 128). 5. The following strap pins have an internal static pull-up resistor enabled during Power-Up reset and therefore may have leakage current to VSUP (when VIN = 0): BADDR, TRIS, TEST, VsbStrap1, VddStrap1, VddStrap2. 6. When VDD3 = 0V, the following pins present a DC load to VSS of 30 KΩminimum (not tested, guaranteed by design) for a pin voltage of 0V to 3.6V: CTS1, CTS2, DCD1, DCD2, DSR1, DSR2, DTR_BOUT1, DTR_BOUT2, RI1, RI2, RTS1, RTS2, SIN1, SIN2, SOUT1, SOUT2. 7. Output from SLCT, BUSY_WAIT (and PE if bit 2 of PP Confg0 register is 0) is open-drain in all SPP modes except in SPP-Compatible mode when the setup mode is ECP-based FIFO and bit 4 of the Control2 parallel port register is 1. Otherwise, output from these signals is level 2. External 4.7 KΩ pull-up resistors should be used. 8. Output from ACK, ERR (and PE if bit 2 of PP Confg0 register is set to 1) is open-drain in all SPP modes except in SPP- Compatible mode when the setup mode is ECP-based FIFO and bit 4 of the Control2 parallel port register is set to 1. Otherwise, output from these signals is level 2. External 4.7 KΩ pull-up resistors should be used. 9. Output from STB, AFD, INIT and SLIN is open-drain in all SPP modes, except in SPP-Compatible mode when the setup mode is ECP-based (FIFO). Otherwise, output from these signals is level 2. External 4.7 KΩpull-up resistors should be used. 10. IOH is valid for a GPIO pin only when it is not configured as open-drain. 11. In XOR Tree mode, the buffer type of the input pins participating in the XOR Tree is INT (Input, TTL compatible), regard- less of the buffer type of these pins in normal device operation mode (see Section 1.4 on page 21). 10.2.14 Terminology Back-Drive Protection. A pin that is back-drive protected does not sink current into the supply when an input voltage higher than the supply, but below the pin’s maximum input voltage, is applied to the pin. This is true even when the supply is inac- tive. Note that active pull-up resistors and active output buffers are typically not back-drive protected. 5-Volt Tolerance. An input signal that is 5V tolerant can operate with input voltage of up to 5V even though the supply to the device is only 3.3V. The actual maximum input voltage allowed to be supplied to the pin is indicated by the maximum high voltage allowed for the input buffer. Note that some pins have multiple buffers, not all of which are 5V tolerant. In such cases, there is a note that indicates at what conditions a 5V input may be applied to the pin; if there is no note, the low max- imum voltage among the buffers is the maximum voltage allowed for the pin. Winbond Electronics Corp. Advanced PC Product Center

10.3 INTERNAL RESISTORS

Figure 42. Internal Resistor Test Conditions, TA = 0°C to 70°C, VSUP = 3.3V Figure 43. Internal Pull-Down Resistor for Straps, TA = 0°C to 70°C, VSUP = 3.3V

1. VSUP is VDD3 or VSB3 according to the pin power well.
2. The equivalent resistance of the pull-up resistor is calculated by RPU = (VSUP − VPIN) / IPU.
3. The equivalent resistance of the pull-down resistor is calculated by RPD = VPIN / IPD.

10.3.1 Pull-Up Resistor

10.3.2 Pull-Down Resistor

1. Not tested. Guaranteed by characterization.
2. Not tested. Guaranteed by characterization.

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10.4 AC ELECTRICAL CHARACTERISTICS

10.4.1 AC Test Conditions

Figure 44. AC Test Conditions, TA = 0°C to 70°C, VSUP = 3.3V ±10%

1. VSUP is either VDD3 or VSB3, according to the pin power well.
2. CL = 50 pF for all output pins except the following pin groups:

−CL = 40 pF for IDE_RSTDRV pin. − CL = 400 pF for SMBus pins (see “SMBus Voltage Translation and Isolation Timing” on page 235). These values include both jig and oscilloscope capacitance. − for push-pull output pins. − for high impedance to active low and active low to high-impedance transition measurements. − for high impedance to active high and active high to high-impedance transition measurements.

1. For the FDC open-drain interface pins, S1 = VDD3 and RL = 150Ω.

10.4.2 Reset Timing

1. Not tested. Guaranteed by design. Max1 tIRST Internal Power-Up Reset Time VSB3 power-up to end of internal reset Ended by

17 * tCP 2. t32KW + t32KVAL from VSB3 power-up to 32 KHz domain toggling; see “Low-Frequency Clock Timing” on page 223. Ended by PCI_RESET tLRST tLRST PCI_RESET active time VSB3 power-up to end of PCI_RESET 10 ms tIPLV Internal VsbStrap1 strap pull- up resistor, valid time3 3. Active only during VSB3 Power-Up reset. Before end of internal reset tIRST tEPLV External VsbStrap1 strap pull- down resistor, valid time Before end of internal reset tIRST Device Under Test 0.1 µf Input Output RL CL Load Circuit AC Testing Input, Output Waveform VSUP 2.4 0.4 2.0 0.8 Test Points 2.0 0.8 (unless otherwise specified) Winbond Electronics Corp. Advanced PC Product Center

Figure 45. Internal VSB Power-Up Reset - Ended by 32 KHz Clock Figure 46. Internal VSB Power-Up Reset - Ended by PCI_RESET

32 KHz Domain

Revision 1.1 221 www.national.com PC8374L VDD Power-Up Reset Figure 47. Internal VDD Power-Up Reset Figure 48. Hardware Reset

1. Not tested. Guaranteed by design. Max1 tIRST Internal Power-Up reset time VDD3 power-up to end of internal reset tLRST tLRST PCI_RESET active time VDD3 power-up to end of PCI_RESET 10 ms 2.5 s tIPLV Internal strap pull-up resistor, valid time2 2. Active only during VDD3 Power-Up reset. Before end of internal reset tIRST tEPLV External strap pull-down resistor, valid time Before end of internal reset tIRST Symbol Figure

PCI_RESET pulse width 100 ns Internal Straps tIPLV tEPLV (Pull-up) (Pull-Down) External Straps VDD3 (Power) (Internal) PCI_RESET VDD Power-Up Reset tIRST VDDONmin tLRST Internal Clock PCI_RESET tWRST Winbond Electronics Corp. Advanced PC Product Center

10.4.3 Clock Timing

Figure 49. High-Frequency Clock Waveform Timing Figure 50. CLOCKI14 and Internal 48 MHz Clock Timing

1. Not tested. Guaranteed by design.
2. Not tested. Guaranteed by characterization.

48 MHz Clock

Figure 51. Internal 32 KHz (INT32K) and CLOCKO32 Timing

1. Not tested. Guaranteed by characterization.

www.national.com 224 Revision1.1 PC8374L

10.4.4 LPC Interface Timing

The AC characteristics of the LPC interface meet the PCI Local Bus Specification (Rev 2.2 December 18, 1998) for 3.3V DC signaling. PCI_CLK and PCI_RESET Symbol Parameter Min Max Units tCYC 1. The PCI may have any clock frequency between nominal DC and 33 MHz. Device operational parameters at frequencies under 16 MHz are guaranteed by design rather than by testing. The clock frequency may be changed at any time during the operation of the system as long as the clock edges remain “clean” (monotonic) and the minimum cycle high and low times are not vio- lated. The clock may only be stopped in a low state. PCI_CLK Cycle Time ns tHIGH PCI_CLK High Time2 2. Not tested. Guaranteed by characterization. ns tLOW PCI_CLK Low Time2 ns PCI_CLK Slew Rate2,3 3. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum peak-to-peak portion of the clock wavering (0.2 * VDD3 to 0.6 * VDD3) as shown below. V/ns PCI_RESET Slew Rate2,4 4. The minimum PCI_RESET slew rate applies only to the rising (de-assertion) edge of the reset signal and ensures that system noise cannot make an otherwise monotonic signal appear to bounce in the switching range. mV/ns tHIGH tLOW tCYC

0.6 VDD

0.2 VDD

0.4 VDD

0.4 VDD3 p-to-p

(minimum) VDD3 = 3.3V ±10% Winbond Electronics Corp. Advanced PC Product Center

Revision 1.1 225 www.national.com PC8374L LPC Signals Symbol Figure

0.615 VDD3

0.4 VDD3

PCI_CLK LAD3−LAD0, LDRQ, SERIRQ Outputs tVAL tON tOFF VDD3 = 3.3V ±10% tVAL LAD3−LAD0, SERIRQ Output Enabled

0.285 VDD3

PCI_CLK LAD3−LAD0, LFRAME SERIRQ Inputs VDD3 = 3.3V ±10% tHL tSU Winbond Electronics Corp. Advanced PC Product Center

www.national.com 226 Revision1.1 PC8374L

10.4.5 FDC Timing

HDSEL Hold from WGATE Inactive1 1. Not tested. Guaranteed by design. 100 µs tHDS HDSEL Setup to WGATE Active1 100 µs tWDW Write Data Pulse Width1 See tDRP, tICP and tWDW values in table below Data Rate tDRP tICP tICP Nominal tWDW tWDW Minimum Unit

1 Mbps

1. tCP is the clock period defined for CLOCKI in “Clock Timing” on page 222. 125 2 x tICP 250 ns

500 Kbps

300 Kbps

250 Kbps

1. Not tested. Guaranteed by design. µs tIW Index Pulse Width 100 ns tSTD DIR Hold from STEP Inactive tSTR ms tSTP STEP Active (Low) Pulse Width1 µs tSTR STEP Rate Time1 0.5 ms tHDS tHDH tWDW HDSEL WGATE WDATA Winbond Electronics Corp. Advanced PC Product Center

Revision 1.1 227 www.national.com PC8374L FDC Read Data Timing Symbol Parameter Min Max Unit tRDW Read Data Pulse Width ns tIW tSTP tDST tSTR tSTD DIR STEP INDEX tRDW RDATA Winbond Electronics Corp. Advanced PC Product Center

www.national.com 228 Revision1.1 PC8374L

10.4.6 Parallel Port Timing

Standard Parallel Port Timing Enhanced Parallel Port Timing Symbol Parameter Conditions Min Max Unit tPDH Port Data Hold SPP Mode 0 and Mode 1, ECP Mode 0 and Mode1: system dependent; ECP Mode 2: device dependent. 750 ns tPDS Port Data Setup SPP Mode 0 and Mode 1, ECP Mode 0 and Mode1: system dependent; ECP Mode 2: device dependent. 750 ns tSW Strobe Width SPP Mode 0 and Mode 1, ECP Mode 0 and Mode1: system dependent; ECP Mode 2: device dependent. 750 ns Symbol Parameter Min Max EPP 1.71 1. Also in ECP Mode 4. EPP 1.91 Unit tWW19a WRITE Active from WAIT Low ns tWW19ia WRITE Inactive from WAIT Low ns tWST19a DSTRB or ASTRB Active from WAIT Low ns tWEST DSTRB or ASTRB Active after WRITE Active ns tWPDH PD7−0 Hold after WRITE Inactive ns tWPDS PD7−0 Valid after WRITE Active ns tEPDW PD7−0 Valid Width ns tEPDH PD7−0 Hold after DSTRB or ASTRB Inactive ns tPDS tPDH tSW BUSY ACK PD7−0 STB WRITE DSTRB ASTRB PD7−0 WAIT Valid tWW19ia tWPDH tEPDH tEPDW or tWW19a tWST19a tWPDS tWEST tWST19a Winbond Electronics Corp. Advanced PC Product Center

Revision 1.1 229 www.national.com PC8374L Extended Capabilities Port (ECP) Timing Forward Mode Reverse Mode Symbol Parameter Min Max Unit tECDSF Data Setup before STB Active ns tECDHF Data Hold after BUSY Inactive ns tECLHF BUSY Active after STB Active ns tECHHF STB Inactive after BUSY Active1 1. Not tested. Guaranteed by design. s tECHLF BUSY Inactive after STB Inactive1 ms tECLLF STB Active after BUSY Inactive ns Symbol Parameter Min Max Unit tECDSR Data Setup before ACK Active ns tECDHR Data Hold after AFD Active ns tECLHR AFD Inactive after ACK Active ns tECHHR ACK Inactive after AFD Inactive1 1. Not tested. Guaranteed by design. ms tECHLR AFD Active after ACK Inactive1 s tECLLR ACK Active after AFD Active ns PD7−0 STB BUSY tECHHF tECHLF tECLLF tECDSF tECLHF tECDHF AFD PD7−0 ACK AFD tECHHR tECHLR tECLLR tECDSR tECLHR tECDHR BUSY Winbond Electronics Corp. Advanced PC Product Center

www.national.com 230 Revision1.1 PC8374L

10.4.7 Serial Ports 1 and 2 Timing

See Section 10.4.8 on page 231. Modem Control Timing Symbol Parameter Min Max Unit tL RI1,2 Low Time1,2 1. Not tested. Guaranteed by characterization. 2. The value also applies to RI1,2 wake-up detection in the SWC module. ns tH RI1,2 High Time1,2 ns tSIM Delay to Set IRQ from Modem Input ns CTS, DSR, DCD INTERRUPT (Read MSR) RI tSIM tSIM tSIM tH tL (Read MSR) Winbond Electronics Corp. Advanced PC Product Center

Revision 1.1 231 www.national.com PC8374L

10.4.8 Serial Port, Sharp-IR, SIR and Consumer Remote Control Timing

1. Not tested. Guaranteed by design. Max1 Unit tBT Single Bit Time in Serial Port and Sharp-IR Transmitter tBTN −252 2. tBTN is the nominal bit time in Serial Port, Sharp-IR, SIR and Consumer Remote Control modes. It is deter- mined by the setting of the Baud Generator Divisor registers. tBTN + 25 ns Receiver tBTN −2% tBTN + 2% ns tCMW Modulation Signal Pulse Width in Sharp-IR and Consumer Remote Control Transmitter tCWN −253 3. tCWN is the nominal pulse width of the modulation signal for Sharp-IR and Consumer Remote Control modes. It is determined by MCPW field (bits 7-5) of IRTXMC register and TXHSC bit (bit 2) of RCCFG register. tCWN + 25 ns Receiver 500 ns tCMP Modulation Signal Period in Sharp-IR and Consumer Remote Control Transmitter tCPN −254 4. tCPN is the nominal period of the modulation signal for Sharp-IR and Consumer Remote Control modes. It is determined by MCFR field (bits 4-0) of IRTXMC register and the TXHSC bit (bit 2) of RCCFG register. tCPN + 25 ns Receiver tMMIN 5. tMMIN and tMMAX define the time range within which the period of the incoming subcarrier signal has to fall in order for the signal to be accepted by the receiver. These time values are determined by the contents of the IRRXDC register and the setting of RXHSC bit (bit 5) of RCCFG register. tMMAX ns tSPW SIR Signal Pulse Width Transmitter, Variable (3/16) x tBTN −152 (3/16) x tBTN + 152 ns Transmitter, Fixed 1.48 1.78 µs Receiver µs SDRT SIR Data Rate Tolerance. % of Nominal Data Rate. Transmitter ± 0.87% Receiver ± 2.0% tSJT SIR Leading Edge Jitter. % of Nominal Bit Duration. Transmitter ± 2.5% Receiver ± 6.5% Serial Port tCMW tCMP Sharp-IR Consumer Remote Control tBT SIR tSPW Winbond Electronics Corp. Advanced PC Product Center

www.national.com 232 Revision1.1 PC8374L

10.4.9 Glue Function Timing

Highest Active Main and Standby Supply Reference Figure 52. REF5V and REF5V_STBY (AC Characteristics) VDD3 to REF5V Propagation Delay1 1. Not tested. Guaranteed by design. VDD5 = 0; VDD3 slew rate > 10 V/ms 1 ms Standby tPD VSB3 to REF5V_STBY Propagation Delay1 VSB5 = 0; VSB3 slew rate > 10 V/ms 1 ms Symbol Figure Rising Supply Delay1 (typ. 32 ms) 1. Not tested. Guaranteed by characterization. VSB5 > VTRIP and VSB3 > VSB3ON 100 ms tFD5 Falling VSB5 Supply Delay1 VSB5 < VTRIP and VSB3 > VSB3ON 100 ns tGA VSB5 and VSB3 Glitch Allowance1 VSB5 < VTRIP or VSB3 < VSB3OFF 100 ns tFD3 Falling VSB3 Supply Delay1 VSB3 < VSB3OFF and VSB5 > VTRIP 100 ns tR Rise Time2 2. Not tested. Guaranteed by design. VSB3 > VSB3ON 100 ns tF Fall Time2 VSB3 > VSB3ON 100 ns tPD 1.5V 3.3V VDD3, VSB3 REF5V, REF5V_STBY tPD Winbond Electronics Corp. Advanced PC Product Center

Revision 1.1 233 www.national.com PC8374L Figure 53. RSMRST (AC Characteristics) Figure 54. Reset Outputs From RE of PCI_RESET to RE of PCIRST_OUT, PCIRST_OUT2 ns tR Rise Time PCIRST_OUT, PCIRST_OUT2 ns tPDF Fall Propagation Delay From FE of PCI_RESET to FE of IDE_RSTDRV ns tF Fall Time IDE_RSTDRV ns 0.8V tRD tFD3 VSB3 VSB3ON tRD tFD5 RSMRST VSB5 VTRIP tGA VSB3OFF 1.4V tF 2.0V 0.8V 1.4V tR 2.0V 1.4V 2.0V 1.4V tF 0.8V 2.0V VDD3 = 3.3V ±10% tPDF PCI_RESET IDE_RSTDRV tPDR 1.4V tR 0.8V PCIRST_OUT, PCIRST_OUT2 Winbond Electronics Corp. Advanced PC Product Center

www.national.com 234 Revision1.1 PC8374L Main Power Good Power Distribution Control Figure 55. BKFD_CUT and LATCHED_BF_CUT (AC Characteristics)

1. Not tested. Guaranteed by design. After RE of PWRGD_PS 100 120 ms tS3D High-to-Low Delay1 After FE of SLP_S3 ns tR PWRGD_3V Rise Time1 0.8V to 2.0V ns tF PWRGD_3V Fall Time1 2.0V to 0.8V ns Symbol Figure

BKFD_CUT Propagation Delay1 1. Not tested. Guaranteed by design. PWRGD_PS or SLP_S3 to BKFD_CUT µs tTB BKFD_CUT Transition Time1 0.8V to 2.0V ns tPL LATCHED_BF_CUT Propagation Delay1 BKFD_CUT or SLP_S5 to LATCHED_BF_CUT µs tTL LATCHED_BF_CUT Transition Time1 0.8V to 2.0V ns 0.8V 1.4V 2.0V SLP_S5 BKFD_CUT LATCHED_BF_CUT tPL tTL 0.8V tPL 1.4V tTL 2.0V tPL tPL Winbond Electronics Corp. Advanced PC Product Center

Revision 1.1 235 www.national.com PC8374L Main Power Supply Control SMBus Voltage Translation and Isolation Timing Symbol Figure Rise Propagation Delay1,2 1. Not tested. Guaranteed by design. 2. Test conditions: CL = 50 pF and 1 KΩ external resistor to VSB5. (CPU_PRESENT = 1) or (SLP_S3 = 0) or (ETC event occurred) to RE of PS_ON µs tPF Fall Propagation Delay1 From whichever occurs last: (CPU_PRESENT = 0), (SLP_S3 = 1), (No ETC event and RE on SLP_S3) to FE of PS_ON µs tR Rise Time1,2 0.8V to 2.0V ns tF Fall Time1 2.0V to 0.8V ns Symbol Figure

1. An “Input” type is a value the PC8374L device expects from the system; an “Output” type is a value the PC8374L device provides to the system. Min Max Unit tSMBR Rise Time (all signals) Input 10002,3 3. Not tested. Guaranteed by design. ns tSMBF Fall Time (all signals) Input 2503 ns Output 3002,4 4. Not tested. Guaranteed by characterization. ns tSMBD Propagation Delay (each signal pair, in both directions) Output 5002,4 ns Winbond Electronics Corp. Advanced PC Product Center

www.national.com 236 Revision1.1 PC8374L 10.4.10 SWC Timing Wake-Up Inputs at VSB3 Power Switching Figure 56. Inputs at VSB3 Power Switching Figure 57. Wake-Up Inputs at VDD3 Power Switching External Wake-Up Inputs Valid1 1. Not tested. Guaranteed by characterization. At VSB3 power on, after the

32 KHz Domain is toggling

24576 * tCP 2. tCP is the cycle time of the 32 KHz clock domain (see “Low-Frequency Clock Timing” on page 223). 32768 * tCP Symbol Figure External Wake-Up Inputs Valid1 1. Not tested. Guaranteed by characterization. After VDD3 power on2 2. The 32 KHz clock domain is assumed to be toggling at VDD3 power stable. 24576 * tCP 3. tCP is the cycle time of the 32 KHz clock domain (see “Low-Frequency Clock Timing” on page 223). 32768 * tCP VSB3 (Power) RI GPIOE14-10, tEWIV GPIOE07-00, KBCLK, MCLK VSB3OFF VSB3ON KBDAT, MDAT (Internal) VSB Power-Up Reset t32KW + t32KVAL tIRST (Internal) GPIOE17-16, VDD3 (Power) GPIOE17-16, tEWIV VDD3OFF VDD3ON (VDDLOAD = 1) GPIOE07-00 GPIOE14-10, Winbond Electronics Corp. Advanced PC Product Center

Revision 1.1 237 www.national.com PC8374L 10.4.11 SMBus Timing Figure 58. SMBus Signals (HMSCL and HMSDA) Rising Time and Falling Time

1. An “Input” type is a value the PC8374L expects from the system; an “Output” type is a value the PC8374L provides to the system. Min Max Unit tSMBR Rise time (HMSCL and HMSDA) Input2 2. Test conditions: RL = 1 KΩ to VSB = 3.3V, CL = 400 pF to GND. 10003 3. Not tested. Guaranteed by design. ns tSMBF Fall time (HMSCL and HMSDA) Input 3003 ns Output2 2504 4. Not tested. Guaranteed by characterization. ns tSMBCKL Clock low period (HMSCL) Input 4.7 µs tSMBCKH Clock high period (HMSCL) Input µs tSMBCY Clock cycle (HMSCL) Input µs tSMBDS Data setup time (before clock rising edge) Input 250 ns Output2 250 ns tSMBDH Data hold time (after clock falling edge) Input ns Output2 300 ns tSMBPS Stop condition setup time (clock before data) Input µs tSMBSH Start condition hold time (clock after data) Input µs tSMBBUF Bus free time between Stop and Start conditions (HMSDA) Input 4.7 µs tSMBRS Restart condition setup time (clock before data) Input 4.7 µs tSMBRH Restart condition hold time (clock after data) Input µs tSMBLEX Cumulative clock low extend time from Start to Stop (HMSCL) Output 253 ms tSMBTO Clock low time-out (HMSCL) Input 253,5 5. The PC8374L detects a time-out condition if HMSCL is held low for more than tSMBTO. ms Output 353,6 6. On detection of a time-out condition, the PC8374L resets the SMBus Interface no later than tSMBTO. ms tSMBR 2.5V 0.4V tSMBF 3.0V 0.4V 2.5V 0.4V 0.4V tSMBCKH tSMBCKL Winbond Electronics Corp. Advanced PC Product Center

Figure 59. SMBus Data Bit Timing Figure 60. SMBus Start and Stop Condition Timing Figure 61. SMBus Restart Condition TIming

10.5 PACKAGE THERMAL INFORMATION

Table 105. Theta (Θ) J Values Note: Airflow for ThetaJA values is measured in linear feet per minute (lfpm).

www.national.com PC8374L SensorPathTM SuperI/O with Glue Functions Physical Dimensions All dimensions are in millimeters Plastic Quad Flatpack (PQFP), JEDEC Order Number PC8374L0xxx/VLA Note: ’xxx’ stands for the following Keyboard Controller Microcodes: IBW - for AMI IBU - for Intel IBM - for IBM ICG - for Dell ICK - for Phoenix LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. National Semiconductor Corporation Americas Email: new.feedback@nsc.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 87 90 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: ap.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 Email: nsj.crc@jksmtp.nsc.com Winbond Electronics Corp. Advanced PC Product Center