PC7410

PC7410 ETC2 | Alldatasheet

Document overview

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Technical content

Features

• 22.8 SPECint95 (estimated), 17SPECfp95 at 500 MHz (estimated)  917MIPS at 500 MHz  Selectable Bus Clock (14 CPU Bus Dividers Up To 9x)  Seven Selectable Core-to-L2 Frequency Divisors  Selectable 603 Interface Voltage Below 3.3V (1.8V, 2.5V)  Selectable L2 interface of 1.8V or 2.5V  PD Typical 5.3W at 500 MHz, Full Operating Conditions  Nap, Doze and Sleep Modes for Power Saving  Superscalar (Four Instructions fetched per Clock Cycle)  4 GB Direct Addressing Range  Virtual Memory: 4 hexabytes (252)  64-bit Data and 32-bit Address Bus Interface  32 KB Instruction and Data Cache  Eight Independent Execution Units and Three Register Files  Write-back and Write-through Operations  fINT Max = 450 MHz 500 MHz  fBUS Max = 133 MHz

Description

The PC7410 is the second microprocessor that uses the fourth (G4) full implementation of the PowerPC Reduced Instruc- tion Set Computer (RISC) architecture. It is fully JTAG-compliant. The PC7410 maintains some of the characteristics of G3 microprocessors:  The design is superscalar, capable of issuing three instructions per clock cycle into eight independent execution units  The microprocessor provides four software controllable power-saving modes and a thermal assist unit management  The microprocessor has separate 32-Kbyte, physically-addressed instruction and data caches with dedicated L2 cache interface with on-chip L2 tags In addition, the PC7410 integrates full hardware-based multiprocessing capability, including a 5-state cache coherency pro- tocol (4 MESI states plus a fifth state for shared intervention) and an implementation of the new AltiVec ® technology instruction set. New features have been developed to make latency equal fo r double-precision and single-precision floating-point opera- tions involving multiplication. Additionally, in memory subs ystem (MSS) bandwidth, the PC7410 offers an optional, high- bandwidth MPX bus interface. Unlike the PC7400, the PC7410 does not support the 3.3V I/O on the L2 cache interface.

0832F–HIREL–02/07 PC7410 e2v semiconductors SAS 2007 Screening  CBGA Upscreenings Based on e2v Standards  Full Military Temperature Range (TJ = -55° C, +125° C), Industrial Temperature Range (TJ = -40° C, +110° C)  CI-CGA Package Version, HiTCE Package Version

0832F–HIREL–02/07 e2v semiconductors SAS 2007 PC7410 1. Block Diagram Figure 1-1. PC7410 Microprocessor Block Diagram Fetcher Branch Processing Unit Instruction Queue 6-word Dispatch Unit Instruction Unit Data MMU SRs (Original) 128-entry DTLB DBAT Array Instruction MMU SRs (Shadow) 128-entry ITLB IBAT Array Reservation Station Vector Permute Unit Vector ALU Integer Unit 1 Integer Unit 2 System Register Unit Reservation Station Reservation Station Reservation Station Reservation Station Reservation Station 2-entry Reservation Station VR File

6 Rename

64-entry BTIC/512-entry BHT LR/CTR Add-Multiply- divide - Add - VSCR - Add - Add-Multiply- divide FPSCR EA Calculation Finished Stores Completed Stores 128-bit 32-bit 128-bit

2 Instructions

(2 Instructions) 32-bit Address Bus 64- or 32-bit L2 Data Bus 19-bit L2 Address Bus 64-bit Data Bus 32-bit EA PA 64-bit 64-bit Data Reload Buffer Data Reload Table Instruction Reload Buffer Instruction Reload Table Memory Subsystem L2 Miss Data Transaction Queue L2 Castout Bus Interface Unit L2 Data Transaction Queue L2 Controller L2 Tags L2CR L2PMCR Additional featuresTime Base Counter/Decrementer Clock Multiplier JTAG/COP Interface Thermal/Power Management Performance Monitor 128 bits 128 bits (4 instructions)

0832F–HIREL–02/07 PC7410 e2v semiconductors SAS 2007 2. General Parameters Table 2-1 provides a summary of the general parameters of the PC7410. Note: 1. 3.3V I/O bus not supported for 1.5V core power supply processor version. 3. Overview This section summarizes features of the PC7410’s implementation of the PowerPC architecture. Major features of the PC7410 are as follows:  Branch Processing Unit – Four instructions fetched per clock – One branch processed per cycle (plus resolving two speculations) – Up to one speculative stream in execution, one additional speculative stream in fetch – 512-entry Branch History Table (BHT) for dynamic prediction – 64-entry, 4-way set associative Branch Target Instruction Cache (BTIC) for eliminating branch delay slots  Dispatch Unit – Full hardware detection of dependencies (resolved in the execution units) – Dispatch two instructions to eight independent units (system, branch, load/store, fixed-point unit 1, fixed-point unit 2, floating-point, AltiVec permute, AltiVec ALU) – Serialization control (predispatch, pos tdispatch, execution serialization)  Decode – Register file access – Forwarding control – Partial instruction decode Table 2-1. Device Parameters Parameter Description Technology 0.18 µm CMOS, six-layer metal Die size 6.32 mm × 8.26 mm (52 mm 2) Transistor count 10.5 million Logic design Fully-static Packages Surface-mount 360 Ceramic Ball Grid Array (CBGA) Surface mount 360 high coefficient of thermal expansion ceramic ball grid array (HiTCE) Surface mount 360-column Ci-CGA Package Core power supply 1.8V ± 100 mV dc or 1.5V ± 50 mV dc (nominal; see Table 6-3 on page 11 for Recommended Operating Conditions) I/O power supply 1.8V ± 100 mV dc or 2.5V ± 100 mV 3.3V ± 165 mV (603 bus only)(1) (input thresholds are configuration pin selectable)

0832F–HIREL–02/07 e2v semiconductors SAS 2007 PC7410  Completion – 8-entry completion buffer – Instruction tracking and peak comple tion of two instructions per cycle – Completion of instructions in program order while supporting out-of-order instruction execution, completion serialization and all instruction flow changes  Fixed-point Units (FXUs) that Share 32 GPRs for Integer Operands – Fixed-point Unit 1 (FXU1): multiply, divide, shift, rotate, arithmetic, logical – Fixed-point Unit 2 (FXU2)—shift, rotate, arithmetic, logical – Single-cycle arithmetic, shifts, rotates, logical – Multiply and divide support (multi-cycle) – Early out multiply  Three-stage Floating-point Unit and a 32-entry FPR File – Support for IEEE-754 standard single- and double-precision floating-point arithmetic – Three-cycle latency, one-cycle throughput (single or double precision) – Hardware support for divide – Hardware support for denormalized numbers – Time deterministic non-IEEE mode  System Unit – Executes CR logical instructions and miscellaneous system instructions – Special register transfer instructions  AltiVec Unit – Full 128-bit data paths – Two dispatchable units: vector permute unit and vector ALU unit – Contains its own 32-entry 128-bit Vector Register File (VRF) with six renames – The vector ALU unit is further sub-divided into the Vector Simple Integer Unit (VSIU), the Vector Complex Integer Unit (VCIU) and the Vector Floating-point Unit (VFPU) – Fully pipelined  Load/Store Unit – One-cycle load or store cache access (byte, half-word, word, double-word) – Two-cycle load latency with one-cycle throughput – Effective address generation – Hits under misses (multip le outstanding misses) – Single-cycle unaligned access within double-word boundary – Alignment, zero padding, sign extend for integer register file – Floating-point internal format conversion (alignment, normalization) – Sequencing for load/store multiples and string operations – Store gathering – Executes the cache and TLB instructions – Big- and little-endian byte addressing supported – Misaligned little-endian supported

0832F–HIREL–02/07 PC7410 e2v semiconductors SAS 2007 – Supports FXU, FPU, and AltiVec load/store traffic – Complete support for all four architecture AltiVec DST streams  Level 1 (L1) Cache Structure – 32K 32-byte line, 8-way set associative instruction cache (iL1) – 32K 32-byte line, 8-way set associative data cache (dL1) – Single-cycle cache access – Pseudo Least-recently-used (LRU) replacement – Data cache supports AltiVec LRU and transient instructions algorithm – Copy-back or write-through data cache (on a page-per-page basis) – Supports all PowerPC memory coherency modes – Non-blocking instruction and data cache – Separate copy of data cache tags for efficient snooping – No snooping of instruction cache except for ICBI instruction  Level 2 (L2) Cache Interface – Internal L2 cache controller and tags; external data SRAMs – 512K, 1M and 2-Mbyte 2-way set associative L2 cache support – Copyback or write-through data cache (on a page basis or for all L2) – 32-byte (512K), 64-byte (1M), or 128-byte (2M) sectored line size – Supports pipelined (register-register) synchronous burst SRAMs and pipelined (register- register) late-write synchronous burst SRAMs – Supports direct mapped mode for 256K, 512K, 1M or 2 Mbytes of SRAM (either all, half or none of L2 SRAM must be configured as direct mapped – Core-to-L2 frequency divisors of ÷1, ÷1.5, ÷2, ÷2.5, ÷3, ÷3.5, and ÷4 supported – 64-bit data bus which also support 32-bits bus mode – Selectable interface voltages of 1.8V and 2.5V  Memory Management Unit – 128 entry, 2-way set associative instruction TLB – 128 entry, 2-way set associative data TLB – Hardware reload for TLBs – Four instruction BATs and four data BATs – Virtual memory support for up to four petabytes (2 52) of virtual memory – Real memory support for up to four gigabytes (2 32) of physical memory – Snooped and invalidated for TLBI instructions  Efficient Data Flow – All data buses between VRF , load/store unit, dL1, iL1, L2 and the bus are 128 bits wide – dL1 is fully pipelined to provide 128 bits per cycle to/from the VRF – L2 is fully pipelined to provide 128 bits per L2 clock cycle to the L1s – Up to eight outstanding out-of-order cache misses between dL1 and L2/bus – Up to seven outstanding out-of-order transactions on the bus

0832F–HIREL–02/07 e2v semiconductors SAS 2007 PC7410 – Load folding to fold new dL1 misses into older outstanding load and store misses to the same line – Store miss merging for multiple store misses to the same line. Only coherency action taken (i.e., address only) for store misses merged to all 32 bytes of a cache line (no data tenure needed) – Two-entry finished store queue and four-entry completed store queue between load/store unit and dL1 – Separate additional queues for efficient buffering of outbound data (castouts, write throughs, etc.) from dL1 and L2  Bus Interface – MPX bus extension to 60X processor interface – Mode-compatible with 60x processor interface – 32-bit address bus – 64-bit data bus 8x, 9x supported – Selectable interface voltages of 1.8V, 2.5V and 3.3V  Power Management – Low-power design with thermal requirements very similar to PC740 and PC750 – Low voltage 1.8V or 1.5V processor core – Selectable interface voltages of 1.8V can reduce power in output buffers – Three static power saving modes: doze, nap, and sleep – Dynamic power management  Testability – LSSD scan design – IEEE 1149.1 JTAG interface – Array Built-in Self Test (ABIST) – factory test only – Redundancy on L1 data arrays and L2 tag arrays  Reliability and Serviceability – Parity checking on 60x and L2 cache buses

0832F–HIREL–02/07 PC7410 e2v semiconductors SAS 2007 4. Signal Description Figure 4-1. PC7410 Microprocessor Signal Groups PCX7410 VDD OVDD AVDD L2OVDD L2AVDD 13 49 1 GND TS CHK GBL ARTRY WT CI DBG D[0:63] DP[0:7] TA DTI1 TEA BR BG ABB/AMON[0] A[0:31] AP[0:3] TT[0:4] TBST TSIZ[0:2] AACK DBWO, DTI(0) DBB, DMON(0) DTI(2) L2CE L2WE SRESET HRESET HIT L2ADDR[0:18] L2DATA[0:63] L2DP[0:7] L2CLKOUTA, L2CLKOUTB L2SYNC_OUT L2SYNC_IN L2ZZ INT SMI MCP CKSTP_IN CKSTP_OUT SHDO, SHD1 RSRV TBEN EMODE QREQ QACK DRDY SYSCLK PLL_CFG[0:3] CLK_OUT JTAG:COP Factory Test L1_TSTCLK, L2_TSTCLK BVSEL L2VSEL 112 20 1 L2 Cache Address/Data Address Arbitration Address Bus Address Start Transfer Attribute Address Termination Data Arbitration Data Transfer Data Termination L2 Cache Clock/Control Interrupts ResetProcessor Status Control Clock Control Test Interface LSSD_MODE I/O Voltage Selection

0832F–HIREL–02/07 e2v semiconductors SAS 2007 PC7410 5. Detailed Specification This specification describes the specific requirements for the microprocessor PC7410 in compliance with e2v standard screening. 6. Applicable Documents 1. MIL-STD-883: Test methods and procedures for electronics 2. MIL-PRF-38535: Appendix A: General specifications for microcircuits The microcircuits are in accordance with the applicable documents and as specified herein.

6.1 Design and Construction

6.1.1 Terminal Connections

Depending on the package, the terminal connections are as shown in Table 12-1 on page 33, Table 6-3 on page 11 and Figure 4-1 on page 8.

6.2 Absolute Maximum Ratings

Notes: 1. Functional and tested operating conditions are given in Table 6-3 on page 11. Absolute maximum ratings are stress ratings only. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. Caution: V IN must not exceed OVDD or L2OVDD by more than 0.2V at any time including during power-on reset. 3. Caution: L2OV DD/OVDD must not exceed VDD/AVDD/L2AVDD by more than 2.0V at any time including during power-on reset; this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 4. Caution: V DD/AVDD/L2AVDD must not exceed L2OVDD/OVDD by more than 0.4V at any time including during power-on reset; this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 5. V IN may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 6-1 on page 10. 6. PC7410RXnnnLE (Rev 1.4) and later only. Previous revisions do not support 3.3V OVDD and have a maximum value OVDD of -0.3 to 2.6V. Table 6-1. Absolute Maximum Ratings(1) Symbol Characteri stic Value Unit VDD Core supply voltage -0.3 to 2.1 (4) V AVDD PLL supply voltage -0.3 to 2.1 (4) V L2AVDD L2 DLL supply voltage -0.3 to 2.1 (4) V OVDD 60x bus supply voltage -0.3 to 3.465 (3)(6) V L2OVDD L2 bus supply voltage -0.3 to 2.6 (3) V VIN Processor bus input voltage -0.3 to OV DD + 0,2V(2)(5) V VIN L2 bus input voltage -0.3 to L2OVDD + 0,2V(2)(5) V VIN JTAG signal input voltage -0.3 to OVDD + 0,2V V TSTG Storage temperature range -55 to 150 °C Rework temperature 260 °C

0832F–HIREL–02/07 PC7410 e2v semiconductors SAS 2007 Figure 6-1. Overshoot/Undershoot Voltage The PC7410 provides several I/O voltages to support both compatibility with existing systems and migra- tion to future systems. The PC7410 “core” voltage must always be provided at nominal voltage (see Table 6-3 on page 11 for actual recommended core voltage). Voltage to the L2 I/Os and processor inter- face I/Os are provided through separate sets of supp ly pins and may be provided at the voltages shown in Table 6-2. The input voltage threshold for each bus is selected by sampling the state of the voltage select pins at the negation of the signal HRESET . The output voltage will swing from GND to the maxi- mum voltage applied to the OVDD or L2OVDD power pins. Notes: 1. Caution: The input threshold selection must agree with the OV DD/L2OVDD voltages supplied. 2. To select the 2.5V thre shold option, L2VSEL/BVSEL should be tied to HRESET so that the two signals change state together. This is the preferred method for selecting this mode operation. 3. To overcome the internal pull-up resistance, a pull-down resistance less than 250 Ω should be used. 4. Default voltage setting if left unconnected (internal pulled-up). Parts Rev 1.4 and later only. Previous revisions do not support 3.3V OVDD, the default voltage setting if left unconnected is 2.5V. 5. Parts Rev 1.4 and later only. Previous revisions do not support 3.3V OV DD, having BVSEL = 1 selects the 2.5V threshold. 6. Parts Rev 1.4 and later only. Previous revisions do not support BVSEL = HRESET. 7. NSpec does not support the default OV DD setting of 3.3V. The BVSEL input must be tie either low or HRESET. Table 6-2. Input Threshold Voltage Setting BVSEL Signal Processor Bus Input Threshold is Relative to: L2VSEL Signal (3) L2 Bus Input Threshold is Relative to: 0(1) 1.8V 0 1.8 HRESET(1)(2) 2.5V HRESET 2.5 HRESET(6) 3.3V(7) HRESET Not supported Not to exceed 10% of tSYSCLK (L2)OVDD + 20% (L2)OVDD + 5% (L2)OVDD VIH VIL GND GND - 0.3V GND - 0.7V

0832F–HIREL–02/07 e2v semiconductors SAS 2007 PC7410

6.3 Recommended O perating Conditions

Notes: 1. These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed. 2. PC7410RXnnnLE (Rev 1.4) and later only. Previous revisions do not support 3.3V OV DD and have a recommended OVDD value of 2.5V ±100 mV for BVSEL = 1. 3. PC7410RXnnnLE (Rev 1.4) and later only. Previous revisions do not support BVSEL = HRESET. 4. Not supported for N spec with V DD = 1.5V Table 6-3. Recommended Operating Conditions(1) Symbol Characteristic Recommended Value Unit VDD Core supply voltage 1.8 ± 100 mV or 1.5 ± 50 mV V AVDD PLL supply voltage 1.8 ± 100 mV or 1.5 ± 50 mV V L2AVDD L2 DLL supply voltage 1.8 ± 100 mV or 1.5 ± 50 mV V OVDD Processor bus supply voltage see note (3) BVSEL = 0 1.8 ± 100 mV V OVDD BVSEL = HRESET 2.5 ± 100 mV V OVDD (2)(3) BVSEL = 1 or = HRESET(4) 3.3 ± 165 mV V L2OVDD L2 bus supply voltage L2VSEL = 0 1.8 ± 100 mV V L2OVDD L2VSEL = 1(2) or L2VSEL = HRESET 2.5 ± 100 mV V VIN Input voltage Processor bus GND to OV DD V VIN L2 Bus GND to L2OV DD V VIN JTAG Signals GND to OV DD V TJ Die-junction temperature -55 to 125 °C

0832F–HIREL–02/07 PC7410 e2v semiconductors SAS 2007 7. Thermal Characteristics

7.1 Package Characteristics

Notes: 1. Junction temperature is a function of on-chip power diss ipation, package thermal resistance, mounting site (board) tempera- ture, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per SEMI G38-87 and JEDEC JESD51-2 wit h the single layer board horizontal. 3. Per JEDEC JESD51-6 with the board horizontal. 4. Thermal resistance between the die and the printed circui t board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5. Thermal resistance between th e die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1) with the calculated case temperature. The actual value of RθJC for the part is less than 0.1°C/W. See “Thermal Management Information” on page 13 for more details about thermal management. The board designer can choose between several commerc ially available heat sink types to place on the PC7410. For exposed-die packaging technology as in Table 7-1, the intrinsic conduction thermal resis- tance paths are shown in Figure 7-1 on page 13.

7.1.1 Package Thermal Characteristics for HiTCE

Table 7-2 provides the package thermal characteristics for the PC7410, HiTCE. Notes: 1. Simulation, no convection air flow. 2. Per JEDEC JESD51-6 with the board horizontal. Table 7-1. Package Thermal Characteristics CBGA Symbol Characteristic Value PC7410 CBGA Unit RθJA Junction-to-ambient thermal resistance, natural convection, single-layer (1s) board(1)(2) 24 ° C/W RθJMA Junction-to-ambient thermal resistance, natural convection, four-layer (2s2p) board(1)(3) 17 ° C/W RθJMA Junction-to-ambient thermal resistance, 200 ft/min airflow, single-layer (1s) board(1)(3) 18 ° C/W RθJMA Junction-to-ambient thermal resistance, 400 ft/min airflow, single-layer (1s) board 16 ° C/W RθJMA Junction-to-ambient thermal resistance, 200 ft/min airflow, four-layer (2s2p) board(1)(3) 14 ° C/W RθJMA Junction-to-ambient thermal resistance, 400 ft/min airflow, four-layer (2s2p) board 13 ° C/W RθJB Junction-to-board thermal resistance(4) 8 ° C/W RθJC Junction-to-case thermal resistance(5) < 0.1 ° C/W Table 7-2. Package Thermal Characteristics for HiTCE Package Characteristic Symbol Value UnitPC7410 HiTCE Junction-to-bottom of balls(1) RθJ 6.8 ° C/W Junction-to-ambient thermal resistance, natural convection, four-layer (2s2p) board(1)(2) RθJMA 20.7 ° C/W Junction to board thermal resistance R θJB 11.0 ° C/W

0832F–HIREL–02/07 e2v semiconductors SAS 2007 PC7410

7.1.2 Package Thermal Characteristics for CI-CGA

7.2 Internal Package Conduction Resistance

Figure 7-1 depicts the primary heat transfer path for a package with an attached heat sink mounted on a printed circuit board. Heat generated on the active side of the chip is conducted through the silicon, then through the heat sink attach material (or thermal interface material) and fina lly to the heat sink where it is removed by forced- air convection. Since the silicon thermal resistance is quite small, for a first-order analysis the temperature drop in the silicon may be neglected. Thus, the heat sink atta ch material and the heat sink conducti on/convective thermal resistances are the dominant terms. Figure 7-1. C4 Package with Heat Sink Mounted on a Printed Circuit Board

7.3 Thermal Management Information

This section provides thermal management informati on for the ceramic ball grid array (CBGA) package for air-cooled applications. Proper thermal control design is primarily dependent upon the system-level design – the heat sink, airflow and thermal interface material. To reduce the die-junction temperature, heat sinks may be attached to the package by severa l methods: adhesive, spring clip to holes in the printed-circuit board or package and mounting clip and screw assembly; see Figure 7-2 on page 14. This spring force should not exceed 5.5 pounds of force. Ultimately, the final selection of an appropriate heat sink depends on many factors such as thermal performance at a given air velocity, spatial volume, mass, attachment method, assembly and cost. Table 7-3. Package Thermal Characteristics for CI-CGA Characteristic Symbol Value UnitPC7410 CI-CGA Junction to board thermal resistance R θJB 8.42 ° C/W External Resistance External Resistance Internal Resistance Radiation Convection Heat Sink Thermal Interface Material Die/Package Die Junction Package/Leads Printed Circuit Board Radiation Convection

0832F–HIREL–02/07 PC7410 e2v semiconductors SAS 2007 Figure 7-2. CBGA Package Cross-section with Heat Sink Options

7.3.1 Adhesives and Thermal Interface Materials

A thermal interface material is recommended at the package lid-to-heat sink interface to minimize the thermal contact resistance. For those applications where the heat sink is attached by spring clip mecha- nism, Figure 7-3 on page 15 shows the thermal performance of three thin-sheet thermal-interface materials (silicone, graphite/oil, floroether oil), a bare joint and a joint with thermal grease as a function of contact pressure. As shown, the performance of these thermal interface materials improves with increas- ing contact pressure. The use of thermal grease significantly reduces the interface thermal resistance. That is, the bare joint results in a thermal resistance approximately seven times greater than the thermal grease joint. Heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see Figure 7-2). This spring force should not exceed 5.5 pounds of force. Therefore, synthetic grease offers the best thermal performance, considering the low interface pressure. The board designer can choose between several types of thermal interface. Heat sink adhesive materi- als should be selected based upon high conductivity, yet must have adequate mechanical strength to meet equipment shock/vibration requirements. Printed-Circuit Board Adhesive or Thermal Interface Material Heat Sink Clip Heat Sink Option

0832F–HIREL–02/07 e2v semiconductors SAS 2007 PC7410 Figure 7-3. Thermal Performance of Different Thermal Interface Materials

7.3.1.1 Heat Sink Selection Example

For preliminary heat sink sizing, the die-junction temperature can be expressed as follows: where: TJ = die-junction temperature Ta = inlet cabinet ambient temperature Tr = air temperature rise within the computer cabinet θjc = junction-to-case thermal resistance θint = adhesive or interface material thermal resistance θsa = heat sink base-to-ambient thermal resistance Pd = power dissipated by the device During operation, the die-junction temperatures (T J) should be maintained less than the value specified in Table 6-3 on page 11 . The temperature of the air cooling the component greatly depends upon the ambient inlet air temperature and the air temperature rise within the electronic cabinet. An electronic cabinet inlet-air temperature (T a) may range from 30 ° C to 40° C. The air temperature rise within a cabi- net (Tr) may be in the range of 5 ° C to 10 ° C. The thermal resistance of the thermal interface material (θint) is typically about 1 ° C/W. Assuming a T a of 30° C, a Tr of 5° C, a CBGA package θjc = 0.03, and a power consumption (Pd) of 5.0 watts, the following expression for TJ is obtained: 0.5 1.5 01 0 2 0 3 0 4 05 06 07 08 0 Silicone Sheet (0.006") Bare Joint Floroether Oil Sheet (0.007") Graphite/Oil Sheet (0.005") Synthetic Grease Contact Pressure (psi) Specific Thermal Resistance (K-in.2/W) Tj Ta Tr θjc θint θsa++() Pd×++= Tj 30° C 5° C 0,03° CW⁄ 1,0° CW⁄θ sa++() 5W×++=

0832F–HIREL–02/07 PC7410 e2v semiconductors SAS 2007 For a Thermally heat sink #2328B, the heat sink-to-ambient thermal resistance (θsa) versus airflow veloc- ity is shown in Figure 7-4. Figure 7-4. Thermalloy #2328B Heat Sink-to-ambient Thermal Resistance vs. Airflow Velocity Assuming an air velocity of 0.5 m/s, the effective Rsa is 7° C/W, thus resulting in a die-junction temperature of approximately 75 ° C which is well within the maximum operat- ing temperature of the component. Other heat sinks offered by Chip Coolers, IERC, Thermalloy, Wakefield Engineering and Aavid Engi- neering offer different heat sink-to-ambient thermal resistances and may or may not need air flow. Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common fig- ure of merit used for comparing the thermal performance of various microelectronic packaging technologies, one should exercise caution when only using this metric in determining thermal manage- ment because no single parameter can adequately descr ibe three-dimensional heat flow. The final die- junction operating temperature is not only a function of the component-level thermal resistance, but of the system-level design and its operating conditions. In addition to the component's power consumption, a number of factors affect the final operating die- junction temperature – airflow, board population (local heat flux of adjacent components), heat sink efficiency, heat sink attach, heat sink placement, next-level interconnect technology, system air temperature rise, altitude, etc. 0 0.5 1 1.5 2 2.5 3 3.5 Thermalloy #2328B Pin-Fin Heat Sink (25 x 28 x 15 mm) Approach Air Velocity (m/s) Heat Sink Thermal Resistance (˚C/W)

0832F–HIREL–02/07 e2v semiconductors SAS 2007 PC7410 Due to the complexity and the many variations of system-level boundary conditions for today's micro- electronic equipment, the combined effects of the heat transfer mechanisms (radiation, convection and conduction) may vary widely. For these reasons, it is recommended to use conjugate heat transfer mod- els for the board, as well as system-level designs. To expedite system-level thermal analysis, several “compact” thermal-package models are available within FLOTHERM®. These are available upon request. 8. Power Consideration

8.1 Power Management

The PC7410 provides four power modes, selectable by setting the appropriate control bits in the MSR and HIDO registers. The four power modes are:  Full-power: This is the default power state of the PC7410. The PC7410 is fully powered and the internal functional units are operating at the full processor clock speed. If the dynamic power management mode is enabled, functional units that are idle will automatically enter a low-power state without affecting performance, software execution or external hardware.  Doze: All the functional units of the PC7410 are disabled except for the time base/decrementer registers and the bus snooping logic. When the processor is in doze mode, an external asynchronous interrupt, a system management interrupt, a decrementer exception, a hard or soft reset or machine check brings the PC7410 into the full-power state. The PC7410 in doze mode maintains the PLL in a fully powered state and locked to the system external clock input (SYSCLK) so a transition to the full- power state takes only a few processor clock cycles.  Nap: The nap mode further reduces power consumption by disabling bus snooping, leaving only the time base register and the PLL in a powered state. The PC7410 returns to the full-power state upon receipt of an external asynchronous interrupt, a system management interrupt, a decrementer exception, a hard or soft reset or a machine check input (MCP ). A return to full-power state from a nap state takes only a few processor clock cycles. When the processor is in nap mode, if QACK is negated, the processor is put in doze mode to support snooping.  Sleep: Sleep mode minimizes power consumption by disabling all internal functional units, after which external system logic may disable the PLL and SYSCLK. Returning the PC7410 to the full-power state requires the enabling of the PLL and SYSCLK, followed by the assertion of an external asynchronous interrupt, a system management interrupt, a hard or soft reset or a machine check input (MCP ) signal after the time required to relock the PLL.

0832F–HIREL–02/07 PC7410 e2v semiconductors SAS 2007

8.2 Power Dissipation

Notes: 1. These values apply for all valid processor bus and L2 bus ratios. The values do not include I/O supply power (OVDD and L2OVDD) or PLL/DLL supply power (AVDD and L2AVDD). OVDD and L2OVDD power is system dependent, but is typically <5% of VDD power. Worst case power consumption for AVDD = 15 mW and L2AVDD = 15 mW. 2. Maximum power is measured at 105°C, at V DD = 1.8V or 1.5Vwhile running an entirely cache-resident, contrived sequence of instructions which keep the execution units, including AltiVec, maximally busy. 3. Typical power is an average value measured at 65°C, V DD = 1.8V or 1.5V, OVDD = L2OVDD = 2.5V in a system while running a codec application that is AltiVec intensive. 4. These values include the use of AltiVec. Wi thout AltiVec operation, estimate a 25% decrease. 5. Power consumption derating at low temperatures to be defined after device characterization. Table 8-1. Power Consumption for PC7410 (1.8V) Processor (CPU) Frequency Unit Power Mode 400 MHz 450 MHz 500 MHz Full-On Mode Doze Mode Nap Mode Sleep Mode Maximum Sleep Mode - PLL and DLL Disabled Typical(1)(3) 600 600 600 600 600 mW

0832F–HIREL–02/07 e2v semiconductors SAS 2007 PC7410 9. Electrical Characteristics

9.1 Static Characteristics

Note: 1. Nominal voltages; see Table 6-3 on page 11 for recommended operating conditions. 2. For processor bus signals, the reference is OV DD while L2OVDD is the reference for the L2 bus signals. 3. Excludes factory test signals. 4. Capacitance is periodically sampled rather than 100% tested. 5. The leakage is measured for nominal OV DD and L2OVDD, or both OVDD and L2OVDD must vary in the same direction (for example, both OVDD and L2OVDD vary by either +5% or -5%). 6. Measured at max OV DD/L2OVDD. 7. Excludes IEEE 1149.1 boun dary scan (JTAG) signals. Table 9-1. DC Electrical Specifications (see Table 6-3 on page 11 for Recommended Operating Conditions) Symbol Characteristic Nominal Bus Voltage(1) Min Max Unit VIH Input high voltage (all inputs except SYSCLK)(2)(3)(8) 1.8 0.65 x (L2)OV DD (L2)OVDD + 0.2 VVIH 2.5 1.7 (L2)OV DD + 0.2 VIH 3.3 2.0 OV DD + 0.3 VIL Input low voltage (all inputs except SYSCLK)(8) 1.8 -0.3 0.35 x (L2)OV DD VVIL 2.5 -0.3 0.2 x (L2)OV DD VIL 3.3 -0.3 0.8 CVIH SYSCLK input high voltage(2)(8) 1.8 1.5 OV DD + 0.2 VCVIH 2.5 2.0 OV DD + 0.2 CVIH 3.3 2.4 OV DD + 0.3 CVIL SYSCLK input low voltage(8) 1.8 -0.3 0.2 VCVIL 2.5 -0.3 0.4 CVIL 3.3 -0.3 0.4 IIN Input leakage current, VIN = L2OVDD/OVDD (2)(3)(6)(7) 1.8 – 20 µAIIN 2.5 – 35 IIN 3.3 – 70 ITSI High-Z (off-state) leakage current, VIN = L2OVDD/OVDD (2)(3)(5)(7) 1.8 – 20 µAITSI 2.5 – 35 ITSI 3.3 – 70 VOH Output high voltage, IOH = -5 mA(8) VVOH 2.5 1.7 – VOH 3.3 2.4 – VOL Output low voltage, IOL = 5 mA(8) 1.8 – 0.45 VVOL 2.5 – 0.4 VOL 3.3 – 0.4 CIN Capacitance, VIN = 0V, f = 1 MHz(3)(4)(7) –6 . 0 p F

0832F–HIREL–02/07 PC7410 e2v semiconductors SAS 2007 8. For JTAG support: all signals controlled by BVSEL and L2VSEL will see V IL/VIH/VOL/VOH/CVIH/CVIL DC limits of 1.8V mode while either the EXTEST or CLAMP instruction is loaded into the IEEE 1149.1 instruction register by the UpdateIR TAP state until a different instruction is loaded into the instruction register by either another UpdateIR or a Test-Logic-Reset TAP state. If only TSRT is asserted to the part, and then a SAMPLE instruction is executed, there is no way to control or predict what the DC voltage limits are. If HRESET is asserted before executing a SAMPLE instruction, the DC voltage limits will be con- trolled by the BVSEL/L2VSEL settings during HRESET. Anytime HRESET is not asserted (i.e., just asserting TRST), the voltage mode is not known until either EXTEST or CLAMP is executed, at which time the voltage level will be at the DC limits of 1.8V.

9.2 Dynamic Characteristics

After fabrication, parts are sorted by maximum processor core frequency as shown in “Clock AC Specifi- cations” and tested for conformance to the AC specifications for that frequency. These specifications are for valid processor core frequencies. The processor core frequency is determined by the bus (SYSCLK) frequency and the settings of the PLL_CFG[0:3] signals. Parts are sold by maximum processor core frequency.

9.2.1 Clock AC Specifications

Table 9-2 provides the clock AC timing specifications as defined in Figure 9-1 on page 21. Note: 1. Caution: The SYSCLK frequency and PLL_CFG[0:3] settings must be chosen such that the resulting SYSCLK (bus) fre- quency, CPU (core) frequency and PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies. Refer to the PLL_CFG[0:3] signal description in “Clock Selection” on page 42 for valid PLL_CFG[0:3] settings. 4. Timing is guaranteed by design and characterization. 5. This represents total input jitt er, short-term and long-term combined, and is guaranteed by design. 6. Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required for PLL lock after a stable V DD and SYSCLK are reached during the power-on reset sequence. This specification also applies when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence. Table 9-2. Clock AC Timing Specifications (See Table 6-3 on page 11 for Recommended Operating Conditions) Symbol Characteristic Maximum Processor Core Frequency Unit

400 MHz 450 MHz 500 MHz

(1) Processor frequency 350 400 350 450 350 500 MHz fVCO (1) VCO frequency 700 800 700 900 700 1000 MHz fSYSCLK (1) SYSCLK frequency 33 133 33 133 33 133 MHz tSYSCLK SYSCLK cycle time 7.5 30 7.5 30 7.5 30 ns tKR & tKF (2) SYSCLK rise and fall time 1.0 1.0 1 ns tKR & tKF (3) 0.5 0.5 0.5 ns tKHKL/tSYSCLK (4) SYSCLK duty cycle measured at OVDD/2 40 60 40 60 40 60 % SYSCLK jitter(5) ±150 ±150 ±150 ps Internal PLL relock time(6) 100 100 100 µs

0832F–HIREL–02/07 e2v semiconductors SAS 2007 PC7410 Figure 9-1. SYSCLK Input Timing Diagram Note: VM = Midpoint Voltage (OV DD/2).

9.2.2 Processor Bus AC Specifications

Table 9-3 provides the processor AC timing s pecifications for the PC7410 as defined in Figure 9-3 on page 23 and Figure 9-4 on page 24 . Timing specifications for the L2 bus are provided in “L2 Bus AC Specifications” on page 26. Note: 1. All input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge of the input SYSCLK. All output specifications are measured from the midpoint of the rising edge of SYSCLK to the midpoint of the sig- nal in question. All output timings assume a purely resistive 50Ω load (see Figure 9-3 on page 23). Input and output timings are measured at the pin; time-of-flight delays must be added for trace lengths, vias and connectors in the system. 2. The symbology used for timing specific ations herein follows the pattern of t(signal)(state)(reference)(state) for inputs and t(reference)(state)(signal)(state) for outputs. For example, tIVKH symbolizes the time input signals (I) reach the valid state (V) relative to the SYSCLK reference (K) going to the high (H) state or input setup time. And tKHOV symbolizes the time from SYSCLK (K) going high (H) until outputs (O) are valid (V) or output valid time. Input hold time can be read as the time that the input signal (I) went invalid (X) with respect to the rising clock edge (KH) - note the position of the reference and its state for inputs -and output hold time can be read as the time from the rising edge (KH) until the output went invalid (OX). 3. The setup and hold time is with re spect to the rising edge of HRESET (see Figure 9-4 on page 24). SYSCLK VM VM VM CVIL CVIH tKHKL tSYSCLK tKR tKF Table 9-3. Processor Bus AC Timing Specifications(1) at VDD = AVDD = 1.8V ± 100 mV; -55°C ≤ TJ ≤ 125°C, OVDD = 1.8V ± 100 mV Symbol(2) Parameter 400, 450, 500 MHz UnitMin Max tIVKH Input Setup 1.0 – ns tIXKH Input Hold 0– n s tKHTSV tKHARV tKHOV Output Valid Times:(7)(8) TS ARTRY/SHD0/SHD1 All Other Outputs 3.0 2.3 3.0 ns tKHTSX tKHARX tKHOX Output Hold Times:(7)(12) TS ARTRY/SHD0/SHD1 All Other Outputs 0.5 0.5 0.5 ns t KHOE (11) SYSCLK to Output Enable 0.5 – ns tKHOZ SYSCLK to Output High Impedance (all except ABB/AMON[0], ARTRY/SHD, DBB/DMON[0]), SHD0, SHD1) –3 . 5 n s tKHABPZ (5)(9)(11) SYSCLK to ABB/AMON[0], DBB/DMON[0] High Impedance after precharge – 1 t SYSCLK tKHARP (5)(10)(11) Maximum Delay to ARTRY/SHD0/SHD1 Precharge – 1 t SYSCLK

0832F–HIREL–02/07 PC7410 e2v semiconductors SAS 2007 4. This specification is for configuration mode select only. Also note that the HRESET must be held asserted for a minimum of 255 bus clocks after the PLL re-lock time during the power-on reset sequence. 5. t SYSCLK is the period of the external clock (SYSCLK) in nanoseconds(ns). The numbers given in the table must be multiplied by the period of SYSCLK to compute the actual time duration (in nanoseconds) of the parameter in question. 6. Mode select signals are BVSEL, EMODE, L2VSEL, PLL_CFG[0:3]. 7. All other output signals are composed of th e following - A[0:31], AP[0:3], TT[0:4], TBST , TSIZ[0:2], GBL, WT, CI, DH[0:31], DL[0:31], DP[0:7], BR, CKSTP_OUT, DRDY, HIT, QREQ, RSRV. 9. According to the 60x bus protocol, ABB and DBB are driven only by the currently active bus master. They are asserted low then precharged high before returning to high-Z as shown in Figure 9-2 on page 23. The nominal precharge width for ABB or DBB is 0.5 x tSYSCLK, i.e., less than the minimum tSYSCLK period, to ensure that another master asserting ABB, or DBB on the following clock will not contend with the precharge. Output valid and output hold timing is tested for the signal asserted. Out- put valid time is tested for precharge.The high-Z behavior is guaranteed by design. 10. According to the 60x bus protocol, ARTRY can be driven by multiple bus masters through the clock period immediately fol- lowing AACK. Bus contention is not an issue since any master asserting ARTRY will be driving it low. Any master asserting it low in the first clock following AACK will then go to high-Z for one clock before precharging it high during the second cycle after the assertion of AACK. The nominal precharge width for ARTRY is 1.0 tSYSCLK ; i.e., it should be high-Z as shown in Fig- ure 9-2 on page 23 before the first opportunity for another master to assert ARTRY. Output valid and output hold timing are tested for the signal asserted. Output valid time is tested for precharge. The high-Z behavior is guaranteed by design. 11. Guaranteed by design and not tested. 12. Output hold time characteristics can be altered by the use of the L2_TSTCK pin during system reset, similar to L2 output hold being altered by the use of bits [14-15] in the L2CR register. Information on the operation of the L2_TSTCLK will be included in future revisions of this specification.

0832F–HIREL–02/07 PC7410 e2v semiconductors SAS 2007 Figure 9-4. Mode Input Timing Diagram where VM = Midpoint Voltage (OVDD/2)

9.2.3 L2 Clock AC Specifications

The L2CLK frequency is programmed by the L2 confi guration register (L2CR[4:6]) core-to-L2 divisor ratio. See Table 13-2 on page 43 for example core and L2 frequencies at various divisors. Table 9-4 on page 25 provides the potential range of L2CLK output AC timing specifications as defined in Figure 9-5 on page 26. The L2SYNC_OUT signal is intended to be routed halfway out to the SRAMs and then returned to the L2SYNC_IN input of the PC7410 to synchronize L2CLKO UT at the SRAM with the processor’s internal clock. L2CLKOUT at the SRAM can be offset forward or backward in time by shortening or lengthening the routing of L2SYNC_OUT to L2SYNC_IN. See Freescale ™ Application Note AN179/D "PowerPC Backside L2 Timing Analysis for the PCB Design Engineer." The minimum L2CLK frequency of Table 9-4 is specified by the maximum delay of the internal DLL. The variable-tap DLL introduces up to a full cloc k period delay in the L2CLKOUTA, L2CLKOUTB and L2SYNC_OUT signals so that the returning L2SYNC_IN signal is phase aligned with the next core clock (divided by the L2 divisor ratio). Do not choose a core-to-L2 divisor which results in an L2 frequency below this minimum, or the L2CLKOUT signals prov ided for SRAM clocking will not be phase aligned with the PC7410 core clock at the SRAMs. The maximum L2CLK frequency shown in Table 9-4 is the core frequency divided by one. Very few L2 SRAM designs will be able to operate in this mode. Most designs will se lect a greater core-to-L2 divisor to provide a longer L2CLK period for read and write access to the L2 SRAMs. The maximum L2CLK fre- quency for any application of the PC7410 will be a function of th e AC timings of the PC7410, the AC timings for the SRAM, bus loading and printed circuit board trace length. e2v is similarly limited by system constraints and ca nnot perform tests of the L2 interface on a socketed part on a functional tester at the maximum frequencies of Table 9-4. Therefore, functional operation and AC timing information are tested at core-to-L2 divisors of 2 or greater. L2 input and output signals are latched or enabled respectively by the internal L2CLK (which is SYSCLK multiplied up to the core frequency and divided down to the L2CLK frequency). In other words, the AC timings of Table 9-5 on page 26 are entirely independent of L2SYNC_IN. In a closed loop system, where L2SYNC_IN is driven through the board trace by L2SYNC_OUT, L2SYNC_IN only controls the output phase of L2CLKOUTA and L2CLKOUTB which are used to latch or enable data at the SRAMs. How- ever, since in a closed loop system L2SYNC_IN is held in phase alignment with the internal L2CLK, the signals of Table 9-5 are referenced to this signal rather than the not-externally-visible internal L2CLK. During manufacturing test, these times are actually measured relative to SYSCLK. HRESET Mode Signals SYSCLK First sample Second sample VM VM

0832F–HIREL–02/07 e2v semiconductors SAS 2007 PC7410 Note: 1. L2CLK outputs are L2CLK_OUTA, L2CLK_OUTB, and L2SY NC_OUT pins. The L2CLK frequency to core frequency set- tings must be chosen such that the resulting L2CLK frequency and core frequency do not exceed their respective maximum or minimum operating frequencies. The maximum L2LCK frequency will be system-dependent. L2CLK_OUTA and L2CLK_OUTB must have equal loading. 2. The nominal duty cycle of the L2CLK is 50% measured at midpoint voltage. 3. The DLL re-lock time is specified in terms of L2CLKs. The numb er in the table must be multiplied by the period of L2CLK to compute the actual time duration in nanoseconds. Re-lock timing is guaranteed by design and characterization. 4. The L2CR[L2SL] bit should be set for L2CLK frequencies less th an 110 MHz. This adds more delay to each tap of the DLL. 5. Allowable skew between L2SYNC_OUT and L2SYNC_IN. 6. Guaranteed by design and not tested. This output jitter number represents the maximum delay of one tap forward or one tap back from the current DLL tap as the phase comparator seeks to minimize the phase difference between L2SYNC_IN and the internal L2CLK. This number must be comprehended in the L2 timing analysis. The input jitter on SYSCLK affects L2CLKOUT and the L2 address/data/control signals equally and therefore is already comprehended in the AC timing and does not have to be considered in the L2 timing analysis. Table 9-4. L2CLK Output AC Timing Specifications at Recommended Operating Conditions (See Table 6-3 on page 11) Symbol Parameter UnitMin Max Min Max Min Max fL2CLK (1)(4) L2CLK frequency 133 400 133 400 133 400 MHz tCHCL/tL2CLK (2) L2CLK duty cycle 50 50 50 % Internal DLL-relock time(3) 640 640 640 - L2CLK DLL capture window(5) 01 001 001 0n s tL2CSKW L2CLKOUT output-to-output skew(6) -5 0-5 0-5 0 p s L2CLKOUT output jitter(6) - ±150 - ±150 - ±150 ps

0832F–HIREL–02/07 PC7410 e2v semiconductors SAS 2007 Figure 9-5. L2CLK_OUT Output Timing Diagram Note: VM = Midpoint Voltage (L2OV DD/2)

9.2.4 L2 Bus AC Specifications

Table 9-5 provides the L2 bus interface AC timing specifications for the PC7410 as defined in Figure 9-6 on page 27 and Figure 9-7 on page 28 for the loading conditions described in Figure 9-8 on page 28. tCHCL tL2CLK tL2CR tL2CF L2 Single-Ended Clock Mode L2CLK_OUTA L2CLK_OUTB L2SYNC_OUT L2CLK_OUTA L2CLK_OUTB L2SYNC_OUT tCHCL tL2CLK VM VM VM VM VM VM VM VM VM VM VM VM VM VM VM tL2CSKW VM L2 Differential Clock Mode Table 9-5. L2 Bus Interface AC Timing Specifications at VDD = AVDD = L2AVDD = 1.8V ± 100mV or 1.5V ± 50mV ; -55°C ≤ TJ ≤ 125°C, L2OVDD = 2.5V ± 100mV or L2OVDD = 1.8V ± 100mV Symbol Parameter 400, 450, 500 MHz UnitMin Max tL2CR & tL2CF (1) L2SYNC_IN rise and fall time 1.0 ns tDVL2CH (2) Setup Times Data and parity 1.5 ns tDXL2CH (2) Input Hold Times Data and parity 0.0 ns

0832F–HIREL–02/07 e2v semiconductors SAS 2007 PC7410 10. Preparation for Delivery

10.1 Handling

MOS devices must be handled with certain precautions to avoid damage due to accumulation of static charge. Input protection devices have been designed in the chip to minimize the effect of static buildup. However, the following handling practices are recommended:  Devices should be handled on benches with conductive and grounded surfaces  Ground test equipment, tools and operator  Do not handle devices by the leads  Store devices in conductive foam or carriers  Avoid use of plastic, rubber or silk in MOS areas  Maintain relative humidity above 50% if practical  For CI-CGA packages, use specific tray to take care of the highest height of the package compared with the normal CBGA 11. Package Mechanical Data

11.1 Parameters

The package parameters are as provided in the following list. The package type is 25x25 mm, 360-lead CBGA, HiTCE and CI-CGA. The following remarks apply to Figure 12-7 on page 39 and Figure 12-9 on page 41:  Dimensions and tolerancing are as per ASME Y14.5M-1994.  All dimensions are in millimeters.  Top side A1 corner index is a metallized feature with various shapes. Bottom side A1 corner is designated with a ball missing from the array.  Dimension B is the maximum solder ball diameter measured parallel to datum A.  D2 and E2 define the area occupied by the die and underfill. Actual size of this area may be smaller than shown. D3 and E3 are the minimum clearance from the package edge to the chip capacitors. Table 11-1. Package Parameters Parameter Package outline 25 mm x 25 mm Interconnects 360 (19 x 19 ball array minus one) Pitch 1.27 mm (50 mil) Minimum module height 2.65 mm (C BGA, HiTCE), 3.65 mm (CI-CGA) Maximum module height 3.20 mm (CBGA), 3.24 mm (HiTCE), 4.20 mm (CI-CGA) Ball or column diameter 0.89 mm (35 mil)

0832F–HIREL–02/07 PC7410 e2v semiconductors SAS 2007 12. Pin Assignments

12.1 BGA360 Package

Figure 12-1 , Figure 12-2 , Figure 12-3 on page 33 and Figure 12-4 on page 33 show top views of the packages available for the PC7410. Note that these drawings are not to scale. Figure 12-1. Top View of 360-Ball CBGA and 360-Pin CI-CGA Packages Figure 12-2. Top View of 360-pin CBGA and CI-CGA Packages Pin A1 Index A B C D E F G H J K L M N P R T 12 3 4 5678 91 0 1 1 1 2 1 3 1 4 1 5 1 6 17 18 19 U V W

0832F–HIREL–02/07 PC7410 e2v semiconductors SAS 2007 DH[0:31] W12, W11, V11, T9, W10, U9, U10, M11, M9, P8, W7, P9, W9, R10, W6, V7, V6, U8, V9, T7, U7, R7, U6, W5, U5, W4, P7, V5, V4, W3, U4, R5 High I/O BVSEL DL[0:31] M6, P3, N4, N5, R3, M7, T2, N6, U2, N7, P11, V13, U12, P12, T13, W13, U13, V10, W8, T11, U11, V12, V8, T1, P1, V1, U1, N1, R2, V3, U3, W2 High I/O BVSEL DP[0:7] L1, P2, M2, V2, M1, N2, T3, R1 High I/O BVSEL DRDY(6)(8)(13) K9 Low Output BVSEL DBWO DTI[0] D1 Low Input BVSEL DTI1:2(13) H6, G1 High Input BVSEL EMODE(7)(10) A3 Low Input BVSEL GBL B1 Low I/O BVSEL GND D10, D14, D16, D4, D6, E12, E8, F4, F6, F10, F14, F16, G9, G11, H5, H8, H10, H12, H15, J9, J11, K4, K6, K8, K10, K12, K14, K16, L9, L11, M5, M8, M10, M12, M15, N9, N11, P4, P6, P10, P14, P16, R8, R12, T4, T6, T10, T14, T16 N/A HIT(6)(8) B5 Low Output BVSEL HRESET B6 Low Input BVSEL INT C11 Low Input BVSEL L1_TSTCLK(2) F8 High Input BVSEL L2ADDR[0:16] L17, L18, L19, M19, K18, K17, K15, J19, J18, J17, J16, H18, H17, J14, J13, H19, G18 High Output L2VSEL L2ADDR17:18 K19, W19 High Output L2VSEL L2AVDD L13 VDD L2CE P17 Low Output L2VSEL L2CLKOUTA N15 High Output L2VSEL L2CLKOUTB L16 High Output L2VSEL L2DATA[0:63] U14, R13, W14, W15, V15, U15, W16, V16, W17, V17, U17, W18, V18, U18, V19, U19, T18, T17, R19, R18, R17, R15, P19, P18, P13, N14, N13, N19, N17, M17, M13, M18, H13, G19, G16, G15, G14, G13, F19, F18, F13, E19, E18, E17, E15, D19, D18, D17, C18, C17, B19, B18, B17, A18, A17, A16, B16, C16, A14, A15, C15, B14, C14, E13 High I/O L2VSEL L2DP[0:7] V14, U16, T 19, N18, H14, F17, C19, B15 High I/O L2VSEL L2OVDD (11) D15, E14, E16, H16, J15, L15, M16, K13, P15, R14, R16, T15, F15 N/A L2SYNC_IN L14 High Input L2VSEL L2SYNC_OUT M14 High Output L2VSEL L2_TSTCLK(2) F7 High Input BVSEL L2VSEL(1)(3)(8)(9)(14) A19 High Input N/A Table 12-1. Pinout Listing for the PC7410, 360-ball CBGA and CI-CGA packages (Continued) Signal Name Pin Number Active I/O I/F Select (1)

0832F–HIREL–02/07 e2v semiconductors SAS 2007 PC7410 Notes: 1. OV DD supplies power to the processor bus, JTAG and all control signals except the L2 cache controls (L2CE, L2WE, and L2ZZ); L2OVDD supplies power to the L2 cache interface (L2ADDR[0:18], L2ASPARE, L2DATA[0:63], L2DP[0:7] and L2SYNC_OUT) and the L2 control signals and VDD supplies power to the processor core and the PLL and DLL (after filtering to become AVDD and L2AVDD respectively). These columns serve as a reference for the nominal voltage supported on a given signal as selected by the BVSEL/L2VSEL pin configurations of Table 6-2 on page 10 and the voltage supplied. For actual recommended value of VIN or supply voltages, see Table 6-3 on page 11. 2. These are test signals for factory use only and must be pulled up to OV DD for normal machine operation. L2WE N16 Low Output L2VSEL L2ZZ G17 High Output L2VSEL LSSD_MODE(2) F9 Low Input BVSEL MCP B11 Low Input BVSEL OVDD D5, D8, D12, E4, E6, E9, E11, F5, H4, J5, L5, M4, P5, R4, R6, R9, R11, T5, T8, T12 N/A PLL_CFG[0:3] A4, A5, A6, A7 High Input BVSEL QACK B2 Low Input BVSEL QREQ J3 Low Output BVSEL RSRV D3 Low Output BVSEL SHD0(8) B3 Low I/O BVSEL SHD1(5)(8) B4 Low I/O BVSEL SMI A12 Low Input BVSEL SRESET E10 Low Input BVSEL SYSCLK H9 Input BVSEL TA F1 Low Input BVSEL TBEN A2 High Input BVSEL TBST A11 Low Output BVSEL TCK B10 High Input BVSEL TDI(9) B7 High Input BVSEL TDO D9 High Output BVSEL TEA J1 Low Input BVSEL TMS(9) C8 High Input BVSEL TRST(9)(14) A10 Low Input BVSEL TS K7 Low I/O BVSEL TSIZ[0:2] A9, B9 , C9 High Output BVSEL TT[0:4] C10, D11, B12, C12, F11 High I/O BVSEL WT C3 Low I/O BVSEL VDD G8, G10, G12, J8, J10, J12, L8, L10, L12, N8, N10, N12 N/A Table 12-1. Pinout Listing for the PC7410, 360-ball CBGA and CI-CGA packages (Continued) Signal Name Pin Number Active I/O I/F Select (1)

0832F–HIREL–02/07 PC7410 e2v semiconductors SAS 2007 3. To allow for future I/O voltage changes, provide the option to connect BVSEL and L2VSEL independently to either OVDD (selects 2.5V), GND (selects 1.8V), or to HRESET (selects 2.5V). The PC7410 Both the 60x processor bus and the L2 bus only support the 1.8 and 2.5 options (see Table 6-2 on page 10). the default selection if BVSEL and/or L2VSEL is left uncon- nected is 2.5V. 4. Connect to HRESET to trigger post power-on-reset (por) internal memory test. 5. Ignored in 60x bus mode. 6. Unused output in 60x bus mode. 7. Deasserted (pulled high) at HRESET for 60x bus mode. 8. Uses one of 9 existing no-connects in PC750’s 360-ball BGA package. 9. Internal pull-up on die. 10. Reuses PC750’s DRTRY , DBDIS and TLBISYNC pins (DTI1, DTI2 and EMODE respectively). 11. The VOLTDET pin position on the PC750 360-ball CBGA package is now an L2OVDD pin on the PC7410 packages. 12. Output only for PC7410, was I/O for PC750. 13. Enhanced mode only. 14. To overcome the internal pull-up resistance and ensure this input will recognize a low signal, a pull-down resistance less than 250Ω should be used.

0832F–HIREL–02/07 e2v semiconductors SAS 2007 PC7410 Figure 12-5. Mechanical Dimensions and Bottom Surface Nomenclature of the 360-ball CBGA Package Notes: 1. Dimensioning and tolerancing per ASME Y14.5M, 1994 2. Dimensions in millimeters 3. Top side A1 corner index is a metallized feature with various shapes. Bottom side A1 corner is designated with a ball missing from the array Package Caps Value µF Voltage Reference C1-1 0.01 L2OVDD C1-2 GND C2-1 0.01 L2OVDD C2-2 GND C3-1 0.01 VDD C3-2 GND C4-1 0.01 OVDD C4-2 GND C5-1 0.01 OVDD C5-2 GND C6-1 0.01 VDD C6-2 GND Millimeters DIM MIN MAX A 2,72 3,2 A1 0,8 1 A2 1,1 1,3 A3 0,6 A4 0,82 0,9 b 0,82 0,93 D 25 BSC D2 10 typ D3 6,32 e1 , 2 7 BSC E 25 BSC E2 12,6 typ E3 8, 26 J1 0, 89 BSC J2 3,2 BSC J3 0, 68 BSC K1 6,56 K2 8,13 L1 8,61 L2 7,04 BC360X e 1 2 3 4 5 6 7 8 9 10 111213141516 A B C D E F G H J K L M N P R T A0.3 C0.15 B 171819 U W V D C6-2 C6-1 E2E B 0.2 0.2 A C1-1 C1-2 12X L2 L1 C5-1 C5-2 C2-2 C2-1 C4-1 C3-1 C3-2 C4-2 12X 12X A1 CORNER 0.15 A 0.25 A 0.35 A C A

0832F–HIREL–02/07 PC7410 e2v semiconductors SAS 2007

12.2 Substrate Capacito rs for the PC7410

Figure 12-6 shows the connectivity of the substrate capacitor pads for the PC7410, 360 CBGA package. Figure 12-6. Substrate Bypass Capacitors for the PC7410 C1-1 C1-2 C2-1 C2-2 C3-1 C3-2 C4-1 C4-2 C5-1 C5-2 C6-1 C6-2

0.01 L2OVDD

0.01 0.01 0.01 0.01 0.01 C1-1 C1-2 C2-1 C2-2 C3-2 C3-1 C4-2 C4-1 C5-2 C5-1 C6-1 C6-2 L1L2 A1 CORNER Package Caps Value µF Voltage Reference

0832F–HIREL–02/07 e2v semiconductors SAS 2007 PC7410 Figure 12-7. Mechanical Dimensions and Bottom Surface Nomenclature of the 360-ball HiTCE Package Notes: 1. Dimensioning and tolerancing per ASME Y14.5M, 1994 2. Dimensions in millimeters 3. Top side A1 corner index is a metallized feature with various shapes. Bottom side A1 corner is designated with a ball missing from the array Package Caps Value µF Voltage Reference C1-1 0.01 L2OVDD C1-2 GND C2-1 0.01 L2OVDD C2-2 GND C3-1 0.01 VDD C3-2 GND C4-1 0.01 OVDD C4-2 GND C5-1 0.01 OVDD C5-2 GND C6-1 0.01 VDD C6-2 GND Millimeters DIM MIN MAX A 2,72 3,2 A1 0,8 1 A2 1,1 1,3 A3 0,6 A4 0,82 0,9 b 0,82 0,93 D 25 BSC D2 10 typ D3 6,32 e1 , 2 7 BSC E 25 BSC E2 12,6 typ E3 8, 26 J1 0, 89 BSC J2 3,2 BSC J3 0, 68 BSC K1 6,56 K2 8,13 L1 8,61 L2 7,04 BC360X e 1 2 3 4 5 6 7 8 9 10 111213141516 A B C D E F G H J K L M N P R T A0.3 C0.15 B 171819 U W V D C6-2 C6-1 E2E B 0.2 0.2 A C1-1 C1-2 12X L2 L1 C5-1 C5-2 C2-2 C2-1 C4-1 C3-1 C3-2 C4-2 12X 12X A1 CORNER 0.15 A 0.25 A 0.35 A C A

0832F–HIREL–02/07 PC7410 e2v semiconductors SAS 2007

12.3 Substrate Capacito rs for the PC7410

Figure 12-8 shows the connectivity of the substrate capacitor pads for the PC7410, 360 HITCE package. Figure 12-8. Substrate Bypass Capacitors for the PC7410 C1-1 C1-2 C2-1 C2-2 C3-1 C3-2 C4-1 C4-2 C5-1 C5-2 C6-1 C6-2 0.01 0.01 0.01 0.01 0.01 C1-1 C1-2 C2-1 C2-2 C3-2 C3-1 C4-2 C4-1 C5-2 C5-1 C6-1 C6-2 L1L2 A1 CORNER Package Caps Value µF Voltage Reference

0832F–HIREL–02/07 e2v semiconductors SAS 2007 PC7410 Figure 12-9. Mechanical Dimensions and Bottom Surface Nomenclature of the 360-column CI-CGA Package A A 0.15 A FT360X G 1 2 3 4 5 6 7 8 9 10 111213141516 A B C D E F G H J K L M N P R T E0.3 T0.15 B 171819 U W V K K DPIN A1 E 0.22X B TOP VIEW INDEX 0.2 C 0.15 360X 0.35 A C1.1, C2.1 : L2OVDD C3.1, C6.1 : OVDD C4.1, C5.1 : OVDD

0832F–HIREL–02/07 PC7410 e2v semiconductors SAS 2007 13. Clock Selection The PC7410’s PLL is configured by the PLL_CFG[0 :3] signals. For a given SYSCLK (bus) frequency, the PLL configuration signals set the internal CPU and VCO frequency of operation. The PLL configura- tion for the PC7410 is shown in Table 13-1 for example frequencies. In this example, shaded cells represent settings that, for a given SYSCLK frequency, result in core and/or VCO frequencies that do not comply with the minimum and maximum core frequencies listed in Table 9-3 on page 21. Notes: 1. PLL_CFG[0:3] settings not listed are reserved. 2. The sample bus-to-core frequencies show n are for reference only. Some PLL configurations may select bus, core, or VCO frequencies which are not useful, not supported, or not tested for by the PC7410; see “Clock AC Specifications” on page 20 for valid SYSCLK, core, and VCO frequencies. 3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus mode is set for 1:1 mode operation. This mode is intended for factory use and third- party emulator tool development only. Note: The AC timing specifications given in this document do not apply in PLL-bypass mode. 4. In PLL-off mode, no clocking occurs insi de the PC7410 regardless of the SYSCLK input. 5. PLL-off mode should not be used during chip power-up sequencing. Table 13-1. PC7410 Microprocessor PLL Configuration(1)(2)(3)(4)(5) PLL_CFG [0:3] Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz) Bus-to- Core Multiplier Core-to- VCO Multiplier Bus

33.3 MHz

50 MHz

66.6 MHz

75 MHz

83.3 MHz

100 MHz

133 MHz

0110 2.5x 2x 1000 3x 2x 400 (800) 1110 3.5x 2x 350 (700) 465 (930) 1010 4x 2x 400 (800) 0111 4.5x 2x 375 (750) 450 (900) 1011 5x 2x 375 (750) 416 (833) 500 (1000) 1001 5.5x 2x 366 (733) 412 (825) 458 (916) 1101 6x 2x 400 (800) 450 (900) 500 (1000) 0101 6.5x 2x 433 (866) 488 (967) 0010 7x 2x 350 (700) 466 (933) 0001 7.5x 2x 375 (750) 500 (1000) 1100 8x 2x 400 (800) 0000 9x 2x 450 (900)

0011 PLL off/bypass PLL off, SYSCLK clocks core circuitry directly, 1x bus-to-core implied

1111 PLL off PLL off, no core clocking occurs

0832F–HIREL–02/07 e2v semiconductors SAS 2007 PC7410 The PC7410 generates the clock for the external L2 synchronous data SRAMs by dividing the core clock frequency of the PC7410. The divided-down clock is then phase-adjusted by an on-chip delay-lock-loop (DLL) circuit and should be routed from the PC74107410 to the external RAMs. A separate clock output, L2SYNC_OUT is sent out half the distance to the SRAMs and then returned as an input to the DLL on pin L2SYNC_IN so that the rising-edge of the clock as seen at the external RAMs can be aligned to the clocking of the internal latches in the L2 bus interface. The core-to-L2 frequency divisor for the L2 PLL is selected through the L2CLK bits of the L2CR register. Generally, the divisor must be chosen according to the frequency supported by the external RAMs, the frequency of the PC7410 core, and the phase adjustment range that the L2 DLL supports. Table 13-2 shows various example L2 clock frequencies that ca n be obtained for a given set of core frequencies. The minimum L2 frequency target is 133 MHz. Samp le core-to-L2 frequencies for the PC7410 is shown in Table 13-2. In this example, shaded cells represent settin gs that, for a given core frequency, result in L2 frequencies that do not comply with the minimum and maximum L2 frequencies listed in Table 9-6 on page 28. Note: The core and L2 frequencies are for reference only. Some examples may represent core or L2 frequencies which are not useful, not supported or not tested for by the PC7410; see “L2 Clock AC Specifications” on page 24 for valid L2CLK frequencies. The L2CR[L2SL] bit should be set for L2CLK frequencies less than 150 MHz. 14. System Design Information

14.1 PLL and DLL Po wer Supply Filtering

The AVDD and L2AVDD power signals are provided on the PC7410 to supply power to the PLL and DLL, respectively. Both AVDD and L2AVDD can be supplied power from the V DD power plane. High frequency noise in the 500 kHz to 10 MHz resonant frequency range of the PLL on the V DD power plane could affect the stability of the internal clocks. On systems that use the PC7410 HCTE device, the AV DD and L2AVDD input signals should both imple- ment the circuit shown in Figure 14-1 on page 44. On systems that use the PC7410 CBGA device, the L2AVDD input should implement the circuit shown in Figure 14-1. Table 13-2. Sample Core-to-L2 Frequencies Core Frequency in MHz ÷1 ÷1.5 ÷2 ÷2.5 ÷3 ÷3.5 ÷4 350 350 233 175 140 – – – 366 366 244 183 147 – – – 400 400 266 200 160 133 – – 433 – 288 216 173 144 – – 450 – 300 225 180 150 – – 466 – 311 233 186 155 133 – 500 – 333 250 200 166 143 –

0832F–HIREL–02/07 e2v semiconductors SAS 2007 PC7410

14.2 Power Supply Voltage Sequency

The notes in Table 6-1 on page 9 contain cautions about the sequencing of the external bus voltages and core voltage of the PC7410 (when they are different). These cautions are necessary for the long term reliability of the part. If they are violated, the electrostatic discharge (ESD) protection diodes will be forward-biased and excessive current can flow through these diodes. If the system power supply design does not control the voltage sequencing, one or both of the circuits of Figure 14-3 can be added to meet these requirements. The MUR420 Schottky diodes of Figure 14-3 control the maximum potential differ- ence between the external bus and core power supplies on power-up and the 1N5820 diodes regulate the maximum potential difference on power-down. Figure 14-3. Example Voltage Sequencing Circuits

14.3 Decoupling Recommendations

Due to the PC7410’s dynamic power management feature, large address and data buses and high oper- ating frequencies, the PC7410 can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. Th is noise must be prevented from reach- ing other components in the PC7410 system and the PC7410 itself requires a clean, tightly regulated source of power. Therefore, it is recommended t hat the system designer place at least one decoupling capacitor at each VDD, OVDD, and L2OVDD pin of the PC7410. It is also recommended that these decou- pling capacitors receive their power from separate V DD, (L2)OVDD, and GND power planes in the PCB, utilizing short traces to minimize inductance. These capacitors should have a value of 0.01 µF or 0.1 µF. Only ceramic SMT (surface mount technol- ogy) capacitors should be used to minimize lead inductance, preferably 0508 or 0603 orientations where connections are made along the length of the part. Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993) and contrary to previous recommendations for decoupling PowerPC microprocessors, multiple small capacitors of equal value are recommended over using multiple values of capacitance. In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the V DD, L2OVDD, and OVDD planes to enable quick recharging of the smaller chip capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should also be c onnected to the power and ground planes through two vias to minimize inductance. Su ggested bulk capacitors are 100 - 330 µF (AVX TPS tantalum or Sanyo OSCON). MUR420 MUR420 1N5820 1N5820 1.8V2.5V

0832F–HIREL–02/07 PC7410 e2v semiconductors SAS 2007

14.4 Connection Recommendations

To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. Unused active low inputs should be tied to OV DD. Unused active high inputs should be connected to GND. All NC (no-connect) signals must remain unconnected. Power and ground connections must be made to all external V DD, OVDD, L2OVDD, and GND pins of the PC7410. See “L2 Clock AC Specifications” on page 24 for a discussion of the L2SYNC_OUT and L2SYNC_IN signals.

14.5 Output Buffer DC Impedance

The PC7410 60x and L2 I/O drivers are characterized over process, voltage and temperature. To mea- sure Z 0, an external resistor is connected from the chip pad to OV DD or GND. Then the value of each resistor is varied until the pad voltage is OVDD/2 (see Figure 14-4). The output impedance is the average of two components, the resistances of the pull-up and pull-down devices. When data is held low, SW2 is closed (SW1 is open), and RN is trimmed until the voltage at the pad equals OVDD/2. RN then becomes the resistance of the pull-down devices. When data is held high, SW1 is closed (SW2 is open), and R P is trimmed until the voltage at the pad equals OV DD/2. RP then becomes the resistance of the pull-up devices. R P and R N are designed to be close to each other in value. Then Z0 = (RP + RN)/2. Figure 14-4 describes the driver impedance measurement circuit described above. Figure 14-4. Driver Impedance Measurement Circuit Alternately, the following is another method to determine the output impedance of the PC7410. A voltage source, Vforce, is connected to the output of the PC7410, as in Figure 14-4. Data is held low, the voltage source is set to a value that is equal to (L2)OVDD/2, and the current sourced by Vforce is measured. The voltage drop across the pull-down device, which is equal to (L2)OV DD/2, is divided by the measured cur- rent to determine the output impedance of the pull-down device, RN. Similarly, the impedance of the pull- up device is determined by dividing the voltage drop of the pull-up, (L2)OV DD/2, by the current sank by the pull-up when the data is high and Vforce is equal to (L2)OV DD/2. This method can be employed with either empirical data from a test setup or with data from simulation models, such as IBIS. OVDD OGND SW2 SW1 RN RP Pad Data

0832F–HIREL–02/07 e2v semiconductors SAS 2007 PC7410 RP and RN are designed to be close to each other in value. Then, Z0 = (RP + RN)/2. Figure 14-5 describes the alternate driver impedance measurement circuit. Figure 14-5. Alternate Driver Impedance Measurement Circuit Table 14-1 summarizes the signal impedance results. The driver impedance values were characterized at 0°, 65°, and 105°C. The impedance increases with junction temperature and is relatively unaffected by bus voltage.

14.6 Pull-up Resistor Requirements

The PC7410 requires pull-up resistors (1 kΩ – 5 kΩ) on several control pins of the bus interface to main- tain the control signals in the negated state after they have been actively negated and released by the PC7410 or other bus masters. These pins are: TS , ARTRY, SHDO, SHD1. Four test pins also require pull-up resistors (100 Ω – 1 k Ω). These pins are CHK , L1_TSTCLK, L2_TSTCLK, and LSSD_MODE . These signals are for factory use only and must be pulled up to OV DD for normal machine operation. If pull-down resistors are used to configure BVSE L or L2VSEL, the resistors should be less than 250 Ω. (see Table 12-1 on page 33 ). Because PLL_CFG[0:3] must remain stable during normal operation, strong pull-up and pull-down resistors (1 k Ω or less) are recommended to configure these signals in order to protect against erroneous switching due to ground bounce, power supply noise or noise coupling. In addition, CKSTP_OUT is an open-drain style output that requires a pull-up resistor (1 k Ω–5 kΩ) if it is used by the system. The CKSTP_IN signal should likewise be pulled up through a pull-up resistor (1 kΩ– 5 kΩ) to prevent erroneous assertions of this signal. Table 14-1. Impedance Characteristics with VDD = 1.8V, OVDD = 2.5V, TJ = 0° C - 105° C Impedance Processor bus L2 Bus Symbol Unit RN 41.5 – 54.3 42.7 – 54.1 Z 0 Ω RP 37.3 – 55.3 39.3 – 50 Z 0 Ω (L2)OVDD BGA Data Pin Vforce OGND

0832F–HIREL–02/07 PC7410 e2v semiconductors SAS 2007 During inactive periods on the bus, the address and transfer attributes may not be driven by any master and may, therefore, float in the high-impedance stat e for relatively long periods of time. Since the PC7410 must continually monitor these signals for snooping, this float condition may cause excessive power draw by the input receivers on the PC7410 or by other receivers in the system. These signals can be pulled up through weak (10 k Ω) pull-up resistors by the system, address bus driven mode can be enabled (see the PC7410 RISC Microporcessor Family Users’ Manual for more information on this mode), or these signals may be otherwise driven by t he system during inactive periods of the bus to avoid this additional power draw. The snooped addres s and transfer attribute inputs are: A[0:31], AP[0:3], TT[0:4], CI , WT, and GBL. In systems where GBL is not connected and other devices may be asserting TS for a snoopable transac- tion while not driving GBL to the processor, we recommend that a strong (1 k Ω) pull-up resistor be used on GBL. Note that the PC7410 will only snoop transactions when GBL is asserted. The data bus input receivers are normally turned off when no read operation is in progress and, there- fore, do not require pull-up resistors on the bus. Other data bus receivers in the system, however, may require pull-ups, or that those signals be otherwise driven by the system during inactive periods by the system. The data bus signals are: DH[0:31], DL[0:31], and DP[0:7]. If address or data parity is not used by the system, and the respective parity checking is disabled through HID0, the input receivers for those pins are disabled , and those pins do not require pull-up resistors and should be left unconnected by the system. If parity checking is disabled through HID0, and parity gener- ation is not required by the PC7410 (note that the PC7410 always generates parity), then all parity pins may be left unconnected by the system. The L2 interface does not normally require pull-up resistors.

14.7 JTAG Configuration Signals

Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the IEEE 1149.1 specification, but is provided on all pr ocessors that implement the PowerPC architecture. While it is possible to force the TAP controller to the reset state using only the TCK and TMS signals, more reliable power-on reset performance will be obtained if the TRST signal is asserted during power- on reset. Because the JTAG interface is also used for acce ssing the common on-chip processor (COP) function, simply tying TRST to HRESET is not practical. The COP function of these processors allows a remote computer system (typically, a PC with dedicated hardware and debugging software) to access and control the internal operations of the processor. The COP interface connects primarily through the JTAG port of the processor, with some additional status monitoring signals. The COP port requires the ability to independently assert HRESET or TRST in order to fully control the processor. If the target system has independent reset sources, such as voltage moni- tors, watchdog timers, power supply failures, or push-button switches, then the COP reset signals must be merged into these signals with logic. The arrangement shown in Figure 14-6 on page 50 allows the COP port to independently assert HRESET or TRST, while ensuring that the target can drive HRESET as well. If the JTAG interface and COP header will not be used, TRST should be tied to HRESET through a 0Ω isolation resistor so that it is asserted when the system reset signal (HRESET ) is asserted ensuring that the JTAG scan chain is ini- tialized during power-on. While Freescale recommends that the COP header be designed into the system as shown in Figure 14-6, if this is not possible, the isolati on resistor will allow future access to TRST in the case where a JTAG interface may need to be wired onto the system in debug situations.

0832F–HIREL–02/07 e2v semiconductors SAS 2007 PC7410 The COP header shown in Figure 14-6 on page 50 adds many benefits — breakpoints, watchpoints, reg- ister and memory examination/modification, and ot her standard debugger features are possible through this interface — and can be as inexpensive as an unpopulated footprint for a header to be added when needed. The COP interface has a standard header for connection to the target system, based on the 0.025" square-post 0.100" centered header assembly (often called a Berg header). The connector typically has pin 14 removed as a connector key. There is no standardized way to number the COP header shown in Figure 14-6; consequently, many dif- ferent pin numbers have been observed from emulator vendors. Some are numbered top-to-bottom then left-to-right, while others use left-to-right then top- to-bottom, while still others number the pins counter clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement recommended in Figure 14-6 is common to all known emulators. The QACK signal shown in Figure 14-6 is usually connected to the PCI bridge chip in a system and is an input to the PC7410 informing it that it can go into the quiescent state. Under normal operation this occurs during a low-power mode selection. In order for COP to work, the PC7410 must see this signal asserted (pulled down). While shown on the COP header, not all emulator products drive this signal. If the product does not, a pull-down resistor can be populated to assert this signal. Additionally, some emu- lator products implement open-drain type outputs and can only drive QACK asserted; for these tools, a pull-up resistor can be implemented to ensure this signal is deasserted when it is not being driven by the tool. Note that the pull-up and pull-down resistors on the QACK signal are mutually exclusive and it is never necessary to populate both in a system. To preserve correct power-down operation, QACK should be merged via logic so that it also can be driven by the PCI bridge.

0832F–HIREL–02/07 PC7410 e2v semiconductors SAS 2007 Figure 14-6. COP Connector Diagram Notes: 1. RUN/STOP , normally found on pin 5 of the COP header, is not implemented on the PC7410. Connect pin 5 of the COP header to OVDD with a 10 kΩ pull-up resistor. 2. Key location; pin 14 is not physically present on the COP header. 3. Component not populated. Populate only if debug tool does not drive QACK . 4. Populate only if debug tool uses an open-drain type output and does not actively deassert QACK . 5. If the JTAG interface is implemented, connect HRESET from the target source to TRST from the COP header though an AND gate to TRST of the part. If the JTAG interface is not implemented, connect HRESET from the target source to TRST of the part through a 0Ω isolation resistor. 6. The COP port and target board should be able to independently assert HRESET and TRST to the pro- cessor in order to fully control the processor as shown above. HRESET HRESET HRESET SRESET SRESET SRESET NC NC VDD_SENSE6 5(1) 2 kΩ 10 kΩ 10 kΩ 10 kΩ OVDD OVDD OVDD OVDD CHKSTP_IN CHKSTP_IN8 TMS TDO TDI TCK TMS TDO TDI TCK TRST COP Header 14(2) Key QACK OVDD OVDD 10 kΩ OVDD TRST 10 kΩ OVDD 10 kΩ 10 kΩ QACK QACK CHKSTP_OUTCHKSTP_OUT KEY No pin COP Connector Physical Pin Out 10 kΩ(4) OVDD 2 kΩ(3) 0Ω (5) From Target Board Sources (if any) (6) (6)

0832F–HIREL–02/07 e2v semiconductors SAS 2007 PC7410 Boundary scan testing is enabled through the JTAG interface signals. (BSDL descriptions of the PC7410 are available on the Internet at www.mot.com/PowerPC/teksupport.) The TRST signal is optional in the IEEE 1149.1 specification but is provided on all PowerPC implementa tions. While it is possible to force the TAP controller to the reset state using only the TCK and TMS signals, more reliable power-on reset performance will be obtained if the TRST signal is asserted during power-on reset. Since the JTAG inter- face is also used for accessing the common on-chi p processor (COP) function of PowerPC processors, simply tying TRST to HRESET is not practical. The common on-chip processor (COP) function of PowerPC processors allows a remote computer sys- tem (typically a PC with dedicated hardware and debugging software) to access and control the internal operations of the processor. The COP interface connects primarily through the JTAG port of the proces- sor with some additional status monitoring signals. The COP port requires the ability to independently assert HRESET or TRST in order to fully control the processor. If the target system has independent reset sources, such as voltage monitors, watchdog timers, power supply failures or push-button switches, then the COP reset signals must be merged into these signals with logic. The arrangement shown in Figure 14-6 on page 50 allows the COP to independently assert HRESET or TRST, while ensuring that the target can drive HRESET as well. The pull-down resistor on TRST ensures that the JTAG scan chain is initialized during power-on if a JTAG interface cable is not attached; if it is attached, it is responsible for driving TRST when needed. Table 14-2. COP Pin Definitions Pins Signal Connection Special Notes 1T D O T D O 2Q A C K QACK Add 2K pull-down to ground. Must be merged with on-board QACK , if any 3T D I T D I 4T R S T TRST Add 2K pull-down to ground. Must be merged with on-board TRST if any See Figure 14-6 on page 50

5 RUN/STOP No Connect Used on 604e; leave no-connect for all other processors

6 VDD_SENSE VDD Add 2K pull-up to OV DD (for short circuit limiting protection only)

8 CKSTP_IN CKSTP_IN Optional. Add 10K pull-up to OVDD. Used on several emulator products. Useful for checkstopping the processor from a logic analyzer of other external trigger 9T M S T M S

10 N/A

11 SRESET SRESET Merge with on-board SRESET , if any

12 N/A

13 HRESET HRESET Merge with on-board HRESET

14 N/A Key location; pin should be removed

15 CKSTP_OUT CKSTP_OUT Add 10K pull-up to OV DD

16 Ground Digital Ground

0832F–HIREL–02/07 PC7410 e2v semiconductors SAS 2007 The COP header shown in Figure 14-6 on page 50 adds many benefits – breakpoints, watchpoints, reg- ister and memory examination/modification and other standard debugger features are possible through this interface – and can be as inexpensive as an unpopulated footprint for a header to be added when needed. The COP interface has a standard header for connection to the target system, based on the 0.025” square-post 0.100” centered header assembly (often called a “Berg” header). The connector typically has pin 14 removed as a connector key, as shown in Figure 14-6. 15. Ordering Information Notes: 1. For availability of the different versions, contact your local e2v sales office. 2. The letter X in the part number designates a "Prototype" pr oduct that has not been qualified by e2v. Reliability of a PCX part- number is not guaranteed and such part-number shall not be used in Flight Hardware. Product changes may still occur while shipping prototypes. 16. Definitions

16.1 Life Support Applications

These products are not designed for use in life s upport appliances, devices or systems where malfunc- tion of these products can reasonably be expected to result in personal injury. e2v customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify e2v for any damages resulting from such improper use or sale. G: CBGA GS: CI-CBGA GH: HITCE U: Upscreening blank: Std

400 MHz

450 MHz

500 MHz

7410 L: 1.8V ± 100 mV N: 1.5V ± 50 mV E Product Code(1) PC(X)(2) Package(1) Max Internal Processor Speed(1) Revision Level(1) Application Modifier (1) Temperature Range TJ (1) V: -40˚C, +110˚C M: -55˚C, +125˚C

i 0832F–HIREL–02/07 e2v semiconductors SAS 2007 PC7410 Table of Contents

0832F–HIREL–02/07 PC7410 e2v semiconductors SAS 2007

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0832F–HIREL–02/07 PC7410 e2v semiconductors SAS 2007