PC56F8006VWL

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Document Number: MC56F8006 Rev. 4, 06/2011 © Freescale Semiconductor, Inc., 2009–2011. All rights reserved. Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. MC56F8006/MC56F8002 48-pin LQFP Case: 932-03 7 x 7 mm2 28-pin SOIC Case: 751F-05 7.5 x 18 mm 32-pin LQFP Case: 873A-03 7 x 7 mm 32-pin PSDIP Case: 1376-02 9 x 28.5 mm This document applies to parts marked with 2M53M. The 56F8006/56F8002 is a member of the 56800E core-based family of digital signal controllers (DSCs). It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to create a cost-effective solution. Because of its low cost, configuration flexibility, and compact program code, the 56F8006/56F8002 is well-suited for many applications. It includes many peripherals that are especially useful for cost-sensitive applications, including:

• Industrial control
• Home appliances
• Smart sensors
• Fire and security systems
• Switched-mode power supply and power management
• P o w e r m e t e r i n g
• Motor control (ACIM, BLDC, PMSM, SR, and stepper)
• Handheld power tools
• Arc detection
• Medical device/equipment
• Instrumentation
• Lighting ballast The 56800E core is based on a dual Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and optimized instruction set allow straightforward generation of efficient, compact DSP and control code. The instruction set is also highly efficient for C compilers to enable rapid development of optimized control applications. The 56F8006/56F8002 supports program execution from internal memories. Two data operands can be accessed from the on-chip data RAM per instruction cycle. The 56F8006/56F8002 also offers up to 40 general-purpose input/output (GPIO) lines, depending on peripheral configuration. The 56F8006/56F8002 digital signal controller includes up to

16 KB of program flash and 2 KB of unified data/program

RAM. Program flash memory can be independently bulk erased or erased in small pages of 512 bytes (256 words). On-chip features include:

• Up to 32 MIPS at 32 MHz core frequency
• DSP and MCU functionality in a unified, C-efficient architecture
• On-chip memory – 56F8006: 16 KB (8K x 16) flash memory – 56F8002: 12 KB (6K x 16) flash memory – 2 KB (1K x 16) unified data/program RAM
• One 6-channel PWM module
• Two 28-channel, 12-bit analog-to-digital converters (ADCs)
• Two programmable gain amplifiers (PGA) with gain up to 32x
• Three analog comparators
• One programmable interval timer (PIT)
• One high-speed serial comm unication interface (SCI) with LIN slave functionality
• One serial peripheral interface (SPI)
• One 16-bit dual timer (2 x 16 bit timers)
• One programmable delay block (PDB)
• One SMBus compatible inter-integrated circuit (I 2C) port
• One real time counter (RTC)
• Computer operating properly (COP)/watchdog
• Two on-chip relaxation oscillators — 1 kHz and 8 MHz (400 kHz at standby mode)
• Crystal oscillator
• Integrated power-on reset (POR) and low-voltage interrupt (LVI) module
• JTAG/enhanced on-chip emulation (OnCE™) for unobtrusive, real-time debugging
• Up to 40 GPIO lines
• 28-pin SOIC, 32-pin LQFP, 32-pin PSDIP, and 48-pin LQFP packages MC56F8006/MC56F8002 Digital Signal Controller

MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor2 Table of Contents

6.8 Joint Test Action Group (JTAG)/Enhanced On-Chip

8.11 Reset, Stop, Wait, Mode Select, and Interrupt Timing. 56 Appendix A Appendix B

1 MC56F8006/MC56F8002 Family Configuration

MC56F8006/MC56F8002 device comparison in Table 1. Table 1. MC56F8006 Series Device Comparison 1 Some ADC inputs share the same pin. See Table 4.

8 MHz (400 kHz at standby mode) on-chip ROSC Y es

2 Block Diagram

family are described later in this document. Italics indicate a 56F8002 device parameter. Figure 1. MC56F8006/MC56F8002 Block Diagram

3 Overview

3.1.1 Core

• Efficient 16-bit 56800E family digital signal controller (DSC) engine with dual Harvard architecture
• As many as 32 million instructions per second (MIPS) at 32 MHz core frequency
• 155 basic instructions in conjunction with up to 20 address modes
• Single-cycle 16  16-bit parallel multiplier-accumulator (MAC)
• Four 36-bit accumulators, including extension bits
• 32-bit arithmetic and logic multi-bit shifter Program Controller and Hardware Looping Unit Data ALU 16 x 16 + 36  36-Bit MAC Three 16-bit Input Registers Four 36-bit Accumulators Address Generation Unit Bit Manipulation Unit 16-Bit 56800E Core Interrupt Controller Unified Data / Program RAM 2KB PDB CDBR SPI IPBus Bridge R/W Control Memory PAB CDBW JTAG/EOnCE Port or GPIOD Digital Reg Analog Reg Low-Voltage Supervisor VDD VSS VDDA VSSA RESET Dual GP Timer ADCA

24 Total

16 Kbytes flash

12 Kbytes flash

3 Fault Inputs

MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 5

• Parallel instruction set with unique DSP addressing modes
• Hardware DO and REP loops
• Three internal address buses
• Four internal data buses
• Instruction set supports DSP and controller functions
• Controller-style addressing modes and instructions for compact code
• Efficient C compiler and local variable support
• Software subroutine and interrupt stack with depth limited only by memory
• JTAG/enhanced on-chip emulation (EOnCE) for unobtrusive, processor speed–independent, real-time debugging

3.1.2 Operation Range

• 1.8 V to 3.6 V operation (power supplies and I/O)
• From power-on-reset: approximately 1.9 V to 3.6 V
• Ambient temperature operating range: — –40 °C to 125 °C

3.1.3 Memory

• Dual Harvard architecture permits as many as thr ee simultaneous accesses to program and data memory
• Flash security and protection that prevent unauthorized users from gaining access to the internal flash
• On-chip memory — 16 KB of program flash for 56F8006 and 12 KB of program flash for 56F8002 — 2 KB of unified data/program RAM
• EEPROM emulation capability using flash

3.1.4 Interrupt Controller

• Five interrupt priority levels — Three user programmable priority levels for each interrupt source: Level 0, 1, 2 — Unmaskable level 3 interrupts include: illegal instruction, hardware stack overflow, misaligned data access, SWI3 instruction. Maskable level 3 interrupts include: EOnCE step counter, EOnCE breakpoint unit, EOnCE trace buffer — Lowest-priority software interrupt: level LP
• Allow nested interrupt that higher priority level interrup t request can interrupt lower priority interrupt subroutine
• The masking of interrupt priority level is managed by the 56800E core
• One programmable fast interrupt that can be assigned to any interrupt source
• Notification to system integration module (SIM) to restart clock out of wait and stop states
• Ability to relocate interrupt vector table

3.1.5 Peripheral Highlights

• One multi-function, six-output pulse width modulator (PWM) module — Up to 96 MHz PWM operating clock — 15 bits of resolution — Center-aligned and edge-aligned PWM signal mode — Phase shifting PWM pulse generation

MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Overview Freescale Semiconductor6 — Four programmable fault inputs with programmable digital filter — Double-buffered PWM registers — Separate deadtime insertions for rising and falling edges — Separate top and bottom pulse-width correction by means of software — Asymmetric PWM output within both Center Aligned and Edge Aligned operation — Separate top and botto m polarity control — Each complementary PWM signal pair allows selection of a PWM supply source from: – PWM generator – Internal timers – Analog comparator outputs

• Two independent 12-bit analog-to-digital converters (ADCs) — 2 x 14 channel external inputs plus seven internal inputs — Support simultaneous and software triggering conversions — ADC conversions can be synchronized by PWM and PDB modules — Sampling rate up to 400 KSPS for 10- or 12-bit conversion result; 470 KSPS for 8-bit conversion result — Two 16-word result registers
• Two programmable gain amplifier (PGAs) — Each PGA is designed to am plify and convert differential signals to a single-ended value fed to one of the ADC inputs — 1X, 2X, 4X, 8X, 16X, or 32X gain — Software and hardware triggers are available — Integrated sample/hold circuit — Includes additional calibration features: – Offset calibration eliminates any errors in the internal reference used to generate the VDDA/2 output center point – Gain calibration can be used to veri fy the gain of the overall datapath – Both features require software correction of the ADC result
• Three analog comparators (CMPs) — Selectable input source includes external pins, internal DACs — Programmable output polarity — Output can drive timer input, PWM fault input, PWM source, external pin output, and trigger ADCs — Output falling and rising edge detection able to generate interrupts
• One dual channel 16-bit multi-purpose timer module (TMR) — Two independent 16-bit counter/timers with cascading capability — Up to 96 MHz operating clock — Each timer has capture and compare and quadrature decoder capability — Up to 12 operating modes — Four external inputs an d two external outputs
• One serial communicatio n interface (SCI) with LIN slave functionality — Up to 96 MHz operating clock — Full-duplex or single-wire operation — Programmable 8- or 9- bit data format — Two receiver wakeup methods: – Idle line – Address mark

MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 7 — 1/16 bit-time noise detection

• One serial peripheral interface (SPI) — Full-duplex operation — Master and slave modes — Programmable length transactions (2 to 16 bits) — Programmable transmit and recei ve shift order (MSB as first or last bit transmitted) — Maximum slave module frequency = module clock frequency/2
• One inter-integrated Circuit (I 2C) port — Operates up to 400 kbps — Supports master and slave operation — Supports 10-bit address mode and broadcasting mode — Supports SMBus, Version 2
• One 16-bit programmable interval timer (PIT) — 16 bit counter with programmable counter modulo — Interrupt capability
• One 16-bit programmable delay block (PDB) — 16 bit counter with programmable counter modulo and delay time — Counter is initiated by positive transition of internal or external trigger pulse — Supports two independently controlled delay pulses used to synchronize PGA and ADC conversions with input trigger event — Two PDB outputs can be ORed together to schedule two conversions from one input trigger event — PDB outputs can be can be used to schedule precise edge placement for a pulsed output that generates the control signal for the CMP windowing comparison — Supports continuous or single shot mode — Bypass mode supported
• Computer operating properly (COP)/watchdog time r capable of selecting different clock sources — Programmable prescaler and timeout period — Programmable wait, stop, and partial powerdown mode operation — Causes loss of reference reset 128 cycles after loss of reference clock to the PLL is detected — Choice of clock sources from four sources in support of EN60730 and IEC61508: – On-chip relaxation oscillator – External crystal oscillat or/external clock source – System clock (IPBus up to 32 MHz) – On-chip low power 1 kHz oscillator
• Real-timer counter (RTC) — 8-bit up-counter — Three software selectable clock sources – External crystal oscillat or/external clock source – On-chip low-power 1 kHz oscillator – System bus (IPBus up to 32 MHz) — Can signal the device to exit power down mode
• Phase lock loop (PLL) provides a high- speed clock to the core and peripherals — Provides 3x system clock to PWM and dual timer and SCI — Loss of lock interrupt — Loss of reference clock interrupt

MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Overview Freescale Semiconductor8

• Clock sources — On-chip relaxation oscillator with two user selectab le frequencies: 400 kHz for low speed mode, 8 MHz for normal operation — On-chip low-power 1 kHz oscillator can be se lected as clock source to the RTC and/or COP — External clock: crystal oscillator, ceram ic resonator, and external clock source
• Power management controller (PMC) — On-chip regulator for digital and analog circuitry to lower cost and reduce noise — Integrated power-on reset (POR) — Low-voltage interrupt with a user select able trip voltage of 1.81 V or 2.31 V — User selectable brown-out reset — Run, wait, and stop modes — Low-power run, wait, and stop modes — Partial power down mode
• Up to 40 general-purpose I/O (GPIO) pins — Individual control for each pin to be in peripheral or GPIO mode — Individual input/output direction control for each pin in GPIO mode — Hysteresis and configurable pullup device on all input pins — Configurable slew rate and drive strength and optional input low pass filters on all output pins — 20 mA sink/source current
• JTAG/EOnCE debug programming interface for real-time debugging — IEEE 1149.1 Joint Test Action Group (JTAG) interface — EOnCE interface for real-time debugging

3.1.6 Power Saving Features

• Three low power modes — Low-speed run, wait, and stop modes: 200 kHz IP bus clock provided by ROSC — Low-power run, wait, and stop modes: cl ock provided by external 32–38.4 kHz crystal — Partial power down mode
• Low power external oscillator can be used in any low-power mode to provide accurate clock to active peripherals
• Low power real time counter for use in run, wait, and stop modes with internal and external clock sources
• 32 s typical wakeup time from partial power down modes
• Each peripheral can be indivi dually disabled to save power

3.2 Award-Winning Development Environment

Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use component-based software application creation with an expert knowledge system. The CodeWarrior Integrated Development Environment is a sophisticated tool for code navigation, compiling, and debugging. A complete set of evaluation modules (EVMs), demonstration board kit, and development system cards support concurrent engineering. Together, PE, CodeWarrior, and EVMs create a complete, scalable tools solution for easy, fast, and efficient development. A full set of programmable peripherals — PWM, PGAs, ADCs, SCI, SPI, I2C, PIT, timers, and analog comparators — supports various applications. Each peripheral can be independently shut down to save power. Any pin in these peripherals can also be used as general-purpose input/outputs (GPIOs).

3.3 Architecture Block Diagram

communicate with internal memories and the IPBus interface and the internal connections among each unit of the 56800E core. Figure 2. 56800E Core Block Diagram

Figure 3. Peripheral Subsystem

3.4 Product Documentation

The documents listed in Table 2 are required for a complete description and proper design with the 56F8006/56F8002. Distribution Centers, or online at http://www.freescale.com.

4 Signal/Connection Descriptions

4.1 Introduction

summarizes all device pins. In Table 4, each table row describes the signal or signals present on a pin, sorted by pin number. Table 2. 56F8006/56F8002 Device Documentation Table 3. Functional Group Pin Allocations 1 Pins may be shared with other peripherals. See Table 4.

In Table 4, peripheral pins in bold identify reset state. Table 4. 56F8006/56F8002 Pins

10 GPIOC7 /ANB5 and

14 GPIOE3 /ANA10 and

16 GPIOE5/ ANA8 and

18 GPIOE4/ANA6 and

21 V DD VDD

4.2 Pin Assignment

shown in Figure 6; MC56F8006 48-pin low-profile quad flat pack (48LQFP) is shown in Figure 7.

28 GPIOE6 E6

30 V SS VSS

31 V DD VDD

34 GPIOE7/ CMP1_M3 E7 CMP1_M3

40 GPIOF1 /CMP1_P3 F1 CMP1_P3

41 GPIOF2 /CMP0_M3 F2 CMP0_M3

42 GPIOF3 /CMP0_P3 F3 CMP0_P3

46 GPIOC3/ EXT_TRIGGER C3 EXT_

Table 4. 56F8006/56F8002 Pins (continued)

Figure 4. Top View, MC56F8006/MC56F8002 28-Pin SOIC Package

Figure 5. Top View, MC56F8006 32-Pin LQFP Package

Figure 6. Top View, MC56F8006 32-Pin PSDIP Package

Figure 7. Top View, MC56F8006 48-Pin LQFP Package needs to be set too. EXT_SEL bit in OSCTL selects CLKIN or XTAL.

Table 5. 56F8006/56F8002 Signal and Package Information VDD 21 Supply Supply I/O Power — This pin supplies 3.3 V power to the chip I/O interface. VSS 8 13 9 20 Supply Supply I/O Ground — These pins provide ground for chip I/O interface. modules. It must be connected to a clean analog power supply. modules. It must be connected to a clean power supply. Reset — This input is a direct hardware reset on the processor. the reset state. A Schmitt-trigger input is used for noise immunity. internal clocks after a fixed number of internal clocks. After reset, the default state is RESET. After reset, the default state is GPIOA0. After reset, the default state is GPIOA1. After reset, the default state is GPIOA2.

to device pins to speed startup. After reset, the default state is GPIOA3. outputs in cases where fault conditions originate off-chip. After reset, the default state is GPIOA4. outputs in cases where fault conditions originate off-chip. positive pulse at the start of every PWM cycle. After reset, the default state is GPIOA5. Table 5. 56F8006/56F8002 Signal and Package Information (continued)

outputs in cases where fault conditions originate off-chip. ANA1 and ANB1 — Analog input to channel 1 of ADCA and ADCB. select register (CLKOUT) in the SIM. After reset, the default state is GPIOA6. SCL — The I 2C serial clock. T1 — Dual timer module channel 1 input/output. After reset, the default state is GPIOB0.

the current transfer is to be received. SDA — The I 2C serial data line. Positive input 3 of analog comparator 2. After reset, the default state is GPIOB1. the slave device is not selected. TIN2 — Dual timer module channel 2 input. ANA2 and ANB2 — Analog input to channel 2 of ADCA and ADCB. CMP0_OUT— Analog comparator 0 output. After reset, the default state is GPIOB2.

data output. In slave mode, this pin serves as the data input. TIN3 — Dual timer module channel 3 input. ANA3 and ANB3 — Analog input to channel 3 of ADCA and ADCB. CMP1_OUT— Analog comparator 1 output. After reset, the default state is GPIOB3. T0 — Dual timer module channel 0 input/output. select register (CLKOUT) of the SIM. the slave device is not selected. RXD — The SCI receive data input. ANA0 and ANB0 — Analog input to channel 0 of ADCA and ADCB. After reset, the default state is GPIOB4.

T1 — Dual timer module channel 1 input/output. outputs in cases where fault conditions originate off-chip. After reset, the default state is GPIOB5. SDA — The I 2C serial data line. positive input 2 of analog comparator 0. External Clock Input — This pin serves as an external clock input. After reset, the default state is GPIOB6. SCL — The I 2C serial clock. negative input 3 of analog comparator 2. After reset, the default state is GPIOB7.

negative input 1 of analog comparator 1. outputs in cases where fault conditions originate off-chip. After reset, the default state is ANA5 and CMP1_M1. After reset, the default state is ANA7 and PGA0+ and CMP2_M2. After reset, the default state is ANA9 and PGA0– and CMP2_P4.

46 Input/

EXT_TRIGGER — PDB external trigger input. After reset, the default state is GPIOC3.

After reset, the default state is ANB8 and PGA1+ and CMP0_M2. After reset, the default state is ANB6 and PGA1– and CMP0_P4. positive input 1 of analog comparator 1. After reset, the default state is ANB4 and CMP1_P1.

10 Input/

negative input 2 of analog comparator 1. After reset, the default state is GPIOC7.

and has an on-chip pullup resistor. the current transfer is to be received. TIN2 — Dual timer module channel 2 input. CMP1_OUT — Analog co mparator 1 output. After reset, the default state is TDI. ANB10 — Analog input to channel 10 of ADCB. T0 — Dual timer module channel 0 input/output. CMP2_OUT — Analog co mparator 2 output. After reset, the default state is TDO. Schmitt-trigger input is used for noise immunity. positive input 2 of analog comparator 1. CMP2_OUT — Analog co mparator 2 output. After reset, the default state is TCK.

edge of TCK and has an on-chip pullup resistor. ANB11 — Analog input to channel 11 of ADCB. T1 — Dual timer module channel 1 input/output. CMP1_OUT — Analog co mparator 2 output. After reset, the default state is TMS. Always tie the TMS pin to VDD through a 2.2 k resistor.

5 Input/

After reset, the default state is GPIOE0.

6 Input/

positive input 1 of analog comparator 0. After reset, the default state is GPIOE1.

8 Input/

negative input 1 of analog comparator 0. After reset, the default state is GPIOE2.

14 Input/

negative input 1 of analog comparator 2. After reset, the default state is GPIOE3.

18 Input/

positive input 2 of analog comparator 2. After reset, the default state is GPIOE4.

16 Input/

positive input 1 of analog comparator 2. After reset, the default state is GPIOE5. After reset, the default state is GPIOE6.

34 Input/

After reset, the default state is GPIOE7. After reset, the default state is GPIOF0.

40 Input/

41 Input/

After reset, the default state is GPIOF2.

42 Input/

After reset, the default state is GPIOF3.

5 Memory Maps

5.1 Introduction

• Program address space, including the interrupt vector table
• Data address space, including the EOnC E memory and peripheral memory maps On-chip memory sizes for the device are summarized in Table 6. Flash memories’ restrictions are identified in the “Use Restrictions” column of Table 6.

5.2 Program Map

read and written to program memory space through primary data memory buses: CDBW for data write and CDBR for data read. tables can be stored and accessed in program memory. The program memory map is shown in Table 7 and Table 8. Table 6. Chip Memory Configurations Table 7. Program Memory Map1 for 56F8006 at Reset 1 All addresses are 16-bit word addresses. 2 This RAM is shared with data space starting at address X: 0x00 0000; see Figure 8.

5.3 Data Map

in parallel on the XDB2 bus. direct address mode is supported for accessing a first 64-location in data memory by using a single word instruction. The data memory map is shown in Table 9. Table 8. Program Memory Map1 for 56F8002 at Reset (continued) 1 All addresses are 16-bit word addresses. 2 This RAM is shared with data space starting at address X: 0x00 0000; see Figure 9. Table 9. Data Memory Map1 1 All addresses are 16-bit word addresses.

2 KB2

Figure 8. 56F8006 Dual Port RAM Map Figure 9. 56F8002 Dual Port RAM Map

5.4 Interrupt Vector Table and Reset Vector

Manual for detail. The reset startup addresses of 56F8002 and 56F8006 are different.

• 56F8006 startup address is located at 0x00 0000. The reset va lue of VBA is reset to a value of 0x0000 that corresponds to address 0x00 0000
• 56F8002 startup address is located at 0x00 0800. The reset va lue of VBA is reset to a value of 0x0010 that corresponds to address 0x00 0800 By default, the chip reset address and COP reset address correspond to vector 0 and 1 of the interrupt vector table. In these instances, the first two locations in the vector table must contain branch or JMP instructions. All other entries must contain JSR instructions. The highest number vector, a user assignable vector USER6 (vector 50), can be defined as a fast interrupt if the instruction located in this vector location is not a JSR or BSR instruction. Please see section 9.3.3.3 of DSP56800E 16-Bit Core Reference Manual for detail. Reserved RAM Reserved Reserved EOnCE Peripherals Reserved RAM Dual Port RAM Program Data Flash 0x00 0000 0x00 0400 0x00 F000 0x01 0000 0xFF FF00 0x00 0000 0x00 2000 0x00 8000 0x00 8400 Reserved RAM Reserved Reserved EOnCE Peripherals Reserved RAM Dual Port RAM Program Data Flash 0x00 0000 0x00 0400 0x00 F000 0x01 0000 0xFF FF00 0x00 0000 0x00 0800 0x00 8000 0x00 8400 Reserved 0x00 2000

Table 43 provides the 56F8006/56F8002’s reset and interrupt priority structure, including on-chip peripherals.

5.5 Peripheral Memory-Mapped Registers

written using word accesses only. Table 10. Data Memory Peripheral Base Address Map Summary

5.6 EOnCE Memory Map

Control registers of the EOnCE are located at the top of data memory space. These locations are fixed by the 56F800E core. to access or control the EOnCE. Table 11. EOnCE Memory Map

MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 General System Control Information Freescale Semiconductor34

6 General System Control Information

6.1 Overview

This section discusses power pins, reset sources, interrupt sources, clock sources, the system integration module (SIM), ADC synchronization, and JTAG/EOnCE interfaces.

6.2 Power Pins

VDD, VSS and VDDA, VSSA are the primary power supply pins for the devices. This voltage source supplies power to all on-chip peripherals, I/O buffer circuitry and to internal voltage regulators. Device has multiple internal voltages provide regulated lower-voltage source for the peripherals, core, memory, and on-chip relaxation oscillators. Typically, there are at least two separate capacitors across the power pins to bypass the glitches and provide bulk charge storage. In this case, there should be a bulk electrolytic or tantalum capacitor, such as a 10 F tantalum capacitor, to provide bulk charge storage for the overall system and a 0.1 F ceramic bypass capacitor located as near to the device power pins as practical to suppress high-frequency noise. Each pin must have a bypass capacitor for best noise suppression. VDDA and VSSAare the analog power supply pins for the device. This voltage source supplies power to the ADC, PGA, and CMP modules. A 0.1 F ceramic bypass capacitor should be located as near to the device VDDA and VSSA pins as practical to suppress high-frequency noise. VDDA and VSSA are also the voltage reference high and voltage reference low inputs, respectively, for the ADC module.

6.3 Reset

Resetting the device provides a way to start processing from a known set of initial conditions. During reset, most control and status registers are forced to initial values and the program counter is loaded from the reset vector. On-chip peripheral modules are disabled and I/O pins are initially configured as the reset status shown in Table 5. The 56F8006/56F8002 has the following sources for reset:

• Power-on reset (POR)
• Partial power down reset (PPD)
• Low-voltage detect (LVD)
• External pin reset (EXTR)
• Computer operating properly loss of reference reset (COP_LOR)
• Computer operating properly time-out reset (COP_CPU)
• Software Reset (SWR) Each of these sources has an associated bit in the reset status register (RSTAT) in the system integration module (SIM). The external pin reset function is shared with an GPIO port A7 on the RESET /GPIOA7 pin. The reset function is enabled following any reset of the device. Bit 7 of GPIOA_PER register must be cleared to use this pin as an GPIO port pin. When enabled as the RESET pin, an internal pullup device is automatically enabled.

6.4 On-chip Clock Synthesis

The on-chip clock synthesis (OCCS) module allows designers using an internal relaxation oscillator, an external crystal, or an external clock to run 56F8000 family devices at user-selectable frequencies up to 32 MHz. The features of OCCS module include:

• Ability to power down the internal relaxation oscillator or crystal oscillator
• Ability to put the internal relaxation oscillator into standby mode
• Ability to power down the PLL

• Provides a 3X system clock that operates at three ti mes the system clock to PWM, timer, and SCI modules
• Safety shutdown feature is available if the PLL reference clock is lost
• Can be driven from an external clock source The clock generation module provides the programming interface for the PLL, internal relaxation oscillator, and crystal oscillator. It also provides a postscaler to divide clock frequency down by 1, 2, 4, 8, 16, 32, 64, 128, 256 before feeding to the SIM. The SIM is responsible for further dividing these frequencies by two, which ensures a 50% duty cycle in the system clock output. For detail, see the OCCS chapter in the MC56F8006 Peripheral Reference Manual.

6.4.1 Internal Clock Source

power, the internal relaxation oscillator supports a run state (8 MHz), standby state (400 kHz), and a power-down state. During a boot or reset sequence, the relaxation oscillator is enabled by default (the PRECS bit in the PLLCR word is set to 0). until the desired external clock source is enabled and stable. frequency accuracy is achieved.

6.4.2 Crystal Oscillator/Ceramic Resonator

Figure 12. Follow the crystal supplier’s recommendations when selecting a crystal, because crystal parameters determine the (Cx, Cy) and feedback resistor (RF) are required. In addition, a series resistor (RS) may be used in high-gain modes. Recommended component values are listed in Table 28.

Figure 10. Typical Crystal Oscillator Circuit: Low-Range, Low-Power Mode Figure 11. Typical Crystal or Ceramic Resonator Circuit: High-Range, Low-Power Mode Figure 12. Typical Crystal or Ceramic Resonator Circuit: Low Range and High Range, High-Gain Mode

6.4.3 External Clock Input — Crystal Oscillator Option

clock input must be generated using a relatively low impedance driver with maximum frequency less than 8 MHz.

Figure 13. Connecting an External Clock Signal Using XTAL

6.4.4 Alternate External Clock Input

GPIOB_PER register GPIO module and GPSB1 register in the system integration module (SIM) are set to the correct values. Figure 14. Connecting an External Clock Signal Using GPIO

6.5 Interrupt Controller

to the 56800E core when an interrupt of sufficient priority exists and what address to jump to to service this interrupt.

6.6 System Integration Module (SIM)

the MC56F8006 Peripheral Reference Manual.

• Chip reset sequencing
• Core and peripheral clock control and distribution
• Stop/wait mode control
• System status control EXTALXTAL 56F8006/56F8002 External Clock (<50 MHz) GND or GPIO CLK_MOD = 1 56F8002/56F8006 GPIOB6/RXD/SDA/ANA13 and CMP0_P2/CLKIN External Clock ( 64 MHz) EXT_SEL = 1; GPIO_B_PER[6] = 0; GPS_B6 = 11

• Registers containing the JTAG ID of the chip
• Controls for programmable pe ripheral and GPIO connections
• Peripheral clocks for TMR and PWM and SCI with a high-speed (3X) option
• Power-saving clock gating for peripherals
• Controls the enable/disable functions of large regu lator standby mode with write protection capability
• Permits selected peripherals to run in stop mode to generate stop recovery interrupts
• Controls for programmable pe ripheral and GPIO connections
• Software chip reset
• I/O short address base location control
• Peripheral protection control to provide runaway code protection for safety-critical applications
• Controls output of internal clock sources to CLKO pin
• Four general-purpose software control registers are reset only at power-on
• Peripherals stop mode clocking control

6.7 PWM, PDB, PGA, and ADC Connections

The comparators, timers, and PWM_reload_sync output can be connected to the programmable delay block (PDB) trigger input. Peripheral Reference Manual for additional information. Figure 15. Synchronization of ADC, PDB

MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 39 Each ADC contains a temperature sensor. Outputs of temperature sensors, PGAs, on-chip regulators and VDDA are internally routed to ADC inputs.

• Internal PGA0 output available on ANA15
• Internal PGA0 positive input calibration voltage available on ANA16
• Internal PGA0 negative input calibration voltage available on ANA17
• Internal PGA1 output available on ANB15
• Internal PGA1 positive input calibration voltage available on ANB16
• Internal PGA1 negative input calibration voltage available on ANB17
• ADCA temperature sens or available on ANA26
• ADCB temperature sensor available on ANB26
• Output of on-chip digital voltage regulator is routed to ANA24
• Output of on-chip analog voltage regulator is routed to ANA25
• Output of on-chip small voltage regu lator for ROSC is routed to ANB24
• Output of on-chip small voltage regulator for PLL is routed to ANB25
• VDDA is routed to ANA27 and ANB27

6.8 Joint Test Action Group (JTA G)/Enhanced On-Chip Emulator

(EOnCE) The DSP56800E Family includes extensive integrated support for application software development and real-time debugging. Two modules, the Enhanced On-Chip Emulation module (EOnCE) and the core test access port (TAP, commonly called the JTAG port), work together to provide these capabilities. Both are accessed through a common 4-pin JTAG/EOnCE interface. These modules allow you to insert the 56F8006/56F8002 into a target system while retaining debug control. This capability is especially important for devices without an external bus, because it eliminates the need for a costly cable to bring out the footprint of the chip, as is required by a traditional emulator system. The DSP56800E EOnCE module is a Freescale-designed module used to develop and debug application software used with the chip. This module allows non-intrusive interaction with the CPU and is accessible through the pins of the JTAG interface or by software program control of the DSP56800E core. Among the many features of the EOnCE module is the support for data communication between the controller and the host software development and debug systems in real-time program execution. Other features allow for hardware breakpoints, the monitoring and tracking of program execution, and the ability to examine and modify the contents of registers, memory, and on-chip peripherals, all in a special debug environment. No user-accessible resources need to be sacrificed to perform debugging operations. The DSP56800E JTAG port is used to provide an interface for the EOnCE module to the DSP JTAG pins. Joint Test Action Group (JTAG) boundary scan is an IEEE 1149.1 standard methodology enabling access to test features using a test access port (TAP). A JTAG boundary scan consists of a TAP controller and boundary scan registers. Please contact your Freescale sales representative or authorized distributor for device-specific BSDL information. NOTE In normal operation, an external pullup on the TMS pin is highly recommend to place the JTAG state machine in reset state if this pin is not configured as GPIO.

7 Security Features

The 56F8006/56F8002 offers security features intended to prevent unauthorized users from reading the contents of the flash memory (FM) array. The 56F8006/56F8002’s flash security consists of several hardware interlocks that prevent unauthorized users from gaining access to the flash array. After flash security is set, an authorized user can be enabled to access on-chip memory if a user-defined software subroutine, which reads and transfers the contents of internal memory via peripherals, is included in the application software. This

MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Security Features Freescale Semiconductor40 application software could communicate over a serial port, for example, to validate the authenticity of the requested access, then grant it until the next device reset. The inclusion of such a back door technique is at the discretion of the system designer.

7.1 Operation with Security Enabled

After you have programmed flash with the application code, or as part of the programming of the flash with the application code, the 56F8006/56F8002 can be secured by programming the security word, 0x0002, into program memory location 0x00 1FF7. This can also be effected by use of the CodeWarrior IDE menu flash lock command. This nonvolatile word keeps the device secured after reset, caused, for example, by a power-down of the device. Refer to the flash memory chapter in the MC56F8006 Peripheral Reference Manual for detail. When flash security mode is enabled, the 56F8006/56F8002 disables the core EOnCE debug capabilities. Normal program execution is otherwise unaffected.

7.2 Flash Access Lock and Unlock Mechanisms

There are several methods that effectively lock or unlock the on-chip flash.

7.2.1 Disabling EOnCE Access

On-chip flash can be read by issuing commands across the EOnCE port, which is the debug interface for the 56800E CPU. The TCK, TMS, TDO, and TDI pins comprise a JTAG interface onto which the EOnCE port functionality is mapped. When the device boots, the chip-level JTAG TAP (test access port) is active and provides the chip’s boundary scan capability and access to the ID register, but proper implementation of flash security blocks any attempt to access the internal flash memory via the EOnCE port when security is enabled. This protection is effective when the device comes out of reset, even prior to the execution of any code at startup.

7.2.2 Flash Lockout Recovery Using JTAG

If the device is secured, one lockout recovery mechanism is the complete erasure of the internal flash contents, including the configuration field, thus disabling security (the protection register is cleared). This does not compromise security, as the entire contents of your secured code stored in flash are erased before security is disabled on the device on the next reset or power-up sequence. To start the lockout recovery sequence via JTAG , the JTAG public instruction (LOCKOUT_RECOVERY) must first be shifted into the chip-level TAP controller’s instruction register. After the LOCKOUT_RECOVERY instruction has been shifted into the instruction register, the clock divider value must be shifted into the corresponding 7-bit data register. After the data register has been updated, you must transition the TAP controller into the RUN-TEST/IDLE state for the lockout sequence to commence. The controller must remain in this state until the erase sequence is complete. Refer to the MC56F8006 Peripheral Reference Manual for detail, or contact Freescale. NOTE After the lockout recovery sequence has completed, you must reset the JTAG TAP controller and device to return to normal unsecured operation. Power-on reset resets both too.

7.2.3 Flash Lockout Recovery Using CodeWarrior

CodeWarrior can unlock a device by selecting the Debug menu, then selecting DSP56800E, followed by Unlock Flash. Another mechanism is also built into CodeWarrior using the device’s memory configuration file. The command “Unlock_Flash_on_Connect 1” in the .cfg file accomplishes the same task as using the Debug menu. This lockout recovery mechanism is the complete erasure of the internal flash contents, including the configuration field, thus disabling security (the protection register is cleared).

MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 41

7.2.4 Flash Lockout Reco very without Mass Erase

7.2.4.1 Without Presenting Back Do or Access Keys to the Flash Unit

A user can un-secure a secured device by programming the word 0x0000 into program flash location 0x00 1FF7. After completing the programming, the JTAG TAP controller and the device must be reset to return to normal unsecured operation. You are responsible for directing the device to invoke the flash programming subroutine to reprogram the word 0x0000 into program flash location 0x00 1FF7. This is done by, for example, toggling a specific pin or downloading a user-defined key through serial interfaces. NOTE Flash contents can be programmed only from 1s to 0s.

7.2.4.2 Presenting Back Door Ac cess Key to the Flash Unit

It is possible to temporarily bypass the security through a back door access scheme, using a 4-word key, to temporarily unlock of the flash. A back door access requires support from the embedded software. This software would typically permit an external user to enter a four word code through one of the communications interfaces and then use it to attempt the unlock sequence. If your input matches the four word code stored at location 0x00 1FFC–0x00 1FFF in the flash memory, the part immediately becomes unsecured (at runtime) and you can access internal memory via JTAG/EOnCE port. Refer to the MC56F8006 Peripheral Reference Manual for detail. The key must be entered in four consecutive accesses to the flash, so this routine should be designed to run in RAM.

7.3 Product Analysis

The recommended method of unsecuring a secured device for product analysis of field failures is via the method described in Section 7.2.4.2, “Presenting Back Door Access Key to the Flash Unit.” The customer would need to supply technical support with the details of the protocol to access the subroutines in flash memory. An alternative method for performing analysis on a secured device would be to mass-erase and reprogram the flash with the original code, but modify the security word or not program the security word.

8 Specifications

8.1 General Characteristics

The 56F8006/56F8002 is fabricated in high-density low power and low leakage CMOS with a maximum voltage of 3.6 V digital inputs during normal operation without causing damage. Absolute maximum ratings in Table 12 are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent damage to the device. Unless otherwise stated, all specifications within this chapter apply over the temperature range of –40ºC to 105ºC ambient temperature over the following supply ranges: VSS =V SSA =0 V ,VDD =V DDA = 3.0–3.6 V , CL <50 pF, fOP = 32 MHz CAUTION This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level.

8.2 Absolute Maximum Ratings

conditions, refer to the remaining tables in this section. programmable pullup resistor associated with the pin is enabled.

8.2.1 ESD Protection and Latch-Up Immunity

can withstand exposure to reasonable levels of static without suffering any permanent damage. Table 12. Absolute Maximum Ratings resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two resistance values. 2 All functional non-supply pins are internally clamped to VSS and VDD. clock rate is low (which would reduce overall power consumption).

temperature, unless specified otherwise in the device specification.

8.3 Thermal Characteristics

unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small. Table 13. ESD and Latch-up Test Conditions Table 14. 56F8006/56F8002 ESD Protection

1 Parameter is achieved by design characterization on a small sample size from typical devices un-

der typical conditions unless otherwise noted. Table 15. 28SOIC Package Thermal Characteristics

Table 16. 32LQFP Package Thermal Characteristics Table 17. 32PSDIP Package Thermal Characteristics Table 15. 28SOIC Package Thermal Characteristics (continued)

Junction-to-ambient thermal resistance determined per JEDEC JESD51–3 and JESD51–6. Thermal test board meets JEDEC specification for this package. board meets JEDEC specification for the specified package. Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. thermal resistance of the interface layer. dissipation of other components on the board, and board thermal resistance.

8.4 Recommended Oper ating Conditions

This section includes information about recommended operating conditions. Table 18. 48LQFP Package Thermal Characteristics

8.5 DC Electrical Characteristics

This section includes information about power supply requirements and I/O pin characteristics. Table 19. Recommended Operating Conditions 1 Total chip source or sink current cannot exceed 75 mA. Table 20. Default Mode

Table 21. DC Characteristics

frequency < 16 MHz, VDD can be 1.7 V to 3.6 V. 3 All functional non-supply pins are internally clamped to VSS and VDD. resistance values for positive and negative clamp voltages, then use the larger of the two values. in external power supply going out of regulation. Ensure external VDD load shunts current greater than maximum injection current. (which would reduce overall power consumption). 6 Maximum is highest voltage that POR is guaranteed. a temperature range from –40 C to 125 C. Please see the PMC chapter in the reference manual for details. Table 21. DC Characteristics (continued)

8.6 Supply Current Characteristics

Table 22. Supply Current Consumption

1 IDDA IDD

1 IDDA

processor core in stop state. processor core in stop state. processor core in stop state. processor core in stop state. 1 No output switching; all ports configured as inputs; all inputs low; no DC loads. 2 Low speed mode: LPR (lower voltage regulator control bit) = 0 and voltage regulator is in full regulation. Characterization only. 3 Low power mode: LPR (lower voltage regulator control bit) = 1; the voltage regulator is put into standby. down mode the next time that the STOP command is executed. Table 22. Supply Current Consumption (continued)

8.7 Flash Memory Characteristics

8.8 External Clock Operation Timing

Figure 21. External Clock Timing Table 23. Flash Timing Parameters 2 Specifies page erase time. There are 512 bytes per page in the program flash memory. Table 24. External Clock Operation Timing Requirements1 1 Parameters listed are guaranteed by design. 2 See Figure 21 for detail on using the recommended connection of an external clock driver. 3 The chip may not function if the high or low pulse width is smaller than 6.25 ns. 4 External clock input rise time is measured from 10% to 90%. 5 External clock input fall time is measured from 90% to 10%. Note: The midpoint is VIL + (VIH – VIL)/2.

8.9 Phase Locked Loop Timing

8.10 Relaxation Oscillator Timing

Table 25. Phase Locked Loop Timing PLL is optimized for 8 MHz input. 2 The core system clock operates at 1/6 of the PLL output frequency. 3 This is the time required after the PLL is enabled to ensure reliable operation. 4 From powerdown to powerup state at 32 MHz system clock state. frequency and using an 8 MHz oscillator frequency. Table 26. Relaxation Oscillator Timing 1 Output frequency after factory trim. 2 This is the time required from standby to normal mode transition. 3 JA is required to meet QSCI requirements. over the whole temperature and whole voltage range from 1.8 V to 2.6 V will be +/-16%. 5 This data is only applied to devices with temperature range from –40 C to 105 C.

8.11 Reset, Stop, Wait, Mode Select, and Interrupt Timing

All address and data buses described here are internal. Figure 24. GPIO Interrupt Timing (Negative Edge-Sensitive)

8.12 External Oscillator (XOSC) Characteristics

Reference Figure 10, and Figure 11, and Figure 12 for crystal or resonator circuits. Table 27. Reset, Stop, Wait, Mode Select, and Interrupt Timing 1,2 1 In the formulas, T = system clock cycle and Tosc = oscillator clock cycle. For an operating frequency of 32 MHz, T = 31.25 ns. At 4 MHz (used coming out of reset and stop modes), T = 250 ns. 2 Parameters listed are guaranteed by design.

8.13 AC Electrical Characteristics

from the 50% to the 50% point, and rise and fall times are measured between the 10% and 90% points, as shown in Figure 25. Figure 25. Input Signal Measurement References

• Active state, when a bus or signal is driven, and enters a low impedance state

Table 28. Crystal Oscillator Characteristics 1 Data in Typical column was characterized at 3.0 V, 25C or is typical recommended value. 3 See crystal or resonator manufacturer’s recommendation.

4 MHz

1 MHz

4 Proper PC board layout procedures must be followed to achieve specifications. The midpoint is VIL + (VIH – VIL)/2.

• Tri-stated, when a bu s or signal is placed in a high impedance state
• Data Valid state, when a signal level has reached VOL or VOH
• Data Invalid state, when a signal level is in transition between VOL and VOH

Figure 26. Signal States

8.13.1 Serial Peripheral Interface (SPI) Timing

Table 29. SPI Timing1

Figure 30. SPI Slave Timing (CPHA = 1)

8.13.2 Serial Communication Interface (SCI) Timing

Table 30. SCI Timing1 1 Parameters listed are guaranteed by design.

Figure 31. RXD Pulse Width Figure 32. TXD Pulse Width

8.13.3 Inter-Integrated Circuit Interface (I 2C) Timing

Table 31. I2C Timing Hold time (repeated) START condition. After this period, the first clock pulse is generated. acknowledge this address byte, a negative hold time can result, depending on the edge rates of the SDA and SCL lines. 2 The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.

Figure 33. Timing Definition for Standard Mode Devices on the I2C Bus

8.13.4 JTAG Timing

Figure 34. Test Clock Input Timing Diagram Table 32. JTAG Timing 1 TCK frequency of operation must be less than 1/8 the processor rate.

Figure 35. Test Access Port Timing Diagram

8.13.5 Dual Timer Timing

Figure 36. Timer Timing Table 33. Timer Timing1, 2 1 In the formulas listed, T = the clock cycle. For 32 MHz operation, T = 31.25ns.

1. Parameters listed are guaranteed by design.

8.14 COP Specifications

8.15 PGA Specifications

Table 34. COP Specifications Table 35. PGA Specifications

8.16 ADC Specifications

Figure 37. ADC Input Impedance Equivalency Diagram Table 36. ADC Operating Conditions reference only and are not tested in production.

2 VREFL = VSSA

3 VREFH = VDDA

Table 37. ADC Characteristics (VREFH = VDDA, VREFL = VSSA)

8.17 HSCMP Specifications

8.18 Optimize Power Consumption

provides additional detail that can be used to optimize power consumption for a given application. reference only and are not tested in production.

3 Monotonicity and no-missing-codes guaranteed in 10-bit and 8-bit modes

4 Based on input pad leakage current. Refer to pad electricals. Table 38. HSCMP Specifications VLVI_WARNING => LVI_WARNING NOT ASSERTED. VLVI_WARNING => LVI_WARNING ASSERTED. VLVI_WARNING => LVI_WARNING NOT ASSERTED. VLVI_WARNING => LVI_WARNING ASSERTED.

references. These sources operate independently of processor state or operating frequency. resources are in use. These include RAM, flash memory, and the ADCs. reveal that the power-versus-load curve does have a non-zero Y-intercept. outputs change. Table 39 provides coefficients for calculating power dissipated in the I/O cells as a function of capacitive load.

• Summation is performed over all output pins with capacitive loads
• Total power is expressed in mW load is expressed in pF Because of the low duty cycle on most device pins, power dissipation due to capacitive loads was found to be fairly low when averaged over a period of time. E, the external [static component], reflects the effects of placing resistive loads on the outputs of the device. Sum the total of all V2/R or IV to arrive at the resistive load contribution to power. Assume V = 0.5 for the purposes of these rough calculations. For instance, if there is a total of eight PWM outputs driving 10 mA into LEDs, then P = 8*0.5*0.01 = 40 mW. In previous discussions, power consumption due to parasitics associated with pure input pins is ignored, as it is assumed to be negligible. Total power = A: internal [static component] +B: internal [state-dependent component] +C: internal [dynamic component] +D: external [dynamic component] +E: external [static component]

Table 39. I/O Loading Coefficients at 10 MHz

MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Design Considerations Freescale Semiconductor70

9 Design Considerations

9.1 Thermal Design Considerations

An estimation of the chip junction temperature, TJ, can be obtained from the equation: TJ = TA + (RJ x PD) Eqn. 3 where: The junction-to-ambient thermal resistance is an industry-standard value that provides a quick and easy estimation of thermal performance. Unfortunately, there are two values in common usage: the value determined on a single-layer board and the value obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which value is closer to the application depends on the power dissipated by other components on the board. The value obtained on a single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low-power dissipation and the components are well separated. When a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: R JA = RJC + RCA Eqn. 4 where: RJC is device related and cannot be adjusted. You control the thermal environment to change the case to ambient thermal resistance, RCA. For instance, you can change the size of the heat sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. To determine the junction temperature of the device in the application when heat sinks are not used, the thermal characterization parameter (JT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation: TJ = TT + (JT x PD) Eqn. 5 where: The thermal characterization parameter is measured per JESD51–2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the TA = Ambient temperature for the package ( oC) RJ = Junction-to-ambient thermal resistance ( oC/W) PD = Power dissipation in the package (W) RJA = Package junction-to-ambient thermal resistance (°C/W) RJC = Package junction-to-case thermal resistance (°C/W) RCA = Package case-to-ambient thermal resistance (°C/W) TT = Thermocouple temperature on top of package ( oC) JT = Thermal characterization parameter ( oC/W) PD = Power dissipation in package (W)

MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 71 junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. When heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface between the case of the package and the interface material. A clearance slot or hole is normally required in the heat sink. Minimizing the size of the clearance is important to minimize the change in thermal performance caused by removing part of the thermal interface to the heat sink. Because of the experimental difficulties with this technique, many engineers measure the heat sink temperature and then back-calculate the case temperature using a separate measurement of the thermal resistance of the interface. From this case temperature, the junction temperature is determined from the junction-to-case thermal resistance.

9.2 Electrical Design Considerations

This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, take normal precautions to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. Use the following list of considerations to assure correct operation of the 56F8006/56F8002:

• Provide a low-impedance path from the board power supply to each VDD pin on the 56F8006/56F8002 and from the board ground to each VSS (GND) pin.
• The minimum bypass requirement is to place 0.01–0.1µF capaci tors positioned as near as possible to the package supply pins. The recommended bypass configuration is to place one bypass capacitor on each of the VDD/VSS pairs, including VDDA/VSSA. Ceramic and tantalum capacitors tend to provide better tolerances.
• Ensure that capacitor leads and associated prin ted circuit traces that connect to the chip VDD and VSS (GND) pins are as short as possible.
• Bypass the V DD and VSS with approximately 100 µF, plus the number of 0.1 µF ceramic capacitors.
• PCB trace lengths should be minimal for high-frequency signals.
• Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VDD and VSS circuits.
• Take special care to minimize noise levels on the V REF, VDDA, and VSSA pins.
• Using separate power planes for V DD and VDDA and separate ground planes for VSS and VSSA are recommended. Connect the separate analog and digital power and ground planes as near as possible to power supply outputs. If an analog circuit and digital circuit are powered by the same power supply, you should connect a small inductor or ferrite bead in serial with V DDA and VSSA traces.
• Physically separate analog components from noisy digital components by ground planes. Do not place an analog trace in parallel with digital traces. Place an analog ground trace around an analog signal trace to isolate it from digital traces.
• Because the flash memory is programmed thr ough the JTAG/EOnCE port, SPI, SCI, or I2C, the designer should provide an interface to this port if in-circuit flash programming is desired.
• If desired, connect an external RC circuit to the RESET pin. The resistor value should be in the range of 4.7 k–10 k; the capacitor value should be in the range of 0.22 µF–4.7 µF.
• Configuring the RESET pin to GPIO output in normal operation in a high-noise environment may help to improve the performance of noise transient immunity.
• Add a 2.2 k  external pullup on the TMS pin of the JTAG port to keep EOnCE in a restate during normal operation if JTAG converter is not present.
• During reset and after reset but before I/O initialization, all I/O pins are at input state with internal pullup enabled. The typical value of internal pullup is around 33 k. These internal pullups can be disabled by software.
• To eliminate PCB trace impedance effect, each ADC input should have a no less than 33 pF 10  RC filter.
• External clamp diodes on analog input pins are recommended.

9.3 Ordering Information

distributor to determine availability and to order devices. Table 40. 56F8006/56F8002 Ordering Information 1 This package is RoHS compliant.

Package Mechanical Outline Drawings MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 73 10.1 28-pin SOIC Package

MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Package Mechanical Outline Drawings Freescale Semiconductor74

Figure 38. 56F8006/56F8002 28-Pin SOIC Mechanical Information

MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Package Mechanical Outline Drawings Freescale Semiconductor76 10.2 32-pin LQFP

Package Mechanical Outline Drawings MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 77

Figure 39. 56F8006/56F8002 32-Pin LQFP Mechanical Information

Package Mechanical Outline Drawings MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 79 10.3 48-pin LQFP

Figure 40. 56F8006/56F8002 48-Pin LQFP Mechanical Information

Package Mechanical Outline Drawings MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 81 10.4 32-Pin PSDIP

Figure 41. 56F8006/56F8002 32-Pin PSDIP Mechanical Information

Revision History

MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4 Freescale Semiconductor 83 Table 41 lists major changes between versions of the MC56F8006 document. Appendix A Interrupt Vector Table Table 43 provides the 56F8006/56F8002’s reset and interrupt priority structure, including on-chip peripherals. The table is organized with higher-priority vectors at the top and lower-priority interrupts lower in the table. As indicated, the priority of an interrupt can be assigned to different levels, allowing some control over interrupt priorities. All level 3 interrupts are serviced before level 2 and so on. For a selected priority level, the lowest vector number has the highest priority. The location of the vector table is determined by the vector base address (VBA). Please see the MC56F8006 Peripheral Reference Manual for detail. By default, the chip reset address and COP reset address correspond to vector 0 and 1 of the interrupt vector table. In these instances, the first two locations in the vector table must contain branch or JMP instructions. All other entries must contain JSR instructions. Table 41. Changes Between Revisions 2 and 3 Table 42. Changes Between Revisions 3 and 4

Table 43. Interrupt Vector Table Contents1

the vector table, providing only 19 bits of address. reset address would match the base of this vector table. 3 USER6 vector can be defined as a fast interrupt if the instruction located in this vector location is not a JSR or BSR instruction. Please see section 9.3.3.3 of DSP56800E 16-Bit Core Reference Manual for detail. Table 43. Interrupt Vector Table Contents1 (continued)

GPIOA_PUR is the same as GPIO_A_PUR). Table 44. Detailed Peripheral Memory Map

Table 44. Detailed Peripheral Memory Map (continued)

41 FFFF COP COP_

42 FFFF COP COP_

49 F000 SIM SIM_ISAL ADDR_15_6 0 0 0 0 0 0

03 FFFF PDB PDB_MOD MOD

04 FFFF PDB PDB_

0 AEIE

10 FFFF 6 HFM FM_PROT PROTECT

1 The binary reset value of this register is 0000 0000 0UUU UUUU, where U represents an undefined value. Spaces have been added to the value for clarity. 2 The binary reset value of this register is 0000 0000 111NC NC NC NC NC. Spaces have been added to the value for clarity. indicates that the reset state is determined by the security state of the module. Spaces have been added to the value for clarity. 4 The reset state is loaded from the flash array during reset. 5 The reset state is loaded from the flash array during reset. 6 The reset state is loaded from the flash array during reset.

Document Number: MC56F8006 Rev. 4 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516

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