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PC3S12G128F0CLCR

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MC9S12G Family Reference Manual

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freescale.com MC9S12G Family Reference Manual MC9S12GRMV1 Rev.1.10 February 10, 2012

MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 2 To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ A full list of family members and options is included in the appendices.

MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 3 The following revision history table summarizes changes contained in this document. This document contains information for all constituent modules, with the exception of the CPU. For CPU information please refer to CPU12-1 in the CPU12 & CPU12X Reference Manual

Revision History

Apr, 2011 1.00 • Public relasease for the launch of the S12G96 and the S12G128 May, 2011 1.01

Updated Chapter 1, “Device Overview MC9S12G-Family” (Reason: Typos and formatting)
Updated Appendix A, “Electrical Characteristics” (Reason: Updated electricals) Jun, 2011 1.02 • Updated Appendix A, “Electrical Characteristics” (Reason: Updated electricals) Jun, 2011 1.03 • Updated Appendix A, “Electrical Characteristics” (Reason: Updated electricals) Jul, 2011 1.04 • Updated Appendix A, “Electrical Characteristics” (Reason: Updated electricals) Jul, 2011 1.05 • Updated Appendix A, “Electrical Characteristics” (Reason: Updated electricals) Nov, 2011 1.06
Updated Chapter 2, “Port Integration Module (S12GPIMV0)” (Reason: Updated spec)
Updated Appendix A, “Electrical Characteristics” (Reason: Updated electricals) Jan, 2012 1.07
Updated Chapter 1, “Device Overview MC9S12G-Family” (Reason: Typos and formatting)
Updated Chapter 2, “Port Integration Module (S12GPIMV1)” (Reason: Updated spec)
Updated Chapter 3, “5V Analog Comparator (ACMPV1)” (Reason: Typos and formatting)
Updated Chapter 4, “Reference Voltage Attenuator (RVAV1)” (Reason: Typos and formatting)
Updated Appendix A, “Electrical Characteristics” (Reason: Updated electricals)Added Appendix E, “Notes on the S12GS32” Feb, 2012 1.08 • Updated Appendix A, “Electrical Characteristics” (Reason: Updated electricals) Feb, 2012 1.09 • Updated Appendix A, “Electrical Characteristics” (Reason: Fixed typos) Feb, 2012 1.10 • Updated Chapter 1, “Device Overview MC9S12G-Family” (Reason: Updated mask set numbers and part IDs)

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MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 5

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MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 7 Chapter 1 Device Overview MC9S12G-Family

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Port Integration Module (S12GPIMV1)

MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 9 Chapter 3 5V Analog Comparator (ACMPV1) Chapter 4 Reference Voltage Attenuator (RVAV1) Chapter 5 S12G Memory Map Controller (S12GMMCV1)

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Interrupt Module (S12SINTV1) Chapter 7 Background Debug Module (S12SBDMV1)

MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 11 Chapter 8 S12S Debug Module (S12SDBG)

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Security (S12XS9SECV2) Chapter 10 S12 Clock, Reset and Power Management Unit (S12CPMU)

MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 13 Chapter 11 Analog-to-Digital Converter (ADC10B8CV2) Chapter 12 Analog-to-Digital Converter (ADC10B12CV2) Chapter 13 Analog-to-Digital Converter (ADC10B16CV2)

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Analog-to-Digital Converter (ADC12B16CV2) Chapter 15 Digital Analog Converter (DAC_8B5V)

MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 15 Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3) Chapter 17 Pulse-Width Modulator (S12PWM8B8CV2)

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Serial Communication Interface (S12SCIV5) Chapter 19 Serial Peripheral Interface (S12SPIV5)

MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 17 19.2.3 Chapter 20 Timer Module (TIM16B8CV3)

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16 KByte Flash Module (S12FTMRG16K1V1)

32 KByte Flash Module (S12FTMRG32K1V1)

MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 19 Chapter 23

48 KByte Flash Module (S12FTMRG48K1V1)

64 KByte Flash Module (S12FTMRG64K1V1)

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96 KByte Flash Module (S12FTMRG96K1V1)

MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 21 Chapter 26

128 KByte Flash Module (S12FTMRG128K1V1)

192 KByte Flash Module (S12FTMRG192K2V1)

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240 KByte Flash Module (S12FTMRG240K2V1)

Electrical Characteristics

MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 23 Appendix B Detailed Register Address Map Appendix C

Ordering Information

Package Information

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MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 25 Chapter 1 Device Overview MC9S12G-Family

1.1 Introduction

The MC9S12G-Family is an optimized, automotive, 16-bit microcontroller product line focused on low-cost, high-performance, and low pin-count. This family is intended to bridge between high-end 8-bit microcontrollers and high-performance 16-bit microcontrollers, such as the MC9S12XS-Family. The MC9S12G-Family is targeted at generic automotive applications requiring CAN or LIN/J2602 communication. Typical examples of these applications include body controllers, occupant detection, door modules, seat controllers, RKE receivers, smart actuators, lighting modules, and smart junction boxes. Version Number Revision Date Description of Changes Rev 0.21 15-Oct-2010 • Corrected Table 1-28

Typos and formatting Rev 0.22 8-Nov-2010 • Reformatted Section 1.8, “Device Pinouts”
Typos and formatting Rev 0.23 3-Jan-2010 • Corrected Figure 1-4
Corrected Figure 1-6
Corrected Figure 1-9
Typos and formatting Rev 0.24 8-Feb-2010 • Added Section 1.14, “Autonomous Clock (ACLK) Conﬁguration”
Corrected Figure 1-12
Corrected Figure 1-10
Corrected Figure 1-13
Corrected Figure 1-11
Typos and formatting Rev 0.25 18-Feb-2011 • Added Section 1.14, “Autonomous Clock (ACLK) Conﬁguration”
Corrected Figure 1-12
Corrected Figure 1-10
Corrected Figure 1-13
Corrected Figure 1-11
Typos and formatting Rev 0.26 21-Feb-2011 • Updated Table 1-1(added temperatur sensor feature)
Updated Section 1.3.14, “Analog-to-Digital Converter Module (ADC)”
Updated Table 1-31
Typos and formatting Rev 0.27 1-Apr-2011 • Typos and formatting Rev 0.28 11-May-2011 • Rev 0.29 10-Jan-2011 • Corrected Figure 1-4 Rev 0.30 10-Feb-2012 • Updated Table 1-5(added mask set 1N75C)
Typos and formatting

Device Overview MC9S12G-Family MC9S12G Family Reference Manual, Rev.1.10

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The MC9S12G-Family uses many of the same features found on the MC9S12XS- and MC9S12P-Family, including error correction code (ECC) on ﬂash memory, a fast analog-to-digital converter (ADC) and a frequency modulated phase locked loop (IPLL) that improves the EMC performance. The MC9S12G-Family is optimized for lower program memory sizes down to 16k. In order to simplify customer use it features an EEPROM with a small 4 bytes erase sector size. The MC9S12G-Family deliver all the advantages and efﬁciencies of a 16-bit MCU while retaining the low cost, power consumption, EMC, and code-size efﬁciency advantages currently enjoyed by users of Freescale’s existing 8-bit and 16-bit MCU families. Like the MC9S12XS-Family, the MC9S12G-Family run 16-bit wide accesses without wait states for all peripherals and memories. The MC9S12G-Family is available in 100-pin LQFP, 64-pin LQFP, 48-pin LQFP/QFN, 32-pin LQFP and 20-pin TSSOP package options and aims to maximize the amount of functionality especially for the lower pin count packages. In addition to the I/O ports available in each module, further I/O ports are available with interrupt capability allowing wake-up from stop or wait modes.

1.2 Features

This section describes the key features of the MC9S12G-Family.

1.2.1 MC9S12G-Family Comparison

Table 1-1 provides a summary of different members of the MC9S12G-Family and their features. This information is intended to provide an understanding of the range of functionality offered by this microcontroller family. Table 1-1. MC9S12G-Family Overview1 Feature S12GN16 S12GN32 S12GN48 S12G48 S12G64 S12G96 S12G128 S12G192 S12GA192 S12G240 S12GA240 CPU CPU12V1 Flash memory [kBytes] 16 32 48 48 64 96 128 192 192 240 240 EEPROM [Bytes] 512 1024 1536 1536 2048 3072 4096 4096 4096 4096 4096 RAM [Bytes] 1024 2048 4096 4096 4096 8192 8192 11264 11264 11264 11264 MSCAN — — — 1 1 1 1 1111 S C I 112 2 2 3 3 3333 S P I 112 2 2 3 3 3333 16-Bit Timer channels 666 6 6 8 8 8888 8-Bit PWM channels 666 6 6 8 8 8888 10-Bit ADC channels 8 8 12 12 12 12 12 16 — 16 — 12-Bit ADC

Device Overview MC9S12G-Family MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 27 Table 1-2shows the maximum number of peripherals or peripheral channels per package type. Not all peripherals are available at the same time. The maximum number of peripherals is also limited by the device chosen as per Table 1-1. Temperature ACMP (analog PLL Y es Y es Y es Y es Y es Y es Y es Y es Y es Y es Y es External osc Y es Y es Y es Y es Y es Y es Y es Y es Y es Y es Y es Internal 1 MHz RC oscillator Ye s Ye s Ye s Ye s Ye s Ye s Ye s Ye s Ye s Ye s Ye s 32-pin LQFP Y es Y es Y es Y es Y es — — ———— 48-pin LQFP Y es Y es Y es Y es Y es Y es Y es Y es Y es Y es Y es 64-pin LQFP — — Y es Y es Y es Y es Y es Y es Y es Y es Y es 100-pin LQFP — — — — — Y es Y es Y es Y es Y es Y es Supply voltage 3.13 V – 5.5 V Execution speed Static – 25 MHz

1 Not all peripherals are available in all package types

Table 1-2. Maximum Peripheral Availability per Package Peripheral 20 TSSOP 32 LQFP 48 LQFP,

48 QNFN 64 LQFP 100 LQFP

MSCAN — Y es Y es Y es Y es SCI0 Y es Y es Y es Y es Y es SCI1 — Y es Y es Y es Y es SCI2 — — Y es Y es Y es SPI0 Y es Y es Y es Y es Y es SPI1 — — Y es Y es Y es SPI2 — — — Y es Y es Timer Channels 4 = 0 … 3 6 = 0 … 5 8 = 0 … 7 8 = 0 … 7 8 = 0 … 7 8-Bit PWM Channels 4 = 0 … 3 6 = 0 … 5 8 = 0 … 7 8 = 0 … 7 8 = 0 … 7 ADC channels 6 = 0 … 5 8 = 0 … 7 12 = 0 … 11 16 = 0 … 15 16 = 0 … 15 Table 1-1. MC9S12G-Family Overview1 Feature S12GN16 S12GN32 S12GN48 S12G48 S12G64 S12G96 S12G128 S12G192 S12GA192 S12G240 S12GA240

Device Overview MC9S12G-Family MC9S12G Family Reference Manual, Rev.1.10

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1.2.2 Chip-Level Features

On-chip modules available within the family include the following features:

S12 CPU core
Up to 240 Kbyte on-chip ﬂash with ECC
Up to 4 Kbyte EEPROM with ECC
Up to 11 Kbyte on-chip SRAM
Phase locked loop (IPLL) frequency multiplier with internal ﬁlter
4–16 MHz amplitude controlled Pierce oscillator
1 MHz internal RC oscillator
Timer module (TIM) supporting up to eight channels that provide a range of 16-bit input capture, output compare, counter, and pulse accumulator functions
Pulse width modulation (PWM) module with up to eight x 8-bit channels
Up to 16-channel, 10 or 12-bit resolution successive approximation analog-to-digital converter (ADC)
Up to two 8-bit digital-to-analog converters (DAC)
Up to one 5V analog comparator (ACMP)
Up to three serial peripheral interface (SPI) modules
Up to three serial communication interface (SCI) modules supporting LIN communications
Up to one multi-scalable controller area network (MSCAN) module (supporting CAN protocol 2.0A/B)
On-chip voltage regulator (VREG) for regulation of input supply and all internal voltages
Autonomous periodic interrupt (API)
Precision ﬁxed voltage reference for ADC conversions
Optional reference voltage attenuator module to increase ADC accuracy

1.3 Module Features

The following sections provide more details of the modules implemented on the MC9S12G-Family family. DAC0 — — Y es Y es Y es DAC1 — — Y es Y es Y es ACMP Y es Y es Y es Y es — Total GPIO 14 26 40 54 86 Table 1-2. Maximum Peripheral Availability per Package Peripheral 20 TSSOP 32 LQFP 48 LQFP,

Device Overview MC9S12G-Family MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 29

1.3.1 S12 16-Bit Central Processor Unit (CPU)

S12 CPU is a high-speed 16-bit processing unit:

Full 16-bit data paths supports efﬁcient arithmetic operation and high-speed math execution
Includes many single-byte instructions. This allows much more efﬁcient use of ROM space.
Extensive set of indexed addressing capabilities, including: — Using the stack pointer as an indexing register in all indexed operations — Using the program counter as an indexing register in all but auto increment/decrement mode — Accumulator offsets using A, B, or D accumulators — Automatic index predecrement, preincrement, postdecrement, and postincrement (by –8 to +8)

1.3.2 On-Chip Flash with ECC

On-chip ﬂash memory on the MC9S12G-Family family features the following:

Up to 240 Kbyte of program ﬂash memory — 32 data bits plus 7 syndrome ECC (error correction code) bits allow single bit error correction and double fault detection — Erase sector size 512 bytes — Automated program and erase algorithm — User margin level setting for reads — Protection scheme to prevent accidental program or erase
Up to 4 Kbyte EEPROM — 16 data bits plus 6 syndrome ECC (error correction code) bits allow single bit error correction and double fault detection — Erase sector size 4 bytes — Automated program and erase algorithm — User margin level setting for reads

1.3.3 On-Chip SRAM

Up to 11 Kbytes of general-purpose RAM

1.3.4 Port Integration Module (PIM)

Data registers and data direction registers for ports A, B, C, D, E, T, S, M, P, J and AD when used as general-purpose I/O
Control registers to enable/disable pull devices and select pullups/pulldowns on ports T, S, M, P, J and AD on per-pin basis
Single control register to enable/disable pull devices on ports A, B, C, D and E, on per-port basis and on BKGD pin
Control registers to enable/disable open-drain (wired-or) mode on ports S and M

Device Overview MC9S12G-Family MC9S12G Family Reference Manual, Rev.1.10

30 Freescale Semiconductor

Interrupt ﬂag register for pin interrupts on ports P, J and AD
Control register to conﬁgure IRQ pin operation
Routing register to support programmable signal redirection in 20 TSSOP only
Routing register to support programmable signal redirection in 100 LQFP package only
Package code register preset by factory related to package in use, writable once after reset. Also includes bit to reprogram routing of API_EXTCLK in all packages.
Control register for free-running clock outputs

1.3.5 Main External Oscillator (XOSCLCP)

Loop control Pierce oscillator using a 4 MHz to 16 MHz crystal — Current gain control on amplitude output — Signal with low harmonic distortion — Low power — Good noise immunity — Eliminates need for external current limiting resistor — Transconductance sized for optimum start-up margin for typical crystals — Oscillator pins can be shared w/ GPIO functionality

1.3.6 Internal RC Oscillator (IRC)

Trimmable internal reference clock. — Frequency: 1 MHz — Trimmed accuracy over –40˚C to +125˚C ambient temperature range: ±1.0% for temperature option C and V (see Table A-4) ±1.3% for temperature option M (see Table A-4)

1.3.7 Internal Phase-Locked Loop (IPLL)

Phase-locked-loop clock frequency multiplier — No external components required — Reference divider and multiplier allow large variety of clock rates — Automatic bandwidth control mode for low-jitter operation — Automatic frequency lock detector — Conﬁgurable option to spread spectrum for reduced EMC radiation (frequency modulation) — Reference clock sources: – External 4–16 MHz resonator/crystal (XOSCLCP) – Internal 1 MHz RC oscillator (IRC)

Device Overview MC9S12G-Family MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 31

1.3.8 System Integrity Support

Power-on reset (POR)
System reset generation
Illegal address detection with reset
Low-voltage detection with interrupt or reset
Real time interrupt (RTI)
Computer operating properly (COP) watchdog — Conﬁgurable as window COP for enhanced failure detection — Initialized out of reset using option bits located in ﬂash memory
Clock monitor supervising the correct function of the oscillator

1.3.9 Timer (TIM)

Up to eight x 16-bit channels for input capture or output compare
16-bit free-running counter with 7-bit precision prescaler
In case of eight channel timer Version an additional 16-bit pulse accumulator is available

1.3.10 Pulse Width Modulation Module (PWM)

Up to eight channel x 8-bit or up to four channel x 16-bit pulse width modulator — Programmable period and duty cycle per channel — Center-aligned or left-aligned outputs — Programmable clock select logic with a wide range of frequencies

1.3.11 Controller Area Network Module (MSCAN)

1 Mbit per second, CAN 2.0 A, B software compatible — Standard and extended data frames — 0–8 bytes data length — Programmable bit rate up to 1 Mbps
Five receive buffers with FIFO storage scheme
Three transmit buffers with internal prioritization
Flexible identiﬁer acceptance ﬁlter programmable as: — 2 x 32-bit — 4 x 16-bit — 8 x 8-bit
Wakeup with integrated low pass ﬁlter option
Loop back for self test
Listen-only mode to monitor CAN bus

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Bus-off recovery by software intervention or automatically
16-bit time stamp of transmitted/received messages

1.3.12 Serial Communication Interface Module (SCI)

Up to three SCI modules
Full-duplex or single-wire operation
Standard mark/space non-return-to-zero (NRZ) format
Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse widths
13-bit baud rate selection
Programmable character length
Programmable polarity for transmitter and receiver
Active edge receive wakeup
Break detect and transmit collision detect supporting LIN 1.3, 2.0, 2.1 and SAE J2602

1.3.13 Serial Peripheral Interface Module (SPI)

Up to three SPI modules
Conﬁgurable 8- or 16-bit data size
Full-duplex or single-wire bidirectional
Double-buffered transmit and receive
Master or slave mode
MSB-ﬁrst or LSB-ﬁrst shifting
Serial clock phase and polarity options

1.3.14 Analog-to-Digital Converter Module (ADC)

Up to 16-channel, 10-bit/12-bit1 analog-to-digital converter — 3 us conversion time — 8-/10 1-bit resolution — Left or right justiﬁed result data — Wakeup from low power modes on analog comparison > or <= match — Continuous conversion mode — External triggers to initiate conversions via GPIO or peripheral outputs such as PWM or TIM — Multiple channel scans — Precision ﬁxed voltage reference for ADC conversions

Pins can also be used as digital I/O including wakeup capability 1. 12-bit resolution only available on S12GA192 and S12GA240 devices.

Device Overview MC9S12G-Family MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 33

1.3.15 Reference Voltage Attenuator (RVA)

Attenuation of ADC reference voltage with low long-term drift

1.3.16 Digital-to-Analog Converter Module (DAC)

1 digital-analog converter channel (per module) with: — 8 bit resolution — full and reduced output voltage range — buffered or unbuffered analog output voltage usable
operational ampliﬁer stand alone usable

1.3.17 Analog Comparator (ACMP)

Low offset, low long-term offset drift
Selectable interrupt on rising, falling, or rising and falling edges of comparator output
Option to output comparator signal on an external pin
Option to trigger timer input capture events

1.3.18 On-Chip Voltage Regulator (VREG)

Linear voltage regulator with bandgap reference
Low-voltage detect (LVD) with low-voltage interrupt (LVI)
Power-on reset (POR) circuit
Low-voltage reset (LVR)

1.3.19 Background Debug (BDM)

Non-intrusive memory access commands
Supports in-circuit programming of on-chip nonvolatile memory

1.3.20 Debugger (DBG)

Trace buffer with depth of 64 entries
Three comparators (A, B and C) — Access address comparisons with optional data comparisons — Program counter comparisons — Exact address or address range comparisons
Two types of comparator matches — Tagged This matches just before a speciﬁc instruction begins execution — Force This is valid on the ﬁrst instruction boundary after a match occurs
Four trace modes

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Four stage state sequencer

1.4 Key Performance Parameters

The key performance parameters of S12G devices feature:

Continuous Operating voltage of 3.15 V to 5.5 V
Operating temperature (T A) of –40˚C to 125˚C
Junction temperature (T J) of up to 150˚C
Bus frequency (f Bus) of dc to 25 MHz
Packaging: — 100-pin LQFP, 0.5 mm pitch, 14 mm x 14 mm outline — 64-pin LQFP, 0.5 mm pitch, 10 mm x 10 mm outline — 48-pin LQFP, 0.5 mm pitch, 7 mm x 7 mm outline — 48-pin QFN, 0.5 mm pitch, 7 mm x 7 mm outline — 32-pin LQFP, 0.8 mm pitch, 7 mm x 7 mm outline — 20 TSSOP, 0.65 mm pitch, 4.4 mm x 6.5 mm outline

1.5 Block Diagram

Figure 1-1 shows a block diagram of the MC9S12G-Family.

Device Overview MC9S12G-Family MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 35 Figure 1-1. MC9S12G-Family Block Diagram

1.6 Family Memory Map

Table 1-3 shows the MC9S12G-Family register memory map. Table 1-3. Device Register Memory Map Address Module Size (Bytes) 0x0000–0x0009 PIM (Port Integration Module ) 10 1K … 11K bytes RAM RESET EXTAL XTAL 0.5K … 4K bytes EEPROM with ECC BKGD VDDR Real Time Interrupt Clock Monitor Single-wire Background TEST Debug Module ADC Interrupt Module (WU Int) SCI0 PS3 PS0 PS1 PS2 PTS AN[15:0] PAD[15:0] 10-bit 8...16 ch. 16-bit 6 … 8 channel Timer TIM Asynchronous Serial IF 8-bit 6 … 8 channel Pulse Width Modulator PWM PB[7:0] PTB PA[7:0] PTA 16K … 240K bytes Flash with ECC CPU12-V1 COP Watchdog PLL with Frequency Modulation option Debug Module 3 comparators

64 Byte Trace Buffer

PTJ (Wake-up Int) CAN PM3 PM0 PM1 PM2 PTM msCAN 2.0B RXCAN TXCAN Auton. Periodic Int. PJ7 PJ6 PT3 PT0 PT1 PT2 PTT PT7 PT4 PT5 PT6 PP3 PP0 PP1 PP2 PTP (Wake-up Int)PP7 PP4 PP5 PWM3 PWM0 PWM1 PWM2 PWM4 PWM5 IOC3 IOC0 IOC1 IOC2 IOC7 IOC4 IOC5 IOC6 VDDA VSSA VRH VDDX1/VSSX1 VDDX2/VSSX2 PJ0 PJ1 3-5V IO Supply VSS Low Power Pierce Oscillator PP6PWM6 PWM7 SCI1 Asynchronous Serial IF RXD TXD MOSI SS SCK MISOSPI0 Synchronous Serial IF PS4 PS5 PS6 PS7 SCI2 Asynchronous Serial IF RXD TXD Voltage Regulator Input: 3.13V – 5.5V Block Diagram shows the maximum configuration! MOSI SS SCK MISOSPI1 Synchronous Serial IF MOSI SS SCK MISOSPI2 Synchronous Serial IF PJ3 PJ4 PJ5 PD[7:0] PTD PC[7:0] PTC VDDX3/VSSX3 Not all pins or all peripherals are available on all devices and packages. Rerouting options are not shown. PE0 PTEPE1 PTAD Analog-Digital Converter ACMP Analog Comparator DAC0 Digital-Analog Converter AMPM AMP DACU AMPP DAC1 Digital-Analog Converter 12-bit 16 ch. or RVA Internal RC Oscillator

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0x000A–0x000B MMC (Memory Map Control) 2 0x000C–0x000D PIM (Port Integration Module) 2 0x000E–0x000F Reserved 2 0x0010–0x0017 MMC (Memory Map Control) 8 0x0018–0x0019 Reserved 2 0x001A–0x001B Device ID register 2 0x001C–0x001F PIM (Port Integration Module) 4 0x0020–0x002F DBG (Debug Module) 16 0x0030–0x0033 Reserved 4 0x0034–0x003F CPMU (Clock and Power Management) 12 0x0040–0x006F TIM (Timer Module <= 8 channels) 48 0x0070–0x009F ADC (Analog to Digital Converter <= 16 channels) 48 0x00A0–0x00C7 PWM (Pulse-Width Modulator <= 8 channels) 40 0x00C8–0x00CF SCI0 (Serial Communication Interface) 8 0x00D0–0x00D7 SCI1 (Serial Communication Interface) 1 8 0x00D8–0x00DF SPI0 (Serial Peripheral Interface) 8 0x00E0–0x00E7 Reserved 8 0x00E8–0x00EF SCI2 (Serial Communication Interface) 2 8 0x00F0–0x00F7 SPI1 (Serial Peripheral Interface) 3 8 0x00F8–0x00FF SPI2 (Serial Peripheral Interface) 4 8 0x0100–0x0113 FTMRG control registers 20 0x0114–0x011F Reserved 12 0x0120 INT (Interrupt Module) 1 0x0121–0x013F Reserved 31 0x0140–0x017F CAN 5 64 0x0180–0x023F Reserved 192 0x0240–0x025F PIM (Port Integration Module) 32 0x0260–0x0261 ACMP (Analog Comparator) 6 2 0x0262–0x0275 PIM (Port Integration Module) 20 0x0276 RVA (Reference Voltage Attenuator) 7 1 0x0277–0x027F PIM (Port Integration Module) 9 0x0280–0x02EF Reserved 112 0x02F0–0x02FF CPMU (Clock and Power Management) 16 0x0300–0x03BF Reserved 192 0x03C0–0x03C7 DAC0 (Digital to Analog Converter) 8 8 Address Module Size (Bytes)

Device Overview MC9S12G-Family MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 37 NOTE Reserved register space shown in Table 1-3 is not allocated to any module. This register space is reserved for future use. Writing to these locations has no effect. Read access to these locations returns zero. Figure 1-2 shows S12G CPU and BDM local address translation to the global memory map as a graphical representation. In conjunction Table 1-4 shows the address ranges and mapping to 256K global memory space for P-Flash, EEPROM and RAM. The whole 256K global memory space is visible through the P-Flash window located in the 64k local memory map located at 0x8000 - 0xBFFF using the PPAGE register. 0x03C8–0x03CF DAC1 (Digital to Analog Converter) 8 8 0x03D0–0x03FF Reserved 48

1 The SCI1 is not available on the S12GN8, S12GN16, S12GN32, and S12GN32 devices

2 The SCI2 is not available on the S12GN8, S12GN16, S12GN32, , S12GN32, S12G48,

3 The SPI1 is not available on the S12GN8, S12GN16, S12GN24, and S12GN32 devices

4 The SPI2 is not available on the S12GN8, S12GN16, S12GN32, , S12GN32, S12G48,

5 The CAN is not available on the S12GN8, S12GN16, S12GN24, S12GN32, and

6 The ACMP is only available on the S12GN8, S12GN16, S12GN24, S12GN32,

S12GN48,S12GN48, S12G48, and S12G64 devices

7 The RVA is only available on the S12GA192 and S12GA240 devices

8 DAC0 and DAC1 are only available on the S12GA192 and S12GA240 devices

Table 1-4. MC9S12G-Family Memory Parameters Feature S12GN16 S12GN32 S12G48 S12GN48 S12G64 S12G96 S12G128 S12G192 S12GA192 S12G240 S12GA240 P-Flash size 16KB 32KB 48KB 64KB 96KB 128KB 192KB 240KB PF_LOW 0x3C000 0x38000 0x34000 0x30000 0x28000 0x20000 0x10000 0x04000 PF_LOW_UNP (unpaged) 0xC000 0x8000 0x4000 ————— PPAGES 0x0F 0x0E - 0x0F 0x0D - 0x0F 0x0C - 0x0F 0x0A - 0x0F 0x08 - 0x0F 0x04 - 0x0F 0x01 - 0x0F EEPROM [Bytes] 512 1024 1536 2048 3072 4096 4096 4096 EEPROM_HI 0x05FF 0x07FF 0x09FF 0x0BFF 0x0FFF 0x13FF 0x13FF 0x13FF Address Module Size (Bytes)

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RAM [Bytes] 1024 2048 4096 4096 8192 8192 11264 11264 RAM_LOW 0x3C00 0x3800 0x3000 0x3000 0x2000 0x2000 0x1400 0x1400 Unpaged Flash space left — — — 0x0C00- 0x2FFF 0x1000- 0x1FFF 0x1400- 0x1FFF Unpaged Flash2 — — — 9KB 4KB 3KB — — 1 While for memory sizes <64K the whole 256k space could be addressed using the PPAGE, it is more efﬁcient to use an unpaged memory model

2 Page 0xC

Table 1-4. MC9S12G-Family Memory Parameters Feature S12GN16 S12GN32 S12G48 S12GN48 S12G64 S12G96 S12G128 S12G192 S12GA192 S12G240 S12GA240

Device Overview MC9S12G-Family MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 39 Figure 1-2. MC9S12G Global Memory Map Paging Window 0x3_FFFF Local CPU and BDM Memory Map Global Memory Map 0xFFFF 0xC000 0x0_0400 0x0_0000 0x3_C000 0x0000 0x8000 0x0400 0x4000 0x0_4000 Paging Window Flash Space Flash Space RAMRAM UnimplementedUnimplemented Flash SpaceFlash Space Flash SpaceFlash Space Flash SpaceFlash Space Register SpaceRegister Space Internal NVM Resources Internal NVM Resources Flash SpaceFlash Space Flash SpaceFlash Space Flash SpaceFlash Space Flash SpaceFlash Space EEPROMEEPROM EEPROMEEPROM Page 0x1Page 0x1 Page 0xFPage 0xF Page 0xDPage 0xD Register SpaceRegister Space Page 0xCPage 0xC Page 0xEPage 0xE Page 0xFPage 0xF Page 0xDPage 0xD Page 0xCPage 0xC NVMRES=0NVMRES=0 NVMRES=1NVMRES=1 Flash SpaceFlash Space Page 0x2Page 0x2 0x3_0000 0x3_4000 0x3_8000 0x0_8000 RAMRAM

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1.6.1 Part ID Assignments

The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses 0x001A and 0x001B). The read-only value is a unique part ID for each revision of the chip.Table 1-5 shows the assigned part ID number and Mask Set number.

1.7 Signal Description and Device Pinouts

This section describes signals that connect off-chip. It includes a pinout diagram, a table of signal properties, and detailed discussion of signals. It is built from the signal description sections of the individual IP blocks on the device.

1.7.1 Pin Assignment Overview

Table 1-6 provides a summary of which ports are available for each package option. Table 1-5. Assigned Part ID Numbers Device Mask Set Number Part ID MC9S12GA240 0N95B 0xF080 MC9S12G240 0N95B 0xF080 MC9S12GA192 0N95B 0xF080 MC9S12G192 0N95B 0xF080 MC9S12G128 0N51A 0xF180 MC9S12G96 0N51A 0xF180 MC9S12G64 0N75C1

1 Only available in 48-pin LQFP and 64-pin LQFP

2 Only available in 32-pin LQFP

3 Only available in 48-pin LQFP and 48-pin QFN

4 Only available in 20-pin TSSOP and 32-pin LQFP

Device Overview MC9S12G-Family MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 41 NOTE To avoid current drawn from ﬂoating inputs, the input buffers of all non-bonded pins are disabled.

1.7.2 Detailed Signal Descriptions

This section describes the signal properties. The relation between signals and package pins is described in section 1.8 Device Pinouts.

1.7.2.1 RESET — External Reset Signal

The RESET signal is an active low bidirectional control signal. It acts as an input to initialize the MCU to a known start-up state, and an output when an internal MCU function causes a reset. TheRESET pin has an internal pull-up device.

1.7.2.2 TEST — Test Pin

This input only pin is reserved for factory test. This pin has an internal pull-down device. NOTE The TEST pin must be tied to ground in all applications. Table 1-6. Port Availability by Package Option Port 20 TSSOP 32 LQFP 48 LQFP

48 QFN 64 LQFP 100 LQFP

Port AD/ADC Channels 6 8 12 16 16 Port A pins 00008 Port B pins 00008 Port C pins 00008 Port D pins 00008 Port E pins 22222 P o r t J 00488 P o r t M 02244 P o r t P 04688 P o r t S 46888 P o r t T 24688 Sum of Ports 14 26 40 54 86 I/O Power Pairs VDDX/VSSX 1/1 1/1 1/1 1/1 3/3

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1.7.2.3 BKGD / MODC — Background Debug and Mode Pin

The BKGD/MODC pin is used as a pseudo-open-drain pin for the background debug communication. It is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODC bit at the rising edge of RESET. The BKGD pin has an internal pull-up device.

1.7.2.4 EXTAL, XTAL — Oscillator Signal

EXTAL and XTAL are the crystal driver and external clock signals. On reset all the device clocks are derived from the internal reference clock. XTAL is the oscillator output.

1.7.2.5 PAD[15:0] / KWAD[15:0] — Port AD Input Pins of ADC

PAD[15:0] are general-purpose input or output signals. These signals can have a pull-up or pull-down device selected and enabled on per signal basis. Out of reset the pull devices are disabled.

1.7.2.6 PA[7:0] — Port A I/O Signals

PA[7:0] are general-purpose input or output signals. The signals can have pull-up devices, enabled by a single control bit for this signal group. Out of reset the pull-up devices are disabled .

1.7.2.7 PB[7:0] — Port B I/O Signals

PB[7:0] are general-purpose input or output signals. The signals can have pull-up devices, enabled by a single control bit for this signal group. Out of reset the pull-up devices are disabled .

1.7.2.8 PC[7:0] — Port C I/O Signals

PC[7:0] are general-purpose input or output signals. The signals can have pull-up devices, enabled by a single control bit for this signal group. Out of reset the pull-up devices are disabled .

1.7.2.9 PD[7:0] — Port D I/O Signals

PD[7:0] are general-purpose input or output signals. The signals can have pull-up device, enabled by a single control bit for this signal group. Out of reset the pull-up devices are disabled.

1.7.2.10 PE[1:0] — Port E I/O Signals

PE[1:0] are general-purpose input or output signals. The signals can have pull-down device, enabled by a single control bit for this signal group. Out of reset the pull-down devices are enabled.

1.7.2.11 PJ[7:0] / KWJ[7:0] — Port J I/O Signals

PJ[7:0] are general-purpose input or output signals. The signals can be conﬁgured on per signal basis as interrupt inputs with wakeup capability (KWJ[7:0]). They can have a pull-up or pull-down device selected and enabled on per signal basis. Out of reset the pull devices are enabled .

Device Overview MC9S12G-Family MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 43

1.7.2.12 PM[3:0] — Port M I/O Signals

PM[3:0] are general-purpose input or output signals. They can have a pull-up or pull-down device selected and enabled on per signal basis. Out of reset the pull devices are disabled. The signals can be conﬁgured on per pin basis to open-drain mode.

1.7.2.13 PP[7:0] / KWP[7:0] — Port P I/O Signals

PP[7:0] are general-purpose input or output signals. The signals can be conﬁgured on per signal basis as interrupt inputs with wakeup capability (KWP[7:0]). They can have a pull-up or pull-down device selected and enabled on per signal basis. Out of reset the pull devices are disabled .

1.7.2.14 PS[7:0] — Port S I/O Signals

PS[7:0] are general-purpose input or output signals. They can have a pull-up or pull-down device selected and enabled on per signal basis. Out of reset the pull-up devices are enabled. The signals can be conﬁgured on per pin basis in open-drain mode.

1.7.2.15 PT[7:0] — Port TI/O Signals

PT[7:0] are general-purpose input or output signals. They can have a pull-up or pull-down device selected and enabled on per signal basis. Out of reset the pull devices are disabled .

1.7.2.16 AN[15:0] — ADC Input Signals

AN[15:0] are the analog inputs of the Analog-to-Digital Converter.

1.7.2.17 ACMP Signals

1.7.2.17.1 ACMPP — Non-Inverting Analog Comparator Input

ACMPP is the non-inverting input of the analog comparator.

1.7.2.17.2 ACMPM — Inverting Analog Comparator Input

ACMPM is the inverting input of the analog comparator.

1.7.2.17.3 ACMPO — Analog Comparator Output

ACMPO is the output of the analog comparator.

1.7.2.18 DAC Signals

1.7.2.18.1 DACU[1:0] Output Pins

These analog pins is used for the unbuffered analog output V oltages from the DAC0 and the DAC1 resistor network output, when the according mode is selected.

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1.7.2.18.2 AMP[1:0] Output Pins

These analog pins are used for the buffered analog outputs V oltage from the operational ampliﬁer outputs, when the according mode is selected.

1.7.2.18.3 AMPP[1:0] Input Pins

These analog input pins areused as input signals for the operational ampliﬁers positive input pins when the according mode is selected.

1.7.2.18.4 AMPM[1:0] Input Pins

These analog input pins are used as input signals for the operational ampliﬁers negative input pin when the according mode is selected.

1.7.2.19 SPI Signals

1.7.2.19.1 SS[2:0] Signals

Those signals are associated with the slave select SS functionality of the serial peripheral interfaces SPI2-0.

1.7.2.19.2 SCK[2:0] Signals

Those signals are associated with the serial clock SCK functionality of the serial peripheral interfaces SPI2-0.

1.7.2.19.3 MISO[2:0] Signals

Those signals are associated with the MISO functionality of the serial peripheral interfaces SPI2-0. They act as master input during master mode or as slave output during slave mode.

1.7.2.19.4 MOSI[2:0] Signals

Those signals are associated with the MOSI functionality of the serial peripheral interfaces SPI2-0. They act as master output during master mode or as slave input during slave mode.

1.7.2.20 SCI Signals

1.7.2.20.1 RXD[2:0] Signals

Those signals are associated with the receive functionality of the serial communication interfaces SCI2-0.

1.7.2.20.2 TXD[2:0] Signals

Those signals are associated with the transmit functionality of the serial communication interfaces SCI2-0.

Device Overview MC9S12G-Family MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 45

1.7.2.21 CAN signals

1.7.2.21.1 RXCAN Signal

This signal is associated with the receive functionality of the scalable controller area network controller (MSCAN).

1.7.2.21.2 TXCAN Signal

This signal is associated with the transmit functionality of the scalable controller area network controller (MSCAN).

1.7.2.22 PWM[7:0] Signals

The signals PWM[7:0] are associated with the PWM module outputs.

1.7.2.23 Internal Clock outputs

1.7.2.23.1 ECLK

This signal is associated with the output of the divided bus clock (ECLK). NOTE This feature is only intended for debug purposes at room temperature. It must not be used for clocking external devices in an application.

1.7.2.23.2 ECLKX2

This signal is associated with the output of twice the bus clock (ECLKX2). NOTE This feature is only intended for debug purposes at room temperature. It must not be used for clocking external devices in an application.

1.7.2.23.3 API_EXTCLK

This signal is associated with the output of the API clock (API_EXTCLK).

1.7.2.24 IOC[7:0] Signals

The signals IOC[7:0] are associated with the input capture or output compare functionality of the timer (TIM) module.

1.7.2.25 IRQ

This signal is associated with the maskable IRQ interrupt.

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1.7.2.26 XIRQ

This signal is associated with the non-maskable XIRQ interrupt.

1.7.2.27 ETRIG[3:0]

These signals are inputs to the Analog-to-Digital Converter. Their purpose is to trigger ADC conversions.

1.7.3 Power Supply Pins

MC9S12G power and ground pins are described below. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. NOTE All ground pins must be connected together in the application.

1.7.3.1 VDDX[3:1]/VDDX, VSSX[3:1]/VSSX— Power and Ground Pins for I/O Drivers

External power and ground for I/O drivers. Bypass requirements depend on how heavily the MCU pins are loaded. All VDDX pins are connected together internally. All VSSX pins are connected together internally. NOTE Not all VDDX[3:1]/VDDX and VSSX[3:1]VSSX pins are available on all packages. Refer to section 1.8 Device Pinouts for further details.

1.7.3.2 VDDR — Power Pin for Internal Voltage Regulator

Power supply input to the internal voltage regulator. NOTE On some packages VDDR is bonded to VDDX and the pin is named VDDXR. Refer to section 1.8 Device Pinouts for further details.

1.7.3.3 VSS — Core Ground Pin

The voltage supply of nominally 1.8V is derived from the internal voltage regulator. The return current path is through the VSS pin.

1.7.3.4 VDDA, VSSA — Power Supply Pins for DAC,ACMP, RVA, ADC and

These are the power supply and ground input pins for the digital-to-analog converter, the analog comparator, the reference voltage attenuator, the analog-to-digital converter and the voltage regulator.

Device Overview MC9S12G-Family MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 47 NOTE On some packages VDDA is connected with VDDXR and the common pin is named VDDXRA. Also the VSSA is connected to VSSX and the common pin is named VSSXA. See section Section 1.8, “Device Pinouts” for further details.

1.7.3.5 VRH — Reference Voltage Input Pin

VRH is the reference voltage input pin for the digital-to-analog converter and the analog-to-digital converter. Refer to Section 1.18, “ADC VRH/VRL Signal Connection” for further details. On some packages VRH is tied to VDDA or VDDXRA. Refer to section1.8 Device Pinouts for further details.

1.7.3.6 Power and Ground Connection Summary

Table 1-7. Power and Ground Connection Summary Mnemonic Nominal Voltage Description VDDR 3.15V – 5.0 V External power supply for internal voltage regulator. VSS 0V Return ground for the logic supply generated by the internal regulator VDDX[3:1] 3.15V – 5.0 V External power supply for I/O drivers. The 100-pin package features 3 I/O supply pins. VSSX[3:1] 0V Return ground for I/O drivers. The100-pin package provides 3 ground pins VDDX 3.15V – 5.0 V External power supply for I/O drivers, All packages except 100-pin feature 1 I/O supply. VSSX 0V Return ground for I/O drivers. All packages except 100-pin provide 1 I/O ground pin. VDDA 3.15V – 5.0 V External power supply for the analog-to-digital converter and for the reference circuit of the internal voltage regulator. VSSA 0V Return ground for VDDA analog supply VDDXR 3.15V – 5.0 V External power supply for I/O drivers and internal voltage regulator. For the 48-pin package the VDDX and VDDR supplies are combined on one pin. VDDXRA 3.15V – 5.0 V External power supply for I/O drivers, internal voltage regulator and analog-to-digital converter. For the 20- and 32-pin package the VDDX, VDDR and VDDA supplies are combined on one pin. VSSXA 0V Return ground for I/O driver and VDDA analog supply VRH 3.15V – 5.0 V Reference voltage for the analog-to-digital converter.

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1.8 Device Pinouts

1.8.1 S12GN16 and S12GN32

1.8.1.1 Pinout 20-Pin TSSOP

Figure 1-3. 20-Pin TSSOP Pinout for S12GN16 and S12GN32 Table 1-8. 20-Pin TSSOP Pinout for S12GN16 and S12GN32 Function <----lowest-----PRIORITY -----highest----> Power Supply Internal Pull Resistor Package Pin Pin 2nd Func. 3rd Func. 4th Func 5th Func 6th Func 7th Func 8th Func CTRL Reset State

1 PS6 IOC3 SCK0 — — — — — V DDX PERS/PPSS Up

2 PS7 ETRIG3 API_EXTCLK ECLK PWM3 TXD0 SS0 — V DDX PERS/PPSS Up

6 PE0

1 ETRIG0 PWM0 IOC2 RXD0 EXTAL — — V DDX PUCR/PDPEE Down

8 PE1

1 ETRIG1 PWM1 IOC3 TXD0 XTAL — — PUCR/PDPEE Down

9 TEST — — — — — — — N.A. RESET pin Down

10 BKGD MODC — — — — — — V DDX Always on Up

11 PT1 IOC1 IRQ — — — — — V DDX PERT/PPST Disabled

12 PT0 IOC0 XIRQ — — — — — V DDX PERT/PPST Disabled

13 PAD0 KWAD0 AN0 — — — — — V DDA PER1AD/PPS1AD Disabled

14 PAD1 KWAD1 AN1 — — — — — V DDA PER1AD/PPS1AD Disabled

15 PAD2 KWAD2 AN2 — — — — — V DDA PER1AD/PPS1AD Disabled

PS4/ETRIG2/PWM2/RXD0/MISO0 PAD5/KWAD5/ETRIG3/PWM3/IOC3/TXD0/AN5/ACMPM PAD4/KWAD4/ETRIG2/PWM2/IOC2/RXD0/AN4/ACMPP PAD3/KWAD3/AN3/ACMPO PAD2/KWAD2/AN2 PAD1/KWAD1/AN1 PAD0/KWAD0/AN0 PT0/IOC0/ XIRQ PT1/IOC1/IRQ SCK0/IOC3/PS6 SS0/TXD0/PWM3/ECLK/API_EXTCLK/ETRIG3/PS7 RESET VRH/VDDXRA VSSXA EXTAL/RXD0/PWM0/IOC2/ETRIG0/PE0 VSS XTAL/TXD0/PWM1/IOC3/ETRIG1/PE1 TEST BKGD

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16 PAD3 KWAD3 AN3 ACMPO — — — — V DDA PER1AD/PPS1AD Disabled

17 PAD4 KWAD4 ETRIG2 PWM2 IOC2 RXD0 AN4 ACMPP V DDA PER1AD/PPS1AD Disabled

18 PAD5 KWAD5 ETRIG3 PWM3 IOC3 TXD0 AN5 ACMPM V DDA PER1AD/PPS1AD Disabled

19 PS4 ETRIG2 PWM2 RXD0 MISO0 — — — V DDX PERS/PPSS Up

20 PS5 IOC2 MOSI0 — — — — — V DDX PERS/PPSS Up

1 The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled Table 1-8. 20-Pin TSSOP Pinout for S12GN16 and S12GN32 Function <----lowest-----PRIORITY -----highest----> Power Supply Internal Pull Resistor Package Pin Pin 2nd Func. 3rd Func. 4th Func 5th Func 6th Func 7th Func 8th Func CTRL Reset State

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1.8.1.2 Pinout 32-Pin LQFP

Figure 1-4. 32-Pin LQFP OPinout for S12GN16 and S12GN32 Table 1-9. 32-Pin LQFP OPinout for S12GN16 and S12GN32 Function <----lowest-----PRIORITY -----highest----> Power Supply Internal Pull Resistor Package Pin Pin 2nd Func. 3rd Func. 4th Func 5th Func CTRL Reset State

1 RESET — — — — V DDX PULLUP

PWM0/API_EXTCLK/ETRIG0/KWP0/PP0 PWM1/ECLKX2/ETRIG1/KWP1/PP1 PWM2/ETRIG2/KWP2/PP2 PWM3/ETRIG3/KWP3/PP3 IOC3/PT3 IOC2/PT2 IRQ/IOC1/PT1 XIRQ/IOC0/PT0 RESET VRH/VDDXRA VSSXA EXTAL/PE0 VSS XTAL/PE1 TEST BKGD PM1/TXD1 PM0/RXD1 PS7/API_EXTCLK/ECLK/PWM5/ SS0 PS6/IOC5/SCK0 PS5/IOC4/MOSI0 PS4/PWM4/MISO0 PS1/TXD0 PS0/RXD0

Device Overview MC9S12G-Family MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 51

4 PE0 1 EXTAL — — — — PUCR/PDPEE Down

6 PE1

1 XTAL — — — — PUCR/PDPEE Down

7 TEST — — — — N.A. RESET pin Down

8 BKGD MODC — — — V DDX PUCR/BKPUE Up

9 PP0 KWP0 ETRIG0 API_EXTCLK PWM0 V DDX PERP/PPSP Disabled

10 PP1 KWP1 ETRIG1 ECLKX2 PWM1 V DDX PERP/PPSP Disabled

11 PP2 KWP2 ETRIG2 PWM2 — V DDX PERP/PPSP Disabled

12 PP3 KWP3 ETRIG3 PWM3 — V DDX PERP/PPSP Disabled

13 PT3 IOC3 — — — V DDX PERT/PPST Disabled

14 PT2 IOC2 — — — V DDX PERT/PPST Disabled

15 PT1 IOC1 IRQ — — V DDX PERT/PPST Disabled

16 PT0 IOC0 XIRQ — — V DDX PERT/PPST Disabled

17 PAD0 KWAD0 AN0 — — V DDA PER1AD/PPS1AD Disabled

18 PAD1 KWAD1 AN1 — — V DDA PER1AD/PPS1AD Disabled

19 PAD2 KWAD2 AN2 — — V DDA PER1AD/PPS1AD Disabled

20 PAD3 KWAD3 AN3 — — V DDA PER1AD/PPS1AD Disabled

21 PAD4 KWAD4 AN4 — — V DDA PER1AD/PPS1AD Disabled

22 PAD5 KWAD5 AN5 ACMPO — V DDA PER1AD/PPS1AD Disabled

23 PAD6 KWAD6 AN6 ACMPP — V DDA PER1AD/PPS1AD Disabled

24 PAD7 KWAD7 AN7 ACMPM — V DDA PER1AD/PPS1AD Disabled

25 PS0 RXD0 — — — V DDX PERS/PPSS Up

26 PS1 TXD0 — — — V DDX PERS/PPSS Up

27 PS4 PWM4 MISO0 — — V DDX PERS/PPSS Up

28 PS5 IOC4 MOSI0 — — V DDX PERS/PPSS Up

29 PS6 IOC5 SCK0 — — V DDX PERS/PPSS Up

30 PS7 API_EXTCLK ECLK PWM5 SS0 V DDX PERS/PPSS Up

31 PM0 — — — — V DDX PERM/PPSM Disabled

32 PM1 — — — — V DDX PERM/PPSM Disabled

Table 1-9. 32-Pin LQFP OPinout for S12GN16 and S12GN32 Function <----lowest-----PRIORITY -----highest----> Power Supply Internal Pull Resistor Package Pin Pin 2nd Func. 3rd Func. 4th Func 5th Func CTRL Reset State

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1.8.1.3 Pinout 48-Pin LQFP/QFN

Figure 1-5. 48-Pin LQFP/QFN Pinout for S12GN16 and S12GN32 1 The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled S12GN16 S12GN32 48-Pin LQFP/QFN PAD7/KWAD7/AN7 PAD6/KWAD6/AN6 PAD5/KWAD5/AN5 PAD4/KWAD4/AN4 PAD11/KWAD11/ACMPM PAD3/KWAD3/AN3 PAD10/KWAD10/ACMPP PAD2/KWAD2/AN2 PAD9/KWAD9/ACMPO PAD1/KWAD1/AN1 PAD8/KWAD8 PAD0/KWAD0/AN0 PWM0/API_EXTCLK/ETRIG0/KWP0/PP0 PWM1/ECLKX2/ETRIG1/KWP1/PP1 ETRIG2/KWP2/PP2 ETRIG3/KWP3/PP3 PWM4/KWP4/PP4 PWM5/KWP5/PP5 IOC5/PT5 IOC4/PT4 IOC3/PT3 IOC2/PT2 IRQ/IOC1/PT1 XIRQ/IOC0/PT0 RESET VDDXR VSSX EXTAL/PE0 VSS XTAL/PE1 TEST KWJ0/PJ0 KWJ1/PJ1 KWJ2/PJ2 KWJ3/PJ3 BKGD PM1 PM0 PS7/API_EXTCLK/ECLK/ SS0 PS6/SCK0 PS5/MOSI0 PS4/MISO0 PS3 PS2 PS1/TXD0 PS0/RXD0 VSSA VDDA/VRH

Device Overview MC9S12G-Family MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 53 Table 1-10. 48-Pin LQFP/QFN Pinout for S12GN16 and S12GN32 Function <----lowest-----PRIORITY -----highest----> Power Supply Internal Pull Resistor Package Pin Pin 2nd Func. 3rd Func. 4th Func 5th Func CTRL Reset State

4 PE0

1 EXTAL — — — V DDX PUCR/PDPEE Down

1 XTAL — — — V DDX PUCR/PDPEE Down

7 TEST — — — — N.A. RESET pin Down

8 PJ0 KWJ0 — — — V DDX PERJ/PPSJ Up

9 PJ1 KWJ1 — — — V DDX PERJ/PPSJ Up

10 PJ2 KWJ2 — — — V DDX PERJ/PPSJ Up

11 PJ3 KWJ3 — — — V DDX PERJ/PPSJ Up

12 BKGD MODC — — — V DDX PUCR/BKPUE Up

13 PP0 KWP0 ETRIG0 API_EXTCLK PWM0 V DDX PERP/PPSP Disabled

14 PP1 KWP1 ETRIG1 ECLKX2 PWM1 V DDX PERP/PPSP Disabled

15 PP2 KWP2 ETRIG2 PWM2 — V DDX PERP/PPSP Disabled

16 PP3 KWP3 ETRIG3 PWM3 — V DDX PERP/PPSP Disabled

17 PP4 KWP4 PWM4 — — V DDX PERP/PPSP Disabled

18 PP5 KWP5 PWM5 — — V DDX PERP/PPSP Disabled

19 PT5 IOC5 — — — V DDX PERT/PPST Disabled

20 PT4 IOC4 — — — V DDX PERT/PPST Disabled

21 PT3 IOC3 — — — V DDX PERT/PPST Disabled

22 PT2 IOC2 — — — V DDX PERT/PPST Disabled

23 PT1 IOC1 IRQ — — V DDX PERT/PPST Disabled

24 PT0 IOC0 XIRQ — — V DDX PERT/PPST Disabled

25 PAD0 KWAD0 AN0 — — V DDA PER1AD/PPS1AD Disabled

26 PAD8 KWAD8 — — — V DDA PER0AD/PPS0AD Disabled

27 PAD1 KWAD1 AN1 — — V DDA PER1AD/PPS1AD Disabled

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1.8.2 S12GN48

1.8.2.1 Pinout 32-Pin LQFP

28 PAD9 KWAD9 ACMPO — — V DDA PER0AD/PPS0AD Disabled

29 PAD2 KWAD2 AN2 — — V DDA PER1AD/PPS1AD Disabled

30 PAD10 KWAD10 ACMPP V DDA PER0AD/PPS0AD Disabled

31 PAD3 KWAD3 AN3 — — V DDA PER1AD/PPS1AD Disabled

32 PAD11 KWAD11 ACMPM V DDA PER0AD/PPS0AD Disabled

33 PAD4 KWAD4 AN4 — — V DDA PER1AD/PPS1AD Disabled

34 PAD5 KWAD5 AN5 — — V DDA PER1AD/PPS0AD Disabled

35 PAD6 KWAD6 AN6 — — V DDA PER1AD/PPS1AD Disabled

36 PAD7 KWAD7 AN7 — — V DDA PER1AD/PPS1AD Disabled

39 PS0 RXD0 — — — V

40 PS1 TXD0 — — — V DDX PERS/PPSS Up

41 PS2 — — — — V DDX PERS/PPSS Up

42 PS3 — — — — V DDX PERS/PPSS Up

43 PS4 MISO0 — — — V DDX PERS/PPSS Up

44 PS5 MOSI0 — — — V DDX PERS/PPSS Up

45 PS6 SCK0 — — — V DDX PERS/PPSS Up

46 PS7 API_EXTCLK ECLK SS0 — V DDX PERS/PPSS Up

47 PM0 — — — — V DDX PERM/PPSM Disabled

48 PM1 — — — — V DDX PERM/PPSM Disabled

1 The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled Table 1-10. 48-Pin LQFP/QFN Pinout for S12GN16 and S12GN32 Function <----lowest-----PRIORITY -----highest----> Power Supply Internal Pull Resistor Package Pin Pin 2nd Func. 3rd Func. 4th Func 5th Func CTRL Reset State

Device Overview MC9S12G-Family MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 55 Figure 1-6. 32-Pin LQFP Pinout for S12GN48 Table 1-11. 32-Pin LQFP Pinout for S12GN48 Function <----lowest-----PRIORITY -----highest----> Power Supply Internal Pull Resistor Package Pin Pin 2nd Func. 3rd Func. 4th Func 5th Func CTRL Reset State

1 EXTAL — — — — PUCR/PDPEE Down

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56 Freescale Semiconductor

6 PE1 1 XTAL — — — — PUCR/PDPEE Down

7 TEST — — — — N.A. RESET pin Down

31 PM0 RXD1 — — — V DDX PERM/PPSM Disabled

32 PM1 TXD1 — — — V DDX PERM/PPSM Disabled

1 The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled Table 1-11. 32-Pin LQFP Pinout for S12GN48 Function <----lowest-----PRIORITY -----highest----> Power Supply Internal Pull Resistor Package Pin Pin 2nd Func. 3rd Func. 4th Func 5th Func CTRL Reset State

Device Overview MC9S12G-Family MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 57

1.8.2.2 Pinout 48-Pin LQFP

Figure 1-7. 48-Pin LQFP Pinout for S12GN48 Table 1-12. 48-Pin LQFP Pinout for S12GN48 Function <----lowest-----PRIORITY -----highest----> Power Supply Internal Pull Resistor Package Pin Pin 2nd Func. 3rd Func. 4th Func 5th Func CTRL Reset State PWM0/API_EXTCLK/ETRIG0/KWP0/PP0 PWM1/ECLKX2/ETRIG1/KWP1/PP1 PWM2/ETRIG2/KWP2/PP2 PWM3/ETRIG3/KWP3/PP3 PWM4/KWP4/PP4 PWM5/KWP5/PP5 IOC5/PT5 IOC4/PT4 IOC3/PT3 IOC2/PT2 IRQ/IOC1/PT1 XIRQ/IOC0/PT0 RESET VDDXR VSSX EXTAL/PE0 VSS XTAL/PE1 TEST MISO1/KWJ0/PJ0 MOSI1/KWJ1/PJ1 SCK1/KWJ2/PJ2 SS1/KWJ3/PJ3 BKGD PM1 PM0 PS7/API_EXTCLK/ECLK/ SS0 PS6/SCK0 PS5/MOSI0 PS4/MISO0 PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 VSSA VDDA/VRH

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4 PE0 1 EXTAL — — — V DDX PUCR/PDPEE Down

7 TEST — — — — N.A. RESET pin Down

8 PJ0 KWJ0 MISO1 — — V DDX PERJ/PPSJ Up

9 PJ1 KWJ1 MOSI1 — — V DDX PERJ/PPSJ Up

10 PJ2 KWJ2 SCK1 — — V DDX PERJ/PPSJ Up

11 PJ3 KWJ3 SS1 — — V DDX PERJ/PPSJ Up

26 PAD8 KWAD8 AN8 — — V DDA PER0AD/PPS0AD Disabled

28 PAD9 KWAD9 AN9 ACMPO — V DDA PER0AD/PPS0AD Disabled

30 PAD10 KWAD10 AN10 ACMPP V DDA PER0AD/PPS0AD Disabled

Table 1-12. 48-Pin LQFP Pinout for S12GN48 Function <----lowest-----PRIORITY -----highest----> Power Supply Internal Pull Resistor Package Pin Pin 2nd Func. 3rd Func. 4th Func 5th Func CTRL Reset State

Device Overview MC9S12G-Family MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 59

32 PAD11 KWAD11 AN11 ACMPM V DDA PER0AD/PPS0AD Disabled

41 PS2 RXD1 — — — V DDX PERS/PPSS Up

42 PS3 TXD1 — — — V DDX PERS/PPSS Up

1 The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled Table 1-12. 48-Pin LQFP Pinout for S12GN48 Function <----lowest-----PRIORITY -----highest----> Power Supply Internal Pull Resistor Package Pin Pin 2nd Func. 3rd Func. 4th Func 5th Func CTRL Reset State

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1.8.2.3 Pinout 64-Pin LQFP

Figure 1-8. 64-Pin LQFP Pinout for S12GN48 S12GN48 64-Pin LQFP PWM0/API_EXTCLK/ETRIG0/KWP0/PP0 PWM1/ECLKX2/ETRIG1/KWP1/PP1 PWM2/ETRIG2/KWP2/PP2 PWM3/ETRIG3/KWP3/PP3 PWM4/KWP4/PP4 PWM5/KWP5/PP5 KWP6/PP6 KWP7/PP7 PT7 PT6 IOC5/PT5 IOC4/PT4 IOC3/PT3 IOC2/PT2 IRQ/IOC1/PT1 XIRQ/IOC0/PT0 KWJ6/PJ6 KWJ5/PJ5 KWJ4/PJ4 RESET VDDX VDDR VSSX EXTAL/PE0 VSS XTAL/PE1 TEST MISO1/KWJ0/PJ0 MOSI1/KWJ1/PJ1 SCK1/KWJ2/PJ2 SS1/KWJ3/PJ3 BKGD PJ7/KWJ7 PM3 PM2 PM1 PM0 PS7/API_EXTCLK/ECLK/ SS0 PS6/SCK0 PS5/MOSI0 PS4/MISO0 PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 VSSA VDDA VRH PAD15/KWAD15 PAD7/KWAD7/AN7 PAD14/KWAD14 PAD6/KWAD6/AN6 PAD13/KWAD13 PAD5/KWAD5/AN5 PAD12/KWAD12 PAD4/KWAD4/AN4 PAD11/KWAD11/AN11/ACMPM PAD3/KWAD3/AN3 PAD10/KWAD10/AN10/ACMPP PAD2/KWAD2/AN2 PAD9/KWAD9/AN9/ACMPO PAD1/KWAD1/AN1 PAD8/KWAD8/AN8 PAD0/KWAD0/AN0

Device Overview MC9S12G-Family MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 61 Table 1-13. 64-Pin LQFP Pinout for S12GN48 Function <----lowest-----PRIORITY -----highest----> Power Supply Internal Pull Resistor Package Pin Pin 2nd Func. 3rd Func. 4th Func 5th Func CTRL Reset State

1 PJ6 KWJ6 — — — V DDX PERJ/PPSJ Up

2 PJ5 KWJ5 — — — V DDX PERJ/PPSJ Up

3 PJ4 KWJ4 — — — V DDX PERJ/PPSJ Up

4 RESET — — — — V DDX PULLUP

8 PE0

10 PE1 1 XTAL — — — V DDX PUCR/PDPEE Down

11 TEST — — — — N.A. RESET pin Down

12 PJ0 KWJ0 MISO1 — — V DDX PERJ/PPSJ Up

13 PJ1 KWJ1 MOSI1 — — V DDX PERJ/PPSJ Up

14 PJ2 KWJ2 SCK1 — — V DDX PERJ/PPSJ Up

15 PJ3 KWJ3 SS1 — — V DDX PERJ/PPSJ Up

16 BKGD MODC — — — V DDX PUCR/BKPUE Up

17 PP0 KWP0 ETRIG0 API_EXTCLK PWM0 V DDX PERP/PPSP Disabled

18 PP1 KWP1 ETRIG1 ECLKX2 PWM1 V DDX PERP/PPSP Disabled

19 PP2 KWP2 ETRIG2 PWM2 — V DDX PERP/PPSP Disabled

20 PP3 KWP3 ETRIG3 PWM3 — V DDX PERP/PPSP Disabled

21 PP4 KWP4 PWM4 — — V DDX PERP/PPSP Disabled

22 PP5 KWP5 PWM5 — — V DDX PERP/PPSP Disabled

23 PP6 KWP6 — — V DDX PERP/PPSP Disabled

24 PP7 KWP7 — — V DDX PERP/PPSP Disabled

25 PT7 — — — — V DDX PERT/PPST Disabled

26 PT6 — — — — V DDX PERT/PPST Disabled

27 PT5 IOC5 — — — V DDX PERT/PPST Disabled

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28 PT4 IOC4 — — — V DDX PERT/PPST Disabled

29 PT3 IOC3 — — — V DDX PERT/PPST Disabled

30 PT2 IOC2 — — — V DDX PERT/PPST Disabled

31 PT1 IOC1 IRQ — — V DDX PERT/PPST Disabled

32 PT0 IOC0 XIRQ — — V DDX PERT/PPST Disabled

33 PAD0 KWAD0 AN0 — — V DDA PER1AD/PPS1AD Disabled

34 PAD8 KWAD8 AN8 — — V DDA PER0AD/PPS0AD Disabled

35 PAD1 KWAD1 AN1 — — V DDA PER1AD/PPS1AD Disabled

36 PAD9 KWAD9 AN9 ACMPO — V DDA PER0ADPPS0AD Disabled

37 PAD2 KWAD2 AN2 — — V DDA PER1AD/PPS1AD Disabled

38 PAD10 KWAD10 AN10 ACMPP — V DDA PER0AD/PPS0AD Disabled

39 PAD3 KWAD3 AN3 — — V DDA PER1AD/PPS1AD Disabled

40 PAD11 KWAD11 AN11 ACMPM — V DDA PER0AD/PPS0AD Disabled

41 PAD4 KWAD4 AN4 — — V DDA PER1AD/PPS1AD Disabled

42 PAD12 KWAD12 — — — V DDA PER0AD/PPS0AD Disabled

43 PAD5 KWAD5 AN5 — — V DDA PER1AD/PPS1AD Disabled

44 PAD13 KWAD13 — — — V DDA PER0AD/PPS0AD Disabled

45 PAD6 KWAD6 AN6 — — V DDA PER1AD/PPS1AD Disabled

46 PAD14 KWAD14 — — V DDA PER0AD/PPS0AD Disabled

47 PAD7 KWAD7 AN7 — — V DDA PER1AD/PPS1AD Disabled

48 PAD15 KWAD15 — — V DDA PER0AD/PPS0AD Disabled

52 PS0 RXD0 — — — V

53 PS1 TXD0 — — — V DDX PERS/PPSS Up

54 PS2 RXD1 — — — V DDX PERS/PPSS Up

55 PS3 TXD1 — — — V DDX PERS/PPSS Up

56 PS4 MISO0 — — — V DDX PERS/PPSS Up

Table 1-13. 64-Pin LQFP Pinout for S12GN48 Function <----lowest-----PRIORITY -----highest----> Power Supply Internal Pull Resistor Package Pin Pin 2nd Func. 3rd Func. 4th Func 5th Func CTRL Reset State

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57 PS5 MOSI0 — — — V DDX PERS/PPSS Up

58 PS6 SCK0 — — — V DDX PERS/PPSS Up

59 PS7 API_EXTCLK ECLK SS0 — V DDX PERS/PPSS Up

60 PM0 — — — — V DDX PERM/PPSM Disabled

61 PM1 — — — — V DDX PERM/PPSM Disabled

62 PM2 — — — — V DDX PERM/PPSM Disabled

63 PM3 — — — — V DDX PERM/PPSM Disabled

64 PJ7 KWJ7 — — — V DDX PERJ/PPSJ Up

1 The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled Table 1-13. 64-Pin LQFP Pinout for S12GN48 Function <----lowest-----PRIORITY -----highest----> Power Supply Internal Pull Resistor Package Pin Pin 2nd Func. 3rd Func. 4th Func 5th Func CTRL Reset State

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1.8.3 S12G48 and S12G64

1.8.3.1 Pinout 32-Pin LQFP

Figure 1-9. 32-Pin LQFP Pinout for S12G48 and S12G64 Table 1-14. 32-Pin LQFP Pinout for S12G48 and S12G64 Function <----lowest-----PRIORITY -----highest----> Power Supply Internal Pull Resistor Package Pin Pin 2nd Func. 3rd Func. 4th Func 5th Func CTRL Reset State PWM0/API_EXTCLK/ETRIG0/KWP0/PP0 PWM1/ECLKX2/ETRIG1/KWP1/PP1 PWM2/ETRIG2/KWP2/PP2 PWM3/ETRIG3/KWP3/PP3 IOC3/PT3 IOC2/PT2 IRQ/IOC1/PT1 XIRQ/IOC0/PT0 RESET VRH/VDDXRA VSSXA EXTAL/PE0 VSS XTAL/PE1 TEST BKGD PM1/TXD1/TXCAN PM0/RXD1/RXCAN PS7/API_EXTCLK/ECLK/PWM5/ SS0 PS6/IOC5/SCK0 PS5/IOC4/MOSI0 PS4/PWM4/MISO0 PS1/TXD0 PS0/RXD0

Device Overview MC9S12G-Family MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 65 7 TEST — — — — N.A. RESET pin Down Table 1-14. 32-Pin LQFP Pinout for S12G48 and S12G64 Function <----lowest-----PRIORITY -----highest----> Power Supply Internal Pull Resistor Package Pin Pin 2nd Func. 3rd Func. 4th Func 5th Func CTRL Reset State

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1.8.3.2 Pinout 48-Pin LQFP

Figure 1-10. 48-Pin LQFP Pinout for S12G48 and S12G64

31 PM0 RXD1 RXCAN — — V DDX PERM/PPSM Disabled

32 PM1 TXD1 TXCAN — — V DDX PERM/PPSM Disabled

1 The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled Table 1-14. 32-Pin LQFP Pinout for S12G48 and S12G64 Function <----lowest-----PRIORITY -----highest----> Power Supply Internal Pull Resistor Package Pin Pin 2nd Func. 3rd Func. 4th Func 5th Func CTRL Reset State S12G48 S12G64 48-Pin LQFP PAD7/KWAD7/AN7 PAD6/KWAD6/AN6 PAD5/KWAD5/AN5 PAD4/KWAD4/AN4 PAD11/KWAD11/AN11/ACMPM PAD3/KWAD3/AN3 PAD10/KWAD10/AN10/ACMPP PAD2/KWAD2/AN2 PAD9/KWAD9/AN9/ACMPO PAD1/KWAD1/AN1 PAD8/KWAD8/AN8 PAD0/KWAD0/AN0 PWM0/API_EXTCLK/ETRIG0/KWP0/PP0 PWM1/ECLKX2/ETRIG1/KWP1/PP1 PWM2/ETRIG2/KWP2/PP2 PWM3/ETRIG3/KWP3/PP3 PWM4/KWP4/PP4 PWM5/KWP5/PP5 IOC5/PT5 IOC4/PT4 IOC3/PT3 IOC2/PT2 IRQ/IOC1/PT1 XIRQ/IOC0/PT0 RESET VDDXR VSSX EXTAL/PE0 VSS XTAL/PE1 TEST MISO1/KWJ0/PJ0 MOSI1/KWJ1/PJ1 SCK1/KWJ2/PJ2 SS1/KWJ3/PJ3 BKGD PM1/TXCAN PM0/RXCAN PS7/API_EXTCLK/ECLK/ SS0 PS6/SCK0 PS5/MOSI0 PS4/MISO0 PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 VSSA VDDA/VRH

Device Overview MC9S12G-Family MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 67 Table 1-15. 48-Pin LQFP Pinout for S12G48 and S12G64 Function <----lowest-----PRIORITY -----highest----> Power Supply Internal Pull Resistor Package Pin Pin 2nd Func. 3rd Func. 4th Func 5th Func CTRL Reset State 7 TEST — — — — N.A. RESET pin Down

8 PJ0 KWJ0 — MISO1 — V DDX PERJ/PPSJ Up

9 PJ1 KWJ1 — MOSI1 — V DDX PERJ/PPSJ Up

10 PJ2 KWJ2 — SCK1 — V DDX PERJ/PPSJ Up

11 PJ3 KWJ3 — SS1 — V DDX PERJ/PPSJ Up

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47 PM0 RXCAN — — — V DDX PERM/PPSM Disabled

48 PM1 TXCAN — — — V DDX PERM/PPSM Disabled

1 The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled Table 1-15. 48-Pin LQFP Pinout for S12G48 and S12G64 Function <----lowest-----PRIORITY -----highest----> Power Supply Internal Pull Resistor Package Pin Pin 2nd Func. 3rd Func. 4th Func 5th Func CTRL Reset State

Device Overview MC9S12G-Family MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 69

1.8.3.3 Pinout 64-Pin LQFP

Figure 1-11. 64-Pin LQFP Pinout for S12G48 and S12G64 S12G48 S12G64 64-pin LQFP PWM0/API_EXTCLK/ETRIG0/KWP0/PP0 PWM1/ECLKX2/ETRIG1/KWP1/PP1 PWM2/ETRIG2/KWP2/PP2 PWM3/ETRIG3/KWP3/PP3 PWM4/KWP4/PP4 PWM5/KWP5/PP5 KWP6/PP6 KWP7/PP7 PT7 PT6 IOC5/PT5 IOC4/PT4 IOC3/PT3 IOC2/PT2 IRQ/IOC1/PT1 XIRQ/IOC0/PT0 KWJ6/PJ6 KWJ5/PJ5 KWJ4/PJ4 RESET VDDX VDDR VSSX EXTAL/PE0 VSS XTAL/PE1 TEST MISO1/KWJ0/PJ0 MOSI1/KWJ1/PJ1 SCK1/KWJ2/PJ2 SS1/KWJ3/PJ3 BKGD PJ7/KWJ7 PM3 PM2 PM1/TXCAN PM0/RXCAN PS7/API_EXTCLK/ECLK/ SS0 PS6/SCK0 PS5/MOSI0 PS4/MISO0 PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 VSSA VDDA VRH PAD15/KWAD15 PAD7/KWAD7/AN7 PAD14/KWAD14 PAD6/KWAD6/AN6 PAD13/KWAD13 PAD5/KWAD5/AN5 PAD12/KWAD12 PAD4/KWAD4/AN4 PAD11/KWAD11/AN11/ACMPM PAD3/KWAD3/AN3 PAD10/KWAD10/AN10/ACMPP PAD2/KWAD2/AN2 PAD9/KWAD9/AN9/ACMPO PAD1/KWAD1/AN1 PAD8/KWAD8/AN8 PAD0/KWAD0/AN0

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Table 1-16. 64-Pin LQFP Pinout for S12G48 and S12G64 Function <----lowest-----PRIORITY -----highest----> Power Supply Internal Pull Resistor Package Pin Pin 2nd Func. 3rd Func. 4th Func 5th Func CTRL Reset State 11 TEST — — — — N.A. RESET pin Down

23 PP6 KWP6 — — — V DDX PERP/PPSP Disabled

24 PP7 KWP7 — — — V DDX PERP/PPSP Disabled

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38 PAD10 KWAD10 AN10 ACMPP V DDA PER0AD/PPS0AD Disabled

40 PAD11 KWAD11 AN11 ACMPM V DDA PER0AD/PPS0AD Disabled

46 PAD14 KWAD14 — — — V DDA PER0AD/PPS0AD Disabled

48 PAD15 KWAD15 — — — V DDA PER0AD/PPS0AD Disabled

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60 PM0 RXCAN — — — V DDX PERM/PPSM Disabled

61 PM1 TXCAN — — — V DDX PERM/PPSM Disabled

1 The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled Table 1-16. 64-Pin LQFP Pinout for S12G48 and S12G64 Function <----lowest-----PRIORITY -----highest----> Power Supply Internal Pull Resistor Package Pin Pin 2nd Func. 3rd Func. 4th Func 5th Func CTRL Reset State

Device Overview MC9S12G-Family MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 73

1.8.4 S12G96 and S12G128

1.8.4.1 Pinout 48-Pin LQFP

Figure 1-12. 48-Pin LQFP Pinout for S12G96 and S12G128 Table 1-17. 48-Pin LQFP Pinout for S12G96 and S12G128 Function <----lowest-----PRIORITY -----highest----> Power Supply Internal Pull Resistor Package Pin Pin 2nd Func. 3rd Func. 4th Func 5th Func CTRL Reset State PWM0/API_EXTCLK/ETRIG0/KWP0/PP0 PWM1/ECLKX2/ETRIG1/KWP1/PP1 PWM2/ETRIG2/KWP2/PP2 PWM3/ETRIG3/KWP3/PP3 PWM4/KWP4/PP4 PWM5/KWP5/PP5 IOC5/PT5 IOC4/PT4 IOC3/PT3 IOC2/PT2 IRQ/IOC1/PT1 XIRQ/IOC0/PT0 RESET VDDXR VSSX EXTAL/PE0 VSS XTAL/PE1 TEST MISO1/PWM6/KWJ0/PJ0 MOSI1/IOC6/KWJ1/PJ1 SCK1/IOC7/KWJ2/PJ2 SS1/PWM7/KWJ3/PJ3 BKGD PM1/TXD2/TXCAN PM0/RXD2/RXCAN PS7/API_EXTCLK/ECLK/ SS0 PS6/SCK0 PS5/MOSI0 PS4/MISO0 PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 VSSA VDDA/VRH

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6 PE1 1 XTAL — — — V DDX PUCR/PDPEE Down

7 TEST — — — — N.A. RESET pin Down

8 PJ0 KWJ0 PWM6 MISO1 — V DDX PERJ/PPSJ Up

9 PJ1 KWJ1 IOC6 MOSI1 — V DDX PERJ/PPSJ Up

10 PJ2 KWJ2 IOC7 SCK1 — V DDX PERJ/PPSJ Up

11 PJ3 KWJ3 PWM7 SS1 — V DDX PERJ/PPSJ Up

28 PAD9 KWAD9 AN9 — V DDA PER0AD/PPS0AD Disabled

30 PAD10 KWAD10 AN10 V DDA PER0AD/PPS0AD Disabled

Table 1-17. 48-Pin LQFP Pinout for S12G96 and S12G128 Function <----lowest-----PRIORITY -----highest----> Power Supply Internal Pull Resistor Package Pin Pin 2nd Func. 3rd Func. 4th Func 5th Func CTRL Reset State

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32 PAD11 KWAD11 AN11 — — V DDA PER0AD/PPS0AD Disabled

47 PM0 RXD2 RXCAN — — V DDX PERM/PPSM Disabled

48 PM1 TXD2 TXCAN — — V DDX PERM/PPSM Disabled

1 The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled Table 1-17. 48-Pin LQFP Pinout for S12G96 and S12G128 Function <----lowest-----PRIORITY -----highest----> Power Supply Internal Pull Resistor Package Pin Pin 2nd Func. 3rd Func. 4th Func 5th Func CTRL Reset State

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76 Freescale Semiconductor

1.8.4.2 Pinout 64-Pin LQFP

Figure 1-13. 64-Pin LQFP Pinout for S12G96 and S12G128 S12G96 S12G128 64-Pin LQFP PWM0/API_EXTCLK/ETRIG0/KWP0/PP0 PWM1/ECLKX2/ETRIG1/KWP1/PP1 PWM2/ETRIG2/KWP2/PP2 PWM3/ETRIG3/KWP3/PP3 PWM4/KWP4/PP4 PWM5/KWP5/PP5 PWM6/KWP6/PP6 PWM7/KWP7/PP7 IOC7/PT7 IOC6/PT6 IOC5/PT5 IOC4/PT4 IOC3/PT3 IOC2/PT2 IRQ/IOC1/PT1 XIRQ/IOC0/PT0 SCK2/KWJ6/PJ6 MOSI2/KWJ5/PJ5 MISO2/KWJ4/PJ4 RESET VDDX VDDR VSSX EXTAL/PE0 VSS XTAL/PE1 TEST MISO1/KWJ0/PJ0 MOSI1/KWJ1/PJ1 SCK1/KWJ2/PJ2 SS1/KWJ3/PJ3 BKGD PJ7/KWJ7/SS2 PM3/TXD2 PM2/RXD2 PM1/TXCAN PM0/RXCAN PS7/API_EXTCLK/ECLK/ SS0 PS6/SCK0 PS5/MOSI0 PS4/MISO0 PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 VSSA VDDA VRH PAD15/KWAD15 PAD7/KWAD7/AN7 PAD14/KWAD14 PAD6/KWAD6/AN6 PAD13/KWAD13 PAD5/KWAD5/AN5 PAD12/KWAD12 PAD4/KWAD4/AN4 PAD11/KWAD11/AN11 PAD3/KWAD3/AN3 PAD10/KWAD10/AN10 PAD2/KWAD2/AN2 PAD9/KWAD9/AN9 PAD1/KWAD1/AN1 PAD8/KWAD8/AN8 PAD0/KWAD0/AN0

Device Overview MC9S12G-Family MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 77 Table 1-18. 64-Pin LQFP Pinout for S12G96 and S12G128 Function <----lowest-----PRIORITY -----highest----> Power Supply Internal Pull Resistor Package Pin Pin 2nd Func. 3rd Func. 4th Func 5th Func CTRL Reset State

1 PJ6 KWJ6 SCK2 — — V DDX PERJ/PPSJ Up

2 PJ5 KWJ5 MOSI2 — — V DDX PERJ/PPSJ Up

3 PJ4 KWJ4 MISO2 — — V DDX PERJ/PPSJ Up

11 TEST — — — — N.A. RESET pin Down

23 PP6 KWP6 PWM6 — — V DDX PERP/PPSP Disabled

24 PP7 KWP7 PWM7 — — V DDX PERP/PPSP Disabled

25 PT7 IOC7 — — — V DDX PERT/PPST Disabled

26 PT6 IOC6 — — — V DDX PERT/PPST Disabled

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78 Freescale Semiconductor

36 PAD9 KWAD9 AN9 — — V DDA PER0ADPPS0AD Disabled

38 PAD10 KWAD10 AN10 — — V DDA PER0AD/PPS0AD Disabled

40 PAD11 KWAD11 AN11 — — V DDA PER0AD/PPS0AD Disabled

42 PAD12 KWAD12 — — V DDA PER0AD/PPS0AD Disabled

44 PAD13 KWAD13 — — V DDA PER0AD/PPS0AD Disabled

Table 1-18. 64-Pin LQFP Pinout for S12G96 and S12G128 Function <----lowest-----PRIORITY -----highest----> Power Supply Internal Pull Resistor Package Pin Pin 2nd Func. 3rd Func. 4th Func 5th Func CTRL Reset State

Device Overview MC9S12G-Family MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 79

62 PM2 RXD2 — — — V DDX PERM/PPSM Disabled

63 PM3 TXD2 — — — V DDX PERM/PPSM Disabled

64 PJ7 KWJ7 SS2 — — V DDX PERJ/PPSJ Up

1 The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled Table 1-18. 64-Pin LQFP Pinout for S12G96 and S12G128 Function <----lowest-----PRIORITY -----highest----> Power Supply Internal Pull Resistor Package Pin Pin 2nd Func. 3rd Func. 4th Func 5th Func CTRL Reset State

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80 Freescale Semiconductor

1.8.4.3 Pinout 100-Pin LQFP

Figure 1-14. 100-Pin LQFP Pinout for S12G96 and S12G128 VRH PC7 PC6 PC5 PC4 PAD15/KWAD15/ PAD7/KWAD7/AN7 PAD14/KWAD14 PAD6/KWAD6/AN6 PAD13/KWAD13 PAD5/KWAD5/AN5 PAD12/KWAD12 PAD4/KWAD4/AN4 PAD11/KWAD11/AN11 PAD3/KWAD3/AN3 PAD10/KWAD10/AN10 PAD2/KWAD2/AN2 PAD9/KWAD9/AN9 PAD1/KWAD1/AN1 PAD8/KWAD8/AN8 PAD0/KWAD0/AN0 PC3 PC2 PC1 PC0 API_EXTCLK/PB1 ECLKX2/PB2 PB3 PWM0/ETRIG0/KWP0/PP0 PWM1/ETRIG1/KWP1/PP1 PWM2/ETRIG2/KWP2/PP2 PWM3/ETRIG3/KWP3/PP3 PWM4/KWP4/PP4 PWM5/KWP5/PP5 PWM6/KWP6/PP6 PWM7/KWP7/PP7 VDDX3 VSSX3 IOC7/PT7 IOC6/PT6 IOC5/PT5 IOC4/PT4 IOC3/PT3 IOC2/PT2 IOC1/PT1 IOC0/PT0 IRQ/PB4 XIRQ/PB5 PB6 PB7 100 SCK2/KWJ6/PJ6 MOSI2/KWJ5/PJ5 MISO2/KWJ4/PJ4 PA0 PA1 PA2 PA3 RESET VDDX1 VDDR VSSX1 EXTAL/PE0 VSS XTAL/PE1 TEST PA4 PA5 PA6 PA7 MISO1/KWJ0/PJ0 MOSI1/KWJ1/PJ1 SCK1/KWJ2/PJ2 SS1/KWJ3/PJ3 BKGD ECLK/PB0 PJ7/KWJ7/SS2 PM3/TXD2 PM2/RXD2 PD7 PD6 PD5 PD4 PM1/TXCAN PM0/RXCAN VDDX2 VSSX2 PS7/API_EXTCLK/ SS0 PS6/SCK0 PS5/MOSI0 PS4/MISO0 PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 PD3 PD2 PD1 PD0 VSSA VDDA S12G96 S12G128 100-Pin LQFP

Device Overview MC9S12G-Family MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 81 Table 1-19. 100-Pin LQFP Pinout for S12G96 and S12G128 Function <----lowest-----PRIORITY -----highest----> Power Supply Internal Pull Resistor Package Pin Pin 2nd Func. 3rd Func. 4th Func. CTRL Reset State

1 PJ6 KWJ6 SCK2 — V DDX PERJ/PPSJ Up

2 PJ5 KWJ5 MOSI2 — V DDX PERJ/PPSJ Up

3 PJ4 KWJ4 MISO2 — V DDX PERJ/PPSJ Up

4 P A 0 ——— V DDX PUCR/PUPAE Disabled

5 P A 1 ——— V DDX PUCR/PUPAE Disabled

6 P A 2 ——— V DDX PUCR/PUPAE Disabled

7 P A 3 ——— V DDX PUCR/PUPAE Disabled

8 RESET — — — V DDX PULLUP

12 PE0

1 EXTAL — — V DDX PUCR/PDPEE Down

14 PE1

1 XTAL — — V DDX PUCR/PDPEE Down

15 TEST — — — N.A. RESET pin Down 1 6P A 4 ——— V DDX PUCR/PUPAE Disabled 1 7P A 5 ——— V DDX PUCR/PUPAE Disabled 1 8P A 6 ——— V DDX PUCR/PUPAE Disabled 1 9P A 7 ——— V DDX PUCR/PUPAE Disabled

20 PJ0 KWJ0 MISO1 — V DDX PERJ/PPSJ Up

21 PJ1 KWJ1 MOSI1 — V DDX PERJ/PPSJ Up

22 PJ2 KWJ2 SCK1 — V DDX PERJ/PPSJ Up

23 PJ3 KWJ3 SS1 — V DDX PERJ/PPSJ Up

24 BKGD MODC — — V DDX PUCR/BKPUE Up

25 PB0 ECLK — — V DDX PUCR/PUPBE Disabled

26 PB1 API_EXTCLK —— V DDX PUCR/PUPBE Disabled

27 PB2 ECLKX2 — — V DDX PUCR/PUPBE Disabled

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28 PB3 — — — V DDX PUCR/PUPBE Disabled

29 PP0 KWP0 ETRIG0 PWM0 V DDX PERP/PPSP Disabled

30 PP1 KWP1 ETRIG1 PWM1 V DDX PERP/PPSP Disabled

31 PP2 KWP2 ETRIG2 PWM2 V DDX PERP/PPSP Disabled

32 PP3 KWP3 ETRIG3 PWM3 V DDX PERP/PPSP Disabled

33 PP4 KWP4 PWM4 — V DDX PERP/PPSP Disabled

34 PP5 KWP5 PWM5 — V DDX PERP/PPSP Disabled

35 PP6 KWP6 PWM6 — V DDX PERP/PPSP Disabled

36 PP7 KWP7 PWM7 — V DDX PERP/PPSP Disabled

39 PT7 IOC7 — — V

40 PT6 IOC6 — — V DDX PERT/PPST Disabled

41 PT5 IOC5 — — V DDX PERT/PPST Disabled

42 PT4 IOC4 — — V DDX PERT/PPST Disabled

43 PT3 IOC3 — — V DDX PERT/PPST Disabled

44 PT2 IOC2 — — V DDX PERT/PPST Disabled

45 PT1 IOC1 — — V DDX PERT/PPST Disabled

46 PT0 IOC0 — — V DDX PERT/PPST Disabled

47 PB4 IRQ — — V DDX PUCR/PUPBE Disabled

48 PB5 XIRQ — — V DDX PUCR/PUPBE Disabled

49 PB6 — — — V DDX PUCR/PUPBE Disabled

50 PB7 — — — V DDX PUCR/PUPBE Disabled

51 PC0 — — — V DDA PUCR/PUPCE Disabled

52 PC1 — — — V DDA PUCR/PUPCE Disabled

53 PC2 — — — V DDA PUCR/PUPCE Disabled

54 PC3 — — — V DDA PUCR/PUPCE Disabled

55 PAD0 KWAD0 AN0 — V DDA PER1AD/PPS1AD Disabled

56 PAD8 KWAD8 AN8 — V DDA PER0AD/PPS0AD Disabled

Table 1-19. 100-Pin LQFP Pinout for S12G96 and S12G128 Function <----lowest-----PRIORITY -----highest----> Power Supply Internal Pull Resistor Package Pin Pin 2nd Func. 3rd Func. 4th Func. CTRL Reset State

Device Overview MC9S12G-Family MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 83

57 PAD1 KWAD1 AN1 — V DDA PER1AD/PPS1AD Disabled

58 PAD9 KWAD9 AN9 — V DDA PER0AD/PPS0AD Disabled

59 PAD2 KWAD2 AN2 — V DDA PER1AD/PPS1AD Disabled

60 PAD10 KWAD10 AN10 — V DDA PER0AD/PPS0AD Disabled

61 PAD3 KWAD3 AN3 — V DDA PER1AD/PPS1AD Disabled

62 PAD11 KWAD11 AN11 — V DDA PER0AD/PPS0AD Disabled

63 PAD4 KWAD4 AN4 — V DDA PER1AD/PPS1AD Disabled

64 PAD12 KWAD12 — — V DDA PER0AD/PPS0AD Disabled

65 PAD5 KWAD5 AN5 — V DDA PER1AD/PPS1AD Disabled

66 PAD13 KWAD13 — — V DDA PER0AD/PPS0AD Disabled

67 PAD6 KWAD6 AN6 — V DDA PER1AD/PPS1AD Disabled

68 PAD14 KWAD14 — — V DDA PER0AD/PPS0AD Disabled

69 PAD7 KWAD7 AN7 — V DDA PER1AD/PPS1AD Disabled

70 PAD15 KWAD15 — — V DDA PER0AD/PPS0AD Disabled

71 PC4 — — — V DDA PUCR/PUPCE Disabled

72 PC5 — — V DDA PUCR/PUPCE Disabled

73 PC6 — — V DDA PUCR/PUPCE Disabled

74 PC7 — — V DDA PUCR/PUPCE Disabled

78 PD0 — — — V

79 PD1 — — — V DDX PUCR/PUPDE Disabled

80 PD2 — — — V DDX PUCR/PUPDE Disabled

81 PD3 — — — V DDX PUCR/PUPDE Disabled

82 PS0 RXD0 — — V DDX PERS/PPSS Up

83 PS1 TXD0 — — V DDX PERS/PPSS Up

84 PS2 RXD1 — — V DDX PERS/PPSS Up

85 PS3 TXD1 — — V DDX PERS/PPSS Up

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84 Freescale Semiconductor

86 PS4 MISO0 — — V DDX PERS/PPSS Up

87 PS5 MOSI0 — — V DDX PERS/PPSS Up

88 PS6 SCK0 — — V DDX PERS/PPSS Up

89 PS7 API_EXTCLK SS0 — V DDX PERS/PPSS Up

92 PM0 RXCAN — — V

93 PM1 TXCAN — — V DDX PERM/PPSM Disabled

94 PD4 — — — V DDX PUCR/PUPDE Disabled

95 PD5 — — — V DDX PUCR/PUPDE Disabled

96 PD6 — — — V DDX PUCR/PUPDE Disabled

97 PD7 — — — V DDX PUCR/PUPDE Disabled

98 PM2 RXD2 — — V DDX PERM/PPSM Disabled

99 PM3 TXD2 — — V DDX PERM/PPSM Disabled

100 PJ7 KWJ7 SS2 — V DDX PERJ/PPSJ Up

1 The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled Table 1-19. 100-Pin LQFP Pinout for S12G96 and S12G128 Function <----lowest-----PRIORITY -----highest----> Power Supply Internal Pull Resistor Package Pin Pin 2nd Func. 3rd Func. 4th Func. CTRL Reset State

Device Overview MC9S12G-Family MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 85

1.8.5 S12G192 and S12G240

1.8.5.1 Pinout 48-Pin LQFP

Figure 1-15. 48-Pin LQFP Pinout for S12G192 and S12G240 Table 1-20. 48-Pin LQFP Pinout for S12G192 and S12G240 Function <----lowest-----PRIORITY -----highest----> Power Supply Internal Pull Resistor Package Pin Pin 2nd Func. 3rd Func. 4th Func 5th Func CTRL Reset State PWM0/API_EXTCLK/ETRIG0/KWP0/PP0 PWM1/ECLKX2/ETRIG1/KWP1/PP1 PWM2/ETRIG2/KWP2/PP2 PWM3/ETRIG3/KWP3/PP3 PWM4/KWP4/PP4 PWM5/KWP5/PP5 IOC5/PT5 IOC4/PT4 IOC3/PT3 IOC2/PT2 IRQ/IOC1/PT1 XIRQ/IOC0/PT0 RESET VDDXR VSSX EXTAL/PE0 VSS XTAL/PE1 TEST MISO1/PWM6/KWJ0/PJ0 MOSI1/IOC6/KWJ1/PJ1 SCK1/IOC7/KWJ2/PJ2 SS1/PWM7/KWJ3/PJ3 BKGD PM1/TXD2/TXCAN PM0/RXD2/RXCAN PS7/API_EXTCLK/ECLK/ SS0 PS6/SCK0 PS5/MOSI0 PS4/MISO0 PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 VSSA VDDA/VRH

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86 Freescale Semiconductor

7 TEST — — — — N.A. RESET pin Down

28 PAD9 KWAD9 AN9 — — V DDA PER0AD/PPS0AD Disabled

30 PAD10 KWAD10 AN10 — — V DDA PER0AD/PPS0AD Disabled

Table 1-20. 48-Pin LQFP Pinout for S12G192 and S12G240 Function <----lowest-----PRIORITY -----highest----> Power Supply Internal Pull Resistor Package Pin Pin 2nd Func. 3rd Func. 4th Func 5th Func CTRL Reset State

Device Overview MC9S12G-Family MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 87 1 The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled Table 1-20. 48-Pin LQFP Pinout for S12G192 and S12G240 Function <----lowest-----PRIORITY -----highest----> Power Supply Internal Pull Resistor Package Pin Pin 2nd Func. 3rd Func. 4th Func 5th Func CTRL Reset State

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88 Freescale Semiconductor

1.8.5.2 Pinout 64-Pin LQFP

Figure 1-16. 64-Pin LQFP Pinout for S12G192 and S12G240 S12G192 S12G240 64-Pin LQFP PWM0/API_EXTCLK/ETRIG0/KWP0/PP0 PWM1/ECLKX2/ETRIG1/KWP1/PP1 PWM2/ETRIG2/KWP2/PP2 PWM3/ETRIG3/KWP3/PP3 PWM4/KWP4/PP4 PWM5/KWP5/PP5 PWM6/KWP6/PP6 PWM7/KWP7/PP7 IOC7/PT7 IOC6/PT6 IOC5/PT5 IOC4/PT4 IOC3/PT3 IOC2/PT2 IRQ/IOC1/PT1 XIRQ/IOC0/PT0 SCK2/KWJ6/PJ6 MOSI2/KWJ5/PJ5 MISO2/KWJ4/PJ4 RESET VDDX VDDR VSSX EXTAL/PE0 VSS XTAL/PE1 TEST MISO1/KWJ0/PJ0 MOSI1/KWJ1/PJ1 SCK1/KWJ2/PJ2 SS1/KWJ3/PJ3 BKGD PJ7/KWJ7/SS2 PM3/TXD2 PM2/RXD2 PM1/TXCAN PM0/RXCAN PS7/API_EXTCLK/ECLK/ SS0 PS6/SCK0 PS5/MOSI0 PS4/MISO0 PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 VSSA VDDA VRH PAD15/KWAD15/AN15 PAD7/KWAD7/AN7 PAD14/KWAD14/AN14 PAD6/KWAD6/AN6 PAD13/KWAD13/AN13 PAD5/KWAD5/AN5 PAD12/KWAD12/AN12 PAD4/KWAD4/AN4 PAD11/KWAD11/AN11 PAD3/KWAD3/AN3 PAD10/KWAD10/AN10 PAD2/KWAD2/AN2 PAD9/KWAD9/AN9 PAD1/KWAD1/AN1 PAD8/KWAD8/AN8 PAD0/KWAD0/AN0

Device Overview MC9S12G-Family MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 89 Table 1-21. 64-Pin LQFP Pinout for S12G192 and S12G240 Function <----lowest-----PRIORITY -----highest----> Power Supply Internal Pull Resistor Package Pin Pin 2nd Func. 3rd Func. 4th Func 5th Func CTRL Reset State 11 TEST — — — — N.A. RESET pin Down

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90 Freescale Semiconductor

42 PAD12 KWAD12 AN12 — — V DDA PER0AD/PPS0AD Disabled

44 PAD13 KWAD13 AN13 — — V DDA PER0AD/PPS0AD Disabled

46 PAD14 KWAD14 AN14 — — V DDA PER0AD/PPS0AD Disabled

48 PAD15 KWAD15 AN15 — — V DDA PER0AD/PPS0AD Disabled

Table 1-21. 64-Pin LQFP Pinout for S12G192 and S12G240 Function <----lowest-----PRIORITY -----highest----> Power Supply Internal Pull Resistor Package Pin Pin 2nd Func. 3rd Func. 4th Func 5th Func CTRL Reset State

Device Overview MC9S12G-Family MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 91 1 The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled Table 1-21. 64-Pin LQFP Pinout for S12G192 and S12G240 Function <----lowest-----PRIORITY -----highest----> Power Supply Internal Pull Resistor Package Pin Pin 2nd Func. 3rd Func. 4th Func 5th Func CTRL Reset State

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92 Freescale Semiconductor

1.8.5.3 Pinout 100-Pin LQFP

Figure 1-17. 100-Pin LQFP Pinout for S12G192 and S12G240 VRH PC7 PC6 PC5 PC4 PAD15/KWAD15/AN15 PAD7/KWAD7/AN7 PAD14/KWAD14/AN14 PAD6/KWAD6/AN6 PAD13/KWAD13/AN13 PAD5/KWAD5/AN5 PAD12/KWAD12/AN12 PAD4/KWAD4/AN4 PAD11/KWAD11/AN11 PAD3/KWAD3/AN3 PAD10/KWAD10/AN10 PAD2/KWAD2/AN2 PAD9/KWAD9/AN9 PAD1/KWAD1/AN1 PAD8/KWAD8/AN8 PAD0/KWAD0/AN0 PC3 PC2 PC1 PC0 API_EXTCLK/PB1 ECLKX2/PB2 PB3 PWM0/ETRIG0/KWP0/PP0 PWM1/ETRIG1/KWP1/PP1 PWM2/ETRIG2/KWP2/PP2 PWM3/ETRIG3/KWP3/PP3 PWM4/KWP4/PP4 PWM5/KWP5/PP5 PWM6/KWP6/PP6 PWM7/KWP7/PP7 VDDX3 VSSX3 IOC7/PT7 IOC6/PT6 IOC5/PT5 IOC4/PT4 IOC3/PT3 IOC2/PT2 IOC1/PT1 IOC0/PT0 IRQ/PB4 XIRQ/PB5 PB6 PB7 100 SCK2/KWJ6/PJ6 MOSI2/KWJ5/PJ5 MISO2/KWJ4/PJ4 PA0 PA1 PA2 PA3 RESET VDDX1 VDDR VSSX1 EXTAL/PE0 VSS XTAL/PE1 TEST PA4 PA5 PA6 PA7 MISO1/KWJ0/PJ0 MOSI1/KWJ1/PJ1 SCK1/KWJ2/PJ2 SS1/KWJ3/PJ3 BKGD ECLK/PB0 PJ7/KWJ7/SS2 PM3/TXD2 PM2/RXD2 PD7 PD6 PD5 PD4 PM1/TXCAN PM0/RXCAN VDDX2 VSSX2 PS7/API_EXTCLK/ SS0 PS6/SCK0 PS5/MOSI0 PS4/MISO0 PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 PD3 PD2 PD1 PD0 VSSA VDDA S12G192 S12G240 100-Pin LQFP

Device Overview MC9S12G-Family MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 93 Table 1-22. 100-Pin LQFP Pinout for S12G192 and S12G240 Function <----lowest-----PRIORITY -----highest----> Power Supply Internal Pull Resistor Package Pin Pin 2nd Func. 3rd Func. 4th Func. CTRL Reset State 15 TEST — — — N.A. RESET pin Down 1 6P A 4 ——— V DDX PUCR/PUPAE Disabled 1 7P A 5 ——— V DDX PUCR/PUPAE Disabled 1 8P A 6 ——— V DDX PUCR/PUPAE Disabled 1 9P A 7 ——— V DDX PUCR/PUPAE Disabled

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94 Freescale Semiconductor

Table 1-22. 100-Pin LQFP Pinout for S12G192 and S12G240 Function <----lowest-----PRIORITY -----highest----> Power Supply Internal Pull Resistor Package Pin Pin 2nd Func. 3rd Func. 4th Func. CTRL Reset State

Device Overview MC9S12G-Family MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 95

64 PAD12 KWAD12 AN12 — V DDA PER0AD/PPS0AD Disabled

66 PAD13 KWAD13 AN13 — V DDA PER0AD/PPS0AD Disabled

68 PAD14 KWAD14 AN14 — V DDA PER0AD/PPS0AD Disabled

70 PAD15 KWAD15 AN15 — V DDA PER0AD/PPS0AD Disabled

72 PC5 — — — V DDA PUCR/PUPCE Disabled

73 PC6 — — — V DDA PUCR/PUPCE Disabled

74 PC7 — — — V DDA PUCR/PUPCE Disabled

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1 The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled Table 1-22. 100-Pin LQFP Pinout for S12G192 and S12G240 Function <----lowest-----PRIORITY -----highest----> Power Supply Internal Pull Resistor Package Pin Pin 2nd Func. 3rd Func. 4th Func. CTRL Reset State

Device Overview MC9S12G-Family MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 97

1.8.6 S12GA192 and S12GA240

1.8.6.1 Pinout 48-Pin LQFP

Figure 1-18. 48-Pin LQFP Pinout for S12GA192 and S12GA240 Table 1-23. 48-Pin LQFP Pinout for S12GA192 and S12GA240 Function <----lowest-----PRIORITY -----highest----> Power Supply Internal Pull Resistor Package Pin Pin 2nd Func. 3rd Func. 4th Func 5th Func CTRL Reset State PAD11/KWAD11/AN11/DACU0/AMP0 PAD3/KWAD3/AN3 PAD10/KWAD10/AN10/DACU1/AMP1 PAD2/KWAD2/AN2 PAD9/KWAD9/AN9 PAD1/KWAD1/AN1 PAD8/KWAD8/AN8 PAD0/KWAD0/AN0 PWM0/API_EXTCLK/ETRIG0/KWP0/PP0 PWM1/ECLKX2/ETRIG1/KWP1/PP1 PWM2/ETRIG2/KWP2/PP2 PWM3/ETRIG3/KWP3/PP3 PWM4/KWP4/PP4 PWM5/KWP5/PP5 IOC5/PT5 IOC4/PT4 IOC3/PT3 IOC2/PT2 IRQ/IOC1/PT1 XIRQ/IOC0/PT0 RESET VDDXR VSSX EXTAL/PE0 VSS XTAL/PE1 TEST MISO1/PWM6/KWJ0/PJ0 MOSI1/IOC6/KWJ1/PJ1 SCK1/IOC7/KWJ2/PJ2 SS1/PWM7/KWJ3/PJ3 BKGD PM1/TXD2/TXCAN PM0/RXD2/RXCAN PS7/API_EXTCLK/ECLK/ SS0 PS6/SCK0 PS5/MOSI0 PS4/MISO0 PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 VSSA VDDA/VRH

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7 TEST — — — — N.A. RESET pin Down

30 PAD10 KWAD10 AN10 DACU1 AMP1 V DDA PER0AD/PPS0AD Disabled

Table 1-23. 48-Pin LQFP Pinout for S12GA192 and S12GA240 Function <----lowest-----PRIORITY -----highest----> Power Supply Internal Pull Resistor Package Pin Pin 2nd Func. 3rd Func. 4th Func 5th Func CTRL Reset State

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32 PAD11 KWAD11 AN11 DACU0 AMP0 V DDA PER0AD/PPS0AD Disabled

1 The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled Table 1-23. 48-Pin LQFP Pinout for S12GA192 and S12GA240 Function <----lowest-----PRIORITY -----highest----> Power Supply Internal Pull Resistor Package Pin Pin 2nd Func. 3rd Func. 4th Func 5th Func CTRL Reset State

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1.8.6.2 Pinout 64-Pin LQFP

Figure 1-19. 64-Pin LQFP Pinout for S12GA192 and S12GA240 S12GA192 S12GA240 64-Pin LQFP PWM0/API_EXTCLK/ETRIG0/KWP0/PP0 PWM1/ECLKX2/ETRIG1/KWP1/PP1 PWM2/ETRIG2/KWP2/PP2 PWM3/ETRIG3/KWP3/PP3 PWM4/KWP4/PP4 PWM5/KWP5/PP5 PWM6/KWP6/PP6 PWM7/KWP7/PP7 IOC7/PT7 IOC6/PT6 IOC5/PT5 IOC4/PT4 IOC3/PT3 IOC2/PT2 IRQ/IOC1/PT1 XIRQ/IOC0/PT0 SCK2/KWJ6/PJ6 MOSI2/KWJ5/PJ5 MISO2/KWJ4/PJ4 RESET VDDX VDDR VSSX EXTAL/PE0 VSS XTAL/PE1 TEST MISO1/KWJ0/PJ0 MOSI1/KWJ1/PJ1 SCK1/KWJ2/PJ2 SS1/KWJ3/PJ3 BKGD PJ7/KWJ7/SS2 PM3/TXD2 PM2/RXD2 PM1/TXCAN PM0/RXCAN PS7/API_EXTCLK/ECLK/ SS0 PS6/SCK0 PS5/MOSI0 PS4/MISO0 PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 VSSA VDDA VRH PAD15/KWAD15/AN15/DACU0 PAD7/KWAD7/AN7 PAD14/KWAD14/AN14/AMPP0 PAD6/KWAD6/AN6 PAD13/KWAD13/AN13/AMPM0 PAD5/KWAD5/AN5 PAD12/KWAD12/AN12 PAD4/KWAD4/AN4 PAD11/KWAD11/AN11/AMP0 PAD3/KWAD3/AN3 PAD10/KWAD10/AN10/DACU1/AMP1 PAD2/KWAD2/AN2 PAD9/KWAD9/AN9 PAD1/KWAD1/AN1 PAD8/KWAD8/AN8 PAD0/KWAD0/AN0

Device Overview MC9S12G-Family MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 101 Table 1-24. 64-Pin LQFP Pinout for S12GA192 and S12GA240 Function <----lowest-----PRIORITY -----highest----> Power Supply Internal Pull Resistor Package Pin Pin 2nd Func. 3rd Func. 4th Func 5th Func CTRL Reset State 11 TEST — — — — N.A. RESET pin Down

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36 PAD9 KWAD9 AN9 — V DDA PER0ADPPS0AD Disabled

38 PAD10 KWAD10 AN10 DACU1 AMP1 V DDA PER0AD/PPS0AD Disabled

40 PAD11 KWAD11 AN11 AMP0 — V DDA PER0AD/PPS0AD Disabled

44 PAD13 KWAD13 AN13 AMPM0 — V DDA PER0AD/PPS0AD Disabled

46 PAD14 KWAD14 AN14 AMPP0 — V DDA PER0AD/PPS0AD Disabled

48 PAD15 KWAD15 AN15 DACU0 — V DDA PER0AD/PPS0AD Disabled

Table 1-24. 64-Pin LQFP Pinout for S12GA192 and S12GA240 Function <----lowest-----PRIORITY -----highest----> Power Supply Internal Pull Resistor Package Pin Pin 2nd Func. 3rd Func. 4th Func 5th Func CTRL Reset State

Device Overview MC9S12G-Family MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 103 1 The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled Table 1-24. 64-Pin LQFP Pinout for S12GA192 and S12GA240 Function <----lowest-----PRIORITY -----highest----> Power Supply Internal Pull Resistor Package Pin Pin 2nd Func. 3rd Func. 4th Func 5th Func CTRL Reset State

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1.8.6.3 Pinout 100-Pin LQFP

Figure 1-20. 100-Pin LQFP Pinout for S12GA192 and S12GA240 VRH PC7/DACU1 PC6/AMPP1 PC5/AMPM1 PC4 PAD15/KWAD15/AN15/DACU0 PAD7/KWAD7/AN7 PAD14/KWAD14/AN14/AMPP0 PAD6/KWAD6/AN6 PAD13/KWAD13/AN13/AMPM0 PAD5/KWAD5/AN5 PAD12/KWAD12/AN12 PAD4/KWAD4/AN4 PAD11/KWAD11/AN11/AMP0 PAD3/KWAD3/AN3 PAD10/KWAD10/AN10/AMP1 PAD2/KWAD2/AN2 PAD9/KWAD9/AN9 PAD1/KWAD1/AN1 PAD8/KWAD8/AN8 PAD0/KWAD0/AN0 PC3 PC2 PC1 PC0 API_EXTCLK/PB1 ECLKX2/PB2 PB3 PWM0/ETRIG0/KWP0/PP0 PWM1/ETRIG1/KWP1/PP1 PWM2/ETRIG2/KWP2/PP2 PWM3/ETRIG3/KWP3/PP3 PWM4/KWP4/PP4 PWM5/KWP5/PP5 PWM6/KWP6/PP6 PWM7/KWP7/PP7 VDDX3 VSSX3 IOC7/PT7 IOC6/PT6 IOC5/PT5 IOC4/PT4 IOC3/PT3 IOC2/PT2 IOC1/PT1 IOC0/PT0 IRQ/PB4 XIRQ/PB5 PB6 PB7 100 SCK2/KWJ6/PJ6 MOSI2/KWJ5/PJ5 MISO2/KWJ4/PJ4 PA0 PA1 PA2 PA3 RESET VDDX1 VDDR VSSX1 EXTAL/PE0 VSS XTAL/PE1 TEST PA4 PA5 PA6 PA7 MISO1/KWJ0/PJ0 MOSI1/KWJ1/PJ1 SCK1/KWJ2/PJ2 SS1/KWJ3/PJ3 BKGD ECLK/PB0 PJ7/KWJ7/SS2 PM3/TXD2 PM2/RXD2 PD7 PD6 PD5 PD4 PM1/TXCAN PM0/RXCAN VDDX2 VSSX2 PS7/API_EXTCLK/ SS0 PS6/SCK0 PS5/MOSI0 PS4/MISO0 PS3/TXD1 PS2/RXD1 PS1/TXD0 PS0/RXD0 PD3 PD2 PD1 PD0 VSSA VDDA S12GA192 S12GA240 100-Pin LQFP

Device Overview MC9S12G-Family MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 105 Table 1-25. 100-Pin LQFP Pinout for S12GA192 and S12GA240 Function <----lowest-----PRIORITY -----highest----> Power Supply Internal Pull Resistor Package Pin Pin 2nd Func. 3rd Func. 4th Func. CTRL Reset State 15 TEST — — — N.A. RESET pin Down 1 6P A 4 ——— V DDX PUCR/PUPAE Disabled 1 7P A 5 ——— V DDX PUCR/PUPAE Disabled 1 8P A 6 ——— V DDX PUCR/PUPAE Disabled 1 9P A 7 ——— V DDX PUCR/PUPAE Disabled

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Table 1-25. 100-Pin LQFP Pinout for S12GA192 and S12GA240 Function <----lowest-----PRIORITY -----highest----> Power Supply Internal Pull Resistor Package Pin Pin 2nd Func. 3rd Func. 4th Func. CTRL Reset State

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60 PAD10 KWAD10 AN10 AMP1 V DDA PER0AD/PPS0AD Disabled

62 PAD11 KWAD11 AN11 AMP0 V DDA PER0AD/PPS0AD Disabled

66 PAD13 KWAD13 AN13 AMPM0 V DDA PER0AD/PPS0AD Disabled

68 PAD14 KWAD14 AN14 AMPP0 V DDA PER0AD/PPS0AD Disabled

70 PAD15 KWAD15 AN15 DACU0 V DDA PER0AD/PPS0AD Disabled

72 PC5 AMPM1 — — V DDA PUCR/PUPCE Disabled

73 PC6 AMPP1 — — V DDA PUCR/PUPCE Disabled

74 PC7 DACU1 — — V DDA PUCR/PUPCE Disabled

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1.9 System Clock Description

For the system clock description please refer to chapterChapter 1, “Device Overview MC9S12G-Family”.

1.10 Modes of Operation

The MCU can operate in different modes. These are described in 1.10.1 Chip Conﬁguration Summary. The MCU can operate in different power modes to facilitate power saving when full system performance is not required. These are described in 1.10.2 Low Power Operation. Some modules feature a software programmable option to freeze the module status whilst the background debug module is active to facilitate debugging.

1.10.1 Chip Conﬁguration Summary

The different modes and the security state of the MCU affect the debug features (enabled or disabled). 1 The regular I/O characteristics (see Section A.2, “I/O Characteristics”) apply if the EXTAL/XTAL function is disabled Table 1-25. 100-Pin LQFP Pinout for S12GA192 and S12GA240 Function <----lowest-----PRIORITY -----highest----> Power Supply Internal Pull Resistor Package Pin Pin 2nd Func. 3rd Func. 4th Func. CTRL Reset State

Device Overview MC9S12G-Family MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 109 The operating mode out of reset is determined by the state of the MODC signal during reset (see Table 1-26). The MODC bit in the MODE register shows the current operating mode and provides limited mode switching during operation. The state of the MODC signal is latched into this bit on the rising edge of RESET.

1.10.1.1 Normal Single-Chip Mode

This mode is intended for normal device operation. The opcode from the on-chip memory is being executed after reset (requires the reset vector to be programmed correctly). The processor program is executed from internal memory.

1.10.1.2 Special Single-Chip Mode

This mode is used for debugging single-chip operation, boot-strapping, or security related operations. The background debug module BDM is active in this mode. The CPU executes a monitor program located in an on-chip ROM. BDM ﬁrmware waits for additional serial commands through the BKGD pin.

1.10.2 Low Power Operation

The MC9S12G has two static low-power modes Pseudo Stop and Stop Mode. For a detailed description refer to S12CPMU section.

1.11 Security

The MCU security mechanism prevents unauthorized access to the Flash memory. Refer to Chapter 9, “Security (S12XS9SECV2)”, Section 7.4.1, “Security”, and Section 26.5, “Security”.

1.12 Resets and Interrupts

Consult the S12 CPU manual and the S12SINT section for information on exception processing.

1.12.1 Resets

Table 1-27. lists all Reset sources and the vector locations. Resets are explained in detail in theChapter 10, “S12 Clock, Reset and Power Management Unit (S12CPMU)”. Table 1-26. Chip Modes Chip Modes MODC Normal single chip 1 Special single chip 0

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Table 1-27. Reset Sources and Vector Locations

1.12.2 Interrupt Vectors

Table 1-28 lists all interrupt sources and vectors in the default order of priority. The interrupt module (see Chapter 6, “Interrupt Module (S12SINTV1)”) provides an interrupt vector base register (IVBR) to relocate the vectors. Vector Address Reset Source CCR Mask Local Enable $FFFE Power-On Reset (POR) None None $FFFE Low Voltage Reset (LVR) None None $FFFE External pin RESET None None $FFFE Illegal Address Reset None None $FFFC Clock monitor reset None OSCE Bit in CPMUOSC register $FFFA COP watchdog reset None CR[2:0] in CPMUCOP register Table 1-28. Interrupt Vector Locations (Sheet 1 of 2) Vector Address1 Interrupt Source CCR Mask Local Enable Wake up from STOP Wakeup from WAIT Vector base + $F8 Unimplemented instruction trap None None - - Vector base+ $F6 SWI None None - - Vector base+ $F4 XIRQ X Bit None Y es Y es Vector base+ $F2 IRQ I bit IRQCR (IRQEN) Y es Y es Vector base+ $F0 RTI time-out interrupt I bit CPMUINT (RTIE) 10.6 Interrupts Vector base+ $EE TIM timer channel 0 I bit TIE (C0I) No Y es Vector base + $EC TIM timer channel 1 I bit TIE (C1I) No Y es Vector base+ $EA TIM timer channel 2 I bit TIE (C2I) No Y es Vector base+ $E8 TIM timer channel 3 I bit TIE (C3I) No Y es Vector base+ $E6 TIM timer channel 4 I bit TIE (C4I) No Y es Vector base+ $E4 TIM timer channel 5 I bit TIE (C5I) No Y es Vector base + $E2 TIM timer channel 6 I bit TIE (C6I) No Y es Vector base+ $E0 TIM timer channel 7 I bit TIE (C7I) No Y es Vector base+ $DE TIM timer overﬂow I bit TSCR2 (TOI) No Y es Vector base+ $DC TIM Pulse accumulator A overﬂow

2 I bit PACTL (PAOVI) No Y es

Vector base + $DA TIM Pulse accumulator input edge 3 I bit PACTL (PAI) No Y es Vector base + $D8 SPI0 I bit SPI0CR1 (SPIE, SPTIE) No Y es Vector base+ $D6 SCI0 I bit SCI0CR2 (TIE, TCIE, RIE, ILIE) Ye s Ye s Vector base + $D4 SCI1 I bit SCI1CR2 (TIE, TCIE, RIE, ILIE) Ye s Ye s

Device Overview MC9S12G-Family MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 111 Vector base + $D2 ADC I bit ATDCTL2 (ASCIE) No Y es Vector base + $D0 Reserved Vector base + $CE Port J I bit PIEJ (PIEJ7-PIEJ0) Y es Y es Vector base + $CC ACMP I bit ACMPC (ACIE) No Y es Vector base + $CA Reserved Vector base + $C8 Oscillator status interrupt I bit CPMUINT (OSCIE) No Y es Vector base + $C6 PLL lock interrupt I bit CPMUINT (LOCKIE) No Y es Vector base + $C4 Reserved Vector base + $C2 SCI2 I bit SCI2CR2 (TIE, TCIE, RIE, ILIE) Ye s Ye s Vector base + $C0 Reserved Vector base + $BE SPI1 I bit SPI1CR1 (SPIE, SPTIE) No Y es Vector base + $BC SPI2 I bit SPI2CR1 (SPIE, SPTIE) No Y es Vector base + $BA FLASH error I bit FERCNFG (SFDIE, DFDIE) No No Vector base + $B8 FLASH command I bit FCNFG (CCIE) No Y es Vector base + $B6 CAN wake-up I bit CANRIER (WUPIE) Y es Y es Vector base + $B4 CAN errors I bit CANRIER (CSCIE, OVRIE) No Y es Vector base + $B2 CAN receive I bit CANRIER (RXFIE) No Y es Vector base + $B0 CAN transmit I bit CANTIER (TXEIE[2:0]) No Y es Vector base + $AE to Vector base + $90 Reserved Vector base + $8E Port P interrupt I bit PIEP (PIEP7-PIEP0) Y es Y es Vector base+ $8C Reserved Vector base + $8A Low-voltage interrupt (LVI) I bit CPMUCTRL (LVIE) No Y es Vector base + $88 Autonomous periodical interrupt (API) I bit CPMUAPICTRL (APIE) Y es Y es Vector base + $86 Reserved Vector base + $84 ADC compare interrupt I bit ATDCTL2 (ACMPIE) No Y es Vector base + $82 Port AD interrupt I bit PIE1AD(PIE1AD7-PIE1AD0) PIE0AD(PIE0AD7-PIE0AD0) Ye s Ye s Vector base + $80 Spurious interrupt — None - - 116 bits vector address based 2Only available if the 8 channel timer module is instantiated on the device 3Only available if the 8 channel timer module is instantiated on the device Table 1-28. Interrupt Vector Locations (Sheet 2 of 2) Vector Address1 Interrupt Source CCR Mask Local Enable Wake up from STOP Wakeup from WAIT

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1.12.3 Effects of Reset

When a reset occurs, MCU registers and control bits are initialized. Refer to the respective block sections for register reset states. On each reset, the Flash module executes a reset sequence to load Flash conﬁguration registers.

1.12.3.1 Flash Conﬁguration Reset Sequence Phase

On each reset, the Flash module holds CPU activity while loading Flash module registers from the Flash memory. If double faults are detected in the reset phase, Flash module protection and security may be active on leaving reset. This is explained in more detail in the Flash module Section 26.1, “Introduction”.

1.12.3.2 Reset While Flash Command Active

If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The state of the word being programmed or the sector/block being erased is not guaranteed.

1.12.3.3 I/O Pins

Refer to the PIM section for reset conﬁgurations of all peripheral module ports.

1.12.3.4 RAM

The RAM arrays are not initialized out of reset.

1.13 COP Conﬁguration

The COP time-out rate bits CR[2:0] and the WCOP bit in the CPMUCOP register at address 0x003C are loaded from the Flash register FOPT. See Table 1-29 and Table 1-30 for coding. The FOPT register is loaded from the Flash conﬁguration ﬁeld byte at global address 0x3_FF0E during the reset sequence. Table 1-29. Initial COP Rate Conﬁguration NV[2:0] in FOPT Register CR[2:0] in CPMUCOP Register 000 111 001 110 010 101 011 100 100 011 101 010 110 001 111 000

Device Overview MC9S12G-Family MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 113

1.14 Autonomous Clock (ACLK) Conﬁguration

The autonomous clock1 (ACLK) is not factory trimmed. The reset value of the autonomous clock trimming register2 (CPMUACLKTR) is 0xFC.

1.15 ADC External Trigger Input Connection

The ADC module includes external trigger inputs ETRIG0, ETRIG1, ETRIG2, and ETRIG3. The external trigger allows the user to synchronize ADC conversion to external trigger events.Chapter 2, “Port Integration Module (S12GPIMV0)” describes the connection of the external trigger inputs. Consult the ADC section for information about the analog-to-digital converter module. References to freeze mode are equivalent to active BDM mode.

1.16 ADC Special Conversion Channels

Whenever the ADC’s Special Channel Conversion Bit (SC) is set, it is capable of running conversion on a number of internal channels (see Table 12-15). Table 1-31 lists the internal reference voltages which are connected to these special conversion channels. Table 1-30. Initial WCOP Conﬁguration NV[3] in FOPT Register WCOP in CPMUCOP Register 1. See Chapter 10, “S12 Clock, Reset and Power Management Unit (S12CPMU)” 2. See Section 10.3.2.15, “Autonomous Clock Trimming Register (CPMUACLKTR)” Table 1-31. Usage of ADC Special Conversion Channels ADC Channel Usage Internal_0 V DDF 1 See Section 1.17, “ADC Result Reference”. Internal_1 unused Internal_2 unused Internal_3 unused Internal_4 unused Internal_5 unused Internal_6 unused Temperature sense of ADC hardmacro

2 The ADC temperature sensor is only available on S12GA192 and

S12GA240 devices. Internal_7 unused

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1.17 ADC Result Reference

MCUs of the S12G-Family are able to measure the internal reference voltage VDDF (see Table 1-31). VDDF is a constant voltage with a narrow distribution over temperature and external voltage supply (see Table A-30). A 12-bit left justiﬁed1 ADC conversion result of VDDF is provided at address 0x0_4022/0x0_4023 in the NVM’s IFR for reference.The measurement conditions of the reference conversion are listed in Section A.16, “ADC Conversion Result Reference”. By measuring the voltage V DDF (see Table 1-31) and comparing the result to the reference value in the IFR, it is possible to determine the ADC’s reference voltage V RH in the application environment: The exact absolute value of an analog conversion can be determined as follows: With: ConvertedADInput: Result of the analog to digital conversion of the desired pin ConvertedReference: Result of channel “Internal_0” conversion StoredReference: Value in IFR locatio 0x0_4022/0x0_4023 n: ADC resolution (10 bit) CAUTION To assure high accuracy of the V DDF reference conversion, the NVMs must not be programmed, erased, or read while the conversion takes place. This implies that code must be executed from RAM. The “ConvertedReference” value must be the average of eight consecutive conversions. CAUTION The ADC’s reference voltage V RH must remain at a constant level throughout the conversion process.

1.18 ADC VRH/VRL Signal Connection

On all S12G devices except for the S12GA192 and the S12GA240 the external VRH signal is directly connected to the ADC’s VRH signal input. The ADC’s VRL input is connected to VSSA. (see Figure 1-21). 1. The format of the stored VDDF reference value is still subject to change. VRH StoredReference Result ConvertedADInput StoredReference 5V• ConvertedReference 2 n•

Device Overview MC9S12G-Family MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 115 The S12GA192 and the S12GA240 contain a Reverence V oltage Attenuator (RV A) module. The connection of the ADC’s VRH/VRL inputs on these devices is shown inFigure 1-21. Figure 1-21. ADC VRH/VRL Signal Connection ADC VRH VRL VRH VSSA S12GN16, S12GN32, S12GN48, S12G48, S12G64, S12G96, S12G128, S12G192, S12G240 ADCRVA VRH VRL VRH_INT VRL_INT VSSA VRHVRH VSSA S12GA192, S12G240

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MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 117 Chapter 2 Port Integration Module (S12GPIMV1)

2.1 Introduction

This section describes the S12G-family port integration module (PIM) in its conﬁgurations depending on the family devices in their available package options. It is split up into two parts, ﬁrstly determining the routing of the various signals to the available package pins (“PIM Routing”) and secondly describing the general-purpose port related logic (“PIM Ports”).

2.1.1 Glossary

Table 2-1. Glossary Of Terms Rev. No. (Item No.) Date (Submitted By) Sections Affected Substantial Change(s) V00.53 13 Oct 2010 • Reworked interrupt section V01.00 18 Oct 2010 • Initial version V01.01 01 Dec 2010 Table 2-4 Table 2-5 Table 2-8 Table 2-16 Table 2-17

Removed TXD2 and RXD2 from PM1 and PM0 for G64
Simpliﬁed input buffer control description on port C and AD
Corrected DAC signal priorities on pins PAD10 and PAD11 with shared AMP and DACU output functions V01.02 30 Aug 2011 2.4.3.40/2-192 2.4.3.48/2-198 2.4.3.63/2-207 2.4.3.64/2-208
Corrected PIFx descriptions Term Deﬁnition Pin Package terminal with a unique number deﬁned in the device pinout section Signal Input or output line of a peripheral module or general-purpose I/O function arbitrating for a dedicated pin Port Group of general-purpose I/O pins sharing peripheral signals

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2.1.2 Overview

The PIM establishes the interface between the peripheral modules and the I/O pins. It controls the electrical pin properties as well as the signal prioritization and multiplexing on shared pins. The family devices share same sets of package options (refer to device overview section) determining the availability of pins and the related PIM memory maps. The corresponding devices are referenced throughout this section by their group name as shown in Table 2-2.2.1.3 Features The PIM includes these distinctive registers:

Data registers and data direction registers for ports A, B, C, D, E, T, S, M, P, J and AD when used as general-purpose I/O
Control registers to enable/disable pull devices and select pullups/pulldowns on ports T, S, M, P, J and AD on per-pin basis
Single control register to enable/disable pull devices on ports A, B, C, D and E, on per-port basis and on BKGD pin
Control registers to enable/disable open-drain (wired-or) mode on ports S and M
Interrupt ﬂag register for pin interrupts on ports P, J and AD
Control register to conﬁgure IRQ pin operation
Routing register to support programmable signal redirection in 20 TSSOP only
Routing register to support programmable signal redirection in 100 LQFP package only
Package code register preset by factory related to package in use, writable once after reset. Also includes bit to reprogram routing of API_EXTCLK in all packages.
Control register for free-running clock outputs A standard port pin has the following minimum features:
Input/output selection
3.15 V - 5 V digital and analog input
Input with selectable pullup or pulldown device Optional features supported on dedicated pins:
Open drain for wired-or connections Table 2-2. Device Groups Group Devices with same set of package options G1 S12G240, S12GA240, S12G192, S12GA192, S12G128, S12G96 G2 S12G64, S12G48, S12GN48 G3 S12GN32, S12GN16

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Key-wakeup feature: External pin interrupt with glitch filtering, which can also be used for wakeup from stop mode.

2.1.4 Block Diagram

Figure 2-1. Block Diagram

2.2 PIM Routing - External Signal Description

This section lists and describes the signals that do connect off-chip. Table 2-3 shows the availability of I/O port pins for each group in the largest offered package option. Table 2-3. Port Pin Availability (in largest package) per Device Port Device Group (100 pin) (64 pin) (48 pin) A 7-0 - - B 7-0 - - C 7-0 - - D 7-0 - - E 1-0 1-0 1-0 T 7-0 7-0 5-0 S 7-0 7-0 7-0 M 3-0 3-0 1-0 Peripheral Module PIM Ports PIM Routing n Pin #0 Package Code Pin Routing (20 TSSOP only) Pin #n Pin Enable, Data Pin Enable, Data Data Data Control Control

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2.2.1 Package Code

The availability of pins and the related peripheral signals are determined by a package code (Section 2.4.3.33, “Package Code Register (PKGCR)”). The related value is loaded from a factory programmed non-volatile memory location into the register during the reset sequence. Based on the package code all non-bonded pins will have the input buffer disabled to avoid shoot-through current resulting in excess current in stop mode.

2.2.2 Prioritization

If more than one output signal is attempted to be enabled on a speciﬁc pin, a priority scheme determines the signal taking effect. General rules:

The peripheral with the highest amount of pins has priority on the related pins when it is enabled.
If a peripheral can selectively disable a function, the freed up pin is used with the next enabled peripheral signal.
The general-purpose output function takes control if no peripheral function is enabled. Input signals are not prioritized. Therefore the input function remains active (for example timer input capture) even if a pin is used with the output signal of another peripheral or general-purpose output.

2.2.3 Signals and Priorities

Table 2-4 shows all pins with their related signals per device and package that are controlled by the PIM. A signal name in squared brackets denotes the port register bit related to the digital I/O function of the pin (port register PORT/PT not listed). It is a representative for any other port related register bit with the same index in PTI, DDR, PER, PPS, and where applicable in PIE, PIF or WOM (seeSection 2.4, “PIM Ports - Memory Map and Register Deﬁnition”). For example pin PAD15: Signal [PT0AD7] is bit 7 of register PT0AD; other related register bits of this pin are PTI0AD7, DDR0AD7, PER0AD7, PPS0AD7, PIE0AD7 and PIF0AD7. P 7-0 7-0 5-0 J 7-0 7-0 3-0 AD 15-0 15-0 11-0 Table 2-3. Port Pin Availability (in largest package) per Device Port Device Group (100 pin) (64 pin) (48 pin)

Port Integration Module (S12GPIMV1) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 121 NOTE If there is more than one signal associated with a pin, the priority is indicated by the position in the table from top (highest priority) to bottom (lowest priority). Table 2-4. Signals and Priorities Port Pin Signal Signals per Device and Package (signal priority on pin from top to bottom) Legend ■ Signal available on pin ❍ Routing option on pin ❏ Routing reset location Not available on pin GA240 / GA192 G240 / G192 G128 / G96 GA240 / GA192 G240 / G192 G128 / G96 G64 / G48 GN48 GA240 / GA192 G240 / G192 G128 / G96 G64 / G48 GN48 GN32 GN16 G64 / G48 GN48 GN32 GN16 GN32 GN16I/O Description 100 64 48 32 20 RESET A PA7-PA0 [PA7:PA0] ■ ■ ■ I/O GPIO B PB7-PB6 [PB7:PB6] ■ ■ ■ I/O GPIO PB5 XIRQ ■ ■ ■ I Non-maskable level-sensitive interrupt [PB5] ■ ■ ■ I/O GPIO PB4 IRQ ■ ■ ■ I Maskable level- or falling-edge sensitive interrupt [PB4] ■ ■ ■ I/O GPIO PB3 [PB3] ■ ■ ■ I/O GPIO PB2 ECLKX2 ■ ■ ■ O Free-running clock (ECLK x 2) [PB2] ■ ■ ■ I/O GPIO PB1 API_EXTCLK ❏ ❏ ❏ O API Clock [PB1] ■ ■ ■ I/O GPIO PB0 ECLK ■ ■ ■ O Free-running clock [PB0] ■ ■ ■ I/O GPIO

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C PC7 DACU1 ■ O DAC1 output unbuffered [PC7] ■ ■ ■ I/O GPIO PC6 AMPP1 ■ I DAC1 non-inv. input (+) [PC6] ■ ■ ■ I/O GPIO PC5 AMPM1 ■ I DAC1 inverting input (-) [PC5] ■ ■ ■ I/O GPIO PC4-PC2 AN15-AN13 ❍ ❍ I ADC analog [PC4:PC2] ■ ■ ■ I/O GPIO PC1-PC0 AN11-AN10 ❍ ❍ I ADC analog [PC1:PC0] ■ ■ ■ I/O GPIO D PD7-PD0 [PD7:PD0] ■ ■ ■ I/O GPIO TXD0 ❏ ❏ I/O SCI transmit IOC3 ❍ ❍ I/O Timer channel PWM1 ■ ■ O PWM channel ETRIG1 ■ ■ I ADC external trigger RXD0 ❏ ❏ I SCI receive IOC2 ❍ ❍ I/O Timer channel PWM0 ■ ■ O PWM channel ETRIG0 ■ ■ I ADC external trigger Table 2-4. Signals and Priorities Port Pin Signal Signals per Device and Package (signal priority on pin from top to bottom) Legend ■ Signal available on pin ❍ Routing option on pin ❏ Routing reset location Not available on pin GA240 / GA192 G240 / G192 G128 / G96 GA240 / GA192 G240 / G192 G128 / G96 G64 / G48 GN48 GA240 / GA192 G240 / G192 G128 / G96 G64 / G48 GN48 GN32 GN16 G64 / G48 GN48 GN32 GN16 GN32 GN16I/O Description 100 64 48 32 20

Port Integration Module (S12GPIMV1) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 123 T PT7-PT6 IOC7-IOC6 ■ ■ ■ ■ ■ ■ I/O Timer channel falling-edge sensitive interrupt IOC1 level-sensitive interrupt Table 2-4. Signals and Priorities Port Pin Signal Signals per Device and Package (signal priority on pin from top to bottom) Legend ■ Signal available on pin ❍ Routing option on pin ❏ Routing reset location Not available on pin GA240 / GA192 G240 / G192 G128 / G96 GA240 / GA192 G240 / G192 G128 / G96 G64 / G48 GN48 GA240 / GA192 G240 / G192 G128 / G96 G64 / G48 GN48 GN32 GN16 G64 / G48 GN48 GN32 GN16 GN32 GN16I/O Description 100 64 48 32 20

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TXD0 ❍ ❍ I/O SCI transmit PWM5 ■ ■ ■ ■ O PWM channel PWM3 ❏ ❏ O PWM channel ETRIG3 ❏ ❏ I ADC external trigger IOC5 ■ ■ ■ ■ I/O Timer channel IOC3 ❏ ❏ I/O Timer channel IOC4 ■ ■ ■ ■ I/O Timer channel IOC2 ❏ ❏ I/O Timer channel RXD0 ❍ ❍ I SCI receive pin PWM4 ■ ■ ■ ■ O PWM channel PWM2 ❏ ❏ O PWM channel ETRIG2 ❏ ❏ I ADC external trigger Table 2-4. Signals and Priorities Port Pin Signal Signals per Device and Package (signal priority on pin from top to bottom) Legend ■ Signal available on pin ❍ Routing option on pin ❏ Routing reset location Not available on pin GA240 / GA192 G240 / G192 G128 / G96 GA240 / GA192 G240 / G192 G128 / G96 G64 / G48 GN48 GA240 / GA192 G240 / G192 G128 / G96 G64 / G48 GN48 GN32 GN16 G64 / G48 GN48 GN32 GN16 GN32 GN16I/O Description 100 64 48 32 20

Port Integration Module (S12GPIMV1) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 125 M PM3 TXD2 ■ ■ ■ ■ ■ ■ I/O SCI transmit PM2 RXD2 ■ ■ ■ ■ ■ ■ I SCI receive TXD2 ■ ■ ■ I/O SCI transmit TXD1 ■ ■ I/O SCI transmit RXD2 ■ ■ ■ I SCI receive RXD1 ■ ■ I SCI receive Table 2-4. Signals and Priorities Port Pin Signal Signals per Device and Package (signal priority on pin from top to bottom) Legend ■ Signal available on pin ❍ Routing option on pin ❏ Routing reset location Not available on pin GA240 / GA192 G240 / G192 G128 / G96 GA240 / GA192 G240 / G192 G128 / G96 G64 / G48 GN48 GA240 / GA192 G240 / G192 G128 / G96 G64 / G48 GN48 GN32 GN16 G64 / G48 GN48 GN32 GN16 GN32 GN16I/O Description 100 64 48 32 20

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P PP7-PP6 PWM7-PWM6 ■ ■ ■ ■ ■ ■ O PWM channel [PTP7:PTP6]/ KWP7-KWP6 [PTP5:PTP4]/ KWP5-KWP4 ETRIG3- ETRIG2 [PTP3:PTP2]/ KWP3-KWP2 (ECLK x 2) [PTP1]/ KWP1 [PTP0]/ KWP0 Table 2-4. Signals and Priorities Port Pin Signal Signals per Device and Package (signal priority on pin from top to bottom) Legend ■ Signal available on pin ❍ Routing option on pin ❏ Routing reset location Not available on pin GA240 / GA192 G240 / G192 G128 / G96 GA240 / GA192 G240 / G192 G128 / G96 G64 / G48 GN48 GA240 / GA192 G240 / G192 G128 / G96 G64 / G48 GN48 GN32 GN16 G64 / G48 GN48 GN32 GN16 GN32 GN16I/O Description 100 64 48 32 20

Port Integration Module (S12GPIMV1) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 127 J PJ7 SS2 ■ ■ ■ ■ ■ ■ I/O SPI slave select [PTJ7]/ KWJ7 PJ6 SCK2 ■ ■ ■ ■ ■ ■ I/O SPI serial clock [PTJ6]/ KWJ6 PJ5 MOSI2 ■ ■ ■ ■ ■ ■ I/O SPI master out/slave in [PTJ5]/ KWJ5 PJ4 MISO2 ■ ■ ■ ■ ■ ■ I/O SPI master in/slave out [PTJ4]/ KWJ4 PWM7 ■ ■ ■ O PWM channel [PTJ3]/ KWJ3 IOC7 ■ ■ ■ I/O Timer channel [PTJ2]/ KWJ2 IOC6 ■ ■ ■ I/O Timer channel [PTJ1]/ KWJ1 PWM6 ■ ■ ■ I/O Timer channel [PTJ0]/ KWJ0 Table 2-4. Signals and Priorities Port Pin Signal Signals per Device and Package (signal priority on pin from top to bottom) Legend ■ Signal available on pin ❍ Routing option on pin ❏ Routing reset location Not available on pin GA240 / GA192 G240 / G192 G128 / G96 GA240 / GA192 G240 / G192 G128 / G96 G64 / G48 GN48 GA240 / GA192 G240 / G192 G128 / G96 G64 / G48 GN48 GN32 GN16 G64 / G48 GN48 GN32 GN16 GN32 GN16I/O Description 100 64 48 32 20

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AD PAD15 DACU0 ■ ■ O DAC0 output unbuffered AN15 ❏ ❏ ■ ■ I ADC analog [PT0AD7]/ KWAD15 PAD14 AMPP0 ■ ■ I DAC0 non-inv. input (+) AN14 ❏ ❏ ■ ■ I ADC analog [PT0AD6]/ KWAD14 PAD13 AMPM0 ■ ■ I DAC0 inverting input (-) AN13 ❏ ❏ ■ ■ I ADC analog [PT0AD5]/ KWAD13 PAD12 AN12 ■ ■ ■ ■ I ADC analog [PT0AD4]/ KWAD12 PAD11 AMP0 ■ ■ ■ O DAC0 output buffered DACU0 ■ O DAC0 output unbuffered ACMPM ■ ■ ■ ■ ■ ■ I ACMP inverting input (-) [PT0AD3]/ KWAD11 PAD10 AMP1 ■ ■ ■ O DAC1 output buffered DACU1 ■ ■ O DAC1 output unbuffered ACMPP ■ ■ ■ ■ ■ ■ I ACMP non-inv. input (+) [PT0AD2]/ KWAD10 PAD9 ACMPO ■ ■ ■ ■ ■ ■ O ACMP unsync. dig. out [PT0AD1]/ KWAD9 [PT0AD0]/ KWAD8 Table 2-4. Signals and Priorities Port Pin Signal Signals per Device and Package (signal priority on pin from top to bottom) Legend ■ Signal available on pin ❍ Routing option on pin ❏ Routing reset location Not available on pin GA240 / GA192 G240 / G192 G128 / G96 GA240 / GA192 G240 / G192 G128 / G96 G64 / G48 GN48 GA240 / GA192 G240 / G192 G128 / G96 G64 / G48 GN48 GN32 GN16 G64 / G48 GN48 GN32 GN16 GN32 GN16I/O Description 100 64 48 32 20

Port Integration Module (S12GPIMV1) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 129 AD PAD7 ACMPM ■ ■ ■ ■ I ACMP inverting input (-) [PT1AD7]/ KWAD7 PAD6 ACMPP ■ ■ ■ ■ I ACMP non-inv. input (+) [PT1AD6]/ KWAD6 PAD5 ACMPO ■ ■ ■ ■ O ACMP unsync. dig. out ACMPM ■ ■ I ACMP inverting input (-) TXD0 ❍ ❍ I/O SCI transmit IOC3 ❍ ❍ I/O Timer channel PWM3 ❍ ❍ O PWM channel ETRIG3 ❍ ❍ I ADC external trigger [PT1AD5]/ KWAD5 PAD4 ACMPP ■ ■ I ACMP non-inv. input (+) RXD0 ❍ ❍ I SCI receive IOC2 ❍ ❍ I/O Timer channel PWM2 ❍ ❍ O PWM channel ETRIG2 ❍ ❍ I ADC external trigger [PT1AD4]/ KWAD4 PAD3 ACMPO ■ ■ O ACMP unsync. dig. out [PT1AD3]/ KWAD3 [PT1AD2: PT1AD0]/ KWAD2- KWAD0 Table 2-4. Signals and Priorities Port Pin Signal Signals per Device and Package (signal priority on pin from top to bottom) Legend ■ Signal available on pin ❍ Routing option on pin ❏ Routing reset location Not available on pin GA240 / GA192 G240 / G192 G128 / G96 GA240 / GA192 G240 / G192 G128 / G96 G64 / G48 GN48 GA240 / GA192 G240 / G192 G128 / G96 G64 / G48 GN48 GN32 GN16 G64 / G48 GN48 GN32 GN16 GN32 GN16I/O Description 100 64 48 32 20

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2.3 PIM Routing - Functional description

This section describes the signals available on each pin. Although trying to enable multiple signals on a shared pin is not a proper use case in most applications, Only enabled signals arbitrate for the pin and the highest priority deﬁnes its data direction and output value if used as output. Signals with programmable routing options are assumed to select the appropriate target pin to participate in the arbitration. The priority is represented for each pin with shared signals from highest to lowest in the following format: SignalA > SignalB > GPO Here SignalA has priority over SignalB and general-purpose output function (GPO; represented by related port data register bit). The general-purpose output is always of lowest priority if no other signal is enabled. Peripheral input signals on shared pins are always connected monitoring the pin level independent of their use.

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2.3.1 Pin BKGD

2.3.2 Pins PA7-0

2.3.3 Pins PB7-0

2.3.4 Pins PC7-0

When using AMPM1, AMPP1 or DACU1 please refer to section 2.6.1, “Initialization”. Table 2-5. Pin BKGD BKGD • The BKGD pin is associated with the BDM module in all packages. During reset, the BKGD pin is used as MODC input. Table 2-6. Port A Pins PA7-0 PA7-PA0 • These pins feature general-purpose I/O functionality only. Table 2-7. Port B Pins PB7-0 PB7-PB6 • These pins feature general-purpose I/O functionality only. PB5 • 100 LQFP: The XIRQ signal is mapped to this pin when used with the XIRQ interrupt function. The interrupt is enabled by clearing the X mask bit in the CPU Condition Code register. The I/O state of the pin is forced to input level upon the ﬁrst clearing of the X bit and held in this state even if the bit is set again. A STOP or WAIT recovery with the X bit set (refer to CPU12/CPU12X Reference Manual) is not available.
Signal priority:

100 LQFP:

XIRQ > GPO PB4 • 100 LQFP: The IRQ signal is mapped to this pin when used with the IRQ interrupt function. If enabled (IRQEN=1) the I/O state of the pin is forced to be an input.

Signal priority:

100 LQFP: IRQ > GPO

PB3 • This pin features general-purpose I/O functionality only. PB2 • 100 LQFP: The ECLKX2 signal is mapped to this pin when used with the external clock function. The enabled ECLKX2 signal forces the I/O state to an output.

Signal priority:

100 LQFP: ECLKX2 > GPO

PB1 • 100 LQFP: The API_EXTCLK signal is mapped to this pin when used with the external clock function. If the Autonomous Periodic Interrupt clock is enabled and routed here the I/O state is forced to output.

Signal priority:

100 LQFP: API_EXTCLK > GPO

PB0 • 100 LQFP: The ECLK signal is mapped to this pin when used with the external clock function. The enabled ECLK signal forces the I/O state to an output.

Signal priority:

100 LQFP: ECLK > GPO

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When routing of ADC channels to PC4-PC0 is selected (PRR1[PRR1AN]=1) the related bit in the ADC Digital Input Enable Register (ATDDIEN) must be set to 1 to activate the digital input function on those pins not used as ADC inputs. If the external trigger source is one of the ADC channels, the digital input buffer of this channel is automatically enabled. Table 2-8. Port C Pins PC7-0 PC7 • 100 LQFP: The unbuffered analog output signal DACU1 of the DAC1 module is mapped to this pin if the DAC is operating in “unbuffered DAC” mode. If this pin is used with the DAC then the digital I/O function and pull device are disabled.
Signal priority:

100 LQFP: DACU1 > GPO

PC6 • 100 LQFP: The non-inverting analog input signal AMPP1 of the DAC1 module is mapped to this pin if the DAC is operating in “unbuffered DAC with operational ampliﬁer” or “operational ampliﬁer only” mode. If this pin is used with the DAC then the digital input buffer is disabled.

Signal priority:

100 LQFP: GPO

PC5 • 100 LQFP: The inverting analog input signal AMPM1 of the DAC1 module is mapped to this pin if the DAC is operating in “unbuffered DAC with operational ampliﬁer” or “operational ampliﬁer only” mode. If this pin is used with the DAC then the digital input buffer is disabled.

Signal priority:

PC4-PC2 • 100 LQFP: If routing is active (PRR1[PRR1AN]=1) the ADC analog input channel signals AN15-13 and their related digital trigger inputs are mapped to these pins. The routed ADC function has no effect on the output state. Refer to NOTE/2-131 for input buffer control.

Signal priority:

PC1-PC0 • 100 LQFP: If routing is active (PRR1[PRR1AN]=1) the ADC analog input channel signals AN11-10 and their related digital trigger inputs are mapped to these pins. The routed ADC function has no effect on the output state. Refer to NOTE/2-131 for input buffer control.

Signal priority:

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2.3.5 Pins PD7-0

2.3.6 Pins PE1-0

2.3.7 Pins PT7-0

Table 2-9. Port D Pins PD7-0 PD7-PD0 • These pins feature general-purpose I/O functionality only. Table 2-10. Port E Pins PE1-0 PE1 • If the CPMU OSC function is active this pin is used as XTAL signal and the pulldown device is disabled.

20 TSSOP: The SCI0 TXD signal is mapped to this pin when used with the SCI function. If the SCI0 TXD signal is enabled and routed here the I/O state will depend on the SCI0 conﬁguration.
20 TSSOP: The TIM channel 3 signal is mapped to this pin when used with the timer function. The TIM forces the I/O state to be an output for a timer port associated with an enabled output compare.
20 TSSOP: The PWM channel 1 signal is mapped to this pin when used with the PWM function. The enabled PWM channel forces the I/O state to be an output.
20 TSSOP: The ADC ETRIG1 signal is mapped to this pin when used with the ADC function. The enabled external trigger function has no effect on the I/O state. Refer toSection 2.6.4, “ADC External Triggers ETRIG3-0”.
Signal priority:

20 TSSOP: XTAL > TXD0 > IOC3 > PWM1 > GPO

Others: XTAL > GPO PE0 • If the CPMU OSC function is active this pin is used as EXTAL signal and the pulldown device is disabled.

20 TSSOP: The SCI0 RXD signal is mapped to this pin when used with the SCI function. If the SCI0 RXD signal is enabled and routed here the I/O state will be forced to input.
20 TSSOP: The TIM channel 2 signal is mapped to this pin when used with the timer function. The TIM forces the I/O state to be an output for a timer port associated with an enabled output compare.
20 TSSOP: The PWM channel 0 signal is mapped to this pin when used with the PWM function. The enabled PWM channel forces the I/O state to be an output.
20 TSSOP: The ADC ETRIG0 signal is mapped to this pin when used with the ADC function. The enabled external trigger function has no effect on the I/O state. Refer toSection 2.6.4, “ADC External Triggers ETRIG3-0”.
Signal priority:

20 TSSOP: EXTAL > RXD0 > IOC2 > PWM0 > GPO

Others: EXTAL > GPO Table 2-11. Port T Pins PT7-0 PT7-PT6 • 64/100 LQFP: The TIM channels 7 and 6 signal are mapped to these pins when used with the timer function. The TIM forces the I/O state to be an output for a timer port associated with an enabled output compare.

Signal priority: 64/100 LQFP: IOC7-6 > GPO PT5 • 48/64/100 LQFP: The TIM channel 5 signal is mapped to this pin when used with the timer function. The TIM forces the I/O state to be an output for a timer port associated with an enabled output compare. If the ACMP timer link is enabled this pin is disconnected from the timer input so that it can still be used as general-purpose I/O or as timer output. The use case for the ACMP timer link requires the timer input capture function to be enabled.
Signal priority: 48/64/100 LQFP: IOC5 > GPO

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PT4 • 48/64/100 LQFP: The TIM channel 4 signal is mapped to this pin when used with the timer function. The TIM forces the I/O state to be an output for a timer port associated with an enabled output compare.

Signal priority: 48/64/100 LQFP: IOC4 > GPO PT3-PT2 • Except 20 TSSOP: The TIM channels 3 and 2 signal are mapped to these pins when used with the timer function. The TIM forces the I/O state to be an output for a timer port associated with an enabled output compare.
Signal priority: Except 20 TSSOP: IOC3-2 > GPO PT1 • Except 100 LQFP: The IRQ signal is mapped to this pin when used with the IRQ interrupt function. If enabled (IRQCR[IRQEN]=1) the I/O state of the pin is forced to be an input.
The TIM channel 1 signal is mapped to this pin when used with the timer function. The TIM forces the I/O state to be an output for a timer port associated with an enabled output compare.
Signal priority:

100 LQFP: IOC1 > GPO

Others: IRQ > IOC1 > GPO PT0 • Except 100 LQFP: The XIRQ signal is mapped to this pin when used with the XIRQ interrupt function.The interrupt is enabled by clearing the X mask bit in the CPU Condition Code register. The I/O state of the pin is forced to input level upon the ﬁrst clearing of the X bit and held in this state even if the bit is set again. A STOP or WAIT recovery with the X bit set (refer to CPU12/CPU12X Reference Manual) is not available.

The TIM channel 0 signal is mapped to this pin when used with the timer function. The TIM forces the I/O state to be an output for a timer port associated with an enabled output compare.
Signal priority:

100 LQFP: IOC0 > GPO

Others: XIRQ > IOC0 > GPO Table 2-11. Port T Pins PT7-0 (continued)

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2.3.8 Pins PS7-0

Table 2-12. Port S Pins PS7-0 PS7 • The SPI0 SS signal is mapped to this pin when used with the SPI function. Depending on the conﬁguration of the enabled SPI0 the I/O state is forced to be input or output.

20 TSSOP: The SCI0 TXD signal is mapped to this pin when used with the SCI function. If the SCI0 TXD signal is enabled and routed here the I/O state will depend on the SCI0 conﬁguration.
20 TSSOP: The PWM channel 3 signal is mapped to this pin when used with the PWM function. If the PWM channel is enabled and routed here the I/O state is forced to output.The enabled PWM channel forces the I/O state to be an output.
32 LQFP: The PWM channel 5 signal is mapped to this pin when used with the PWM function. The enabled PWM channel forces the I/O state to be an output.
64/48/32/20 LQFP: The ECLK signal is mapped to this pin when used with the external clock function. If the ECLK output is enabled the I/O state will be forced to output.
The API_EXTCLK signal is mapped to this pin when used with the external clock function. If the Autonomous Periodic Interrupt clock is enabled and routed here the I/O state is forced to output.
20 TSSOP: The ADC ETRIG3 signal is mapped to this pin if PWM channel 3 is routed here. The enabled external trigger function has no effect on the I/O state. Refer toSection 2.6.4, “ADC External Triggers ETRIG3-0”.
Signal priority:

20 TSSOP:

SS0 > TXD0 > PWM3 > ECLK > API_EXTCLK > GPO

32 LQFP: SS0 > PWM5 > ECLK > API_EXTCLK > GPO

48/64 LQFP: SS0 > ECLK > API_EXTCLK > GPO

100 LQFP: SS0 > API_EXTCLK > GPO

PS6 • The SPI0 SCK signal is mapped to this pin when used with the SPI function. Depending on the conﬁguration of the enabled SPI0 the I/O state is forced to be input or output.

20 TSSOP: The TIM channel 3 signal is mapped to this pin when used with the timer function. If the TIM output compare signal is enabled and routed here the I/O state will be forced to output.
32 LQFP: The TIM channel 5 signal is mapped to this pin when used with the timer function. If the TIM output compare signal is enabled and routed here the I/O state will be forced to output. If the ACMP timer link is enabled this pin is disconnected from the timer input so that it can still be used as general-purpose I/O or as timer output. The use case for the ACMP timer link requires the timer input capture function to be enabled.
Signal priority:

20 TSSOP: SCK0 > IOC3 > GPO

32 LQFP: SCK0 > IOC5 > GPO

Others: SCK0 > GPO PS5 • The SPI0 MOSI signal is mapped to this pin when used with the SPI function. Depending on the conﬁguration of the enabled SPI0 the I/O state is forced to be input or output.

20 TSSOP: The TIM channel 2 signal is mapped to this pin when used with the timer function. If the TIM output compare signal is enabled and routed here the I/O state will be forced to output.
32 LQFP: The TIM channel 4 signal is mapped to this pin when used with the timer function. If the TIM output compare signal is enabled and routed here the I/O state will be forced to output.
Signal priority:

20 TSSOP: MOSI0 > IOC2 > GPO

32 LQFP: MOSI0 > IOC4 > GPO

Others: MOSI0 > GPO

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PS4 • The SPI0 MISO signal is mapped to this pin when used with the SPI function. Depending on the conﬁguration of the enabled SPI0 the I/O state is forced to be input or output.

20 TSSOP: The SCI0 RXD signal is mapped to this pin when used with the SCI function. If the SCI0 RXD signal is enabled and routed here the I/O state will be forced to input.
20 TSSOP: The PWM channel 2 signal is mapped to this pin when used with the PWM function. If the PWM channel is enabled and routed here the I/O state is forced to output.
32 LQFP: The PWM channel 4 signal is mapped to this pin when used with the PWM function. The enabled PWM channel forces the I/O state to be an output.
20 TSSOP: The ADC ETRIG2 signal is mapped to this pin if PWM channel 2 is routed here. The enabled external trigger function has no effect on the I/O state. Refer toSection 2.6.4, “ADC External Triggers ETRIG3-0”.
Signal priority:

20 TSSOP: MISO0 > RXD0 > PWM2 > GPO

32 LQFP: MISO0 > PWM4 > GPO

Others: MISO0 > GPO PS3 • Except 20 TSSOP and 32 LQFP: The SCI1 TXD signal is mapped to this pin when used with the SCI function. If the SCI1 TXD signal is enabled the I/O state will depend on the SCI1 conﬁguration.

Signal priority: 48/64/100 LQFP: TXD1 > GPO PS2 • Except 20 TSSOP and 32 LQFP: The SCI1 RXD signal is mapped to this pin when used with the SCI function. If the SCI1 RXD signal is enabled the I/O state will be forced to be input.
Signal priority:

20 TSSOP and 32 LQFP: GPO

Others: RXD1 > GPO PS1 • Except 20 TSSOP: The SCI0 TXD signal is mapped to this pin when used with the SCI function. If the SCI0 TXD signal is enabled the I/O state will depend on the SCI0 conﬁguration.

Signal priority: Except 20 TSSOP: TXD0 > GPO PS0 • Except 20 TSSOP: The SCI0 RXD signal is mapped to this pin when used with the SCI function. If the SCI0 RXD signal is enabled the I/O state will be forced to be input.
Signal priority:

20 TSSOP: GPO

Others: RXD0 > GPO Table 2-12. Port S Pins PS7-0 (continued)

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2.3.9 Pins PM3-0

2.3.10 Pins PP7-0

Table 2-13. Port M Pins PM3-0 PM3 • 64/100 LQFP: The SCI2 TXD signal is mapped to this pin when used with the SCI function. If the SCI2 TXD signal is enabled the I/O state will depend on the SCI2 conﬁguration.

Signal priority: 64/100 LQFP: TXD2 > GPO PM2 • 64/100 LQFP: The SCI2 RXD signal is mapped to this pin when used with the SCI function. If the SCI2 RXD signal is enabled the I/O state will be forced to be input.
Signal priority: 64/100 LQFP: RXD2 > GPO PM1 • Except 20 TSSOP: The TXCAN signal is mapped to this pin when used with the CAN function. The enabled CAN forces the I/O state to be an output.
32 LQFP: The SCI1 TXD signal is mapped to this pin when used with the SCI function. If the SCI1 TXD signal is enabled the I/O state will depend on the SCI1 conﬁguration.
48 LQFP: The SCI2 TXD signal is mapped to this pin when used with the SCI function. If the SCI2 TXD signal is enabled the I/O state will depend on the SCI2 conﬁguration.
Signal priority:

32 LQFP: TXCAN > TXD1 > GPO

48 LQFP: TXCAN > TXD2 > GPO

64/100 LQFP: TXCAN > GPO PM0 • Except 20 TSSOP: The RXCAN signal is mapped to this pin when used with the CAN function. The enabled CAN forces the I/O state to be an input. If CAN is active the selection of a pulldown device on the RXCAN input has no effect.

32 LQFP: The SCI1 RXD signal is mapped to this pin when used with the SCI function. The enabled SCI1 RXD signal forces the I/O state to an input.
48 LQFP: The SCI2 RXD signal is mapped to this pin when used with the SCI function. The enabled SCI2 RXD signal forces the I/O state to an input.
Signal priority:

32 LQFP: RXCAN > RXD1 > GPO

48 LQFP: RXCAN > RXD2 > GPO

64/100 LQFP: RXCAN > GPO Table 2-14. Port P Pins PP7-0 PP7-PP6 • 64/100 LQFP: The PWM channels 7 and 6 signal are mapped to these pins when used with the PWM function. The enabled PWM channel forces the I/O state to be an output.

64/100 LQFP: Pin interrupts can be generated if enabled in input or output mode.
Signal priority: 64/100 LQFP: PWM > GPO PP5-PP4 • 48/64/100 LQFP: The PWM channels 5 and 4 signal are mapped to these pins when used with the PWM function. The enabled PWM channel forces the I/O state to be an output.
48/64/100 LQFP: Pin interrupts can be generated if enabled in input or output mode.
Signal priority: 48/64/100 LQFP: PWM > GPO

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PP3-PP2 • Except 20 TSSOP: The PWM channels 3 and 2 signal are mapped to these pins when used with the PWM function. The enabled PWM channel forces the I/O state to be an output.

Except 20 TSSOP: The ADC ETRIG 3 and 2 signal are mapped to these pins when used with the ADC function. The enabled external trigger function has no effect on the I/O state. Refer to Section 2.6.4, “ADC External Triggers ETRIG3-0”.
Except 20 TSSOP: Pin interrupts can be generated if enabled in input or output mode.
Signal priority: Except 20 TSSOP: PWM > GPO PP1 • Except 20 TSSOP: The PWM channel 1 signal is mapped to this pin when used with the PWM function. The enabled PWM channel forces the I/O state to be an output.
Except 100 LQFP and 20 TSSOP: The ECLKX2 signal is mapped to this pin when used with the external clock function. The enabled ECLKX2 forces the I/O state to an output.
Except 20 TSSOP: The ADC ETRIG1 signal is mapped to this pin when used with the ADC function. The enabled external trigger function has no effect on the I/O state. Refer to Section 2.6.4, “ADC External Triggers ETRIG3-0”.
Except 20 TSSOP: Pin interrupts can be generated if enabled in input or output mode.
Signal priority: Except 100 LQFP and 20 TSSOP: PWM1 > ECLKX2 > GPO

100 LQFP: PWM1 > GPO

PP0 • Except 20 TSSOP: The PWM channel 0 signal is mapped to this pin when used with the PWM function. The enabled PWM channel forces the I/O state to be an output.

Except 100 LQFP and 20 TSSOP: The API_EXTCLK signal is mapped to this pin when used with the external clock function. If the Autonomous Periodic Interrupt clock is enabled and routed here the I/O state is forced to output.
Except 20 TSSOP: The ADC ETRIG0 signal is mapped to this pin when used with the ADC function. The enabled external trigger function has no effect on the I/O state. Refer to Section 2.6.4, “ADC External Triggers ETRIG3-0”.
Except 20 TSSOP: Pin interrupts can be generated if enabled in input or output mode.
Signal priority: Except 100 LQFP and 20 TSSOP: PWM0 > API_EXTCLK > GPO

100 LQFP: PWM0 > GPO

Table 2-14. Port P Pins PP7-0 (continued)

Port Integration Module (S12GPIMV1) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 139

2.3.11 Pins PJ7-0

Table 2-15. Port J Pins PJ7-0 PJ7 • 64/100 LQFP: The SPI2 SS signal is mapped to this pin when used with the SPI function. Depending on the conﬁguration of the enabled SPI2 the I/O state is forced to be input or output.

64/100 LQFP: Pin interrupts can be generated if enabled in input or output mode.
Signal priority: 64/100 LQFP: SS2 > GPO PJ6 • 64/100 LQFP: The SPI2 SCK signal is mapped to this pin when used with the SPI function. Depending on the conﬁguration of the enabled SPI2 the I/O state is forced to be input or output.
64/100 LQFP: Pin interrupts can be generated if enabled in input or output mode.
Signal priority: 64/100 LQFP: SCK2 > GPO PJ5 • 64/100 LQFP: The SPI2 MOSI signal is mapped to this pin when used with the SPI function. Depending on the conﬁguration of the enabled SPI2 the I/O state is forced to be input or output.
64/100 LQFP: Pin interrupts can be generated if enabled in input or output mode.
Signal priority: 64/100 LQFP: MOSI2 > GPO PJ4 • 64/100 LQFP: The SPI2 MISO signal is mapped to this pin when used with the SPI function.Depending on the conﬁguration of the enabled SPI2 the I/O state is forced to be input or output.
64/100 LQFP: Pin interrupts can be generated if enabled in input or output mode.
Signal priority: 64/100 LQFP: MISO2 > GPO PJ3 • Except 20 TSSOP and 32 LQFP: The SPI1 SS signal is mapped to this pin when used with the SPI function. Depending on the conﬁguration of the enabled SPI1 the I/O state is forced to be input or output.
48 LQFP: The PWM channel 7 signal is mapped to this pin when used with the PWM function. The enabled PWM channel forces the I/O state to be an output.
Except 20 TSSOP and 32 LQFP: Pin interrupts can be generated if enabled in input or output mode.
Signal priority:

48 LQFP:

SS1 > PWM7 > GPO 64/100 LQFP: SS1 > GPO PJ2 • Except 20 TSSOP and 32 LQFP: The SPI1 SCK signal is mapped to this pin when used with the SPI function. Depending on the conﬁguration of the enabled SPI1 the I/O state is forced to be input or output.

48 LQFP: The TIM channel 7 signal is mapped to this pin when used with the TIM function. The TIM forces the I/O state to be an output for a timer port associated with an enabled output.
Except 20 TSSOP and 32 LQFP: Pin interrupts can be generated if enabled in input or output mode.
Signal priority:

48 LQFP: SCK1 > IOC7 > GPO

64/100 LQFP: SCK1 > GPO

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2.3.12 Pins AD15-0

The following sources contribute to enable the input buffers on port AD:

Digital input enable register bits set for each individual pin in ADC
External trigger function of ADC enabled on ADC channel
ADC channels routed to port C freeing up pins
Digital input enable register set bit in and ACMP Taking the availability of the different sources on each pin into account the following logic equation must be true to activate the digital input buffer for general-purpose input use: IBEx = ( (ATDDIENH/L[IENx]=1) OR (ATDCTL1[ETRIGSEL]=0 AND ATDCTL2[ETRIGE]=1) OR (PRR1[PRR1AN]=1) ) AND (ACDIEN=1) Eqn. 2-1 PJ1 • Except 20 TSSOP and 32 LQFP: The SPI1 MOSI signal is mapped to this pin when used with the SPI function. Depending on the conﬁguration of the enabled SPI1 the I/O state is forced to be input or output.
48 LQFP: The TIM channel 6 signal is mapped to this pin when used with the timer function. The TIM forces the I/O state to be an output for a timer port associated with an enabled output.
Except 20 TSSOP and 32 LQFP: Pin interrupts can be generated if enabled in input or output mode.
Signal priority:

48 LQFP: MOSI1 > IOC6 > GPO

64/100 LQFP: MOSI1 > GPO PJ0 • Except 20 TSSOP and 32 LQFP: The SPI1 MISO signal is mapped to this pin when used with the SPI function. Depending on the conﬁguration of the enabled SPI1 the I/O state is forced to be input or output.

48 LQFP: The PWM channel 6 signal is mapped to this pin when used with the PWM function. The enabled PWM channel forces the I/O state to be an output.
Except 20 TSSOP and 32 LQFP: Pin interrupts can be generated if enabled in input or output mode.
Signal priority:

48 LQFP: MISO1 > PWM6 > GPO

64/100 LQFP: MISO1 > GPO Table 2-15. Port J Pins PJ7-0 (continued)

Port Integration Module (S12GPIMV1) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 141 Table 2-16. Port AD Pins AD15-8 PAD15 • 64/100 LQFP: The unbuffered analog output signal DACU0 of the DAC0 module is mapped to this pin if the DAC is operating in “unbuffered DAC” mode. If this pin is used with the DAC then the digital I/O function and pull device are disabled.

64/100 LQFP: If routing is inactive (PRR1[PRR1AN]=0) the ADC analog input channel signal AN15 and the related digital trigger input are mapped to this pin. The ADC function has no effect on the output state. Refer to NOTE/2-140 for input buffer control.
64/100 LQFP: Pin interrupts can be generated if enabled in digital input or output mode.
Signal priority: 64/100 LQFP: DACU0 > GPO PAD14 • 64/100 LQFP: The non-inverting analog input signal AMPP0 of the DAC0 module is mapped to this pin if the DAC is operating in “unbuffered DAC with operational ampliﬁer” or “operational ampliﬁer only” mode. If this pin is used with the DAC then the digital input buffer is disabled.
64/100 LQFP: If routing is inactive (PRR1[PRR1AN]=0) the ADC analog input channel signal AN14 and the related digital trigger input are mapped to this pin. The ADC function has no effect on the output state. Refer to NOTE/2-140 for input buffer control.
64/100 LQFP: Pin interrupts can be generated if enabled in digital input or output mode.
Signal priority: 64/100 LQFP: GPO PAD13 • 64/100 LQFP: The inverting analog input signal AMPM0 of the DAC0 module is mapped to this pin if the DAC is operating in “unbuffered DAC with operational ampliﬁer” or “operational ampliﬁer only” mode. If this pin is used with the DAC then the digital input buffer is disabled.
64/100 LQFP: If routing is inactive (PRR1[PRR1AN]=0) the ADC analog input channel signal AN13 and the related digital trigger input are mapped to this pin. The ADC function has no effect on the output state. Refer to NOTE/2-140 for input buffer control.
64/100 LQFP: Pin interrupts can be generated if enabled in digital input or output mode.
Signal priority: 64/100 LQFP: GPO PAD12 • 64/100 LQFP: The ADC analog input channel signal AN12 and the related digital trigger input are mapped to this pin. The ADC function has no effect on the output state. Refer toNOTE/2-140 for input buffer control.
64/100 LQFP: Pin interrupts can be generated if enabled in digital input or output mode.
Signal priority: 64/100 LQFP: GPO

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PAD11 • 64/100 LQFP: The buffered analog output signal AMP0 of the DAC0 module is mapped to this pin if the DAC is operating in “buffered DAC”, “unbuffered DAC with operational ampliﬁer” or “operational ampliﬁer only” mode. If this pin is used with the DAC then the digital I/O function and pull device are disabled.

48 LQFP: The buffered analog output signal AMP0 of the DAC0 module is mapped to this pin if the DAC is operating in “buffered DAC”, “unbuffered DAC with operational ampliﬁer” 1 or “operational ampliﬁer only” mode. If this pin is used with the DAC then the digital I/O function and pull device are disabled.
48 LQFP: The unbuffered analog output signal DACU0 of the DAC0 module is mapped to this pin if the DAC is operating in “unbuffered DAC” mode. If this pin is used with the DAC then the digital output function and pull device are disabled.
48/64 LQFP: The inverting input signal ACMPM of the analog comparator is mapped to this pin when used with the ACMP function. The ACMP function has no effect on the output state. Refer to NOTE/2-140 for input buffer control.
48/64/100 LQFP: If routing is inactive (PRR1[PRR1AN]=0) the ADC analog input channel signal AN11 and the related digital trigger input are mapped to this pin. The ADC function has no effect on the output state. Refer to NOTE/2-140 for input buffer control.
48/64/100 LQFP: Pin interrupts can be generated if enabled in digital input or output mode.
Signal priority:

48 LQFP: AMP0 > DACU0 > GPO

64/100 LQFP: AMP0 > GPO PAD10 • 100 LQFP: The buffered analog output signal AMP1 of the DAC1 module is mapped to this pin if the DAC is operating in “buffered DAC”, “unbuffered DAC with operational ampliﬁer” or “operational ampliﬁer only” mode. If this pin is used with the DAC then the digital I/O function and pull device are disabled.

48/64 LQFP: The buffered analog output signal AMP1 of the DAC1 module is mapped to this pin if the DAC is operating in “buffered DAC”, “unbuffered DAC with operational ampliﬁer” 1 or “operational ampliﬁer only” mode. If this pin is used with the DAC then the digital output function and pull device are disabled.
48/64 LQFP: The unbuffered analog output signal DACU1 of the DAC1 module is mapped to this pin if the DAC is operating in “unbuffered DAC” mode. If this pin is used with the DAC then the digital output function and pull device are disabled.
48/64 LQFP: The non-inverting input signal ACMPP of the analog comparator is mapped to this pin when used with the ACMP function. The ACMP function has no effect on the output state. Refer to NOTE/2-140 for input buffer control.
48/64/100 LQFP: If routing is inactive (PRR1[PRR1AN]=0) the ADC analog input channel signal AN10 and the related digital trigger input are mapped to this pin. The ADC function has no effect on the output state. Refer to NOTE/2-140 for input buffer control.
48/64/100 LQFP: Pin interrupts can be generated if enabled in digital input or output mode.
Signal priority: 48/64 LQFP: AMP1 > DACU1 > GPO

100 LQFP: AMP1 > GPO

Table 2-16. Port AD Pins AD15-8

Port Integration Module (S12GPIMV1) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 143 PAD9 • 48/64 LQFP: The ACMPO signal of the analog comparator is mapped to this pin when used with the ACMP function. If the ACMP output is enabled (ACMPC[ACOPE]=1) the I/O state will be forced to output.

48/64/100 LQFP: The ADC analog input channel signal AN9 and the related digital trigger input are mapped to this pin. The ADC function has no effect on the output state. Refer toNOTE/2-140 for input buffer control.
48/64/100 LQFP: Pin interrupts can be generated if enabled in digital input or output mode.
Signal priority:

48 LQFP: ACMPO > GPO

64/100 LQFP: GPO PAD8 • 48/64/100 LQFP: The ADC analog input channel signal AN8 and the related digital trigger input are mapped to this pin. The ADC function has no effect on the output state. Refer toNOTE/2-140 for input buffer control.

48/64/100 LQFP: Pin interrupts can be generated if enabled in digital input or output mode.
Signal priority: 48/64/100 LQFP: GPO 1 AMP output takes precedence over DACU output on shared pin. Table 2-17. Port AD Pins AD7-0 PAD7 • 32 LQFP: The inverting input signal ACMPM of the analog comparator is mapped to this pin when used with the ACMP function. The ACMP function has no effect on the output state. Refer to NOTE/2-140 for input buffer control.
Except 20 TSSOP: The ADC analog input channel signal AN7 and the related digital trigger input are mapped to this pin. The ADC function has no effect on the output state. Refer toNOTE/2-140 for input buffer control.
Except 20 TSSOP: Pin interrupts can be generated if enabled in digital input or output mode.
Signal priority: Except 20 TSSOP: GPO PAD6 • 32 LQFP: The non-inverting input signal ACMPP of the analog comparator is mapped to this pin when used with the ACMP function. The ACMP function has no effect on the output state. Refer to NOTE/2-140 for input buffer control.
Except 20 TSSOP: The ADC analog input channel signal AN6 and the related digital trigger input are mapped to this pin. The ADC function has no effect on the output state. Refer toNOTE/2-140 for input buffer control.
Except 20 TSSOP: Pin interrupts can be generated if enabled in digital input or output mode.
Signal priority: Except 20 TSSOP: GPO Table 2-16. Port AD Pins AD15-8

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PAD5 • 32 LQFP: The ACMPO signal of the analog comparator is mapped to this pin when used with the ACMP function. If the ACMP output is enabled (ACMPC[ACOPE]=1) the I/O state will be forced to output.

20 TSSOP: The inverting input signal ACMPM of the analog comparator is mapped to this pin when used with the ACMP function. The ACMP function has no effect on the output state. Refer to NOTE/2-140 for input buffer control.
The ADC analog input channel signal AN5 and the related digital trigger input are mapped to this pin. The ADC function has no effect on the output state. Refer to NOTE/2-140 for input buffer control.
20 TSSOP: The SCI0 TXD signal is mapped to this pin. If the SCI0 TXD signal is enabled the I/O state will depend on the SCI0 conﬁguration.
20 TSSOP: The TIM channel 3 signal is mapped to this pin. The TIM forces the I/O state to be an output for a timer port associated with an enabled output compare.
20 TSSOP: The PWM channel 3 signal is mapped to this pin. If the PWM channel is enabled and routed here the I/O state is forced to output.
20 TSSOP: The ADC ETRIG3 signal is mapped to this pin if PWM channel 3 is routed here. The enabled external trigger function has no effect on the I/O state. Refer toSection 2.6.4, “ADC External Triggers ETRIG3-0”.
Pin interrupts can be generated if enabled in digital input or output mode.
Signal priority:

32 LQFP: ACMPO > GPO

20 TSSOP: TXD0 > IOC3 > PWM3 > GPO

Others: GPO PAD4 • 20 TSSOP: The non-inverting input signal ACMPP of the analog comparator is mapped to this pin when used with the ACMP function. The ACMP function has no effect on the output state. Refer to NOTE/2-140 for input buffer control.

The ADC analog input channel signal AN4 and the related digital trigger input are mapped to this pin. The ADC function has no effect on the output state. Refer to NOTE/2-140 for input buffer control.
20 TSSOP: The SCI0 RXD signal is mapped to this pin. If the SCI0 RXD signal is enabled and routed here the I/O state will be forced to input.
20 TSSOP: The TIM channel 2 signal is mapped to this pin. The TIM forces the I/O state to be an output for a timer port associated with an enabled output compare.
20 TSSOP: The PWM channel 2 signal is mapped to this pin. If the PWM channel is enabled and routed here the I/O state is forced to output.
20 TSSOP: The ADC ETRIG2 signal is mapped to this pin if PWM channel 2 is routed here. The enabled external trigger function has no effect on the I/O state. Refer toSection 2.6.4, “ADC External Triggers ETRIG3-0”.
Pin interrupts can be generated if enabled in digital input or output mode.
Signal priority:

20 TSSOP: RXD0 > IOC2 > PWM2 > GPO

Others: GPO Table 2-17. Port AD Pins AD7-0 (continued)

Port Integration Module (S12GPIMV1) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 145 PAD3 • 20 TSSOP: The ACMPO signal of the analog comparator is mapped to this pin when used with the ACMP function. If the ACMP output is enabled (ACMPC[ACOPE]=1) the I/O state will be forced to output.

The ADC analog input channel signal AN3 and the related digital trigger input are mapped to this pin. The ADC function has no effect on the output state. Refer to NOTE/2-140 for input buffer control.
Pin interrupts can be generated if enabled in digital input or output mode.
Signal priority:

20 TSSOP: ACMPO > GPO

Others: GPO PAD2-PAD0 • The ADC analog input channel signals AN2-0 and their related digital trigger inputs are mapped to this pin. The ADC function has no effect on the output state. Refer to NOTE/2-140 for input buffer control.

Pin interrupts can be generated if enabled in digital input or output mode.
Signal priority: GPO Table 2-17. Port AD Pins AD7-0 (continued)

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2.4 PIM Ports - Memory Map and Register Deﬁnition

This section provides a detailed description of all PIM registers.

2.4.1 Memory Map

Table 2-18 shows the memory maps of all groups (for deﬁnitions see Table 2-2). Addresses 0x0000 to 0x0007 are only implemented in group G1 otherwise reserved. Table 2-18. Block Memory Map (0x0000-0x027F) Port Global Address Register Access Reset Value Section/Page (A) (B) 0x0000 PORTA—Port A Data Register 1 R/W 0x00 2.4.3.1/2-165 0x0001 PORTB—Port B Data Register 1 R/W 0x00 2.4.3.2/2-165 0x0002 DDRA—Port A Data Direction Register 1 R/W 0x00 2.4.3.3/2-166 0x0003 DDRB—Port B Data Direction Register 1 R/W 0x00 2.4.3.4/2-167 (C) (D) 0x0004 PORTC—Port C Data Register 1 R/W 0x00 2.4.3.5/2-167 0x0005 PORTD—Port D Data Register 1 R/W 0x00 2.4.3.6/2-168 0x0006 DDRC—Port C Data Direction Register 1 R/W 0x00 2.4.3.7/2-169 0x0007 DDRD—Port D Data Direction Register 1 R/W 0x00 2.4.3.8/2-169 E 0x0008 PORTE—Port E Data Register R/W 0x00 0x0009 DDRE—Port E Data Direction Register R/W 0x00 0x000A 0x000B Non-PIM address range2 - - - (A) (B) (C) (D) E 0x000C PUCR—Pull Control Register R/W 0x50 2.4.3.11/2-171 0x000D Reserved R 0x00 0x000E 0x001B Non-PIM address range2 - - - 0x001C ECLKCTL—ECLK Control Register R/W 0xC0 2.4.3.12/2-173 0x001D Reserved R 0x00 0x001E IRQCR—IRQ Control Register R/W 0x00 2.4.3.13/2-173 0x001F Reserved R 0x00 0x0020 0x023F Non-PIM address range2 - - -

Port Integration Module (S12GPIMV1) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 147 T 0x0240 PTT—Port T Data Register R/W 0x00 2.4.3.15/2-175 0x0241 PTIT—Port T Input Register R 3 2.4.3.16/2-175 0x0242 DDRT—Port T Data Direction Register R/W 0x00 2.4.3.17/2-176 0x0243 Reserved R 0x00 0x0244 PERT—Port T Pull Device Enable Register R/W 0x00 2.4.3.18/2-177 0x0245 PPST—Port T Polarity Select Register R/W 0x00 2.4.3.19/2-178 0x0246 Reserved R 0x00 0x0247 Reserved R 0x00 S 0x0248 PTS—Port S Data Register R/W 0x00 2.4.3.20/2-178 0x0249 PTIS—Port S Input Register R 3 2.4.3.21/2-179 0x024A DDRS—Port S Data Direction Register R/W 0x00 2.4.3.22/2-179 0x024B Reserved R 0x00 0x024C PERS—Port S Pull Device Enable Register R/W 0xFF 2.4.3.23/2-180 0x024D PPSS—Port S Polarity Select Register R/W 0x00 2.4.3.24/2-180 0x024E WOMS—Port S Wired-Or Mode Register R/W 0x00 2.4.3.25/2-181 0x024F PRR0—Pin Routing Register 0 4 R/W 0x00 2.4.3.26/2-181 M 0x0250 PTM—Port M Data Register R/W 0x00 2.4.3.27/2-183 0x0251 PTIM—Port M Input Register R 3 2.4.3.29/2-184 0x0252 DDRM—Port M Data Direction Register R/W 0x00 2.4.3.29/2-184 0x0253 Reserved R 0x00 0x0254 PERM—Port M Pull Device Enable Register R/W 0x00 2.4.3.30/2-185 0x0255 PPSM—Port M Polarity Select Register R/W 0x00 2.4.3.31/2-186 0x0256 WOMM—Port M Wired-Or Mode Register R/W 0x00 2.4.3.32/2-186 0x0257 PKGCR—Package Code Register R/W 5 2.4.3.33/2-187 P 0x0258 PTP—Port P Data Register R/W 0x00 2.4.3.34/2-188 0x0259 PTIP—Port P Input Register R 3 2.4.3.35/2-189 0x025A DDRP—Port P Data Direction Register R/W 0x00 2.4.3.36/2-190 0x025B Reserved R 0x00 0x025C PERP—Port P Pull Device Enable Register R/W 0x00 2.4.3.37/2-190 0x025D PPSP—Port P Polarity Select Register R/W 0x00 2.4.3.38/2-191 0x025E PIEP—Port P Interrupt Enable Register R/W 0x00 2.4.3.39/2-192 0x025F PIFP—Port P Interrupt Flag Register R/W 0x00 2.4.3.40/2-192 Table 2-18. Block Memory Map (0x0000-0x027F) (continued) Port Global Address Register Access Reset Value Section/Page

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0x0260 Reserved for ACMP available in group G2 and G3 R(/W) 0x00 (ACMP) 0x0261 R(/W) 0x00 (ACMP) 0x0262 0x0266 Reserved R 0x00 J 0x0268 PTJ—Port J Data Register R/W 0x00 2.4.3.42/2-194 0x0269 PTIJ—Port J Input Register R 3 2.4.3.43/2-195 0x026A DDRJ—Port J Data Direction Register R/W 0x00 2.4.3.44/2-195 0x026B Reserved R 0x00 0x026C PERJ—Port J Pull Device Enable Register R/W 0xFF (G1,G2) 0x0F (G3) 2.4.3.45/2-196 0x026D PPSJ—Port J Polarity Select Register R/W 0x00 2.4.3.46/2-197 0x026E PIEJ—Port J Interrupt Enable Register R/W 0x00 2.4.3.47/2-197 0x026F PIFJ—Port J Interrupt Flag Register R/W 0x00 2.4.3.48/2-198 AD 0x0270 PT0AD—Port AD Data Register R/W 0x00 2.4.3.49/2-199 0x0271 PT1AD—Port AD Data Register R/W 0x00 2.4.3.50/2-199 0x0272 PTI0AD—Port AD Input Register R 3 2.4.3.51/2-200 0x0273 PTI1AD—Port AD Input Register R 3 2.4.3.54/2-201 0x0274 DDR0AD—Port AD Data Direction Register R/W 0x00 2.4.3.53/2-201 0x0275 DDR1AD—Port AD Data Direction Register R/W 0x00 2.4.3.54/2-201 0x0276 Reserved for RVACTL on G(A)240 and G(A)192 only R(/W) 0x00 (RVA) 0x0277 PRR1—Pin Routing Register 1 6 R/W 0x00 2.4.3.56/2-202 0x0278 PER0AD—Port AD Pull Device Enable Register R/W 0x00 2.4.3.57/2-203 0x0279 PER1AD—Port AD Pull Device Enable Register R/W 0x00 2.4.3.58/2-204 0x027A PPS0AD—Port AD Polarity Select Register R/W 0x00 2.4.3.59/2-204 0x027B PPS1AD—Port AD Polarity Select Register R/W 0x00 2.4.3.60/2-205 0x027C PIE0AD—Port AD Interrupt Enable Register R/W 0x00 2.4.3.61/2-206 0x027D PIE1AD—Port AD Interrupt Enable Register R/W 0x00 2.4.3.62/2-206 0x027E PIF0AD—Port AD Interrupt Flag Register R/W 0x00 2.4.3.63/2-207 0x027F PIF1AD—Port AD Interrupt Flag Register R/W 0x00 2.4.3.64/2-208 1 Available in group G1 only. In any other case this address is reserved. 2 Refer to device memory map to determine related module. 3 Read always returns logic level on pins. 4 Routing takes only effect if the PKGCR is set to 20 TSSOP . Table 2-18. Block Memory Map (0x0000-0x027F) (continued) Port Global Address Register Access Reset Value Section/Page

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2.4.2 Register Map

The following tables show the individual register maps of groups G1 (Table 2-19), G2 (Table 2-20) and G3 (Table 2-21). NOTE To maintain SW compatibility write data to unimplemented register bits must be zero.

2.4.2.1 Block Register Map (G1)

5 Preset by factory. 6 Routing register only available on G(A)240 and G(A)192 only. Takes only effect if the PKGCR is set to 100 LQFP . Table 2-19. Block Register Map (G1) Global Address Register Name Bit 7 654321 Bit 0 0x0000 PORTA R PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 W 0x0001 PORTB R PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 W 0x0002 DDRA R DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 W 0x0003 DDRB R DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 W 0x0004 PORTC R PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 W 0x0005 PORTD R PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 W 0x0006 DDRC R DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 W 0x0007 DDRD R DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0 0x0008 PORTE R 000000 PE1 PE0W 0x0009 DDRE R 000000 DDRE1 DDRE0W = Unimplemented or Reserved

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0x000A–0x000B Non-PIM Address Range R Non-PIM Address RangeW 0x000C PUCR BKPUE PDPEE PUPDE PUPCE PUPBE PUPAE W 0x000D Reserved R 00000000 W 0x000E–0x001B Non-PIM Address Range R Non-PIM Address RangeW 0x001C ECLKCTL R NECLK NCLKX2 DIV16 EDIV4 EDIV3 EDIV2 EDIV1 EDIV0 W 0x001D Reserved R 00000000 W 0x001E IRQCR R IRQE IRQEN 000000 W 0x001F Reserved R Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved W 0x0020–0x023F Non-PIM Address Range R Non-PIM Address RangeW 0x0240 PTT R PTT7 PTT6 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0 W 0x0241 PTIT R PTIT7 PTIT6 PTIT5 PTIT4 PTIT3 PTIT2 PTIT1 PTIT0 W 0x0242 DDRT R DDRT7 DDRT6 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0 W 0x0243 Reserved R 00000000 W 0x0244 PERT R PERT7 PERT6 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0 W 0x0245 PPST R PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 W Table 2-19. Block Register Map (G1) (continued) Global Address Register Name Bit 7 654321 Bit 0 = Unimplemented or Reserved

Port Integration Module (S12GPIMV1) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 151 0x0246 Reserved R 00000000 W 0x0247 Reserved R 00000000 W 0x0248 PTS R PTS7 PTS6 PTS5 PTS4 PTS3 PTS2 PTS1 PTS0 W 0x0249 PTIS R PTIS7 PTIS6 PTIS5 PTIS4 PTIS3 PTIS2 PTIS1 PTIS0 W 0x024A DDRS R DDRS7 DDRS6 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0 W 0x024B Reserved R 00000000 W 0x024C PERS R PERS7 PERS6 PERS5 PERS4 PERS3 PERS2 PERS1 PERS0 W 0x024D PPSS R PPSS7 PPSS6 PPSS5 PPSS4 PPSS3 PPSS2 PPSS1 PPSS0 W 0x024E WOMS R WOMS7 WOMS6 WOMS5 WOMS4 WOMS3 WOMS2 WOMS1 WOMS0 W 0x024F PRR0 R PRR0P3 PRR0P2 PRR0T31 PRR0T30 PRR0T21 PRR0T20 PRR0S1 PRR0S0 W 0x0250 PTM R 0000 PTM3 PTM2 PTM1 PTM0 W 0x0251 PTIM R 0000 PTIM3 PTIM2 PTIM1 PTIM0 W 0x0252 DDRM R 0000 DDRM3 DDRM2 DDRM1 DDRM0 W 0x0253 Reserved R 00000000 W 0x0254 PERM R 0000 PERM3 PERM2 PERM1 PERM0 W Table 2-19. Block Register Map (G1) (continued) Global Address Register Name Bit 7 654321 Bit 0 = Unimplemented or Reserved

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W 0x0256 WOMM R 0000 WOMM3 WOMM2 WOMM1 WOMM0 W 0x0257 PKGCR R APICLKS7 0000 PKGCR2 PKGCR1 PKGCR0 W 0x0258 PTP R PTP7 PTP6 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0 W 0x0259 PTIP R PTIP7 PTIP6 PTIP5 PTIP4 PTIP3 PTIP2 PTIP1 PTIP0 W 0x025A DDRP R DDRP7 DDRP6 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0 W 0x025B Reserved R 00000000 W 0x025C PERP R PERP7 PERP6 PERP5 PERP4 PERP3 PERP2 PERP1 PERP0 W 0x025D PPSP R PPSP7 PPSP6 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSP0 W 0x025E PIEP R PIEP7 PIEP6 PIEP5 PIEP4 PIEP3 PIEP2 PIEP1 PIEP0 W 0x025F PIFP R PIFP7 PIFP6 PIFP5 PIFP4 PIFP3 PIFP2 PIFP1 PIFP0 W 0x0260–0x0267 Reserved R 00000000 W 0x0268 PTJ R PTJ7 PTJ6 PTJ5 PTJ4 PTJ3 PTJ2 PTJ1 PTJ0 W 0x0269 PTIJ R PTIJ7 PTIJ6 PTIJ5 PTIJ4 PTIJ3 PTIJ2 PTIJ1 PTIJ0 W 0x026A DDRJ R DDRJ7 DDRJ6 DDRJ5 DDRJ4 DDRJ3 DDRJ2 DDRJ1 DDRJ0 W Table 2-19. Block Register Map (G1) (continued) Global Address Register Name Bit 7 654321 Bit 0 = Unimplemented or Reserved

Port Integration Module (S12GPIMV1) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 153 0x026B Reserved R 00000000 W 0x026C PERJ R PERJ7 PERJ6 PERJ5 PERJ4 PERJ3 PERJ2 PERJ1 PERJ0 W 0x026D PPSJ R PPSJ7 PPSJ6 PPSJ5 PPSJ4 PPSJ3 PPSJ2 PPSJ1 PPSJ0 W 0x026E PIEJ R PIEJ7 PIEJ6 PIEJ5 PIEJ4 PIEJ3 PIEJ2 PIEJ1 PIEJ0 W 0x026F PIFJ R PIFJ7 PIFJ6 PIFJ5 PIFJ4 PIFJ3 PIFJ2 PIFJ1 PIFJ0 W 0x0270 PT0AD R PT0AD7 PT0AD6 PT0AD5 PT0AD4 PT0AD3 PT0AD2 PT0AD1 PT0AD0 W 0x0271 PT1AD R PT1AD7 PT1AD6 PT1AD5 PT1AD4 PT1AD3 PT1AD2 PT1AD1 PT1AD0 W 0x0272 PTI0AD R PTI0AD7 PTI0AD6 PTI0AD5 PTI0AD4 PTI0AD3 PTI0AD2 PTI0AD1 PTI0AD0 W 0x0273 PTI1AD R PTI1AD7 PTI1AD6 PTI1AD5 PTI1AD4 PTI1AD3 PTI1AD2 PTI1AD1 PTI1AD0 W 0x0274 DDR0AD R DDR0AD7 DDR0AD6 DDR0AD5 DDR0AD4 DDR0AD3 DDR0AD2 DDR0AD1 DDR0AD0 W 0x0275 DDR1AD R DDR1AD7 DDR1AD6 DDR1AD5 DDR1AD4 DDR1AD3 DDR1AD2 DDR1AD1 DDR1AD0 W 0x0276 Reserved R Reserved for RVACTL on G(A)240 and G(A)192 W 0x0277 PRR1 R 0000000 PRR1AN W 0x0278 PER0AD R PER0AD7 PER0AD6 PER0AD5 PER0AD4 PER0AD3 PER0AD2 PER0AD1 PER0AD0 W 0x0279 PER1AD R PER1AD7 PER1AD6 PER1AD5 PER1AD4 PER1AD3 PER1AD2 PER1AD1 PER1AD0 W Table 2-19. Block Register Map (G1) (continued) Global Address Register Name Bit 7 654321 Bit 0 = Unimplemented or Reserved

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2.4.2.2 Block Register Map (G2)

R PPS0AD7 PPS0AD6 PPS0AD5 PPS0AD4 PPS0AD3 PPS0AD2 PPS0AD1 PPS0AD0 W 0x027B PPS1AD R PPS1AD7 PPS1AD6 PPS1AD5 PPS1AD4 PPS1AD3 PPS1AD2 PPS1AD1 PPS1AD0 W 0x027C PIE0AD R PIE0AD7 PIE0AD6 PIE0AD5 PIE0AD4 PIE0AD3 PIE0AD2 PIE0AD1 PIE0AD0 W 0x027D PIE1AD R PIE1AD7 PIE1AD6 PIE1AD5 PIE1AD4 PIE1AD3 PIE1AD2 PIE1AD1 PIE1AD0 W 0x027E PIF0AD R PIF0AD7 PIF0AD6 PIF0AD5 PIF0AD4 PIF0AD3 PIF0AD2 PIF0AD1 PIF0AD0 W 0x027F PIF1AD R PIF1AD7 PIF1AD6 PIF1AD5 PIF1AD4 PIF1AD3 PIF1AD2 PIF1AD1 PIF1AD0 W Table 2-20. Block Register Map (G2) Global Address Register Name Bit 7 654321 Bit 0 0x0000–0x0007 Reserved R 00000000 W 0x0008 PORTE R 000000 PE1 PE0W 0x0009 DDRE R 000000 DDRE1 DDRE0W 0x000A–0x000B Non-PIM Address Range R Non-PIM Address RangeW 0x000C PUCR BKPUE PDPEE 0000 W 0x000D Reserved R 00000000 W = Unimplemented or Reserved Table 2-19. Block Register Map (G1) (continued) Global Address Register Name Bit 7 654321 Bit 0 = Unimplemented or Reserved

Port Integration Module (S12GPIMV1) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 155 0x000E–0x001B Non-PIM Address Range R Non-PIM Address RangeW 0x001C ECLKCTL R NECLK NCLKX2 DIV16 EDIV4 EDIV3 EDIV2 EDIV1 EDIV0 W 0x001D Reserved R 00000000 W 0x001E IRQCR R IRQE IRQEN 000000 W 0x001F Reserved R Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved W 0x0020–0x023F Non-PIM Address Range R Non-PIM Address RangeW 0x0240 PTT R PTT7 PTT6 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0 W 0x0241 PTIT R PTIT7 PTIT6 PTIT5 PTIT4 PTIT3 PTIT2 PTIT1 PTIT0 W 0x0242 DDRT R DDRT7 DDRT6 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0 W 0x0243 Reserved R 00000000 W 0x0244 PERT R PERT7 PERT6 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0 W 0x0245 PPST R PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 W 0x0246 Reserved R 00000000 W 0x0247 Reserved R 00000000 W 0x0248 PTS R PTS7 PTS6 PTS5 PTS4 PTS3 PTS2 PTS1 PTS0 W Table 2-20. Block Register Map (G2) (continued) Global Address Register Name Bit 7 654321 Bit 0 = Unimplemented or Reserved

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R PTIS7 PTIS6 PTIS5 PTIS4 PTIS3 PTIS2 PTIS1 PTIS0 W 0x024A DDRS R DDRS7 DDRS6 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0 W 0x024B Reserved R 00000000 W 0x024C PERS R PERS7 PERS6 PERS5 PERS4 PERS3 PERS2 PERS1 PERS0 W 0x024D PPSS R PPSS7 PPSS6 PPSS5 PPSS4 PPSS3 PPSS2 PPSS1 PPSS0 W 0x024E WOMS R WOMS7 WOMS6 WOMS5 WOMS4 WOMS3 WOMS2 WOMS1 WOMS0 W 0x024F PRR0 R PRR0P3 PRR0P2 PRR0T31 PRR0T30 PRR0T21 PRR0T20 PRR0S1 PRR0S0 W 0x0250 PTM R 0000 PTM3 PTM2 PTM1 PTM0 W 0x0251 PTIM R 0000 PTIM3 PTIM2 PTIM1 PTIM0 W 0x0252 DDRM R 0000 DDRM3 DDRM2 DDRM1 DDRM0 W 0x0253 Reserved R 00000000 W 0x0254 PERM R 0000 PERM3 PERM2 PERM1 PERM0 W 0x0255 PPSM R 0000 PPSM3 PPSM2 PPSM1 PPSM0 W 0x0256 WOMM R 0000 WOMM3 WOMM2 WOMM1 WOMM0 W 0x0257 PKGCR R APICLKS7 0000 PKGCR2 PKGCR1 PKGCR0 W Table 2-20. Block Register Map (G2) (continued) Global Address Register Name Bit 7 654321 Bit 0 = Unimplemented or Reserved

Port Integration Module (S12GPIMV1) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 157 0x0258 PTP R PTP7 PTP6 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0 W 0x0259 PTIP R PTIP7 PTIP6 PTIP5 PTIP4 PTIP3 PTIP2 PTIP1 PTIP0 W 0x025A DDRP R DDRP7 DDRP6 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0 W 0x025B Reserved R 00000000 W 0x025C PERP R PERP7 PERP6 PERP5 PERP4 PERP3 PERP2 PERP1 PERP0 W 0x025D PPSP R PPSP7 PPSP6 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSP0 W 0x025E PIEP R PIEP7 PIEP6 PIEP5 PIEP4 PIEP3 PIEP2 PIEP1 PIEP0 W 0x025F PIFP R PIFP7 PIFP6 PIFP5 PIFP4 PIFP3 PIFP2 PIFP1 PIFP0 W 0x0260–0x0261 Reserved R Reserved for ACMP W 0x0262–0x0266 Reserved R 00000000 W 0x0267 Reserved R Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved W 0x0268 PTJ R PTJ7 PTJ6 PTJ5 PTJ4 PTJ3 PTJ2 PTJ1 PTJ0 W 0x0269 PTIJ R PTIJ7 PTIJ6 PTIJ5 PTIJ4 PTIJ3 PTIJ2 PTIJ1 PTIJ0 W 0x026A DDRJ R DDRJ7 DDRJ6 DDRJ5 DDRJ4 DDRJ3 DDRJ2 DDRJ1 DDRJ0 W 0x026B Reserved R 00000000 W Table 2-20. Block Register Map (G2) (continued) Global Address Register Name Bit 7 654321 Bit 0 = Unimplemented or Reserved

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R PERJ7 PERJ6 PERJ5 PERJ4 PERJ3 PERJ2 PERJ1 PERJ0 W 0x026D PPSJ R PPSJ7 PPSJ6 PPSJ5 PPSJ4 PPSJ3 PPSJ2 PPSJ1 PPSJ0 W 0x026E PIEJ R PIEJ7 PIEJ6 PIEJ5 PIEJ4 PIEJ3 PIEJ2 PIEJ1 PIEJ0 W 0x026F PIFJ R PIFJ7 PIFJ6 PIFJ5 PIFJ4 PIFJ3 PIFJ2 PIFJ1 PIFJ0 W 0x0270 PT0AD R PT0AD7 PT0AD6 PT0AD5 PT0AD4 PT0AD3 PT0AD2 PT0AD1 PT0AD0 W 0x0271 PT1AD R PT1AD7 PT1AD6 PT1AD5 PT1AD4 PT1AD3 PT1AD2 PT1AD1 PT1AD0 W 0x0272 PTI0AD R PTI0AD7 PTI0AD6 PTI0AD5 PTI0AD4 PTI0AD3 PTI0AD2 PTI0AD1 PTI0AD0 W 0x0273 PTI1AD R PTI1AD7 PTI1AD6 PTI1AD5 PTI1AD4 PTI1AD3 PTI1AD2 PTI1AD1 PTI1AD0 W 0x0274 DDR0AD R DDR0AD7 DDR0AD6 DDR0AD5 DDR0AD4 DDR0AD3 DDR0AD2 DDR0AD1 DDR0AD0 W 0x0275 DDR1AD R DDR1AD7 DDR1AD6 DDR1AD5 DDR1AD4 DDR1AD3 DDR1AD2 DDR1AD1 DDR1AD0 W 0x0276 Reserved R 00000000 W 0x0277 Reserved R 00000000 W 0x0278 PER0AD R PER0AD7 PER0AD6 PER0AD5 PER0AD4 PER0AD3 PER0AD2 PER0AD1 PER0AD0 W 0x0279 PER1AD R PER1AD7 PER1AD6 PER1AD5 PER1AD4 PER1AD3 PER1AD2 PER1AD1 PER1AD0 W 0x027A PPS0AD R PPS0AD7 PPS0AD6 PPS0AD5 PPS0AD4 PPS0AD3 PPS0AD2 PPS0AD1 PPS0AD0 W Table 2-20. Block Register Map (G2) (continued) Global Address Register Name Bit 7 654321 Bit 0 = Unimplemented or Reserved

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2.4.2.3 Block Register Map (G3)

R PPS1AD7 PPS1AD6 PPS1AD5 PPS1AD4 PPS1AD3 PPS1AD2 PPS1AD1 PPS1AD0 W 0x027C PIE0AD R PIE0AD7 PIE0AD6 PIE0AD5 PIE0AD4 PIE0AD3 PIE0AD2 PIE0AD1 PIE0AD0 W 0x027D PIE1AD R PIE1AD7 PIE1AD6 PIE1AD5 PIE1AD4 PIE1AD3 PIE1AD2 PIE1AD1 PIE1AD0 W 0x027E PIF0AD R PIF0AD7 PIF0AD6 PIF0AD5 PIF0AD4 PIF0AD3 PIF0AD2 PIF0AD1 PIF0AD0 W 0x027F PIF1AD R PIF1AD7 PIF1AD6 PIF1AD5 PIF1AD4 PIF1AD3 PIF1AD2 PIF1AD1 PIF1AD0 W Table 2-21. Block Register Map (G3) Global Address Register Name Bit 7 654321 Bit 0 0x0000–0x0007 Reserved R 00000000 W 0x0008 PORTE R 000000 PE1 PE0W 0x0009 DDRE R 000000 DDRE1 DDRE0W 0x000A–0x000B Non-PIM Address Range R Non-PIM Address RangeW 0x000C PUCR BKPUE PDPEE 0000 W 0x000D Reserved R 00000000 W = Unimplemented or Reserved Table 2-20. Block Register Map (G2) (continued) Global Address Register Name Bit 7 654321 Bit 0 = Unimplemented or Reserved

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0x000E–0x001B Non-PIM Address Range R Non-PIM Address RangeW 0x001C ECLKCTL R NECLK NCLKX2 DIV16 EDIV4 EDIV3 EDIV2 EDIV1 EDIV0 W 0x001D Reserved R 00000000 W 0x001E IRQCR R IRQE IRQEN 000000 W 0x001F Reserved R Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved W 0x0020–0x023F Non-PIM Address Range R Non-PIM Address RangeW 0x0240 PTT R0 0 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0 W 0x0241 PTIT R 0 0 PTIT5 PTIT4 PTIT3 PTIT2 PTIT1 PTIT0 W 0x0242 DDRT R0 0 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0 W 0x0243 Reserved R 00000000 W 0x0244 PERT R0 0 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0 W 0x0245 PPST R0 0 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 W 0x0246 Reserved R 00000000 W 0x0247 Reserved R 00000000 W 0x0248 PTS R PTS7 PTS6 PTS5 PTS4 PTS3 PTS2 PTS1 PTS0 W Table 2-21. Block Register Map (G3) (continued) Global Address Register Name Bit 7 654321 Bit 0 = Unimplemented or Reserved

Port Integration Module (S12GPIMV1) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 161 0x0249 PTIS R PTIS7 PTIS6 PTIS5 PTIS4 PTIS3 PTIS2 PTIS1 PTIS0 W 0x024A DDRS R DDRS7 DDRS6 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0 W 0x024B Reserved R 00000000 W 0x024C PERS R PERS7 PERS6 PERS5 PERS4 PERS3 PERS2 PERS1 PERS0 W 0x024D PPSS R PPSS7 PPSS6 PPSS5 PPSS4 PPSS3 PPSS2 PPSS1 PPSS0 W 0x024E WOMS R WOMS7 WOMS6 WOMS5 WOMS4 WOMS3 WOMS2 WOMS1 WOMS0 W 0x024F PRR0 R PRR0P3 PRR0P2 PRR0T31 PRR0T30 PRR0T21 PRR0T20 PRR0S1 PRR0S0 W 0x0250 PTM R 000000 PTM1 PTM0 W 0x0251 PTIM R 000000 PTIM1 PTIM0 W 0x0252 DDRM R 000000 DDRM1 DDRM0 W 0x0253 Reserved R 00000000 W 0x0254 PERM R 000000 PERM1 PERM0 W 0x0255 PPSM R 000000 PPSM1 PPSM0 W 0x0256 WOMM R 000000 WOMM1 WOMM0 W 0x0257 PKGCR R APICLKS7 0000 PKGCR2 PKGCR1 PKGCR0 W Table 2-21. Block Register Map (G3) (continued) Global Address Register Name Bit 7 654321 Bit 0 = Unimplemented or Reserved

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PTP5 PTP4 PTP3 PTP2 PTP1 PTP0 W 0x0259 PTIP R 0 0 PTIP5 PTIP4 PTIP3 PTIP2 PTIP1 PTIP0 W 0x025A DDRP R0 0 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0 W 0x025B Reserved R 00000000 W 0x025C PERP R0 0 PERP5 PERP4 PERP3 PERP2 PERP1 PERP0 W 0x025D PPSP R0 0 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSP0 W 0x025E PIEP R0 0 PIEP5 PIEP4 PIEP3 PIEP2 PIEP1 PIEP0 W 0x025F PIFP R0 0 PIFP5 PIFP4 PIFP3 PIFP2 PIFP1 PIFP0 W 0x0260–0x0261 Reserved R Reserved for ACMP W 0x0262–0x0267 Reserved R 00000000 W 0x0268 PTJ R 0000 PTJ3 PTJ2 PTJ1 PTJ0 W 0x0269 PTIJ R 0000 PTIJ3 PTIJ2 PTIJ1 PTIJ0 W 0x026A DDRJ R 0000 DDRJ3 DDRJ2 DDRJ1 DDRJ0 W 0x026B Reserved R 00000000 W 0x026C PERJ R 0000 PERJ3 PERJ2 PERJ1 PERJ0W Table 2-21. Block Register Map (G3) (continued) Global Address Register Name Bit 7 654321 Bit 0 = Unimplemented or Reserved

Port Integration Module (S12GPIMV1) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 163 0x026D PPSJ R 0000 PPSJ3 PPSJ2 PPSJ1 PPSJ0W 0x026E PIEJ R 0000 PIEJ3 PIEJ2 PIEJ1 PIEJ0W 0x026F PIFJ R 0000 PIFJ3 PIFJ2 PIFJ1 PIFJ0W 0x0270 PT0AD R 0000 PT0AD3 PT0AD2 PT0AD1 PT0AD0W 0x0271 PT1AD R PT1AD7 PT1AD6 PT1AD5 PT1AD4 PT1AD3 PT1AD2 PT1AD1 PT1AD0 W 0x0272 PTI0AD R 0000 PTI0AD3 PTI0AD2 PTI0AD1 PTI0AD0 W 0x0273 PTI1AD R PTI1AD7 PTI1AD6 PTI1AD5 PTI1AD4 PTI1AD3 PTI1AD2 PTI1AD1 PTI1AD0 W 0x0274 DDR0AD R 0000 DDR0AD3 DDR0AD2 DDR0AD1 DDR0AD0W 0x0275 DDR1AD R DDR1AD7 DDR1AD6 DDR1AD5 DDR1AD4 DDR1AD3 DDR1AD2 DDR1AD1 DDR1AD0 W 0x0276 Reserved R 00000000 W 0x0277 Reserved R 00000000 W 0x0278 PER0AD R 0000 PER0AD3 PER0AD2 PER0AD1 PER0AD0W 0x0279 PER1AD R PER1AD7 PER1AD6 PER1AD5 PER1AD4 PER1AD3 PER1AD2 PER1AD1 PER1AD0 W 0x027A PPS0AD R 0000 PPS0AD3 PPS0AD2 PPS0AD1 PPS0AD0W 0x027B PPS1AD R PPS1AD7 PPS1AD6 PPS1AD5 PPS1AD4 PPS1AD3 PPS1AD2 PPS1AD1 PPS1AD0 W Table 2-21. Block Register Map (G3) (continued) Global Address Register Name Bit 7 654321 Bit 0 = Unimplemented or Reserved

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2.4.3 Register Descriptions

This section describes the details of all conﬁguration registers. Every register has the same functionality in all groups if not speciﬁed separately. Refer to the register ﬁgures for reserved locations. If not stated differently, writing to reserved bits has not effect and read returns zero. NOTE

All register read accesses are synchronous to internal clocks
General-purpose data output availability depends on prioritization; input data registers always reﬂect the pin status independent of the use
Pull-device availability, pull-device polarity, wired-or mode, key-wakeup functionality are independent of the prioritization unless noted differently in section Section 2.3, “PIM Routing - Functional description”. 0x027C PIE0AD R 0000 PIE0AD3 PIE0AD2 PIE0AD1 PIE0AD0W 0x027D PIE1AD R PIE1AD7 PIE1AD6 PIE1AD5 PIE1AD4 PIE1AD3 PIE1AD2 PIE1AD1 PIE1AD0 W 0x027E PIF0AD R 0000 PIF0AD3 PIF0AD2 PIF0AD1 PIF0AD0W 0x027F PIF1AD R PIF1AD7 PIF1AD6 PIF1AD5 PIF1AD4 PIF1AD3 PIF1AD2 PIF1AD1 PIF1AD0 W Table 2-21. Block Register Map (G3) (continued) Global Address Register Name Bit 7 654321 Bit 0 = Unimplemented or Reserved

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2.4.3.1 Port A Data Register (PORTA)

2.4.3.2 Port B Data Register (PORTB)

Address 0x0000 (G1) Access: User read/write1 1 Read: Anytime. The data source is depending on the data direction value. Write: Anytime 76543210 R PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 W Reset 0 0000000 Address 0x0000 (G2, G3) Access: User read only 76543210 R 00000000 W Reset 0 0000000 Figure 2-2. Port A Data Register (PORTA) Table 2-22. PORTA Register Field Descriptions Field Description 7-0 PA Port A general-purpose input/output data—Data Register The associated pin can be used as general-purpose I/O. In general-purpose output mode the port data register bit value is driven to the pin. If the associated data direction bit is set to 1, a read returns the value of the port data register bit, otherwise the buffered pin input state is read. Address 0x0001 (G1) Access: User read/write 76543210 R PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 W Reset 0 0000000 Address 0x0001 (G2, G3) Access: User read only 76543210 R 00000000 W Reset 0 0000000 Figure 2-3. Port B Data Register (PORTB)

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2.4.3.3 Port A Data Direction Register (DDRA)

1 Read: Anytime. The data source is depending on the data direction value. Write: Anytime Table 2-23. PORTB Register Field Descriptions Field Description 7-0 PB Port B general-purpose input/output data—Data Register The associated pin can be used as general-purpose I/O. In general-purpose output mode the port data register bit value is driven to the pin. If the associated data direction bit is set to 1, a read returns the value of the port data register bit, otherwise the buffered pin input state is read. Address 0x0002 (G1) Access: User read/write

1 Read: Anytime

Write: Anytime 76543210 R DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 W Reset 0 0000000 Address 0x0002 (G2, G3) Access: User read only 76543210 R 00000000 W Reset 0 0000000 Figure 2-4. Port A Data Direction Register (DDRA) Table 2-24. DDRA Register Field Descriptions Field Description 7-0 DDRA Port A Data Direction— This bit determines whether the associated pin is an input or output.

1 Associated pin conﬁgured as output

0 Associated pin conﬁgured as input

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2.4.3.4 Port B Data Direction Register (DDRB)

2.4.3.5 Port C Data Register (PORTC)

Address 0x0003 (G1) Access: User read/write1 Write: Anytime 76543210 R DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 W Reset 0 0000000 Address 0x0003 (G2, G3) Access: User read only 76543210 R 00000000 W Reset 0 0000000 Figure 2-5. Port B Data Direction Register (DDRB) Table 2-25. DDRB Register Field Descriptions Field Description 7-0 DDRB Port B Data Direction— This bit determines whether the associated pin is an input or output. Address 0x0004 (G1) Access: User read/write1 1 Read: Anytime. The data source is depending on the data direction value. Write: Anytime 76543210 R PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 W Reset 0 0000000 Address 0x0004 (G2, G3) Access: User read only 76543210 R 00000000 W Reset 0 0000000 Figure 2-6. Port C Data Register (PORTC)

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2.4.3.6 Port D Data Register (PORTD)

Table 2-26. PORTC Register Field Descriptions Field Description 7-0 PC Port C general-purpose input/output data—Data Register The associated pin can be used as general-purpose I/O. In general-purpose output mode the port data register bit value is driven to the pin. If the associated data direction bit is set to 1, a read returns the value of the port data register bit, otherwise the buffered pin input state is read. Address 0x0005 (G1) Access: User read/write 1 Read: Anytime. The data source is depending on the data direction value. Write: Anytime 76543210 R PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 W Reset 0 0000000 Address 0x0005 (G2, G3) Access: User read only 76543210 R 00000000 W Reset 0 0000000 Figure 2-7. Port D Data Register (PORTD) Table 2-27. PORTD Register Field Descriptions Field Description 7-0 PD Port D general-purpose input/output data—Data Register The associated pin can be used as general-purpose I/O. In general-purpose output mode the port data register bit value is driven to the pin. If the associated data direction bit is set to 1, a read returns the value of the port data register bit, otherwise the buffered pin input state is read.

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2.4.3.7 Port C Data Direction Register (DDRC)

2.4.3.8 Port D Data Direction Register (DDRD)

Address 0x0006 (G1) Access: User read/write1 Write: Anytime 76543210 R DDRC7 DDRC6 DDRC5 DDRA4 DDRC3 DDRC2 DDRC1 DDRC0 W Reset 0 0000000 Address 0x0006 (G2, G3) Access: User read only 76543210 R 00000000 W Reset 0 0000000 Figure 2-8. Port C Data Direction Register (DDRC) Table 2-28. DDRC Register Field Descriptions Field Description 7-0 DDRC Port C Data Direction— This bit determines whether the associated pin is an input or output. Address 0x0007 (G1) Access: User read/write1 Write: Anytime 76543210 R DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0 W Reset 0 0000000 Address 0x0007 (G2, G3) Access: User read only 76543210 R 00000000 W Reset 0 0000000 Figure 2-9. Port D Data Direction Register (DDRD)

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2.4.3.9 Port E Data Register (PORTE)

2.4.3.10 Port E Data Direction Register (DDRE)

Table 2-29. DDRD Register Field Descriptions Field Description 7-0 DDRD Port D Data Direction— This bit determines whether the associated pin is an input or output. Address 0x0008 Access: User read/write1 1 Read: Anytime. The data source is depending on the data direction value. Write: Anytime 76543210 R 000000 PE1 PE0 W Reset 00000000 Figure 2-10. Port E Data Register (PORTE) Table 2-30. PORTE Register Field Descriptions Field Description 1-0 PE Port E general-purpose input/output data—Data Register When not used with an alternative signal, this pin can be used as general-purpose I/O. In general-purpose output mode the port data register bit is driven to the pin. If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the buffered pin input state is read. Address 0x0009 Access: User read/write Write: Anytime 76543210 R 000000 DDRE1 DDRE0 W Reset 00000000 Figure 2-11. Port E Data Direction Register (DDRE)

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2.4.3.11 Ports A, B, C, D, E, BKGD pin Pull Control Register (PUCR)

Table 2-31. DDRE Register Field Descriptions Field Description 1-0 DDRE Port E Data Direction— This bit determines whether the associated pin is an input or output. Address 0x000C (G1) Access: User read/write1 1 Read:Anytime in normal mode. Write:Anytime, except BKPUE, which is writable in special mode only. 76543210 BKPUE PDPEE PUPDE PUPCE PUPBE PUPAE W Reset 0 1010000 Address 0x000C (G2, G3) Access: User read/write 76543210 BKPUE PDPEE 0000 W Reset 0 1010000 Figure 2-12. Ports A, B, C, D, E, BKGD pin Pullup Control Register (PUCR) Table 2-32. PUCR Register Field Descriptions Field Description BKPUE BKGD pin Pullup Enable—Enable pullup device on pin This bit conﬁgures whether a pullup device is activated, if the pin is used as input. If a pin is used as output this bit has no effect. Out of reset the pullup device is enabled.

1 Pullup device enabled

0 Pullup device disabled

Port E Pulldown Enable—Enable pulldown devices on all port input pins This bit conﬁgures whether a pulldown device is activated on all associated port input pins. If a pin is used as output or used with the CPMU OSC function this bit has no effect. Out of reset the pulldown devices are enabled.

1 Pulldown devices enabled

0 Pulldown devices disabled

Port D Pullup Enable—Enable pullup devices on all port input pins This bit conﬁgures whether a pullup device is activated on all associated port input pins. If a pin is used as output this bit has no effect.

1 Pullup devices enabled

0 Pullup devices disabled

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Port C Pullup Enable—Enable pullup devices on all port input pins This bit conﬁgures whether a pullup device is activated on all associated port input pins. If a pin is used as output this bit has no effect. Port B Pullup Enable—Enable pullup devices on all port input pins This bit conﬁgures whether a pullup device is activated on all associated port input pins. If a pin is used as output this bit has no effect. Port A Pullup Enable—Enable pullup devices on all port input pins This bit conﬁgures whether a pullup device is activated on all associated port input pins. If a pin is used as output this bit has no effect. Table 2-32. PUCR Register Field Descriptions (continued) Field Description

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2.4.3.12 ECLK Control Register (ECLKCTL)

2.4.3.13 IRQ Control Register (IRQCR)

Address 0x001C Access: User read/write1 Write: Anytime 76543210 R NECLK NCLKX2 DIV16 EDIV4 EDIV3 EDIV2 EDIV1 EDIV0 W Reset: 11000000 Figure 2-13. ECLK Control Register (ECLKCTL) Table 2-33. ECLKCTL Register Field Descriptions Field Description NECLK No ECLK—Disable ECLK output This bit controls the availability of a free-running clock on the ECLK pin. This clock has a ﬁxed rate equivalent to the internal bus clock.

1 ECLK disabled

0 ECLK enabled

No ECLKX2—Disable ECLKX2 output This bit controls the availability of a free-running clock on the ECLKX2 pin. This clock has a ﬁxed rate of twice the internal bus clock.

1 ECLKX2 disabled

0 ECLKX2 enabled

Free-running ECLK predivider—Divide by 16 This bit enables a divide-by-16 stage on the selected EDIV rate.

1 Divider enabled: ECLK rate = EDIV rate divided by 16

0 Divider disabled: ECLK rate = EDIV rate

Free-running ECLK Divider—Conﬁgure ECLK rate These bits determine the rate of the free-running clock on the ECLK pin.

00000 ECLK rate = bus clock rate

00001 ECLK rate = bus clock rate divided by 2

00010 ECLK rate = bus clock rate divided by 3,...

11111 ECLK rate = bus clock rate divided by 32

Address 0x001E Access: User read/write 76543210 R IRQE IRQEN 000000 W Reset 00000000 Figure 2-14. IRQ Control Register (IRQCR)

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If the input is driven to active level (IRQ=0) a write access to set either IRQCR[IRQEN] and IRQCR[IRQE] to 1 simultaneously or to set IRQCR[IRQEN] to 1 when IRQCR[IRQE]=1 causes an IRQ interrupt to be generated if the I-bit is cleared. Refer to Section 2.6.3, “Enabling IRQ edge-sensitive mode”.

2.4.3.14 Reserved Register

Write: IRQE: Once in normal mode, anytime in special mode IRQEN: Anytime Table 2-34. IRQCR Register Field Descriptions Field Description IRQE IRQ select edge sensitive only— 1 IRQ pin conﬁgured to respond only to falling edges. Falling edges on the IRQ pin are detected anytime when IRQE=1 and will be cleared only upon a reset or the servicing of the IRQ interrupt.

0 IRQ pin conﬁgured for low level recognition

IRQ enable—

1 IRQ pin is connected to interrupt logic

0 IRQ pin is disconnected from interrupt logic

Address 0x001F Access: User read/write1 Write: Only in special mode NOTE These reserved registers are designed for factory test purposes only and are not intended for general user access. Writing to these registers when in special mode can alter the module’s functionality. 76543210 R Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved W Reset xxxxxxxx Figure 2-15. Reserved Register

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2.4.3.15 Port T Data Register (PTT)

2.4.3.16 Port T Input Register (PTIT)

Address 0x0240 (G1, G2) Access: User read/write1 1 Read: Anytime. The data source is depending on the data direction value. Write: Anytime 76543210 R PTT7 PTT6 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0 W Reset 00000000 Address 0x0240 (G3) Access: User read/write1 76543210 R 0 0 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0 W Reset 00000000 Figure 2-16. Port T Data Register (PTT) Table 2-35. PTT Register Field Descriptions Field Description 7-0 PTT Port T general-purpose input/output data—Data Register When not used with an alternative signal, the associated pin can be used as general-purpose I/O. In general-purpose output mode the port data register bit value is driven to the pin. If the associated data direction bit is set to 1, a read returns the value of the port data register bit, otherwise the buffered pin input state is read. Address 0x0241 (G1, G2) Access: User read only Write:Never 76543210 R PTIT7 PTIT6 PTIT5 PTIT4 PTIT3 PTIT2 PTIT1 PTIT0 W Reset 00000000 Address 0x0241 (G3) Access: User read only1 76543210 R 0 0 PTIT5 PTIT4 PTIT3 PTIT2 PTIT1 PTIT0 W Reset 00000000 Figure 2-17. Port T Input Register (PTIT)

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2.4.3.17 Port T Data Direction Register (DDRT)

Table 2-36. PTIT Register Field Descriptions Field Description 7-0 PTIT Port T input data— A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit conditions on output pins. Address 0x0242 (G1, G2) Access: User read/write Write: Anytime 76543210 R DDRT7 DDRT6 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0 W Reset 00000000 Address 0x0242 (G3) Access: User read/write1 76543210 R 0 0 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRT0 W Reset 00000000 Figure 2-18. Port T Data Direction Register (DDRT) Table 2-37. DDRT Register Field Descriptions Field Description 7-0 DDRT Port T data direction— This bit determines whether the pin is a general-purpose input or output.

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2.4.3.18 Port T Pull Device Enable Register (PERT)

Address 0x0244 (G1, G2) Access: User read/write1 Write: Anytime 76543210 R PERT7 PERT6 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0 W Reset 00000000 Address 0x0244 (G3) Access: User read/write1 76543210 R0 0 PERT5 PERT4 PERT3 PERT2 PERT1 PERT0 W Reset 00000000 Figure 2-19. Port T Pull Device Enable Register (PERT) Table 2-38. PERT Register Field Descriptions Field Description 7-2 PERT Port T pull device enable—Enable pull device on input pin This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has no effect. The polarity is selected by the related polarity select register bit.

1 Pull device enabled

0 Pull device disabled

Port T pull device enable—Enable pull device on input pin This bit controls whether a pull device on the associated port input pin is active. The polarity is selected by the related polarity select register bit. If this pin is used as IRQ only a pullup device can be enabled. Port T pull device enable—Enable pull device on input pin This bit controls whether a pull device on the associated port input pin is active. The polarity is selected by the related polarity select register bit. If this pin is used as XIRQ only a pullup device can be enabled.

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2.4.3.19 Port T Polarity Select Register (PPST)

2.4.3.20 Port S Data Register (PTS)

Address 0x0245 (G1, G2) Access: User read/write1 Write: Anytime 76543210 R PPST7 PPST6 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 W Reset 00000000 Address 0x0245 (G3) Access: User read/write1 76543210 R0 0 PPST5 PPST4 PPST3 PPST2 PPST1 PPST0 W Reset 00000000 Figure 2-20. Port T Polarity Select Register (PPST) Table 2-39. PPST Register Field Descriptions Field Description 7-0 PPST Port T pull device select—Conﬁgure pull device polarity on input pin This bit selects a pullup or a pulldown device if enabled on the associated port input pin.

1 Pulldown device selected

0 Pullup device selected

Address 0x0248 Access: User read/write1 1 Read: Anytime. The data source is depending on the data direction value. Write: Anytime 76543210 R PTS7 PTS6 PTS5 PTS4 PTS3 PTS2 PTS1 PTS0 W 00000000 Figure 2-21. Port S Data Register (PTS)

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2.4.3.21 Port S Input Register (PTIS)

2.4.3.22 Port S Data Direction Register (DDRS)

Table 2-40. PTS Register Field Descriptions Field Description 7-0 PTS Port S general-purpose input/output data—Data Register When not used with an alternative signal, the associated pin can be used as general-purpose I/O. In general-purpose output mode the port data register bit value is driven to the pin. If the associated data direction bit is set to 1, a read returns the value of the port data register bit, otherwise the buffered pin input state is read. Address 0x0249 Access: User read only Write:Never 76543210 R PTIS7 PTIS6 PTIS5 PTIS4 PTIS3 PTIS2 PTIS1 PTIS0 W Reset 00000000 Figure 2-22. Port S Input Register (PTIS) Table 2-41. PTIS Register Field Descriptions Field Description 7-0 PTIS Port S input data— A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit conditions on output pins. Address 0x024A Access: User read/write Write: Anytime 76543210 R DDRS7 DDRS6 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRS0 W Reset 00000000 Figure 2-23. Port S Data Direction Register (DDRS)

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2.4.3.23 Port S Pull Device Enable Register (PERS)

2.4.3.24 Port S Polarity Select Register (PPSS)

Table 2-42. DDRS Register Field Descriptions Field Description 7-0 DDRS Port S data direction— This bit determines whether the associated pin is a general-purpose input or output. Address 0x024C Access: User read/write1 Write: Anytime 76543210 R PERS7 PERS6 PERS5 PERS4 PERS3 PERS2 PERS1 PERS0 W Reset 11111111 Figure 2-24. Port S Pull Device Enable Register (PERS) Table 2-43. PERS Register Field Descriptions Field Description 7-0 PERS Port S pull device enable—Enable pull device on input pin or wired-or output pin This bit controls whether a pull device on the associated port input pin is active. The polarity is selected by the related polarity select register bit. If a pin is used as output this bit has only effect if used in wired-or mode with a pullup device. Address 0x024D Access: User read/write Write: Anytime 76543210 R PPSS7 PPSS6 PPSS5 PPSS4 PPSS3 PPSS2 PPSS1 PPSS0 W Reset 00000000 Figure 2-25. Port S Polarity Select Register (PPSS)

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2.4.3.25 Port S Wired-Or Mode Register (WOMS)

2.4.3.26 Pin Routing Register 0 (PRR0)

Routing takes only effect if PKGCR is set to select the 20 TSSOP package. Table 2-44. PPSS Register Field Descriptions Field Description 7-0 PPSS Port S pull device select—Conﬁgure pull device polarity on input pin This bit selects a pullup or a pulldown device if enabled on the associated port input pin. Address 0x024E Access: User read/write1 Write: Anytime 76543210 R WOMS7 WOMS6 WOMS5 WOMS4 WOMS3 WOMS2 WOMS1 WOMS0 W Reset 00000000 Figure 2-26. Port S Wired-Or Mode Register (WOMS) Table 2-45. WOMS Register Field Descriptions Field Description 7-0 WOMS Port S wired-or mode—Enable open-drain functionality on output pin This bit conﬁgures an output pin as wired-or (open-drain) or push-pull. In wired-or mode a logic “0” is driven active-low while a logic “1” remains undriven. This allows a multipoint connection of several serial modules. The bit has no inﬂuence on pins used as input. 1 Output buffer operates as open-drain output. 0 Output buffer operates as push-pull output. Address 0x024F Access: User read/write Write: Anytime 76543210 R PRR0P3 PRR0P2 PRR0T31 PRR0T30 PRR0T21 PRR0T20 PRR0S1 PRR0S0 W Reset 00000000 Figure 2-27. Pin Routing Register (PRR0)

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Table 2-46. PRR0 Register Field Descriptions Field Description PRR0P3 Pin Routing Register PWM3 —Select alternative routing of PWM3 output, ETRIG3 input This bit programs the routing of the PWM3 channel and the ETRIG3 input to a different external pin in 20 TSSOP . See Table 2-47 for more details. PRR0P2 Pin Routing Register PWM2 —Select alternative routing of PWM2 output, ETRIG2 input This bit programs the routing of the PWM2 channel and the ETRIG2 input to a different external pin in 20 TSSOP . See Table 2-48 for more details. PRR0T31 Pin Routing Register IOC3 —Select alternative routing of IOC3 output and input Those two bits program the routing of the timer IOC3 channel to different external pins in 20 TSSOP . See Table 2-49 for more details.4 PRR0T30 PRR0T21 Pin Routing Register IOC2 —Select alternative routing of IOC2 output and input Those two bits program the routing of the timer IOC2 channel to different external pins in 20 TSSOP . See Table 2-50 for more details.2 PRR0T20 PRR0S1 Pin Routing Register Serial Module —Select alternative routing of SCI0 pins Those bits program the routing of the SCI0 module pins to different external pins in 20 TSSOP . See Table 2-51 for more details.0 PRR0S0 Table 2-47. PWM3/ETRIG3 Routing Options PRR0P3 PWM3/ETRIG3 Associated Pin

0 PS7 - PWM3, ETRIG3

1 PAD5 - PWM3, ETRIG3

Table 2-48. PWM2/ETRIG2 Routing Options PRR0P2 PWM2/ETRIG2 Associated Pin

0 PS4 - PWM2, ETRIG2

1 PAD4 - PWM2, ETRIG2

Table 2-49. IOC3 Routing Options PRR0T31 PRR0T30 IOC3 Associated Pin 0 0 PS6 - IOC3 0 1 PE1 - IOC3 1 0 PAD5 - IOC3 1 1 Reserved

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2.4.3.27 Port M Data Register (PTM)

Table 2-50. IOC2 Routing Options PRR0T21 PRR0T20 IOC2 Associated Pin 0 0 PS5 - IOC2 0 1 PE0 - IOC2 1 0 PAD4 - IOC2 1 1 Reserved Table 2-51. SCI0 Routing Options PRR0S1 PRR0S0 SCI0 Associated Pin 0 0 PE0 - RXD, PE1 - TXD 0 1 PS4 - RXD, PS7 - TXD 1 0 PAD4 - RXD, PAD5 - TXD 1 1 Reserved Address 0x0250 (G1, G2) Access: User read/write 1 Read: Anytime. The data source is depending on the data direction value. Write: Anytime 76543210 R 0000 PTM3 PTM2 PTM1 PTM0 W Reset 00000000 Address 0x0250 (G3) Access: User read/write1 76543210 R 000000 PTM1 PTM0 W Reset 00000000 Figure 2-28. Port M Data Register (PTM) Table 2-52. PTM Register Field Descriptions Field Description 3-0 PTM Port M general-purpose input/output data—Data Register When not used with an alternative signal, the associated pin can be used as general-purpose I/O. In general-purpose output mode the port data register bit value is driven to the pin. If the associated data direction bit is set to 1, a read returns the value of the port data register bit, otherwise the buffered pin input state is read.

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2.4.3.28 Port M Input Register (PTIM)

2.4.3.29 Port M Data Direction Register (DDRM)

Address 0x0251 (G1, G2) Access: User read only1 Write:Never 76543210 R 0000 PTIM3 PTIM2 PTIM1 PTIM0 W Reset 00000000 Address 0x0251 (G3) Access: User read only1 76543210 R 000000 PTIM1 PTIM0 W Reset 00000000 Figure 2-29. Port M Input Register (PTIM) Table 2-53. PTIM Register Field Descriptions Field Description 3-0 PTIM Port M input data— A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit conditions on output pins. Address 0x0252 (G1, G2) Access: User read/write Write: Anytime 76543210 R 0000 DDRM3 DDRM2 DDRM1 DDRM0 W Reset 00000000 Address 0x0252 (G3) Access: User read/write1 76543210 R 000000 DDRM1 DDRM0 W Reset 00000000 Figure 2-30. Port M Data Direction Register (DDRM)

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2.4.3.30 Port M Pull Device Enable Register (PERM)

Table 2-54. DDRM Register Field Descriptions Field Description 3-0 DDRM Port M data direction— This bit determines whether the associated pin is a general-purpose input or output. Address 0x0254 (G1, G2) Access: User read/write1 Write: Anytime 76543210 R 0000 PERM3 PERM2 PERM1 PERM0 W Reset 00000000 Address 0x0254 (G3) Access: User read/write1 76543210 R 000000 PERM1 PERM0 W Reset 00000000 Figure 2-31. Port M Pull Device Enable Register (PERM) Table 2-55. PERM Register Field Descriptions Field Description 3-1 PERM Port M pull device enable—Enable pull device on input pin or wired-or output pin This bit controls whether a pull device on the associated port input pin is active. The polarity is selected by the related polarity select register bit. If a pin is used as output this bit has only effect if used in wired-or mode with a pullup device. Port M pull device enable—Enable pull device on input pin or wired-or output pin This bit controls whether a pull device on the associated port input pin is active. The polarity is selected by the related polarity select register bit. If a pin is used as output this bit has only effect if used in wired-or mode with a pullup device. If CAN is active the selection of a pulldown device on the RXCAN input will have no effect.

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2.4.3.31 Port M Polarity Select Register (PPSM)

2.4.3.32 Port M Wired-Or Mode Register (WOMM)

Address 0x0255 (G1, G2) Access: User read/write1 Write: Anytime 76543210 R 0000 PPSM3 PPSM2 PPSM1 PPSM0 W Reset 00000000 Address 0x0255 (G3) Access: User read/write1 76543210 R 000000 PPSM1 PPSM0 W Reset 00000000 Figure 2-32. Port M Polarity Select Register (PPSM) Table 2-56. PPSM Register Field Descriptions Field Description 3-0 PPSM Port M pull device select—Conﬁgure pull device polarity on input pin This bit selects a pullup or a pulldown device if enabled on the associated port input pin. Address 0x0256 (G1, G2) Access: User read/write1 Write: Anytime 76543210 R 0000 WOMM3 WOMM2 WOMM1 WOMM0 W Reset 00000000 Address 0x0256 (G3) Access: User read/write1 76543210 R 000000 WOMM1 WOMM0 W Reset 00000000 Figure 2-33. Port M Wired-Or Mode Register (WOMM)

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2.4.3.33 Package Code Register (PKGCR)

Table 2-57. WOMM Register Field Descriptions Field Description 3-0 WOMM Port M wired-or mode—Enable open-drain functionality on output pin This bit conﬁgures an output pin as wired-or (open-drain) or push-pull. In wired-or mode a logic “0” is driven active-low while a logic “1” remains undriven. This allows a multipoint connection of several serial modules. The bit has no inﬂuence on pins used as input. 1 Output buffer operates as open-drain output. 0 Output buffer operates as push-pull output. Address 0x0257 Access: User read/write Write: APICLKS7: Anytime PKGCR2-0: Once in normal mode, anytime in special mode 76543210 R APICLKS7 0000 PKGCR2 PKGCR1 PKGCR0 W Reset 00000FFF After deassert of system reset the values are automatically loaded from the Flash memory. See device speciﬁcation for details. Figure 2-34. Package Code Register (PKGCR) Table 2-58. PKGCR Register Field Descriptions Field Description APICLKS7 Pin Routing Register API_EXTCLK —Select PS7 as API_EXTCLK output When set to 1 the API_EXTCLK output will be routed to PS7. The default pin will be disconnected in all packages except 20 TSSOP , which has no default location for API_EXTCLK. SeeTable 2-59 for more details. 2-0 PKGCR Package Code Register —Select package in use Those bits are preset by factory and reﬂect the package in use. See Table 2-60 for code deﬁnition. The bits can be modiﬁed once after reset to allow software development for a different package. In any other application it is recommended to re-write the actual package code once after reset to lock the register from inadvertent changes during operation. Writing reserved codes or codes of larger packages than the given device is offered in are illegal. In these cases the code will be converted to PKGCR[2:0]=0b111 and select the maximum available package option for the given device. Codes writes of smaller packages than the given device is offered in are not restricted. Depending on the package selection the input buffers of non-bonded pins are disabled to avoid shoot-through current. Also a predeﬁned signal routing will take effect. Refer also to Section 2.6.5, “Emulation of Smaller Packages”.

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2.4.3.34 Port P Data Register (PTP)

Table 2-59. API_EXTCLK Routing Options APICLKS7 API_EXTCLK Associated Pin

0 PB1 (100 LQFP)

PP0 (64/48/32 LQFP) N.C. (20TSSOP)

1 PS7

Table 2-60. Package Options PKGCR2 PKGCR1 PKGCR0 Selected Package 1 1 1 Reserved 1 1 Reading this value indicates an illegal code write or uninitialized factory programming. 1 1 0 100 LQFP 1 0 1 Reserved 1 0 0 64 LQFP 0 1 1 48 LQFP 0 1 0 Reserved 0 0 1 32 LQFP 0 0 0 20 TSSOP Address 0x0258 (G1, G2) Access: User read/write 1 Read: Anytime. The data source is depending on the data direction value. Write: Anytime 76543210 R PTP7 PTP6 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0 W Reset 00000000 Address 0x0258 (G3) Access: User read/write1 76543210 R0 0 PTP5 PTP4 PTP3 PTP2 PTP1 PTP0 W Reset 00000000 Figure 2-35. Port P Data Register (PTP)

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2.4.3.35 Port P Input Register (PTIP)

Table 2-61. PTP Register Field Descriptions Field Description 7-0 PTP Port P general-purpose input/output data—Data Register When not used with an alternative signal, the associated pin can be used as general-purpose I/O. In general-purpose output mode the port data register bit value is driven to the pin. If the associated data direction bit is set to 1, a read returns the value of the port data register bit, otherwise the buffered pin input state is read. Address 0x0259 (G1, G2) Access: User read only Write:Never 76543210 R PTIP7 PTIP6 PTIP5 PTIP4 PTIP3 PTIP2 PTIP1 PTIP0 W Reset 00000000 Address 0x0259 (G3) Access: User read only1 76543210 R 0 0 PTIP5 PTIP4 PTIP3 PTIP2 PTIP1 PTIP0 W Reset 00000000 Figure 2-36. Port P Input Register (PTIP) Table 2-62. PTIP Register Field Descriptions Field Description 7-0 PTIP Port P input data— A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit conditions on output pins.

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2.4.3.36 Port P Data Direction Register (DDRP)

2.4.3.37 Port P Pull Device Enable Register (PERP)

Address 0x025A (G1, G2) Access: User read/write1 Write: Anytime 76543210 R DDRP7 DDRP6 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0 W Reset 00000000 Address 0x025A (G3) Access: User read/write1 76543210 R0 0 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRP0 W Reset 00000000 Figure 2-37. Port P Data Direction Register (DDRP) Table 2-63. DDRP Register Field Descriptions Field Description 7-0 DDRP Port P data direction— This bit determines whether the associated pin is an input or output. Address 0x025C (G1, G2) Access: User read/write1 Write: Anytime 76543210 R PERP7 PERP6 PERP5 PERP4 PERP3 PERP2 PERP1 PERP0 W Reset 00000000 Address 0x025C (G3) Access: User read/write1 76543210 R0 0 PERP5 PERP4 PERP3 PERP2 PERP1 PERP0 W Reset 00000000 Figure 2-38. Port P Pull Device Enable Register (PERP)

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2.4.3.38 Port P Polarity Select Register (PPSP)

Table 2-64. PERP Register Field Descriptions Field Description 7-0 PERP Port P pull device enable—Enable pull device on input pin This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has no effect. The polarity is selected by the related polarity select register bit. Address 0x025D (G1, G2) Access: User read/write Write: Anytime 76543210 R PPSP7 PPSP6 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSP0 W Reset 00000000 Address 0x025D (G3) Access: User read/write1 76543210 R0 0 PPSP5 PPSP4 PPSP3 PPSP2 PPSP1 PPSP0 W Reset 00000000 Figure 2-39. Port P Polarity Select Register (PPSP) Table 2-65. PPSP Register Field Descriptions Field Description 7-0 PPSP Port P pull device select—Conﬁgure pull device and pin interrupt edge polarity on input pin This bit selects a pullup or a pulldown device if enabled on the associated port input pin. This bit also selects the polarity of the active pin interrupt edge.

1 Pulldown device selected; rising edge selected

0 Pullup device selected; falling edge selected

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2.4.3.39 Port P Interrupt Enable Register (PIEP)

Read: Anytime

2.4.3.40 Port P Interrupt Flag Register (PIFP)

Address 0x025E (G1, G2) Access: User read/write1 Write: Anytime 76543210 R PIEP7 PIEP6 PIEP5 PIEP4 PIEP3 PIEP2 PIEP1 PIEP0 W Reset 00000000 Address 0x025E (G3) Access: User read/write1 76543210 R0 0 PIEP5 PIEP4 PIEP3 PIEP2 PIEP1 PIEP0 W Reset 00000000 Figure 2-40. Port P Interrupt Enable Register (PIEP) Table 2-66. PIEP Register Field Descriptions Field Description 7-0 PIEP Port P interrupt enable— This bit enables or disables the edge sensitive pin interrupt on the associated pin. An interrupt can be generated if the pin is operating in input or output mode when in use with the general-purpose or related peripheral function.

1 Interrupt is enabled

0 Interrupt is disabled (interrupt ﬂag masked)

Address 0x025F (G1, G2) Access: User read/write 76543210 R PIFP7 PIFP6 PIFP5 PIFP4 PIFP3 PIFP2 PIFP1 PIFP0 W Reset 00000000 Address 0x025F (G3) Access: User read/write1 76543210 R0 0 PIFP5 PIFP4 PIFP3 PIFP2 PIFP1 PIFP0 W Reset 00000000 Figure 2-41. Port P Interrupt Flag Register (PIFP)

Port Integration Module (S12GPIMV1) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 193 Write: Anytime, write 1 to clear Table 2-67. PIFP Register Field Descriptions Field Description 7-0 PIFP Port P interrupt ﬂag— This ﬂag asserts after a valid active edge was detected on the related pin (see Section 2.5.4.2, “Pin Interrupts and Wakeup”). This can be a rising or a falling edge based on the state of the polarity select register. An interrupt will occur if the associated interrupt enable bit is set. Writing a logic “1” to the corresponding bit ﬁeld clears the ﬂag.

1 Active edge on the associated bit has occurred

0 No active edge occurred

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2.4.3.41 Reserved Registers

Addresses 0x0260-0x0261 are reserved for ACMP registers in G2 and G3 only. Refer to ACMP section “ACMP Control Register (ACMPC)” and “ACMP Status Register (ACMPS)”.

2.4.3.42 Port J Data Register (PTJ)

Address 0x0268 (G1, G2) Access: User read/write1 1 Read: Anytime. The data source is depending on the data direction value. Write: Anytime 76543210 R PTJ7 PTJ6 PTJ5 PTJ4 PTJ3 PTJ2 PTJ1 PTJ0 W Reset 00000000 Address 0x0268 (G3) Access: User read/write1 76543210 R 0000 PTJ3 PTJ2 PTJ1 PTJ0 W Reset 00000000 Figure 2-42. Port J Data Register (PTJ) Table 2-68. PTJ Register Field Descriptions Field Description 7-0 PTJ Port J general-purpose input/output data—Data Register When not used with an alternative signal, the associated pin can be used as general-purpose I/O. In general-purpose output mode the port data register bit value is driven to the pin. If the associated data direction bit is set to 1, a read returns the value of the port data register bit, otherwise the buffered pin input state is read.

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2.4.3.43 Port J Input Register (PTIJ)

2.4.3.44 Port J Data Direction Register (DDRJ)

Address 0x0269 (G1, G2) Access: User read only1 Write:Never 76543210 R PTIJ7 PTIJ6 PTIJ5 PTIJ4 PTIJ3 PTIJ2 PTIJ1 PTIJ0 W Reset 00000000 Address 0x0269 (G3) Access: User read only1 76543210 R 0000 PTIJ3 PTIJ2 PTIJ1 PTIJ0 W Reset 00000000 Figure 2-43. Port J Input Register (PTIJ) Table 2-69. PTIJ Register Field Descriptions Field Description 7-0 PTIJ Port J input data— A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit conditions on output pins. Address 0x026A (G1, G2) Access: User read/write Write: Anytime 76543210 R DDRJ7 DDRJ6 DDRJ5 DDRJ4 DDRJ3 DDRJ2 DDRJ1 DDRJ0 W Reset 00000000 Address 0x026A (G3) Access: User read/write1 76543210 R 0000 DDRJ3 DDRJ2 DDRJ1 DDRJ0 W Reset 00000000 Figure 2-44. Port J Data Direction Register (DDRJ)

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2.4.3.45 Port J Pull Device Enable Register (PERJ)

Table 2-70. DDRJ Register Field Descriptions Field Description 7-0 DDRJ Port J data direction— This bit determines whether the associated pin is an input or output. Address 0x026C (G1, G2) Access: User read/write1 Write: Anytime 76543210 R PERJ7 PERJ6 PERJ5 PERJ4 PERJ3 PERJ2 PERJ1 PERJ0 W Reset 11111111 Address 0x026C (G3) Access: User read/write1 76543210 R 0000 PERJ3 PERJ2 PERJ1 PERJ0 W Reset 00001111 Figure 2-45. Port J Pull Device Enable Register (PERJ) Table 2-71. PERJ Register Field Descriptions Field Description 7-0 PERJ Port J pull device enable—Enable pull device on input pin This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has no effect. The polarity is selected by the related polarity select register bit.

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2.4.3.46 Port J Polarity Select Register (PPSJ)

2.4.3.47 Port J Interrupt Enable Register (PIEJ)

Read: Anytime Address 0x026D (G1, G2) Access: User read/write1 Write: Anytime 76543210 R PPSJ7 PPSJ6 PPSJ5 PPSJ4 PPSJ3 PPSJ2 PPSJ1 PPSJ0 W Reset 00000000 Address 0x026D (G3) Access: User read/write1 76543210 R 0000 PPSJ3 PPSJ2 PPSJ1 PPSJ0 W Reset 00000000 Figure 2-46. Port J Polarity Select Register (PPSJ) Table 2-72. PPSJ Register Field Descriptions Field Description 7-0 PPSJ Port J pull device select—Conﬁgure pull device and pin interrupt edge polarity on input pin This bit selects a pullup or a pulldown device if enabled on the associated port input pin. This bit also selects the polarity of the active pin interrupt edge. Address 0x026E (G1, G2) Access: User read/write 76543210 R PIEJ7 PIEJ6 PIEJ5 PIEJ4 PIEJ3 PIEJ2 PIEJ1 PIEJ0 W Reset 00000000 Address 0x026E (G3) Access: User read/write1 76543210 R 0000 PIEJ3 PIEJ2 PIEJ1 PIEJ0 W Reset 00000000 Figure 2-47. Port J Interrupt Enable Register (PIEJ)

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2.4.3.48 Port J Interrupt Flag Register (PIFJ)

Write: Anytime Table 2-73. PIEJ Register Field Descriptions Field Description 7-0 PIEJ Port J interrupt enable— This bit enables or disables the edge sensitive pin interrupt on the associated pin. An interrupt can be generated if the pin is operating in input or output mode when in use with the general-purpose or related peripheral function. Address 0x026F (G1, G2) Access: User read/write Write: Anytime, write 1 to clear 76543210 R PIFJ7 PIFJ6 PIFJ5 PIFJ4 PIFJ3 PIFJ2 PIFJ1 PIFJ0 W Reset 00000000 Address 0x026F (G3) Access: User read/write1 76543210 R 0000 PIFJ3 PIFJ2 PIFJ1 PIFJ0 W Reset 00000000 Figure 2-48. Port J Interrupt Flag Register (PIFJ) Table 2-74. PIFJ Register Field Descriptions Field Description 7-0 PIFJ Port J interrupt ﬂag— This ﬂag asserts after a valid active edge was detected on the related pin (see Section 2.5.4.2, “Pin Interrupts and Wakeup”). This can be a rising or a falling edge based on the state of the polarity select register. An interrupt will occur if the associated interrupt enable bit is set. Writing a logic “1” to the corresponding bit ﬁeld clears the ﬂag.

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2.4.3.49 Port AD Data Register (PT0AD)

2.4.3.50 Port AD Data Register (PT1AD)

Address 0x0270 (G1, G2) Access: User read/write1 1 Read: Anytime. The data source is depending on the data direction value. Write: Anytime 76543210 R PT0AD7 PT0AD6 PT0AD5 PT0AD4 PT0AD3 PT0AD2 PT0AD1 PT0AD0 W Reset 00000000 Address 0x0270 (G3) Access: User read/write1 76543210 R 0000 PT0AD3 PT0AD2 PT0AD1 PT0AD0 W Reset 00000000 Figure 2-49. Port AD Data Register (PT0AD) Table 2-75. PT0AD Register Field Descriptions Field Description 7-0 PT0AD Port AD general-purpose input/output data—Data Register When not used with an alternative signal, the associated pin can be used as general-purpose I/O. In general-purpose output mode the port data register bit value is driven to the pin. If the associated data direction bit is set to 1, a read returns the value of the port data register bit, otherwise the buffered pin input state is read if the digital input buffers are enabled (Section 2.3.12, “Pins AD15-0”). Address 0x0271 Access: User read/write 1 Read: Anytime. The data source is depending on the data direction value. Write: Anytime 76543210 R PT1AD7 PT1AD6 PT1AD5 PT1AD4 PT1AD3 PT1AD2 PT1AD1 PT1AD0 W Reset 00000000 Figure 2-50. Port AD Data Register (PT1AD)

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2.4.3.51 Port AD Input Register (PTI0AD)

2.4.3.52 Port AD Input Register (PTI1AD)

Table 2-76. PT1AD Register Field Descriptions Field Description 7-0 PT1AD Port AD general-purpose input/output data—Data Register When not used with an alternative signal, the associated pin can be used as general-purpose I/O. In general-purpose output mode the port data register bit value is driven to the pin. If the associated data direction bit is set to 1, a read returns the value of the port data register bit, otherwise the buffered pin input state is read if the digital input buffers are enabled (Section 2.3.12, “Pins AD15-0”). Address 0x0272 (G1, G2) Access: User read only Write: Never 76543210 R PTI0AD7 PTI0AD6 PTI0AD5 PTI0AD4 PTI0AD3 PTI0AD2 PTI0AD1 PTI0AD0 W Reset 00000000 Address 0x0272 (G3) Access: User read only1 76543210 R 0000 PTI0AD3 PTI0AD2 PTI0AD1 PTI0AD0 W Reset 00000000 Figure 2-51. Port AD Input Register (PTI0AD) Table 2-77. PTI0AD Register Field Descriptions Field Description 7-0 PTI0AD Port AD input data— A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit conditions on output pins. Address 0x0273 Access: User read only Write: Never 76543210 R PTI1AD7 PTI1AD6 PTI1AD5 PTI1AD4 PTI1AD3 PTI1AD2 PTI1AD1 PTI1AD0 W Reset 00000000 Figure 2-52. Port AD Input Register (PTI1AD)

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2.4.3.53 Port AD Data Direction Register (DDR0AD)

2.4.3.54 Port AD Data Direction Register (DDR1AD)

Table 2-78. PTI1AD Register Field Descriptions Field Description 7-0 PTI1AD Port AD input data— A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit conditions on output pins. Address 0x0274 (G1, G2) Access: User read/write Write: Anytime 76543210 R DDR0AD7 DDR0AD6 DDR0AD5 DDR0AD4 DDR0AD3 DDR0AD2 DDR0AD1 DDR0AD0 W Reset 00000000 Address 0x0274 (G3) Access: User read/write1 76543210 R 0000 DDR0AD3 DDR0AD2 DDR0AD1 DDR0AD0 W Reset 00000000 Figure 2-53. Port AD Data Direction Register (DDR0AD) Table 2-79. DDR0AD Register Field Descriptions Field Description 7-0 DDR0AD Port AD data direction— This bit determines whether the associated pin is an input or output. Address 0x0275 Access: User read/write1 Write: Anytime 76543210 R DDR1AD7 DDR1AD6 DDR1AD5 DDR1AD4 DDR1AD3 DDR1AD2 DDR1AD1 DDR1AD0 W Reset 00000000 Figure 2-54. Port AD Data Direction Register (DDR1AD)

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2.4.3.55 Reserved Register

Address 0x0276 is reserved for RV A on G(A)240 and G(A)192 only. Refer to RV A section “RV A Control Register (RV ACTL)”.

2.4.3.56 Pin Routing Register 1 (PRR1)

Routing takes only effect if PKGCR is set to select the 100 LQFP package. Table 2-80. DDR1AD Register Field Descriptions Field Description 7-0 DDR1AD Port AD data direction— This bit determines whether the associated pin is an input or output. Address 0x0277 (G(A)240 and G(A)192 only) Access: User read/write 1 Write: Anytime 76543210 R 0000000 PRR1AN W Reset 00000000 Address 0x0277 (non G(A)240 and G(A)192) Access: User read/write 76543210 R 00000000 W Reset 00000000 Figure 2-55. Pin Routing Register (PRR1) Table 2-81. PRR1 Register Field Descriptions Field Description PRR1AN Pin Routing Register ADC channels — Select alternative routing for AN15/14/13/11/10 pins to port C This bit programs the routing of the speciﬁc ADC channels to alternative external pins in 100 LQFP . SeeTable 2-82. The routing affects the analog signals and digital input trigger paths to the ADC. Refer to the related pin descriptions

1 AN inputs on port C

0 AN inputs on port AD

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2.4.3.57 Port AD Pull Enable Register (PER0AD)

Table 2-82. AN Routing Options PRR1AN Associated Pins

0 AN10 - PAD10

1 AN10 - PC0

Address 0x0278 (G1, G2) Access: User read/write Write: Anytime 76543210 R PER0AD7 PER0AD6 PER0AD5 PER0AD4 PER0AD3 PER0AD2 PER0AD1 PER0AD0 W Reset 00000000 Address 0x0278 (G3) Access: User read/write1 76543210 R 0000 PER0AD3 PER0AD2 PER0AD1 PER0AD0 W Reset 00000000 Figure 2-56. Port AD Pullup Enable Register (PER0AD) Table 2-83. PER0AD Register Field Descriptions Field Description 7-0 PER0AD Port AD pull enable—Enable pull device on input pin This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has no effect. The polarity is selected by the related polarity select register bit.

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2.4.3.58 Port AD Pull Enable Register (PER1AD)

2.4.3.59 Port AD Polarity Select Register (PPS0AD)

Address 0x0279 Access: User read/write1 Write: Anytime 76543210 R PER1AD7 PER1AD6 PER1AD5 PER1AD4 PER1AD3 PER1AD2 PER1AD1 PER1AD0 W Reset 00000000 Figure 2-57. Port AD Pullup Enable Register (PER1AD) Table 2-84. PER1AD Register Field Descriptions Field Description 7-0 PER1AD Port AD pull enable—Enable pull device on input pin This bit controls whether a pull device on the associated port input pin is active. If a pin is used as output this bit has no effect. The polarity is selected by the related polarity select register bit. Address 0x027A (G1, G2) Access: User read/write Write: Anytime 76543210 R PPS0AD7 PPS0AD6 PPS0AD5 PPS0AD4 PPS0AD3 PPS0AD2 PPS0AD1 PPS0AD0 W Reset 00000000 Address 0x027A (G3) Access: User read/write1 76543210 R 0000 PPS0AD3 PPS0AD2 PPS0AD1 PPS0AD0 W Reset 00000000 Figure 2-58. Port AD Polarity Select Register (PPS0AD)

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2.4.3.60 Port AD Polarity Select Register (PPS1AD)

Table 2-85. PPS0AD Register Field Descriptions Field Description 7-0 PPS0AD Port AD pull device select—Conﬁgure pull device and pin interrupt edge polarity on input pin This bit selects a pullup or a pulldown device if enabled on the associated port input pin. This bit also selects the polarity of the active pin interrupt edge. Address 0x027B Access: User read/write Write: Anytime 76543210 R PPS1AD7 PPS1AD6 PPS1AD5 PPS1AD4 PPS1AD3 PPS1AD2 PPS1AD1 PPS1AD0 W Reset 00000000 Figure 2-59. Port AD Polarity Select Register (PPS1AD) Table 2-86. PPS1AD Register Field Descriptions Field Description 7-0 PPS1AD Port AD pull device select—Conﬁgure pull device and pin interrupt edge polarity on input pin This bit selects a pullup or a pulldown device if enabled on the associated port input pin. This bit also selects the polarity of the active pin interrupt edge.

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2.4.3.61 Port AD Interrupt Enable Register (PIE0AD)

Read: Anytime

2.4.3.62 Port AD Interrupt Enable Register (PIE1AD)

Read: Anytime Address 0x027C (G1, G2) Access: User read/write1 Write: Anytime 76543210 R PIE0AD7 PIE0AD6 PIE0AD5 PIE0AD4 PIE0AD3 PIE0AD2 PIE0AD1 PIE0AD0 W Reset 00000000 Address 0x027C (G3) Access: User read/write1 76543210 R 0000 PIE0AD3 PIE0AD2 PIE0AD1 PIE0AD0 W Reset 00000000 Figure 2-60. Port AD Interrupt Enable Register (PIE0AD) Table 2-87. PIE0AD Register Field Descriptions Field Description 7-0 PIE0AD Port AD interrupt enable— This bit enables or disables the edge sensitive pin interrupt on the associated pin. An interrupt can be generated if the pin is operating in input or output mode when in use with the general-purpose or related peripheral function. Address 0x027D Access: User read/write Write: Anytime 76543210 R PIE1AD7 PIE1AD6 PIE1AD5 PIE1AD4 PIE1AD3 PIE1AD2 PIE1AD1 PIE1AD0 W Reset 00000000 Figure 2-61. Port AD Interrupt Enable Register (PIE1AD)

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2.4.3.63 Port AD Interrupt Flag Register (PIF0AD)

Table 2-88. PIE1AD Register Field Descriptions Field Description 7-0 PIE1AD Port AD interrupt enable— This bit enables or disables the edge sensitive pin interrupt on the associated pin. An interrupt can be generated if the pin is operating in input or output mode when in use with the general-purpose or related peripheral function. Address 0x027E (G1, G2) Access: User read/write Write: Anytime, write 1 to clear 76543210 R PIF0AD7 PIF0AD6 PIF0AD5 PIF0AD4 PIF0AD3 PIF0AD2 PIF0AD1 PIF0AD0 W Reset 00000000 Address 0x027E (G3) Access: User read/write1 76543210 R 0000 PIF0AD3 PIF0AD2 PIF0AD1 PIF0AD0 W Reset 00000000 Figure 2-62. Port AD Interrupt Flag Register (PIF0AD) Table 2-89. PIF0AD Register Field Descriptions Field Description 7-0 PIF0AD Port AD interrupt ﬂag— This ﬂag asserts after a valid active edge was detected on the related pin (see Section 2.5.4.2, “Pin Interrupts and Wakeup”). This can be a rising or a falling edge based on the state of the polarity select register. An interrupt will occur if the associated interrupt enable bit is set. Writing a logic “1” to the corresponding bit ﬁeld clears the ﬂag.

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2.4.3.64 Port AD Interrupt Flag Register (PIF1AD)

Address 0x027F Access: User read/write1 Write: Anytime 76543210 R PIF1AD7 PIF1AD6 PIF1AD5 PIF1AD4 PIF1AD3 PIF1AD2 PIF1AD1 PIF1AD0 W Reset 00000000 Figure 2-63. Port AD Interrupt Flag Register (PIF1AD) Table 2-90. PIF1AD Register Field Descriptions Field Description 7-0 PIF1AD Port AD interrupt ﬂag— This ﬂag asserts after a valid active edge was detected on the related pin (see Section 2.5.4.2, “Pin Interrupts and Wakeup”). This can be a rising or a falling edge based on the state of the polarity select register. An interrupt will occur if the associated interrupt enable bit is set. Writing a logic “1” to the corresponding bit ﬁeld clears the ﬂag.

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2.5 PIM Ports - Functional Description

2.5.1 General

Each pin except BKGD can act as general-purpose I/O. In addition most pins can act as an output or input of a peripheral module.

2.5.2 Registers

A set of conﬁguration registers is common to all ports with exception of the ADC port (Table 2-91). All registers can be written at any time, however a speciﬁc conﬁguration might not become active. Example: Selecting a pullup device. This device does not become active while the port is used as a push-pull output.

2.5.2.1 Data Register (PORTx, PTx)

This register holds the value driven out to the pin if the pin is used as a general-purpose I/O. Writing to this register has only an effect on the pin if the pin is used as general-purpose output. When reading this address, the buffered state of the pin is returned if the associated data direction register bit is set to 0. If the data direction register bits are set to 1, the contents of the data register is returned. This is independent of any other conﬁguration (Figure 2-64).

2.5.2.2 Input Register (PTIx)

This register is read-only and always returns the buffered state of the pin (Figure 2-64). Table 2-91. Register availability per port1

1 Each cell represents one register with individual conﬁguration bits

(Portx, PTx) Input (PTIx) Data Direction (DDRx) Pull Enable (PERx) Polarity Select (PPSx) Wired- Or Mode (WOMx) Interrupt Enable (PIEx) Interrupt Flag (PIFx) A yes - yes yes ---- B y e s - y e s ---- C y e s - y e s ---- D y e s - y e s ---- E y e s - y e s ---- T yes yes yes yes yes - - - S yes yes yes yes yes yes - - M yes yes yes yes yes yes - - P yes yes yes yes yes - yes yes J yes yes yes yes yes - yes yes AD yes yes yes yes yes - yes yes

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2.5.2.3 Data Direction Register (DDRx)

This register deﬁnes whether the pin is used as an general-purpose input or an output. If a peripheral module controls the pin the contents of the data direction register is ignored (Figure 2-64). Independent of the pin usage with a peripheral module this register determines the source of data when reading the associated data register address (2.5.2.1/2-209). NOTE Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read on port data or port input registers, when changing the data direction register. Figure 2-64. Illustration of I/O pin functionality

2.5.2.4 Pull Device Enable Register (PERx)

This register turns on a pullup or pulldown device on the related pins determined by the associated polarity select register (2.5.2.5/2-210). The pull device becomes active only if the pin is used as an input or as a wired-or output. Some peripheral module only allow certain conﬁgurations of pull devices to become active. Refer to Section 2.3, “PIM Routing - Functional description”.

2.5.2.5 Pin Polarity Select Register (PPSx)

This register selects either a pullup or pulldown device if enabled. It becomes only active if the pin is used as an input. A pullup device can be activated if the pin is used as a wired-or output. PT DDR output enable module enable PIN PTI data out Module

Port Integration Module (S12GPIMV1) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 211

2.5.2.6 Wired-Or Mode Register (WOMx)

If the pin is used as an output this register turns off the active-high drive. This allows wired-or type connections of outputs.

2.5.2.7 Interrupt Enable Register (PIEx)

If the pin is used as an interrupt input this register serves as a mask to the interrupt ﬂag to enable/disable the interrupt.

2.5.2.8 Interrupt Flag Register (PIFx)

If the pin is used as an interrupt input this register holds the interrupt ﬂag after a valid pin event.

2.5.2.9 Pin Routing Register (PRRx)

This register allows software re-conﬁguration of the pinouts for speciﬁc peripherals in the 20 TSSOP package only.

2.5.2.10 Package Code Register (PKGCR)

This register determines the package in use. Pre programmed by factory.

2.5.3 Pin Conﬁguration Summary

The following table summarizes the effect of the various conﬁguration bits, that is data direction (DDR), output level (IO), pull enable (PE), pull select (PS) on the pin function and pull device The conﬁguration bit PS is used for two purposes: 1. Conﬁgure the sensitive interrupt edge (rising or falling), if interrupt is enabled. 2. Select either a pullup or pulldown device if PE is active.

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Table 2-92. Pin Conﬁguration Summary

2.5.4 Interrupts

This section describes the interrupts generated by the PIM and their individual sources. Vector addresses and interrupt priorities are deﬁned at MCU level.

2.5.4.1 XIRQ, IRQ Interrupts

The XIRQ pin allows requesting non-maskable interrupts after reset initialization. During reset, the X bit in the condition code register is set and any interrupts are masked until software enables them. The IRQ pin allows requesting asynchronous interrupts. The interrupt input is disabled out of reset. To enable the interrupt the IRQCR[IRQEN] bit must be set and the I bit cleared in the condition code register. The interrupt can be conﬁgured for level-sensitive or falling-edge-sensitive triggering. If IRQCR[IRQEN] is cleared while an interrupt is pending, the request will deassert. DDR IO PE PS 1 1 Always “0” on port A, B, C, D, BKGD. Always “1” on port E IE2 2 Applicable only on port P , J and AD. Function Pull Device Interrupt 0 x 0 x 0 Input 3

3 Port AD: Assuming digital input buffer enabled in ADC module (ATDDIEN) and ACMP module (ACDIEN)

0 x 1 0 0 Input 3 Pullup Disabled 0 x 1 1 0 Input 3 Pulldown Disabled 0 x 0 0 1 Input 3 Disabled Falling edge 0 x 0 1 1 Input 3 Disabled Rising edge 0 x 1 0 1 Input 3 Pullup Falling edge 0 x 1 1 1 Input 3 Pulldown Rising edge 1 0 x x 0 Output, drive to 0 Disabled Disabled 1 1 x x 0 Output, drive to 1 Disabled Disabled 1 0 x 0 1 Output, drive to 0 Disabled Falling edge 1 1 x 1 1 Output, drive to 1 Disabled Rising edge Table 2-93. PIM Interrupt Sources Module Interrupt Sources Local Enable XIRQ None IRQ IRQCR[IRQEN] Port P pin interrupt PIEP[PIEP7-PIEP0] Port J pin interrupt PIEJ[PIEJ7-PIEJ0] Port AD pin interrupt PIE0AD[PIE0AD7-PIE0AD0] PIE1AD[PIE1AD7-PIE1AD0]

Port Integration Module (S12GPIMV1) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 213 Both interrupts are capable to wake-up the device from stop mode. Means for glitch ﬁltering are not provided on these pins.

2.5.4.2 Pin Interrupts and Wakeup

Ports P, J and AD offer pin interrupt capability. The related interrupt enable (PIE) as well as the sensitivity to rising or falling edges (PPS) can be individually conﬁgured on per-pin basis. All bits/pins in a port share the same interrupt vector. Interrupts can be used with the pins conﬁgured as inputs or outputs. An interrupt is generated when a port interrupt ﬂag (PIF) and its corresponding port interrupt enable (PIE) are both set. The pin interrupt feature is also capable to wake up the CPU when it is in stop or wait mode. A digital ﬁlter on each pin prevents short pulses from generating an interrupt. A valid edge on an input is detected if 4 consecutive samples of a passive level are followed by 4 consecutive samples of an active level. Else the sampling logic is restarted. In run and wait mode the ﬁlters are continuously clocked by the bus clock. Pulses with a duration of t PULSE <n P_MASK/fbus are assuredly ﬁltered out while pulses with a duration of tPULSE >n P_PASS/fbus guarantee a pin interrupt. In stop mode the clock is generated by an RC-oscillator. The minimum pulse length varies over process conditions, temperature and voltage (Figure 2-65). Pulses with a duration of tPULSE < tP_MASK are assuredly ﬁltered out while pulses with a duration of tPULSE > tP_PASS guarantee a wakeup event. Please refer to the appendix table “Pin Interrupt Characteristics” for pulse length limits. To maximize current saving the RC oscillator is active only if the following condition is true on any individual pin: Sample count <= 4 (at active or passive level) and interrupt enabled (PIE=1) and interrupt ﬂag not set (PIF=0). Figure 2-65. Interrupt Glitch Filter (here: active low level selected) Glitch, ﬁltered out, no interrupt ﬂag set Valid pulse, interrupt ﬂag set uncertain tPULSE(min) tPULSE(max)

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2.6 Initialization/Application Information

2.6.1 Initialization

After a system reset, software should: 1. Read the PKGCR and write to it with its preset content to engage the write lock on PKGCR[PKGCR2:PKGCR0] bits protecting the device from inadvertent changes to the pin layout in normal applications. 2. Write to PRR0 in 20 TSSOP to deﬁne the module routing and to PKGCR[APICLKS7] bit in any package for API_EXTCLK. GA240 / GA192 devices only: 3. In applications using the analog functions on port C pins shared with AMPM1, AMPP1 or DACU1 the input buffers should be disabled early after reset by enabling the related mode of the DAC1 module. This shortens the time of potentially increased power consumption caused by the digital input buffers operating in the linear region.

2.6.2 Port Data and Data Direction Register writes

It is not recommended to write PORTx/PTx and DDRx in a word access. When changing the register pins from inputs to outputs, the data may have extra transitions during the write access. Initialize the port data register before enabling the outputs.

2.6.3 Enabling IRQ edge-sensitive mode

To avoid unintended IRQ interrupts resulting from writing to IRQCR while the IRQ pin is driven to active level ( IRQ=0) the following initialization sequence is recommended: 1. Mask I-bit 2. Set IRQCR[IRQEN] 3. Set IRQCR[IRQE] 4. Clear I-bit

2.6.4 ADC External Triggers ETRIG3-0

The ADC external trigger inputs ETRIG3-0 allow the synchronization of conversions to external trigger events if selected as trigger source (for details refer to ATDCTL1[ETRIGSEL] and ATDCTL1[ETRIGCH] conﬁguration bits in ADC section). These signals are related to PWM channels 3-0 to support periodic trigger applications with the ADC. Other pin functions can also be used as triggers. If a PWM channel is routed to an alternative pin, the ETRIG input function will follow the relocation accordingly. If the related PWM channel is enabled, the PWM signal as seen on the pin will drive the ETRIG input. If another signal of higher priority takes control of the pin or if on a port AD pin the input buffer is disabled,

Port Integration Module (S12GPIMV1) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 215 the ETRIG will be driven by the PWM internally. If the related PWM channel is not enabled, the ETRIG function will be triggered by other functions on the pin including general-purpose input. Table 2-94 illustrates the resulting trigger sources and their dependencies. Shaded ﬁelds apply to 20 TSSOP with shared ACMP analog input functions on port AD pins only.

2.6.5 Emulation of Smaller Packages

The Package Code Register (PKGCR) allows the emulation of smaller packages to support software development and debugging without need to have the actual target package at hand. Cross-device programming for the shared functions is also supported because smaller package sizes than the given device is offered in can be selected The PKGCR can be written in normal mode once after reset to overwrite the factory pre-programmed value, which determines the actual package. Further attempts are blocked to avoid inadvertent changes (blocking released in special mode). Trying to select a package larger than the given device is offered in will be ignored and result in the “illegal” code being written. When a smaller package is selected the pin availability and pin functionality changes according to the target package speciﬁcation. The input buffers of unused pins are disabled however the output functions of unused pins are not disabled. Therefore these pins should be don’t-cared. Depending on the different feature sets of the G-family derivatives the input buffers of speciﬁc pins, which are shared with analog functions need to be explicitly enabled before they can be used with digital input functions. For example devices featuring an ACMP module contain a control register for the related input buffers, which is not available on other family members. Also larger devices in general feature more ADC channels with individual input buffer enable bits, which are not present on smaller ones. These differences need to be accounted for when developing cross-functional code. Table 2-94. ETRIG Sources Port AD Input Buffer Enable1

1 Refer to NOTE/2-140 for enable condition

2 With higher priority than PWM on pin including ACMP enable (ACMPC[ACE]=1)

0 0 0 Const. 1 Forced High 0 0 1 Const. 1 Forced High 0 1 0 PWM Internal Link 0 1 1 PWM Internal Link 1 0 0 Pin Driven by General-Purpose Function 1 0 1 Pin Driven by Peripheral 1 1 0 Pin Driven by PWM 1 1 1 PWM Internal Link 1. Except G128/G96 in 20 TSSOP: Internal routing of PWM to ETRIG is not available.

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MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 217 Chapter 3 5V Analog Comparator (ACMPV1)

3.1 Introduction

The analog comparator (ACMP) provides a circuit for comparing two analog input voltages. Refer to the device overview section for availability on a speciﬁc device.

3.2 Features

The ACMP has the following features:

Low offset, low long-term offset drift
Selectable interrupt on rising, falling, or rising and falling edges of comparator output
Option to output comparator signal on an external pin ACMPO
Option to trigger timer input capture events
VDDX over-voltage monitoring with alternative digital output ACMPO1

3.3 Block Diagram

The block diagram of the ACMP is shown below. Rev. No. (Item No.) Date (Submitted By) Sections Affected Substantial Change(s) V00.08 13 Aug 2010 • Added register name to every bitﬁeld reference V00.09 10 Sep 2010 • Internal updates

Added preliminary VDDX over-voltage monitor application info V01.00 18 Oct 2010 • Initial version

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Figure 3-1. ACMP Block Diagram Figure 3-2. VDDX Over-Voltage Monitoring Option Interrupt Control ACMP IRQ Control & Status Register ACMOD SET ACIF ACE ACIF ACIE ACOPE ACMPO ACO ACMPP ACMPM To Input (enable) ACICE Capture SyncHold Channel ACDIEN digital buffer input INTERNAL BUS Interrupt Control ACMP IRQ Control & Status Register ACMOD SET ACIF ACE ACIF ACIE ACOPE ACMPO ACO INTERNAL BUS ACMPP ACMPM To Input (enable) ACICE Capture SyncHold Channel ACDIEN VDDX VSSX PRR2[ACROV] ACMPO1 PRR2[ACOPS] PRR2[ACOPE1] REFERENCE

5V Analog Comparator (ACMPV1) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 219

3.4 External Signals

The ACMP has two analog input signals, ACMPP and ACMPM, and one digital output, ACMPO. The associated pins are defined by the package option. The ACMPP signal is connected to the non-inverting input of the comparator. The ACMPM signal is connected to the inverting input of the comparator. Each of these signals can accept an input voltage that varies across the full 5V operating voltage range. The module monitors the voltage on these inputs independent of any other functions in use (GPIO, ADC). The raw comparator output signal can optionally be driven on an external pin.

3.5 Modes of Operation

Normal Mode The ACMP is operating when enabled and not in STOP mode. 2. Shutdown Mode The ACMP is held in shutdown mode either when disabled or during STOP mode. In this case the supply of the analog block is disconnected for power saving. ACMPO drives zero in shutdown mode.

3.6 Memory Map and Register Deﬁnition

3.6.1 Register Map

Table 3-1 shows the ACMP register map. Table 3-1. ACMP Register Map Global Address Register Name Bit 7 654321 Bit 0 0x0260 ACMPC R ACIE ACOPE ACICE ACDIEN ACMOD1 ACMOD0 ACE W 0x0261 ACMPS R ACIF A C O 000000 W = Unimplemented or Reserved

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3.6.2 Register Descriptions

3.6.2.1 ACMP Control Register (ACMPC)

Address 0x0260 Access: User read/write1 Write: Anytime 76543210 R ACIE ACOPE ACICE ACDIEN ACMOD1 ACMOD0 ACE W Reset 00000000 Figure 3-3. ACMP Control Register (ACMPC) Table 3-2. ACMPC Register Field Descriptions Field Description ACIE ACMP Interrupt Enable— Enables the ACMP interrupt.

0 Interrupt disabled

1 Interrupt enabled

ACMP Output Pin Enable— Enables raw comparator output on external ACMPO pin.

0 ACMP output not available

1 ACMP output is driven out on ACMPO

ACMP Input Capture Enable— Establishes internal link to a timer input capture channel. When enabled, the associated timer pin is disconnected from the timer input. Refer to ACE description to account for initialization delay on this path.

0 Timer link disabled

1 ACMP output connected to input capture channel 5

ACMP Digital Input Buffer Enable— Enables the input buffers on ACMPP and ACMPM for the pins to be used with digital functions. Note: If this bit is set while simultaneously using the pin as an analog port, there is potentially increased power consumption because the digital input buffer may be in the linear region.

0 Input buffers disabled on ACMPP and ACMPM

1 Input buffers enabled on ACMPP and ACMPM

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3.6.2.2 ACMP Status Register (ACMPS)

[1:0] ACMP Mode— Selects the type of compare event setting ACIF .

00 Flag setting disabled

01 Comparator output rising edge

10 Comparator output falling edge

11 Comparator output rising or falling edge

ACMP Enable— This bit enables the ACMP module and takes it into normal mode (see Section 3.5, “Modes of Operation”). This bit also connects the related input pins with the module’s low pass input ﬁlters. When the module is not enabled, it remains in low power shutdown mode. Note: After setting ACE=1 an initialization delay of 63 bus clock cycles must be accounted for. During this time the comparator output path to all subsequent logic (ACO, ACIF , timer link, excl. ACMPO) is held at its current state. When resetting ACE to 0 the current state of the comparator will be maintained.

0 ACMP disabled

1 ACMP enabled

Address 0x0261 Access: User read/write Write: ACIF: Anytime, write 1 to clear ACO: Never 76543210 R ACIF A C O 000000 W Reset 00000000 Figure 3-4. ACMP Status Register (ACMPS) Table 3-3. ACMPS Register Field Descriptions Field Description ACIF ACMP Interrupt Flag— ACIF is set when a compare event occurs. Compare events are deﬁned by ACMOD[1:0]. Writing a logic “1” to the bit ﬁeld clears the ﬂag.

0 Compare event has not occurred

1 Compare event has occurred

ACMP Output— Reading ACO returns the current value of the synchronized ACMP output. Refer to ACE description to account for initialization delay on this path. Table 3-2. ACMPC Register Field Descriptions (continued) Field Description

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3.7 Functional Description

The ACMP compares two analog input voltages applied to ACMPM and ACMPP. The comparator output is high when the voltage at the non-inverting input is greater than the voltage at the inverting input, and is low when the non-inverting input voltage is lower than the inverting input voltage. The ACMP is enabled with register bit ACMPC[ACE]. When ACMPC[ACE] is set, the input pins are connected to low-pass filters. The comparator output is disconnected from the subsequent logic, which is held at its state for 63 bus clock cycles after setting ACMPC[ACE] to “1” to mask potential glitches. This initialization delay must be accounted for before the first comparison result can be expected. The initial hold state after reset is zero, thus if input voltages are set to result in “true” result ACMPP >V ACMPM) before the initialization delay has passed, a flag will be set immediately after this. Similarly the flag will also be set when disabling the ACMP, then re-enabling it with the inputs changing to produce an opposite result to the hold state before the end of the initialization delay. By setting the ACMPC[ACICE] bit the gated comparator output can be connected to the synchronized timer input capture channel 5 (seeFigure 3-1). This feature can be used to generate time stamps and timer interrupts on ACMP events. The comparator output signal synchronized to the bus clock is used to read the comparator output status (ACMPS[ACO]) and to set the interrupt flag (ACMPS[ACIF]). The condition causing the interrupt flag (ACMPS[ACIF]) to assert is selected with register bits ACMPC[ACMOD1:ACMOD0]. This includes any edge configuration, that is rising, or falling, or rising and falling (toggle) edges of the comparator output. Also flag setting can be disabled. An interrupt will be generated if the interrupt enable bit (ACMPC[ACIE]) and the interrupt flag (ACMPS[ACIF]) are both set. ACMPS[ACIF] is cleared by writing a 1. The raw comparator output signal ACMPO can be driven out on an external pin by setting the ACMPC[ACOPE] bit.

3.8 Initialization/Application Information

3.8.1 VDDX Over-Voltage Monitor

The ACMP can be conﬁgured to compare the internally downscaled voltage present on the VDDX supply against a constant internal reference for over-voltage detection. In this case the ACMPM and ACMPP input signals are disconnected from the comparator. The standard output features of the ACMP like interrupt ﬂag and external digital output can be used to display the result. Alternatively pin ACMPO1 can be used as digital output to control an external component. An over-voltage event is triggered if the supply voltage on VDDX exceeds V VDDXassert. In order to setup the module for over-voltage monitoring also refer to PIM section “Pin Routing Register 2 (PRR2)”.

5V Analog Comparator (ACMPV1) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 223 The following setup is recommended to control an external component: 1. Route internal monitoring signals to ACMP inputs: PRR2[ACROV]=1 2. Enable ACMP raw signal output on ACMPO1 pin: PRR2[ACOPE1]=1 3. Select desired ACMPO1 output polarity by setting PRR2[ACOPS] 4. Conﬁgure ACMP to trigger on rising edge: ACMPC[ACMOD1:ACMOD0]=0b01 5. Enable ACMP: ACMCP[ACE]=1 NOTE Operation of the device with supply V DD35 between maximum speciﬁed operating voltage and Vassert(max) must be limited over total lifetime (refer to operating conditions in App. A). The TJ(max) speciﬁcation must be obeyed.

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MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 225 Chapter 4 Reference Voltage Attenuator (RVAV1)

4.1 Introduction

The reference voltage attenuator (RV A) provides a circuit for reduction of the ADC reference voltage difference VRH-VSSA to gain more ADC resolution.

4.2 Features

The RV A has the following features:

Attenuation of ADC reference voltage with low long-term drift

4.3 Block Diagram

The block diagram of the RVA module is shown below. Refer to device overview section “ADC VRH/VRL Signal Connection” for connection of RVA to pins and ADC module. Rev. No. (Item No.) Date (Submitted By) Sections Affected Substantial Change(s) V00.05 09 Jun 2010 • Added appendix title in note to reference reduced ADC clock

Orthographical corrections aligned to Freescale Publications Style Guide V00.06 01 Jul 2010 • Aligned to S12 register guidelines V01.00 18 Oct 2010 • Initial version

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Figure 4-1. RVA Module Block Diagram

4.4 External Signals

The RVA has two external input signals, VRH and VSSA.

4.5 Modes of Operation

Attenuation Mode The RV A is attenuating the reference voltage when enabled by the register control bit and the MCU not being in STOP mode. 2. Bypass Mode The RV A is in bypass mode either when disabled or during STOP mode. In these cases the resistor ladder of the RV A is disconnected for power saving. VRH_INT VRL_INT to ADC RVA RVAON VSSA VRH R STOP

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4.6 Memory Map and Register Deﬁnition

4.6.1 Register Map

Table 4-1 shows the RV A register map. Table 4-1. RVA Register Map

4.6.2 Register Descriptions

4.6.2.1 RVA Control Register (RVACTL)

Register Name Bit 7 654321 Bit 0 0x0276 RVACTL R 0000000 RVAON W = Unimplemented or Reserved Address 0x0276 Access: User read/write1 Write: Anytime 76543210 R 0000000 RVAON W Reset 00000000 Figure 4-2. RVA Control Register (RVACTL) Table 4-2. RVACTL Register Field Descriptions Field Description RVAON RVA On — This bit turns on the reference voltage attenuation.

0 RVA in bypass mode

1 RVA in attenuation mode

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4.7 Functional Description

The RV A is a prescaler for the ADC reference voltage. If the attenuation is turned off the resistive divider is disconnected from VSSA, VRH_INT is connected to VRH and VRL_INT is connected to VSSA. In this mode the attenuation is bypassed and the resistive divider does not draw current. If the attenuation is turned on the resistive divider is connected to VSSA, VRH_INT and VRL_INT are connected to intermediate voltage levels: VRH_INT = 0.9 * (VRH - VSSA) + VSSA Eqn. 4-1 VRL_INT = 0.4 * (VRH - VSSA) + VSSA Eqn. 4-2 The attenuated reference voltage difference (VRH_INT - VRL_INT) equals 50% of the input reference voltage difference (VRH - VSSA). With reference voltage attenuation the resolution of the ADC is improved by a factor of 2. NOTE In attenuation mode the maximum ADC clock is reduced. Please refer to the conditions in appendix A “ATD Accuracy”, table “ATD Conversion Performance 5V range, RV A enabled”.

MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 229 Chapter 5 S12G Memory Map Controller (S12GMMCV1) Table 5-1. Revision History Table

5.1 Introduction

The S12GMMC module controls the access to all internal memories and peripherals for the CPU12 and S12SBDM module. It regulates access priorities and determines the address mapping of the on-chip ressources. Figure 5-1 shows a block diagram of the S12GMMC module.

5.1.1 Glossary

5.1.2 Overview

The S12GMMC connects the CPU12’s and the S12SBDM’s bus interfaces to the MCU’s on-chip resources (memories and peripherals). It arbitrates the bus accesses and determines all of the MCU’s memory maps. Furthermore, the S12GMMC is responsible for constraining memory accesses on secured devices and for selecting the MCU’s functional mode. Rev. No. (Item No.) Date (Submitted By) Sections Affected Substantial Change(s) 01.02 20-May 2010 Updates for S12VR48 and S12VR64 01.03 26-Jul 2010 01.04 20-Aug 2010 Table 5-2. Glossary Of Terms Term Deﬁnition Local Addresses Address within the CPU12’s Local Address Map ( Figure 5-11) Global Address Address within the Global Address Map ( Figure 5-11) Aligned Bus Access Bus access to an even address. Misaligned Bus Access Bus access to an odd address. NS Normal Single-Chip Mode SS Special Single-Chip Mode Unimplemented Address Ranges Address ranges which are not mapped to any on-chip resource. NVM Non-volatile Memory; Flash or EEPROM IFR NVM Information Row. Refer to FTMRG Block Guide

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5.1.3 Features

The main features of this block are:

Paging capability to support a global 256 KByte memory address space
Bus arbitration between the masters CPU12, S12SBDM to different resources.
MCU operation mode control
MCU security control
Generation of system reset when CPU12 accesses an unimplemented address (i.e., an address which does not belong to any of the on-chip modules) in single-chip modes

5.1.4 Modes of Operation

The S12GMMC selects the MCU’s functional mode. It also determines the devices behavior in secured and unsecured state.

5.1.4.1 Functional Modes

Two functional modes are implemented on devices of the S12G product family:

Normal Single Chip (NS) The mode used for running applications.
Special Single Chip Mode (SS) A debug mode which causes the device to enter BDM Active Mode after each reset. Peripherals may also provide special debug features in this mode.

5.1.4.2 Security

S12G devices can be secured to prohibit external access to the on-chip ﬂash. The S12GMMC module determines the access permissions to the on-chip memories in secured and unsecured state.

5.1.5 Block Diagram

Figure 5-1 shows a block diagram of the S12GMMC.

S12G Memory Map Controller (S12GMMCV1) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 231 Figure 5-1. S12GMMC Block Diagram

5.2 External Signal Description

The S12GMMC uses two external pins to determine the devices operating mode: RESET and MODC (Figure 5-3) See Device User Guide (DUG) for the mapping of these signals to device pins.

5.3 Memory Map and Registers

5.3.1 Module Memory Map

A summary of the registers associated with the S12GMMC block is shown in Figure 5-2. Detailed descriptions of the registers and bits are given in the subsections that follow. Table 5-3. External System Pins Associated With S12GMMC Pin Name Pin Functions Description RESET (See Section Device Overview) RESET The RESET pin is used the select the MCU’s operating mode. MODC (See Section Device Overview) MODC The MODC pin is captured at the rising edge of the RESET pin. The captured value determines the MCU’s operating mode. CPUBDM Target Bus Controller DBG MMC Address Decoder & Priority PeripheralsFlashEEPROM RAM

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5.3.2 Register Descriptions

This section consists of the S12GMMC control register descriptions in address order.

5.3.2.1 Mode Register (MODE)

0x000A Reserved R 000000 0 0 W 0x000B MODE R MODC 00000 0 0 W 0x0010 Reserved R 000000 0 0 W 0x0011 DIRECT R DP15 DP14 DP13 DP12 DP11 DP10 DP9 DP8W 0x0012 Reserved R 000000 0 0 W 0x0013 MMCCTL1 R 000000 0 NVMRESW 0x0014 Reserved R 000000 0 0 W 0x0015 PPAGE R 0000 PIX3 PIX2 PIX1 PIX0W 0x0016- 0x0017 Reserved R 000000 0 0 W = Unimplemented or Reserved Figure 5-2. MMC Register Summary Address: 0x000B 76543210 R MODC 0000000 W Reset MODC 1 0000000 1. External signal (see Table 5-3). = Unimplemented or Reserved Figure 5-3. Mode Register (MODE)

S12G Memory Map Controller (S12GMMCV1) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 233 Read: Anytime. Write: Only if a transition is allowed (see Figure 5-4). The MODC bit of the MODE register is used to select the MCU’s operating mode. Figure 5-4. Mode Transition Diagram when MCU is Unsecured

5.3.2.2 Direct Page Register (DIRECT)

Read: Anytime Write: anytime in special SS, write-once in NS. This register determines the position of the 256 Byte direct page within the memory map.It is valid for both global and local mapping scheme. Table 5-4. MODE Field Descriptions Field Description MODC Mode Select Bit — This bit controls the current operating mode during RESET high (inactive). The external mode pin MODC determines the operating mode during RESET low (active). The state of the pin is registered into the respective register bit after the RESET signal goes inactive (see Figure 5-4). Write restrictions exist to disallow transitions between certain modes. Figure 5-4 illustrates all allowed mode changes. Attempting non authorized transitions will not change the MODE bit, but it will block further writes to the register bit except in special modes. Write accesses to the MODE register are blocked when the device is secured. Address: 0x0011 76543210 R DP15 DP14 DP13 DP12 DP11 DP10 DP9 DP8 W Reset 00000000 Figure 5-5. Direct Register (DIRECT) Normal Single-Chip Special Single-Chip (SS) RESET (NS)

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Figure 5-6. DIRECT Address Mapping Example 5-1. This example demonstrates usage of the Direct Addressing Mode MOVB #$04,DIRECT ;Set DIRECT register to 0x04. From this point on, all memory ;accesses using direct addressing mode will be in the local ;address range from 0x0400 to 0x04FF. LDY <$12 ;Load the Y index register from 0x0412 (direct access).

5.3.2.3 MMC Control Register (MMCCTL1)

Read: Anytime. Write: Anytime. The NVMRES bit maps 16k of internal NVM resources (see Section FTMRG) to the global address space 0x04000 to 0x07FFF. Table 5-5. DIRECT Field Descriptions Field Description 7–0 DP[15:8] Direct Page Index Bits 15–8 — These bits are used by the CPU when performing accesses using the direct addressing mode. These register bits form bits [15:8] of the local address (see Figure 5-6). Address: 0x0013 76543210 R 0000000 NVMRES W Reset 00000000 = Unimplemented or Reserved Figure 5-7. MMC Control Register (MMCCTL1) Table 5-6. MODE Field Descriptions Field Description NVMRES Map internal NVM resources into the global memory map Write: Anytime This bit maps internal NVM resources into the global address space. 0 Program ﬂash is mapped to the global address range from 0x04000 to 0x07FFF. 1 NVM resources are mapped to the global address range from 0x04000 to 0x07FFF. Bit15 Bit0Bit7 CPU Address [15:0] Bit8 DP [15:8]

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5.3.2.4 Program Page Index Register (PPAGE)

Read: Anytime Write: Anytime The four index bits of the PPAGE register select a 16K page in the global memory map (Figure 5-11). The selected 16K page is mapped into the paging window ranging from local address 0x8000 to 0xBFFF. Figure 5-9 illustrates the translation from local to global addresses for accesses to the paging window. The CPU has special access to read and write this register directly during execution of CALL and RTC instructions. Figure 5-9. PPAGE Address Mapping NOTE Writes to this register using the special access of the CALL and RTC instructions will be complete before the end of the instruction execution. The ﬁxed 16KB page from 0x0000 to 0x3FFF is the page number 0xC. Parts of this page are covered by Registers, EEPROM and RAM space. See SoC Guide for details. The ﬁxed 16KB page from 0x4000–0x7FFF is the page number 0xD. Address: 0x0015 76543210 R 0000 PIX3 PIX2 PIX1 PIX0 W Reset 00001110 Figure 5-8. Program Page Index Register (PPAGE) Table 5-7. PPAGE Field Descriptions Field Description 3–0 PIX[3:0] Program Page Index Bits 3–0 — These page index bits are used to select which of the 256 ﬂash array pages is to be accessed in the Program Page Window. Bit14 Bit0 Address [13:0]PPAGE Register [3:0] Global Address [17:0] Bit13Bit17 Address: CPU Local Address or BDM Local Address

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The reset value of 0xE ensures that there is linear Flash space available between addresses 0x0000 and 0xFFFF out of reset. The ﬁxed 16KB page from 0xC000-0xFFFF is the page number 0xF.

5.4 Functional Description

The S12GMMC block performs several basic functions of the S12G sub-system operation: MCU operation modes, priority control, address mapping, select signal generation and access limitations for the system. Each aspect is described in the following subsections.

5.4.1 MCU Operating Modes

Normal single chip mode This is the operation mode for running application code. There is no external bus in this mode.
Special single chip mode This mode is generally used for debugging operation, boot-strapping or security related operations. The active background debug mode is in control of the CPU code execution and the BDM ﬁrmware is waiting for serial commands sent through the BKGD pin.

5.4.2 Memory Map Scheme

5.4.2.1 CPU and BDM Memory Map Scheme

The BDM ﬁrmware lookup tables and BDM register memory locations share addresses with other modules; however they are not visible in the memory map during user’s code execution. The BDM memory resources are enabled only during the READ_BD and WRITE_BD access cycles to distinguish between accesses to the BDM memory area and accesses to the other modules. (Refer to BDM Block Guide for further details). When the MCU enters active BDM mode, the BDM ﬁrmware lookup tables and the BDM registers become visible in the local memory map in the range 0xFF00-0xFFFF (global address 0x3_FF00 - 0x3_FFFF) and the CPU begins execution of ﬁrmware commands or the BDM begins execution of hardware commands. The resources which share memory space with the BDM module will not be visible in the memory map during active BDM mode. Please note that after the MCU enters active BDM mode the BDM ﬁrmware lookup tables and the BDM registers will also be visible between addresses 0xBF00 and 0xBFFF if the PPAGE register contains value of 0x0F.

5.4.2.1.1 Expansion of the Local Address Map

Expansion of the CPU Local Address Map The program page index register in S12GMMC allows accessing up to 256KB of address space in the global memory map by using the four index bits (PPAGE[3:0]) to page 16x16 KB blocks into the program page window located from address 0x8000 to address 0xBFFF in the local CPU memory map.

S12G Memory Map Controller (S12GMMCV1) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 237 The page value for the program page window is stored in the PPAGE register. The value of the PPAGE register can be read or written by normal memory accesses as well as by the CALL and RTC instructions. Control registers, vector space and parts of the on-chip memories are located in unpaged portions of the 64KB local CPU address space. The starting address of an interrupt service routine must be located in unpaged memory unless the user is certain that the PPAGE register will be set to the appropriate value when the service routine is called. However an interrupt service routine can call other routines that are in paged memory. The upper 16KB block of the local CPU memory space (0xC000–0xFFFF) is unpaged. It is recommended that all reset and interrupt vectors point to locations in this area or to the other unmapped pages sections of the local CPU memory map. Expansion of the BDM Local Address Map PPAGE and BDMPPR register is also used for the expansion of the BDM local address to the global address. These registers can be read and written by the BDM. The BDM expansion scheme is the same as the CPU expansion scheme. The four BDMPPR Program Page index bits allow access to the full 256KB address map that can be accessed with 18 address bits. The BDM program page index register (BDMPPR) is used only when the feature is enabled in BDM and, in the case the CPU is executing a ﬁrmware command which uses CPU instructions, or by a BDM hardware commands. See the BDM Block Guide for further details. (see Figure 5-10).

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Figure 5-10. BDM HARDWARE COMMAND BDM FIRMWARE COMMAND Bit14 Bit0 BDM Local Address [13:0]BDMPPR Register [3:0] Global Address [17:0] Bit13Bit17 Bit14 Bit0 CPU Local Address [13:0]BDMPPR Register [3:0] Global Address [17:0] Bit13Bit17

S12G Memory Map Controller (S12GMMCV1) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 239 Figure 5-11. Local to Global Address Mapping Paging Window 0x3_FFFF Local CPU and BDM Memory Map Global Memory Map 0xFFFF 0xC000 0x0_0400 0x0_0000 0x3_C000 0x0000 0x8000 0x0400 0x4000 0x0_4000 Paging Window Flash Space Flash Space RAMRAM UnimplementedUnimplemented Flash SpaceFlash Space Flash SpaceFlash Space Flash SpaceFlash Space Register SpaceRegister Space Internal NVM Resources Internal NVM Resources Flash SpaceFlash Space Flash SpaceFlash Space Flash SpaceFlash Space Flash SpaceFlash Space EEPROMEEPROM EEPROMEEPROM Page 0x1Page 0x1 Page 0xFPage 0xF Page 0xDPage 0xD Register SpaceRegister Space Page 0xCPage 0xC Page 0xEPage 0xE Page 0xFPage 0xF Page 0xDPage 0xD Page 0xCPage 0xC NVMRES=0NVMRES=0 NVMRES=1NVMRES=1 Flash SpaceFlash Space Page 0x2Page 0x2 0x3_0000 0x3_4000 0x3_8000 0x0_8000 RAMRAM

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5.4.3 Unimplemented and Reserved Address Ranges

The S12GMMC is capable of mapping up 240K of ﬂash, up to 4K of EEPROM and up to 11K of RAM into the global memory map. Smaller devices of the S12G-family do not utilize all of the available address space. Address ranges which are not associated with one of the on-chip memories fall into two categories: Unimplemented addresses and reserved addresses. Unimplemented addresses are not mapped to any of the on-chip memories. The S12GMMC is aware that accesses to these address location have no destination and triggers a system reset (illegal address reset) whenever they are attempted by the CPU. The BDM is not able to trigger illegal address resets. Reserved addresses are associated with a memory block on the device, even though the memory block does not contain the resources to ﬁll the address space. The S12GMMC is not aware that the associated memory does not physically exist. It does not trigger an illegal address reset when accesses to reserved locations are attempted. Table 5-8 shows the global address ranges of all members of the S12G-family. Table 5-8. Global Address Ranges S12GN16 S12GN32 S12G48, S12GN48 S12G64 S12G96 S12G128 S12G192 S12G240 0x00000- 0x003FF Register Space 0x00400- 0x005FF 0.5k 1k 1.5k 2k 3k 4k 4k 4k 0x00600- 0x007FF Reserved EEPROM 0x00800- 0x009FF 0x00A00- 0x00BFF Reserved 0x00C00- 0x00FFF 0x01000- 0x013FF Reserved 0x01400- 0x01FFF Unimplemented 0x02000- 0x2FFF 0x03000- 0x037FF RAM 0x03800- 0x03BFF Reserved 0x03C00- 0x03FFF 1k 2k 4k 4k 8k 8k 11k 11k

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5.4.4 Prioritization of Memory Accesses

On S12G devices, the CPU and the BDM are not able to access the memory in parallel. An arbitration occurs whenever both modules attempt a memory access at the same time. CPU accesses are handled with higher priority than BDM accesses unless the BDM module has been stalled for more then 128 bus cycles. In this case the pending BDM access will be processed immediately.

5.4.5 Interrupts

The S12GMMC does not generate any interrupts. 0x04000- 0x07FFF (NVMRES=1) Internal NVM Resources (for details refer to section FTMRG) 0x04000- 0x07FFF (NVMRES=0) Reserved 0x08000- 0x0FFFF 0x08000- 0x1FFFF Unimplemented 0x20000- 0x27FFF Reserved 0x28000- 0x2FFFF 0x30000- 0x33FFF Reserved 0x34000- 0x37FFF Flash 0x38000- 0x3BFFF Reserved 0x3C000- 0x3FFFF 16k 32k 48k 64k 96k 128k 192k 240k Table 5-8. Global Address Ranges S12GN16 S12GN32 S12G48, S12GN48 S12G64 S12G96 S12G128 S12G192 S12G240

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MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 243 Chapter 6 Interrupt Module (S12SINTV1)

6.1 Introduction

The INT module decodes the priority of all system exception requests and provides the applicable vector for processing the exception to the CPU. The INT module supports:

I bit and X bit maskable interrupt requests
A non-maskable unimplemented op-code trap
A non-maskable software interrupt (SWI) or background debug mode request
Three system reset vector requests
A spurious interrupt vector Each of the I bit maskable interrupt requests is assigned to a ﬁxed priority level.

6.1.1 Glossary

Table 6-2 contains terms and abbreviations used in the document.

6.1.2 Features

Interrupt vector base register (IVBR)
One spurious interrupt vector (at address vector base 1 + 0x0080). Version Number Revision Date Effective Date Author Description of Changes 01.02 13 Sep 2007 updates for S12P family devices: - re-added XIRQ and IRQ references since this functionality is used on devices without D2D - added low voltage reset as possible source to the pin reset vector 01.03 21 Nov 2007 added clariﬁcation of “Wake-up from STOP or WAIT by XIRQ with X bit set” feature 01.04 20 May 2009 added footnote about availability of “Wake-up from STOP or WAIT by XIRQ with X bit set” feature Table 6-2. Terminology Term Meaning CCR Condition Code Register (in the CPU) ISR Interrupt Service Routine MCU Micro-Controller Unit

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2–58 I bit maskable interrupt vector requests (at addresses vector base + 0x0082–0x00F2).
I bit maskable interrupts can be nested.
One X bit maskable interrupt vector request (at address vector base + 0x00F4).
One non-maskable software interrupt request (SWI) or background debug mode vector request (at address vector base + 0x00F6).
One non-maskable unimplemented op-code trap (TRAP) vector (at address vector base + 0x00F8).
Three system reset vectors (at addresses 0xFFFA–0xFFFE).
Determines the highest priority interrupt vector requests, drives the vector to the bus on CPU request
Wakes up the system from stop or wait mode when an appropriate interrupt request occurs.

6.1.3 Modes of Operation

Run mode This is the basic mode of operation.
Wait mode In wait mode, the clock to the INT module is disabled. The INT module is however capable of waking-up the CPU from wait mode if an interrupt occurs. Please refer toSection 6.5.3, “Wake Up from Stop or Wait Mode” for details.
Stop Mode In stop mode, the clock to the INT module is disabled. The INT module is however capable of waking-up the CPU from stop mode if an interrupt occurs. Please refer toSection 6.5.3, “Wake Up from Stop or Wait Mode” for details.
Freeze mode (BDM active) In freeze mode (BDM active), the interrupt vector base register is overridden internally. Please refer to Section 6.3.1.1, “Interrupt Vector Base Register (IVBR)” for details.

6.1.4 Block Diagram

Figure 6-1 shows a block diagram of the INT module. 1. The vector base is a 16-bit address which is accumulated from the contents of the interrupt vector base register (IVBR, used as upper byte) and 0x00 (used as lower byte).

Interrupt Module (S12SINTV1) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 245 Figure 6-1. INT Block Diagram

6.2 External Signal Description

The INT module has no external signals.

6.3 Memory Map and Register Deﬁnition

This section provides a detailed description of all registers accessible in the INT module.

6.3.1 Register Descriptions

This section describes in address order all the INT registers and their individual bits.

6.3.1.1 Interrupt Vector Base Register (IVBR)

Read: Anytime Write: Anytime Address: 0x0120 76543210 R IVB_ADDR[7:0] W Reset 11111111 Figure 6-2. Interrupt Vector Base Register (IVBR) Wake Up IVBR Interrupt Requests Interrupt Requests CPU Vector Address Peripheral To CPU Priority Decoder Non I bit Maskable Channels I bit Maskable Channels

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6.4 Functional Description

The INT module processes all exception requests to be serviced by the CPU module. These exceptions include interrupt vector requests and reset vector requests. Each of these exception types and their overall priority level is discussed in the subsections below.

6.4.1 S12S Exception Requests

The CPU handles both reset requests and interrupt requests. A priority decoder is used to evaluate the priority of pending interrupt requests.

6.4.2 Interrupt Prioritization

The INT module contains a priority decoder to determine the priority for all interrupt requests pending for the CPU. If more than one interrupt request is pending, the interrupt request with the higher vector address wins the prioritization. The following conditions must be met for an I bit maskable interrupt request to be processed. 1. The local interrupt enabled bit in the peripheral module must be set. 2. The I bit in the condition code register (CCR) of the CPU must be cleared. 3. There is no SWI, TRAP, or X bit maskable request pending. NOTE All non I bit maskable interrupt requests always have higher priority than the I bit maskable interrupt requests. If the X bit in the CCR is cleared, it is possible to interrupt an I bit maskable interrupt by an X bit maskable interrupt. It is possible to nest non maskable interrupt requests, for example by nesting SWI or TRAP calls. Since an interrupt vector is only supplied at the time when the CPU requests it, it is possible that a higher priority interrupt request could override the original interrupt request that caused the CPU to request the vector. In this case, the CPU will receive the highest priority vector and the system will process this interrupt request ﬁrst, before the original interrupt request is processed. Table 6-3. IVBR Field Descriptions Field Description 7–0 IVB_ADDR[7:0] Interrupt Vector Base Address Bits — These bits represent the upper byte of all vector addresses. Out of reset these bits are set to 0xFF (that means vectors are located at 0xFF80–0xFFFE) to ensure compatibility to HCS12. Note: A system reset will initialize the interrupt vector base register with “0xFF” before it is used to determine the reset vector address. Therefore, changing the IVBR has no effect on the location of the three reset vectors (0xFFFA–0xFFFE). Note: If the BDM is active (that means the CPU is in the process of executing BDM ﬁrmware code), the contents of IVBR are ignored and the upper byte of the vector address is ﬁxed as “0xFF”. This is done to enable handling of all non-maskable interrupts in the BDM ﬁrmware.

Interrupt Module (S12SINTV1) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 247 If the interrupt source is unknown (for example, in the case where an interrupt request becomes inactive after the interrupt has been recognized, but prior to the CPU vector request), the vector address supplied to the CPU will default to that of the spurious interrupt vector. NOTE Care must be taken to ensure that all interrupt requests remain active until the system begins execution of the applicable service routine; otherwise, the exception request may not get processed at all or the result may be a spurious interrupt request (vector at address (vector base + 0x0080)).

6.4.3 Reset Exception Requests

The INT module supports three system reset exception request types (please refer to the Clock and Reset generator module for details): 1. Pin reset, power-on reset or illegal address reset, low voltage reset (if applicable) 2. Clock monitor reset request 3. COP watchdog reset request

6.4.4 Exception Priority

The priority (from highest to lowest) and address of all exception vectors issued by the INT module upon request by the CPU is shown in Table 6-4. Table 6-4. Exception Vector Map and Priority Vector Address1 1 16 bits vector address based Source 0xFFFE Pin reset, power-on reset, illegal address reset, low voltage reset (if applicable) 0xFFFC Clock monitor reset 0xFFFA COP watchdog reset (Vector base + 0x00F8) Unimplemented opcode trap (Vector base + 0x00F6) Software interrupt instruction (SWI) or BDM vector request (Vector base + 0x00F4) X bit maskable interrupt request (XIRQ or D2D error interrupt)

2 D2D error interrupt on MCUs featuring a D2D initiator module, otherwise XIRQ pin interrupt

(Vector base + 0x00F2) IRQ or D2D interrupt request 3

3 D2D interrupt on MCUs featuring a D2D initiator module, otherwise IRQ pin interrupt

(Vector base + 0x00F0–0x0082) Device speciﬁc I bit maskable interrupt sources (priority determined by the low byte of the vector address, in descending order) (Vector base + 0x0080) Spurious interrupt

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6.5 Initialization/Application Information

6.5.1 Initialization

After system reset, software should: 1. Initialize the interrupt vector base register if the interrupt vector table is not located at the default location (0xFF80–0xFFF9). 2. Enable I bit maskable interrupts by clearing the I bit in the CCR. 3. Enable the X bit maskable interrupt by clearing the X bit in the CCR.

6.5.2 Interrupt Nesting

The interrupt request scheme makes it possible to nest I bit maskable interrupt requests handled by the CPU.

I bit maskable interrupt requests can be interrupted by an interrupt request with a higher priority. I bit maskable interrupt requests cannot be interrupted by other I bit maskable interrupt requests per default. In order to make an interrupt service routine (ISR) interruptible, the ISR must explicitly clear the I bit in the CCR (CLI). After clearing the I bit, other I bit maskable interrupt requests can interrupt the current ISR. An ISR of an interruptible I bit maskable interrupt request could basically look like this: 1. Service interrupt, that is clear interrupt ﬂags, copy data, etc. 2. Clear I bit in the CCR by executing the instruction CLI (thus allowing other I bit maskable interrupt requests) 3. Process data 4. Return from interrupt by executing the instruction RTI

6.5.3 Wake Up from Stop or Wait Mode

6.5.3.1 CPU Wake Up from Stop or Wait Mode

Every I bit maskable interrupt request is capable of waking the MCU from stop or wait mode. To determine whether an I bit maskable interrupts is qualiﬁed to wake-up the CPU or not, the same conditions as in normal run mode are applied during stop or wait mode:

If the I bit in the CCR is set, all I bit maskable interrupts are masked from waking-up the MCU. Since there are no clocks running in stop mode, only interrupts which can be asserted asynchronously can wake-up the MCU from stop mode. The X bit maskable interrupt request can wake up the MCU from stop or wait mode at anytime, even if the X bit in CCR is set 1. The capability of the XIRQ pin to wake-up the MCU with the X bit set may not be available if, for example, theXIRQ pin is shared with other peripheral modules on the device. Please refer to the Device section of the MCU reference manual for details.

Interrupt Module (S12SINTV1) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 249 If the X bit maskable interrupt request is used to wake-up the MCU with the X bit in the CCR set, the associated ISR is not called. The CPU then resumes program execution with the instruction following the W AI or STOP instruction. This features works following the same rules like any interrupt request, that is care must be taken that the X interrupt request used for wake-up remains active at least until the system begins execution of the instruction following the W AI or STOP instruction; otherwise, wake-up may not occur.

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MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 251 Chapter 7 Background Debug Module (S12SBDMV1) Table 7-1. Revision History

7.1 Introduction

This section describes the functionality of the background debug module (BDM) sub-block of the HCS12S core platform. The background debug module (BDM) sub-block is a single-wire, background debug system implemented in on-chip hardware for minimal CPU intervention. All interfacing with the BDM is done via the BKGD pin. The BDM has enhanced capability for maintaining synchronization between the target and host while allowing more ﬂexibility in clock rates. This includes a sync signal to determine the communication rate and a handshake signal to indicate when an operation is complete. The system is backwards compatible to the BDM of the S12 family with the following exceptions:

TAGGO command not supported by S12SBDM
External instruction tagging feature is part of the DBG module
S12SBDM register map and register content modiﬁed
Family ID readable from BDM ROM at global address 0x3_FF0F in active BDM (value for devices with HCS12S core is 0xC2)
Clock switch removed from BDM (CLKSW bit removed from BDMSTS register)

7.1.1 Features

The BDM includes these distinctive features:

Single-wire communication with host development system
Enhanced capability for allowing more ﬂexibility in clock rates
SYNC command to determine communication rate Revision Number Date Sections Affected Summary of Changes 1.03 14.May.2009 Internal Conditional text only 1.04 30.Nov.2009 Internal Conditional text only 1.05 07.Dec.2010 Standardized format of revision history table header. 7.2/7-253 Corrected BPAE bit description. Removed references to ﬁxed VCO frequencies

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GO_UNTIL command
Hardware handshake protocol to increase the performance of the serial communication
Active out of reset in special single chip mode
Nine hardware commands using free cycles, if available, for minimal CPU intervention
Hardware commands not requiring active BDM
14 ﬁrmware commands execute from the standard BDM ﬁrmware lookup table
Software control of BDM operation during wait mode
When secured, hardware commands are allowed to access the register space in special single chip mode, if the Flash erase tests fail.
Family ID readable from BDM ROM at global address 0x3_FF0F in active BDM (value for devices with HCS12S core is 0xC2)
BDM hardware commands are operational until system stop mode is entered

7.1.2 Modes of Operation

BDM is available in all operating modes but must be enabled before ﬁrmware commands are executed. Some systems may have a control bit that allows suspending the function during background debug mode.

7.1.2.1 Regular Run Modes

All of these operations refer to the part in run mode and not being secured. The BDM does not provide controls to conserve power during run mode.

Normal modes General operation of the BDM is available and operates the same in all normal modes.
Special single chip mode In special single chip mode, background operation is enabled and active out of reset. This allows programming a system with blank memory.

7.1.2.2 Secure Mode Operation

If the device is in secure mode, the operation of the BDM is reduced to a small subset of its regular run mode operation. Secure operation prevents access to Flash other than allowing erasure. For more information please see Section 7.4.1, “Security”.

7.1.2.3 Low-Power Modes

The BDM can be used until stop mode is entered. When CPU is in wait mode all BDM ﬁrmware commands as well as the hardware BACKGROUND command cannot be used and are ignored. In this case the CPU can not enter BDM active mode, and only hardware read and write commands are available. Also the CPU can not enter a low power mode (stop or wait) during BDM active mode. In stop mode the BDM clocks are stopped. When BDM clocks are disabled and stop mode is exited, the BDM clocks will restart and BDM will have a soft reset (clearing the instruction register, any command in progress and disable the ACK function). The BDM is now ready to receive a new command.

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7.1.3 Block Diagram

A block diagram of the BDM is shown in Figure 7-1. Figure 7-1. BDM Block Diagram

7.2 External Signal Description

A single-wire interface pin called the background debug interface (BKGD) pin is used to communicate with the BDM system. During reset, this pin is a mode select input which selects between normal and special modes of operation. After reset, this pin becomes the dedicated serial interface pin for the background debug mode. The communication rate of this pin is always the BDM clock frequency deﬁned at device level (refer to device overview section). When modifying the VCO clock please make sure that the communication rate is adapted accordingly and a communication time-out (BDM soft reset) has occurred.

7.3 Memory Map and Register Deﬁnition

7.3.1 Module Memory Map

Table 7-2 shows the BDM memory map when BDM is active. 16-Bit Shift RegisterBKGD Host System Serial Interface Data Control Register Block Register BDMSTS Instruction Code and Execution Standard BDM Firmware LOOKUP TABLE Secured BDM Firmware LOOKUP TABLE Bus Interface and Control Logic Address Data Control ClocksBDMACT TRACE ENBDM SDV UNSEC

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7.3.2 Register Descriptions

A summary of the registers associated with the BDM is shown in Figure 7-2. Registers are accessed by host-driven communications to the BDM hardware using READ_BD and WRITE_BD commands. Table 7-2. BDM Memory Map Global Address Module Size (Bytes) 0x3_FF00–0x3_FF0B BDM registers 12 0x3_FF0C–0x3_FF0E BDM ﬁrmware ROM 3 0x3_FF0F Family ID (part of BDM ﬁrmware ROM) 1 0x3_FF10–0x3_FFFF BDM ﬁrmware ROM 240 Global Address Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x3_FF00 Reserved R X X X X X X 0 0 W 0x3_FF01 BDMSTS R ENBDM BDMACT 0 SDV TRACE 0 UNSEC 0 W 0x3_FF02 Reserved R X X X X X X X X W 0x3_FF03 Reserved R X X X X X X X X W 0x3_FF04 Reserved R X X X X X X X X W 0x3_FF05 Reserved R X X X X X X X X W 0x3_FF06 BDMCCR R CCR7 CCR6 CCR5 CCR4 CCR3 CCR2 CCR1 CCR0 W 0x3_FF07 Reserved R 0 0 0 0 0 0 0 0 W = Unimplemented, Reserved = Implemented (do not alter) X = Indeterminate 0 = Always read zero Figure 7-2. BDM Register Summary

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7.3.2.1 BDM Status Register (BDMSTS)

Figure 7-3. BDM Status Register (BDMSTS) Read: All modes through BDM operation when not secured Write: All modes through BDM operation when not secured, but subject to the following: — ENBDM should only be set via a BDM hardware command if the BDM ﬁrmware commands are needed. (This does not apply in special single chip mode). — BDMACT can only be set by BDM hardware upon entry into BDM. It can only be cleared by the standard BDM ﬁrmware lookup table upon exit from BDM active mode. 0x3_FF08 BDMPPR R BPAE 000 BPP3 BPP2 BPP1 BPP0W 0x3_FF09 Reserved R 0 0 0 0 0 0 0 0 W 0x3_FF0A Reserved R 0 0 0 0 0 0 0 0 W 0x3_FF0B Reserved R 0 0 0 0 0 0 0 0 W Register Global Address 0x3_FF01 7 6 54 3 2 1 0 R ENBDM BDMACT 0S D V TRACE 0 UNSEC 0 W Reset Special Single-Chip Mode 01 1 ENBDM is read as 1 by a debugging environment in special single chip mode when the device is not secured or secured but fully erased (Flash). This is because the ENBDM bit is set by the standard BDM ﬁrmware before a BDM command can be fully transmitted and executed. 1 00 0 0 02 2 UNSEC is read as 1 by a debugging environment in special single chip mode when the device is secured and fully erased, else it is 0 and can only be read if not secure (see also bit description). All Other Modes 0 0 00 0 0 0 0 = Unimplemented, Reserved = Implemented (do not alter) 0 = Always read zero Global Address Register Name Bit 7 6 5 4 3 2 1 Bit 0 = Unimplemented, Reserved = Implemented (do not alter) X = Indeterminate 0 = Always read zero Figure 7-2. BDM Register Summary (continued)

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— All other bits, while writable via BDM hardware or standard BDM ﬁrmware write commands, should only be altered by the BDM hardware or standard ﬁrmware lookup table as part of BDM command execution. Table 7-3. BDMSTS Field Descriptions Field Description ENBDM Enable BDM — This bit controls whether the BDM is enabled or disabled. When enabled, BDM can be made active to allow ﬁrmware commands to be executed. When disabled, BDM cannot be made active but BDM hardware commands are still allowed.

0 BDM disabled

1 BDM enabled

Note: ENBDM is set out of reset in special single chip mode. In special single chip mode with the device secured, this bit will not be set until after the Flash erase verify tests are complete. BDMACT BDM Active Status — This bit becomes set upon entering BDM. The standard BDM ﬁrmware lookup table is then enabled and put into the memory map. BDMACT is cleared by a carefully timed store instruction in the standard BDM ﬁrmware as part of the exit sequence to return to user code and remove the BDM memory from the map.

0 BDM not active

1 BDM active

Shift Data Valid— This bit is set and cleared by the BDM hardware. It is set after data has been transmitted as part of a BDM ﬁrmware or hardware read command or after data has been received as part of a BDM ﬁrmware or hardware write command. It is cleared when the next BDM command has been received or BDM is exited. SDV is used by the standard BDM ﬁrmware to control program ﬂow execution.

0 Data phase of command not complete

1 Data phase of command is complete

TRACE1 BDM Firmware Command is Being Executed — This bit gets set when a BDM TRACE1 ﬁrmware command is ﬁrst recognized. It will stay set until BDM ﬁrmware is exited by one of the following BDM commands: GO or GO_UNTIL.

0 TRACE1 command is not being executed

1 TRACE1 command is being executed

Unsecure — If the device is secured this bit is only writable in special single chip mode from the BDM secure ﬁrmware. It is in a zero state as secure mode is entered so that the secure BDM ﬁrmware lookup table is enabled and put into the memory map overlapping the standard BDM ﬁrmware lookup table. The secure BDM ﬁrmware lookup table veriﬁes that the on-chip Flash is erased. This being the case, the UNSEC bit is set and the BDM program jumps to the start of the standard BDM ﬁrmware lookup table and the secure BDM ﬁrmware lookup table is turned off. If the erase test fails, the UNSEC bit will not be asserted. 0 System is in a secured mode. 1 System is in a unsecured mode. Note: When UNSEC is set, security is off and the user can change the state of the secure bits in the on-chip Flash EEPROM. Note that if the user does not change the state of the bits to “unsecured” mode, the system will be secured again when it is next taken out of reset.After reset this bit has no meaning or effect when the security byte in the Flash EEPROM is conﬁgured for unsecure mode.

Background Debug Module (S12SBDMV1) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 257 Figure 7-4. BDM CCR Holding Register (BDMCCR) Read: All modes through BDM operation when not secured Write: All modes through BDM operation when not secured NOTE When BDM is made active, the CPU stores the content of its CCR register in the BDMCCR register. However, out of special single-chip reset, the BDMCCR is set to 0xD8 and not 0xD0 which is the reset value of the CCR register in this CPU mode. Out of reset in all other modes the BDMCCR register is read zero. When entering background debug mode, the BDM CCR holding register is used to save the condition code register of the user’s program. It is also used for temporary storage in the standard BDM ﬁrmware mode. The BDM CCR holding register can be written to modify the CCR value.

7.3.2.2 BDM Program Page Index Register (BDMPPR)

Figure 7-5. BDM Program Page Register (BDMPPR) Read: All modes through BDM operation when not secured Write: All modes through BDM operation when not secured Register Global Address 0x3_FF06 7 6 5 4 3 2 1 0 R CCR7 CCR6 CCR5 CCR4 CCR3 CCR2 CCR1 CCR0 W Reset Special Single-Chip Mode 1 1 0 0 1 0 0 0 All Other Modes 0 0 0 0 0 0 0 0 Register Global Address 0x3_FF08 7 6 5 4 3 2 1 0 R BPAE 0 0 0 BPP3 BPP2 BPP1 BPP0W Reset 0 0 0 0 0 0 0 0 = Unimplemented, Reserved Table 7-4. BDMPPR Field Descriptions Field Description BPAE BDM Program Page Access Enable Bit — BPAE enables program page access for BDM hardware and ﬁrmware read/write instructions The BDM hardware commands used to access the BDM registers (READ_BD and WRITE_BD) can not be used for program page accesses even if the BPAE bit is set.

0 BDM Program Paging disabled

1 BDM Program Paging enabled

3–0 BPP[3:0] BDM Program Page Index Bits 3–0 — These bits deﬁne the selected program page. For more detailed information regarding the program page window scheme, please refer to the S12S_MMC Block Guide.

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7.3.3 Family ID Assignment

The family ID is an 8-bit value located in the BDM ROM in active BDM (at global address: 0x3_FF0F). The read-only value is a unique family ID which is 0xC2 for devices with an HCS12S core.

7.4 Functional Description

The BDM receives and executes commands from a host via a single wire serial interface. There are two types of BDM commands: hardware and ﬁrmware commands. Hardware commands are used to read and write target system memory locations and to enter active background debug mode, see Section 7.4.3, “BDM Hardware Commands”. Target system memory includes all memory that is accessible by the CPU. Firmware commands are used to read and write CPU resources and to exit from active background debug mode, see Section 7.4.4, “Standard BDM Firmware Commands”. The CPU resources referred to are the accumulator (D), X index register (X), Y index register (Y), stack pointer (SP), and program counter (PC). Hardware commands can be executed at any time and in any mode excluding a few exceptions as highlighted (see Section 7.4.3, “BDM Hardware Commands”) and in secure mode (see Section 7.4.1, “Security”). BDM ﬁrmware commands can only be executed when the system is not secure and is in active background debug mode (BDM).

7.4.1 Security

If the user resets into special single chip mode with the system secured, a secured mode BDM ﬁrmware lookup table is brought into the map overlapping a portion of the standard BDM ﬁrmware lookup table. The secure BDM ﬁrmware veriﬁes that the on-chip Flash EEPROM are erased. This being the case, the UNSEC and ENBDM bit will get set. The BDM program jumps to the start of the standard BDM ﬁrmware and the secured mode BDM ﬁrmware is turned off and all BDM commands are allowed. If the Flash does not verify as erased, the BDM ﬁrmware sets the ENBDM bit, without asserting UNSEC, and the ﬁrmware enters a loop. This causes the BDM hardware commands to become enabled, but does not enable the ﬁrmware commands. This allows the BDM hardware to be used to erase the Flash. BDM operation is not possible in any other mode than special single chip mode when the device is secured. The device can only be unsecured via BDM serial interface in special single chip mode. For more information regarding security, please see the S12S_9SEC Block Guide.

7.4.2 Enabling and Activating BDM

The system must be in active BDM to execute standard BDM ﬁrmware commands. BDM can be activated only after being enabled. BDM is enabled by setting the ENBDM bit in the BDM status (BDMSTS) register. The ENBDM bit is set by writing to the BDM status (BDMSTS) register, via the single-wire interface, using a hardware command such as WRITE_BD_BYTE. After being enabled, BDM is activated by one of the following 1. BDM is enabled and active immediately out of special single-chip reset.

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Hardware BACKGROUND command
CPU BGND instruction
Breakpoint force or tag mechanism When BDM is activated, the CPU ﬁnishes executing the current instruction and then begins executing the ﬁrmware in the standard BDM ﬁrmware lookup table. When BDM is activated by a breakpoint, the type of breakpoint used determines if BDM becomes active before or after execution of the next instruction. NOTE If an attempt is made to activate BDM before being enabled, the CPU resumes normal instruction execution after a brief delay. If BDM is not enabled, any hardware BACKGROUND commands issued are ignored by the BDM and the CPU is not delayed. In active BDM, the BDM registers and standard BDM ﬁrmware lookup table are mapped to addresses 0x3_FF00 to 0x3_FFFF. BDM registers are mapped to addresses 0x3_FF00 to 0x3_FF0B. The BDM uses these registers which are readable anytime by the BDM. However, these registers are not readable by user programs. When BDM is activated while CPU executes code overlapping with BDM ﬁrmware space the saved program counter (PC) will be auto incremented by one from the BDM ﬁrmware, no matter what caused the entry into BDM active mode (BGND instruction, BACKGROUND command or breakpoints). In such a case the PC must be set to the next valid address via a WRITE_PC command before executing the GO command.

7.4.3 BDM Hardware Commands

Hardware commands are used to read and write target system memory locations and to enter active background debug mode. Target system memory includes all memory that is accessible by the CPU such as on-chip RAM, Flash, I/O and control registers. Hardware commands are executed with minimal or no CPU intervention and do not require the system to be in active BDM for execution, although, they can still be executed in this mode. When executing a hardware command, the BDM sub-block waits for a free bus cycle so that the background access does not disturb the running application program. If a free cycle is not found within 128 clock cycles, the CPU is momentarily frozen so that the BDM can steal a cycle. When the BDM ﬁnds a free cycle, the operation does not intrude on normal CPU operation provided that it can be completed in a single cycle. However, if an operation requires multiple cycles the CPU is frozen until the operation is complete, even though the BDM found a free cycle. The BDM hardware commands are listed in Table 7-5. The READ_BD and WRITE_BD commands allow access to the BDM register locations. These locations are not normally in the system memory map but share addresses with the application in memory. To distinguish between physical memory locations that share the same address, BDM memory resources are 1. This method is provided by the S12S_DBG module.

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enabled just for the READ_BD and WRITE_BD access cycle. This allows the BDM to access BDM locations unobtrusively, even if the addresses conﬂict with the application memory map.

7.4.4 Standard BDM Firmware Commands

BDM ﬁrmware commands are used to access and manipulate CPU resources. The system must be in active BDM to execute standard BDM ﬁrmware commands, seeSection 7.4.2, “Enabling and Activating BDM”. Normal instruction execution is suspended while the CPU executes the ﬁrmware located in the standard BDM ﬁrmware lookup table. The hardware command BACKGROUND is the usual way to activate BDM. As the system enters active BDM, the standard BDM ﬁrmware lookup table and BDM registers become visible in the on-chip memory map at 0x3_FF00–0x3_FFFF, and the CPU begins executing the standard BDM ﬁrmware. The standard BDM ﬁrmware watches for serial commands and executes them as they are received. The ﬁrmware commands are shown in Table 7-6. Table 7-5. Hardware Commands Command Opcode (hex) Data Description BACKGROUND 90 None Enter background mode if BDM is enabled. If enabled, an ACK will be issued when the part enters active background mode. ACK_ENABLE D5 None Enable Handshake. Issues an ACK pulse after the command is executed. ACK_DISABLE D6 None Disable Handshake. This command does not issue an ACK pulse. READ_BD_BYTE E4 16-bit address 16-bit data out Read from memory with standard BDM ﬁrmware lookup table in map. Odd address data on low byte; even address data on high byte. READ_BD_WORD EC 16-bit address 16-bit data out Read from memory with standard BDM ﬁrmware lookup table in map. Must be aligned access. READ_BYTE E0 16-bit address 16-bit data out Read from memory with standard BDM ﬁrmware lookup table out of map. Odd address data on low byte; even address data on high byte. READ_WORD E8 16-bit address 16-bit data out Read from memory with standard BDM ﬁrmware lookup table out of map. Must be aligned access. WRITE_BD_BYTE C4 16-bit address 16-bit data in Write to memory with standard BDM ﬁrmware lookup table in map. Odd address data on low byte; even address data on high byte. WRITE_BD_WORD CC 16-bit address 16-bit data in Write to memory with standard BDM ﬁrmware lookup table in map. Must be aligned access. WRITE_BYTE C0 16-bit address 16-bit data in Write to memory with standard BDM ﬁrmware lookup table out of map. Odd address data on low byte; even address data on high byte. WRITE_WORD C8 16-bit address 16-bit data in Write to memory with standard BDM ﬁrmware lookup table out of map. Must be aligned access. NOTE: If enabled, ACK will occur when data is ready for transmission for all BDM READ commands and will occur after the write is complete for all BDM WRITE commands.

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7.4.5 BDM Command Structure

Hardware and ﬁrmware BDM commands start with an 8-bit opcode followed by a 16-bit address and/or a 16-bit data word, depending on the command. All the read commands return 16 bits of data despite the byte or word implication in the command name. 8-bit reads return 16-bits of data, only one byte of which contains valid data. If reading an even address, the valid data will appear in the MSB. If reading an odd address, the valid data will appear in the LSB. Table 7-6. Firmware Commands Command1 1 If enabled, ACK will occur when data is ready for transmission for all BDM READ commands and will occur after the write is complete for all BDM WRITE commands. Opcode (hex) Data Description READ_NEXT2 2 When the ﬁrmware command READ_NEXT or WRITE_NEXT is used to access the BDM address space the BDM resources are accessed rather than user code. Writing BDM ﬁrmware is not possible. 62 16-bit data out Increment X index register by 2 (X = X + 2), then read word X points to. READ_PC 63 16-bit data out Read program counter. READ_D 64 16-bit data out Read D accumulator. READ_X 65 16-bit data out Read X index register. READ_Y 66 16-bit data out Read Y index register. READ_SP 67 16-bit data out Read stack pointer. WRITE_NEXT 2 42 16-bit data in Increment X index register by 2 (X = X + 2), then write word to location pointed to by X. WRITE_PC 43 16-bit data in Write program counter. WRITE_D 44 16-bit data in Write D accumulator. WRITE_X 45 16-bit data in Write X index register. WRITE_Y 46 16-bit data in Write Y index register. WRITE_SP 47 16-bit data in Write stack pointer. GO 08 none Go to user program. If enabled, ACK will occur when leaving active background mode. GO_UNTIL 3 System stop disables the ACK function and ignored commands will not have an ACK-pulse (e.g., CPU in stop or wait mode). The GO_UNTIL command will not get an Acknowledge if CPU executes the wait or stop instruction before the “UNTIL ” condition (BDM active again) is reached (see Section 7.4.7, “Serial Interface Hardware Handshake Protocol”last note). 0C none Go to user program. If enabled, ACK will occur upon returning to active background mode. TRACE1 10 none Execute one user instruction then return to active BDM. If enabled, ACK will occur upon returning to active background mode. TAGGO -> GO 18 none (Previous enable tagging and go to user program.) This command will be deprecated and should not be used anymore. Opcode will be executed as a GO command.

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16-bit misaligned reads and writes are generally not allowed. If attempted by BDM hardware command, the BDM ignores the least signiﬁcant bit of the address and assumes an even address from the remaining bits. For hardware data read commands, the external host must wait at least 150 bus clock cycles after sending the address before attempting to obtain the read data. This is to be certain that valid data is available in the BDM shift register, ready to be shifted out. For hardware write commands, the external host must wait 150 bus clock cycles after sending the data to be written before attempting to send a new command. This is to avoid disturbing the BDM shift register before the write has been completed. The 150 bus clock cycle delay in both cases includes the maximum 128 cycle delay that can be incurred as the BDM waits for a free cycle before stealing a cycle. For BDM ﬁrmware read commands, the external host should wait at least 48 bus clock cycles after sending the command opcode and before attempting to obtain the read data. The 48 cycle wait allows enough time for the requested data to be made available in the BDM shift register, ready to be shifted out. For BDM ﬁrmware write commands, the external host must wait 36 bus clock cycles after sending the data to be written before attempting to send a new command. This is to avoid disturbing the BDM shift register before the write has been completed. The external host should wait for at least for 76 bus clock cycles after a TRACE1 or GO command before starting any new serial command. This is to allow the CPU to exit gracefully from the standard BDM ﬁrmware lookup table and resume execution of the user code. Disturbing the BDM shift register prematurely may adversely affect the exit from the standard BDM ﬁrmware lookup table. NOTE If the bus rate of the target processor is unknown or could be changing, it is recommended that the ACK (acknowledge function) is used to indicate when an operation is complete. When using ACK, the delay times are automated. Figure 7-6 represents the BDM command structure. The command blocks illustrate a series of eight bit times starting with a falling edge. The bar across the top of the blocks indicates that the BKGD line idles in the high state. The time for an 8-bit command is 8 × 16 target clock cycles. 1. Target clock cycles are cycles measured using the target MCU’s serial clock rate. SeeSection 7.4.6, “BDM Serial Interface” and Section 7.3.2.1, “BDM Status Register (BDMSTS)” for information on how serial clock rate is selected.

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7.4.6 BDM Serial Interface

The BDM communicates with external devices serially via the BKGD pin. During reset, this pin is a mode select input which selects between normal and special modes of operation. After reset, this pin becomes the dedicated serial interface pin for the BDM. The BDM serial interface is timed based on the VCO clock (please refer to the CPMU Block Guide for more details), which gets divided by 8. This clock will be referred to as the target clock in the following explanation. The BDM serial interface uses a clocking scheme in which the external host generates a falling edge on the BKGD pin to indicate the start of each bit time. This falling edge is sent for every bit whether data is transmitted or received. Data is transferred most signiﬁcant bit (MSB) ﬁrst at 16 target clock cycles per bit. The interface times out if 512 clock cycles occur between falling edges from the host. The BKGD pin is a pseudo open-drain pin and has an weak on-chip active pull-up that is enabled at all times. It is assumed that there is an external pull-up and that drivers connected to BKGD do not typically drive the high level. Since R-C rise time could be unacceptably long, the target system and host provide brief driven-high (speedup) pulses to drive BKGD to a logic 1. The source of this speedup pulse is the host for transmit cases and the target for receive cases. The timing for host-to-target is shown in Figure 7-7 and that of target-to-host in Figure 7-8 and Figure 7-9. All four cases begin when the host drives the BKGD pin low to generate a falling edge. Since the host and target are operating from separate clocks, it can take the target system up to one full clock cycle to recognize this edge. The target measures delays from this perceived start of the bit time while the host measures delays from the point it actually drove BKGD low to start the bit up to one target clock cycle Hardware Hardware Firmware Firmware GO, 48-BC BC = Bus Clock Cycles Command Address 150-BC Delay Next DELAY

8 Bits

AT ~16 TC/Bit

16 Bits

AT ~16 TC/Bit AT ~16 TC/Bit Command Address Data Next DataRead Write Read Write TRACE Command Next Command Data 76-BC Delay Next Command 150-BC Delay 36-BC DELAY Command Command Command CommandData Next Command TC = Target Clock Cycles

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earlier. Synchronization between the host and target is established in this manner at the start of every bit time. Figure 7-7 shows an external host transmitting a logic 1 and transmitting a logic 0 to the BKGD pin of a target system. The host is asynchronous to the target, so there is up to a one clock-cycle delay from the host-generated falling edge to where the target recognizes this edge as the beginning of the bit time. Ten target clock cycles later, the target senses the bit level on the BKGD pin. Internal glitch detect logic requires the pin be driven high no later that eight target clock cycles after the falling edge for a logic 1 transmission. Since the host drives the high speedup pulses in these two cases, the rising edges look like digitally driven signals. Figure 7-7. BDM Host-to-Target Serial Bit Timing The receive cases are more complicated. Figure 7-8 shows the host receiving a logic 1 from the target system. Since the host is asynchronous to the target, there is up to one clock-cycle delay from the host-generated falling edge on BKGD to the perceived start of the bit time in the target. The host holds the BKGD pin low long enough for the target to recognize it (at least two target clock cycles). The host must release the low drive before the target drives a brief high speedup pulse seven target clock cycles after the perceived start of the bit time. The host should sample the bit level about 10 target clock cycles after it started the bit time. Target Senses Bit

10 Cycles

(Target MCU) Host Transmit 1 Host Transmit 0 Perceived Start of Bit Time Earliest Start of Next Bit

Background Debug Module (S12SBDMV1) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 265 Figure 7-8. BDM Target-to-Host Serial Bit Timing (Logic 1) Figure 7-9 shows the host receiving a logic 0 from the target. Since the host is asynchronous to the target, there is up to a one clock-cycle delay from the host-generated falling edge on BKGD to the start of the bit time as perceived by the target. The host initiates the bit time but the target ﬁnishes it. Since the target wants the host to receive a logic 0, it drives the BKGD pin low for 13 target clock cycles then brieﬂy drives it high to speed up the rising edge. The host samples the bit level about 10 target clock cycles after starting the bit time. Figure 7-9. BDM Target-to-Host Serial Bit Timing (Logic 0) High-Impedance Earliest Start of Next Bit R-C Rise (Target MCU) Host Drive to BKGD Pin Target System Speedup Pulse High-Impedance High-Impedance Earliest Start of Next Bit BDM Clock (Target MCU) Host Drive to BKGD Pin BKGD Pin Perceived Start of Bit Time

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7.4.7 Serial Interface Hardware Handshake Protocol

BDM commands that require CPU execution are ultimately treated at the MCU bus rate. Since the BDM clock source can be modiﬁed when changing the settings for the VCO frequency (CPMUSYNR), it is very helpful to provide a handshake protocol in which the host could determine when an issued command is executed by the CPU. The BDM clock frequency is always VCO frequency divided by 8. The alternative is to always wait the amount of time equal to the appropriate number of cycles at the slowest possible rate the clock could be running. This sub-section will describe the hardware handshake protocol. The hardware handshake protocol signals to the host controller when an issued command was successfully executed by the target. This protocol is implemented by a 16 serial clock cycle low pulse followed by a brief speedup pulse in the BKGD pin. This pulse is generated by the target MCU when a command, issued by the host, has been successfully executed (see Figure 7-10). This pulse is referred to as the ACK pulse. After the ACK pulse has ﬁnished: the host can start the bit retrieval if the last issued command was a read command, or start a new command if the last command was a write command or a control command (BACKGROUND, GO, GO_UNTIL or TRACE1). The ACK pulse is not issued earlier than 32 serial clock cycles after the BDM command was issued. The end of the BDM command is assumed to be the 16th tick of the last bit. This minimum delay assures enough time for the host to perceive the ACK pulse. Note also that, there is no upper limit for the delay between the command and the related ACK pulse, since the command execution depends upon the CPU bus, which in some cases could be very slow due to long accesses taking place.This protocol allows a great ﬂexibility for the POD designers, since it does not rely on any accurate time measurement or short response time to any event in the serial communication. Figure 7-10. Target Acknowledge Pulse (ACK) NOTE If the ACK pulse was issued by the target, the host assumes the previous command was executed. If the CPU enters wait or stop prior to executing a hardware command, the ACK pulse will not be issued meaning that the BDM command was not executed. After entering wait or stop mode, the BDM command is no longer pending.

16 Cycles

(Target MCU) Target Transmits ACK Pulse High-Impedance BKGD Pin Minimum Delay From the BDM Command

32 Cycles

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The ACK pulse does not provide a time out. This means for the GO_UNTIL command that it can not be distinguished if a stop or wait has been executed (command discarded and ACK not issued) or if the “UNTIL” condition (BDM active) is just not reached yet. Hence in any case where the ACK pulse of a command is not issued the possible pending command should be aborted before issuing a new command. See the handshake abort procedure described in Section 7.4.8, “Hardware Handshake Abort Procedure”.

7.4.8 Hardware Handshake Abort Procedure

The abort procedure is based on the SYNC command. In order to abort a command, which had not issued the corresponding ACK pulse, the host controller should generate a low pulse in the BKGD pin by driving it low for at least 128 serial clock cycles and then driving it high for one serial clock cycle, providing a speedup pulse. By detecting this long low pulse in the BKGD pin, the target executes the SYNC protocol, see Section 7.4.9, “SYNC — Request Timed Reference Pulse” , and assumes that the pending command and therefore the related ACK pulse, are being aborted. Therefore, after the SYNC protocol has been completed the host is free to issue new BDM commands. For BDM ﬁrmware READ or WRITE commands it can not be guaranteed that the pending command is aborted when issuing a SYNC before the corresponding ACK pulse. There is a short latency time from the time the READ or WRITE access begins until it is ﬁnished and the corresponding ACK pulse is issued. The latency time depends on the ﬁrmware READ or WRITE command that is issued and on the selected bus clock rate. When the SYNC command starts during this latency time the READ or WRITE command will not be aborted, but the corresponding ACK pulse will be aborted. A pending GO, TRACE1 or GO_UNTIL command can not be aborted. Only the corresponding ACK pulse can be aborted by the SYNC command. Although it is not recommended, the host could abort a pending BDM command by issuing a low pulse in the BKGD pin shorter than 128 serial clock cycles, which will not be interpreted as the SYNC command. The ACK is actually aborted when a negative edge is perceived by the target in the BKGD pin. The short abort pulse should have at least 4 clock cycles keeping the BKGD pin low, in order to allow the negative edge to be detected by the target. In this case, the target will not execute the SYNC protocol but the pending command will be aborted along with the ACK pulse. The potential problem with this abort procedure is when there is a conﬂict between the ACK pulse and the short abort pulse. In this case, the target may not perceive the abort pulse. The worst case is when the pending command is a read command (i.e., READ_BYTE). If the abort pulse is not perceived by the target the host will attempt to send a new command after the abort pulse was issued, while the target expects the host to retrieve the accessed memory byte. In this case, host and target will run out of synchronism. However, if the command to be aborted is not a read command the short abort pulse could be used. After a command is aborted the target assumes the next negative edge, after the abort pulse, is the ﬁrst bit of a new BDM command. NOTE The details about the short abort pulse are being provided only as a reference for the reader to better understand the BDM internal behavior. It is not recommended that this procedure be used in a real application.

Background Debug Module (S12SBDMV1) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 269 Since the host knows the target serial clock frequency, the SYNC command (used to abort a command) does not need to consider the lower possible target frequency. In this case, the host could issue a SYNC very close to the 128 serial clock cycles length. Providing a small overhead on the pulse length in order to assure the SYNC pulse will not be misinterpreted by the target. See Section 7.4.9, “SYNC — Request Timed Reference Pulse”. Figure 7-12 shows a SYNC command being issued after a READ_BYTE, which aborts the READ_BYTE command. Note that, after the command is aborted a new command could be issued by the host computer. Figure 7-12. ACK Abort Procedure at the Command Level NOTE Figure 7-12 does not represent the signals in a true timing scale Figure 7-13 shows a conﬂict between the ACK pulse and the SYNC request pulse. This conﬂict could occur if a POD device is connected to the target BKGD pin and the target is already in debug active mode. Consider that the target CPU is executing a pending BDM command at the exact moment the POD is being connected to the BKGD pin. In this case, an ACK pulse is issued along with the SYNC command. In this case, there is an electrical conﬂict between the ACK speedup pulse and the SYNC pulse. Since this is not a probable situation, the protocol does not prevent this conﬂict from happening. Figure 7-13. ACK Pulse and SYNC Request Conﬂict READ_BYTE READ_STATUSBKGD Pin Memory Address New BDM Command New BDM Command Host Target Host Target Host Target SYNC Response From the Target (Out of Scale) BDM Decode and Starts to Execute the READ_BYTE Command READ_BYTE CMD is Aborted by the SYNC Request (Out of Scale) BDM Clock (Target MCU) Target MCU Drives to BKGD Pin BKGD Pin Electrical Conﬂict Host and Target Drive to BKGD Pin

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This information is being provided so that the MCU integrator will be aware that such a conﬂict could occur. The hardware handshake protocol is enabled by the ACK_ENABLE and disabled by the ACK_DISABLE BDM commands. This provides backwards compatibility with the existing POD devices which are not able to execute the hardware handshake protocol. It also allows for new POD devices, that support the hardware handshake protocol, to freely communicate with the target device. If desired, without the need for waiting for the ACK pulse. The commands are described as follows:

ACK_ENABLE — enables the hardware handshake protocol. The target will issue the ACK pulse when a CPU command is executed by the CPU. The ACK_ENABLE command itself also has the ACK pulse as a response.
ACK_DISABLE — disables the ACK pulse protocol. In this case, the host needs to use the worst case delay time at the appropriate places in the protocol. The default state of the BDM after reset is hardware handshake protocol disabled. All the read commands will ACK (if enabled) when the data bus cycle has completed and the data is then ready for reading out by the BKGD serial pin. All the write commands will ACK (if enabled) after the data has been received by the BDM through the BKGD serial pin and when the data bus cycle is complete. See Section 7.4.3, “BDM Hardware Commands” and Section 7.4.4, “Standard BDM Firmware Commands” for more information on the BDM commands. The ACK_ENABLE sends an ACK pulse when the command has been completed. This feature could be used by the host to evaluate if the target supports the hardware handshake protocol. If an ACK pulse is issued in response to this command, the host knows that the target supports the hardware handshake protocol. If the target does not support the hardware handshake protocol the ACK pulse is not issued. In this case, the ACK_ENABLE command is ignored by the target since it is not recognized as a valid command. The BACKGROUND command will issue an ACK pulse when the CPU changes from normal to background mode. The ACK pulse related to this command could be aborted using the SYNC command. The GO command will issue an ACK pulse when the CPU exits from background mode. The ACK pulse related to this command could be aborted using the SYNC command. The GO_UNTIL command is equivalent to a GO command with exception that the ACK pulse, in this case, is issued when the CPU enters into background mode. This command is an alternative to the GO command and should be used when the host wants to trace if a breakpoint match occurs and causes the CPU to enter active background mode. Note that the ACK is issued whenever the CPU enters BDM, which could be caused by a breakpoint match or by a BGND instruction being executed. The ACK pulse related to this command could be aborted using the SYNC command. The TRACE1 command has the related ACK pulse issued when the CPU enters background active mode after one instruction of the application program is executed. The ACK pulse related to this command could be aborted using the SYNC command.

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7.4.9 SYNC — Request Timed Reference Pulse

The SYNC command is unlike other BDM commands because the host does not necessarily know the correct communication speed to use for BDM communications until after it has analyzed the response to the SYNC command. To issue a SYNC command, the host should perform the following steps: 1. Drive the BKGD pin low for at least 128 cycles at the lowest possible BDM serial communication frequency (The lowest serial communication frequency is determined by the settings for the VCO clock (CPMUSYNR). The BDM clock frequency is always VCO clock frequency divided by 8.) 2. Drive BKGD high for a brief speedup pulse to get a fast rise time (this speedup pulse is typically one cycle of the host clock.) 3. Remove all drive to the BKGD pin so it reverts to high impedance. 4. Listen to the BKGD pin for the sync response pulse. Upon detecting the SYNC request from the host, the target performs the following steps: 1. Discards any incomplete command received or bit retrieved. 2. Waits for BKGD to return to a logic one. 3. Delays 16 cycles to allow the host to stop driving the high speedup pulse. 4. Drives BKGD low for 128 cycles at the current BDM serial communication frequency. 5. Drives a one-cycle high speedup pulse to force a fast rise time on BKGD. 6. Removes all drive to the BKGD pin so it reverts to high impedance. The host measures the low time of this 128 cycle SYNC response pulse and determines the correct speed for subsequent BDM communications. Typically, the host can determine the correct communication speed within a few percent of the actual target speed and the communication protocol can easily tolerate speed errors of several percent. As soon as the SYNC request is detected by the target, any partially received command or bit retrieved is discarded. This is referred to as a soft-reset, equivalent to a time-out in the serial communication. After the SYNC response, the target will consider the next negative edge (issued by the host) as the start of a new BDM command or the start of new SYNC request. Another use of the SYNC command pulse is to abort a pending ACK pulse. The behavior is exactly the same as in a regular SYNC command. Note that one of the possible causes for a command to not be acknowledged by the target is a host-target synchronization problem. In this case, the command may not have been understood by the target and so an ACK response pulse will not be issued.

7.4.10 Instruction Tracing

When a TRACE1 command is issued to the BDM in active BDM, the CPU exits the standard BDM ﬁrmware and executes a single instruction in the user code. Once this has occurred, the CPU is forced to return to the standard BDM ﬁrmware and the BDM is active and ready to receive a new command. If the TRACE1 command is issued again, the next user instruction will be executed. This facilitates stepping or tracing through the user code one instruction at a time.

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If an interrupt is pending when a TRACE1 command is issued, the interrupt stacking operation occurs but no user instruction is executed. Once back in standard BDM ﬁrmware execution, the program counter points to the ﬁrst instruction in the interrupt service routine. Be aware when tracing through the user code that the execution of the user code is done step by step but all peripherals are free running. Hence possible timing relations between CPU code execution and occurrence of events of other peripherals no longer exist. Do not trace the CPU instruction BGND used for soft breakpoints. Tracing over the BGND instruction will result in a return address pointing to BDM ﬁrmware address space. When tracing through user code which contains stop or wait instructions the following will happen when the stop or wait instruction is traced: The CPU enters stop or wait mode and the TRACE1 command can not be ﬁnished before leaving the low power mode. This is the case because BDM active mode can not be entered after CPU executed the stop instruction. However all BDM hardware commands except the BACKGROUND command are operational after tracing a stop or wait instruction and still being in stop or wait mode. If system stop mode is entered (all bus masters are in stop mode) no BDM command is operational. As soon as stop or wait mode is exited the CPU enters BDM active mode and the saved PC value points to the entry of the corresponding interrupt service routine. In case the handshake feature is enabled the corresponding ACK pulse of the TRACE1 command will be discarded when tracing a stop or wait instruction. Hence there is no ACK pulse when BDM active mode is entered as part of the TRACE1 command after CPU exited from stop or wait mode. All valid commands sent during CPU being in stop or wait mode or after CPU exited from stop or wait mode will have an ACK pulse. The handshake feature becomes disabled only when system stop mode has been reached. Hence after a system stop mode the handshake feature must be enabled again by sending the ACK_ENABLE command.

7.4.11 Serial Communication Time Out

The host initiates a host-to-target serial transmission by generating a falling edge on the BKGD pin. If BKGD is kept low for more than 128 target clock cycles, the target understands that a SYNC command was issued. In this case, the target will keep waiting for a rising edge on BKGD in order to answer the SYNC request pulse. If the rising edge is not detected, the target will keep waiting forever without any time-out limit. Consider now the case where the host returns BKGD to logic one before 128 cycles. This is interpreted as a valid bit transmission, and not as a SYNC request. The target will keep waiting for another falling edge marking the start of a new bit. If, however, a new falling edge is not detected by the target within 512 clock cycles since the last falling edge, a time-out occurs and the current command is discarded without affecting memory or the operating mode of the MCU. This is referred to as a soft-reset. If a read command is issued but the data is not retrieved within 512 serial clock cycles, a soft-reset will occur causing the command to be disregarded. The data is not available for retrieval after the time-out has occurred. This is the expected behavior if the handshake protocol is not enabled. In order to allow the data to be retrieved even with a large clock frequency mismatch (between BDM and CPU) when the hardware

Background Debug Module (S12SBDMV1) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 273 handshake protocol is enabled, the time out between a read command and the data retrieval is disabled. Therefore, the host could wait for more then 512 serial clock cycles and still be able to retrieve the data from an issued read command. However, once the handshake pulse (ACK pulse) is issued, the time-out feature is re-activated, meaning that the target will time out after 512 clock cycles. Therefore, the host needs to retrieve the data within a 512 serial clock cycles time frame after the ACK pulse had been issued. After that period, the read command is discarded and the data is no longer available for retrieval. Any negative edge in the BKGD pin after the time-out period is considered to be a new command or a SYNC request. Note that whenever a partially issued command, or partially retrieved data, has occurred the time out in the serial communication is active. This means that if a time frame higher than 512 serial clock cycles is observed between two consecutive negative edges and the command being issued or data being retrieved is not complete, a soft-reset will occur causing the partially received command or data retrieved to be disregarded. The next negative edge in the BKGD pin, after a soft-reset has occurred, is considered by the target as the start of a new BDM command, or the start of a SYNC request pulse.

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MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 275 Chapter 8 S12S Debug Module (S12SDBG)

8.1 Introduction

The S12SDBG module provides an on-chip trace buffer with ﬂexible triggering capability to allow non-intrusive debug of application software. The S12SDBG module is optimized for S12SCPU debugging. Typically the S12SDBG module is used in conjunction with the S12SBDM module, whereby the user conﬁgures the S12SDBG module for a debugging session over the BDM interface. Once conﬁgured the S12SDBG module is armed and the device leaves BDM returning control to the user program, which is then monitored by the S12SDBG module. Alternatively the S12SDBG module can be conﬁgured over a serial interface using SWI routines.

8.1.1 Glossary Of Terms

COF: Change Of Flow. Change in the program ﬂow due to a conditional branch, indexed jump or interrupt. Revision Number Date Author Summary of Changes 02.00 31.JUL..2007 State sequencer encoding enhanced Simultaneous TRIG and ARM setting updated Pure PC replaced with Compressed Pure PC Mode 8.4.5.2.4 02.01 09.AUG..2007 Enhanced compressed Pure PC mode description 02.02 10.AUG..2007 Added CompA size & databus byte compare enhancement 02.03 29.AUG..2007 DBGSCR1 encoding 1101 added. CompA functional description improved Swapped NDB and SZ in DBGACTL to match DBGBCTL 02.04 17.OCT.2007 Reverted to ﬁnal state transition priority 02.05 19.OCT.2007 Table 8-33 DB byte access conﬁguration corrected 02.06 22.NOV.2007 Table 8-39 Correction Section 8.4.5.6, “Trace Buffer Reset State Added NOTE 02.07 13.DEC.2007 Section 8.5, “Application Information Added application information

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BDM: Background Debug Mode S12SBDM: Background Debug Module DUG: Device User Guide, describing the features of the device into which the DBG is integrated. WORD: 16 bit data entity Data Line: 20 bit data entity CPU: S12SCPU module DBG: S12SDBG module POR: Power On Reset Tag: Tags can be attached to CPU opcodes as they enter the instruction pipe. If the tagged opcode reaches the execution stage a tag hit occurs.

8.1.2 Overview

The comparators monitor the bus activity of the CPU module. A match can initiate a state sequencer transition. On a transition to the Final State, bus tracing is triggered and/or a breakpoint can be generated. Independent of comparator matches a transition to Final State with associated tracing and breakpoint can be triggered immediately by writing to the TRIG control bit. The trace buffer is visible through a 2-byte window in the register address map and can be read out using standard 16-bit word reads. Tracing is disabled when the MCU system is secured.

8.1.3 Features

Three comparators (A, B and C) — Comparators A compares the full address bus and full 16-bit data bus — Comparator A features a data bus mask register — Comparators B and C compare the full address bus only — Each comparator features selection of read or write access cycles — Comparator B allows selection of byte or word access cycles — Comparator matches can initiate state sequencer transitions
Three comparator modes — Simple address/data comparator match mode — Inside address range mode, Addmin ≤ Address ≤ Addmax — Outside address range match mode, Address < Addmin or Address > Addmax
Two types of matches — Tagged — This matches just before a speciﬁc instruction begins execution — Force — This is valid on the ﬁrst instruction boundary after a match occurs
Two types of breakpoints

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Trigger mode independent of comparators — TRIG Immediate software trigger
Four trace modes — Normal: change of ﬂow (COF) PC information is stored (see Section 8.4.5.2.1, “Normal Mode) for change of ﬂow deﬁnition. — Loop1: same as Normal but inhibits consecutive duplicate source address entries — Detail: address and data for all cycles except free cycles and opcode fetches are stored — Compressed Pure PC: all program counter addresses are stored
4-stage state sequencer for trace buffer control — Tracing session trigger linked to Final State of state sequencer — Begin and End alignment of tracing to trigger

8.1.4 Modes of Operation

The DBG module can be used in all MCU functional modes. During BDM hardware accesses and whilst the BDM module is active, CPU monitoring is disabled. When the CPU enters active BDM Mode through a BACKGROUND command, the DBG module, if already armed, remains armed. The DBG module tracing is disabled if the MCU is secure, however, breakpoints can still be generated Table 8-1. Mode Dependent Restriction Summary BDM Enable BDM Active MCU Secure Comparator Matches Enabled Breakpoints Possible Tagging Possible Tracing Possible x x 1 Y es Y es Y es No 0 0 0 Y es Only SWI Y es Y es 0 1 0 Active BDM not possible when not enabled 1 0 0 Y es Y es Y es Y es 11 0 N o N o N o N o

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8.1.5 Block Diagram

Figure 8-1. Debug Module Block Diagram

8.2 External Signal Description

There are no external signals associated with this module.

8.3 Memory Map and Registers

8.3.1 Module Memory Map

A summary of the registers associated with the DBG sub-block is shown in Figure 8-2. Detailed descriptions of the registers and bits are given in the subsections that follow. Address Name Bit 7 6 54321 Bit 0 0x0020 DBGC1 R ARM 00 BDM DBGBRK 0 COMRVW TRIG 0x0021 DBGSR R 1TBF 0 0 0 0 SSF2 SSF1 SSF0 W 0x0022 DBGTCR R0 TSOURCE 00 TRCMOD 0 TALIGNW 0x0023 DBGC2 R 000000 ABCMW Figure 8-2. Quick Reference to DBG Registers CPU BUS TRACE BUFFER BUS INTERFACE TRANSITIONMATCH0 STATE COMPARATOR B COMPARATOR C COMPARATOR A STATE SEQUENCERMATCH1 MATCH2 TRACE READ TRACE DATA (DBG READ DATA BUS) CONTROL SECURE BREAKPOINT REQUESTS COMPARATOR MATCH CONTROL TRIGGER TAG & MATCH CONTROL LOGIC TAGSTAGHITS STATE TO CPU

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8.3.2 Register Descriptions

This section consists of the DBG control and trace buffer register descriptions in address order. Each comparator has a bank of registers that are visible through an 8-byte window between 0x0028 and 0x002F in the DBG module register address map. When ARM is set in DBGC1, the only bits in the DBG module registers that can be written are ARM, TRIG, and COMRV[1:0] 0x0024 DBGTBH R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 W 0x0025 DBGTBL R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W 0x0026 DBGCNT R 1 TBF 0 CNT W 0x0027 DBGSCRX R0 0 0 0 SC3 SC2 SC1 SC0W 0x0027 DBGMFR R 0 0 0 0 0 MC2 MC1 MC0 W 2 0x0028 DBGACTL R SZE SZ TAG BRK RW RWE NDB COMPEW 3 0x0028 DBGBCTL R SZE SZ TAG BRK RW RWE 0 COMPEW 4 0x0028 DBGCCTL R0 0 TAG BRK RW RWE 0 COMPEW 0x0029 DBGXAH R 000000 Bit 17 Bit 16W 0x002A DBGXAM R Bit 15 14 13 12 11 10 9 Bit 8W 0x002B DBGXAL R Bit 7 6 54321 Bit 0W 0x002C DBGADH R Bit 15 14 13 12 11 10 9 Bit 8W 0x002D DBGADL R Bit 7 6 54321 Bit 0W 0x002E DBGADHM R Bit 15 14 13 12 11 10 9 Bit 8W 0x002F DBGADLM R Bit 7 6 54321 Bit 0W

1 This bit is visible at DBGCNT[7] and DBGSR[7]

2 This represents the contents if the Comparator A control register is blended into this address.

3 This represents the contents if the Comparator B control register is blended into this address

4 This represents the contents if the Comparator C control register is blended into this address

Address Name Bit 7 6 54321 Bit 0 Figure 8-2. Quick Reference to DBG Registers

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8.3.2.1 Debug Control Register 1 (DBGC1)

Read: Anytime Write: Bits 7, 1, 0 anytime Bit 6 can be written anytime but always reads back as 0. Bits 4:3 anytime DBG is not armed. NOTE When disarming the DBG by clearing ARM with software, the contents of bits[4:3] are not affected by the write, since up until the write operation, ARM = 1 preventing these bits from being written. These bits must be cleared using a second write if required. Address: 0x0020 76543210 R ARM BDM DBGBRK COMRV W TRIG Reset 0 0 0 00000 = Unimplemented or Reserved Figure 8-3. Debug Control Register (DBGC1) Table 8-2. DBGC1 Field Descriptions Field Description ARM Arm Bit — The ARM bit controls whether the DBG module is armed. This bit can be set and cleared by user software and is automatically cleared on completion of a debug session, or if a breakpoint is generated with tracing not enabled. On setting this bit the state sequencer enters State1.

0 Debugger disarmed

1 Debugger armed

Immediate Trigger Request Bit— This bit when written to 1 requests an immediate trigger independent of state sequencer status. When tracing is complete a forced breakpoint may be generated depending upon DBGBRK and BDM bit settings. This bit always reads back a 0. Writing a 0 to this bit has no effect. If the DBGTCR_TSOURCE bit is clear no tracing is carried out. If tracing has already commenced using BEGIN trigger alignment, it continues until the end of the tracing session as deﬁned by the TALIGN bit, thus TRIG has no affect. In secure mode tracing is disabled and writing to this bit cannot initiate a tracing session. The session is ended by setting TRIG and ARM simultaneously. 0 Do not trigger until the state sequencer enters the Final State.

1 Trigger immediately

Background Debug Mode Enable— This bit determines if a breakpoint causes the system to enter Background Debug Mode (BDM) or initiate a Software Interrupt (SWI). If this bit is set but the BDM is not enabled by the ENBDM bit in the BDM module, then breakpoints default to SWI. 0 Breakpoint to Software Interrupt if BDM inactive. Otherwise no breakpoint. 1 Breakpoint to BDM, if BDM enabled. Otherwise breakpoint to SWI DBGBRK S12SDBG Breakpoint Enable Bit— The DBGBRK bit controls whether the debugger will request a breakpoint on reaching the state sequencer Final State. If tracing is enabled, the breakpoint is generated on completion of the tracing session. If tracing is not enabled, the breakpoint is generated immediately.

0 No Breakpoint generated

1 Breakpoint generated

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8.3.2.2 Debug Status Register (DBGSR)

Read: Anytime Write: Never 1–0 COMRV Comparator Register Visibility Bits— These bits determine which bank of comparator register is visible in the 8-byte window of the S12SDBG module address map, located between 0x0028 to 0x002F. Furthermore these bits determine which register is visible at the address 0x0027. See Table 8-3. Table 8-3. COMRV Encoding COMRV Visible Comparator Visible Register at 0x0027

00 Comparator A DBGSCR1

01 Comparator B DBGSCR2

10 Comparator C DBGSCR3

11 None DBGMFR

Address: 0x0021 76543210 R TBF 0 0 0 0 SSF2 SSF1 SSF0 W Reset POR = Unimplemented or Reserved Figure 8-4. Debug Status Register (DBGSR) Table 8-4. DBGSR Field Descriptions Field Description TBF Trace Buffer Full — The TBF bit indicates that the trace buffer has stored 64 or more lines of data since it was last armed. If this bit is set, then all 64 lines will be valid data, regardless of the value of DBGCNT bits. The TBF bit is cleared when ARM in DBGC1 is written to a one. The TBF is cleared by the power on reset initialization. Other system generated resets have no affect on this bit This bit is also visible at DBGCNT[7] 2–0 SSF[2:0] State Sequencer Flag Bits — The SSF bits indicate in which state the State Sequencer is currently in. During a debug session on each transition to a new state these bits are updated. If the debug session is ended by software clearing the ARM bit, then these bits retain their value to reﬂect the last state of the state sequencer before disarming. If a debug session is ended by an internal event, then the state sequencer returns to state0 and these bits are cleared to indicate that state0 was entered during the session. On arming the module the state sequencer enters state1 and these bits are forced to SSF[2:0] = 001. See Table 8-5 Table 8-2. DBGC1 Field Descriptions Field Description

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8.3.2.3 Debug Trace Control Register (DBGTCR)

Read: Anytime Write: Bit 6 only when DBG is neither secure nor armed.Bits 3,2,0 anytime the module is disarmed. Table 8-5. SSF[2:0] — State Sequence Flag Bit Encoding SSF[2:0] Current State

000 State0 (disarmed)

001 State1

010 State2

011 State3

100 Final State

101,110,111 Reserved Address: 0x0022 76543210 TSOURCE TRCMOD TALIGN W Reset 0 0 0 00000 Figure 8-5. Debug Trace Control Register (DBGTCR) Table 8-6. DBGTCR Field Descriptions Field Description TSOURCE Trace Source Control Bit— The TSOURCE bit enables a tracing session given a trigger condition. If the MCU system is secured, this bit cannot be set and tracing is inhibited. This bit must be set to read the trace buffer.

0 Debug session without tracing requested

1 Debug session with tracing requested

3–2 TRCMOD Trace Mode Bits — See Section 8.4.5.2, “Trace Modesfor detailed Trace Mode descriptions. In Normal Mode, change of ﬂow information is stored. In Loop1 Mode, change of ﬂow information is stored but redundant entries into trace memory are inhibited. In Detail Mode, address and data for all memory and register accesses is stored. In Compressed Pure PC mode the program counter value for each instruction executed is stored. SeeTable 8-7. TALIGN Trigger Align Bit— This bit controls whether the trigger is aligned to the beginning or end of a tracing session.

0 Trigger at end of stored data

1 Trigger before storing data

Table 8-7. TRCMOD Trace Mode Bit Encoding TRCMOD Description

00 Normal

01 Loop1

10 Detail

11 Compressed Pure PC

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8.3.2.4 Debug Control Register2 (DBGC2)

Read: Anytime Write: Anytime the module is disarmed. This register conﬁgures the comparators for range matching.

8.3.2.5 Debug Trace Buffer Register (DBGTBH:DBGTBL)

Read: Only when unlocked AND unsecured AND not armed AND TSOURCE set. Write: Aligned word writes when disarmed unlock the trace buffer for reading but do not affect trace buffer contents. Address: 0x0023 76543210 R 000000 ABCM W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 8-6. Debug Control Register2 (DBGC2) Table 8-8. DBGC2 Field Descriptions Field Description 1–0 ABCM[1:0] A and B Comparator Match Control — These bits determine the A and B comparator match mapping as described in Table 8-9. Table 8-9. ABCM Encoding ABCM Description 00 Match0 mapped to comparator A match: Match1 mapped to comparator B match. 01 Match 0 mapped to comparator A/B inside range: Match1 disabled. 10 Match 0 mapped to comparator A/B outside range: Match1 disabled.

11 Reserved

1 Currently defaults to Comparator A, Comparator B disabled

Address: 0x0024, 0x0025 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W P O R XXXXXXXXXXXXXXXX Other Figure 8-7. Debug Trace Buffer Register (DBGTB)

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8.3.2.6 Debug Count Register (DBGCNT)

Read: Anytime Write: Never Table 8-10. DBGTB Field Descriptions Field Description 15–0 Bit[15:0] Trace Buffer Data Bits— The Trace Buffer Register is a window through which the 20-bit wide data lines of the Trace Buffer may be read 16 bits at a time. Each valid read of DBGTB increments an internal trace buffer pointer which points to the next address to be read. When the ARM bit is set the trace buffer is locked to prevent reading. The trace buffer can only be unlocked for reading by writing to DBGTB with an aligned word write when the module is disarmed. The DBGTB register can be read only as an aligned word, any byte reads or misaligned access of these registers return 0 and do not cause the trace buffer pointer to increment to the next trace buffer address. Similarly reads while the debugger is armed or with the TSOURCE bit clear, return 0 and do not affect the trace buffer pointer. The POR state is undeﬁned. Other resets do not affect the trace buffer contents. Address: 0x0026 76543210 R TBF 0 CNT W Reset POR = Unimplemented or Reserved Figure 8-8. Debug Count Register (DBGCNT) Table 8-11. DBGCNT Field Descriptions Field Description TBF Trace Buffer Full — The TBF bit indicates that the trace buffer has stored 64 or more lines of data since it was last armed. If this bit is set, then all 64 lines will be valid data, regardless of the value of DBGCNT bits. The TBF bit is cleared when ARM in DBGC1 is written to a one. The TBF is cleared by the power on reset initialization. Other system generated resets have no affect on this bit This bit is also visible at DBGSR[7] 5–0 CNT[5:0] Count Value — The CNT bits indicate the number of valid data 20-bit data lines stored in the Trace Buffer. Table 8-12 shows the correlation between the CNT bits and the number of valid data lines in the Trace Buffer. When the CNT rolls over to zero, the TBF bit in DBGSR is set and incrementing of CNT will continue in end-trigger mode. The DBGCNT register is cleared when ARM in DBGC1 is written to a one. The DBGCNT register is cleared by power-on-reset initialization but is not cleared by other system resets. Thus should a reset occur during a debug session, the DBGCNT register still indicates after the reset, the number of valid trace buffer entries stored before the reset occurred. The DBGCNT register is not decremented when reading from the trace buffer. Table 8-12. CNT Decoding Table TBF CNT[5:0] Description 0 000000 No data valid

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8.3.2.7 Debug State Control Registers

There is a dedicated control register for each of the state sequencer states 1 to 3 that determines if transitions from that state are allowed, depending upon comparator matches or tag hits, and deﬁnes the next state for the state sequencer following a match. The three debug state control registers are located at the same address in the register address map (0x0027). Each register can be accessed using the COMRV bits in DBGC1 to blend in the required register. The COMRV = 11 value blends in the match ﬂag register (DBGMFR).

8.3.2.7.1 Debug State Control Register 1 (DBGSCR1)

Read: If COMRV[1:0] = 00 Write: If COMRV[1:0] = 00 and DBG is not armed. This register is visible at 0x0027 only with COMRV[1:0] = 00. The state control register 1 selects the targeted next state whilst in State1. The matches refer to the match channels of the comparator match 0 000001 000010 000100 000110 111111 1 line valid 2 lines valid 4 lines valid 6 lines valid 63 lines valid 1 000000 64 lines valid; if using Begin trigger alignment, ARM bit will be cleared and the tracing session ends. 1 000001 111110 64 lines valid, oldest data has been overwritten by most recent data Table 8-13. State Control Register Access Encoding COMRV Visible State Control Register

00 DBGSCR1

01 DBGSCR2

10 DBGSCR3

11 DBGMFR

Address: 0x0027 76543210 R 0000 SC3 SC2 SC1 SC0 W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 8-9. Debug State Control Register 1 (DBGSCR1) Table 8-12. CNT Decoding Table TBF CNT[5:0] Description

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the comparator enable bit in the associated DBGXCTL control register. The priorities described in Table 8-35 dictate that in the case of simultaneous matches, a match leading to ﬁnal state has priority followed by the match on the lower channel number (0,1,2). Thus with SC[3:0]=1101 a simultaneous match0/match1 transitions to final state.

8.3.2.7.2 Debug State Control Register 2 (DBGSCR2)

Read: If COMRV[1:0] = 01 Write: If COMRV[1:0] = 01 and DBG is not armed. Table 8-14. DBGSCR1 Field Descriptions Field Description 3–0 SC[3:0] These bits select the targeted next state whilst in State1, based upon the match event. Table 8-15. State1 Sequencer Next State Selection SC[3:0] Description (Unspeciﬁed matches have no effect)

0000 Any match to Final State

0001 Match1 to State3

0010 Match2 to State2

0011 Match1 to State2

0111 Either Match0 or Match1 to State2

1000 Reserved

1001 Match0 to State3

1010 Reserved

1011 Reserved

1100 Reserved

1110 Reserved

1111 Reserved

Address: 0x0027 76543210 R 0000 SC3 SC2 SC1 SC0 W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 8-10. Debug State Control Register 2 (DBGSCR2)

S12S Debug Module (S12SDBG) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 287 This register is visible at 0x0027 only with COMRV[1:0] = 01. The state control register 2 selects the targeted next state whilst in State2. The matches refer to the match channels of the comparator match control logic as depicted in Figure 8-1 and described in Section 8.3.2.8.1, “Debug Comparator Control Register (DBGXCTL). Comparators must be enabled by setting the comparator enable bit in the associated DBGXCTL control register. The priorities described in Table 8-35 dictate that in the case of simultaneous matches, a match leading to ﬁnal state has priority followed by the match on the lower channel number (0,1,2)

8.3.2.7.3 Debug State Control Register 3 (DBGSCR3)

Read: If COMRV[1:0] = 10 Table 8-16. DBGSCR2 Field Descriptions Field Description 3–0 SC[3:0] These bits select the targeted next state whilst in State2, based upon the match event. Table 8-17. State2 —Sequencer Next State Selection SC[3:0] Description (Unspeciﬁed matches have no effect)

0010 Match2 to State3

0101 Match2 to Final State

0111 Either Match0 or Match1 to Final State

1001 Reserved

1101 Reserved

Address: 0x0027 76543210 R 0000 SC3 SC2 SC1 SC0 W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 8-11. Debug State Control Register 3 (DBGSCR3)

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Write: If COMRV[1:0] = 10 and DBG is not armed. This register is visible at 0x0027 only with COMRV[1:0] = 10. The state control register three selects the targeted next state whilst in State3. The matches refer to the match channels of the comparator match control logic as depicted in Figure 8-1 and described in Section 8.3.2.8.1, “Debug Comparator Control Register (DBGXCTL). Comparators must be enabled by setting the comparator enable bit in the associated DBGXCTL control register. The priorities described in Table 8-35 dictate that in the case of simultaneous matches, a match leading to ﬁnal state has priority followed by the match on the lower channel number (0,1,2).

8.3.2.7.4 Debug Match Flag Register (DBGMFR)

Table 8-18. DBGSCR3 Field Descriptions Field Description 3–0 SC[3:0] These bits select the targeted next state whilst in State3, based upon the match event. Table 8-19. State3 — Sequencer Next State Selection SC[3:0] Description (Unspeciﬁed matches have no effect)

0000 Match0 to State1

0100 Match1 to State2

0101 Match1 to Final State

0111 Match0 to Final State

Address: 0x0027 76543210 R 0 0 0 0 0 MC2 MC1 MC0 W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 8-12. Debug Match Flag Register (DBGMFR)

S12S Debug Module (S12SDBG) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 289 Read: If COMRV[1:0] = 11 Write: Never DBGMFR is visible at 0x0027 only with COMRV[1:0] = 11. It features 3 ﬂag bits each mapped directly to a channel. Should a match occur on the channel during the debug session, then the corresponding ﬂag is set and remains set until the next time the module is armed by writing to the ARM bit. Thus the contents are retained after a debug session for evaluation purposes. These ﬂags cannot be cleared by software, they are cleared only when arming the module. A set ﬂag does not inhibit the setting of other ﬂags. Once a ﬂag is set, further comparator matches on the same channel in the same session have no affect on that ﬂag.

8.3.2.8 Comparator Register Descriptions

Each comparator has a bank of registers that are visible through an 8-byte window in the DBG module register address map. Comparator A consists of 8 register bytes (3 address bus compare registers, two data bus compare registers, two data bus mask registers and a control register). Comparator B consists of four register bytes (three address bus compare registers and a control register). Comparator C consists of four register bytes (three address bus compare registers and a control register). Each set of comparator registers can be accessed using the COMRV bits in the DBGC1 register. Unimplemented registers (e.g. Comparator B data bus and data bus masking) read as zero and cannot be written. The control register for comparator B differs from those of comparators A and C.

8.3.2.8.1 Debug Comparator Control Register (DBGXCTL)

The contents of this register bits 7 and 6 differ depending upon which comparator registers are visible in the 8-byte window of the DBG module register address map. Table 8-20. Comparator Register Layout 0x0028 CONTROL Read/Write Comparators A,B and C 0x0029 ADDRESS HIGH Read/Write Comparators A,B and C 0x002A ADDRESS MEDIUM Read/Write Comparators A,B and C 0x002B ADDRESS LOW Read/Write Comparators A,B and C 0x002C DATA HIGH COMPARATOR Read/Write Comparator A only 0x002D DATA LOW COMPARATOR Read/Write Comparator A only 0x002E DATA HIGH MASK Read/Write Comparator A only 0x002F DATA LOW MASK Read/Write Comparator A only Address: 0x0028 76543210 R SZE SZ TAG BRK RW RWE NDB COMPE W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 8-13. Debug Comparator Control Register DBGACTL (Comparator A)

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Read: DBGACTL if COMRV[1:0] = 00 DBGBCTL if COMRV[1:0] = 01 DBGCCTL if COMRV[1:0] = 10 Write: DBGACTL if COMRV[1:0] = 00 and DBG not armed DBGBCTL if COMRV[1:0] = 01 and DBG not armed DBGCCTL if COMRV[1:0] = 10 and DBG not armed Address: 0x0028 76543210 R SZE SZ TAG BRK RW RWE COMPE W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 8-14. Debug Comparator Control Register DBGBCTL (Comparator B) Address: 0x0028 76543210 R0 0 TAG BRK RW RWE COMPE W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 8-15. Debug Comparator Control Register DBGCCTL (Comparator C) Table 8-21. DBGXCTL Field Descriptions Field Description SZE (Comparators A and B) Size Comparator Enable Bit — The SZE bit controls whether access size comparison is enabled for the associated comparator. This bit is ignored if the TAG bit in the same register is set.

0 Word/Byte access size is not used in comparison

1 Word/Byte access size is used in comparison

(Comparators A and B) Size Comparator Value Bit — The SZ bit selects either word or byte access size in comparison for the associated comparator. This bit is ignored if the SZE bit is cleared or if the TAG bit in the same register is set.

0 Word access size is compared

1 Byte access size is compared

Tag Select— This bit controls whether the comparator match has immediate effect, causing an immediate state sequencer transition or tag the opcode at the matched address. Tagged opcodes trigger only if they reach the execution stage of the instruction queue.

0 Allow state sequencer transition immediately on match

1 On match, tag the opcode. If the opcode is about to be executed allow a state sequencer transition BRK Break— This bit controls whether a comparator match terminates a debug session immediately, independent of state sequencer state. To generate an immediate breakpoint the module breakpoints must be enabled using the DBGC1 bit DBGBRK. 0 The debug session termination is dependent upon the state sequencer and trigger conditions. 1 A match on this channel terminates the debug session immediately; breakpoints if active are generated, tracing, if active, is terminated and the module disarmed.

S12S Debug Module (S12SDBG) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 291 Table 8-22 shows the effect for RWE and RW on the comparison conditions. These bits are ignored if the corresponding TAG bit is set since the match occurs based on the tagged opcode reaching the execution stage of the instruction queue.

8.3.2.8.2 Debug Comparator Address High Register (DBGXAH)

The DBGC1_COMRV bits determine which comparator address registers are visible in the 8-byte window from 0x0028 to 0x002F as shown in Section Table 8-23., “Comparator Address Register Visibility RW Read/Write Comparator Value Bit — The RW bit controls whether read or write is used in compare for the associated comparator. The RW bit is not used if RWE = 0. This bit is ignored if the TAG bit in the same register is set.

0 Write cycle is matched1Read cycle is matched

Read/Write Enable Bit — The RWE bit controls whether read or write comparison is enabled for the associated comparator.This bit is ignored if the TAG bit in the same register is set

0 Read/Write is not used in comparison

1 Read/Write is used in comparison

(Comparator A) Not Data Bus— The NDB bit controls whether the match occurs when the data bus matches the comparator register value or when the data bus differs from the register value. This bit is ignored if the TAG bit in the same register is set. This bit is only available for comparator A.

0 Match on data bus equivalence to comparator register contents

1 Match on data bus difference to comparator register contents

Determines if comparator is enabled

0 The comparator is not enabled

1 The comparator is enabled

Table 8-22. Read or Write Comparison Logic Table RWE Bit RW Bit RW Signal Comment 0 x 0 RW not used in comparison 0 x 1 RW not used in comparison 1 0 0 Write data bus 1 0 1 No match 1 1 0 No match 1 1 1 Read data bus Address: 0x0029 76543210 R 000000 Bit 17 Bit 16 W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 8-16. Debug Comparator Address High Register (DBGXAH) Table 8-21. DBGXCTL Field Descriptions Field Description

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Table 8-23. Comparator Address Register Visibility Read: Anytime. See Table 8-23 for visible register encoding. Write: If DBG not armed. See Table 8-23 for visible register encoding.

8.3.2.8.3 Debug Comparator Address Mid Register (DBGXAM)

Read: Anytime. See Table 8-23 for visible register encoding. Write: If DBG not armed. See Table 8-23 for visible register encoding. COMRV Visible Comparator

00 DBGAAH, DBGAAM, DBGAAL

01 DBGBAH, DBGBAM, DBGBAL

10 DBGCAH, DBGCAM, DBGCAL

11 None

Table 8-24. DBGXAH Field Descriptions Field Description 1–0 Bit[17:16] Comparator Address High Compare Bits — The Comparator address high compare bits control whether the selected comparator compares the address bus bits [17:16] to a logic one or logic zero.

0 Compare corresponding address bit to a logic zero

1 Compare corresponding address bit to a logic one

Address: 0x002A 76543210 R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 W Reset 0 0 0 00000 Figure 8-17. Debug Comparator Address Mid Register (DBGXAM) Table 8-25. DBGXAM Field Descriptions Field Description 7–0 Bit[15:8] Comparator Address Mid Compare Bits — The Comparator address mid compare bits control whether the selected comparator compares the address bus bits [15:8] to a logic one or logic zero.

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8.3.2.8.4 Debug Comparator Address Low Register (DBGXAL)

Read: Anytime. See Table 8-23 for visible register encoding. Write: If DBG not armed. See Table 8-23 for visible register encoding.

8.3.2.8.5 Debug Comparator Data High Register (DBGADH)

Read: If COMRV[1:0] = 00 Write: If COMRV[1:0] = 00 and DBG not armed. Address: 0x002B 76543210 R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W Reset 0 0 0 00000 Figure 8-18. Debug Comparator Address Low Register (DBGXAL) Table 8-26. DBGXAL Field Descriptions Field Description 7–0 Bits[7:0] Comparator Address Low Compare Bits — The Comparator address low compare bits control whether the selected comparator compares the address bus bits [7:0] to a logic one or logic zero. Address: 0x002C 76543210 R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 W Reset 0 0 0 00000 Figure 8-19. Debug Comparator Data High Register (DBGADH) Table 8-27. DBGADH Field Descriptions Field Description 7–0 Bits[15:8] Comparator Data High Compare Bits— The Comparator data high compare bits control whether the selected comparator compares the data bus bits [15:8] to a logic one or logic zero. The comparator data compare bits are only used in comparison if the corresponding data mask bit is logic 1. This register is available only for comparator A. Data bus comparisons are only performed if the TAG bit in DBGACTL is clear.

0 Compare corresponding data bit to a logic zero

1 Compare corresponding data bit to a logic one

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8.3.2.8.6 Debug Comparator Data Low Register (DBGADL)

Read: If COMRV[1:0] = 00 Write: If COMRV[1:0] = 00 and DBG not armed.

8.3.2.8.7 Debug Comparator Data High Mask Register (DBGADHM)

Read: If COMRV[1:0] = 00 Write: If COMRV[1:0] = 00 and DBG not armed. Address: 0x002D 76543210 R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W Reset 0 0 0 00000 Figure 8-20. Debug Comparator Data Low Register (DBGADL) Table 8-28. DBGADL Field Descriptions Field Description 7–0 Bits[7:0] Comparator Data Low Compare Bits — The Comparator data low compare bits control whether the selected comparator compares the data bus bits [7:0] to a logic one or logic zero. The comparator data compare bits are only used in comparison if the corresponding data mask bit is logic 1. This register is available only for comparator A. Data bus comparisons are only performed if the TAG bit in DBGACTL is clear Address: 0x002E 76543210 R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 W Reset 0 0 0 00000 Figure 8-21. Debug Comparator Data High Mask Register (DBGADHM) Table 8-29. DBGADHM Field Descriptions Field Description 7–0 Bits[15:8] Comparator Data High Mask Bits — The Comparator data high mask bits control whether the selected comparator compares the data bus bits [15:8] to the corresponding comparator data compare bits. Data bus comparisons are only performed if the TAG bit in DBGACTL is clear 0 Do not compare corresponding data bit Any value of corresponding data bit allows match.

1 Compare corresponding data bit

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8.3.2.8.8 Debug Comparator Data Low Mask Register (DBGADLM)

Read: If COMRV[1:0] = 00 Write: If COMRV[1:0] = 00 and DBG not armed.

8.4 Functional Description

This section provides a complete functional description of the DBG module. If the part is in secure mode, the DBG module can generate breakpoints but tracing is not possible.

8.4.1 S12SDBG Operation

Arming the DBG module by setting ARM in DBGC1 allows triggering the state sequencer, storing of data in the trace buffer and generation of breakpoints to the CPU. The DBG module is made up of four main blocks, the comparators, control logic, the state sequencer, and the trace buffer. The comparators monitor the bus activity of the CPU. All comparators can be conﬁgured to monitor address bus activity. Comparator A can also be conﬁgured to monitor databus activity and mask out individual data bus bits during a compare. Comparators can be conﬁgured to use R/W and word/byte access qualiﬁcation in the comparison. A match with a comparator register value can initiate a state sequencer transition to another state (seeFigure 8-24). Either forced or tagged matches are possible. Using a forced match, a state sequencer transition can occur immediately on a successful match of system busses and comparator registers. Whilst tagging, at a comparator match, the instruction opcode is tagged and only if the instruction reaches the execution stage of the instruction queue can a state sequencer transition occur. In the case of a transition to Final State, bus tracing is triggered and/or a breakpoint can be generated. A state sequencer transition to ﬁnal state (with associated breakpoint, if enabled) can be initiated by writing to the TRIG bit in the DBGC1 control register. The trace buffer is visible through a 2-byte window in the register address map and must be read out using standard 16-bit word reads. Address: 0x002F 76543210 R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W Reset 0 0 0 00000 Figure 8-22. Debug Comparator Data Low Mask Register (DBGADLM) Table 8-30. DBGADLM Field Descriptions Field Description 7–0 Bits[7:0] Comparator Data Low Mask Bits — The Comparator data low mask bits control whether the selected comparator compares the data bus bits [7:0] to the corresponding comparator data compare bits. Data bus comparisons are only performed if the TAG bit in DBGACTL is clear 0 Do not compare corresponding data bit. Any value of corresponding data bit allows match

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Figure 8-23. DBG Overview

8.4.2 Comparator Modes

The DBG contains three comparators, A, B and C. Each comparator compares the system address bus with the address stored in DBGXAH, DBGXAM, and DBGXAL. Furthermore, comparator A also compares the data buses to the data stored in DBGADH, DBGADL and allows masking of individual data bus bits. All comparators are disabled in BDM and during BDM accesses. The comparator match control logic (seeFigure 8-23) conﬁgures comparators to monitor the buses for an exact address or an address range, whereby either an access inside or outside the speciﬁed range generates a match condition. The comparator conﬁguration is controlled by the control register contents and the range control by the DBGC2 contents. A match can initiate a transition to another state sequencer state (see Section 8.4.4, “State Sequence Control”). The comparator control register also allows the type of access to be included in the comparison through the use of the RWE, RW, SZE, and SZ bits. The RWE bit controls whether read or write comparison is enabled for the associated comparator and the RW bit selects either a read or write access for a valid match. Similarly the SZE and SZ bits allow the size of access (word or byte) to be considered in the compare. Only comparators A and B feature SZE and SZ. The TAG bit in each comparator control register is used to determine the match condition. By setting TAG, the comparator qualiﬁes a match with the output of opcode tracking logic and a state sequencer transition occurs when the tagged instruction reaches the CPU execution stage. Whilst tagging the RW, RWE, SZE, and SZ bits and the comparator data registers are ignored; the comparator address register must be loaded with the exact opcode address. If the TAG bit is clear (forced type match) a comparator match is generated when the selected address appears on the system address bus. If the selected address is an opcode address, the match is generated CPU BUS TRACE BUFFER BUS INTERFACE TRANSITIONMATCH0 STATE COMPARATOR B COMPARATOR C COMPARATOR A STATE SEQUENCERMATCH1 MATCH2 TRACE READ TRACE DATA (DBG READ DATA BUS) CONTROL SECURE BREAKPOINT REQUESTS COMPARATOR MATCH CONTROL TRIGGER TAG & MATCH CONTROL LOGIC TAGSTAGHITS STATE TO CPU

S12S Debug Module (S12SDBG) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 297 when the opcode is fetched from the memory, which precedes the instruction execution by an indeﬁnite number of cycles due to instruction pipelining. For a comparator match of an opcode at an odd address when TAG = 0, the corresponding even address must be contained in the comparator register. Thus for an opcode at odd address (n), the comparator register must contain address (n–1). Once a successful comparator match has occurred, the condition that caused the original match is not veriﬁed again on subsequent matches. Thus if a particular data value is veriﬁed at a given address, this address may not still contain that data value when a subsequent match occurs. Match[0, 1, 2] map directly to Comparators [A, B, C] respectively, except in range modes (see Section 8.3.2.4, “Debug Control Register2 (DBGC2)). Comparator channel priority rules are described in the priority section (Section 8.4.3.4, “Channel Priorities).

8.4.2.1 Single Address Comparator Match

With range comparisons disabled, the match condition is an exact equivalence of address bus with the value stored in the comparator address registers. Further qualiﬁcation of the type of access (R/W, word/byte) and databus contents is possible, depending on comparator channel.

8.4.2.1.1 Comparator C

Comparator C offers only address and direction (R/W) comparison. The exact address is compared, thus with the comparator address register loaded with address (n) a word access of address (n–1) also accesses (n) but does not cause a match.

8.4.2.1.2 Comparator B

Comparator B offers address, direction (R/W) and access size (word/byte) comparison. If the SZE bit is set the access size (word or byte) is compared with the SZ bit value such that only the speciﬁed size of access causes a match. Thus if conﬁgured for a byte access of a particular address, a word access covering the same address does not lead to match. Assuming the access direction is not qualiﬁed (RWE=0), for simplicity, the size access considerations are shown in Table 8-32. Table 8-31. Comparator C Access Considerations Condition For Valid Match Comp C Address RWE RW Examples Read and write accesses of ADDR[n] ADDR[n] 1 1 A word access of ADDR[n-1] also accesses ADDR[n] but does not generate a match. The comparator address register must contain the exact address from the code.

0 X LDAA ADDR[n]

STAA #$BYTE ADDR[n] Write accesses of ADDR[n] ADDR[n] 1 0 STAA #$BYTE ADDR[n] Read accesses of ADDR[n] ADDR[n] 1 1 LDAA #$BYTE ADDR[n] Table 8-32. Comparator B Access Size Considerations Condition For Valid Match Comp B Address RWE SZE SZ8 Examples Word and byte accesses of ADDR[n] ADDR[n] 1 0 0 X MOVB #$BYTE ADDR[n] MOVW #$WORD ADDR[n]

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Access direction can also be used to qualify a match for Comparator B in the same way as described for Comparator C in Table 8-31.

8.4.2.1.3 Comparator A

Comparator A offers address, direction (R/W), access size (word/byte) and data bus comparison. Table 8-33 lists access considerations with data bus comparison. On word accesses the data byte of the lower address is mapped to DBGADH. Access direction can also be used to qualify a match for Comparator A in the same way as described for Comparator C in Table 8-31. Table 8-33. Comparator A Matches When Accessing ADDR[n]

8.4.2.1.4 Comparator A Data Bus Comparison NDB Dependency

Comparator A features an NDB control bit, which allows data bus comparators to be conﬁgured to either trigger on equivalence or trigger on difference. This allows monitoring of a difference in the contents of an address location from an expected value. When matching on an equivalence (NDB=0), each individual data bus bit position can be masked out by clearing the corresponding mask bit (DBGADHM/DBGADLM) so that it is ignored in the comparison. A Word accesses of ADDR[n] only ADDR[n] 0 1 0 MOVW #$WORD ADDR[n] LDD ADDR[n] Byte accesses of ADDR[n] only ADDR[n] 0 1 1 MOVB #$BYTE ADDR[n] LDAB ADDR[n] 1 A word access of ADDR[n-1] also accesses ADDR[n] but does not generate a match. The comparator address register must contain the exact address from the code. SZE SZ DBGADHM, DBGADLM Access DH=DBGADH, DL=DBGADL Comment

0 X $0000 Byte

0 X $FF00 Byte, data(ADDR[n])=DH

Word, data(ADDR[n])=DH, data(ADDR[n+1])=X Match data( ADDR[n])

0 X $00FF Word, data(ADDR[n])=X, data(ADDR[n+1])=DL Match data( ADDR[n+1])

0 X $00FF Byte, data(ADDR[n])=X, data(ADDR[n+1])=DL Possible unintended match

0 X $FFFF Word, data(ADDR[n])=DH, data(ADDR[n+1])=DL Match data( ADDR[n], ADDR[n+1])

0 X $FFFF Byte, data(ADDR[n])=DH, data(ADDR[n+1])=DL Possible unintended match

1 0 $0000 Word No databus comparison 1 0 $00FF Word, data(ADDR[n])=X, data(ADDR[n+1])=DL Match only data at ADDR[n+1] 1 0 $FF00 Word, data(ADDR[n])=DH, data(ADDR[n+1])=X Match only data at ADDR[n] 1 0 $FFFF Word, data(ADDR[n])=DH, data(ADDR[n+1])=DL Match data at ADDR[n] & ADDR[n+1] 1 1 $0000 Byte No databus comparison 1 1 $FF00 Byte, data(ADDR[n])=DH Match data at ADDR[n] Table 8-32. Comparator B Access Size Considerations Condition For Valid Match Comp B Address RWE SZE SZ8 Examples

S12S Debug Module (S12SDBG) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 299 match occurs when all data bus bits with corresponding mask bits set are equivalent. If all mask register bits are clear, then a match is based on the address bus only, the data bus is ignored. When matching on a difference, mask bits can be cleared to ignore bit positions. A match occurs when any data bus bit with corresponding mask bit set is different. Clearing all mask bits, causes all bits to be ignored and prevents a match because no difference can be detected. In this case address bus equivalence does not cause a match.

8.4.2.2 Range Comparisons

Using the AB comparator pair for a range comparison, the data bus can also be used for qualiﬁcation by using the comparator A data registers. Furthermore the DBGACTL RW and RWE bits can be used to qualify the range comparison on either a read or a write access. The corresponding DBGBCTL bits are ignored. The SZE and SZ control bits are ignored in range mode. The comparator A TAG bit is used to tag range comparisons. The comparator B TAG bit is ignored in range modes. In order for a range comparison using comparators A and B, both COMPEA and COMPEB must be set; to disable range comparisons both must be cleared. The comparator A BRK bit is used to for the AB range, the comparator B BRK bit is ignored in range mode. When conﬁgured for range comparisons and tagging, the ranges are accurate only to word boundaries.

8.4.2.2.1 Inside Range (CompA_Addr ≤ address ≤ CompB_Addr)

In the Inside Range comparator mode, comparator pair A and B can be conﬁgured for range comparisons. This conﬁguration depends upon the control register (DBGC2). The match condition requires that a valid match for both comparators happens on the same bus cycle. A match condition on only one comparator is not valid. An aligned word access which straddles the range boundary is valid only if the aligned address is inside the range.

8.4.2.2.2 Outside Range (address < CompA_Addr or address > CompB_Addr)

In the Outside Range comparator mode, comparator pair A and B can be conﬁgured for range comparisons. A single match condition on either of the comparators is recognized as valid. An aligned word access which straddles the range boundary is valid only if the aligned address is outside the range. Outside range mode in combination with tagging can be used to detect if the opcode fetches are from an unexpected range. In forced match mode the outside range match would typically be activated at any interrupt vector fetch or register access. This can be avoided by setting the upper range limit to $3FFFF or lower range limit to $00000 respectively. Table 8-34. NDB and MASK bit dependency NDB DBGADHM[n] / DBGADLM[n] Comment 0 0 Do not compare data bus bit. 0 1 Compare data bus bit. Match on equivalence. 1 0 Do not compare data bus bit. 1 1 Compare data bus bit. Match on difference.

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8.4.3 Match Modes (Forced or Tagged)

Match modes are used as qualiﬁers for a state sequencer change of state. The Comparator control register TAG bits select the match mode. The modes are described in the following sections.

8.4.3.1 Forced Match

When conﬁgured for forced matching, a comparator channel match can immediately initiate a transition to the next state sequencer state whereby the corresponding ﬂags in DBGSR are set. The state control register for the current state determines the next state. Forced matches are typically generated 2-3 bus cycles after the ﬁnal matching address bus cycle, independent of comparator RWE/RW settings. Furthermore since opcode fetches occur several cycles before the opcode execution a forced match of an opcode address typically precedes a tagged match at the same address.

8.4.3.2 Tagged Match

If a CPU taghit occurs a transition to another state sequencer state is initiated and the corresponding DBGSR ﬂags are set. For a comparator related taghit to occur, the DBG must ﬁrst attach tags to instructions as they are fetched from memory. When the tagged instruction reaches the execution stage of the instruction queue a taghit is generated by the CPU. This can initiate a state sequencer transition.

8.4.3.3 Immediate Trigger

Independent of comparator matches it is possible to initiate a tracing session and/or breakpoint by writing to the TRIG bit in DBGC1. If conﬁgured for begin aligned tracing, this triggers the state sequencer into the Final State, if conﬁgured for end alignment, setting the TRIG bit disarms the module, ending the session and issues a forced breakpoint request to the CPU. It is possible to set both TRIG and ARM simultaneously to generate an immediate trigger, independent of the current state of ARM.

8.4.3.4 Channel Priorities

In case of simultaneous matches the priority is resolved according to Table 8-35. The lower priority is suppressed. It is thus possible to miss a lower priority match if it occurs simultaneously with a higher priority. The priorities described inTable 8-35 dictate that in the case of simultaneous matches, the match pointing to ﬁnal state has highest priority followed by the lower channel number (0,1,2). Table 8-35. Channel Priorities Priority Source Action Highest TRIG Enter Final State Channel pointing to Final State Transition to next state as deﬁned by state control registers Match0 (force or tag hit) Transition to next state as deﬁned by state control registers Match1 (force or tag hit) Transition to next state as deﬁned by state control registers Lowest Match2 (force or tag hit) Transition to next state as deﬁned by state control registers

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8.4.4 State Sequence Control

Figure 8-24. State Sequencer Diagram The state sequencer allows a deﬁned sequence of events to provide a trigger point for tracing of data in the trace buffer. Once the DBG module has been armed by setting the ARM bit in the DBGC1 register, then state1 of the state sequencer is entered. Further transitions between the states are then controlled by the state control registers and channel matches. From Final State the only permitted transition is back to the disarmed state0. Transition between any of the states 1 to 3 is not restricted. Each transition updates the SSF[2:0] ﬂags in DBGSR accordingly to indicate the current state. Alternatively writing to the TRIG bit in DBGSC1, provides an immediate trigger independent of comparator matches. Independent of the state sequencer, each comparator channel can be individually conﬁgured to generate an immediate breakpoint when a match occurs through the use of the BRK bits in the DBGxCTL registers. Thus it is possible to generate an immediate breakpoint on selected channels, whilst a state sequencer transition can be initiated by a match on other channels. If a debug session is ended by a match on a channel the state sequencer transitions through Final State for a clock cycle to state0. This is independent of tracing and breakpoint activity, thus with tracing and breakpoints disabled, the state sequencer enters state0 and the debug module is disarmed.

8.4.4.1 Final State

On entering Final State a trigger may be issued to the trace buffer according to the trace alignment control as deﬁned by the TALIGN bit (see Section 8.3.2.3, “Debug Trace Control Register (DBGTCR)”). If the TSOURCE bit in DBGTCR is clear then the trace buffer is disabled and the transition to Final State can only generate a breakpoint request. In this case or upon completion of a tracing session when tracing is enabled, the ARM bit in the DBGC1 register is cleared, returning the module to the disarmed state0. If tracing is enabled a breakpoint request can occur at the end of the tracing session. If neither tracing nor breakpoints are enabled then when the ﬁnal state is reached it returns automatically to state0 and the debug module is disarmed. State1 Final State State3 ARM = 1 Session Complete (Disarm) State2 State 0 (Disarmed) ARM = 0 ARM = 0 ARM = 0

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8.4.5 Trace Buffer Operation

The trace buffer is a 64 lines deep by 20-bits wide RAM array. The DBG module stores trace information in the RAM array in a circular buffer format. The system accesses the RAM array through a register window (DBGTBH:DBGTBL) using 16-bit wide word accesses. After each complete 20-bit trace buffer line is read, an internal pointer into the RAM increments so that the next read receives fresh information. Data is stored in the format shown in Table 8-36 and Table 8-39. After each store the counter register DBGCNT is incremented. Tracing of CPU activity is disabled when the BDM is active. Reading the trace buffer whilst the DBG is armed returns invalid data and the trace buffer pointer is not incremented.

8.4.5.1 Trace Trigger Alignment

Using the TALIGN bit (see Section 8.3.2.3, “Debug Trace Control Register (DBGTCR)) it is possible to align the trigger with the end or the beginning of a tracing session. If End tracing is selected, tracing begins when the ARM bit in DBGC1 is set and State1 is entered; the transition to Final State signals the end of the tracing session. Tracing with Begin-Trigger starts at the opcode of the trigger. Using End Trigger or when the tracing is initiated by writing to the TRIG bit whilst conﬁgured for Begin-Trigger, tracing starts in the second cycle after the DBGC1 write cycle.

8.4.5.1.1 Storing with Begin-Trigger

Storing with Begin-Trigger, data is not stored in the Trace Buffer until the Final State is entered. Once the trigger condition is met the DBG module remains armed until 64 lines are stored in the Trace Buffer. If the trigger is at the address of the change-of-ﬂow instruction the change of ﬂow associated with the trigger is stored in the Trace Buffer. Using Begin-trigger together with tagging, if the tagged instruction is about to be executed then the trace is started. Upon completion of the tracing session the breakpoint is generated, thus the breakpoint does not occur at the tagged instruction boundary.

8.4.5.1.2 Storing with End-Trigger

Storing with End-Trigger, data is stored in the Trace Buffer until the Final State is entered, at which point the DBG module becomes disarmed and no more data is stored. If the trigger is at the address of a change of ﬂow instruction, the trigger event is not stored in the Trace Buffer.

8.4.5.2 Trace Modes

Four trace modes are available. The mode is selected using the TRCMOD bits in the DBGTCR register. Tracing is enabled using the TSOURCE bit in the DBGTCR register. The modes are described in the following subsections.

8.4.5.2.1 Normal Mode

In Normal Mode, change of ﬂow (COF) program counter (PC) addresses are stored. COF addresses are deﬁned as follows:

Source address of taken conditional branches (long, short, bit-conditional, and loop primitives)
Destination address of indexed JMP, JSR, and CALL instruction

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Destination address of RTI, RTS, and RTC instructions
Vector address of interrupts, except for BDM vectors LBRA, BRA, BSR, BGND as well as non-indexed JMP, JSR, and CALL instructions are not classiﬁed as change of ﬂow and are not stored in the trace buffer. Stored information includes the full 18-bit address bus and information bits, which contains a source/destination bit to indicate whether the stored address was a source address or destination address. NOTE When a COF instruction with destination address is executed, the destination address is stored to the trace buffer on instruction completion, indicating the COF has taken place. If an interrupt occurs simultaneously then the next instruction carried out is actually from the interrupt service routine. The instruction at the destination address of the original program ﬂow gets executed after the interrupt service routine. In the following example an IRQ interrupt occurs during execution of the indexed JMP at address MARK1. The BRN at the destination (SUB_1) is not executed until after the IRQ service routine but the destination address is entered into the trace buffer to indicate that the indexed JMP COF has taken place. LDX #SUB_1 MARK1 JMP 0,X ; IRQ interrupt occurs during execution of this MARK2 NOP ; SUB_1 BRN * ; JMP Destination address TRACE BUFFER ENTRY 1 ; RTI Destination address TRACE BUFFER ENTRY 3 NOP ; ADDR1 DBNE A,PART5 ; Source address TRACE BUFFER ENTRY 4 IRQ_ISR LDAB #$F0 ; IRQ Vector $FFF2 = TRACE BUFFER ENTRY 2 STAB VAR_C1 RTI ; The execution ﬂow taking into account the IRQ is as follows LDX #SUB_1 MARK1 JMP 0,X ; IRQ_ISR LDAB #$F0 ; STAB VAR_C1 RTI ; SUB_1 BRN * NOP ; ADDR1 DBNE A,PART5 ;

8.4.5.2.2 Loop1 Mode

Loop1 Mode, similarly to Normal Mode also stores only COF address information to the trace buffer, it however allows the ﬁltering out of redundant information. The intent of Loop1 Mode is to prevent the Trace Buffer from being ﬁlled entirely with duplicate information from a looping construct such as delays using the DBNE instruction or polling loops using

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BRSET/BRCLR instructions. Immediately after address information is placed in the Trace Buffer, the DBG module writes this value into a background register. This prevents consecutive duplicate address entries in the Trace Buffer resulting from repeated branches. Loop1 Mode only inhibits consecutive duplicate source address entries that would typically be stored in most tight looping constructs. It does not inhibit repeated entries of destination addresses or vector addresses, since repeated entries of these would most likely indicate a bug in the user’s code that the DBG module is designed to help ﬁnd.

8.4.5.2.3 Detail Mode

In Detail Mode, address and data for all memory and register accesses is stored in the trace buffer. This mode is intended to supply additional information on indexed, indirect addressing modes where storing only the destination address would not provide all information required for a user to determine where the code is in error. This mode also features information bit storage to the trace buffer, for each address byte storage. The information bits indicate the size of access (word or byte) and the type of access (read or write). When tracing in Detail Mode, all cycles are traced except those when the CPU is either in a free or opcode fetch cycle.

8.4.5.2.4 Compressed Pure PC Mode

In Compressed Pure PC Mode, the PC addresses of all executed opcodes, including illegal opcodes are stored. A compressed storage format is used to increase the effective depth of the trace buffer. This is achieved by storing the lower order bits each time and using 2 information bits to indicate if a 64 byte boundary has been crossed, in which case the full PC is stored. Each Trace Buffer row consists of 2 information bits and 18 PC address bits NOTE: When tracing is terminated using forced breakpoints, latency in breakpoint generation means that opcodes following the opcode causing the breakpoint can be stored to the trace buffer. The number of opcodes is dependent on program ﬂow. This can be avoided by using tagged breakpoints.

8.4.5.3 Trace Buffer Organization (Normal, Loop1, Detail modes)

ADRH, ADRM, ADRL denote address high, middle and low byte respectively. The numerical sufﬁx refers to the tracing count. The information format for Loop1 and Normal modes is identical. In Detail mode, the address and data for each entry are stored on consecutive lines, thus the maximum number of entries is 32. In this case DBGCNT bits are incremented twice, once for the address line and once for the data line, on each trace buffer entry. In Detail mode CINF comprises of R/W and size access information (CRW and CSZ respectively). Single byte data accesses in Detail Mode are always stored to the low byte of the trace buffer (DATAL) and the high byte is cleared. When tracing word accesses, the byte at the lower address is always stored to trace buffer byte1 and the byte at the higher address is stored to byte0.

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8.4.5.3.1 Information Bit Organization

The format of the bits is dependent upon the active trace mode as described below. Field2 Bits in Detail Mode In Detail Mode the CSZ and CRW bits indicate the type of access being made by the CPU. Table 8-36. Trace Buffer Organization (Normal,Loop1,Detail modes) Mode Entry Number 4-bits 8-bits 8-bits Field 2 Field 1 Field 0 Detail Mode Entry 1 CINF1,ADRH1 ADRM1 ADRL1

0 DATAH1 DATAL1

CINF2,ADRH2 ADRM2 ADRL2

0 DATAH2 DATAL2

CSZ CRW ADDR[17] ADDR[16] Figure 8-25. Field2 Bits in Detail Mode Table 8-37. Field Descriptions Bit Description CSZ Access Type Indicator— This bit indicates if the access was a byte or word size when tracing in Detail Mode

0 Word Access

1 Byte Access

Read Write Indicator — This bit indicates if the corresponding stored address corresponds to a read or write access when tracing in Detail Mode.

0 Write Access

1 Read Access

ADDR[17] Address Bus bit 17— Corresponds to system address bus bit 17. ADDR[16] Address Bus bit 16— Corresponds to system address bus bit 16.

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Field2 Bits in Normal and Loop1 Modes

8.4.5.4 Trace Buffer Organization (Compressed Pure PC mode)

Table 8-39. Trace Buffer Organization Example (Compressed PurePC mode) Bit 3 Bit 2 Bit 1 Bit 0 CSD CVA PC17 PC16 Figure 8-26. Information Bits PCH Table 8-38. PCH Field Descriptions Bit Description CSD Source Destination Indicator — In Normal and Loop1 mode this bit indicates if the corresponding stored address is a source or destination address. This bit has no meaning in Compressed Pure PC mode.

0 Source Address

1 Destination Address

Vector Indicator — In Normal and Loop1 mode this bit indicates if the corresponding stored address is a vector address. Vector addresses are destination addresses, thus if CVA is set, then the corresponding CSD is also set. This bit has no meaning in Compressed Pure PC mode .

0 Non-Vector Destination Address

1 Vector Destination Address

Program Counter bit 17— In Normal and Loop1 mode this bit corresponds to program counter bit 17. PC16 Program Counter bit 16— In Normal and Loop1 mode this bit corresponds to program counter bit 16. Mode Line Number 2-bits 6-bits 6-bits 6-bits Field 3 Field 2 Field 1 Field 0 Compressed Pure PC Mode Line 1 00 PC1 (Initial 18-bit PC Base Address) Line 2 11 PC4 PC3 PC2 Line 3 01 0 0 PC5 Line 4 00 PC6 (New 18-bit PC Base Address) Line 5 10 0 PC8 PC7 Line 6 00 PC9 (New 18-bit PC Base Address)

S12S Debug Module (S12SDBG) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 307 Field3 Bits in Compressed Pure PC Modes Each time that PC[17:6] differs form the previous base PC[17:6], then a new base address is stored. The base address zero value is the lowest address in the 64 address range The ﬁrst line of the trace buffer always gets a base PC address, this applies also on rollover.

8.4.5.5 Reading Data from Trace Buffer

The data stored in the Trace Buffer can be read provided the DBG module is not armed, is conﬁgured for tracing (TSOURCE bit is set) and the system not secured. When the ARM bit is written to 1 the trace buffer is locked to prevent reading. The trace buffer can only be unlocked for reading by a single aligned word write to DBGTB when the module is disarmed. The Trace Buffer can only be read through the DBGTB register using aligned word reads, any byte or misaligned reads return 0 and do not cause the trace buffer pointer to increment to the next trace buffer address. The Trace Buffer data is read out ﬁrst-in ﬁrst-out. By reading CNT in DBGCNT the number of valid lines can be determined. DBGCNT does not decrement as data is read. Whilst reading an internal pointer is used to determine the next line to be read. After a tracing session, the pointer points to the oldest data entry, thus if no overﬂow has occurred, the pointer points to line0, otherwise it points to the line with the oldest entry. In compressed Pure PC mode on rollover the line with the oldest data entry may also contain newer data entries in ﬁelds 0 and 1. Thus if rollover is indicated by the TBF bit, the line status must be decoded using the INF bits in ﬁeld3 of that line. If both INF bits are clear then the line contains only entires from before the last rollover. If INF0=1 then ﬁeld 0 contains post rollover data but ﬁelds 1 and 2 contain pre rollover data. If INF1=1 then ﬁelds 0 and 1 contain post rollover data but ﬁeld 2 contains pre rollover data. The pointer is initialized by each aligned write to DBGTBH to point to the oldest data again. This enables an interrupted trace buffer read sequence to be easily restarted from the oldest data entry. The least signiﬁcant word of line is read out ﬁrst. This corresponds to the ﬁelds 1 and 0 ofTable 8-36. The next word read returns ﬁeld 2 in the least signiﬁcant bits [3:0] and “0” for bits [15:4]. Reading the Trace Buffer while the DBG module is armed returns invalid data and no shifting of the RAM pointer occurs.

8.4.5.6 Trace Buffer Reset State

The Trace Buffer contents and DBGCNT bits are not initialized by a system reset. Thus should a system reset occur, the trace session information from immediately before the reset occurred can be read out and the number of valid lines in the trace buffer is indicated by DBGCNT. The internal pointer to the current Table 8-40. Compressed Pure PC Mode Field 3 Information Bit Encoding INF1 INF0 TRACE BUFFER ROW CONTENT 0 0 Base PC address TB[17:0] contains a full PC[17:0] value 0 1 Trace Buffer[5:0] contain incremental PC relative to base address zero value 1 0 Trace Buffer[11:0] contain next 2 incremental PCs relative to base address zero value 1 1 Trace Buffer[17:0] contain next 3 incremental PCs relative to base address zero value

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trace buffer address is initialized by unlocking the trace buffer and points to the oldest valid data even if a reset occurred during the tracing session. To read the trace buffer after a reset, TSOURCE must be set, otherwise the trace buffer reads as all zeroes. Generally debugging occurrences of system resets is best handled using end trigger alignment since the reset may occur before the trace trigger, which in the begin trigger alignment case means no information would be stored in the trace buffer. The Trace Buffer contents and DBGCNT bits are undeﬁned following a POR. NOTE An external pin RESET that occurs simultaneous to a trace buffer entry can, in very seldom cases, lead to either that entry being corrupted or the ﬁrst entry of the session being corrupted. In such cases the other contents of the trace buffer still contain valid tracing information. The case occurs when the reset assertion coincides with the trace buffer entry clock edge.

8.4.6 Tagging

A tag follows program information as it advances through the instruction queue. When a tagged instruction reaches the head of the queue a tag hit occurs and can initiate a state sequencer transition. Each comparator control register features a TAG bit, which controls whether the comparator match causes a state sequencer transition immediately or tags the opcode at the matched address. If a comparator is enabled for tagged comparisons, the address stored in the comparator match address registers must be an opcode address. Using Begin trigger together with tagging, if the tagged instruction is about to be executed then the transition to the next state sequencer state occurs. If the transition is to the Final State, tracing is started. Only upon completion of the tracing session can a breakpoint be generated. Using End alignment, when the tagged instruction is about to be executed and the next transition is to Final State then a breakpoint is generated immediately, before the tagged instruction is carried out. R/W monitoring, access size (SZ) monitoring and data bus monitoring are not useful if tagging is selected, since the tag is attached to the opcode at the matched address and is not dependent on the data bus nor on ta type of access. Thus these bits are ignored if tagging is selected. When conﬁgured for range comparisons and tagging, the ranges are accurate only to word boundaries. Tagging is disabled when the BDM becomes active.

8.4.7 Breakpoints

It is possible to generate breakpoints from channel transitions to ﬁnal state or using software to write to the TRIG bit in the DBGC1 register.

8.4.7.1 Breakpoints From Comparator Channels

Breakpoints can be generated when the state sequencer transitions to the Final State. If conﬁgured for tagging, then the breakpoint is generated when the tagged opcode reaches the execution stage of the instruction queue.

S12S Debug Module (S12SDBG) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 309 If a tracing session is selected by the TSOURCE bit, breakpoints are requested when the tracing session has completed, thus if Begin aligned triggering is selected, the breakpoint is requested only on completion of the subsequent trace (see Table 8-41). If no tracing session is selected, breakpoints are requested immediately. If the BRK bit is set, then the associated breakpoint is generated immediately independent of tracing trigger alignment.

8.4.7.2 Breakpoints Generated Via The TRIG Bit

If a TRIG triggers occur, the Final State is entered whereby tracing trigger alignment is deﬁned by the TALIGN bit. If a tracing session is selected by the TSOURCE bit, breakpoints are requested when the tracing session has completed, thus if Begin aligned triggering is selected, the breakpoint is requested only on completion of the subsequent trace (see Table 8-41). If no tracing session is selected, breakpoints are requested immediately. TRIG breakpoints are possible with a single write to DBGC1, setting ARM and TRIG simultaneously.

8.4.7.3 Breakpoint Priorities

If a TRIG trigger occurs after Begin aligned tracing has already started, then the TRIG no longer has an effect. When the associated tracing session is complete, the breakpoint occurs. Similarly if a TRIG is followed by a subsequent comparator channel match, it has no effect, since tracing has already started. If a forced SWI breakpoint coincides with a BGND in user code with BDM enabled, then the BDM is activated by the BGND and the breakpoint to SWI is suppressed.

8.4.7.3.1 DBG Breakpoint Priorities And BDM Interfacing

Breakpoint operation is dependent on the state of the BDM module. If the BDM module is active, the CPU is executing out of BDM ﬁrmware, thus comparator matches and associated breakpoints are disabled. In addition, while executing a BDM TRACE command, tagging into BDM is disabled. If BDM is not active, the breakpoint gives priority to BDM requests over SWI requests if the breakpoint happens to coincide with a SWI instruction in user code. On returning from BDM, the SWI from user code gets executed. Table 8-41. Breakpoint Setup For CPU Breakpoints BRK TALIGN DBGBRK Breakpoint Alignment 0 0 0 Fill Trace Buffer until trigger then disarm (no breakpoints) 0 0 1 Fill Trace Buffer until trigger, then breakpoint request occurs 0 1 0 Start Trace Buffer at trigger (no breakpoints) 0 1 1 Start Trace Buffer at trigger A breakpoint request occurs when Trace Buffer is full 1 x 1 Terminate tracing and generate breakpoint immediately on trigger 1 x 0 Terminate tracing immediately on trigger

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BDM cannot be entered from a breakpoint unless the ENABLE bit is set in the BDM. If entry to BDM via a BGND instruction is attempted and the ENABLE bit in the BDM is cleared, the CPU actually executes the BDM ﬁrmware code, checks the ENABLE and returns if ENABLE is not set. If not serviced by the monitor then the breakpoint is re-asserted when the BDM returns to normal CPU ﬂow. If the comparator register contents coincide with the SWI/BDM vector address then an SWI in user code could coincide with a DBG breakpoint. The CPU ensures that BDM requests have a higher priority than SWI requests. Returning from the BDM/SWI service routine care must be taken to avoid a repeated breakpoint at the same address. Should a tagged or forced breakpoint coincide with a BGND in user code, then the instruction that follows the BGND instruction is the ﬁrst instruction executed when normal program execution resumes. NOTE When program control returns from a tagged breakpoint using an RTI or BDM GO command without program counter modiﬁcation it returns to the instruction whose tag generated the breakpoint. To avoid a repeated breakpoint at the same location reconﬁgure the DBG module in the SWI routine, if conﬁgured for an SWI breakpoint, or over the BDM interface by executing a TRACE command before the GO to increment the program ﬂow past the tagged instruction.

8.5 Application Information

8.5.1 State Machine scenarios

Deﬁning the state control registers as SCR1,SCR2, SCR3 and M0,M1,M2 as matches on channels 0,1,2 respectively. SCR encoding supported by S12SDBGV1 are shown in black. SCR encoding supported only in S12SDBGV2 are shown in red. For backwards compatibility the new scenarios use a 4th bit in each SCR register. Thus the existing encoding for SCRx[2:0] is not changed. Table 8-42. Breakpoint Mapping Summary DBGBRK BDM Bit (DBGC1[4]) BDM Enabled BDM Active Breakpoint Mapping

0 X X X No Breakpoint

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8.5.2 Scenario 1

A trigger is generated if a given sequence of 3 code events is executed. Figure 8-27. Scenario 1 Scenario 1 is possible with S12SDBGV1 SCR encoding

8.5.3 Scenario 2

A trigger is generated if a given sequence of 2 code events is executed. Figure 8-28. Scenario 2a A trigger is generated if a given sequence of 2 code events is executed, whereby the ﬁrst event is entry into a range (COMPA,COMPB conﬁgured for range mode). M1 is disabled in range modes. Figure 8-29. Scenario 2b A trigger is generated if a given sequence of 2 code events is executed, whereby the second event is entry into a range (COMPA,COMPB conﬁgured for range mode) Figure 8-30. Scenario 2c All 3 scenarios 2a,2b,2c are possible with the S12SDBGV1 SCR encoding State1 Final StateState3State2 SCR1=0011 SCR2=0010 SCR3=0111 M1 M2 M0 State1 Final StateState2 SCR1=0011 SCR2=0101 M1 M2 State1 Final StateState2 SCR1=0111 SCR2=0101 M01 M2 State1 Final StateState2 SCR1=0010 SCR2=0011 M2 M0

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8.5.4 Scenario 3

A trigger is generated immediately when one of up to 3 given events occurs Figure 8-31. Scenario 3 Scenario 3 is possible with S12SDBGV1 SCR encoding

8.5.5 Scenario 4

Trigger if a sequence of 2 events is carried out in an incorrect order. Event A must be followed by event B and event B must be followed by event A. 2 consecutive occurances of event A without an intermediate event B cause a trigger. Similarly 2 consecutive occurances of event B without an intermediate event A cause a trigger. This is possible by using CompA and CompC to match on the same address as shown. Figure 8-32. Scenario 4a This scenario is currently not possible using 2 comparators only. S12SDBGV2 makes it possible with 2 comparators, State 3 allowing a M0 to return to state 2, whilst a M2 leads to ﬁnal state as shown. Figure 8-33. Scenario 4b (with 2 comparators) The advantage of using only 2 channels is that now range comparisons can be included (channel0) State1 Final State SCR1=0000 M012 State1 State 3 Final State State2M0 M0M2M1 SCR1=0100 SCR2=0011 SCR3=0001 State1 State 3 Final State State2M0 M01M0M2 SCR1=0110 SCR2=1100 SCR3=1110 M1 disabled in range mode

S12S Debug Module (S12SDBG) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 313 This however violates the S12SDBGV1 speciﬁcation, which states that a match leading to ﬁnal state always has priority in case of a simultaneous match, whilst priority is also given to the lowest channel number. For S12SDBG the corresponding CPU priority decoder is removed to support this, such that on simultaneous taghits, taghits pointing to ﬁnal state have highest priority. If no taghit points to ﬁnal state then the lowest channel number has priority. Thus with the above encoding from State3, the CPU and DBG would break on a simultaneous M0/M2.

8.5.6 Scenario 5

Trigger if following event A, event C precedes event B. ie. the expected execution ﬂow is A->B->C. Figure 8-34. Scenario 5 Scenario 5 is possible with the S12SDBGV1 SCR encoding

8.5.7 Scenario 6

Trigger if event A occurs twice in succession before any of 2 other events (BC) occurs. This scenario is not possible using the S12SDBGV1 SCR encoding. S12SDBGV2 includes additions shown in red. The change in SCR1 encoding also has the advantage that a State1->State3 transition using M0 is now possible. This is advantageous because range and data bus comparisons use channel0 only. Figure 8-35. Scenario 6

8.5.8 Scenario 7

Trigger when a series of 3 events is executed out of order. Specifying the event order as M1,M2,M0 to run in loops (120120120). Any deviation from that order should trigger. This scenario is not possible using the State1 Final StateState2 SCR1=0011 SCR2=0110 M1 M0 State1 Final StateState3 SCR1=1001 SCR3=1010 M0 M0 M12

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S12SDBGV1 SCR encoding because OR possibilities are very limited in the channel encoding. By adding OR forks as shown in red this scenario is possible. Figure 8-36. Scenario 7 On simultaneous matches the lowest channel number has priority so with this conﬁguration the forking from State1 has the peculiar effect that a simultaneous match0/match1 transitions to ﬁnal state but a simultaneous match2/match1transitions to state2.

8.5.9 Scenario 8

Trigger when a routine/event at M2 follows either M1 or M0. Figure 8-37. Scenario 8a Trigger when an event M2 is followed by either event M0 or event M1 Figure 8-38. Scenario 8b Scenario 8a and 8b are possible with the S12SDBGV1 and S12SDBGV2 SCR encoding State1 Final StateState3State2 SCR1=1101 SCR2=1100 SCR3=1101 M1 M2 M12 M02 M01 State1 Final StateState2 SCR1=0111 SCR2=0101 M01 M2 State1 Final StateState2 SCR1=0010 SCR2=0111 M2 M01

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8.5.10 Scenario 9

Trigger when a routine/event at A (M2) does not follow either B or C (M1 or M0) before they are executed again. This cannot be realised with theS12SDBGV1 SCR encoding due to OR limitations. By changing the SCR2 encoding as shown in red this scenario becomes possible. Figure 8-39. Scenario 9

8.5.11 Scenario 10

Trigger if an event M0 occurs following up to two successive M2 events without the resetting event M1. As shown up to 2 consecutive M2 events are allowed, whereby a reset to State1 is possible after either one or two M2 events. If an event M0 occurs following the second M2, before M1 resets to State1 then a trigger is generated. Conﬁguring CompA and CompC the same, it is possible to generate a breakpoint on the third consecutive occurance of event M0 without a reset M1. Figure 8-40. Scenario 10a Figure 8-41. Scenario 10b Scenario 10b shows the case that after M2 then M1 must occur before M0. Starting from a particular point in code, event M2 must always be followed by M1 before M0. If after any M2, event M0 occurs before M1 then a trigger is generated. State1 Final StateState2 SCR1=0111 SCR2=1111 M01 M01 State1 Final StateState3State2 SCR1=0010 SCR2=0100 SCR3=0010 M2 M2 M0 State1 Final StateState3State2 SCR1=0010 SCR2=0011 SCR3=0000 M2 M1

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MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 317 Chapter 9 Security (S12XS9SECV2)

9.1 Introduction

This speciﬁcation describes the function of the security mechanism in the MC9S12G-Family (9SEC). NOTE No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH and/or EEPROM difﬁcult for unauthorized users.

9.1.1 Features

The user must be reminded that part of the security must lie with the application code. An extreme example would be application code that dumps the contents of the internal memory. This would defeat the purpose of security. At the same time, the user may also wish to put a backdoor in the application program. An example of this is the user downloads a security key through the SCI, which allows access to a programming routine that updates parameters stored in another section of the Flash memory. The security features of the MC9S12G-Family (in secure mode) are:

Protect the content of non-volatile memories (Flash, EEPROM)
Execution of NVM commands is restricted
Disable access to internal memory via background debug module (BDM)

9.1.2 Modes of Operation

Table 9-2 gives an overview over availability of security relevant features in unsecure and secure modes. Table 9-1. Revision History Revision Number Revision Date Sections Affected Description of Changes 02.00 27 Aug 2004 reviewed and updated for S12XD architecture 02.01 21 Feb 2007 added S12XE, S12XF and S12XS architectures 02.02 19 Apr 2007 corrected statement about Backdoor key access via BDM on XE, XF , XS Table 9-2. Feature Availability in Unsecure and Secure Modes on S12XS Unsecure Mode Secure Mode NS SS NX ES EX ST NS SS NX ES EX ST Flash Array Access ✔✔ ✔✔

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9.1.3 Securing the Microcontroller

Once the user has programmed the Flash and EEPROM, the chip can be secured by programming the security bits located in the options/security byte in the Flash memory array. These non-volatile bits will keep the device secured through reset and power-down. The options/security byte is located at address 0xFF0F (= global address 0x7F_FF0F) in the Flash memory array. This byte can be erased and programmed like any other Flash location. Two bits of this byte are used for security (SEC[1:0]). On devices which have a memory page window, the Flash options/security byte is also available at address 0xBF0F by selecting page 0x3F with the PPAGE register. The contents of this byte are copied into the Flash security register (FSEC) during a reset sequence. The meaning of the bits KEYEN[1:0] is shown in Table 9-3. Please refer to Section 9.1.5.1, “Unsecuring the MCU Using the Backdoor Key Access” for more information. The meaning of the security bits SEC[1:0] is shown inTable 9-4. For security reasons, the state of device security is controlled by two bits. To put the device in unsecured mode, these bits must be programmed to SEC[1:0] = ‘10’. All other combinations put the device in a secured mode. The recommended value to put the device in secured state is the inverse of the unsecured state, i.e. SEC[1:0] = ‘01’. EEPROM Array Access ✔✔ ✔✔ NVM Commands ✔1 ✔ ✔1 ✔1 BDM ✔✔ — ✔2 DBG Module Trace ✔✔ —— 1 Restricted NVM command set only. Please refer to the NVM wrapper block guides for detailed information. 2 BDM hardware commands restricted to peripheral registers only. 76543210 0xFF0F KEYEN1 KEYEN0 NV5 NV4 NV3 NV2 SEC1 SEC0 Figure 9-1. Flash Options/Security Byte Table 9-3. Backdoor Key Access Enable Bits KEYEN[1:0] Backdoor Key Access Enabled 00 0 (disabled) 01 0 (disabled) 10 1 (enabled) 11 0 (disabled) Table 9-2. Feature Availability in Unsecure and Secure Modes on S12XS Unsecure Mode Secure Mode NS SS NX ES EX ST NS SS NX ES EX ST

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9.1.4 Operation of the Secured Microcontroller

By securing the device, unauthorized access to the EEPROM and Flash memory contents can be prevented. However, it must be understood that the security of the EEPROM and Flash memory contents also depends on the design of the application program. For example, if the application has the capability of downloading code through a serial port and then executing that code (e.g. an application containing bootloader code), then this capability could potentially be used to read the EEPROM and Flash memory contents even when the microcontroller is in the secure state. In this example, the security of the application could be enhanced by requiring a challenge/response authentication before any code can be downloaded. Secured operation has the following effects on the microcontroller:

9.1.4.1 Normal Single Chip Mode (NS)

Background debug module (BDM) operation is completely disabled.
Execution of Flash and EEPROM commands is restricted. Please refer to the NVM block guide for details.
Tracing code execution using the DBG module is disabled.

9.1.4.2 Special Single Chip Mode (SS)

BDM ﬁrmware commands are disabled.
BDM hardware commands are restricted to the register space.
Execution of Flash and EEPROM commands is restricted. Please refer to the NVM block guide for details.
Tracing code execution using the DBG module is disabled. Special single chip mode means BDM is active after reset. The availability of BDM ﬁrmware commands depends on the security state of the device. The BDM secure ﬁrmware ﬁrst performs a blank check of both the Flash memory and the EEPROM. If the blank check succeeds, security will be temporarily turned off and the state of the security bits in the appropriate Flash memory location can be changed If the blank check fails, security will remain active, only the BDM hardware commands will be enabled, and the accessible memory space is restricted to the peripheral register area. This will allow the BDM to be used to erase the EEPROM and Flash memory without giving access to their contents. After erasing both Flash Table 9-4. Security Bits SEC[1:0] Security State 00 1 (secured) 01 1 (secured) 10 0 (unsecured) 11 1 (secured)

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memory and EEPROM, another reset into special single chip mode will cause the blank check to succeed and the options/security byte can be programmed to “unsecured” state via BDM. While the BDM is executing the blank check, the BDM interface is completely blocked, which means that all BDM commands are temporarily blocked.

9.1.5 Unsecuring the Microcontroller

Unsecuring the microcontroller can be done by three different methods: 1. Backdoor key access 2. Reprogramming the security bits 3. Complete memory erase (special modes)

9.1.5.1 Unsecuring the MCU Using the Backdoor Key Access

In normal modes (single chip and expanded), security can be temporarily disabled using the backdoor key access method. This method requires that:

The backdoor key at 0xFF00–0xFF07 (= global addresses 0x3_FF00–0x3_FF07) has been programmed to a valid value.
The KEYEN[1:0] bits within the Flash options/security byte select ‘enabled’.
In single chip mode, the application program programmed into the microcontroller must be designed to have the capability to write to the backdoor key locations. The backdoor key values themselves would not normally be stored within the application data, which means the application program would have to be designed to receive the backdoor key values from an external source (e.g. through a serial port). The backdoor key access method allows debugging of a secured microcontroller without having to erase the Flash. This is particularly useful for failure analysis. NOTE No word of the backdoor key is allowed to have the value 0x0000 or 0xFFFF.

9.1.6 Reprogramming the Security Bits

In normal single chip mode (NS), security can also be disabled by erasing and reprogramming the security bits within Flash options/security byte to the unsecured value. Because the erase operation will erase the entire sector from 0xFE00–0xFFFF (0x7F_FE00–0x7F_FFFF), the backdoor key and the interrupt vectors will also be erased; this method is not recommended for normal single chip mode. The application software can only erase and program the Flash options/security byte if the Flash sector containing the Flash options/security byte is not protected (see Flash protection). Thus Flash protection is a useful means of preventing this method. The microcontroller will enter the unsecured state after the next reset following the programming of the security bits to the unsecured value. This method requires that:

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The application software previously programmed into the microcontroller has been designed to have the capability to erase and program the Flash options/security byte, or security is ﬁrst disabled using the backdoor key method, allowing BDM to be used to issue commands to erase and program the Flash options/security byte.
The Flash sector containing the Flash options/security byte is not protected.

9.1.7 Complete Memory Erase (Special Modes)

The microcontroller can be unsecured in special modes by erasing the entire EEPROM and Flash memory contents. When a secure microcontroller is reset into special single chip mode (SS), the BDM ﬁrmware veriﬁes whether the EEPROM and Flash memory are erased. If any EEPROM or Flash memory address is not erased, only BDM hardware commands are enabled. BDM hardware commands can then be used to write to the EEPROM and Flash registers to mass erase the EEPROM and all Flash memory blocks. When next reset into special single chip mode, the BDM ﬁrmware will again verify whether all EEPROM and Flash memory are erased, and this being the case, will enable all BDM commands, allowing the Flash options/security byte to be programmed to the unsecured value. The security bits SEC[1:0] in the Flash security register will indicate the unsecure state following the next reset.

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MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 323 Chapter 10 S12 Clock, Reset and Power Management Unit (S12CPMU)

10.1 Introduction

This speciﬁcation describes the function of the Clock, Reset and Power Management Unit (S12CPMU).

The Pierce oscillator (XOSCLCP) provides a robust, low-noise and low-power external clock source. It is designed for optimal start-up margin with typical quartz crystals and ceramic resonators.
The V oltage regulator (IVREG) operates from the range 3.13V to 5.5V. It provides all the required chip internal voltages and voltage monitors.
The Phase Locked Loop (PLL) provides a highly accurate frequency multiplier with internal ﬁlter.
The Internal Reference Clock (IRC1M) provides a1MHz clock.

10.1.1 Features

The Pierce Oscillator (XOSCLCP) contains circuitry to dynamically control current gain in the output amplitude. This ensures a signal with low harmonic distortion, low power and good noise immunity.

Supports quartz crystals or ceramic resonators from 4MHz to 16MHz.
High noise immunity due to input hysteresis and spike ﬁltering.
Low RF emissions with peak-to-peak swing limited dynamically Version Number Revision Date Effective Date Author Description of Changes V04.09 22 Jun 10 22 Jun 10 Changed IP-Name from OSCLCP to XOSCLCP , added OSCCLK_LCP clock name intoFigure 10-1 and Figure 10-2 updated description of Section 10.2.2, “EXTAL and XTAL. V04.10 01 Jul 10 01 Jul 10 Added TC trimming to feature list V04.11 23 Aug 10 23 Aug 10 Removed feature of adaptive oscillator ﬁlter. Register bits 6 and 4to 0in the CPMUOSC register are marked reserved and do not alter.

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Transconductance (gm) sized for optimum start-up margin for typical crystals
Dynamic gain control eliminates the need for external current limiting resistor
Integrated resistor eliminates the need for external bias resistor.
Low power consumption: Operates from internal 1.8V (nominal) supply, Amplitude control limits power The V oltage Regulator (IVREG) has the following features:
Input voltage range from 3.13V to 5.5V
Low-voltage detect (LVD) with low-voltage interrupt (LVI)
Power-on reset (POR)
Low-voltage reset (LVR) The Phase Locked Loop (PLL) has the following features:
highly accurate and phase locked frequency multiplier
Conﬁgurable internal ﬁlter for best stability and lock time.
Frequency modulation for deﬁned jitter and reduced emission
Automatic frequency lock detector
Interrupt request on entry or exit from locked condition
Reference clock either external (crystal) or internal square wave (1MHz IRC1M) based.
PLL stability is sufﬁcient for LIN communication, even if using IRC1M as reference clock The Internal Reference Clock (IRC1M) has the following features:
Frequency trimming (A factory trim value for 1MHz is loaded from Flash Memory into the IRCTRIM register after reset, which can be overwritten by application if required)
Temperature Coefﬁcient (TC) trimming. (A factory trim value is loaded from Flash Memory into the IRCTRIM register to turned off TC trimming after reset. Application can trim the TC if required by overwriting the IRCTRIM register). Other features of the S12CPMU include
Clock monitor to detect loss of crystal
Autonomous periodical interrupt (API)
Bus Clock Generator — Clock switch to select either PLLCLK or external crystal/resonator based Bus Clock — PLLCLK divider to adjust system speed
System Reset generation from the following possible sources: — Power-on reset (POR) — Low-voltage reset (LVR) — Illegal address access

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10.1.2 Modes of Operation

This subsection lists and brieﬂy describes all operating modes supported by the S12CPMU.

10.1.2.1 Run Mode

The voltage regulator is in Full Performance Mode (FPM). The Phase Locked Loop (PLL) is on. The Internal Reference Clock (IRC1M) is on. The API is available.

PLL Engaged Internal (PEI) — This is the default mode after System Reset and Power-On Reset. — The Bus Clock is based on the PLLCLK. — After reset the PLL is conﬁgured for 50 MHz VCOCLK operation Post divider is 0x03, so PLLCLK is VCOCLK divided by 4, that is 12.5MHz and Bus Clock is 6.25MHz. The PLL can be re-conﬁgured for other bus frequencies. — The reference clock for the PLL (REFCLK) is based on internal reference clock IRC1M
PLL Engaged External (PEE) — The Bus Clock is based n the PLLCLK. — This mode can be entered from default mode PEI by performing the following steps: – Conﬁgure the PLL for desired bus frequency. – Program the reference divider (REFDIV[3:0] bits) to divide down oscillator frequency if necessary. – Enable the external oscillator (OSCE bit) – Wait for oscillator to start up (UPOSC=1) and PLL to lock (LOCK=1).
PLL Bypassed External (PBE) — The Bus Clock is based on the Oscillator Clock (OSCCLK). — The PLLCLK is always on to qualify the external oscillator clock. Therefore it is necessary to make sure a valid PLL conﬁguration is used for the selected oscillator frequency. — This mode can be entered from default mode PEI by performing the following steps: – Make sure the PLL conﬁguration is valid for the selected oscillator frequency. – Enable the external oscillator (OSCE bit) – Wait for oscillator to start up (UPOSC=1) – Select the Oscillator Clock (OSCCLK) as Bus Clock (PLLSEL=0).

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— The PLLCLK is on and used to qualify the external oscillator clock.

10.1.2.2 Wait Mode

For S12CPMU Wait Mode is the same as Run Mode.

10.1.2.3 Stop Mode

This mode is entered by executing the CPU STOP instruction. The voltage regulator is in Reduced Power Mode (RPM). The API is available. The Phase Locked Loop (PLL) is off. The Internal Reference Clock (IRC1M) is off. Core Clock, Bus Clock and BDM Clock are stopped. Depending on the setting of the PSTP and the OSCE bit, Stop Mode can be differentiated between Full Stop Mode (PSTP = 0 or OSCE=0) and Pseudo Stop Mode (PSTP = 1 and OSCE=1). In addition, the behavior of the COP in each mode will change based on the clocking method selected by COPOSCSEL[1:0].

Full Stop Mode (PSTP = 0 or OSCE=0) External oscillator (XOSCLCP) is disabled. — If COPOSCSEL1=0: The COP and RTI counters halt during Full Stop Mode. After wake-up from Full Stop Mode the Core Clock and Bus Clock are running on PLLCLK (PLLSEL=1). COP and RTI are running on IRCCLK (COPOSCSEL0=0, RTIOSCSEL=0). — If COPOSCSEL1=1: During Full Stop Mode the COP is running on ACLK (trimmable internal RC-Oscillator clock) and the RTI counter halts. After wake-up from Full Stop Mode the Core Clock and Bus Clock are running on PLLCLK (PLLSEL=1). The COP runs on ACLK and RTI is running on IRCCLK (COPOSCSEL0=0, RTIOSCSEL=0).
Pseudo Stop Mode (PSTP = 1 and OSCE=1) External oscillator (XOSCLCP) continues to run. — If COPOSCSEL1=0: If the respective enable bits are set (PCE=1 and PRE=1) the COP and RTI will continue to run with a clock derived from the oscillator clock. The clock conﬁguration bits PLLSEL, COPOSCSEL0, RTIOSCSEL are unchanged. — If COPOSCSEL1=1: If the respective enable bit for the RTI is set (PRE=1) the RTI will continue to run with a clock derived from the oscillator clock.

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10.1.3 S12CPMU Block Diagram

Figure 10-1. Block diagram of S12CPMU S12CPMU EXTAL XTAL System Reset Power-On Detect PLL Lock Interrupt MMC Illegal Address Access COP time out Loop Reference Divider COP Watchdog Voltage VDDR Internal Reset Generator Divide by Phase Post Divider 1,2,.,32 VCOCLK ECLK2X LOCKIE IRCTRIM[9:0] SYNDIV[5:0] LOCK REFDIV[3:0] 2*(SYNDIV+1) Pierce Oscillator 4MHz-16MHz OSCE ILAF PORF divide by 2 ECLK POSTDIV[4:0] Power-On Reset Controlled locked Loop with internal Filter (PLL) REFCLK FBCLK REFFRQ[1:0] VCOFRQ[1:0] Lock detect Regulator 3.13 to 5.5V Autonomous Periodic Interrupt (API) API Interrupt VDDA VSSA PLLSEL (to MSCAN) VDDX VSSX VSS Low Voltage Detect VDDX LVRF PLLCLKReference divide by 8 BDM Clock Clock (IRC1M) Clock Monitor monitor fail Real Time Interrupt (RTI) RTI Interrupt PSTP CPMURTI Oscillator status Interrupt (XOSCLCP) CAN_OSCCLK Low Voltage Interrupt ACLK APICLK RTICLK IRCCLK OSCCLK RTIOSCSEL CPMUCOP COPCLKIRCCLK OSCCLK COPOSCSEL0 to ResetGenerator COP time out PCE PRE UPOSC=0 sets PLLSEL bit API_EXTCLKRC Osc. VDD, VDDF (core supplies) UPOSC RESET OSCIE APIE RTIE LVDS LVIELow Voltage Detect VDDA UPOSC UPOSC=0 clears &OSCCLK divide by 4 Bus Clock IRCCLK (to LCD) ACLK COPOSCSEL1 (Bus Clock) (Core Clock) OSCCLK_LCP External

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10.2 Signal Description

This section lists and describes the signals that connect off chip.

10.2.1 RESET

Pin RESET is an active-low bidirectional pin. As an input it initializes the MCU asynchronously to a known start-up state. As an open-drain output it indicates that an MCU-internal reset has been triggered.

10.2.2 EXTAL and XTAL

These pins provide the interface for a crystal to control the internal clock generator circuitry. EXTAL is the input to the crystal oscillator ampliﬁer. XTAL is the output of the crystal oscillator ampliﬁer. If XOSCLCP is enabled, the MCU internal OSCCLK_LCP is derived from the EXTAL input frequency. If OSCE=0, the EXTAL pin is pulled down by an internal resistor of approximately 200 kΩ and the XTAL pin is pulled down by an internal resistor of approximately 700 kΩ. EXTAL XTAL Gain Control VDD = 1.8 V Rf OSCCLK_LCP Peak Detector VSS VSS VSS C1 C2 Quartz Crystals Ceramic Resonators or Clock Monitor monitor fail

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Freescale recommends an evaluation of the application board and chosen resonator or crystal by the resonator or crystal supplier. The loop controlled circuit (XOSCLCP) is not suited for overtone resonators and crystals.

10.2.3 VDDR — Regulator Power Input Pin

Pin VDDR is the power input of IVREG. All currents sourced into the regulator loads ﬂow through this pin. An off-chip decoupling capacitor (100 nF...220 nF, X7R ceramic) between VDDR and VSS can smooth ripple on VDDR.

10.2.4 VSS — Ground Pin

VSS must be grounded.

10.2.5 VDDA, VSSA — Regulator Reference Supply Pins

Pins VDDA and VSSA are used to supply the analog parts of the regulator. Internal precision reference circuits are supplied from these signals. An off-chip decoupling capacitor (100 nF...220 nF, X7R ceramic) between VDDA and VSSA can improve the quality of this supply.

10.2.6 VDDX, VSSX— Pad Supply Pins

This supply domain is monitored by the Low V oltage Reset circuit. An off-chip decoupling capacitor (100 nF...220 nF, X7R ceramic) between VDDX and VSSX can improve the quality of this supply. NOTE Depending on the device package following device supply pins are maybe combined into one pin: VDDR, VDDX and VDDA. Depending on the device package following device supply pins are maybe combined into one pin: VSS, VSSX and VSSA. Please refer to the device Reference Manual for information if device supply pins are combined into one supply pin for certain packages and which supply pins are combined together. An off-chip decoupling capacitor (100 nF...220 nF, X7R ceramic) between the combined supply pin pair can improve the quality of this supply.

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10.2.7 VDD — Internal Regulator Output Supply (Core Logic)

Node VDD is a device internal supply output of the voltage regulator that provides the power supply for the core logic. This supply domain is monitored by the Low V oltage Reset circuit.

10.2.8 VDDF — Internal Regulator Output Supply (NVM Logic)

Node VDDF is a device internal supply output of the voltage regulator that provides the power supply for the NVM logic. This supply domain is monitored by the Low V oltage Reset circuit

10.2.9 API_EXTCLK — API external clock output pin

This pin provides the signal selected via APIES and is enabled with APIEA bit. See device speciﬁcation to which pin it connects.

10.3 Memory Map and Registers

This section provides a detailed description of all registers accessible in the S12CPMU.

10.3.1 Module Memory Map

The S12CPMU registers are shown in Figure 10-3. Addres s Name Bit 7 6 5 4 3 2 1 Bit 0 0x0034 CPMU SYNR R VCOFRQ[1:0] SYNDIV[5:0] W 0x0035 CPMU REFDIV R REFFRQ[1:0] REFDIV[3:0] W 0x0036 CPMU POSTDIV R0 0 0 POSTDIV[4:0] W 0x0037 CPMUFLG R RTIF PORF LVRF LOCKIF LOCK ILAF OSCIF UPOSC W 0x0038 CPMUINT R RTIE LOCKIE OSCIE W 0x0039 CPMUCLKS R PLLSEL PSTP

0 COP

W = Unimplemented or Reserved Figure 10-3. CPMU Register Summary

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R RTDEC RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0 W 0x003C CPMUCOP R WCOP RSBCK 00 0 CR2 CR1 CR0 W WRTMASK 0x003D RESERVEDCP MUTEST0 R 0 0 0 000 0 0 W 0x003E RESERVEDCP MUTEST1 R 0 0 0 000 0 0 W 0x003F CPMU ARMCOP R 0 0 0 000 0 0 W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x02F0 RESERVED R 0 0 0 000 0 0 W 0x02F1 CPMU LVCTL R 0 0 0 0 0 LVDS LVIE LVIF W 0x02F2 CPMU APICTL R APICLK APIES APIEA APIFE APIE APIF W 0x02F3 CPMUACLKTR R ACLKTR5 ACLKTR4 ACLKTR3 ACLKTR2 ACLKTR1 ACLKTR0 W 0x02F4 CPMUAPIRH R APIR15 APIR14 APIR13 APIR12 APIR11 APIR10 APIR9 APIR8 W 0x02F5 CPMUAPIRL R APIR7 APIR6 APIR5 APIR4 APIR3 APIR2 APIR1 APIR0 W 0x02F6 RESERVEDCP MUTEST3 R 0 0 0 000 0 0 W 0x02F7 RESERVED R 0 0 0 000 0 0 W 0x02F8 CPMU IRCTRIMH R TCTRIM[4:0] IRCTRIM[9:8] W 0x02F9 CPMU IRCTRIML R IRCTRIM[7:0] W 0x02FA CPMUOSC R OSCE Reserved OSCPINS_ EN Reserved W 0x02FB CPMUPROT R 0 0 0 000 0 PROT W 0x02FC RESERVEDCP MUTEST2 R 0 0 0 000 0 0 W Addres s Name Bit 7 6 5 4 3 2 1 Bit 0 = Unimplemented or Reserved Figure 10-3. CPMU Register Summary

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10.3.2 Register Descriptions

This section describes all the S12CPMU registers and their individual bits. Address order is as listed in Figure 10-3.

10.3.2.1 S12CPMU Synthesizer Register (CPMUSYNR)

The CPMUSYNR register controls the multiplication factor of the PLL and selects the VCO frequency range. Read: Anytime Write: Anytime if PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register). Else write has no effect. NOTE Writing to this register clears the LOCK and UPOSC status bits. NOTE fVCO must be within the speciﬁed VCO frequency lock range. Bus frequency fbus must not exceed the speciﬁed maximum. The VCOFRQ[1:0] bits are used to conﬁgure the VCO gain for optimal stability and lock time. For correct PLL operation the VCOFRQ[1:0] bits have to be selected according to the actual target VCOCLK frequency as shown inTable 10-1. Setting the VCOFRQ[1:0] bits incorrectly can result in a non functional PLL (no locking and/or insufﬁcient stability). 0x0034 76543210 R VCOFRQ[1:0] SYNDIV[5:0] W Reset 01011000 Figure 10-4. S12CPMU Synthesizer Register (CPMUSYNR) Table 10-1. VCO Clock Frequency Selection VCOCLK Frequency Ranges VCOFRQ[1:0] 32MHz <= fVCO<= 48MHz 00 48MHz < fVCO<= 50MHz 01 Reserved 10 fVCO 2f REF× SYNDIV 1+()×=If PLL has locked (LOCK=1)

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10.3.2.2 S12CPMU Reference Divider Register (CPMUREFDIV)

The CPMUREFDIV register provides a ﬁner granularity for the PLL multiplier steps when using the external oscillator as reference. Read: Anytime Write: Anytime if PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register). Else write has no effect. NOTE Write to this register clears the LOCK and UPOSC status bits. The REFFRQ[1:0] bits are used to conﬁgure the internal PLL ﬁlter for optimal stability and lock time. For correct PLL operation the REFFRQ[1:0] bits have to be selected according to the actual REFCLK frequency as shown in Table 10-2. If IRC1M is selected as REFCLK (OSCE=0) the PLL ﬁlter is ﬁxed conﬁgured for the 1MHz <= f REF <= 2MHz range. The bits can still be written but will have no effect on the PLL ﬁlter conﬁguration. For OSCE=1, setting the REFFRQ[1:0] bits incorrectly can result in a non functional PLL (no locking and/or insufﬁcient stability). Reserved 11 0x0035 76543210 R REFFRQ[1:0] REFDIV[3:0] W Reset 00001111 Figure 10-5. S12CPMU Reference Divider Register (CPMUREFDIV) Table 10-1. VCO Clock Frequency Selection VCOCLK Frequency Ranges VCOFRQ[1:0] fREF fOSC If XOSCLCP is disabled (OSCE=0) fREF fIRC1M=

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10.3.2.3 S12CPMU Post Divider Register (CPMUPOSTDIV)

The POSTDIV register controls the frequency ratio between the VCOCLK and the PLLCLK. Read: Anytime Write: Anytime if PLLSEL=1. Else write has no effect.

10.3.2.4 S12CPMU Flags Register (CPMUFLG)

This register provides S12CPMU status bits and ﬂags. Table 10-2. Reference Clock Frequency Selection if OSC_LCP is enabled REFCLK Frequency Ranges (OSCE=1) REFFRQ[1:0] 1MHz <= fREF <= 2MHz 00 2MHz < fREF <= 6MHz 01 6MHz < fREF <= 12MHz 10 fREF >12MHz 11 0x0036 76543210 R 000 POSTDIV[4:0] W Reset 00000011 = Unimplemented or Reserved Figure 10-6. S12CPMU Post Divider Register (CPMUPOSTDIV) fPLL fVCO If PLL is not locked (LOCK=0) fPLL fVCO fbus fPLL

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Read: Anytime Write: Refer to each bit for individual write conditions 0x0037 76543210 R RTIF PORF LVRF LOCKIF LOCK ILAF OSCIF UPOSC W Reset 0 Note 1 Note 2 0 0 Note 3 0 0 1. PORF is set to 1 when a power on reset occurs. Unaffected by System Reset. 2. LVRF is set to 1 when a low voltage reset occurs. Unaffected by System Reset. Set by power on reset. 3. ILAF is set to 1 when an illegal address reset occurs. Unaffected by System Reset. Cleared by power on reset. = Unimplemented or Reserved Figure 10-7. S12CPMU Flags Register (CPMUFLG) Table 10-3. CPMUFLG Field Descriptions Field Description RTIF Real Time Interrupt Flag— RTIF is set to 1 at the end of the RTI period. This ﬂag can only be cleared by writing a 1. Writing a 0 has no effect. If enabled (RTIE=1), RTIF causes an interrupt request. 0 RTI time-out has not yet occurred. 1 RTI time-out has occurred. PORF Power on Reset Flag— PORF is set to 1 when a power on reset occurs. This ﬂag can only be cleared by writing a 1. Writing a 0 has no effect. 0 Power on reset has not occurred. 1 Power on reset has occurred. LVRF Low Voltage Reset Flag — LVRF is set to 1 when a low voltage reset occurs. This ﬂag can only be cleared by writing a 1. Writing a 0 has no effect. 0 Low voltage reset has not occurred. 1 Low voltage reset has occurred. LOCKIF PLL Lock Interrupt Flag— LOCKIF is set to 1 when LOCK status bit changes. This ﬂag can only be cleared by writing a 1. Writing a 0 has no effect.If enabled (LOCKIE=1), LOCKIF causes an interrupt request. 0 No change in LOCK bit. 1 LOCK bit has changed. LOCK Lock Status Bit — LOCK reﬂects the current state of PLL lock condition. Writes have no effect. While PLL is unlocked (LOCK=0) fPLL is fVCO / 4 to protect the system from high core clock frequencies during the PLL stabilization time tlock. 0 VCOCLK is not within the desired tolerance of the target frequency. f PLL = fVCO/4. 1 VCOCLK is within the desired tolerance of the target frequency. fPLL = fVCO/(POSTDIV+1). ILAF Illegal Address Reset Flag — ILAF is set to 1 when an illegal address reset occurs. Refer to MMC chapter for details. This ﬂag can only be cleared by writing a 1. Writing a 0 has no effect. 0 Illegal address reset has not occurred. 1 Illegal address reset has occurred.

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10.3.2.5 S12CPMU Interrupt Enable Register (CPMUINT)

This register enables S12CPMU interrupt requests. Read: Anytime Write: Anytime

10.3.2.6 S12CPMU Clock Select Register (CPMUCLKS)

This register controls S12CPMU clock selection. OSCIF Oscillator Interrupt Flag — OSCIF is set to 1 when UPOSC status bit changes. This ﬂag can only be cleared by writing a 1. Writing a 0 has no effect.If enabled (OSCIE=1), OSCIF causes an interrupt request. 0 No change in UPOSC bit. 1 UPOSC bit has changed. UPOSC Oscillator Status Bit — UPOSC reﬂects the status of the oscillator. Writes have no effect. While UPOSC=0 the OSCCLK going to the MSCAN module is off. Entering Full Stop Mode UPOSC is cleared. 0 The oscillator is off or oscillation is not qualiﬁed by the PLL. 1 The oscillator is qualiﬁed by the PLL. 0x0038 76543210 R RTIE LOCKIE OSCIE W Reset 00000000 = Unimplemented or Reserved Figure 10-8. S12CPMU Interrupt Enable Register (CPMUINT) Table 10-4. CRGINT Field Descriptions Field Description RTIE Real Time Interrupt Enable Bit 0 Interrupt requests from RTI are disabled. 1 Interrupt will be requested whenever RTIF is set. LOCKIE PLL Lock Interrupt Enable Bit 0 PLL LOCK interrupt requests are disabled. 1 Interrupt will be requested whenever LOCKIF is set. OSCIE Oscillator Corrupt Interrupt Enable Bit 0 Oscillator Corrupt interrupt requests are disabled. 1 Interrupt will be requested whenever OSCIF is set. Table 10-3. CPMUFLG Field Descriptions (continued) Field Description

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Read: Anytime Write: 1. Only possible if PROT=0 (CPMUPROT register) in all MCU Modes (Normal and Special Mode). 2. All bits in Special Mode (if PROT=0). 3. PLLSEL, PSTP, PRE, PCE, RTIOSCSEL: In Normal Mode (if PROT=0). 4. COPOSCSEL0: In Normal Mode (if PROT=0) until CPMUCOP write once has taken place. If COPOSCSEL0 was cleared by UPOSC=0 (entering Full Stop Mode with COPOSCSEL0=1 or insufﬁcient OSCCLK quality), then COPOSCSEL0 can be set once again. 5. COPOSCSEL1: In Normal Mode (if PROT=0) until CPMUCOP write once is taken. COPOSCSEL1 will not be cleared by UPOSC=0 (entering Full Stop Mode with COPOSCSEL1=1 or insufﬁcient OSCCLK quality if OSCCLK is used as clock source for other clock domains: for instance core clock etc.). NOTE After writing CPMUCLKS register, it is strongly recommended to read back CPMUCLKS register to make sure that write of PLLSEL, RTIOSCSEL, COPOSCSEL0 and COPOSCSEL1 was successful. 0x0039 76543210 R PLLSEL PSTP = Unimplemented or Reserved Figure 10-9. S12CPMU Clock Select Register (CPMUCLKS)

S12 Clock, Reset and Power Management Unit (S12CPMU) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 339 Table 10-5. CPMUCLKS Descriptions Field Description PLLSEL PLL Select Bit This bit selects the PLLCLK as source of the System Clocks (Core Clock and Bus Clock). PLLSEL can only be set to 0, if UPOSC=1. UPOSC= 0 sets the PLLSEL bit. Entering Full Stop Mode sets the PLLSEL bit.

0 System clocks are derived from OSCCLK if oscillator is up (UPOSC=1, f

bus = fosc / 2. 1 System clocks are derived from PLLCLK, f bus = fPLL / 2. PSTP Pseudo Stop Bit This bit controls the functionality of the oscillator during Stop Mode. 0 Oscillator is disabled in Stop Mode (Full Stop Mode). 1 Oscillator continues to run in Stop Mode (Pseudo Stop Mode), option to run RTI and COP. Note: Pseudo Stop Mode allows for faster STOP recovery and reduces the mechanical stress and aging of the resonator in case of frequent STOP conditions at the expense of a slightly increased power consumption. Note: When starting up the external oscillator (either by programming OSCE bit to 1 or on exit from Full Stop Mode with OSCE bit is already 1) the software must wait for a minimum time equivalent to the startup-time of the external oscillator t UPOSC before entering Pseudo Stop Mode. COP OSCSEL1 COP Clock Select 1 — COPOSCSEL0 and COPOSCSEL1 combined determine the clock source to the COP (see also Table 10-6). If COPOSCSEL1 = 1, COPOSCSEL0 has no effect regarding clock select and changing the COPOSCSEL0 bit does not re-start the COP time-out period. COPOSCSEL1 selects the clock source to the COP to be either ACLK (derived from trimmable internal RC-Oscillator) or clock selected via COPOSCSEL0 (IRCCLK or OSCCLK Changing the COPOSCSEL1 bit re-starts the COP time-out period. COPOSCSEL1 can be set independent from value of UPOSC. UPOSC= 0 does not clear the COPOSCSEL1 bit.

0 COP clock source deﬁned by COPOSCSEL0

1 COP clock source is ACLK derived from a trimmable internal RC-Oscillator

RTI Enable During Pseudo Stop Bit — PRE enables the RTI during Pseudo Stop Mode. 0 RTI stops running during Pseudo Stop Mode. 1 RTI continues running during Pseudo Stop Mode if RTIOSCSEL=1. Note: If PRE=0 or RTIOSCSEL=0 then the RTI will go static while Stop Mode is active. The RTI counter will not be reset. PCE COP Enable During Pseudo Stop Bit — PCE enables the COP during Pseudo Stop Mode.

0 COP stops running during Pseudo Stop Mode if: COPOSCSEL1=0 and COPOSCSEL0=0

1 COP continues running during Pseudo Stop Mode if: PSTP=1, COPOSCSEL1=0 and COPOSCSEL0=1

Note: If PCE=0 or COPOSCSEL0=0 while COPOSCSEL1=0 then the COP is static during Stop Mode being active. The COP counter will not be reset.

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Table 10-6. COPOSCSEL1, COPOSCSEL0 clock source select description

10.3.2.7 S12CPMU PLL Control Register (CPMUPLL)

This register controls the PLL functionality. Read: Anytime Write: Anytime if PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register). Else write has no effect. NOTE Write to this register clears the LOCK and UPOSC status bits. RTIOSCSEL RTI Clock Select— RTIOSCSEL selects the clock source to the RTI. Either IRCCLK or OSCCLK. Changing the RTIOSCSEL bit re-starts the RTI time-out period. RTIOSCSEL can only be set to 1, if UPOSC=1. UPOSC= 0 clears the RTIOSCSEL bit. 0 RTI clock source is IRCCLK. 1 RTI clock source is OSCCLK. COP OSCSEL0 COP Clock Select 0 — COPOSCSEL0 and COPOSCSEL1 combined determine the clock source to the COP (see also Table 10-6) If COPOSCSEL1 = 1, COPOSCSEL0 has no effect regarding clock select and changing the COPOSCSEL0 bit does not re-start the COP time-out period. When COPOSCSEL1=0,COPOSCSEL0 selects the clock source to the COP to be either IRCCLK or OSCCLK. Changing the COPOSCSEL0 bit re-starts the COP time-out period. COPOSCSEL0 can only be set to 1, if UPOSC=1. UPOSC= 0 clears the COPOSCSEL0 bit. 0 COP clock source is IRCCLK.

1 COP clock source is OSCCLK

COPOSCSEL1 COPOSCSEL0 COP clock source 0 0 IRCCLK 0 1 OSCCLK 1 x ACLK 0x003A 76543210 R0 0 FM1 FM0 0000 W Reset 00000000 Figure 10-10. S12CPMU PLL Control Register (CPMUPLL) Table 10-5. CPMUCLKS Descriptions (continued) Field Description

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10.3.2.8 S12CPMU RTI Control Register (CPMURTI)

This register selects the time-out period for the Real Time Interrupt. The clock source for the RTI is either IRCCLK or OSCCLK depending on the setting of the RTIOSCSEL bit. In Stop Mode with PSTP=1 (Pseudo Stop Mode) and RTIOSCSEL=1 the RTI continues to run, else the RTI counter halts in Stop Mode. Read: Anytime Write: Anytime Table 10-7. CPMUPLL Field Descriptions Field Description 5, 4 FM1, FM0 PLL Frequency Modulation Enable Bits— FM1 and FM0 enable frequency modulation on the VCOCLK. This is to reduce noise emission. The modulation frequency is fref divided by 16. See Table 10-8 for coding. Table 10-8. FM Amplitude selection FM1 FM0 FM Amplitude / fVCO Variation 0 0 FM off 01 ±1% 10 ±2% 11 ±4% 0x003B 76543210 R RTDEC RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTR0 W Reset 00000000 Figure 10-11. S12CPMU RTI Control Register (CPMURTI)

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A write to this register starts the RTI time-out period. A change of the RTIOSCSEL bit (writing a different value or loosing UPOSC status) re-starts the RTI time-out period. Table 10-9. CPMURTI Field Descriptions Field Description RTDEC Decimal or Binary Divider Select Bit — RTDEC selects decimal or binary based prescaler values. 0 Binary based divider value. See Table 10-10 1 Decimal based divider value. See Table 10-11 6–4 RTR[6:4] Real Time Interrupt Prescale Rate Select Bits — These bits select the prescale rate for the RTI. See Table 10-10 and Table 10-11. 3–0 RTR[3:0] Real Time Interrupt Modulus Counter Select Bits — These bits select the modulus counter target value to provide additional granularity.Table 10-10 and Table 10-11 show all possible divide values selectable by the CPMURTI register. Table 10-10. RTI Frequency Divide Rates for RTDEC = 0 RTR[3:0] RTR[6:4] = 000 (OFF) 001 (210) 010 (211) 011 (212) 100 (213) 101 (214) 110 (215) 111 (216) 0000 (÷1) OFF1 210 211 212 213 214 215 216 0001 (÷2) OFF 2x2 10 2x211 2x212 2x213 2x214 2x215 2x216 0010 (÷3) OFF 3x2 10 3x211 3x212 3x213 3x214 3x215 3x216 0011 (÷4) OFF 4x2 10 4x211 4x212 4x213 4x214 4x215 4x216 0100 (÷5) OFF 5x2 10 5x211 5x212 5x213 5x214 5x215 5x216 0101 (÷6) OFF 6x2 10 6x211 6x212 6x213 6x214 6x215 6x216 0110 (÷7) OFF 7x2 10 7x211 7x212 7x213 7x214 7x215 7x216 0111 (÷8) OFF 8x2 10 8x211 8x212 8x213 8x214 8x215 8x216 1000 (÷9) OFF 9x2 10 9x211 9x212 9x213 9x214 9x215 9x216 1001 (÷10) OFF 10x2 10 10x211 10x212 10x213 10x214 10x215 10x216 1010 (÷11) OFF 11x2 10 11x211 11x212 11x213 11x214 11x215 11x216 1011 (÷12) OFF 12x2 10 12x211 12x212 12x213 12x214 12x215 12x216 1100 (÷13) OFF 13x2 10 13x211 13x212 13x213 13x214 13x215 13x216 1101 (÷14) OFF 14x2 10 14x211 14x212 14x213 14x214 14x215 14x216

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10.3.2.9 S12CPMU COP Control Register (CPMUCOP)

This register controls the COP (Computer Operating Properly) watchdog. 1110 (÷15) OFF 15x2 10 15x211 15x212 15x213 15x214 15x215 15x216 1111 (÷16) OFF 16x2 10 16x211 16x212 16x213 16x214 16x215 16x216 1 Denotes the default value out of reset.This value should be used to disable the RTI to ensure future backwards compatibility. Table 10-11. RTI Frequency Divide Rates for RTDEC=1 RTR[3:0] RTR[6:4] = 000 (1x103) 001 (2x103) 010 (5x103) 011 (10x103) 100 (20x103) 101 (50x103) 110 (100x103) 111 (200x103) 0000 (÷1) 1x103 2x103 5x103 10x103 20x103 50x103 100x103 200x103 0001 (÷2) 2x103 4x103 10x103 20x103 40x103 100x103 200x103 400x103 0010 (÷3) 3x103 6x103 15x103 30x103 60x103 150x103 300x103 600x103 0011 (÷4) 4x103 8x103 20x103 40x103 80x103 200x103 400x103 800x103 0100 (÷5) 5x103 10x103 25x103 50x103 100x103 250x103 500x103 1x106 0101 (÷6) 6x103 12x103 30x103 60x103 120x103 300x103 600x103 1.2x106 0110 (÷7) 7x103 14x103 35x103 70x103 140x103 350x103 700x103 1.4x106 0111 (÷8) 8x103 16x103 40x103 80x103 160x103 400x103 800x103 1.6x106 1000 (÷9) 9x103 18x103 45x103 90x103 180x103 450x103 900x103 1.8x106 1001 (÷10) 10 x103 20x103 50x103 100x103 200x103 500x103 1x106 2x106 1010 (÷11) 11 x103 22x103 55x103 110x103 220x103 550x103 1.1x106 2.2x106 1011 (÷12) 12x103 24x103 60x103 120x103 240x103 600x103 1.2x106 2.4x106 1100 (÷13) 13x103 26x103 65x103 130x103 260x103 650x103 1.3x106 2.6x106 1101 (÷14) 14x103 28x103 70x103 140x103 280x103 700x103 1.4x106 2.8x106 1110 (÷15) 15x103 30x103 75x103 150x103 300x103 750x103 1.5x106 3x106 1111 (÷16) 16x103 32x103 80x103 160x103 320x103 800x103 1.6x106 3.2x106 Table 10-10. RTI Frequency Divide Rates for RTDEC = 0 RTR[3:0] RTR[6:4] = 000 (OFF) 001 (210) 010 (211) 011 (212) 100 (213) 101 (214) 110 (215) 111 (216)

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The clock source for the COP is either ACLK, IRCCLK or OSCCLK depending on the setting of the COPOSCSEL0 and COPOSCSEL1 bit (see also Table 10-6). In Stop Mode with PSTP=1 (Pseudo Stop Mode), COPOSCSEL0=1 and COPOSCEL1=0 and PCE=1 the COP continues to run, else the COP counter halts in Stop Mode with COPOSCSEL1 =0. In Full Stop Mode and Pseudo Stop Mode with COPOSCSEL1=1 the COP continues to run. Read: Anytime Write: 1. RSBCK: Anytime in Special Mode; write to “1” but not to “0” in Normal Mode 2. WCOP, CR2, CR1, CR0: — Anytime in Special Mode, when WRTMASK is 0, otherwise it has no effect — Write once in Normal Mode, when WRTMASK is 0, otherwise it has no effect. – Writing CR[2:0] to “000” has no effect, but counts for the “write once” condition. – Writing WCOP to “0” has no effect, but counts for the “write once” condition. When a non-zero value is loaded from Flash to CR[2:0] the COP time-out period is started. A change of the COPOSCSEL0 or COPSOCSEL1 bit (writing a different value) or loosing UPOSC status while COPOSCSEL1 is clear and COPOSCSEL0 is set, re-starts the COP time-out period. In Normal Mode the COP time-out period is restarted if either of these conditions is true: 1. Writing a non-zero value to CR[2:0] (anytime in Special Mode, once in Normal Mode) with WRTMASK = 0. 2. Writing WCOP bit (anytime in Special Mode, once in Normal Mode) with WRTMASK = 0. 3. Changing RSBCK bit from “0” to “1”. In Special Mode, any write access to CPMUCOP register restarts the COP time-out period. 0x003C 76543210 R WCOP RSBCK 000 CR2 CR1 CR0 W WRTMASK Reset F 0 0 0 0 F F F After de-assert of System Reset the values are automatically loaded from the Flash memory. See Device specification for details. = Unimplemented or Reserved Figure 10-12. S12CPMU COP Control Register (CPMUCOP)

S12 Clock, Reset and Power Management Unit (S12CPMU) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 345 Table 10-12. CPMUCOP Field Descriptions Field Description WCOP Window COP Mode Bit — When set, a write to the CPMUARMCOP register must occur in the last 25% of the selected period. A write during the ﬁrst 75% of the selected period generates a COP reset. As long as all writes occur during this window, $55 can be written as often as desired. Once $AA is written after the $55, the time-out logic restarts and the user must wait until the next window before writing to CPMUARMCOP.Table 10-13shows the duration of this window for the seven available COP rates.

0 Normal COP operation

1 Window COP operation

COP and RTI Stop in Active BDM Mode Bit 0 Allows the COP and RTI to keep running in Active BDM mode. 1 Stops the COP and RTI counters whenever the part is in Active BDM mode. WRTMASK Write Mask for WCOP and CR[2:0] Bit— This write-only bit serves as a mask for the WCOP and CR[2:0] bits while writing the CPMUCOP register. It is intended for BDM writing the RSBCK without changing the content of WCOP and CR[2:0].

0 Write of WCOP and CR[2:0] has an effect with this write of CPMUCOP

1 Write of WCOP and CR[2:0] has no effect with this write of CPMUCOP . (Does not count for “write once”.) 2–0 CR[2:0] COP Watchdog Timer Rate Select — These bits select the COP time-out rate (see Table 10-13 and Table 10-14). Writing a nonzero value to CR[2:0] enables the COP counter and starts the time-out period. A COP counter time-out causes a System Reset. This can be avoided by periodically (before time-out) initializing the COP counter via the CPMUARMCOP register. While all of the following four conditions are true the CR[2:0], WCOP bits are ignored and the COP operates at highest time-out period ( 2 24 cycles) in normal COP mode (Window COP mode disabled): 1) COP is enabled (CR[2:0] is not 000) 2) BDM mode active 3) RSBCK = 0 4) Operation in Special Mode Table 10-13. COP Watchdog Rates if COPOSCSEL1=0 (default out of reset) CR2 CR1 CR0 COPCLK Cycles to Time-out (COPCLK is either IRCCLK or OSCCLK depending on the COPOSCSEL0 bit) 0 0 0 COP disabled 001 2 14 010 2 16 011 2 18 100 2 20 101 2 22 110 2 23 111 2 24

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10.3.2.10 Reserved Register CPMUTEST0

10.3.2.11 Reserved Register CPMUTEST1

This reserved register is designed for factory test purposes only, and is not intended for general user access. Writing to this register when in Special Mode can alter the S12CPMU’s functionality. Table 10-14. COP Watchdog Rates if COPOSCSEL1=1 CR2 CR1 CR0 COPCLK Cycles to Time-out (COPCLK is ACLK - internal RC-Oscillator clock) 0 0 0 COP disabled 001 2 7 010 2 9 011 2 11 100 2 13 101 2 15 110 2 16 111 2 17 0x003D 76543210 R 00000000 W Reset 00000000 = Unimplemented or Reserved Figure 10-13. Reserved Register (CPMUTEST0)

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10.3.2.12 S12CPMU COP Timer Arm/Reset Register (CPMUARMCOP)

This register is used to restart the COP time-out period. Read: Always reads $00 Write: Anytime When the COP is disabled (CR[2:0] = “000”) writing to this register has no effect. When the COP is enabled by setting CR[2:0] nonzero, the following applies: Writing any value other than $55 or $AA causes a COP reset. To restart the COP time-out period write $55 followed by a write of $AA. These writes do not need to occur back-to-back, but the sequence ($55, $AA) must be completed prior to COP end of time-out period to avoid a COP reset. Sequences of $55 writes are allowed. When the WCOP bit is set, $55 and $AA writes must be done in the last 25% of the selected time-out period; writing any value in the ﬁrst 75% of the selected period will cause a COP reset.

10.3.2.13 Low Voltage Control Register (CPMULVCTL)

The CPMULVCTL register allows the conﬁguration of the low-voltage detect features. 0x003E 76543210 R 00000000 W Reset 00000000 = Unimplemented or Reserved Figure 10-14. Reserved Register (CPMUTEST1) 0x003F 76543210 R 00000000 W ARMCOP-Bit ARMCOP-Bit ARMCOP-Bit ARMCOP-Bit ARMCOP-Bit ARMCOP-Bit ARMCOP-Bit ARMCOP-Bit Reset 00000000 Figure 10-15. S12CPMU CPMUARMCOP Register

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Read: Anytime Write: LVIE and LVIF are write anytime, LVDS is read only

10.3.2.14 Autonomous Periodical Interrupt Control Register (CPMUAPICTL)

The CPMUAPICTL register allows the conﬁguration of the autonomous periodical interrupt features. Read: Anytime 0x02F1 76543210 R 00000 L V D S LVIE LVIF W Reset 00000U0U The Reset state of LVDS and LVIF depends on the external supplied VDDA level = Unimplemented or Reserved Figure 10-16. Low Voltage Control Register (CPMULVCTL) Table 10-15. CPMULVCTL Field Descriptions Field Description LVDS Low-Voltage Detect Status Bit— This read-only status bit reﬂects the voltage level on VDDA. Writes have no effect.

0 Input voltage VDDA is above level V

LVID or RPM. 1 Input voltage VDDA is below level V LVIA and FPM. LVIE Low-Voltage Interrupt Enable Bit 0 Interrupt request is disabled. 1 Interrupt will be requested whenever LVIF is set. LVIF Low-Voltage Interrupt Flag— LVIF is set to 1 when LVDS status bit changes. This ﬂag can only be cleared by writing a 1. Writing a 0 has no effect. If enabled (LVIE = 1), LVIF causes an interrupt request. 0 No change in LVDS bit. 1 LVDS bit has changed. 0x02F2 76543210 R APICLK APIES APIEA APIFE APIE APIF W Reset 00000000 = Unimplemented or Reserved Figure 10-17. Autonomous Periodical Interrupt Control Register (CPMUAPICTL)

S12 Clock, Reset and Power Management Unit (S12CPMU) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 349 Write: Anytime Figure 10-18. Waveform selected on API_EXTCLK pin (APIEA=1, APIFE=1) Table 10-16. CPMUAPICTL Field Descriptions Field Description APICLK Autonomous Periodical Interrupt Clock Select Bit — Selects the clock source for the API. Writable only if APIFE = 0. APICLK cannot be changed if APIFE is set by the same write operation. 0 Autonomous Clock (ACLK) used as source. 1 Bus Clock used as source. APIES Autonomous Periodical Interrupt External Select Bit — Selects the waveform at the external pin API_EXTCLK as shown in Figure 10-18. See device level speciﬁcation for connectivity of API_EXTCLK pin. 0 If APIEA and APIFE are set, at the external pin API_EXTCLK periodic high pulses are visible at the end of every selected period with the size of half of the minimum period (APIR=0x0000 in Table 10-20). 1 If APIEA and APIFE are set, at the external pin API_EXTCLK a clock is visible with 2 times the selected API Period. APIEA Autonomous Periodical Interrupt External Access Enable Bit— If set, the waveform selected by bit APIES can be accessed externally. See device level speciﬁcation for connectivity. 0 Waveform selected by APIES can not be accessed externally. 1 Waveform selected by APIES can be accessed externally, if APIFE is set. APIFE Autonomous Periodical Interrupt Feature Enable Bit — Enables the API feature and starts the API timer when set. 0 Autonomous periodical interrupt is disabled. 1 Autonomous periodical interrupt is enabled and timer starts running. APIE Autonomous Periodical Interrupt Enable Bit 0 API interrupt request is disabled. 1 API interrupt will be requested whenever APIF is set. APIF Autonomous Periodical Interrupt Flag — APIF is set to 1 when the in the API conﬁgured time has elapsed. This ﬂag can only be cleared by writing a 1. Writing a 0 has no effect. If enabled (APIE = 1), APIF causes an interrupt request. 0 API time-out has not yet occurred. 1 API time-out has occurred. APIES=0 APIES=1 API period API min. period / 2

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10.3.2.15 Autonomous Clock Trimming Register (CPMUACLKTR)

The CPMUACLKTR register conﬁgures the trimming of the Autonomous Clock (ACLK - trimmable internal RC-Oscillator) which can be selected as clock source for some CPMU features. Read: Anytime Write: Anytime

10.3.2.16 Autonomous Periodical Interrupt Rate High and Low Register

(CPMUAPIRH / CPMUAPIRL) The CPMUAPIRH and CPMUAPIRL registers allow the conﬁguration of the autonomous periodical interrupt rate. 0x02F3 76543210 R ACLKTR5 ACLKTR4 ACLKTR3 ACLKTR2 ACLKTR1 ACLKTR0 W Reset F F FFFF00 After de-assert of System Reset a value is automatically loaded from the Flash memory. Figure 10-19. Autonomous Periodical Interrupt Trimming Register (CPMUACLKTR) Table 10-17. CPMUACLKTR Field Descriptions Field Description 7–2 ACLKTR[5:0] Autonomous Clock Trimming Bits — See Table 10-18 for trimming effects. The ACLKTR[5:0] value represents a signed number inﬂuencing the ACLK period time. Table 10-18. Trimming Effect of ACLKTR Bit Trimming Effect ACLKTR[5] Increases period ACLKTR[4] Decreases period less than ACLKTR[5] increased it ACLKTR[3] Decreases period less than ACLKTR[4] ACLKTR[2] Decreases period less than ACLKTR[3] ACLKTR[1] Decreases period less than ACLKTR[2] ACLKTR[0] Decreases period less than ACLKTR[1]

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10.3.2.17 Reserved Register CPMUTEST3

This reserved register is designed for factory test purposes only, and is not intended for general user access. Writing to this register when in Special Mode can alter the S12CPMU’s functionality. Read: Anytime Write: Only in Special Mode 0 0004 1.0 ms 1 0 0005 1.2 ms 1 0 FFFD 13106.8 ms 1 0 FFFE 13107.0 ms 1 0 FFFF 13107.2 ms 1 1 0000 2 * Bus Clock period 1 0001 4 * Bus Clock period 1 0002 6 * Bus Clock period 1 0003 8 * Bus Clock period 1 0004 10 * Bus Clock period 1 0005 12 * Bus Clock period

1 FFFD 131068 * Bus Clock period

1 FFFE 131070 * Bus Clock period

1 FFFF 131072 * Bus Clock period

1 When fACLK is trimmed to 10KHz. 0x02F6 76543210 R 00000000 W Reset 00000000 = Unimplemented or Reserved Figure 10-22. Reserved Register (CPMUTEST3) Table 10-20. Selectable Autonomous Periodical Interrupt Periods (continued) APICLK APIR[15:0] Selected Period

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10.3.2.18 S12CPMU IRC1M Trim Registers (CPMUIRCTRIMH / CPMUIRCTRIML)

Read: Anytime Write: Anytime if PROT=0 (CPMUPROT register). Else write has no effect NOTE Writes to these registers while PLLSEL=1 clears the LOCK and UPOSC status bits. 0x02F8 15 14 13 12 11 10 9 8 R TCTRIM[4:0] IRCTRIM[9:8] W Reset F F F F 0 0 F F After de-assert of System Reset a factory programmed trim value is automatically loaded from the Flash memory to provide trimmed Internal Reference Frequency fIRC1M_TRIM. Figure 10-23. S12CPMU IRC1M Trim High Register (CPMUIRCTRIMH) 0x02F9 76543210 R IRCTRIM[7:0] W Reset F F FFFFFF After de-assert of System Reset a factory programmed trim value is automatically loaded from the Flash memory to provide trimmed Internal Reference Frequency fIRC1M_TRIM. Figure 10-24. S12CPMU IRC1M Trim Low Register (CPMUIRCTRIML)

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Figure 10-25. IRC1M Frequency Trimming Diagram Table 10-22. CPMUIRCTRIMH/L Field Descriptions Field Description 15-11 TCTRIM[4:0] IRC1M temperature coefﬁcient Trim Bits Trim bits for the Temperature Coefﬁcient (TC) of the IRC1M frequency. Figure 10-26 shows the inﬂuence of the bits TCTRIM4:0] on the relationship between frequency and temperature. Figure 10-26 shows an approximate TC variation, relative to the nominal TC of the IRC1M (i.e. for TCTRIM[4:0]=0x00000 or 0x10000). 9-0 IRCTRIM[9:0] IRC1M Frequency Trim Bits — Trim bits for Internal Reference Clock After System Reset the factory programmed trim value is automatically loaded into these registers, resulting in a Internal Reference Frequency f IRC1M_TRIM. See device electrical characteristics for value of fIRC1M_TRIM. The frequency trimming consists of two different trimming methods: A rough trimming controlled by bits IRCTRIM[9:6] can be done with frequency leaps of about 6% in average. A ﬁne trimming controlled by the bits IRCTRIM[5:0] can be done with frequency leaps of about 0.3% (this trimming determines the precision of the frequency setting of 0.15%, i.e. 0.3% is the distance between two trimming values). Figure 10-25 shows the relationship between the trim bits and the resulting IRC1M frequency. IRCTRIM[9:0] $000 IRCTRIM[9:6] IRCTRIM[5:0] IRC1M frequency (IRCCLK) 600KHz 1.5MHz 1MHz $3FF

S12 Clock, Reset and Power Management Unit (S12CPMU) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 355 Figure 10-26. Inﬂuence of TCTRIM[4:0] on the Temperature Coefﬁcient NOTE The frequency is not necessarily linear with the temperature (in most cases it will not be). The above diagram is meant only to give the direction (positive or negative) of the variation of the TC, relative to the nominal TC. Setting TCTRIM[4:0] to 0x00000 or 0x10000 does not mean that the temperature coefﬁcient will be zero. These two combinations basically switch off the TC compensation module, which results in the nominal TC of the IRC1M. TCTRIM[4:0] IRC1M indicative relative TC variation IRC1M indicative frequency drift for relative TC variation 00000 0 (nominal TC of the IRC) 0% 00001 -0.27% -0.5% 00010 -0.54% -0.9% 00011 -0.81% -1.3% 00100 -1.08% -1.7% 00101 -1.35% -2.0% 00110 -1.63% -2.2% frequency temperature TCTRIM[4:0] = 0x11111 TCTRIM[4:0] = 0x01111 - 40C 150C TCTRIM[4:0] = 0x10000 or 0x00000 (nominal TC) 0x00001 0x00010 0x00011 0x00100 0x00101 ... 0x01111 0x11111 ... 0x10101 0x10100 0x10011 0x10010 0x10001 TC increases TC decreases

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Table 10-23. TC trimming of the IRC1M frequency at ambient temperature NOTE Since the IRC1M frequency is not a linear function of the temperature, but more like a parabola, the above relative variation is only an indication and should be considered with care. Be aware that the output frequency vary with TC trimming. A frequency trimming correction is therefore necessary. The values provided in Table 10-23 are typical values at ambient temperature which can vary from device to device.

10.3.2.19 S12CPMU Oscillator Register (CPMUOSC)

This registers conﬁgures the external oscillator (XOSCLCP). 00111 -1.9% -2.5% 01000 -2.20% -3.0% 01001 -2.47% -3.4% 01010 -2.77% -3.9% 01011 -3.04 -4.3% 01100 -3.33% -4.7% 01101 -3.6% -5.1% 01110 -3.91% -5.6% 01111 -4.18% -5.9% 10000 0 (nominal TC of the IRC) 0% 10001 +0.27% +0.5% 10010 +0.54% +0.9% 10011 +0.81% +1.3% 10100 +1.07% +1.7% 10101 +1.34% +2.0% 10110 +1.59% +2.2% 10111 +1.86% +2.5% 11000 +2.11% +3.0% 11001 +2.38% +3.4% 11010 +2.62% +3.9% 11011 +2.89% +4.3% 11100 +3.12% +4.7% 11101 +3.39% +5.1% 11110 +3.62% +5.6% 11111 +3.89% +5.9% TCTRIM[4:0] IRC1M indicative relative TC variation IRC1M indicative frequency drift for relative TC variation

S12 Clock, Reset and Power Management Unit (S12CPMU) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 357 Read: Anytime Write: Anytime if PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register). Else write has no effect. NOTE. Write to this register clears the LOCK and UPOSC status bits.

10.3.2.20 S12CPMU Protection Register (CPMUPROT)

This register protects the following clock conﬁguration registers from accidental overwrite: 0x02FA 76543210 R OSCE Reserved OSCPINS_E N Reserved] W Reset 00000000 Figure 10-27. S12CPMU Oscillator Register (CPMUOSC) Table 10-24. CPMUOSC Field Descriptions Field Description OSCE Oscillator Enable Bit — This bit enables the external oscillator (XOSCLCP). The UPOSC status bit in the CPMUFLG register indicates when the oscillation is stable and OSCCLK can be selected as Bus Clock or source of the COP or RTI. A loss of oscillation will lead to a clock monitor reset. 0 External oscillator is disabled. REFCLK for PLL is IRCCLK. 1 External oscillator is enabled.Clock monitor is enabled.External oscillator is qualiﬁed by PLLCLK REFCLK for PLL is the external oscillator clock divided by REFDIV. Note: When starting up the external oscillator (either by programming OSCE bit to 1 or on exit from Full Stop Mode with OSCE bit already 1) the software must wait for a minimum time equivalent to the startup-time of the external oscillator t UPOSC before entering Pseudo Stop Mode. Reserved Do not alter this bit from its reset value. It is for Manufacturer use only and can change the PLL behavior. OSCPINS_EN Oscillator Pins EXTAL and XTAL Enable Bit If OSCE=1 this read-only bit is set. It can only be cleared with the next reset. Enabling the external oscillator reserves the EXTAL and XTAL pins exclusively for oscillator application. 0 EXTAL and XTAL pins are not reserved for oscillator. 1 EXTAL and XTAL pins exclusively reserved for oscillator. 4-0 Reserved Do not alter these bits from their reset value. It is for Manufacturer use only and can change the PLL behavior.

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CPMUSYNR, CPMUREFDIV , CPMUCLKS, CPMUPLL, CPMUIRCTRIMH/L and CPMUOSC Read: Anytime Write: Anytime

10.3.2.21 Reserved Register CPMUTEST2

This reserved register is designed for factory test purposes only, and is not intended for general user access. Writing to this register when in Special Mode can alter the S12CPMU’s functionality. Read: Anytime Write: Only in Special Mode 0x02FB 76543210 R 0000000 PROT W Reset 00000000 Figure 10-28. S12CPMU Protection Register (CPMUPROT) Field Description PROT Clock Conﬁguration Registers Protection Bit — This bit protects the clock conﬁguration registers from accidental overwrite (see list of affected registers above): Writing 0x26 to the CPMUPROT register clears the PROT bit, other write accesses set the PROT bit. 0 Protection of clock conﬁguration registers is disabled. 1 Protection of clock conﬁguration registers is enabled. (see list of protected registers above). 0x02FC 76543210 R 00000000 W Reset 00000000 = Unimplemented or Reserved Figure 10-29. Reserved Register CPMUTEST2

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10.4 Functional Description

10.4.1 Phase Locked Loop with Internal Filter (PLL)

The PLL is used to generate a high speed PLLCLK based on a low frequency REFCLK. The REFCLK is by default the IRCCLK which is trimmed to fIRC1M_TRIM=1MHz. If using the oscillator (OSCE=1) REFCLK will be based on OSCCLK. For increased ﬂexibility, OSCCLK can be divided in a range of 1 to 16 to generate the reference frequency REFCLK using the REFDIV[3:0] bits. Based on the SYNDIV[5:0] bits the PLL generates the VCOCLK by multiplying the reference clock by a 2, 4, 6,... 126, 128. Based on the POSTDIV[4:0] bits the VCOCLK can be divided in a range of 1,2, 3, 4, 5, 6,... to 32 to generate the PLLCLK. NOTE Although it is possible to set the dividers to command a very high clock frequency, do not exceed the speciﬁed bus frequency limit for the MCU. Several examples of PLL divider settings are shown in Table 10-25. The following rules help to achieve optimum stability and shortest lock time:

Use lowest possible f VCO / fREF ratio (SYNDIV value).
Use highest possible REFCLK frequency f REF. Table 10-25. Examples of PLL Divider Settings fosc REFDIV[3: 0] fREF REFFRQ[1:0] SYNDIV[5:0] f VCO VCOFRQ[1:0] POSTDIV [4:0] fPLL fbus off $00 1MHz 00 $18 50MHz 01 $03 12.5MHz 6.25MHz fVCO 2f REF× SYNDIV 1+()×= fREF fOSC If oscillator is disabled (OSCE=0) fREF fIRC1M= fPLL fVCO If PLL is not locked (LOCK=0) fPLL fVCO fbus fPLL

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The phase detector inside the PLL compares the feedback clock (FBCLK = VCOCLK/(SYNDIV+1)) with the reference clock (REFCLK = (IRC1M or OSCCLK)/(REFDIV+1)). Correction pulses are generated based on the phase difference between the two signals. The loop ﬁlter alters the DC voltage on the internal ﬁlter capacitor, based on the width and direction of the correction pulse, which leads to a higher or lower VCO frequency. The user must select the range of the REFCLK frequency (REFFRQ[1:0] bits) and the range of the VCOCLK frequency (VCOFRQ[1:0] bits) to ensure that the correct PLL loop bandwidth is set. The lock detector compares the frequencies of the FBCLK and the REFCLK. Therefore the speed of the lock detector is directly proportional to the reference clock frequency. The circuit determines the lock condition based on this comparison. If PLL LOCK interrupt requests are enabled, the software can wait for an interrupt request and for instance check the LOCK bit. If interrupt requests are disabled, software can poll the LOCK bit continuously (during PLL start-up) or at periodic intervals. In either case, only when the LOCK bit is set, the VCOCLK will have stabilized to the programmed frequency.

The LOCK bit is a read-only indicator of the locked state of the PLL.
The LOCK bit is set when the VCO frequency is within the tolerance ∆ Lock and is cleared when the VCO frequency is out of the tolerance ∆unl.
Interrupt requests can occur if enabled (LOCKIE = 1) when the lock condition changes, toggling the LOCK bit.

10.4.2 Startup from Reset

An example of startup of clock system from Reset is given in Figure 10-30. off $00 1MHz 00 $18 50MHz 01 $00 50MHz 25MHz 4MHz $00 4MHz 01 $05 48MHz 00 $00 48MHz 24MHz Table 10-25. Examples of PLL Divider Settings fosc REFDIV[3: 0] fREF REFFRQ[1:0] SYNDIV[5:0] f VCO VCOFRQ[1:0] POSTDIV [4:0] fPLL fbus

S12 Clock, Reset and Power Management Unit (S12CPMU) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 361 Figure 10-30. Startup of clock system after Reset

10.4.3 Stop Mode using PLLCLK as Bus Clock

An example of what happens going into Stop Mode and exiting Stop Mode after an interrupt is shown in Figure 10-31. Disable PLL Lock interrupt (LOCKIE=0) before going into Stop Mode. Figure 10-31. Stop Mode using PLLCLK as Bus Clock

10.4.4 Full Stop Mode using Oscillator Clock as Bus Clock

An example of what happens going into Full Stop Mode and exiting Full Stop Mode after an interrupt is shown in Figure 10-32. System PLLCLK Reset fVCORST CPU reset state vector fetch, program execution LOCK POSTDIV $03 (default target fPLL=fVCO/4 = 12.5MHz) fPLL increasing fPLL=16MHz tlock SYNDIV $18 (default target fVCO=50MHz) $01 fPLL=32 MHz example change of POSTDIV 768 cycles ) ( PLLCLK CPU LOCK tlock STOP instructionexecution interrupt continue execution wakeup tSTP_REC

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Disable PLL Lock interrupt (LOCKIE=0) and oscillator status change interrupt (OSCIE=0) before going into Full Stop Mode. Figure 10-32. Full Stop Mode using Oscillator Clock as Bus Clock

10.4.5 External Oscillator

10.4.5.1 Enabling the External Oscillator

An example of how to use the oscillator as Bus Clock is shown in Figure 10-33. CPU UPOSC tlock STOP instructionexecution interrupt continue execution wakeup tSTP_RECCore Clock select OSCCLK as Core/Bus Clock by writing PLLSEL to “0” PLLSEL automatically set when going into Full Stop Mode OSCCLK PLLCLK

S12 Clock, Reset and Power Management Unit (S12CPMU) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 363 Figure 10-33. Enabling the External Oscillator

10.4.6 System Clock Conﬁgurations

10.4.6.1 PLL Engaged Internal Mode (PEI)

This mode is the default mode after System Reset or Power-On Reset. The Bus clock is based on the PLLCLK, the reference clock for the PLL is internally generated (IRC1M). The PLL is conﬁgured to 50 MHz VCOCLK with POSTDIV set to 0x03. If locked (LOCK=1) this results in a PLLCLK of 12.5 MHz and a Bus clock of 6.25 MHz. The PLL can be re-conﬁgured to other bus frequencies. The clock sources for COP and RTI can be based on the internal reference clock generator (IRC1M) or the RC-Oscillator (ACLK).

10.4.6.2 PLL Engaged External Mode (PEE)

In this mode, the Bus clock is based on the PLLCLK as well (like PEI). The reference clock for the PLL is based on the external oscillator. The clock sources for COP and RTI can be based on the internal reference clock generator or on the external oscillator clock or the RC-Oscillator (ACLK). This mode can be entered from default mode PEI by performing the following steps: 1. Conﬁgure the PLL for desired bus frequency. 2. Enable the external oscillator (OSCE bit). 3. Wait for oscillator to start-up and the PLL being locked (LOCK = 1) and (UPOSC =1). PLLSEL OSCE EXTAL OSCCLK Core enable external Oscillator by writing OSCE bit to one. crystal/resonator starts oscillating UPOSC UPOSC ﬂag is set upon successful start of oscillation select OSCCLK as Core/Bus Clock by writing PLLSEL to zero Clock based on PLLCLK based on OSCCLK

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Clear all ﬂags in the CPMUFLG register to be able to detect any future status bit change. 5. Optionally status interrupts can be enabled (CPMUINT register). Loosing PLL lock status (LOCK=0) means loosing the oscillator status information as well (UPOSC=0). The impact of loosing the oscillator status (UPOSC=0) in PEE mode is as follows:

The PLLCLK is derived from the VCO clock (with its actual frequency) divided by four until the PLL locks again.
The OSCCLK provided to the MSCAN module is off. Application software needs to be prepared to deal with the impact of loosing the oscillator status at any time.

10.4.6.3 PLL Bypassed External Mode (PBE)

In this mode, the Bus Clock is based on the external oscillator clock. The reference clock for the PLL is based on the external oscillator. The clock sources for COP and RTI can be based on the internal reference clock generator or on the external oscillator clock or the RC-Oscillator (ACLK). This mode can be entered from default mode PEI by performing the following steps: 1. Make sure the PLL conﬁguration is valid. 2. Enable the external oscillator (OSCE bit) 3. Wait for the oscillator to start-up and the PLL being locked (LOCK = 1) and (UPOSC =1). 4. Clear all ﬂags in the CPMUFLG register to be able to detect any status bit change. 5. Optionally status interrupts can be enabled (CPMUINT register). 6. Select the Oscillator Clock (OSCCLK) as Bus Clock (PLLSEL=0) Loosing PLL lock status (LOCK=0) means loosing the oscillator status information as well (UPOSC=0). The impact of loosing the oscillator status (UPOSC=0) in PBE mode is as follows:

PLLSEL is set automatically and the Bus Clock is switched back to the PLLCLK.
The PLLCLK is derived from the VCO clock (with its actual frequency) divided by four until the PLL locks again.
The OSCCLK provided to the MSCAN module is off. Application software needs to be prepared to deal with the impact of loosing the oscillator status at any time.

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10.5 Resets

10.5.1 General

All reset sources are listed in Table 10-26. Refer to MCU speciﬁcation for related vector addresses and priorities.

10.5.2 Description of Reset Operation

Upon detection of any reset ofTable 10-26, an internal circuit drives theRESET pin low for 512 PLLCLK cycles. After 512 PLLCLK cycles theRESET pin is released. The reset generator of the S12CPMU waits for additional 256 PLLCLK cycles and then samples the RESET pin to determine the originating source. Table 10-27 shows which vector will be fetched. NOTE While System Reset is asserted the PLLCLK runs with the frequency fVCORST. Table 10-26. Reset Summary Reset Source Local Enable Power-On Reset (POR) None Low Voltage Reset (LVR) None External pin RESET None Illegal Address Reset None Clock Monitor Reset OSCE Bit in CPMUOSC register COP Reset CR[2:0] in CPMUCOP register Table 10-27. Reset Vector Selection Sampled RESET Pin (256 cycles after release) Oscillator monitor fail pending COP time out pending Vector Fetch 1 0 0 POR LVR Illegal Address Reset External pin RESET 1 1 X Clock Monitor Reset 1 0 1 COP Reset

0 X X POR

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The internal reset of the MCU remains asserted while the reset generator completes the 768 PLLCLK cycles long reset sequence. In case the RESET pin is externally driven low for more than these 768 PLLCLK cycles (External Reset), the internal reset remains asserted longer. Figure 10-34. RESET Timing

10.5.2.1 Clock Monitor Reset

If the external oscillator is enabled (OSCE=1) in case of loss of oscillation or the oscillator frequency is below the failure assert frequency f CMFA (see device electrical characteristics for values), the S12CPMU generates a Clock Monitor Reset.In Full Stop Mode the external oscillator and the clock monitor are disabled.

10.5.2.2 Computer Operating Properly Watchdog (COP) Reset

The COP (free running watchdog timer) enables the user to check that a program is running and sequencing properly. When the COP is being used, software is responsible for keeping the COP from timing out. If the COP times out it is an indication that the software is no longer being executed in the intended sequence; thus COP reset is generated. The clock source for the COP is either ACLK, IRCCLK or OSCCLK depending on the setting of the COPOSCSEL0 and COPOSCSEL1 bit. In Stop Mode with PSTP=1 (Pseudo Stop Mode), COPOSCSEL0=1 and COPOSCEL1=0 and PCE=1 the COP continues to run, else the COP counter halts in Stop Mode with COPOSCSEL1 =0. In Pseudo Stop Mode and Full Stop Mode with COPOSCSEL1=1 the COP continues to run. Table 10-28.gives an overview of the COP condition (run, static) in Stop Mode depending on legal conﬁguration and status bit settings: PLLCLK 512 cycles 256 cycles S12_CPMU drives possibly RESET driven low RESET S12_CPMU releases fVCORST RESET pin low RESET pin fVCORST

S12 Clock, Reset and Power Management Unit (S12CPMU) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 367 Table 10-28. COP condition (run, static) in Stop Mode Three control bits in the CPMUCOP register allow selection of seven COP time-out periods. When COP is enabled, the program must write $55 and $AA (in this order) to the CPMUARMCOP register during the selected time-out period. Once this is done, the COP time-out period is restarted. If the program fails to do this and the COP times out, a COP reset is generated. Also, if any value other than $55 or $AA is written, a COP reset is generated. Windowed COP operation is enabled by setting WCOP in the CPMUCOP register. In this mode, writes to the CPMUARMCOP register to clear the COP timer must occur in the last 25% of the selected time-out period. A premature write will immediately reset the part.

10.5.3 Power-On Reset (POR)

The on-chip POR circuitry detects when the internal supply VDD drops below an appropriate voltage level. The POR is deasserted, if the internal supply VDD exceeds an appropriate voltage level (voltage levels are not speciﬁed in this document because this internal supply is not visible on device pins).

10.5.4 Low-Voltage Reset (LVR)

The on-chip LVR circuitry detects when one of the supply voltages VDD, VDDF or VDDX drops below an appropriate voltage level. If LVR is deasserted the MCU is fully operational at the speciﬁed maximum speed. The LVR assert and deassert levels for the supply voltage VDDX are V LVRXA and VLVRXD and are speciﬁed in the device Reference Manual. COPOSCSEL1 PSTP PCE COPOSCSEL0 OSCE UPOSC COP counter behavior in Stop Mode (clock source) 1 x x x x x Run (ACLK) 0 1 1 1 1 1 Run (OSCCLK) 0 1 1 0 0 x Static (IRCCLK) 0 1 1 0 1 x Static (IRCCLK) 0 1 0 0 x x Static (IRCCLK) 0 1 0 1 1 1 Static (OSCCLK) 0 0 1 1 1 1 Static (OSCCLK) 0 0 1 0 1 x Static (IRCCLK) 0 0 1 0 0 0 Static (IRCCLK) 0 0 0 1 1 1 Satic (OSCCLK) 0 0 0 0 1 1 Static (IRCCLK) 0 0 0 0 1 0 Static (IRCCLK) 0 0 0 0 0 0 Static (IRCCLK)

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10.6 Interrupts

The interrupt/reset vectors requested by the S12CPMU are listed in Table 10-29. Refer to MCU speciﬁcation for related vector addresses and priorities.

10.6.1 Description of Interrupt Operation

10.6.1.1 Real Time Interrupt (RTI)

The clock source for the RTI is either IRCCLK or OSCCLK depending on the setting of the RTIOSCSEL bit. In Stop Mode with PSTP=1 (Pseudo Stop Mode), RTIOSCSEL=1 and PRE=1 the RTI continues to run, else the RTI counter halts in Stop Mode. The RTI can be used to generate hardware interrupts at a ﬁxed periodic rate. If enabled (by setting RTIE=1), this interrupt will occur at the rate selected by the CPMURTI register. At the end of the RTI time-out period the RTIF ﬂag is set to one and a new RTI time-out period starts immediately. A write to the CPMURTI register restarts the RTI time-out period.

10.6.1.2 PLL Lock Interrupt

The S12CPMU generates a PLL Lock interrupt when the lock condition (LOCK status bit) of the PLL changes, either from a locked state to an unlocked state or vice versa. Lock interrupts are locally disabled by setting the LOCKIE bit to zero. The PLL Lock interrupt ﬂag (LOCKIF) is set to 1 when the lock condition has changed, and is cleared to 0 by writing a 1 to the LOCKIF bit.

10.6.1.3 Oscillator Status Interrupt

When the OSCE bit is 0, then UPOSC stays 0. When OSCE = 1 the UPOSC bit is set after the LOCK bit is set. Upon detection of a status change (UPOSC) the OSCIF ﬂag is set. Going into Full Stop Mode or disabling the oscillator can also cause a status change of UPOSC. Table 10-29. S12CPMU Interrupt Vectors Interrupt Source CCR Mask Local Enable RTI time-out interrupt I bit CPMUINT (RTIE) PLL lock interrupt I bit CPMUINT (LOCKIE) Oscillator status interrupt I bit CPMUINT (OSCIE) Low voltage interrupt I bit CPMULVCTL (LVIE) Autonomous Periodical Interrupt I bit CPMUAPICTL (APIE)

S12 Clock, Reset and Power Management Unit (S12CPMU) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 369 Any change in PLL conﬁguration or any other event which causes the PLL lock status to be cleared leads to a loss of the oscillator status information as well (UPOSC=0). Oscillator status change interrupts are locally enabled with the OSCIE bit. NOTE Losing the oscillator status (UPOSC=0) affects the clock conﬁguration of the system1. This needs to be dealt with in application software.

10.6.1.4 Low-Voltage Interrupt (LVI)

In FPM the input voltage VDDA is monitored. Whenever VDDA drops below level VLVIA, the status bit LVDS is set to 1. When VDDA rises above level VLVID the status bit LVDS is cleared to 0. An interrupt, indicated by ﬂag LVIF = 1, is triggered by any change of the status bit LVDS if interrupt enable bit LVIE = 1.

10.6.1.5 Autonomous Periodical Interrupt (API)

The API sub-block can generate periodical interrupts independent of the clock source of the MCU. To enable the timer, the bit APIFE needs to be set. The API timer is either clocked by the Autonomous Clock (ACLK - trimmable internal RC oscillator) or the Bus Clock. Timer operation will freeze when MCU clock source is selected and Bus Clock is turned off. The clock source can be selected with bit APICLK. APICLK can only be written when APIFE is not set. The APIR[15:0] bits determine the interrupt period. APIR[15:0] can only be written when APIFE is cleared. As soon as APIFE is set, the timer starts running for the period selected by APIR[15:0] bits. When the conﬁgured time has elapsed, the ﬂag APIF is set. An interrupt, indicated by ﬂag APIF = 1, is triggered if interrupt enable bit APIE = 1. The timer is re-started automatically again after it has set APIF. The procedure to change APICLK or APIR[15:0] is ﬁrst to clear APIFE, then write to APICLK or APIR[15:0], and afterwards set APIFE. The API Trimming bits APITR[5:0] must be set so the minimum period equals 0.2 ms if stable frequency is desired. See Table 10-18 for the trimming effect of APITR. NOTE The ﬁrst period after enabling the counter by APIFE might be reduced by API start up delay t sdel. It is possible to generate with the API a waveform at the external pin API_EXTCLK by setting APIFE and enabling the external access with setting APIEA. 1. For details please refer to “<st-blue>10.4.6 System Clock Conﬁgurations”

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10.7 Initialization/Application Information

10.7.1 General Initialization information

Usually applications run in MCU Normal Mode. It is recommended to write the CPMUCOP register in any case from the application program initialization routine after reset no matter if the COP is used in the application or not, even if a conﬁguration is loaded via the ﬂash memory after reset . By doing a “controlled” write access in MCU Normal Mode (with the right value for the application) the write once for the COP conﬁguration bits (WCOP,CR[2:0]) takes place which protects these bits from further accidental change . In case of a program sequencing issue (code runaway) the COP conﬁguration can not be accidentally modiﬁed anymore .

10.7.2 Application information for COP and API usage

In many applications the COP is used to check that the program is running and sequencing properly. Often the COP is kept running during Stop Mode and periodic wake-up events are needed to service the COP on time and maybe to check the system status. For such an application it is recommended to use the ACLK as clock source for both COP and API. This guarantees lowest possible IDD current during Stop Mode. Additionally it eases software implementation using the same clock source for both, COP and API. The Interrupt Service Routine (ISR) of the Autonomous Periodic Interrupt API should contain the write instruction to the CPMUARMCOP register . The value (byte) written is derived from the “main routine” (alternating sequence of $55 and $AA) of the application software. Using this method, then in the case of a runtime or program sequencing issue the application “main routine” is not executed properly anymore and the alternating values are not provided properly . Hence the COP is written at the correct time (due to independent API interrupt request) but the wrong value is written (alternating sequence of $55 and $AA is no longer maintained) which causes a COP reset

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11.1 Introduction

The ADC10B8C is a 8-channel, , multiplexed input successive approximation analog-to-digital converter. Refer to device electrical speciﬁcations for ATD accuracy.

11.1.1 Features

8-, 10-bit resolution.
Automatic return to low power after conversion sequence
Automatic compare with interrupt for higher than or less/equal than programmable value Version Number Revision Date Effective Date Author Description of Changes V02.00 13 May 2009 13 May 2009 Initial version copied from V01.05, changed unused Bits in ATDDIEN to read logic 1 V02.01 17 Dec 2009 17 Dec 2009 Updated Table 11-15 Analog Input Channel Select Coding - description of internal channels. Updated register ATDDR (left/right justiﬁed result) description added Table 11-21 to improve feature description. V02.02 09 Feb 2010 09 Feb 2010 Fixed typo in Table 11-9- conversion result for 3mV and 10bit resolution V02.03 26 Feb 2010 26 Feb 2010 Corrected Table 11-15Analog Input Channel Select Coding - description of internal channels. V02.04 14 Apr 2010 14 Apr 2010 Corrected typos to be in-line with SoC level pin naming conventions for VDDA, VSSA, VRL and VRH. V02.05 25 Aug 2010 25 Aug 2010 Removed feature of conversion during STOP and general wording clean up done in Section 11.4, “Functional

Description

V02.06 09 Sep 2010 09 Sep 2010 Update of internal only information. V02.07 11 Feb 2011 11 Feb 2011 Connectivity Information regarding internal channel_6 added to Table 11-15.

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Programmable sample time.
Left/right justiﬁed result data.
External trigger control.
Sequence complete interrupt.
Analog input multiplexer for 8 analog input channels.
Special conversions for VRH, VRL, (VRL+VRH)/2.
1-to-8 conversion sequence lengths.
Continuous conversion mode.
Multiple channel scans.
Conﬁgurable external trigger functionality on any AD channel or any of four additional trigger inputs. The four additional trigger inputs can be chip external or internal. Refer to device speciﬁcation for availability and connectivity.
Conﬁgurable location for channel wrap around (when converting multiple channels in a sequence).

11.1.2 Modes of Operation

11.1.2.1 Conversion Modes

There is software programmable selection between performing single or continuous conversion on a single channel or multiple channels.

11.1.2.2 MCU Operating Modes

Stop Mode Entering Stop Mode aborts any conversion sequence in progress and if a sequence was aborted restarts it after exiting stop mode. This has the same effect/consequences as starting a conversion sequence with write to ATDCTL5. So after exiting from stop mode with a previously aborted sequence all ﬂags are cleared etc.
Wait Mode ADC10B8C behaves same in Run and Wait Mode. For reduced power consumption continuous conversions should be aborted before entering Wait mode.
Freeze Mode In Freeze Mode the ADC10B8C will either continue or ﬁnish or stop converting according to the FRZ1 and FRZ0 bits. This is useful for debugging and emulation.

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11.1.3 Block Diagram

Figure 11-1. ADC10B8C Block Diagram VSSA AN6 ATD_12B8C Analog MUX Mode and Successive Approximation Register (SAR) Results ATD 0 ATD 1 ATD 2 ATD 3 ATD 4 ATD 5 ATD 6 ATD 7 and DAC Sample & Hold VDDA VRL VRH Sequence Complete Comparator Clock Prescaler Bus Clock ATD Clock AN5 AN4 AN3 AN1 AN0 AN7 ETRIG0 (See device speciﬁ- cation for availability ETRIG1 ETRIG2 ETRIG3 and connectivity) Timing Control ATDDIENATDCTL1 Trigger Mux Interrupt Compare Interrupt AN2

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11.2 Signal Description

This section lists all inputs to the ADC10B8C block.

11.2.1 Detailed Signal Descriptions

This pin serves as the analog input Channel x. It can also be conﬁgured as digital port or external trigger for the ATD conversion.

11.2.1.2 ETRIG3, ETRIG2, ETRIG1, ETRIG0

These inputs can be conﬁgured to serve as an external trigger for the ATD conversion. Refer to device speciﬁcation for availability and connectivity of these inputs!

11.2.1.3 VRH, VRL

VRH is the high reference voltage, VRL is the low reference voltage for ATD conversion.

11.2.1.4 VDDA, VSSA

These pins are the power supplies for the analog circuitry of the ADC10B8C block.

11.3 Memory Map and Register Deﬁnition

This section provides a detailed description of all registers accessible in the ADC10B8C.

11.3.1 Module Memory Map

Figure 11-2 gives an overview on all ADC10B8C registers. NOTE Register Address = Base Address + Address Offset, where the Base Address is deﬁned at the MCU level and the Address Offset is deﬁned at the module level. Address Name Bit 7 6 5 4 3 2 1 Bit 0 0x0000 ATDCTL0 R Reserved 000 WRAP3 WRAP2 WRAP1 WRAP0W 0x0001 ATDCTL1 R ETRIGSEL SRES1 SRES0 SMP_DIS ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0W 0x0002 ATDCTL2 R0 AFFC Reserved ETRIGLE ETRIGP ETRIGE ASCIE ACMPIEW = Unimplemented or Reserved Figure 11-2. ADC10B8C Register Summary (Sheet 1 of 2)

Analog-to-Digital Converter (ADC10B8CV2) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 375 0x0003 ATDCTL3 R DJM S8C S4C S2C S1C FIFO FRZ1 FRZ0W 0x0004 ATDCTL4 R SMP2 SMP1 SMP0 PRS[4:0]W 0x0005 ATDCTL5 R0 SC SCAN MULT CD CC CB CAW 0x0006 ATDSTAT0 R SCF 0 ETORF FIFOR CC3 CC2 CC1 CC0 W 0x0007 Unimple- mented R 0 000 0 0 0 0 W 0x0008 ATDCMPEH R 0 000 0 0 0 0 W 0x0009 ATDCMPEL R CMPE[7:0]W 0x000A ATDSTAT2H R 0 000 0 0 0 0 W 0x000B ATDSTAT2L R CCF[7:0] W 0x000C ATDDIENH R 1 111 1 1 1 1 W 0x000D ATDDIENL R IEN[7:0]W 0x000E ATDCMPHTH R 0 000 0 0 0 0 W 0x000F ATDCMPHTL R CMPHT[7:0]W 0x0010 ATDDR0 R See Section 11.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” and Section 11.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”W 0x0012 ATDDR1 R See Section 11.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” and Section 11.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”W 0x0014 ATDDR2 R See Section 11.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” and Section 11.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”W 0x0016 ATDDR3 R See Section 11.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” and Section 11.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”W 0x0018 ATDDR4 R See Section 11.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” and Section 11.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”W 0x001A ATDDR5 R See Section 11.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” and Section 11.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”W 0x001C ATDDR6 R See Section 11.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” and Section 11.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”W 0x001E ATDDR7 R See Section 11.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” and Section 11.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”W 0x0020 - 0x002F Unimple- mented R 0 0 0 0 0000 W Address Name Bit 7 6 5 4 3 2 1 Bit 0 = Unimplemented or Reserved Figure 11-2. ADC10B8C Register Summary (Sheet 2 of 2)

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11.3.2 Register Descriptions

This section describes in address order all the ADC10B8C registers and their individual bits.

11.3.2.1 ATD Control Register 0 (ATDCTL0)

Writes to this register will abort current conversion sequence. Read: Anytime Write: Anytime, in special modes always write 0 to Reserved Bit 7. Module Base + 0x0000 76543210 R Reserved 000 WRAP3 WRAP2 WRAP1 WRAP0 W Reset 0 0 0 01111 = Unimplemented or Reserved Figure 11-3. ATD Control Register 0 (ATDCTL0) Table 11-1. ATDCTL0 Field Descriptions Field Description 3-0 WRAP[3-0] Wrap Around Channel Select Bits — These bits determine the channel for wrap around when doing multi-channel conversions. The coding is summarized in Table 11-2. Table 11-2. Multi-Channel Wrap Around Coding WRAP3 WRAP2 WRAP1 WRAP0 Multiple Channel Conversions (MULT = 1) Wraparound to AN0 after Converting

0000 Reserved1

0001 A N 1

0010 A N 2

0011 A N 3

0100 A N 4

0101 A N 5

0110 A N 6

0111 A N 7

1000 A N 7

1001 A N 7

1010 A N 7

1011 A N 7

1100 A N 7

1101 A N 7

1110 A N 7

1111 A N 7

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11.3.2.2 ATD Control Register 1 (ATDCTL1)

Writes to this register will abort current conversion sequence. Read: Anytime Write: Anytime 1If only AN0 should be converted use MULT=0. Module Base + 0x0001 76543210 R ETRIGSEL SRES1 SRES0 SMP_DIS ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0 W Reset 0 0 1 01111 Figure 11-4. ATD Control Register 1 (ATDCTL1) Table 11-3. ATDCTL1 Field Descriptions Field Description ETRIGSEL External Trigger Source Select — This bit selects the external trigger source to be either one of the AD channels or one of the ETRIG3-0 inputs. See device speciﬁcation for availability and connectivity of ETRIG3-0 inputs. If a particular ETRIG3-0 input option is not available, writing a 1 to ETRISEL only sets the bit but has no effect, this means that one of the AD channels (selected by ETRIGCH3-0) is conﬁgured as the source for external trigger. The coding is summarized in Table 11-5. 6–5 SRES[1:0] A/D Resolution Select — These bits select the resolution of A/D conversion results. See Table 11-4 for coding. SMP_DIS Discharge Before Sampling Bit 0 No discharge before sampling. 1 The internal sample capacitor is discharged before sampling the channel. This adds 2 ATD clock cycles to the sampling time. This can help to detect an open circuit instead of measuring the previous sampled channel. 3–0 ETRIGCH[3:0] External Trigger Channel Select— These bits select one of the AD channels or one of the ETRIG3-0 inputs as source for the external trigger. The coding is summarized in Table 11-5. Table 11-4. A/D Resolution Coding SRES1 SRES0 A/D Resolution 0 0 8-bit data 0 1 10-bit data 1 1 Reserved Table 11-5. External Trigger Channel Select Coding ETRIGSEL ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0 External trigger source is 0 0 0 0 0 AN0 0 0 0 0 1 AN1

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11.3.2.3 ATD Control Register 2 (ATDCTL2)

Writes to this register will abort current conversion sequence. Read: Anytime Write: Anytime 0 0 0 1 0 AN2 0 0 0 1 1 AN3 0 0 1 0 0 AN4 0 0 1 0 1 AN5 0 0 1 1 0 AN6 0 0 1 1 1 AN7 0 1 0 0 0 AN7 0 1 0 0 1 AN7 0 1 0 1 0 AN7 0 1 0 1 1 AN7 0 1 1 0 0 AN7 0 1 1 0 1 AN7 0 1 1 1 0 AN7 0 1 1 1 1 AN7 1 0 0 0 0 ETRIG0 1 0 0 0 1 ETRIG1 1 1 0 0 1 0 ETRIG2 1 1 0 0 1 1 ETRIG3 1 1 0 1 X X Reserved 1 1 X X X Reserved 1 Only if ETRIG3-0 input option is available (see device speciﬁcation), else ETRISEL is ignored, that means external trigger source is still on one of the AD channels selected by ETRIGCH3-0 Module Base + 0x0002 76543210 AFFC Reserved ETRIGLE ETRIGP ETRIGE ASCIE ACMPIE W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 11-5. ATD Control Register 2 (ATDCTL2) Table 11-5. External Trigger Channel Select Coding ETRIGSEL ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0 External trigger source is

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11.3.2.4 ATD Control Register 3 (ATDCTL3)

Writes to this register will abort current conversion sequence. Table 11-6. ATDCTL2 Field Descriptions Field Description AFFC ATD Fast Flag Clear All 0 ATD ﬂag clearing done by write 1 to respective CCF[ n] ﬂag. 1 Changes all ATD conversion complete ﬂags to a fast clear sequence. For compare disabled (CMPE[n]=0) a read access to the result register will cause the associated CCF[n] ﬂag to clear automatically. For compare enabled (CMPE[n]=1) a write access to the result register will cause the associated CCF[n] ﬂag to clear automatically. Reserved Do not alter this bit from its reset value.It is for Manufacturer use only and can change the ATD behavior. ETRIGLE External Trigger Level/Edge Control — This bit controls the sensitivity of the external trigger signal. See Table 11-7 for details. ETRIGP External Trigger Polarity— This bit controls the polarity of the external trigger signal. SeeTable 11-7for details. ETRIGE External Trigger Mode Enable— This bit enables the external trigger on one of the AD channels or one of the ETRIG3-0 inputs as described in Table 11-5. If the external trigger source is one of the AD channels, the digital input buffer of this channel is enabled. The external trigger allows to synchronize the start of conversion with external events.

0 Disable external trigger

1 Enable external trigger

ATD Sequence Complete Interrupt Enable 0 ATD Sequence Complete interrupt requests are disabled. 1 ATD Sequence Complete interrupt will be requested whenever SCF=1 is set. ACMPIE ATD Compare Interrupt Enable— If automatic compare is enabled for conversion n (CMPE[n]=1 in ATDCMPE register) this bit enables the compare interrupt. If the CCF[n] ﬂag is set (showing a successful compare for conversion n), the compare interrupt is triggered. 0 ATD Compare interrupt requests are disabled.

1 For the conversions in a sequence for which automatic compare is enabled (CMPE[ n]=1), an ATD Compare

Interrupt will be requested whenever any of the respective CCF ﬂags is set. Table 11-7. External Trigger Conﬁgurations ETRIGLE ETRIGP External Trigger Sensitivity 0 0 Falling edge 0 1 Rising edge 1 0 Low level 1 1 High level

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Read: Anytime Write: Anytime Module Base + 0x0003 76543210 R DJM S8C S4C S2C S1C FIFO FRZ1 FRZ0 W Reset 0 0 1 00000 = Unimplemented or Reserved Figure 11-6. ATD Control Register 3 (ATDCTL3) Table 11-8. ATDCTL3 Field Descriptions Field Description DJM Result Register Data Justiﬁcation — Result data format is always unsigned. This bit controls justiﬁcation of conversion data in the result registers. 0 Left justiﬁed data in the result registers. 1 Right justiﬁed data in the result registers. Table 11-9 gives example ATD results for an input signal range between 0 and 5.12 Volts. 6–3 S8C, S4C, S2C, S1C Conversion Sequence Length — These bits control the number of conversions per sequence. Table 11-10 shows all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity to HC12 family. FIFO Result Register FIFO Mode— If this bit is zero (non-FIFO mode), the A/D conversion results map into the result registers based on the conversion sequence; the result of the ﬁrst conversion appears in the ﬁrst result register (ATDDR0), the second result in the second result register (ATDDR1), and so on. If this bit is one (FIFO mode) the conversion counter is not reset at the beginning or end of a conversion sequence; sequential conversion results are placed in consecutive result registers. In a continuously scanning conversion sequence, the result register counter will wrap around when it reaches the end of the result register ﬁle. The conversion counter value (CC3-0 in ATDSTAT0) can be used to determine where in the result register ﬁle, the current conversion result will be placed. Aborting a conversion or starting a new conversion clears the conversion counter even if FIFO=1. So the ﬁrst result of a new conversion sequence, started by writing to ATDCTL5, will always be place in the ﬁrst result register (ATDDDR0). Intended usage of FIFO mode is continuos conversion (SCAN=1) or triggered conversion (ETRIG=1). Which result registers hold valid data can be tracked using the conversion complete ﬂags. Fast ﬂag clear mode may be useful in a particular application to track valid data. If this bit is one, automatic compare of result registers is always disabled, that is ADC10B8C will behave as if ACMPIE and all CPME[n] were zero. 0 Conversion results are placed in the corresponding result register up to the selected sequence length. 1 Conversion results are placed in consecutive result registers (wrap around at end). 1–0 FRZ[1:0] Background Debug Freeze Enable — When debugging an application, it is useful in many cases to have the ATD pause when a breakpoint (Freeze Mode) is encountered. These 2 bits determine how the ATD will respond to a breakpoint as shown in Table 11-11. Leakage onto the storage node and comparator reference capacitors may compromise the accuracy of an immediately frozen conversion depending on the length of the freeze period.

Analog-to-Digital Converter (ADC10B8CV2) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 381 Table 11-9. Examples of ideal decimal ATD Results Input Signal VRL = 0 Volts VRH = 5.12 Volts 8-Bit Codes (resolution=20mV) 10-Bit Codes (resolution=5mV)

5.120 Volts

... 0.022 0.020 0.018 0.016 0.014 0.012 0.010 0.008 0.006 0.004 0.003 0.002 0.000 255 ... 1023 ... Table 11-10. Conversion Sequence Length Coding S8C S4C S2C S1C Number of Conversions per Sequence 00 0 0 8 00 0 1 1 00 1 0 2 00 1 1 3 01 0 0 4 01 0 1 5 01 1 0 6 01 1 1 7 10 0 0 8 10 0 1 8 10 1 0 8 10 1 1 8 11 0 0 8 11 0 1 8 11 1 0 8 11 1 1 8 Table 11-11. ATD Behavior in Freeze Mode (Breakpoint) FRZ1 FRZ0 Behavior in Freeze Mode 0 0 Continue conversion 0 1 Reserved 1 0 Finish current conversion, then freeze

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11.3.2.5 ATD Control Register 4 (ATDCTL4)

Writes to this register will abort current conversion sequence. Read: Anytime Write: Anytime 1 1 Freeze Immediately Module Base + 0x0004 76543210 R SMP2 SMP1 SMP0 PRS[4:0] W Reset 0 0 0 00101 Figure 11-7. ATD Control Register 4 (ATDCTL4) Table 11-12. ATDCTL4 Field Descriptions Field Description 7–5 SMP[2:0] Sample Time Select — These three bits select the length of the sample time in units of ATD conversion clock cycles. Note that the ATD conversion clock period is itself a function of the prescaler value (bits PRS4-0). Table 11-13 lists the available sample time lengths. 4–0 PRS[4:0] ATD Clock Prescaler— These 5 bits are the binary prescaler value PRS. The ATD conversion clock frequency is calculated as follows: Refer to Device Speciﬁcation for allowed frequency range of f ATDCLK. Table 11-13. Sample Time Select SMP2 SMP1 SMP0 Sample Time in Number of ATD Clock Cycles 000 4 001 6 010 8 011 1 0 100 1 2 101 1 6 110 2 0 111 2 4 Table 11-11. ATD Behavior in Freeze Mode (Breakpoint) FRZ1 FRZ0 Behavior in Freeze Mode fATDCLK fBUS

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11.3.2.6 ATD Control Register 5 (ATDCTL5)

0 Special channel conversions disabled

1 Special channel conversions enabled

Continuous Conversion Sequence Mode — This bit selects whether conversion sequences are performed continuously or only once. If the external trigger function is enabled (ETRIGE=1) setting this bit has no effect, thus the external trigger always starts a single conversion sequence.

0 Single conversion sequence

1 Continuous conversion sequences (scan mode)

Multi-Channel Sample Mode— When MULT is 0, the ATD sequence controller samples only from the speciﬁed analog input channel for an entire conversion sequence. The analog channel is selected by channel selection code (control bits CD/CC/CB/CA located in ATDCTL5). When MULT is 1, the ATD sequence controller samples across channels. The number of channels sampled is determined by the sequence length value (S8C, S4C, S2C, S1C). The ﬁrst analog channel examined is determined by channel selection code (CD, CC, CB, CA control bits); subsequent channels sampled in the sequence are determined by incrementing the channel selection code or wrapping around to AN0 (channel 0).

0 Sample only one channel

1 Sample across several channels

3–0 CD, CC, CB, CA Analog Input Channel Select Code — These bits select the analog input channel(s). Table 11-15 lists the coding used to select the various analog input channels. In the case of single channel conversions (MULT=0), this selection code speciﬁes the channel to be examined. In the case of multiple channel conversions (MULT=1), this selection code speciﬁes the ﬁrst channel to be examined in the conversion sequence. Subsequent channels are determined by incrementing the channel selection code or wrapping around to AN0 (after converting the channel deﬁned by the Wrap Around Channel Select Bits WRAP3-0 in ATDCTL0). When starting with a channel number higher than the one deﬁned by WRAP3-0 the ﬁrst wrap around will be AN7 to AN0.

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11.3.2.7 ATD Status Register 0 (ATDSTAT0)

This register contains the Sequence Complete Flag, overrun ﬂags for external trigger and FIFO mode, and the conversion counter. Table 11-15. Analog Input Channel Select Coding SC CD CC CB CA Analog Input Channel

00000 A N 0

1 0 0 0 0 Internal_6, 0 0 0 1 Internal_7 0 0 1 0 Internal_0 0 0 1 1 Internal_1

0100 V R H

0101 V R L

0 1 1 0 (VRH+VRL) / 2 0 1 1 1 Reserved 1 0 0 0 Internal_2 1 0 0 1 Internal_3 1 0 1 0 Internal_4 1 0 1 1 Internal_5 1 1 X X Reserved

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0 Conversion sequence not completed

1 Conversion sequence has completed

External Trigger Overrun Flag — While in edge sensitive mode (ETRIGLE=0), if additional active edges are detected while a conversion sequence is in process the overrun ﬂag is set. This ﬂag is cleared when one of the following occurs: A) Write “1” to ETORF B) Write to ATDCTL0,1,2,3,4, ATDCMPE or ATDCMPHT (a conversion sequence is aborted) C) Write to ATDCTL5 (a new conversion sequence is started)

0 No External trigger overrun error has occurred

1 External trigger overrun error has occurred

Result Register Overrun Flag— This bit indicates that a result register has been written to before its associated conversion complete ﬂag (CCF) has been cleared. This ﬂag is most useful when using the FIFO mode because the ﬂag potentially indicates that result registers are out of sync with the input channels. However, it is also practical for non-FIFO modes, and indicates that a result register has been overwritten before it has been read (i.e. the old data has been lost). This ﬂag is cleared when one of the following occurs: A) Write “1” to FIFOR B) Write to ATDCTL0,1,2,3,4, ATDCMPE or ATDCMPHT (a conversion sequence is aborted) C) Write to ATDCTL5 (a new conversion sequence is started)

0 No overrun has occurred

1 Overrun condition exists (result register has been written while associated CCFx ﬂag was still set)

3–0 CC[3:0] Conversion Counter — These 4 read-only bits are the binary value of the conversion counter. The conversion counter points to the result register that will receive the result of the current conversion. E.g. CC3=0, CC2=1, CC1=1, CC0=0 indicates that the result of the current conversion will be in ATD Result Register 6. If in non-FIFO mode (FIFO=0) the conversion counter is initialized to zero at the beginning and end of the conversion sequence. If in FIFO mode (FIFO=1) the register counter is not initialized. The conversion counter wraps around when its maximum value is reached. Aborting a conversion or starting a new conversion clears the conversion counter even if FIFO=1.

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11.3.2.8 ATD Compare Enable Register (ATDCMPE)

Writes to this register will abort current conversion sequence. Read: Anytime Write: Anytime

11.3.2.9 ATD Status Register 2 (ATDSTAT2)

This read-only register contains the Conversion Complete Flags CCF[7:0]. Read: Anytime Write: Anytime, no effect Module Base + 0x0008 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 000 CMPE[7:0] W Reset 0 0 0 0 0 0 0 0 0 0000000 = Unimplemented or Reserved Figure 11-10. ATD Compare Enable Register (ATDCMPE) Table 11-17. ATDCMPE Field Descriptions Field Description 7–0 CMPE[7:0] Compare Enable for Conversion Numbern (n= 7, 6, 5, 4, 3, 2, 1, 0) of a Sequence (n conversion number, NOT channel number!) — These bits enable automatic compare of conversion results individually for conversions of a sequence. The sense of each comparison is determined by the CMPHT[n] bit in the ATDCMPHT register. For each conversion number with CMPE[n]=1 do the following: 1) Write compare value to ATDDRn result register 2) Write compare operator with CMPHT[n] in ATDCPMHT register CCF[n] in ATDSTAT2 register will ﬂag individual success of any comparison.

0 No automatic compare

1 Automatic compare of results for conversion n of a sequence is enabled. Module Base + 0x000A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 CCF[7:0] W Reset 0 0 0 0 0 0 0 0 0 0000000 = Unimplemented or Reserved Figure 11-11. ATD Status Register 2 (ATDSTAT2)

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11.3.2.10 ATD Input Enable Register (ATDDIEN)

Read: Anytime Write: Anytime Table 11-18. ATDSTAT2 Field Descriptions Field Description 7–0 CCF[7:0] Conversion Complete Flag n (n= 7, 6, 5, 4, 3, 2, 1, 0) (n conversion number, NOT channel number!)— A conversion complete ﬂag is set at the end of each conversion in a sequence. The ﬂags are associated with the conversion position in a sequence (and also the result register number). Therefore in non-ﬁfo mode, CCF[4] is set when the ﬁfth conversion in a sequence is complete and the result is available in result register ATDDR4; CCF[5] is set when the sixth conversion in a sequence is complete and the result is available in ATDDR5, and so forth. If automatic compare of conversion results is enabled (CMPE[n]=1 in ATDCMPE), the conversion complete ﬂag is only set if comparison with ATDDRn is true. If ACMPIE=1 a compare interrupt will be requested. In this case, as the ATDDRn result register is used to hold the compare value, the result will not be stored there at the end of the conversion but is lost. A ﬂag CCF[n] is cleared when one of the following occurs: A) Write to ATDCTL5 (a new conversion sequence is started) B) If AFFC=0, write “1” to CCF[n] C) If AFFC=1 and CMPE[n]=0, read of result register ATDDRn D) If AFFC=1 and CMPE[n]=1, write to result register ATDDRn In case of a concurrent set and clear on CCF[n]: The clearing by method A) will overwrite the set. The clearing by methods B) or C) or D) will be overwritten by the set.

0 Conversion number n not completed or successfully compared

1 If (CMPE[ n]=0): Conversion number n has completed. Result is ready in ATDDRn. If (CMPE[n]=1): Compare for conversion result number n with compare value in ATDDRn, using compare operator CMPGT[n] is true. (No result available in ATDDRn) Module Base + 0x000C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 1 1 1 1 1 111 IEN[7:0] W Reset 1 1 1 1 1 1 1 1 0 0000000 = Unimplemented or Reserved Figure 11-12. ATD Input Enable Register (ATDDIEN) Table 11-19. ATDDIEN Field Descriptions Field Description 7–0 IEN[7:0] ATD Digital Input Enable on channelx (x=7 ,6 ,5 ,4 ,3 ,2 ,1 ,0 )— This bit controls the digital input buffer from the analog input pin (ANx) to the digital data register.

0 Disable digital input buffer to AN x pin

1 Enable digital input buffer on AN x pin. Note: Setting this bit will enable the corresponding digital input buffer continuously. If this bit is set while simultaneously using it as an analog port, there is potentially increased power consumption because the digital input buffer maybe in the linear region.

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11.3.2.11 ATD Compare Higher Than Register (ATDCMPHT)

Writes to this register will abort current conversion sequence. Read: Anytime Write: Anytime

11.3.2.12 ATD Conversion Result Registers (ATDDR n)

The A/D conversion results are stored in 8 result registers. Results are always in unsigned data representation. Left and right justiﬁcation is selected using the DJM control bit in ATDCTL3. If automatic compare of conversions results is enabled (CMPE[n]=1 in ATDCMPE), these registers must be written with the compare values in left or right justiﬁed format depending on the actual value of the DJM bit. In this case, as the ATDDRn register is used to hold the compare value, the result will not be stored there at the end of the conversion but is lost. Attention, n is the conversion number, NOT the channel number! Read: Anytime Write: Anytime NOTE For conversions not using automatic compare, results are stored in the result registers after each conversion. In this case avoid writing to ATDDRn except for initial values, because an A/D result might be overwritten. Module Base + 0x000E 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 000 CMPHT[7:0] W Reset 0 0 0 0 0 0 0 0 0 0000000 = Unimplemented or Reserved Figure 11-13. ATD Compare Higher Than Register (ATDCMPHT) Table 11-20. ATDCMPHT Field Descriptions Field Description 7–0 CMPHT[7:0] Compare Operation Higher Than Enable for conversion numbern (n= 7, 6, 5, 4, 3, 2, 1, 0) of a Sequence (n conversion number, NOT channel number!)— This bit selects the operator for comparison of conversion results.

0 If result of conversion n is lower or same than compare value in ATDDRn, this is ﬂagged in ATDSTAT2

1 If result of conversion n is higher than compare value in ATDDRn, this is ﬂagged in ATDSTAT2

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11.3.2.12.1 Left Justiﬁed Result Data (DJM=0)

Table 11-21 shows how depending on the A/D resolution the conversion result is transferred to the ATD result registers for left justiﬁed data. Compare is always done using all 12 bits of both the conversion result and the compare value in ATDDRn.

11.3.2.12.2 Right Justiﬁed Result Data (DJM=1)

Table 11-22 shows how depending on the A/D resolution the conversion result is transferred to the ATD result registers for right justiﬁed data. Compare is always done using all 12 bits of both the conversion result and the compare value in ATDDRn. Module Base + 0x0010 = ATDDR0, 0x0012 = ATDDR1, 0x0014 = ATDDR2, 0x0016 = ATDDR3 0x0018 = ATDDR4, 0x001A = ATDDR5, 0x001C = ATDDR6, 0x001E = ATDDR7 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Result-Bit[11:0] 0 000 W Reset 0 0 0 0 0 0 0 0 0 0000000 = Unimplemented or Reserved Figure 11-14. Left justiﬁed ATD conversion result register (ATDDRn) Table 11-21. Conversion result mapping to ATDDRn A/D resolution DJM conversion result mapping to ATDDRn 8-bit data 0 Result-Bit[11:4] = conversion result, Result-Bit[3:0]=0000 10-bit data 0 Result-Bit[11:2] = conversion result, Result-Bit[1:0]=00 Module Base + 0x0010 = ATDDR0, 0x0012 = ATDDR1, 0x0014 = ATDDR2, 0x0016 = ATDDR3 0x0018 = ATDDR4, 0x001A = ATDDR5, 0x001C = ATDDR6, 0x001E = ATDDR7 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 000 Result-Bit[11:0] W Reset 0 0 0 0 0 0 0 0 0 0000000 = Unimplemented or Reserved Figure 11-15. Right justiﬁed ATD conversion result register (ATDDRn)

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11.4 Functional Description

The ADC10B8C consists of an analog sub-block and a digital sub-block.

11.4.1 Analog Sub-Block

The analog sub-block contains all analog electronics required to perform a single conversion. Separate power supplies VDDA and VSSA allow to isolate noise of other MCU circuitry from the analog sub-block.

11.4.1.1 Sample and Hold Machine

The Sample and Hold Machine controls the storage and charge of the sample capacitor to the voltage level of the analog signal at the selected ADC input channel. During the sample process the analog input connects directly to the storage node. The input analog signals are unipolar and must be within the potential range of VSSA to VDDA. During the hold process the analog input is disconnected from the storage node.

11.4.1.2 Analog Input Multiplexer

The analog input multiplexer connects one of the 8 external analog input channels to the sample and hold machine.

11.4.1.3 Analog-to-Digital (A/D) Machine

The A/D Machine performs analog to digital conversions. The resolution is program selectable to be either 8 or 10 bits. The A/D machine uses a successive approximation architecture. It functions by comparing the sampled and stored analog voltage with a series of binary coded discrete voltages. By following a binary search algorithm, the A/D machine identiﬁes the discrete voltage that is nearest to the sampled and stored voltage. When not converting the A/D machine is automatically powered down. Table 11-22. Conversion result mapping to ATDDRn A/D resolution DJM conversion result mapping to ATDDRn 8-bit data 1 Result-Bit[7:0] = result, Result-Bit[11:8]=0000 10-bit data 1 Result-Bit[9:0] = result, Result-Bit[11:10]=00

Analog-to-Digital Converter (ADC10B8CV2) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 391 Only analog input signals within the potential range of VRL to VRH (A/D reference potentials) will result in a non-railed digital output code.

11.4.2 Digital Sub-Block

This subsection describes some of the digital features in more detail. See Section 11.3.2, “Register Descriptions” for all details.

11.4.2.1 External Trigger Input

The external trigger feature allows the user to synchronize ATD conversions to an external event rather than relying only on software to trigger the ATD module when a conversion is about to take place. The external trigger signal (out of reset ATD channel 7, conﬁgurable in ATDCTL1) is programmable to be edge or level sensitive with polarity control.Table 11-23 gives a brief description of the different combinations of control bits and their effect on the external trigger function. In either level or edge sensitive mode, the ﬁrst conversion begins when the trigger is received. Once ETRIGE is enabled a conversion must be triggered externally after writing the ATDCTL5 register. During a conversion in edge sensitive mode, if additional trigger events are detected the overrun error ﬂag ETORF is set. If level sensitive mode is active and the external trigger de-asserts and later asserts again during a conversion sequence, this does not constitute an overrun. Therefore, the ﬂag is not set. If the trigger is left active in level sensitive mode when a sequence is about to complete, another sequence will be triggered immediately. Table 11-23. External Trigger Control Bits ETRIGLE ETRIGP ETRIGE SCAN Description X X 0 0 Ignores external trigger. Performs one conversion sequence and stops. X X 0 1 Ignores external trigger. Performs continuous conversion sequences. 0 0 1 X Trigger falling edge sensitive. Performs one conversion sequence per trigger. 0 1 1 X Trigger rising edge sensitive. Performs one conversion sequence per trigger. 1 0 1 X Trigger low level sensitive. Performs continuous conversions while trigger level is active. 1 1 1 X Trigger high level sensitive. Performs continuous conversions while trigger level is active.

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11.4.2.2 General-Purpose Digital Port Operation

Each ATD input pin can be switched between analog or digital input functionality. An analog multiplexer makes each ATD input pin selected as analog input available to the A/D converter. The pad of the ATD input pin is always connected to the analog input channel of the analog mulitplexer. Each pad input signal is buffered to the digital port register. This buffer can be turned on or off with the ATDDIEN register for each ATD input pin. This is important so that the buffer does not draw excess current when an ATD input pin is selected as analog input to the ADC10B8C.

11.5 Resets

At reset the ADC10B8C is in a power down state. The reset state of each individual bit is listed within the Register Description section (see Section 11.3.2, “Register Descriptions”) which details the registers and their bit-ﬁeld.

11.6 Interrupts

The interrupts requested by the ADC10B8C are listed in Table 11-24. Refer to MCU speciﬁcation for related vector address and priority. See Section 11.3.2, “Register Descriptions” for further details. Table 11-24. ATD Interrupt Vectors Interrupt Source CCR Mask Local Enable Sequence Complete Interrupt I bit ASCIE in ATDCTL2 Compare Interrupt I bit ACMPIE in ATDCTL2

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12.1 Introduction

The ADC10B12C is a 12-channel, , multiplexed input successive approximation analog-to-digital converter. Refer to device electrical speciﬁcations for ATD accuracy.

12.1.1 Features

8-, 10-bit resolution. Version Number Revision Date Effective Date Author Description of Changes V02.00 13 May 2009 13 May 2009 Initial version copied from V01.06, changed unused Bits in ATDDIEN to read logic 1 V02.01 30.Nov 2009 30.Nov 2009 Updated Table 12-15 Analog Input Channel Select Coding - description of internal channels. Updated register ATDDR (left/right justiﬁed result) description added table Table 12-21 to improve feature description. V02.02 09 Feb 2010 09 Feb 2010 Fixed typo in Table 12-9- conversion result for 3mV and 10bit resolution V02.03 26 Feb 2010 26 Feb 2010 Corrected Table 12-15Analog Input Channel Select Coding - description of internal channels. V02.04 14 Apr 2010 14 Apr 2010 Corrected typos to be in-line with SoC level pin naming conventions for VDDA, VSSA, VRL and VRH. V02.05 25 Aug 2010 25 Aug 2010 Removed feature of conversion during STOP and general wording clean up done in Section 12.4, “Functional

V02.06 09 Sep 2010 09 Sep 2010 Update of internal only information. V02.07 11 Feb 2011 11 Feb 2011 Connectivity Information regarding internal channel_6 added to Table 12-15. V02.08 29 Mar 2011 29 Mar 2011 Fixed typo in bit description ﬁeld Table 12-14for bits CD, CC, CB, CA. Last sentence contained a wrong highest channel number (it is not AN7 to AN0 instead it is AN11 to AN0).

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Automatic return to low power after conversion sequence
Automatic compare with interrupt for higher than or less/equal than programmable value
Programmable sample time.
Left/right justiﬁed result data.
External trigger control.
Sequence complete interrupt.
Analog input multiplexer for 8 analog input channels.
Special conversions for VRH, VRL, (VRL+VRH)/2.
1-to-12 conversion sequence lengths.
Continuous conversion mode.
Multiple channel scans.
Conﬁgurable external trigger functionality on any AD channel or any of four additional trigger inputs. The four additional trigger inputs can be chip external or internal. Refer to device speciﬁcation for availability and connectivity.
Conﬁgurable location for channel wrap around (when converting multiple channels in a sequence).

12.1.2 Modes of Operation

12.1.2.1 Conversion Modes

There is software programmable selection between performing single or continuous conversion on a single channel or multiple channels.

12.1.2.2 MCU Operating Modes

Stop Mode Entering Stop Mode aborts any conversion sequence in progress and if a sequence was aborted restarts it after exiting stop mode. This has the same effect/consequences as starting a conversion sequence with write to ATDCTL5. So after exiting from stop mode with a previously aborted sequence all ﬂags are cleared etc.
Wait Mode ADC10B12C behaves same in Run and Wait Mode. For reduced power consumption continuous conversions should be aborted before entering Wait mode.
Freeze Mode In Freeze Mode the ADC10B12C will either continue or ﬁnish or stop converting according to the FRZ1 and FRZ0 bits. This is useful for debugging and emulation.

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12.1.3 Block Diagram

Figure 12-1. ADC10B12C Block Diagram VSSA AN6 ATD_12B12C Analog MUX Mode and Successive Approximation Register (SAR) Results ATD 0 ATD 1 ATD 2 ATD 3 ATD 4 ATD 5 ATD 6 ATD 7 and DAC Sample & Hold VDDA VRL VRH Sequence Complete Comparator Clock Prescaler Bus Clock ATD Clock AN5 AN4 AN3 AN1 AN0 AN7 ETRIG0 (See device speciﬁ- cation for availability ETRIG1 ETRIG2 ETRIG3 and connectivity) Timing Control ATDDIENATDCTL1 Trigger Mux Interrupt Compare Interrupt AN2 AN8 AN9 AN10 AN11 ATD 8 ATD 9 ATD 10 ATD 11

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12.2 Signal Description

This section lists all inputs to the ADC10B12C block.

12.2.1 Detailed Signal Descriptions

This pin serves as the analog input Channel x. It can also be conﬁgured as digital port or external trigger for the ATD conversion.

12.2.1.2 ETRIG3, ETRIG2, ETRIG1, ETRIG0

These inputs can be conﬁgured to serve as an external trigger for the ATD conversion. Refer to device speciﬁcation for availability and connectivity of these inputs!

12.2.1.3 VRH, VRL

VRH is the high reference voltage, VRL is the low reference voltage for ATD conversion.

12.2.1.4 VDDA, VSSA

These pins are the power supplies for the analog circuitry of the ADC10B12C block.

12.3 Memory Map and Register Deﬁnition

This section provides a detailed description of all registers accessible in the ADC10B12C.

12.3.1 Module Memory Map

Figure 12-2 gives an overview on all ADC10B12C registers. NOTE Register Address = Base Address + Address Offset, where the Base Address is deﬁned at the MCU level and the Address Offset is deﬁned at the module level. Address Name Bit 7 6 5 4 3 2 1 Bit 0 0x0000 ATDCTL0 R Reserved 000 WRAP3 WRAP2 WRAP1 WRAP0W 0x0001 ATDCTL1 R ETRIGSEL SRES1 SRES0 SMP_DIS ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0W 0x0002 ATDCTL2 R0 AFFC Reserved ETRIGLE ETRIGP ETRIGE ASCIE ACMPIEW = Unimplemented or Reserved Figure 12-2. ADC10B12C Register Summary (Sheet 1 of 3)

Analog-to-Digital Converter (ADC10B12CV2) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 397 0x0003 ATDCTL3 R DJM S8C S4C S2C S1C FIFO FRZ1 FRZ0W 0x0004 ATDCTL4 R SMP2 SMP1 SMP0 PRS[4:0]W 0x0005 ATDCTL5 R0 SC SCAN MULT CD CC CB CAW 0x0006 ATDSTAT0 R SCF 0 ETORF FIFOR CC3 CC2 CC1 CC0 W 0x0007 Unimple- mented R 0 000 0 0 0 0 W 0x0008 ATDCMPEH R 0 000 CMPE[11:8]W 0x0009 ATDCMPEL R CMPE[7:0]W 0x000A ATDSTAT2H R 0 0 0 0 CCF[11:8] W 0x000B ATDSTAT2L R CCF[7:0] W 0x000C ATDDIENH R 1 111 IEN[11:8]W 0x000D ATDDIENL R IEN[7:0]W 0x000E ATDCMPHTH R 0 000 CMPHT[11:8]W 0x000F ATDCMPHTL R CMPHT[7:0]W 0x0010 ATDDR0 R See Section 12.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” and Section 12.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”W 0x0012 ATDDR1 R See Section 12.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” and Section 12.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”W 0x0014 ATDDR2 R See Section 12.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” and Section 12.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”W 0x0016 ATDDR3 R See Section 12.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” and Section 12.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”W 0x0018 ATDDR4 R See Section 12.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” and Section 12.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”W 0x001A ATDDR5 R See Section 12.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” and Section 12.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”W 0x001C ATDDR6 R See Section 12.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” and Section 12.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”W 0x001E ATDDR7 R See Section 12.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” and Section 12.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”W 0x0020 ATDDR8 R See Section 12.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” and Section 12.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”W 0x0022 ATDDR9 R See Section 12.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” and Section 12.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”W Address Name Bit 7 6 5 4 3 2 1 Bit 0 = Unimplemented or Reserved Figure 12-2. ADC10B12C Register Summary (Sheet 2 of 3)

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12.3.2 Register Descriptions

This section describes in address order all the ADC10B12C registers and their individual bits.

12.3.2.1 ATD Control Register 0 (ATDCTL0)

Writes to this register will abort current conversion sequence. Read: Anytime Write: Anytime, in special modes always write 0 to Reserved Bit 7. 0x0024 ATDDR10 R See Section 12.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” and Section 12.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”W 0x0026 ATDDR11 R See Section 12.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” and Section 12.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”W 0x0028 - 0x002F Unimple- mented R 0 0 0 0 0000 W Module Base + 0x0000 76543210 R Reserved 000 WRAP3 WRAP2 WRAP1 WRAP0 W Reset 0 0 0 01111 = Unimplemented or Reserved Figure 12-3. ATD Control Register 0 (ATDCTL0) Table 12-1. ATDCTL0 Field Descriptions Field Description 3-0 WRAP[3-0] Wrap Around Channel Select Bits — These bits determine the channel for wrap around when doing multi-channel conversions. The coding is summarized in Table 12-2. Table 12-2. Multi-Channel Wrap Around Coding WRAP3 WRAP2 WRAP1 WRAP0 Multiple Channel Conversions (MULT = 1) Wraparound to AN0 after Converting Address Name Bit 7 6 5 4 3 2 1 Bit 0 = Unimplemented or Reserved Figure 12-2. ADC10B12C Register Summary (Sheet 3 of 3)

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12.3.2.2 ATD Control Register 1 (ATDCTL1)

Writes to this register will abort current conversion sequence. Read: Anytime Write: Anytime

1000 A N 8

1001 A N 9

1010 AN10

1011 AN11

1100 AN11

1101 AN11

1110 AN11

1111 AN11

1If only AN0 should be converted use MULT=0. Module Base + 0x0001 76543210 R ETRIGSEL SRES1 SRES0 SMP_DIS ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0 W Reset 0 0 1 01111 Figure 12-4. ATD Control Register 1 (ATDCTL1) Table 12-3. ATDCTL1 Field Descriptions Field Description ETRIGSEL External Trigger Source Select — This bit selects the external trigger source to be either one of the AD channels or one of the ETRIG3-0 inputs. See device speciﬁcation for availability and connectivity of ETRIG3-0 inputs. If a particular ETRIG3-0 input option is not available, writing a 1 to ETRISEL only sets the bit but has no effect, this means that one of the AD channels (selected by ETRIGCH3-0) is conﬁgured as the source for external trigger. The coding is summarized in Table 12-5. 6–5 SRES[1:0] A/D Resolution Select — These bits select the resolution of A/D conversion results. See Table 12-4 for coding. Table 12-2. Multi-Channel Wrap Around Coding WRAP3 WRAP2 WRAP1 WRAP0 Multiple Channel Conversions (MULT = 1) Wraparound to AN0 after Converting

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SMP_DIS Discharge Before Sampling Bit 0 No discharge before sampling. 1 The internal sample capacitor is discharged before sampling the channel. This adds 2 ATD clock cycles to the sampling time. This can help to detect an open circuit instead of measuring the previous sampled channel. 3–0 ETRIGCH[3:0] External Trigger Channel Select— These bits select one of the AD channels or one of the ETRIG3-0 inputs as source for the external trigger. The coding is summarized in Table 12-5. Table 12-4. A/D Resolution Coding SRES1 SRES0 A/D Resolution 0 0 8-bit data 0 1 10-bit data 1 1 Reserved Table 12-5. External Trigger Channel Select Coding ETRIGSEL ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0 External trigger source is 0 0 0 0 0 AN0 0 0 0 0 1 AN1 0 0 0 1 0 AN2 0 0 0 1 1 AN3 0 0 1 0 0 AN4 0 0 1 0 1 AN5 0 0 1 1 0 AN6 0 0 1 1 1 AN7 0 1 0 0 0 AN8 0 1 0 0 1 AN9 0 1 0 1 0 AN10 0 1 0 1 1 AN11 0 1 1 0 0 AN11 0 1 1 0 1 AN11 0 1 1 1 0 AN11 0 1 1 1 1 AN11 1 0 0 0 0 ETRIG0 1 Only if ETRIG3-0 input option is available (see device speciﬁcation), else ETRISEL is ignored, that means external trigger source is still on one of the AD channels selected by ETRIGCH3-0 1 0 0 0 1 ETRIG1 1 1 0 0 1 0 ETRIG2 1 1 0 0 1 1 ETRIG3 1 1 0 1 X X Reserved 1 1 X X X Reserved Table 12-3. ATDCTL1 Field Descriptions (continued) Field Description

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12.3.2.3 ATD Control Register 2 (ATDCTL2)

Writes to this register will abort current conversion sequence. Read: Anytime Write: Anytime Module Base + 0x0002 76543210 AFFC Reserved ETRIGLE ETRIGP ETRIGE ASCIE ACMPIE W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 12-5. ATD Control Register 2 (ATDCTL2) Table 12-6. ATDCTL2 Field Descriptions Field Description AFFC ATD Fast Flag Clear All 0 ATD ﬂag clearing done by write 1 to respective CCF[ n] ﬂag. 1 Changes all ATD conversion complete ﬂags to a fast clear sequence. For compare disabled (CMPE[n]=0) a read access to the result register will cause the associated CCF[n] ﬂag to clear automatically. For compare enabled (CMPE[n]=1) a write access to the result register will cause the associated CCF[n] ﬂag to clear automatically. Reserved Do not alter this bit from its reset value.It is for Manufacturer use only and can change the ATD behavior. ETRIGLE External Trigger Level/Edge Control — This bit controls the sensitivity of the external trigger signal. See Table 12-7 for details. ETRIGP External Trigger Polarity— This bit controls the polarity of the external trigger signal. SeeTable 12-7for details. ETRIGE External Trigger Mode Enable— This bit enables the external trigger on one of the AD channels or one of the ETRIG3-0 inputs as described in Table 12-5. If the external trigger source is one of the AD channels, the digital input buffer of this channel is enabled. The external trigger allows to synchronize the start of conversion with external events. ATD Sequence Complete Interrupt Enable 0 ATD Sequence Complete interrupt requests are disabled. 1 ATD Sequence Complete interrupt will be requested whenever SCF=1 is set. ACMPIE ATD Compare Interrupt Enable— If automatic compare is enabled for conversion n (CMPE[n]=1 in ATDCMPE register) this bit enables the compare interrupt. If the CCF[n] ﬂag is set (showing a successful compare for conversion n), the compare interrupt is triggered. 0 ATD Compare interrupt requests are disabled. Interrupt will be requested whenever any of the respective CCF ﬂags is set.

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12.3.2.4 ATD Control Register 3 (ATDCTL3)

Writes to this register will abort current conversion sequence. Read: Anytime Write: Anytime Table 12-7. External Trigger Conﬁgurations ETRIGLE ETRIGP External Trigger Sensitivity 0 0 Falling edge 0 1 Rising edge 1 0 Low level 1 1 High level Module Base + 0x0003 76543210 R DJM S8C S4C S2C S1C FIFO FRZ1 FRZ0 W Reset 0 0 1 00000 = Unimplemented or Reserved Figure 12-6. ATD Control Register 3 (ATDCTL3) Table 12-8. ATDCTL3 Field Descriptions Field Description DJM Result Register Data Justiﬁcation — Result data format is always unsigned. This bit controls justiﬁcation of conversion data in the result registers. 0 Left justiﬁed data in the result registers. 1 Right justiﬁed data in the result registers. Table 12-9 gives example ATD results for an input signal range between 0 and 5.12 Volts. 6–3 S8C, S4C, S2C, S1C Conversion Sequence Length — These bits control the number of conversions per sequence. Table 12-10 shows all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity to HC12 family.

Analog-to-Digital Converter (ADC10B12CV2) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 403 FIFO Result Register FIFO Mode— If this bit is zero (non-FIFO mode), the A/D conversion results map into the result registers based on the conversion sequence; the result of the ﬁrst conversion appears in the ﬁrst result register (ATDDR0), the second result in the second result register (ATDDR1), and so on. If this bit is one (FIFO mode) the conversion counter is not reset at the beginning or end of a conversion sequence; sequential conversion results are placed in consecutive result registers. In a continuously scanning conversion sequence, the result register counter will wrap around when it reaches the end of the result register ﬁle. The conversion counter value (CC3-0 in ATDSTAT0) can be used to determine where in the result register ﬁle, the current conversion result will be placed. Aborting a conversion or starting a new conversion clears the conversion counter even if FIFO=1. So the ﬁrst result of a new conversion sequence, started by writing to ATDCTL5, will always be place in the ﬁrst result register (ATDDDR0). Intended usage of FIFO mode is continuos conversion (SCAN=1) or triggered conversion (ETRIG=1). Which result registers hold valid data can be tracked using the conversion complete ﬂags. Fast ﬂag clear mode may be useful in a particular application to track valid data. If this bit is one, automatic compare of result registers is always disabled, that is ADC10B12C will behave as if ACMPIE and all CPME[n] were zero. 0 Conversion results are placed in the corresponding result register up to the selected sequence length. 1 Conversion results are placed in consecutive result registers (wrap around at end). 1–0 FRZ[1:0] Background Debug Freeze Enable — When debugging an application, it is useful in many cases to have the ATD pause when a breakpoint (Freeze Mode) is encountered. These 2 bits determine how the ATD will respond to a breakpoint as shown in Table 12-11. Leakage onto the storage node and comparator reference capacitors may compromise the accuracy of an immediately frozen conversion depending on the length of the freeze period. Table 12-9. Examples of ideal decimal ATD Results Input Signal VRL = 0 Volts VRH = 5.12 Volts 8-Bit Codes (resolution=20mV) 10-Bit Codes (resolution=5mV) ... 0.022 0.020 0.018 0.016 0.014 0.012 0.010 0.008 0.006 0.004 0.003 0.002 0.000 255 ... 1023 ... Table 12-8. ATDCTL3 Field Descriptions (continued) Field Description

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12.3.2.5 ATD Control Register 4 (ATDCTL4)

Writes to this register will abort current conversion sequence. Read: Anytime Write: Anytime Table 12-10. Conversion Sequence Length Coding S8C S4C S2C S1C Number of Conversions per Sequence 00 0 0 1 2 00 0 1 1 00 1 0 2 00 1 1 3 01 0 0 4 01 0 1 5 01 1 0 6 01 1 1 7 10 0 0 8 10 0 1 9 10 1 0 1 0 10 1 1 1 1 11 0 0 1 2 11 0 1 1 2 11 1 0 1 2 11 1 1 1 2 Table 12-11. ATD Behavior in Freeze Mode (Breakpoint) FRZ1 FRZ0 Behavior in Freeze Mode 0 0 Continue conversion 0 1 Reserved 1 0 Finish current conversion, then freeze 1 1 Freeze Immediately Module Base + 0x0004 76543210 R SMP2 SMP1 SMP0 PRS[4:0] W Reset 0 0 0 00101 Figure 12-7. ATD Control Register 4 (ATDCTL4)

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12.3.2.6 ATD Control Register 5 (ATDCTL5)

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Table 12-14. ATDCTL5 Field Descriptions Field Description SC Special Channel Conversion Bit— If this bit is set, then special channel conversion can be selected using CD, CC, CB and CA of ATDCTL5.Table 12-15 lists the coding. Continuous Conversion Sequence Mode — This bit selects whether conversion sequences are performed continuously or only once. If the external trigger function is enabled (ETRIGE=1) setting this bit has no effect, thus the external trigger always starts a single conversion sequence. Multi-Channel Sample Mode— When MULT is 0, the ATD sequence controller samples only from the speciﬁed analog input channel for an entire conversion sequence. The analog channel is selected by channel selection code (control bits CD/CC/CB/CA located in ATDCTL5). When MULT is 1, the ATD sequence controller samples across channels. The number of channels sampled is determined by the sequence length value (S8C, S4C, S2C, S1C). The ﬁrst analog channel examined is determined by channel selection code (CD, CC, CB, CA control bits); subsequent channels sampled in the sequence are determined by incrementing the channel selection code or wrapping around to AN0 (channel 0). 3–0 CD, CC, CB, CA Analog Input Channel Select Code — These bits select the analog input channel(s). Table 12-15 lists the coding used to select the various analog input channels. In the case of single channel conversions (MULT=0), this selection code speciﬁes the channel to be examined. In the case of multiple channel conversions (MULT=1), this selection code speciﬁes the ﬁrst channel to be examined in the conversion sequence. Subsequent channels are determined by incrementing the channel selection code or wrapping around to AN0 (after converting the channel deﬁned by the Wrap Around Channel Select Bits WRAP3-0 in ATDCTL0). When starting with a channel number higher than the one deﬁned by WRAP3-0 the ﬁrst wrap around will be AN11 to AN0.

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12.3.2.7 ATD Status Register 0 (ATDSTAT0)

This register contains the Sequence Complete Flag, overrun ﬂags for external trigger and FIFO mode, and the conversion counter. Table 12-15. Analog Input Channel Select Coding SC CD CC CB CA Analog Input Channel 1 0 0 0 0 Internal_6, 0 0 0 1 Internal_7 0 0 1 0 Internal_0 0 0 1 1 Internal_1 0 1 1 0 (VRH+VRL) / 2 0 1 1 1 Reserved 1 0 0 0 Internal_2 1 0 0 1 Internal_3 1 0 1 0 Internal_4 1 0 1 1 Internal_5 1 1 X X Reserved

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Read: Anytime Write: Anytime (No effect on (CC3, CC2, CC1, CC0)) Module Base + 0x0006 76543210 R SCF ETORF FIFOR CC3 CC2 CC1 CC0 W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 12-9. ATD Status Register 0 (ATDSTAT0) Table 12-16. ATDSTAT0 Field Descriptions Field Description SCF Sequence Complete Flag — This ﬂag is set upon completion of a conversion sequence. If conversion sequences are continuously performed (SCAN=1), the ﬂag is set after each one is completed. This ﬂag is cleared when one of the following occurs: A) Write “1” to SCF B) Write to ATDCTL5 (a new conversion sequence is started) C) If AFFC=1 and a result register is read External Trigger Overrun Flag — While in edge sensitive mode (ETRIGLE=0), if additional active edges are detected while a conversion sequence is in process the overrun ﬂag is set. This ﬂag is cleared when one of the following occurs: A) Write “1” to ETORF B) Write to ATDCTL0,1,2,3,4, ATDCMPE or ATDCMPHT (a conversion sequence is aborted) C) Write to ATDCTL5 (a new conversion sequence is started) Result Register Overrun Flag— This bit indicates that a result register has been written to before its associated conversion complete ﬂag (CCF) has been cleared. This ﬂag is most useful when using the FIFO mode because the ﬂag potentially indicates that result registers are out of sync with the input channels. However, it is also practical for non-FIFO modes, and indicates that a result register has been overwritten before it has been read (i.e. the old data has been lost). This ﬂag is cleared when one of the following occurs: A) Write “1” to FIFOR B) Write to ATDCTL0,1,2,3,4, ATDCMPE or ATDCMPHT (a conversion sequence is aborted) C) Write to ATDCTL5 (a new conversion sequence is started) 3–0 CC[3:0] Conversion Counter — These 4 read-only bits are the binary value of the conversion counter. The conversion counter points to the result register that will receive the result of the current conversion. E.g. CC3=0, CC2=1, CC1=1, CC0=0 indicates that the result of the current conversion will be in ATD Result Register 6. If in non-FIFO mode (FIFO=0) the conversion counter is initialized to zero at the beginning and end of the conversion sequence. If in FIFO mode (FIFO=1) the register counter is not initialized. The conversion counter wraps around when its maximum value is reached. Aborting a conversion or starting a new conversion clears the conversion counter even if FIFO=1.

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12.3.2.8 ATD Compare Enable Register (ATDCMPE)

Writes to this register will abort current conversion sequence. Read: Anytime Write: Anytime

12.3.2.9 ATD Status Register 2 (ATDSTAT2)

This read-only register contains the Conversion Complete Flags CCF[11:0]. Read: Anytime Write: Anytime, no effect Module Base + 0x0008 15 14 13 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 CMPE[11:0] W Reset 0 0 0 0 0 0 0 0 0 0000000 = Unimplemented or Reserved Figure 12-10. ATD Compare Enable Register (ATDCMPE) Table 12-17. ATDCMPE Field Descriptions Field Description 11–0 CMPE[11:0] Compare Enable for Conversion Numbern (n= 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) of a Sequence (n conversion number, NOT channel number!)— These bits enable automatic compare of conversion results individually for conversions of a sequence. The sense of each comparison is determined by the CMPHT[n] bit in the ATDCMPHT register. For each conversion number with CMPE[n]=1 do the following: 1) Write compare value to ATDDRn result register 2) Write compare operator with CMPHT[n] in ATDCPMHT register CCF[n] in ATDSTAT2 register will ﬂag individual success of any comparison. 1 Automatic compare of results for conversion n of a sequence is enabled. Module Base + 0x000A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 CCF[11:0] W Reset 0 0 0 0 0 0 0 0 0 0000000 = Unimplemented or Reserved Figure 12-11. ATD Status Register 2 (ATDSTAT2)

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12.3.2.10 ATD Input Enable Register (ATDDIEN)

Read: Anytime Write: Anytime Table 12-18. ATDSTAT2 Field Descriptions Field Description 11–0 CCF[11:0] Conversion Complete Flag n (n= 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) (n conversion number, NOT channel number!)— A conversion complete ﬂag is set at the end of each conversion in a sequence. The ﬂags are associated with the conversion position in a sequence (and also the result register number). Therefore in non-ﬁfo mode, CCF[4] is set when the ﬁfth conversion in a sequence is complete and the result is available in result register ATDDR4; CCF[5] is set when the sixth conversion in a sequence is complete and the result is available in ATDDR5, and so forth. If automatic compare of conversion results is enabled (CMPE[n]=1 in ATDCMPE), the conversion complete ﬂag is only set if comparison with ATDDRn is true. If ACMPIE=1 a compare interrupt will be requested. In this case, as the ATDDRn result register is used to hold the compare value, the result will not be stored there at the end of the conversion but is lost. A ﬂag CCF[n] is cleared when one of the following occurs: A) Write to ATDCTL5 (a new conversion sequence is started) B) If AFFC=0, write “1” to CCF[n] C) If AFFC=1 and CMPE[n]=0, read of result register ATDDRn D) If AFFC=1 and CMPE[n]=1, write to result register ATDDRn In case of a concurrent set and clear on CCF[n]: The clearing by method A) will overwrite the set. The clearing by methods B) or C) or D) will be overwritten by the set. 1 If (CMPE[ n]=0): Conversion number n has completed. Result is ready in ATDDRn. If (CMPE[n]=1): Compare for conversion result number n with compare value in ATDDRn, using compare operator CMPGT[n] is true. (No result available in ATDDRn) Module Base + 0x000C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 1 1 1 1 IEN[11:0] W Reset 1 1 1 1 0 0 0 0 0 0000000 = Unimplemented or Reserved Figure 12-12. ATD Input Enable Register (ATDDIEN) Table 12-19. ATDDIEN Field Descriptions Field Description 11–0 IEN[11:0] ATD Digital Input Enable on channelx (x= 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0)— This bit controls the digital input buffer from the analog input pin (ANx) to the digital data register. 1 Enable digital input buffer on AN x pin. Note: Setting this bit will enable the corresponding digital input buffer continuously. If this bit is set while simultaneously using it as an analog port, there is potentially increased power consumption because the digital input buffer maybe in the linear region.

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12.3.2.11 ATD Compare Higher Than Register (ATDCMPHT)

Writes to this register will abort current conversion sequence. Read: Anytime Write: Anytime

12.3.2.12 ATD Conversion Result Registers (ATDDR n)

The A/D conversion results are stored in 12 result registers. Results are always in unsigned data representation. Left and right justiﬁcation is selected using the DJM control bit in ATDCTL3. If automatic compare of conversions results is enabled (CMPE[n]=1 in ATDCMPE), these registers must be written with the compare values in left or right justiﬁed format depending on the actual value of the DJM bit. In this case, as the ATDDRn register is used to hold the compare value, the result will not be stored there at the end of the conversion but is lost. Attention, n is the conversion number, NOT the channel number! Read: Anytime Write: Anytime NOTE For conversions not using automatic compare, results are stored in the result registers after each conversion. In this case avoid writing to ATDDRn except for initial values, because an A/D result might be overwritten.

12.3.2.12.1 Left Justiﬁed Result Data (DJM=0)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 CMPHT[11:0] W Reset 0 0 0 0 0 0 0 0 0 0000000 = Unimplemented or Reserved Figure 12-13. ATD Compare Higher Than Register (ATDCMPHT) Table 12-20. ATDCMPHT Field Descriptions Field Description 11–0 CMPHT[11:0] Compare Operation Higher Than Enable for conversion numbern (n= 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) of a Sequence (n conversion number, NOT channel number!)— This bit selects the operator for comparison of conversion results.

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Table 12-21 shows how depending on the A/D resolution the conversion result is transferred to the ATD result registers for left justiﬁed data. Compare is always done using all 12 bits of both the conversion result and the compare value in ATDDRn. Table 12-21. Conversion result mapping to ATDDRn

12.3.2.12.2 Right Justiﬁed Result Data (DJM=1)

Table 12-22 shows how depending on the A/D resolution the conversion result is transferred to the ATD result registers for right justiﬁed data. Compare is always done using all 12 bits of both the conversion result and the compare value in ATDDRn. Module Base + 0x0010 = ATDDR0, 0x0012 = ATDDR1, 0x0014 = ATDDR2, 0x0016 = ATDDR3 0x0018 = ATDDR4, 0x001A = ATDDR5, 0x001C = ATDDR6, 0x001E = ATDDR7 0x0020 = ATDDR8, 0x0022 = ATDDR9, 0x0024 = ATDDR10, 0x0026 = ATDDR11 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Result-Bit[11:0] 0 000 W Reset 0 0 0 0 0 0 0 0 0 0000000 = Unimplemented or Reserved Figure 12-14. Left justiﬁed ATD conversion result register (ATDDRn) A/D resolution DJM conversion result mapping to ATDDRn 8-bit data 0 Result-Bit[11:4] = conversion result, Result-Bit[3:0]=0000 10-bit data 0 Result-Bit[11:2] = conversion result, Result-Bit[1:0]=00 Module Base + 0x0010 = ATDDR0, 0x0012 = ATDDR1, 0x0014 = ATDDR2, 0x0016 = ATDDR3 0x0018 = ATDDR4, 0x001A = ATDDR5, 0x001C = ATDDR6, 0x001E = ATDDR7 0x0020 = ATDDR8, 0x0022 = ATDDR9, 0x0024 = ATDDR10, 0x0026 = ATDDR11 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 000 Result-Bit[11:0] W Reset 0 0 0 0 0 0 0 0 0 0000000 = Unimplemented or Reserved Figure 12-15. Right justiﬁed ATD conversion result register (ATDDRn)

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12.4 Functional Description

The ADC10B12C consists of an analog sub-block and a digital sub-block.

12.4.1 Analog Sub-Block

12.4.1.1 Sample and Hold Machine

12.4.1.2 Analog Input Multiplexer

The analog input multiplexer connects one of the 8 external analog input channels to the sample and hold machine.

12.4.1.3 Analog-to-Digital (A/D) Machine

The A/D Machine performs analog to digital conversions. The resolution is program selectable to be either 8 or 10 bits. The A/D machine uses a successive approximation architecture. It functions by comparing the sampled and stored analog voltage with a series of binary coded discrete voltages. By following a binary search algorithm, the A/D machine identiﬁes the discrete voltage that is nearest to the sampled and stored voltage. When not converting the A/D machine is automatically powered down. Only analog input signals within the potential range of VRL to VRH (A/D reference potentials) will result in a non-railed digital output code. Table 12-22. Conversion result mapping to ATDDRn A/D resolution DJM conversion result mapping to ATDDRn 8-bit data 1 Result-Bit[11:8]=0000, Result-Bit[7:0] = conversion result 10-bit data 1 Result-Bit[11:10]=00, Result-Bit[9:0] = conversion result

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12.4.2 Digital Sub-Block

This subsection describes some of the digital features in more detail. See Section 12.3.2, “Register Descriptions” for all details.

12.4.2.1 External Trigger Input

The external trigger feature allows the user to synchronize ATD conversions to an external event rather than relying only on software to trigger the ATD module when a conversions is about to take place. The external trigger signal (out of reset ATD channel 11, conﬁgurable in ATDCTL1) is programmable to be edge or level sensitive with polarity control. Table 12-23 gives a brief description of the different combinations of control bits and their effect on the external trigger function. In either level or edge sensitive modes, the ﬁrst conversion begins when the trigger is received. Once ETRIGE is enabled a conversion must be triggered externally after writing to ATDCTL5 register. During a conversion in edge sensitive mode, if additional trigger events are detected the overrun error ﬂag ETORF is set. If level sensitive mode is active and the external trigger de-asserts and later asserts again during a conversion sequence, this does not constitute an overrun. Therefore, the ﬂag is not set. If the trigger is left active in level sensitive mode when a sequence is about to complete, another sequence will be triggered immediately. Table 12-23. External Trigger Control Bits ETRIGLE ETRIGP ETRIGE SCAN Description X X 0 0 Ignores external trigger. Performs one conversion sequence and stops. X X 0 1 Ignores external trigger. Performs continuous conversion sequences. 0 0 1 X Trigger falling edge sensitive. Performs one conversion sequence per trigger. 0 1 1 X Trigger rising edge sensitive. Performs one conversion sequence per trigger. 1 0 1 X Trigger low level sensitive. Performs continuous conversions while trigger level is active. 1 1 1 X Trigger high level sensitive. Performs continuous conversions while trigger level is active.

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12.4.2.2 General-Purpose Digital Port Operation

12.5 Resets

At reset the ADC10B12C is in a power down state. The reset state of each individual bit is listed within the Register Description section (see Section 12.3.2, “Register Descriptions”) which details the registers and their bit-ﬁeld.

12.6 Interrupts

The interrupts requested by the ADC10B12C are listed in Table 12-24. Refer to MCU speciﬁcation for related vector address and priority. See Section 12.3.2, “Register Descriptions” for further details. Table 12-24. ATD Interrupt Vectors Interrupt Source CCR Mask Local Enable Sequence Complete Interrupt I bit ASCIE in ATDCTL2 Compare Interrupt I bit ACMPIE in ATDCTL2

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MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 417 Chapter 13 Analog-to-Digital Converter (ADC10B16CV2)

13.1 Introduction

The ADC10B16C is a 16-channel, , multiplexed input successive approximation analog-to-digital converter. Refer to device electrical speciﬁcations for ATD accuracy.

13.1.1 Features

8-, 10-bit resolution. Version Number Revision Date Effective Date Author Description of Changes V02.00 18 June 2009 18 June 2009 Initial version copied 12 channel block guide V02.01 09 Feb 2010 09 Feb 2010 Updated Table 13-15 Analog Input Channel Select Coding - description of internal channels. Updated register ATDDR (left/right justiﬁed result) description added Table 13-21 to improve feature description. Fixed typo in Table 13-9- conversion result for 3mV and 10bit resolution V02.03 26 Feb 2010 26 Feb 2010 Corrected Table 13-15Analog Input Channel Select Coding - description of internal channels. V02.04 26 Mar 2010 16 Mar 2010 Corrected typo: Reset value of ATDDIEN register V02.05 14 Apr 2010 14 Apr 2010 Corrected typos to be in-line with SoC level pin naming conventions for VDDA, VSSA, VRL and VRH. V02.06 25 Aug 2010 25 Aug 2010 Removed feature of conversion during STOP and general wording clean up done in Section 13.4, “Functional

v02.07 09 Sep 2010 09 Sep 2010 Update of internal only information. V02.08 11 Feb 2011 11 Feb 2011 Connectivity Information regarding internal channel_6 added to Table 13-15. V02.09 29 Mar 2011 29 Mar 2011 Fixed typo in bit description ﬁeld Table 13-14for bits CD, CC, CB, CA. Last sentence contained a wrong highest channel number (it is not AN7 to AN0 instead it is AN15 to AN0).

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Automatic return to low power after conversion sequence
Automatic compare with interrupt for higher than or less/equal than programmable value
Programmable sample time.
Left/right justiﬁed result data.
External trigger control.
Sequence complete interrupt.
Analog input multiplexer for 8 analog input channels.
Special conversions for VRH, VRL, (VRL+VRH)/2.
1-to-16 conversion sequence lengths.
Continuous conversion mode.
Multiple channel scans.
Conﬁgurable external trigger functionality on any AD channel or any of four additional trigger inputs. The four additional trigger inputs can be chip external or internal. Refer to device speciﬁcation for availability and connectivity.
Conﬁgurable location for channel wrap around (when converting multiple channels in a sequence).

13.1.2 Modes of Operation

13.1.2.1 Conversion Modes

There is software programmable selection between performing single or continuous conversion on a single channel or multiple channels.

13.1.2.2 MCU Operating Modes

Stop Mode Entering Stop Mode aborts any conversion sequence in progress and if a sequence was aborted restarts it after exiting stop mode. This has the same effect/consequences as starting a conversion sequence with write to ATDCTL5. So after exiting from stop mode with a previously aborted sequence all ﬂags are cleared etc.
Wait Mode ADC10B16C behaves same in Run and Wait Mode. For reduced power consumption continuous conversions should be aborted before entering Wait mode.
Freeze Mode In Freeze Mode the ADC10B16C will either continue or ﬁnish or stop converting according to the FRZ1 and FRZ0 bits. This is useful for debugging and emulation.

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13.1.3 Block Diagram

Figure 13-1. ADC10B16C Block Diagram VSSA AN9 ATD_12B12C Analog MUX Mode and Successive Approximation Register (SAR) Results ATD 0 ATD 1 ATD 2 ATD 3 ATD 4 ATD 5 ATD 6 ATD 7 and DAC Sample & Hold VDDA VRL VRH Sequence Complete Comparator Clock Prescaler Bus Clock ATD Clock AN7 AN6 AN5 AN10 ETRIG0 (See device speciﬁ- cation for availability ETRIG1 ETRIG2 ETRIG3 and connectivity) Timing Control ATDDIENATDCTL1 Trigger Mux Interrupt Compare Interrupt AN4 AN11 AN12 AN13 AN14 ATD 8 ATD 9 ATD 10 ATD 11 ATD 13 ATD 14 ATD 12 ATD 15 AN3 AN2 AN1 AN0 AN8 AN15

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13.2 Signal Description

This section lists all inputs to the ADC10B16C block.

13.2.1 Detailed Signal Descriptions

This pin serves as the analog input Channel x. It can also be conﬁgured as digital port or external trigger for the ATD conversion.

13.2.1.2 ETRIG3, ETRIG2, ETRIG1, ETRIG0

These inputs can be conﬁgured to serve as an external trigger for the ATD conversion. Refer to device speciﬁcation for availability and connectivity of these inputs!

13.2.1.3 VRH, VRL

VRH is the high reference voltage, VRL is the low reference voltage for ATD conversion.

13.2.1.4 VDDA, VSSA

These pins are the power supplies for the analog circuitry of the ADC10B16C block.

13.3 Memory Map and Register Deﬁnition

This section provides a detailed description of all registers accessible in the ADC10B16C.

13.3.1 Module Memory Map

Figure 13-2 gives an overview on all ADC10B16C registers. NOTE Register Address = Base Address + Address Offset, where the Base Address is deﬁned at the MCU level and the Address Offset is deﬁned at the module level. Address Name Bit 7 6 5 4 3 2 1 Bit 0 0x0000 ATDCTL0 R Reserved 000 WRAP3 WRAP2 WRAP1 WRAP0W 0x0001 ATDCTL1 R ETRIGSEL SRES1 SRES0 SMP_DIS ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0W 0x0002 ATDCTL2 R0 AFFC Reserved ETRIGLE ETRIGP ETRIGE ASCIE ACMPIEW = Unimplemented or Reserved Figure 13-2. ADC10B16C Register Summary (Sheet 1 of 3)

Analog-to-Digital Converter (ADC10B16CV2) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 421 0x0003 ATDCTL3 R DJM S8C S4C S2C S1C FIFO FRZ1 FRZ0W 0x0004 ATDCTL4 R SMP2 SMP1 SMP0 PRS[4:0]W 0x0005 ATDCTL5 R0 SC SCAN MULT CD CC CB CAW 0x0006 ATDSTAT0 R SCF 0 ETORF FIFOR CC3 CC2 CC1 CC0 W 0x0007 Unimple- mented R 0 000 0 0 0 0 W 0x0008 ATDCMPEH R CMPE[15:8]W 0x0009 ATDCMPEL R CMPE[7:0]W 0x000A ATDSTAT2H R CCF[15:8] W 0x000B ATDSTAT2L R CCF[7:0] W 0x000C ATDDIENH R IEN[15:8]W 0x000D ATDDIENL R IEN[7:0]W 0x000E ATDCMPHTH R CMPHT[15:8]W 0x000F ATDCMPHTL R CMPHT[7:0]W 0x0010 ATDDR0 R See Section 13.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” and Section 13.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”W 0x0012 ATDDR1 R See Section 13.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” and Section 13.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”W 0x0014 ATDDR2 R See Section 13.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” and Section 13.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”W 0x0016 ATDDR3 R See Section 13.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” and Section 13.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”W 0x0018 ATDDR4 R See Section 13.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” and Section 13.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”W 0x001A ATDDR5 R See Section 13.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” and Section 13.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”W 0x001C ATDDR6 R See Section 13.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” and Section 13.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”W 0x001E ATDDR7 R See Section 13.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” and Section 13.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”W 0x0020 ATDDR8 R See Section 13.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” and Section 13.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”W 0x0022 ATDDR9 R See Section 13.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” and Section 13.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”W Address Name Bit 7 6 5 4 3 2 1 Bit 0 = Unimplemented or Reserved Figure 13-2. ADC10B16C Register Summary (Sheet 2 of 3)

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13.3.2 Register Descriptions

This section describes in address order all the ADC10B16C registers and their individual bits.

13.3.2.1 ATD Control Register 0 (ATDCTL0)

Writes to this register will abort current conversion sequence. Read: Anytime Write: Anytime, in special modes always write 0 to Reserved Bit 7. 0x0024 ATDDR10 R See Section 13.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” and Section 13.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”W 0x0026 ATDDR11 R See Section 13.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” and Section 13.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”W 0x0028 ATDDR12 R See Section 13.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” and Section 13.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”W 0x002A ATDDR13 R See Section 13.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” and Section 13.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”W 0x002C ATDDR14 R See Section 13.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” and Section 13.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”W 0x002E ATDDR15 R See Section 13.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” and Section 13.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”W W Module Base + 0x0000 76543210 R Reserved 000 WRAP3 WRAP2 WRAP1 WRAP0 W Reset 0 0 0 01111 = Unimplemented or Reserved Figure 13-3. ATD Control Register 0 (ATDCTL0) Table 13-1. ATDCTL0 Field Descriptions Field Description 3-0 WRAP[3-0] Wrap Around Channel Select Bits — These bits determine the channel for wrap around when doing multi-channel conversions. The coding is summarized in Table 13-2. Address Name Bit 7 6 5 4 3 2 1 Bit 0 = Unimplemented or Reserved Figure 13-2. ADC10B16C Register Summary (Sheet 3 of 3)

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13.3.2.2 ATD Control Register 1 (ATDCTL1)

Writes to this register will abort current conversion sequence. Read: Anytime Write: Anytime Table 13-2. Multi-Channel Wrap Around Coding WRAP3 WRAP2 WRAP1 WRAP0 Multiple Channel Conversions (MULT = 1) Wraparound to AN0 after Converting 1If only AN0 should be converted use MULT=0.

1100 AN12

1101 AN13

1110 AN14

1111 AN15

R ETRIGSEL SRES1 SRES0 SMP_DIS ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0 W Reset 0 0 1 01111 Figure 13-4. ATD Control Register 1 (ATDCTL1)

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Table 13-3. ATDCTL1 Field Descriptions Field Description ETRIGSEL External Trigger Source Select — This bit selects the external trigger source to be either one of the AD channels or one of the ETRIG3-0 inputs. See device speciﬁcation for availability and connectivity of ETRIG3-0 inputs. If a particular ETRIG3-0 input option is not available, writing a 1 to ETRISEL only sets the bit but has no effect, this means that one of the AD channels (selected by ETRIGCH3-0) is conﬁgured as the source for external trigger. The coding is summarized in Table 13-5. 6–5 SRES[1:0] A/D Resolution Select — These bits select the resolution of A/D conversion results. See Table 13-4 for coding. SMP_DIS Discharge Before Sampling Bit 0 No discharge before sampling. 1 The internal sample capacitor is discharged before sampling the channel. This adds 2 ATD clock cycles to the sampling time. This can help to detect an open circuit instead of measuring the previous sampled channel. 3–0 ETRIGCH[3:0] External Trigger Channel Select— These bits select one of the AD channels or one of the ETRIG3-0 inputs as source for the external trigger. The coding is summarized in Table 13-5. Table 13-4. A/D Resolution Coding SRES1 SRES0 A/D Resolution 0 0 8-bit data 0 1 10-bit data 1 1 Reserved Table 13-5. External Trigger Channel Select Coding ETRIGSEL ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0 External trigger source is 0 0 0 0 0 AN0 0 0 0 0 1 AN1 0 0 0 1 0 AN2 0 0 0 1 1 AN3 0 0 1 0 0 AN4 0 0 1 0 1 AN5 0 0 1 1 0 AN6 0 0 1 1 1 AN7 0 1 0 0 0 AN8 0 1 0 0 1 AN9 0 1 0 1 0 AN10 0 1 0 1 1 AN11 0 1 1 0 0 AN12 0 1 1 0 1 AN13 0 1 1 1 0 AN14 0 1 1 1 1 AN15 1 0 0 0 0 ETRIG0 1 0 0 0 1 ETRIG1 1

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13.3.2.3 ATD Control Register 2 (ATDCTL2)

Writes to this register will abort current conversion sequence. Read: Anytime Write: Anytime 1 0 0 1 0 ETRIG2 1 1 0 0 1 1 ETRIG3 1 1 0 1 X X Reserved 1 1 X X X Reserved 1 Only if ETRIG3-0 input option is available (see device speciﬁcation), else ETRISEL is ignored, that means external trigger source is still on one of the AD channels selected by ETRIGCH3-0 Module Base + 0x0002 76543210 AFFC Reserved ETRIGLE ETRIGP ETRIGE ASCIE ACMPIE W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 13-5. ATD Control Register 2 (ATDCTL2) Table 13-6. ATDCTL2 Field Descriptions Field Description AFFC ATD Fast Flag Clear All 0 ATD ﬂag clearing done by write 1 to respective CCF[ n] ﬂag. 1 Changes all ATD conversion complete ﬂags to a fast clear sequence. For compare disabled (CMPE[n]=0) a read access to the result register will cause the associated CCF[n] ﬂag to clear automatically. For compare enabled (CMPE[n]=1) a write access to the result register will cause the associated CCF[n] ﬂag to clear automatically. Reserved Do not alter this bit from its reset value.It is for Manufacturer use only and can change the ATD behavior. ETRIGLE External Trigger Level/Edge Control — This bit controls the sensitivity of the external trigger signal. See Table 13-7 for details. ETRIGP External Trigger Polarity— This bit controls the polarity of the external trigger signal. SeeTable 13-7for details. ETRIGE External Trigger Mode Enable— This bit enables the external trigger on one of the AD channels or one of the ETRIG3-0 inputs as described in Table 13-5. If the external trigger source is one of the AD channels, the digital input buffer of this channel is enabled. The external trigger allows to synchronize the start of conversion with external events. Table 13-5. External Trigger Channel Select Coding ETRIGSEL ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0 External trigger source is

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13.3.2.4 ATD Control Register 3 (ATDCTL3)

Writes to this register will abort current conversion sequence. Read: Anytime Write: Anytime ASCIE ATD Sequence Complete Interrupt Enable 0 ATD Sequence Complete interrupt requests are disabled. 1 ATD Sequence Complete interrupt will be requested whenever SCF=1 is set. ACMPIE ATD Compare Interrupt Enable— If automatic compare is enabled for conversion n (CMPE[n]=1 in ATDCMPE register) this bit enables the compare interrupt. If the CCF[n] ﬂag is set (showing a successful compare for conversion n), the compare interrupt is triggered. 0 ATD Compare interrupt requests are disabled. Interrupt will be requested whenever any of the respective CCF ﬂags is set. Table 13-7. External Trigger Conﬁgurations ETRIGLE ETRIGP External Trigger Sensitivity 0 0 Falling edge 0 1 Rising edge 1 0 Low level 1 1 High level Module Base + 0x0003 76543210 R DJM S8C S4C S2C S1C FIFO FRZ1 FRZ0 W Reset 0 0 1 00000 = Unimplemented or Reserved Figure 13-6. ATD Control Register 3 (ATDCTL3) Table 13-6. ATDCTL2 Field Descriptions (continued) Field Description

Analog-to-Digital Converter (ADC10B16CV2) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 427 Table 13-8. ATDCTL3 Field Descriptions Field Description DJM Result Register Data Justiﬁcation — Result data format is always unsigned. This bit controls justiﬁcation of conversion data in the result registers. 0 Left justiﬁed data in the result registers. 1 Right justiﬁed data in the result registers. Table 13-9 gives example ATD results for an input signal range between 0 and 5.12 Volts. 6–3 S8C, S4C, S2C, S1C Conversion Sequence Length — These bits control the number of conversions per sequence. Table 13-10 shows all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity to HC12 family. FIFO Result Register FIFO Mode— If this bit is zero (non-FIFO mode), the A/D conversion results map into the result registers based on the conversion sequence; the result of the ﬁrst conversion appears in the ﬁrst result register (ATDDR0), the second result in the second result register (ATDDR1), and so on. If this bit is one (FIFO mode) the conversion counter is not reset at the beginning or end of a conversion sequence; sequential conversion results are placed in consecutive result registers. In a continuously scanning conversion sequence, the result register counter will wrap around when it reaches the end of the result register ﬁle. The conversion counter value (CC3-0 in ATDSTAT0) can be used to determine where in the result register ﬁle, the current conversion result will be placed. Aborting a conversion or starting a new conversion clears the conversion counter even if FIFO=1. So the ﬁrst result of a new conversion sequence, started by writing to ATDCTL5, will always be place in the ﬁrst result register (ATDDDR0). Intended usage of FIFO mode is continuos conversion (SCAN=1) or triggered conversion (ETRIG=1). Which result registers hold valid data can be tracked using the conversion complete ﬂags. Fast ﬂag clear mode may be useful in a particular application to track valid data. If this bit is one, automatic compare of result registers is always disabled, that is ADC10B16C will behave as if ACMPIE and all CPME[n] were zero. 0 Conversion results are placed in the corresponding result register up to the selected sequence length. 1 Conversion results are placed in consecutive result registers (wrap around at end). 1–0 FRZ[1:0] Background Debug Freeze Enable — When debugging an application, it is useful in many cases to have the ATD pause when a breakpoint (Freeze Mode) is encountered. These 2 bits determine how the ATD will respond to a breakpoint as shown in Table 13-11. Leakage onto the storage node and comparator reference capacitors may compromise the accuracy of an immediately frozen conversion depending on the length of the freeze period.

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Table 13-9. Examples of ideal decimal ATD Results Input Signal VRL = 0 Volts VRH = 5.12 Volts 8-Bit Codes (resolution=20mV) 10-Bit Codes (resolution=5mV) ... 0.022 0.020 0.018 0.016 0.014 0.012 0.010 0.008 0.006 0.004 0.003 0.002 0.000 255 ... 1023 ... Table 13-10. Conversion Sequence Length Coding S8C S4C S2C S1C Number of Conversions per Sequence 00 0 0 1 6 00 0 1 1 00 1 0 2 00 1 1 3 01 0 0 4 01 0 1 5 01 1 0 6 01 1 1 7 10 0 0 8 10 0 1 9 10 1 0 1 0 10 1 1 1 1 11 0 0 1 2 11 0 1 1 3 11 1 0 1 4 11 1 1 1 5 Table 13-11. ATD Behavior in Freeze Mode (Breakpoint) FRZ1 FRZ0 Behavior in Freeze Mode 0 0 Continue conversion 0 1 Reserved 1 0 Finish current conversion, then freeze

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13.3.2.5 ATD Control Register 4 (ATDCTL4)

Writes to this register will abort current conversion sequence. Read: Anytime Write: Anytime 1 1 Freeze Immediately Module Base + 0x0004 76543210 R SMP2 SMP1 SMP0 PRS[4:0] W Reset 0 0 0 00101 Figure 13-7. ATD Control Register 4 (ATDCTL4) Table 13-12. ATDCTL4 Field Descriptions Field Description 7–5 SMP[2:0] Sample Time Select — These three bits select the length of the sample time in units of ATD conversion clock cycles. Note that the ATD conversion clock period is itself a function of the prescaler value (bits PRS4-0). Table 13-13 lists the available sample time lengths. 4–0 PRS[4:0] ATD Clock Prescaler— These 5 bits are the binary prescaler value PRS. The ATD conversion clock frequency is calculated as follows: Refer to Device Speciﬁcation for allowed frequency range of f ATDCLK. Table 13-13. Sample Time Select SMP2 SMP1 SMP0 Sample Time in Number of ATD Clock Cycles 000 4 001 6 010 8 011 1 0 100 1 2 101 1 6 110 2 0 111 2 4 Table 13-11. ATD Behavior in Freeze Mode (Breakpoint) FRZ1 FRZ0 Behavior in Freeze Mode fATDCLK fBUS

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13.3.2.6 ATD Control Register 5 (ATDCTL5)

Writes to this register will abort current conversion sequence and start a new conversion sequence. If the external trigger function is enabled (ETRIGE=1) an initial write to ATDCTL5 is required to allow starting of a conversion sequence which will then occur on each trigger event. Start of conversion means the beginning of the sampling phase. Read: Anytime Write: Anytime Module Base + 0x0005 76543210 SC SCAN MULT CD CC CB CA W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 13-8. ATD Control Register 5 (ATDCTL5) Table 13-14. ATDCTL5 Field Descriptions Field Description SC Special Channel Conversion Bit— If this bit is set, then special channel conversion can be selected using CD, CC, CB and CA of ATDCTL5.Table 13-15 lists the coding. Continuous Conversion Sequence Mode — This bit selects whether conversion sequences are performed continuously or only once. If the external trigger function is enabled (ETRIGE=1) setting this bit has no effect, thus the external trigger always starts a single conversion sequence. Multi-Channel Sample Mode— When MULT is 0, the ATD sequence controller samples only from the speciﬁed analog input channel for an entire conversion sequence. The analog channel is selected by channel selection code (control bits CD/CC/CB/CA located in ATDCTL5). When MULT is 1, the ATD sequence controller samples across channels. The number of channels sampled is determined by the sequence length value (S8C, S4C, S2C, S1C). The ﬁrst analog channel examined is determined by channel selection code (CD, CC, CB, CA control bits); subsequent channels sampled in the sequence are determined by incrementing the channel selection code or wrapping around to AN0 (channel 0). 3–0 CD, CC, CB, CA Analog Input Channel Select Code — These bits select the analog input channel(s). Table 13-15 lists the coding used to select the various analog input channels. In the case of single channel conversions (MULT=0), this selection code speciﬁes the channel to be examined. In the case of multiple channel conversions (MULT=1), this selection code speciﬁes the ﬁrst channel to be examined in the conversion sequence. Subsequent channels are determined by incrementing the channel selection code or wrapping around to AN0 (after converting the channel deﬁned by the Wrap Around Channel Select Bits WRAP3-0 in ATDCTL0). When starting with a channel number higher than the one deﬁned by WRAP3-0 the ﬁrst wrap around will be AN16 to AN0.

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13.3.2.7 ATD Status Register 0 (ATDSTAT0)

This register contains the Sequence Complete Flag, overrun ﬂags for external trigger and FIFO mode, and the conversion counter. Table 13-15. Analog Input Channel Select Coding SC CD CC CB CA Analog Input Channel 1 0 0 0 0 Internal_6, 0 0 0 1 Internal_7 0 0 1 0 Internal_0 0 0 1 1 Internal_1 0 1 1 0 (VRH+VRL) / 2 0 1 1 1 Reserved 1 0 0 0 Internal_2 1 0 0 1 Internal_3 1 0 1 0 Internal_4 1 0 1 1 Internal_5 1 1 X X Reserved

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Read: Anytime Write: Anytime (No effect on (CC3, CC2, CC1, CC0)) Module Base + 0x0006 76543210 R SCF ETORF FIFOR CC3 CC2 CC1 CC0 W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 13-9. ATD Status Register 0 (ATDSTAT0) Table 13-16. ATDSTAT0 Field Descriptions Field Description SCF Sequence Complete Flag — This ﬂag is set upon completion of a conversion sequence. If conversion sequences are continuously performed (SCAN=1), the ﬂag is set after each one is completed. This ﬂag is cleared when one of the following occurs: A) Write “1” to SCF B) Write to ATDCTL5 (a new conversion sequence is started) C) If AFFC=1 and a result register is read External Trigger Overrun Flag — While in edge sensitive mode (ETRIGLE=0), if additional active edges are detected while a conversion sequence is in process the overrun ﬂag is set. This ﬂag is cleared when one of the following occurs: A) Write “1” to ETORF B) Write to ATDCTL0,1,2,3,4, ATDCMPE or ATDCMPHT (a conversion sequence is aborted) C) Write to ATDCTL5 (a new conversion sequence is started) Result Register Overrun Flag— This bit indicates that a result register has been written to before its associated conversion complete ﬂag (CCF) has been cleared. This ﬂag is most useful when using the FIFO mode because the ﬂag potentially indicates that result registers are out of sync with the input channels. However, it is also practical for non-FIFO modes, and indicates that a result register has been overwritten before it has been read (i.e. the old data has been lost). This ﬂag is cleared when one of the following occurs: A) Write “1” to FIFOR B) Write to ATDCTL0,1,2,3,4, ATDCMPE or ATDCMPHT (a conversion sequence is aborted) C) Write to ATDCTL5 (a new conversion sequence is started) 3–0 CC[3:0] Conversion Counter — These 4 read-only bits are the binary value of the conversion counter. The conversion counter points to the result register that will receive the result of the current conversion. E.g. CC3=0, CC2=1, CC1=1, CC0=0 indicates that the result of the current conversion will be in ATD Result Register 6. If in non-FIFO mode (FIFO=0) the conversion counter is initialized to zero at the beginning and end of the conversion sequence. If in FIFO mode (FIFO=1) the register counter is not initialized. The conversion counter wraps around when its maximum value is reached. Aborting a conversion or starting a new conversion clears the conversion counter even if FIFO=1.

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13.3.2.8 ATD Compare Enable Register (ATDCMPE)

Writes to this register will abort current conversion sequence. Read: Anytime Write: Anytime

13.3.2.9 ATD Status Register 2 (ATDSTAT2)

This read-only register contains the Conversion Complete Flags CCF[15:0]. Read: Anytime Write: Anytime, no effect Module Base + 0x0008 15 14 13 11 10 9 8 7 6 5 4 3 2 1 0 R CMPE[15:0] W Reset 0 0 0 0 0 0 0 0 0 0000000 = Unimplemented or Reserved Figure 13-10. ATD Compare Enable Register (ATDCMPE) Table 13-17. ATDCMPE Field Descriptions Field Description 15–0 CMPE[15:0] Compare Enable for Conversion Numbern (n= 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) of a Sequence (n conversion number, NOT channel number!)— These bits enable automatic compare of conversion results individually for conversions of a sequence. The sense of each comparison is determined by the CMPHT[n] bit in the ATDCMPHT register. For each conversion number with CMPE[n]=1 do the following: 1) Write compare value to ATDDRn result register 2) Write compare operator with CMPHT[n] in ATDCPMHT register CCF[n] in ATDSTAT2 register will ﬂag individual success of any comparison. 1 Automatic compare of results for conversion n of a sequence is enabled. Module Base + 0x000A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R CCF[15:0] W Reset 0 0 0 0 0 0 0 0 0 0000000 = Unimplemented or Reserved Figure 13-11. ATD Status Register 2 (ATDSTAT2)

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13.3.2.10 ATD Input Enable Register (ATDDIEN)

Read: Anytime Write: Anytime Table 13-18. ATDSTAT2 Field Descriptions Field Description 15–0 CCF[15:0] Conversion Complete Flagn (n= 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) (n conversion number, NOT channel number!)— A conversion complete ﬂag is set at the end of each conversion in a sequence. The ﬂags are associated with the conversion position in a sequence (and also the result register number). Therefore in non-ﬁfo mode, CCF[4] is set when the ﬁfth conversion in a sequence is complete and the result is available in result register ATDDR4; CCF[5] is set when the sixth conversion in a sequence is complete and the result is available in ATDDR5, and so forth. If automatic compare of conversion results is enabled (CMPE[n]=1 in ATDCMPE), the conversion complete ﬂag is only set if comparison with ATDDRn is true. If ACMPIE=1 a compare interrupt will be requested. In this case, as the ATDDRn result register is used to hold the compare value, the result will not be stored there at the end of the conversion but is lost. A ﬂag CCF[n] is cleared when one of the following occurs: A) Write to ATDCTL5 (a new conversion sequence is started) B) If AFFC=0, write “1” to CCF[n] C) If AFFC=1 and CMPE[n]=0, read of result register ATDDRn D) If AFFC=1 and CMPE[n]=1, write to result register ATDDRn In case of a concurrent set and clear on CCF[n]: The clearing by method A) will overwrite the set. The clearing by methods B) or C) or D) will be overwritten by the set. 1 If (CMPE[ n]=0): Conversion number n has completed. Result is ready in ATDDRn. If (CMPE[n]=1): Compare for conversion result number n with compare value in ATDDRn, using compare operator CMPGT[n] is true. (No result available in ATDDRn) Module Base + 0x000C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R IEN[15:0] W Reset 0 0 0 0 0 0 0 0 0 0000000 = Unimplemented or Reserved Figure 13-12. ATD Input Enable Register (ATDDIEN) Table 13-19. ATDDIEN Field Descriptions Field Description 15–0 IEN[15:0] ATD Digital Input Enable on channelx (x= 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0)— This bit controls the digital input buffer from the analog input pin (ANx) to the digital data register. 1 Enable digital input buffer on AN x pin. Note: Setting this bit will enable the corresponding digital input buffer continuously. If this bit is set while simultaneously using it as an analog port, there is potentially increased power consumption because the digital input buffer maybe in the linear region.

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13.3.2.11 ATD Compare Higher Than Register (ATDCMPHT)

Writes to this register will abort current conversion sequence. Read: Anytime Write: Anytime

13.3.2.12 ATD Conversion Result Registers (ATDDR n)

The A/D conversion results are stored in 16 result registers. Results are always in unsigned data representation. Left and right justiﬁcation is selected using the DJM control bit in ATDCTL3. If automatic compare of conversions results is enabled (CMPE[n]=1 in ATDCMPE), these registers must be written with the compare values in left or right justiﬁed format depending on the actual value of the DJM bit. In this case, as the ATDDRn register is used to hold the compare value, the result will not be stored there at the end of the conversion but is lost. Attention, n is the conversion number, NOT the channel number! Read: Anytime Write: Anytime NOTE For conversions not using automatic compare, results are stored in the result registers after each conversion. In this case avoid writing to ATDDRn except for initial values, because an A/D result might be overwritten. Module Base + 0x000E 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R CMPHT[15:0] W Reset 0 0 0 0 0 0 0 0 0 0000000 = Unimplemented or Reserved Figure 13-13. ATD Compare Higher Than Register (ATDCMPHT) Table 13-20. ATDCMPHT Field Descriptions Field Description 15–0 CMPHT[15:0] Compare Operation Higher Than Enable for conversion numbern (n= 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) of a Sequence (n conversion number, NOT channel number!)— This bit selects the operator for comparison of conversion results.

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13.3.2.12.1 Left Justiﬁed Result Data (DJM=0)

Table 13-21 shows how depending on the A/D resolution the conversion result is transferred to the ATD result registers for left justiﬁed data. Compare is always done using all 12 bits of both the conversion result and the compare value in ATDDRn.

13.3.2.12.2 Right Justiﬁed Result Data (DJM=1)

0x0010 = ATDDR0, 0x0012 = ATDDR1, 0x0014 = ATDDR2, 0x0016 = ATDDR3 0x0018 = ATDDR4, 0x001A = ATDDR5, 0x001C = ATDDR6, 0x001E = ATDDR7 0x0020 = ATDDR8, 0x0022 = ATDDR9, 0x0024 = ATDDR10, 0x0026 = ATDDR11 0x0028 = ATDDR12, 0x002A = ATDDR13, 0x002C = ATDDR14, 0x002E = ATDDR15 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Result-Bit[11:0] 0 000 W Reset 0 0 0 0 0 0 0 0 0 0000000 = Unimplemented or Reserved Figure 13-14. Left justiﬁed ATD conversion result register (ATDDRn) Table 13-21. Conversion result mapping to ATDDRn A/D resolution DJM conversion result mapping to ATDDRn 8-bit data 0 Result-Bit[11:4] = conversion result, Result-Bit[3:0]=0000 10-bit data 0 Result-Bit[11:2] = conversion result, Result-Bit[1:0]=00 Module Base + 0x0010 = ATDDR0, 0x0012 = ATDDR1, 0x0014 = ATDDR2, 0x0016 = ATDDR3 0x0018 = ATDDR4, 0x001A = ATDDR5, 0x001C = ATDDR6, 0x001E = ATDDR7 0x0020 = ATDDR8, 0x0022 = ATDDR9, 0x0024 = ATDDR10, 0x0026 = ATDDR11 0x0028 = ATDDR12, 0x002A = ATDDR13, 0x002C = ATDDR14, 0x002E = ATDDR15 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 000 Result-Bit[11:0] W Reset 0 0 0 0 0 0 0 0 0 0000000 = Unimplemented or Reserved Figure 13-15. Right justiﬁed ATD conversion result register (ATDDRn)

Analog-to-Digital Converter (ADC10B16CV2) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 437 Table 13-22 shows how depending on the A/D resolution the conversion result is transferred to the ATD result registers for right justiﬁed data. Compare is always done using all 12 bits of both the conversion result and the compare value in ATDDRn.

13.4 Functional Description

The ADC10B16C consists of an analog sub-block and a digital sub-block.

13.4.1 Analog Sub-Block

13.4.1.1 Sample and Hold Machine

13.4.1.2 Analog Input Multiplexer

The analog input multiplexer connects one of the 8 external analog input channels to the sample and hold machine.

13.4.1.3 Analog-to-Digital (A/D) Machine

The A/D Machine performs analog to digital conversions. The resolution is program selectable to be either 8 or 10 bits. The A/D machine uses a successive approximation architecture. It functions by comparing the sampled and stored analog voltage with a series of binary coded discrete voltages. By following a binary search algorithm, the A/D machine identiﬁes the discrete voltage that is nearest to the sampled and stored voltage. When not converting the A/D machine is automatically powered down. Table 13-22. Conversion result mapping to ATDDRn A/D resolution DJM conversion result mapping to ATDDRn 8-bit data 1 Result-Bit[7:0] = result, Result-Bit[11:8]=0000 10-bit data 1 Result-Bit[9:0] = result, Result-Bit[11:10]=00

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Only analog input signals within the potential range of VRL to VRH (A/D reference potentials) will result in a non-railed digital output code.

13.4.2 Digital Sub-Block

This subsection describes some of the digital features in more detail. See Section 13.3.2, “Register Descriptions” for all details.

13.4.2.1 External Trigger Input

The external trigger feature allows the user to synchronize ATD conversions to an external event rather than relying only on software to trigger the ATD module when a conversion is about to take place. The external trigger signal (out of reset ATD channel 15, conﬁgurable in ATDCTL1) is programmable to be edge or level sensitive with polarity control. Table 13-23 gives a brief description of the different combinations of control bits and their effect on the external trigger function. In either level or edge sensitive mode, the ﬁrst conversion begins when the trigger is received. Once ETRIGE is enabled a conversion must be triggered externally after writing to ATDCTL5 register. During a conversion in edge sensitive mode, if additional trigger events are detected the overrun error ﬂag ETORF is set. If level sensitive mode is active and the external trigger de-asserts and later asserts again during a conversion sequence, this does not constitute an overrun. Therefore, the ﬂag is not set. If the trigger is left active in level sensitive mode when a sequence is about to complete, another sequence will be triggered immediately. Table 13-23. External Trigger Control Bits ETRIGLE ETRIGP ETRIGE SCAN Description X X 0 0 Ignores external trigger. Performs one conversion sequence and stops. X X 0 1 Ignores external trigger. Performs continuous conversion sequences. 0 0 1 X Trigger falling edge sensitive. Performs one conversion sequence per trigger. 0 1 1 X Trigger rising edge sensitive. Performs one conversion sequence per trigger. 1 0 1 X Trigger low level sensitive. Performs continuous conversions while trigger level is active. 1 1 1 X Trigger high level sensitive. Performs continuous conversions while trigger level is active.

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13.4.2.2 General-Purpose Digital Port Operation

13.5 Resets

At reset the ADC10B16C is in a power down state. The reset state of each individual bit is listed within the Register Description section (see Section 13.3.2, “Register Descriptions”) which details the registers and their bit-ﬁeld.

13.6 Interrupts

The interrupts requested by the ADC10B16C are listed in Table 13-24. Refer to MCU speciﬁcation for related vector address and priority. See Section 13.3.2, “Register Descriptions” for further details. Table 13-24. ATD Interrupt Vectors Interrupt Source CCR Mask Local Enable Sequence Complete Interrupt I bit ASCIE in ATDCTL2 Compare Interrupt I bit ACMPIE in ATDCTL2

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MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 441 Chapter 14 Analog-to-Digital Converter (ADC12B16CV2)

14.1 Introduction

The ADC12B16C is a 16-channel, 12-bit, multiplexed input successive approximation analog-to-digital converter. Refer to device electrical speciﬁcations for ATD accuracy.

14.1.1 Features

8-, 10-, or 12-bit resolution. Version Number Revision Date Effective Date Author Description of Changes V02.00 18 June 2009 18 June 2009 Initial version copied 12 channel block guide V02.01 09 Feb 2010 09 Feb 2010 Updated Table 14-15 Analog Input Channel Select Coding - description of internal channels. Updated register ATDDR (left/right justiﬁed result) description added Table 14-21 to improve feature description. Fixed typo in Table 14-9- conversion result for 3mV and 10bit resolution V02.03 26 Feb 2010 26 Feb 2010 Corrected Table 14-15Analog Input Channel Select Coding - description of internal channels. V02.04 26 Mar 2010 16 Mar 2010 Corrected typo: Reset value of ATDDIEN register V02.05 14 Apr 2010 14 Apr 2010 Corrected typos to be in-line with SoC level pin naming conventions for VDDA, VSSA, VRL and VRH. V02.06 25 Aug 2010 25 Aug 2010 Removed feature of conversion during STOP and general wording clean up done in Section 14.4, “Functional

v02.07 09 Sep 2010 09 Sep 2010 Update of internal only information. V02.08 11 Feb 2011 11 Feb 2011 Connectivity Information regarding internal channel_6 added to Table 14-15. V02.09 29 Mar 2011 29 Mar 2011 Fixed typo in bit description ﬁeld Table 14-14for bits CD, CC, CB, CA. Last sentence contained a wrong highest channel number (it is not AN7 to AN0 instead it is AN15 to AN0).

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Automatic return to low power after conversion sequence
Automatic compare with interrupt for higher than or less/equal than programmable value
Programmable sample time.
Left/right justiﬁed result data.
External trigger control.
Sequence complete interrupt.
Analog input multiplexer for 8 analog input channels.
Special conversions for VRH, VRL, (VRL+VRH)/2 and ADC temperature sensor.
1-to-16 conversion sequence lengths.
Continuous conversion mode.
Multiple channel scans.
Conﬁgurable external trigger functionality on any AD channel or any of four additional trigger inputs. The four additional trigger inputs can be chip external or internal. Refer to device speciﬁcation for availability and connectivity.
Conﬁgurable location for channel wrap around (when converting multiple channels in a sequence).

14.1.2 Modes of Operation

14.1.2.1 Conversion Modes

There is software programmable selection between performing single or continuous conversion on a single channel or multiple channels.

14.1.2.2 MCU Operating Modes

Stop Mode Entering Stop Mode aborts any conversion sequence in progress and if a sequence was aborted restarts it after exiting stop mode. This has the same effect/consequences as starting a conversion sequence with write to ATDCTL5. So after exiting from stop mode with a previously aborted sequence all ﬂags are cleared etc.
Wait Mode ADC12B16C behaves same in Run and Wait Mode. For reduced power consumption continuous conversions should be aborted before entering Wait mode.
Freeze Mode In Freeze Mode the ADC12B16C will either continue or ﬁnish or stop converting according to the FRZ1 and FRZ0 bits. This is useful for debugging and emulation.

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14.1.3 Block Diagram

Figure 14-1. ADC12B16C Block Diagram VSSA AN9 ATD_12B12C Analog MUX Mode and Successive Approximation Register (SAR) Results ATD 0 ATD 1 ATD 2 ATD 3 ATD 4 ATD 5 ATD 6 ATD 7 and DAC Sample & Hold VDDA VRL VRH Sequence Complete Comparator Clock Prescaler Bus Clock ATD Clock AN7 AN6 AN5 AN10 ETRIG0 (See device speciﬁ- cation for availability ETRIG1 ETRIG2 ETRIG3 and connectivity) Timing Control ATDDIENATDCTL1 Trigger Mux Interrupt Compare Interrupt AN4 AN11 AN12 AN13 AN14 ATD 8 ATD 9 ATD 10 ATD 11 ATD 13 ATD 14 ATD 12 ATD 15 AN3 AN2 AN1 AN0 AN8 AN15

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14.2 Signal Description

This section lists all inputs to the ADC12B16C block.

14.2.1 Detailed Signal Descriptions

This pin serves as the analog input Channel x. It can also be conﬁgured as digital port or external trigger for the ATD conversion.

14.2.1.2 ETRIG3, ETRIG2, ETRIG1, ETRIG0

These inputs can be conﬁgured to serve as an external trigger for the ATD conversion. Refer to device speciﬁcation for availability and connectivity of these inputs!

14.2.1.3 VRH, VRL

VRH is the high reference voltage, VRL is the low reference voltage for ATD conversion.

14.2.1.4 VDDA, VSSA

These pins are the power supplies for the analog circuitry of the ADC12B16C block.

14.3 Memory Map and Register Deﬁnition

This section provides a detailed description of all registers accessible in the ADC12B16C.

14.3.1 Module Memory Map

Figure 14-2 gives an overview on all ADC12B16C registers. NOTE Register Address = Base Address + Address Offset, where the Base Address is deﬁned at the MCU level and the Address Offset is deﬁned at the module level. Address Name Bit 7 6 5 4 3 2 1 Bit 0 0x0000 ATDCTL0 R Reserved 000 WRAP3 WRAP2 WRAP1 WRAP0W 0x0001 ATDCTL1 R ETRIGSEL SRES1 SRES0 SMP_DIS ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0W 0x0002 ATDCTL2 R0 AFFC Reserved ETRIGLE ETRIGP ETRIGE ASCIE ACMPIEW = Unimplemented or Reserved Figure 14-2. ADC12B16C Register Summary (Sheet 1 of 3)

Analog-to-Digital Converter (ADC12B16CV2) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 445 0x0003 ATDCTL3 R DJM S8C S4C S2C S1C FIFO FRZ1 FRZ0W 0x0004 ATDCTL4 R SMP2 SMP1 SMP0 PRS[4:0]W 0x0005 ATDCTL5 R0 SC SCAN MULT CD CC CB CAW 0x0006 ATDSTAT0 R SCF 0 ETORF FIFOR CC3 CC2 CC1 CC0 W 0x0007 Unimple- mented R 0 000 0 0 0 0 W 0x0008 ATDCMPEH R CMPE[15:8]W 0x0009 ATDCMPEL R CMPE[7:0]W 0x000A ATDSTAT2H R CCF[15:8] W 0x000B ATDSTAT2L R CCF[7:0] W 0x000C ATDDIENH R IEN[15:8]W 0x000D ATDDIENL R IEN[7:0]W 0x000E ATDCMPHTH R CMPHT[15:8]W 0x000F ATDCMPHTL R CMPHT[7:0]W 0x0010 ATDDR0 R See Section 14.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” and Section 14.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”W 0x0012 ATDDR1 R See Section 14.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” and Section 14.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”W 0x0014 ATDDR2 R See Section 14.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” and Section 14.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”W 0x0016 ATDDR3 R See Section 14.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” and Section 14.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”W 0x0018 ATDDR4 R See Section 14.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” and Section 14.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”W 0x001A ATDDR5 R See Section 14.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” and Section 14.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”W 0x001C ATDDR6 R See Section 14.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” and Section 14.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”W 0x001E ATDDR7 R See Section 14.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” and Section 14.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”W 0x0020 ATDDR8 R See Section 14.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” and Section 14.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”W 0x0022 ATDDR9 R See Section 14.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” and Section 14.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”W Address Name Bit 7 6 5 4 3 2 1 Bit 0 = Unimplemented or Reserved Figure 14-2. ADC12B16C Register Summary (Sheet 2 of 3)

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14.3.2 Register Descriptions

This section describes in address order all the ADC12B16C registers and their individual bits.

14.3.2.1 ATD Control Register 0 (ATDCTL0)

Writes to this register will abort current conversion sequence. Read: Anytime Write: Anytime, in special modes always write 0 to Reserved Bit 7. 0x0024 ATDDR10 R See Section 14.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” and Section 14.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”W 0x0026 ATDDR11 R See Section 14.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” and Section 14.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”W 0x0028 ATDDR12 R See Section 14.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” and Section 14.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”W 0x002A ATDDR13 R See Section 14.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” and Section 14.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”W 0x002C ATDDR14 R See Section 14.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” and Section 14.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”W 0x002E ATDDR15 R See Section 14.3.2.12.1, “Left Justiﬁed Result Data (DJM=0)” and Section 14.3.2.12.2, “Right Justiﬁed Result Data (DJM=1)”W W Module Base + 0x0000 76543210 R Reserved 000 WRAP3 WRAP2 WRAP1 WRAP0 W Reset 0 0 0 01111 = Unimplemented or Reserved Figure 14-3. ATD Control Register 0 (ATDCTL0) Table 14-1. ATDCTL0 Field Descriptions Field Description 3-0 WRAP[3-0] Wrap Around Channel Select Bits — These bits determine the channel for wrap around when doing multi-channel conversions. The coding is summarized in Table 14-2. Address Name Bit 7 6 5 4 3 2 1 Bit 0 = Unimplemented or Reserved Figure 14-2. ADC12B16C Register Summary (Sheet 3 of 3)

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14.3.2.2 ATD Control Register 1 (ATDCTL1)

Writes to this register will abort current conversion sequence. Read: Anytime Write: Anytime Table 14-2. Multi-Channel Wrap Around Coding WRAP3 WRAP2 WRAP1 WRAP0 Multiple Channel Conversions (MULT = 1) Wraparound to AN0 after Converting 1If only AN0 should be converted use MULT=0. R ETRIGSEL SRES1 SRES0 SMP_DIS ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0 W Reset 0 0 1 01111 Figure 14-4. ATD Control Register 1 (ATDCTL1)

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Table 14-3. ATDCTL1 Field Descriptions Field Description ETRIGSEL External Trigger Source Select — This bit selects the external trigger source to be either one of the AD channels or one of the ETRIG3-0 inputs. See device speciﬁcation for availability and connectivity of ETRIG3-0 inputs. If a particular ETRIG3-0 input option is not available, writing a 1 to ETRISEL only sets the bit but has no effect, this means that one of the AD channels (selected by ETRIGCH3-0) is conﬁgured as the source for external trigger. The coding is summarized in Table 14-5. 6–5 SRES[1:0] A/D Resolution Select — These bits select the resolution of A/D conversion results. See Table 14-4 for coding. SMP_DIS Discharge Before Sampling Bit 0 No discharge before sampling. 1 The internal sample capacitor is discharged before sampling the channel. This adds 2 ATD clock cycles to the sampling time. This can help to detect an open circuit instead of measuring the previous sampled channel. 3–0 ETRIGCH[3:0] External Trigger Channel Select— These bits select one of the AD channels or one of the ETRIG3-0 inputs as source for the external trigger. The coding is summarized in Table 14-5. Table 14-4. A/D Resolution Coding SRES1 SRES0 A/D Resolution 0 0 8-bit data 0 1 10-bit data 1 0 12-bit data 1 1 Reserved Table 14-5. External Trigger Channel Select Coding ETRIGSEL ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0 External trigger source is 0 0 0 0 0 AN0 0 0 0 0 1 AN1 0 0 0 1 0 AN2 0 0 0 1 1 AN3 0 0 1 0 0 AN4 0 0 1 0 1 AN5 0 0 1 1 0 AN6 0 0 1 1 1 AN7 0 1 0 0 0 AN8 0 1 0 0 1 AN9 0 1 0 1 0 AN10 0 1 0 1 1 AN11 0 1 1 0 0 AN12 0 1 1 0 1 AN13 0 1 1 1 0 AN14 0 1 1 1 1 AN15 1 0 0 0 0 ETRIG0 1 0 0 0 1 ETRIG1 1

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14.3.2.3 ATD Control Register 2 (ATDCTL2)

Writes to this register will abort current conversion sequence. Read: Anytime Write: Anytime 1 0 0 1 0 ETRIG2 1 1 0 0 1 1 ETRIG3 1 1 0 1 X X Reserved 1 1 X X X Reserved 1 Only if ETRIG3-0 input option is available (see device speciﬁcation), else ETRISEL is ignored, that means external trigger source is still on one of the AD channels selected by ETRIGCH3-0 Module Base + 0x0002 76543210 AFFC Reserved ETRIGLE ETRIGP ETRIGE ASCIE ACMPIE W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 14-5. ATD Control Register 2 (ATDCTL2) Table 14-6. ATDCTL2 Field Descriptions Field Description AFFC ATD Fast Flag Clear All 0 ATD ﬂag clearing done by write 1 to respective CCF[ n] ﬂag. 1 Changes all ATD conversion complete ﬂags to a fast clear sequence. For compare disabled (CMPE[n]=0) a read access to the result register will cause the associated CCF[n] ﬂag to clear automatically. For compare enabled (CMPE[n]=1) a write access to the result register will cause the associated CCF[n] ﬂag to clear automatically. Reserved Do not alter this bit from its reset value.It is for Manufacturer use only and can change the ATD behavior. ETRIGLE External Trigger Level/Edge Control — This bit controls the sensitivity of the external trigger signal. See Table 14-7 for details. ETRIGP External Trigger Polarity— This bit controls the polarity of the external trigger signal. SeeTable 14-7for details. ETRIGE External Trigger Mode Enable— This bit enables the external trigger on one of the AD channels or one of the ETRIG3-0 inputs as described in Table 14-5. If the external trigger source is one of the AD channels, the digital input buffer of this channel is enabled. The external trigger allows to synchronize the start of conversion with external events. Table 14-5. External Trigger Channel Select Coding ETRIGSEL ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0 External trigger source is

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14.3.2.4 ATD Control Register 3 (ATDCTL3)

Writes to this register will abort current conversion sequence. Read: Anytime Write: Anytime ASCIE ATD Sequence Complete Interrupt Enable 0 ATD Sequence Complete interrupt requests are disabled. 1 ATD Sequence Complete interrupt will be requested whenever SCF=1 is set. ACMPIE ATD Compare Interrupt Enable— If automatic compare is enabled for conversion n (CMPE[n]=1 in ATDCMPE register) this bit enables the compare interrupt. If the CCF[n] ﬂag is set (showing a successful compare for conversion n), the compare interrupt is triggered. 0 ATD Compare interrupt requests are disabled. Interrupt will be requested whenever any of the respective CCF ﬂags is set. Table 14-7. External Trigger Conﬁgurations ETRIGLE ETRIGP External Trigger Sensitivity 0 0 Falling edge 0 1 Rising edge 1 0 Low level 1 1 High level Module Base + 0x0003 76543210 R DJM S8C S4C S2C S1C FIFO FRZ1 FRZ0 W Reset 0 0 1 00000 = Unimplemented or Reserved Figure 14-6. ATD Control Register 3 (ATDCTL3) Table 14-6. ATDCTL2 Field Descriptions (continued) Field Description

Analog-to-Digital Converter (ADC12B16CV2) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 451 Table 14-8. ATDCTL3 Field Descriptions Field Description DJM Result Register Data Justiﬁcation — Result data format is always unsigned. This bit controls justiﬁcation of conversion data in the result registers. 0 Left justiﬁed data in the result registers. 1 Right justiﬁed data in the result registers. Table 14-9 gives example ATD results for an input signal range between 0 and 5.12 Volts. 6–3 S8C, S4C, S2C, S1C Conversion Sequence Length — These bits control the number of conversions per sequence. Table 14-10 shows all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity to HC12 family. FIFO Result Register FIFO Mode— If this bit is zero (non-FIFO mode), the A/D conversion results map into the result registers based on the conversion sequence; the result of the ﬁrst conversion appears in the ﬁrst result register (ATDDR0), the second result in the second result register (ATDDR1), and so on. If this bit is one (FIFO mode) the conversion counter is not reset at the beginning or end of a conversion sequence; sequential conversion results are placed in consecutive result registers. In a continuously scanning conversion sequence, the result register counter will wrap around when it reaches the end of the result register ﬁle. The conversion counter value (CC3-0 in ATDSTAT0) can be used to determine where in the result register ﬁle, the current conversion result will be placed. Aborting a conversion or starting a new conversion clears the conversion counter even if FIFO=1. So the ﬁrst result of a new conversion sequence, started by writing to ATDCTL5, will always be place in the ﬁrst result register (ATDDDR0). Intended usage of FIFO mode is continuos conversion (SCAN=1) or triggered conversion (ETRIG=1). Which result registers hold valid data can be tracked using the conversion complete ﬂags. Fast ﬂag clear mode may be useful in a particular application to track valid data. If this bit is one, automatic compare of result registers is always disabled, that is ADC12B16C will behave as if ACMPIE and all CPME[n] were zero. 0 Conversion results are placed in the corresponding result register up to the selected sequence length. 1 Conversion results are placed in consecutive result registers (wrap around at end). 1–0 FRZ[1:0] Background Debug Freeze Enable — When debugging an application, it is useful in many cases to have the ATD pause when a breakpoint (Freeze Mode) is encountered. These 2 bits determine how the ATD will respond to a breakpoint as shown in Table 14-11. Leakage onto the storage node and comparator reference capacitors may compromise the accuracy of an immediately frozen conversion depending on the length of the freeze period.

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Table 14-9. Examples of ideal decimal ATD Results Input Signal VRL = 0 Volts VRH = 5.12 Volts 8-Bit Codes (resolution=20mV) 10-Bit Codes (resolution=5mV) 12-Bit Codes (transfer curve has 1.25mV offset) (resolution=1.25mV) ... 0.022 0.020 0.018 0.016 0.014 0.012 0.010 0.008 0.006 0.004 0.003 0.002 0.000 255 ... 1023 ... 4095 ... Table 14-10. Conversion Sequence Length Coding S8C S4C S2C S1C Number of Conversions per Sequence 00 0 0 1 6 00 0 1 1 00 1 0 2 00 1 1 3 01 0 0 4 01 0 1 5 01 1 0 6 01 1 1 7 10 0 0 8 10 0 1 9 10 1 0 1 0 10 1 1 1 1 11 0 0 1 2 11 0 1 1 3 11 1 0 1 4 11 1 1 1 5

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14.3.2.5 ATD Control Register 4 (ATDCTL4)

Writes to this register will abort current conversion sequence. Read: Anytime Write: Anytime Table 14-11. ATD Behavior in Freeze Mode (Breakpoint) FRZ1 FRZ0 Behavior in Freeze Mode 0 0 Continue conversion 0 1 Reserved 1 0 Finish current conversion, then freeze 1 1 Freeze Immediately Module Base + 0x0004 76543210 R SMP2 SMP1 SMP0 PRS[4:0] W Reset 0 0 0 00101 Figure 14-7. ATD Control Register 4 (ATDCTL4) Table 14-12. ATDCTL4 Field Descriptions Field Description 7–5 SMP[2:0] Sample Time Select — These three bits select the length of the sample time in units of ATD conversion clock cycles. Note that the ATD conversion clock period is itself a function of the prescaler value (bits PRS4-0). Table 14-13 lists the available sample time lengths. 4–0 PRS[4:0] ATD Clock Prescaler— These 5 bits are the binary prescaler value PRS. The ATD conversion clock frequency is calculated as follows: Refer to Device Speciﬁcation for allowed frequency range of f ATDCLK. Table 14-13. Sample Time Select SMP2 SMP1 SMP0 Sample Time in Number of ATD Clock Cycles 000 4 001 6 010 8 011 1 0 100 1 2 101 1 6 110 2 0 fATDCLK fBUS

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14.3.2.6 ATD Control Register 5 (ATDCTL5)

Analog-to-Digital Converter (ADC12B16CV2) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 455 MULT Multi-Channel Sample Mode— When MULT is 0, the ATD sequence controller samples only from the speciﬁed analog input channel for an entire conversion sequence. The analog channel is selected by channel selection code (control bits CD/CC/CB/CA located in ATDCTL5). When MULT is 1, the ATD sequence controller samples across channels. The number of channels sampled is determined by the sequence length value (S8C, S4C, S2C, S1C). The ﬁrst analog channel examined is determined by channel selection code (CD, CC, CB, CA control bits); subsequent channels sampled in the sequence are determined by incrementing the channel selection code or wrapping around to AN0 (channel 0). 3–0 CD, CC, CB, CA Analog Input Channel Select Code — These bits select the analog input channel(s). Table 14-15 lists the coding used to select the various analog input channels. In the case of single channel conversions (MULT=0), this selection code speciﬁes the channel to be examined. In the case of multiple channel conversions (MULT=1), this selection code speciﬁes the ﬁrst channel to be examined in the conversion sequence. Subsequent channels are determined by incrementing the channel selection code or wrapping around to AN0 (after converting the channel deﬁned by the Wrap Around Channel Select Bits WRAP3-0 in ATDCTL0). When starting with a channel number higher than the one deﬁned by WRAP3-0 the ﬁrst wrap around will be AN16 to AN0. Table 14-15. Analog Input Channel Select Coding SC CD CC CB CA Analog Input Channel Table 14-14. ATDCTL5 Field Descriptions (continued) Field Description

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14.3.2.7 ATD Status Register 0 (ATDSTAT0)

This register contains the Sequence Complete Flag, overrun ﬂags for external trigger and FIFO mode, and the conversion counter. Read: Anytime Write: Anytime (No effect on (CC3, CC2, CC1, CC0)) 1 0 0 0 0 Internal_6, Temperature sense of ADC hardmacro 0 0 0 1 Internal_7 0 0 1 0 Internal_0 0 0 1 1 Internal_1 0 1 1 0 (VRH+VRL) / 2 0 1 1 1 Reserved 1 0 0 0 Internal_2 1 0 0 1 Internal_3 1 0 1 0 Internal_4 1 0 1 1 Internal_5 1 1 X X Reserved Module Base + 0x0006 76543210 R SCF ETORF FIFOR CC3 CC2 CC1 CC0 W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 14-9. ATD Status Register 0 (ATDSTAT0) Table 14-15. Analog Input Channel Select Coding SC CD CC CB CA Analog Input Channel

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14.3.2.8 ATD Compare Enable Register (ATDCMPE)

Writes to this register will abort current conversion sequence. Read: Anytime Write: Anytime Table 14-16. ATDSTAT0 Field Descriptions Field Description SCF Sequence Complete Flag — This ﬂag is set upon completion of a conversion sequence. If conversion sequences are continuously performed (SCAN=1), the ﬂag is set after each one is completed. This ﬂag is cleared when one of the following occurs: A) Write “1” to SCF B) Write to ATDCTL5 (a new conversion sequence is started) C) If AFFC=1 and a result register is read External Trigger Overrun Flag — While in edge sensitive mode (ETRIGLE=0), if additional active edges are detected while a conversion sequence is in process the overrun ﬂag is set. This ﬂag is cleared when one of the following occurs: A) Write “1” to ETORF B) Write to ATDCTL0,1,2,3,4, ATDCMPE or ATDCMPHT (a conversion sequence is aborted) C) Write to ATDCTL5 (a new conversion sequence is started) Result Register Overrun Flag— This bit indicates that a result register has been written to before its associated conversion complete ﬂag (CCF) has been cleared. This ﬂag is most useful when using the FIFO mode because the ﬂag potentially indicates that result registers are out of sync with the input channels. However, it is also practical for non-FIFO modes, and indicates that a result register has been overwritten before it has been read (i.e. the old data has been lost). This ﬂag is cleared when one of the following occurs: A) Write “1” to FIFOR B) Write to ATDCTL0,1,2,3,4, ATDCMPE or ATDCMPHT (a conversion sequence is aborted) C) Write to ATDCTL5 (a new conversion sequence is started) 3–0 CC[3:0] Conversion Counter — These 4 read-only bits are the binary value of the conversion counter. The conversion counter points to the result register that will receive the result of the current conversion. E.g. CC3=0, CC2=1, CC1=1, CC0=0 indicates that the result of the current conversion will be in ATD Result Register 6. If in non-FIFO mode (FIFO=0) the conversion counter is initialized to zero at the beginning and end of the conversion sequence. If in FIFO mode (FIFO=1) the register counter is not initialized. The conversion counter wraps around when its maximum value is reached. Aborting a conversion or starting a new conversion clears the conversion counter even if FIFO=1.

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14.3.2.9 ATD Status Register 2 (ATDSTAT2)

This read-only register contains the Conversion Complete Flags CCF[15:0]. Read: Anytime Write: Anytime, no effect Module Base + 0x0008 15 14 13 11 10 9 8 7 6 5 4 3 2 1 0 R CMPE[15:0] W Reset 0 0 0 0 0 0 0 0 0 0000000 = Unimplemented or Reserved Figure 14-10. ATD Compare Enable Register (ATDCMPE) Table 14-17. ATDCMPE Field Descriptions Field Description 15–0 CMPE[15:0] Compare Enable for Conversion Numbern (n= 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) of a Sequence (n conversion number, NOT channel number!)— These bits enable automatic compare of conversion results individually for conversions of a sequence. The sense of each comparison is determined by the CMPHT[n] bit in the ATDCMPHT register. For each conversion number with CMPE[n]=1 do the following: 1) Write compare value to ATDDRn result register 2) Write compare operator with CMPHT[n] in ATDCPMHT register CCF[n] in ATDSTAT2 register will ﬂag individual success of any comparison. 1 Automatic compare of results for conversion n of a sequence is enabled. Module Base + 0x000A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R CCF[15:0] W Reset 0 0 0 0 0 0 0 0 0 0000000 = Unimplemented or Reserved Figure 14-11. ATD Status Register 2 (ATDSTAT2)

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14.3.2.10 ATD Input Enable Register (ATDDIEN)

Read: Anytime Write: Anytime Table 14-18. ATDSTAT2 Field Descriptions Field Description 15–0 CCF[15:0] Conversion Complete Flagn (n= 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) (n conversion number, NOT channel number!)— A conversion complete ﬂag is set at the end of each conversion in a sequence. The ﬂags are associated with the conversion position in a sequence (and also the result register number). Therefore in non-ﬁfo mode, CCF[4] is set when the ﬁfth conversion in a sequence is complete and the result is available in result register ATDDR4; CCF[5] is set when the sixth conversion in a sequence is complete and the result is available in ATDDR5, and so forth. If automatic compare of conversion results is enabled (CMPE[n]=1 in ATDCMPE), the conversion complete ﬂag is only set if comparison with ATDDRn is true. If ACMPIE=1 a compare interrupt will be requested. In this case, as the ATDDRn result register is used to hold the compare value, the result will not be stored there at the end of the conversion but is lost. A ﬂag CCF[n] is cleared when one of the following occurs: A) Write to ATDCTL5 (a new conversion sequence is started) B) If AFFC=0, write “1” to CCF[n] C) If AFFC=1 and CMPE[n]=0, read of result register ATDDRn D) If AFFC=1 and CMPE[n]=1, write to result register ATDDRn In case of a concurrent set and clear on CCF[n]: The clearing by method A) will overwrite the set. The clearing by methods B) or C) or D) will be overwritten by the set. 1 If (CMPE[ n]=0): Conversion number n has completed. Result is ready in ATDDRn. If (CMPE[n]=1): Compare for conversion result number n with compare value in ATDDRn, using compare operator CMPGT[n] is true. (No result available in ATDDRn) Module Base + 0x000C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R IEN[15:0] W Reset 0 0 0 0 0 0 0 0 0 0000000 = Unimplemented or Reserved Figure 14-12. ATD Input Enable Register (ATDDIEN) Table 14-19. ATDDIEN Field Descriptions Field Description 15–0 IEN[15:0] ATD Digital Input Enable on channelx (x= 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0)— This bit controls the digital input buffer from the analog input pin (ANx) to the digital data register. 1 Enable digital input buffer on AN x pin. Note: Setting this bit will enable the corresponding digital input buffer continuously. If this bit is set while simultaneously using it as an analog port, there is potentially increased power consumption because the digital input buffer maybe in the linear region.

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14.3.2.11 ATD Compare Higher Than Register (ATDCMPHT)

Writes to this register will abort current conversion sequence. Read: Anytime Write: Anytime

14.3.2.12 ATD Conversion Result Registers (ATDDR n)

The A/D conversion results are stored in 16 result registers. Results are always in unsigned data representation. Left and right justiﬁcation is selected using the DJM control bit in ATDCTL3. If automatic compare of conversions results is enabled (CMPE[n]=1 in ATDCMPE), these registers must be written with the compare values in left or right justiﬁed format depending on the actual value of the DJM bit. In this case, as the ATDDRn register is used to hold the compare value, the result will not be stored there at the end of the conversion but is lost. Attention, n is the conversion number, NOT the channel number! Read: Anytime Write: Anytime NOTE For conversions not using automatic compare, results are stored in the result registers after each conversion. In this case avoid writing to ATDDRn except for initial values, because an A/D result might be overwritten. Module Base + 0x000E 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R CMPHT[15:0] W Reset 0 0 0 0 0 0 0 0 0 0000000 = Unimplemented or Reserved Figure 14-13. ATD Compare Higher Than Register (ATDCMPHT) Table 14-20. ATDCMPHT Field Descriptions Field Description 15–0 CMPHT[15:0] Compare Operation Higher Than Enable for conversion numbern (n= 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) of a Sequence (n conversion number, NOT channel number!)— This bit selects the operator for comparison of conversion results.

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14.3.2.12.1 Left Justiﬁed Result Data (DJM=0)

Table 14-21 shows how depending on the A/D resolution the conversion result is transferred to the ATD result registers for left justiﬁed data. Compare is always done using all 12 bits of both the conversion result and the compare value in ATDDRn.

14.3.2.12.2 Right Justiﬁed Result Data (DJM=1)

0x0010 = ATDDR0, 0x0012 = ATDDR1, 0x0014 = ATDDR2, 0x0016 = ATDDR3 0x0018 = ATDDR4, 0x001A = ATDDR5, 0x001C = ATDDR6, 0x001E = ATDDR7 0x0020 = ATDDR8, 0x0022 = ATDDR9, 0x0024 = ATDDR10, 0x0026 = ATDDR11 0x0028 = ATDDR12, 0x002A = ATDDR13, 0x002C = ATDDR14, 0x002E = ATDDR15 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Result-Bit[11:0] 0 000 W Reset 0 0 0 0 0 0 0 0 0 0000000 = Unimplemented or Reserved Figure 14-14. Left justiﬁed ATD conversion result register (ATDDRn) Table 14-21. Conversion result mapping to ATDDRn A/D resolution DJM conversion result mapping to ATDDRn 8-bit data 0 Result-Bit[11:4] = conversion result, Result-Bit[3:0]=0000 10-bit data 0 Result-Bit[11:2] = conversion result, Result-Bit[1:0]=00 12-bit data 0 Result-Bit[11:0] = result Module Base + 0x0010 = ATDDR0, 0x0012 = ATDDR1, 0x0014 = ATDDR2, 0x0016 = ATDDR3 0x0018 = ATDDR4, 0x001A = ATDDR5, 0x001C = ATDDR6, 0x001E = ATDDR7 0x0020 = ATDDR8, 0x0022 = ATDDR9, 0x0024 = ATDDR10, 0x0026 = ATDDR11 0x0028 = ATDDR12, 0x002A = ATDDR13, 0x002C = ATDDR14, 0x002E = ATDDR15 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 000 Result-Bit[11:0] W Reset 0 0 0 0 0 0 0 0 0 0000000 = Unimplemented or Reserved Figure 14-15. Right justiﬁed ATD conversion result register (ATDDRn)

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Table 14-22 shows how depending on the A/D resolution the conversion result is transferred to the ATD result registers for right justiﬁed data. Compare is always done using all 12 bits of both the conversion result and the compare value in ATDDRn.14.4 Functional Description The ADC12B16C consists of an analog sub-block and a digital sub-block.

14.4.1 Analog Sub-Block

14.4.1.1 Sample and Hold Machine

14.4.1.2 Analog Input Multiplexer

The analog input multiplexer connects one of the 8 external analog input channels to the sample and hold machine.

14.4.1.3 Analog-to-Digital (A/D) Machine

The A/D Machine performs analog to digital conversions. The resolution is program selectable to be either 8 or 10 or 12 bits. The A/D machine uses a successive approximation architecture. It functions by comparing the sampled and stored analog voltage with a series of binary coded discrete voltages. By following a binary search algorithm, the A/D machine identiﬁes the discrete voltage that is nearest to the sampled and stored voltage. When not converting the A/D machine is automatically powered down. Table 14-22. Conversion result mapping to ATDDRn A/D resolution DJM conversion result mapping to ATDDRn 8-bit data 1 Result-Bit[7:0] = result, Result-Bit[11:8]=0000 10-bit data 1 Result-Bit[9:0] = result, Result-Bit[11:10]=00 12-bit data 1 Result-Bit[11:0] = result

Analog-to-Digital Converter (ADC12B16CV2) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 463 Only analog input signals within the potential range of VRL to VRH (A/D reference potentials) will result in a non-railed digital output code.

14.4.2 Digital Sub-Block

This subsection describes some of the digital features in more detail. See Section 14.3.2, “Register Descriptions” for all details.

14.4.2.1 External Trigger Input

The external trigger feature allows the user to synchronize ATD conversions to an external event rather than relying only on software to trigger the ATD module when a conversion is about to take place. The external trigger signal (out of reset ATD channel 15, conﬁgurable in ATDCTL1) is programmable to be edge or level sensitive with polarity control. Table 14-23 gives a brief description of the different combinations of control bits and their effect on the external trigger function. In either level or edge sensitive mode, the ﬁrst conversion begins when the trigger is received. Once ETRIGE is enabled a conversion must be triggered externally after writing to ATDCTL5 register. During a conversion in edge sensitive mode, if additional trigger events are detected the overrun error ﬂag ETORF is set. If level sensitive mode is active and the external trigger de-asserts and later asserts again during a conversion sequence, this does not constitute an overrun. Therefore, the ﬂag is not set. If the trigger is left active in level sensitive mode when a sequence is about to complete, another sequence will be triggered immediately. Table 14-23. External Trigger Control Bits ETRIGLE ETRIGP ETRIGE SCAN Description X X 0 0 Ignores external trigger. Performs one conversion sequence and stops. X X 0 1 Ignores external trigger. Performs continuous conversion sequences. 0 0 1 X Trigger falling edge sensitive. Performs one conversion sequence per trigger. 0 1 1 X Trigger rising edge sensitive. Performs one conversion sequence per trigger. 1 0 1 X Trigger low level sensitive. Performs continuous conversions while trigger level is active. 1 1 1 X Trigger high level sensitive. Performs continuous conversions while trigger level is active.

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14.4.2.2 General-Purpose Digital Port Operation

14.5 Resets

At reset the ADC12B16C is in a power down state. The reset state of each individual bit is listed within the Register Description section (see Section 14.3.2, “Register Descriptions”) which details the registers and their bit-ﬁeld.

14.6 Interrupts

The interrupts requested by the ADC12B16C are listed in Table 14-24. Refer to MCU speciﬁcation for related vector address and priority. See Section 14.3.2, “Register Descriptions” for further details. Table 14-24. ATD Interrupt Vectors Interrupt Source CCR Mask Local Enable Sequence Complete Interrupt I bit ASCIE in ATDCTL2 Compare Interrupt I bit ACMPIE in ATDCTL2

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15.1 Revision History

Table 15-1. Revision History Table Rev. No. (Item No.) Data Sections Affected Substantial Change(s) 0.1 28-Oct.-09 all Initial Version 0.4 28-Oct.-09 (Thomas Becker) all Initial Version 0.5 12-Nov.-09 (Thomas Becker) all Reworked all sections, renamed pin names 0.6 17-Nov.-09 (Thomas Becker) 1.2.4 Added CPU stop mode 0.7 18-Nov.-09 (Thomas Becker) 1.2, 1.3 Update block diagram, removed analog and digital submodule, added section 1.3 0.8 04-Dec.-09 (Thomas Becker) 1.4.2 - changed reset value of FVR bit to 1’b1 - added new bit “Load” to DACCTL register - removed S3 switch description - renamed pin DAC to DACU 0.92 12-Feb.-10 (Thomas Becker) all - ﬁxed typo 1.01 04-May-10, Table 1.2, Section 1.4 Replaced VRL,VRL with variable correct wrong ﬁgure, table numbering 1.02 12-May-10 Section 1.4 replaced ipt_test_mode with ips_test_access new description/address of DACDEBUG register 1.1 25-May-10 15.4.2.1 Removed DACCTL register bit DACDIEN 1.2 25-Jun.-10 15.4 Correct table and ﬁgure title format 1.3 29-Jul.-10 15.2 Fixed typos 1.4 17-Nov.-10 15.2.2 Update the behavior of the DACU pin during stop mode Table 15-2. Terminology Term Meaning DAC Digital to Analog Converter VRL Low Reference Voltage

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15.2 Introduction

The DAC_8B5V module is a digital to analog converter. The converter works with a resolution of 8 bit and generates an output voltage between VRL and VRH. The module consists of conﬁguration registers and two analog functional units, a DAC resistor network and an operational ampliﬁer. The conﬁguration registers provide all required control bits for the DAC resistor network and for the operational ampliﬁer. The DAC resistor network generates the desired analog output voltage. The unbuffered voltage from the DAC resistor network output can be routed to the external DACU pin. When enabled, the buffered voltage from the operational ampliﬁer output is available on the external AMP pin. The operational ampliﬁer is also stand alone usable. Figure 15-1 shows the block diagram of the DAC_8B5V module.

15.2.1 Features

The DAC_8B5V module includes these distinctive features:

1 digital-analog converter channel with: — 8 bit resolution — full and reduced output voltage range — buffered or unbuffered analog output voltage usable
operational ampliﬁer stand alone usable

15.2.2 Modes of Operation

The DAC_8B5V module behaves as follows in the system power modes: 1. CPU run mode The functionality of the DAC_8B5V module is available. 2. CPU stop mode Independent from the mode settings, the operational ampliﬁer is disabled, switch S1 and S2 are open. VRH High Reference Voltage FVR Full Voltage Range SSC Special Single Chip Table 15-2. Terminology (continued) Term Meaning

Digital Analog Converter (DAC_8B5V) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 467 If the “Unbuffered DAC” mode was used before entering stop mode, then the DACU pin will reach VRH voltage level during stop mode. The content of the conﬁguration registers is unchanged.

15.2.3 Block Diagram

Figure 15-1. DAC_8B5V Block Diagram

15.3 External Signal Description

This section lists the name and description of all external ports.

15.3.1 DACU Output Pin

This analog pin drives the unbuffered analog output voltage from the DAC resistor network output, if the according mode is selected.

15.3.2 AMP Output Pin

This analog pin is used for the buffered analog output voltage from the operational ampliﬁer output, if the according mode is selected.

15.3.3 AMPP Input Pin

This analog input pin is used as input signal for the operational ampliﬁer positive input pin, if the according mode is selected. Internal Bus Operational AmpliﬁerResistor Network DACU AMPM AMP AMPP Conﬁguration Registers DAC VRH VRL

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15.3.4 AMPM Input Pin

This analog pin is used as input for the operational ampliﬁer negative input pin, if the according mode is selected.

15.4 Memory Map and Register Deﬁnition

This sections provides the detailed information of all registers for the DAC_8B5V module.

15.4.1 Register Summary

Figure 15-2 shows the summary of all implemented registers inside the DAC_8B5V module. NOTE Register Address = Module Base Address + Address Offset, where the Module Base Address is deﬁned at the MCU level and the Address Offset is deﬁned at the module level.

15.4.2 Register Descriptions

This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated ﬁgure number. Details of register bit and ﬁeld function follow the register diagrams, in bit order. Address Offset Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x0000 DACCTL R FVR DRIVE 000 DACM[2:0]W 0x0001 Reserved R 00000000 W 0x0002 DACVOL R VOLTAGE[7:0]W 0x0003 - 0x0006 Reserved R 00000000 W 0x0007 Reserved R Reserved Reserved Reserved Reserved Reserved Reserved Reserved ReservedW = Unimplemented Figure 15-2. DAC_8B5V Register Summaryfv_dac_8b5v_RESERVED

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15.4.2.1 Control Register (DACCTL)

Module Base + 0x0000 Access: User read/write 1 Write: Anytime 76543210 R FVR DRIVE 0 00 DACM[2:0] W Reset 10000000 = Unimplemented Figure 15-3. Control Register (DACCTL) Table 15-3. DACCTL Field Description Field Description FVR Full Voltage Range — This bit deﬁnes the voltage range of the DAC.

0 DAC resistor network operates with the reduced voltage range

1 DAC resistor network operates with the full voltage range

Note: For more details see Section 15.5.7, “Analog output voltage calculation”. DRIVE Drive Select — This bit selects the output drive capability of the operational ampliﬁer, see electrical Spec. for more details.

0 Low output drive for high resistive loads

1 High output drive for low resistive loads

2:0 DACM[2:0] Mode Select — These bits deﬁne the mode of the DAC. A write access with an unsupported mode will be ignored.

000 Off

001 Operational Ampliﬁer

100 Unbuffered DAC

101 Unbuffered DAC with Operational Ampliﬁer

111 Buffered DAC

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15.4.2.2 Analog Output Voltage Level Register (DACVOL)

15.4.2.3 Reserved Register

15.5 Functional Description

15.5.1 Functional Overview

The DAC resistor network and the operational ampliﬁer can be used together or stand alone. Following modes are supported: Module Base + 0x0002 Access: User read/write 1 Write: Anytime 76543210 R VOLTAGE[7:0] W Reset 00000000 Figure 15-4. Analog Output Voltage Level Register (DACVOL) Table 15-4. DACVOL Field Description Field Description 7:0 VOLTAGE[7:0] VOLTAGE— This register deﬁnes (together with the FVR bit) the analog output voltage. For more detail see Equation 15-1 and Equation 15-2. Module Base + 0x0007 Access: User read/write 1 Write: Only in special mode 76543210 R Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved W Reset xxxxxxxx Figure 15-5. Reserved Registerfv_dac_8b5v_RESERVED Table 15-5. DAC Modes of Operation DACM[2:0] Ampliﬁer DACU AMP Off 000 disabled disabled disconnected disconnected

Digital Analog Converter (DAC_8B5V) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 471 The DAC resistor network itself can work on two different voltage ranges: Table 15-7 shows the control signal decoding for each mode. For more detailed mode description see the sections below.

15.5.2 Mode “Off”

The “Off” mode is the default mode after reset and is selected by DACCTL.DACM[2:0] = 0x0. During this mode the DAC resistor network and the operational ampliﬁer are disabled and all switches are open. This mode provides the lowest power consumption. For decoding of the control signals see Table 15-7.

15.5.3 Mode “Operational Ampliﬁer”

The “Operational Ampliﬁer” mode is selected by DACCTL.DACM[2:0] = 0x1. During this mode the operational ampliﬁer can be used independent from the DAC resister network. All required ampliﬁer signals, AMP, AMPP and AMPM are available on the pins. The DAC resistor network output is disconnected from the DACU pin. The connection between the ampliﬁer output and the negative ampliﬁer input is open. For decoding of the control signals see Table 15-7. Operational ampliﬁer 001 disabled enabled disabled depend on AMPP and AMPM input Unbuffered DAC 100 enabled disabled unbuffered resistor output voltage disconnected Unbuffered DAC with Operational ampliﬁer 101 enabled enabled unbuffered resistor output voltage depend on AMPP and AMPM input Buffered DAC 111 enabled enabled disconnected buffered resistor output voltage Table 15-6. DAC Resistor Network Voltage ranges DAC Mode Description Full Voltage Range (FVR) DAC resistor network provides a output voltage over the complete input voltage range, default after reset Reduced Voltage Range DAC resistor network provides a output voltage over a reduced input voltage range Table 15-7. DAC Control Signals DACM DAC resistor network Operational Ampliﬁer Switch S1 Switch S2 Switch S3 Off 000 disabled disabled open open open Operational ampliﬁer 001 disabled enabled closed open open Unbuffered DAC 100 enabled disabled open open closed Unbuffered DAC with Operational ampliﬁer 101 enabled enabled closed open closed Buffered DAC 111 enabled enabled open closed open Table 15-5. DAC Modes of Operation

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15.5.4 Mode “Unbuffered DAC”

The “Unbuffered DAC” mode is selected by DACCNTL.DACM[2:0] = 0x4. During this mode the unbuffered analog voltage from the DAC resistor network output is available on the DACU output pin. The operational ampliﬁer is disabled and the operational ampliﬁer signals are disconnected from the AMP pins. For decoding of the control signals see Table 15-7.

15.5.5 Mode “Unbuffered DAC with Operational Ampliﬁer”

The “Unbuffered DAC with Operational Ampliﬁer” mode is selected by DACCTL.DACM[2:0] = 0x5. During this mode the DAC resistor network and the operational ampliﬁer are enabled and usable independent from each other. The unbuffered analog voltage from the DAC resistor network output is available on the DACU output pin. The operational ampliﬁer is disconnected from the DAC resistor network. All required ampliﬁer signals, AMP, AMPP and AMPM are available on the pins. The connection between the ampliﬁer output and the negative ampliﬁer input is open. For decoding of the control signals see Table 15-7.

15.5.6 Mode “Buffered DAC”

The “Buffered DAC” mode is selected by DACCTL.DACM[2:0] = 0x7. During this is mode the DAC resistor network and the operational ampliﬁer are enabled. The analog output voltage from the DAC resistor network output is buffered by the operational ampliﬁer and is available on the AMP output pin. The DAC resistor network output is disconnected from the DACU pin. For the decoding of the control signals see Table 15-7.

15.5.7 Analog output voltage calculation

The DAC can provide an analog output voltage in two different voltage ranges:

FVR = 0, reduced voltage range The DAC generates an analog output voltage inside the range from 0.1 x (VRH - VRL) + VRL to 0.9 x (VRH-VRL) + VRL with a resolution ((VRH-VRL) x 0.8) / 256, see equation below: analog output voltage = VOLATGE[7:0] x ((VRH-VRL) x 0.8) / 256) + 0.1 x (VRH-VRL) + VRL Eqn. 15-1
FVR = 1, full voltage range The DAC generates an analog output voltage inside the range from VRL to VRH with a resolution (VRH-VRL) / 256, see equation below: analog output voltage = VOLTAGE[7:0] x (VRH-VRL) / 256 +VRL Eqn. 15-2

Digital Analog Converter (DAC_8B5V) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 473 See Table 15-8 for an example for VRL = 0.0 V and VRH = 5.0 V . Table 15-8. Analog output voltage calculation FVR min. voltage max. voltage Resolution Equation 1 0.0V 4.980V 19.531mV VOLTAGE[7:0] x (5.0V) / 256

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MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 477 Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3)

16.1 Introduction

Freescale’s scalable controller area network (S12MSCANV3) deﬁnition is based on the MSCAN12 deﬁnition, which is the speciﬁc implementation of the MSCAN concept targeted for the M68HC12 microcontroller family. The module is a communication controller implementing the CAN 2.0A/B protocol as deﬁned in the Bosch speciﬁcation dated September 1991. For users to fully understand the MSCAN speciﬁcation, it is recommended that the Bosch speciﬁcation be read ﬁrst to familiarize the reader with the terms and concepts contained within this document. Though not exclusively intended for automotive applications, CAN protocol is designed to meet the speciﬁc requirements of a vehicle serial data bus: real-time processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness, and required bandwidth. MSCAN uses an advanced buffer arrangement resulting in predictable real-time behavior and simpliﬁed application software. Table 16-1. Revision History Revision Number Revision Date Sections Affected Description of Changes V03.11 31 Mar 2009 • Orthographic corrections V03.12 09 Aug 2010 Table 16-37 • Added ‘Bosch CAN 2.0A/B’ to bit time settings table V03.13 03 Mar 2011 Figure 16-4 Table 16-3

Corrected CANE write restrictions
Removed footnote from RXFRM bit

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16.1.1 Glossary

16.1.2 Block Diagram

Figure 16-1. MSCAN Block Diagram Table 16-2. Terminology ACK Acknowledge of CAN message CAN Controller Area Network CRC Cyclic Redundancy Code EOF End of Frame FIFO First-In-First-Out Memory IFS Inter-Frame Sequence SOF Start of Frame CPU bus CPU related read/write data bus CAN bus CAN protocol related serial bus oscillator clock Direct clock from external oscillator bus clock CPU bus related clock CAN clock CAN protocol related clock RXCAN TXCAN Receive/ Transmit Engine Message Filtering and Buffering Control and Status Wake-Up Interrupt Req. Errors Interrupt Req. Receive Interrupt Req. Transmit Interrupt Req. CANCLK Bus Clock Conﬁguration Oscillator Clock MUX Presc. Tq Clk MSCAN Low Pass Filter Wake-UpRegisters

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16.1.3 Features

The basic features of the MSCAN are as follows:

Implementation of the CAN protocol — Version 2.0A/B — Standard and extended data frames — Zero to eight bytes data length — Programmable bit rate up to 1 Mbps — Support for remote frames
Five receive buffers with FIFO storage scheme
Three transmit buffers with internal prioritization using a “local priority” concept
Flexible maskable identiﬁer ﬁlter supports two full-size (32-bit) extended identiﬁer ﬁlters, or four 16-bit ﬁlters, or eight 8-bit ﬁlters
Programmable wake-up functionality with integrated low-pass ﬁlter
Programmable loopback mode supports self-test operation
Programmable listen-only mode for monitoring of CAN bus
Programmable bus-off recovery functionality
Separate signalling and interrupt capabilities for all CAN receiver and transmitter error states (warning, error passive, bus-off)
Programmable MSCAN clock source either bus clock or oscillator clock
Internal timer for time-stamping of received and transmitted messages
Three low-power modes: sleep, power down, and MSCAN enable
Global initialization of conﬁguration registers

16.1.4 Modes of Operation

For a description of the speciﬁc MSCAN modes and the module operation related to the system operating modes refer to Section 16.4.4, “Modes of Operation”.

16.2 External Signal Description

The MSCAN uses two external pins. NOTE On MCUs with an integrated CAN physical interface (transceiver) the MSCAN interface is connected internally to the transceiver interface. In these cases the external availability of signals TXCAN and RXCAN is optional.

16.2.1 RXCAN — CAN Receiver Input Pin

RXCAN is the MSCAN receiver input pin. 1. Depending on the actual bit timing and the clock jitter of the PLL.

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16.2.2 TXCAN — CAN Transmitter Output Pin

TXCAN is the MSCAN transmitter output pin. The TXCAN output pin represents the logic level on the CAN bus: 0 = Dominant state 1 = Recessive state

16.2.3 CAN System

A typical CAN system with MSCAN is shown inFigure 16-2. Each CAN station is connected physically to the CAN bus lines through a transceiver device. The transceiver is capable of driving the large current needed for the CAN bus and has current protection against defective CAN or defective stations. Figure 16-2. CAN System

16.3 Memory Map and Register Deﬁnition

This section provides a detailed description of all registers accessible in the MSCAN.

16.3.1 Module Memory Map

Figure 16-3 gives an overview on all registers and their individual bits in the MSCAN memory map. The register address results from the addition of base address and address offset. The base address is determined at the MCU level and can be found in the MCU memory map description. The address offset is deﬁned at the module level. The MSCAN occupies 64 bytes in the memory space. The base address of the MSCAN module is determined at the MCU level when the MCU is deﬁned. The register decode map is ﬁxed and begins at the ﬁrst address of the module address offset. CAN Bus CAN Controller (MSCAN) Transceiver CAN node 1 CAN node 2 CAN node n CANLCANH MCU TXCAN RXCAN

Freescale’s Scalable Controller Area Network (S12MSCANV3) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 481 The detailed register descriptions follow in the order they appear in the register map. Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x0000 CANCTL0 R RXFRM RXACT CSWAI SYNCH TIME WUPE SLPRQ INITRQ W 0x0001 CANCTL1 R CANE CLKSRC LOOPB LISTEN BORM WUPM SLPAK INITAK W 0x0002 CANBTR0 R SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 W 0x0003 CANBTR1 R SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 W 0x0004 CANRFLG R WUPIF CSCIF RSTAT1 RSTAT0 TSTAT1 TSTAT0 OVRIF RXF W 0x0005 CANRIER R WUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE W 0x0006 CANTFLG R0 0 0 00 TXE2 TXE1 TXE0 W 0x0007 CANTIER R 00000 TXEIE2 TXEIE1 TXEIE0 W 0x0008 CANTARQ R 00000 ABTRQ2 ABTRQ1 ABTRQ0 W 0x0009 CANTAAK R 00000 ABTAK2 ABTAK1 ABTAK0 W 0x000A CANTBSEL R 00000 TX2 TX1 TX0 W 0x000B CANIDAC R0 0 IDAM1 IDAM0

0 IDHIT2 IDHIT1 IDHIT0

W 0x000C Reserved R 00000000 W 0x000D CANMISC R 0000000 BOHOLD W = Unimplemented or Reserved Figure 16-3. MSCAN Register Summary

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16.3.2 Register Descriptions

This section describes in detail all the registers and register bits in the MSCAN module. Each description includes a standard register diagram with an associated ﬁgure number. Details of register bit and ﬁeld function follow the register diagrams, in bit order. All bits of all registers in this module are completely synchronous to internal clocks during a register read.

16.3.2.1 MSCAN Control Register 0 (CANCTL0)

The CANCTL0 register provides various control bits of the MSCAN module as described below. 0x000E CANRXERR R RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 W 0x000F CANTXERR R TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 W 0x0010–0x0013 CANIDAR0–3 R AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 W 0x0014–0x0017 CANIDMRx R AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 W 0x0018–0x001B CANIDAR4–7 R AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 W 0x001C–0x001F CANIDMR4–7 R AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 W 0x0020–0x002F CANRXFG R See Section 16.3.3, “Programmer’s Model of Message Storage” W 0x0030–0x003F CANTXFG R See Section 16.3.3, “Programmer’s Model of Message Storage” W Register Name Bit 7 6 5 4 3 2 1 Bit 0 = Unimplemented or Reserved Figure 16-3. MSCAN Register Summary (continued)

Freescale’s Scalable Controller Area Network (S12MSCANV3) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 483 NOTE The CANCTL0 register, except WUPE, INITRQ, and SLPRQ, is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable again as soon as the initialization mode is exited (INITRQ = 0 and INITAK = 0). Module Base + 0x0000 Access: User read/write1 Write: Anytime when out of initialization mode; exceptions are read-only RXACT and SYNCH, RXFRM (which is set by the module only), and INITRQ (which is also writable in initialization mode) 76543210 R RXFRM RXACT CSWAI SYNCH TIME WUPE SLPRQ INITRQ W Reset: 00000001 = Unimplemented Figure 16-4. MSCAN Control Register 0 (CANCTL0) Table 16-3. CANCTL0 Register Field Descriptions Field Description RXFRM Received Frame Flag — This bit is read and clear only. It is set when a receiver has received a valid message correctly, independently of the ﬁlter conﬁguration. After it is set, it remains set until cleared by software or reset. Clearing is done by writing a 1. Writing a 0 is ignored. This bit is not valid in loopback mode.

0 No valid message was received since last clearing this ﬂag

1 A valid message was received since last clearing of this ﬂag

Receiver Active Status — This read-only ﬂag indicates the MSCAN is receiving a message 1. The ﬂag is controlled by the receiver front end. This bit is not valid in loopback mode.

0 MSCAN is transmitting or idle

1 MSCAN is receiving a message (including when arbitration is lost)

CAN Stops in Wait Mode — Enabling this bit allows for lower power consumption in wait mode by disabling all the clocks at the CPU bus interface to the MSCAN module.

0 The module is not affected during wait mode

1 The module ceases to be clocked during wait mode

Synchronized Status — This read-only ﬂag indicates whether the MSCAN is synchronized to the CAN bus and able to participate in the communication process. It is set and cleared by the MSCAN.

0 MSCAN is not synchronized to the CAN bus

1 MSCAN is synchronized to the CAN bus

Timer Enable— This bit activates an internal 16-bit wide free running timer which is clocked by the bit clock rate. If the timer is enabled, a 16-bit time stamp will be assigned to each transmitted/received message within the active TX/RX buffer. Right after the EOF of a valid message on the CAN bus, the time stamp is written to the highest bytes (0x000E, 0x000F) in the appropriate buffer (seeSection 16.3.3, “Programmer’s Model of Message Storage”). The internal timer is reset (all bits set to 0) when disabled. This bit is held low in initialization mode.

0 Disable internal MSCAN timer

1 Enable internal MSCAN timer

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16.3.2.2 MSCAN Control Register 1 (CANCTL1)

The CANCTL1 register provides various control bits and handshake status information of the MSCAN module as described below. WUPE3 Wake-Up Enable — This conﬁguration bit allows the MSCAN to restart from sleep mode or from power down mode (entered from sleep) when trafﬁc on CAN is detected (seeSection 16.4.5.5, “MSCAN Sleep Mode”). This bit must be conﬁgured before sleep mode entry for the selected function to take effect.

0 Wake-up disabled — The MSCAN ignores trafﬁc on CAN

1 Wake-up enabled — The MSCAN is able to restart

Sleep Mode Request — This bit requests the MSCAN to enter sleep mode, which is an internal power saving mode (see Section 16.4.5.5, “MSCAN Sleep Mode”). The sleep mode request is serviced when the CAN bus is idle, i.e., the module is not receiving a message and all transmit buffers are empty. The module indicates entry to sleep mode by setting SLPAK = 1 (seeSection 16.3.2.2, “MSCAN Control Register 1 (CANCTL1)”). SLPRQ cannot be set while the WUPIF ﬂag is set (seeSection 16.3.2.5, “MSCAN Receiver Flag Register (CANRFLG)”). Sleep mode will be active until SLPRQ is cleared by the CPU or, depending on the setting of WUPE, the MSCAN detects activity on the CAN bus and clears SLPRQ itself.

0 Running — The MSCAN functions normally

1 Sleep mode request — The MSCAN enters sleep mode when CAN bus idle

5,6 Initialization Mode Request — When this bit is set by the CPU, the MSCAN skips to initialization mode (see Section 16.4.4.5, “MSCAN Initialization Mode”). Any ongoing transmission or reception is aborted and synchronization to the CAN bus is lost. The module indicates entry to initialization mode by setting INITAK = 1 (Section 16.3.2.2, “MSCAN Control Register 1 (CANCTL1)”). The following registers enter their hard reset state and restore their default values: CANCTL07, CANRFLG8, CANRIER9, CANTFLG, CANTIER, CANTARQ, CANTAAK, and CANTBSEL. The registers CANCTL1, CANBTR0, CANBTR1, CANIDAC, CANIDAR0-7, and CANIDMR0-7 can only be written by the CPU when the MSCAN is in initialization mode (INITRQ = 1 and INITAK = 1). The values of the error counters are not affected by initialization mode. When this bit is cleared by the CPU, the MSCAN restarts and then tries to synchronize to the CAN bus. If the MSCAN is not in bus-off state, it synchronizes after 11 consecutive recessive bits on the CAN bus; if the MSCAN is in bus-off state, it continues to wait for 128 occurrences of 11 consecutive recessive bits. Writing to other bits in CANCTL0, CANRFLG, CANRIER, CANTFLG, or CANTIER must be done only after initialization mode is exited, which is INITRQ = 0 and INITAK = 0.

0 Normal operation

1 MSCAN in initialization mode

1 See the Bosch CAN 2.0A/B speciﬁcation for a detailed deﬁnition of transmitter and receiver states. 2 In order to protect from accidentally violating the CAN protocol, TXCAN is immediately forced to a recessive state when the in Stop Mode”) 3 The CPU has to make sure that the WUPE register and the WUPIE wake-up interrupt enable register (see Section 16.3.2.6, “MSCAN Receiver Interrupt Enable Register (CANRIER)) is enabled, if the recovery mechanism from stop or wait is required. 4 The CPU cannot clear SLPRQ before the MSCAN has entered sleep mode (SLPRQ = 1 and SLPAK = 1). 5 The CPU cannot clear INITRQ before the MSCAN has entered initialization mode (INITRQ = 1 and INITAK = 1). 6 In order to protect from accidentally violating the CAN protocol, TXCAN is immediately forced to a recessive state when the initialization mode is requested by the CPU. Thus, the recommended procedure is to bring the MSCAN into sleep mode (SLPRQ = 1 and SLPAK = 1) before requesting initialization mode. 7 Not including WUPE, INITRQ, and SLPRQ. 8 TSTAT1 and TSTAT0 are not affected by initialization mode. 9 RSTAT1 and RSTAT0 are not affected by initialization mode. Table 16-3. CANCTL0 Register Field Descriptions (continued) Field Description

Freescale’s Scalable Controller Area Network (S12MSCANV3) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 485 Module Base + 0x0001 Access: User read/write1 Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1), except CANE which is write once in normal and anytime in special system operation modes when the MSCAN is in initialization mode (INITRQ = 1 and INITAK = 1) 76543210 R CANE CLKSRC LOOPB LISTEN BORM WUPM SLPAK INITAK W Reset: 00010001 = Unimplemented Figure 16-5. MSCAN Control Register 1 (CANCTL1) Table 16-4. CANCTL1 Register Field Descriptions Field Description CANE MSCAN Enable

0 MSCAN module is disabled

1 MSCAN module is enabled

MSCAN Clock Source— This bit deﬁnes the clock source for the MSCAN module (only for systems with a clock

0 MSCAN clock source is the oscillator clock

1 MSCAN clock source is the bus clock

Loopback Self Test Mode— When this bit is set, the MSCAN performs an internal loopback which can be used for self test operation. The bit stream output of the transmitter is fed back to the receiver internally. The RXCAN input is ignored and the TXCAN output goes to the recessive state (logic 1). The MSCAN behaves as it does normally when transmitting and treats its own transmitted message as a message received from a remote node. In this state, the MSCAN ignores the bit sent during the ACK slot in the CAN frame acknowledge ﬁeld to ensure proper reception of its own message. Both transmit and receive interrupts are generated.

0 Loopback self test disabled

1 Loopback self test enabled

Listen Only Mode — This bit conﬁgures the MSCAN as a CAN bus monitor. When LISTEN is set, all valid CAN messages with matching ID are received, but no acknowledgement or error frames are sent out (see applications which require “hot plugging” or throughput analysis. The MSCAN is unable to transmit any messages when listen only mode is active.

1 Listen only mode activated

Bus-Off Recovery Mode — This bit conﬁgures the bus-off state recovery mode of the MSCAN. Refer to Section 16.5.2, “Bus-Off Recovery,” for details. 0 Automatic bus-off recovery (see Bosch CAN 2.0A/B protocol speciﬁcation)

1 Bus-off recovery upon user request

Wake-Up Mode — If WUPE in CANCTL0 is enabled, this bit deﬁnes whether the integrated low-pass ﬁlter is applied to protect the MSCAN from spurious wake-up (see Section 16.4.5.5, “MSCAN Sleep Mode”).

0 MSCAN wakes up on any dominant level on the CAN bus

1 MSCAN wakes up only in case of a dominant pulse on the CAN bus that has a length of T

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16.3.2.3 MSCAN Bus Timing Register 0 (CANBTR0)

The CANBTR0 register conﬁgures various CAN bus timing parameters of the MSCAN module. SLPAK Sleep Mode Acknowledge — This ﬂag indicates whether the MSCAN module has entered sleep mode (see Sleep mode is active when SLPRQ = 1 and SLPAK = 1. Depending on the setting of WUPE, the MSCAN will clear the ﬂag if it detects activity on the CAN bus while in sleep mode.

0 Running — The MSCAN operates normally

1 Sleep mode active — The MSCAN has entered sleep mode

Initialization Mode Acknowledge — This ﬂag indicates whether the MSCAN module is in initialization mode (see Section 16.4.4.5, “MSCAN Initialization Mode”). It is used as a handshake ﬂag for the INITRQ initialization mode request. Initialization mode is active when INITRQ = 1 and INITAK = 1. The registers CANCTL1, CANBTR0, CANBTR1, CANIDAC, CANIDAR0–CANIDAR7, and CANIDMR0–CANIDMR7 can be written only by the CPU when the MSCAN is in initialization mode.

1 Initialization mode active — The MSCAN has entered initialization mode

Module Base + 0x0002 Access: User read/write Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1) 76543210 R SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 W Reset: 00000000 Figure 16-6. MSCAN Bus Timing Register 0 (CANBTR0) Table 16-5. CANBTR0 Register Field Descriptions Field Description 7-6 SJW[1:0] Synchronization Jump Width— The synchronization jump width deﬁnes the maximum number of time quanta (Tq) clock cycles a bit can be shortened or lengthened to achieve resynchronization to data transitions on the CAN bus (see Table 16-6). 5-0 BRP[5:0] Baud Rate Prescaler — These bits determine the time quanta (Tq) clock which is used to build up the bit timing (see Table 16-7). Table 16-6. Synchronization Jump Width SJW1 SJW0 Synchronization Jump Width 0 0 1 Tq clock cycle 0 1 2 Tq clock cycles 1 0 3 Tq clock cycles 1 1 4 Tq clock cycles Table 16-4. CANCTL1 Register Field Descriptions (continued) Field Description

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16.3.2.4 MSCAN Bus Timing Register 1 (CANBTR1)

The CANBTR1 register conﬁgures various CAN bus timing parameters of the MSCAN module. Table 16-7. Baud Rate Prescaler BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 Prescaler value (P) 000000 1 000001 2 000010 3 000011 4 :::::: : 111111 6 4 Module Base + 0x0003 Access: User read/write Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1) 76543210 R SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 W Reset: 00000000 Figure 16-7. MSCAN Bus Timing Register 1 (CANBTR1) Table 16-8. CANBTR1 Register Field Descriptions Field Description SAMP Sampling — This bit determines the number of CAN bus samples taken per bit time. 0 One sample per bit.

1 Three samples per bit

If SAMP = 0, the resulting bit value is equal to the value of the single bit positioned at the sample point. If SAMP = 1, the resulting bit value is determined by using majority rule on the three total samples. For higher bit rates, it is recommended that only one sample is taken per bit time (SAMP = 0). 1 In this case, PHASE_SEG1 must be at least 2 time quanta (Tq). 6-4 TSEG2[2:0] Time Segment 2— Time segments within the bit time ﬁx the number of clock cycles per bit time and the location of the sample point (see Figure 16-44). Time segment 2 (TSEG2) values are programmable as shown in Table 16-9. 3-0 TSEG1[3:0] Time Segment 1— Time segments within the bit time ﬁx the number of clock cycles per bit time and the location of the sample point (see Figure 16-44). Time segment 1 (TSEG1) values are programmable as shown in Table 16-10.

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The bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of time quanta (Tq) clock cycles per bit (as shown in Table 16-9 and Table 16-10). Eqn. 16-1

16.3.2.5 MSCAN Receiver Flag Register (CANRFLG)

A ﬂag can be cleared only by software (writing a 1 to the corresponding bit position) when the condition which caused the setting is no longer valid. Every ﬂag has an associated interrupt enable bit in the CANRIER register. Table 16-9. Time Segment 2 Values TSEG22 TSEG21 TSEG20 Time Segment 2 0 0 0 1 Tq clock cycle1 1 This setting is not valid. Please refer to Table 16-37 for valid settings. 0 0 1 2 Tq clock cycles ::: : 1 1 0 7 Tq clock cycles 1 1 1 8 Tq clock cycles Table 16-10. Time Segment 1 Values TSEG13 TSEG12 TSEG11 TSEG10 Time segment 1 0 0 0 0 1 Tq clock cycle1 1 This setting is not valid. Please refer to Table 16-37 for valid settings. 0 0 0 1 2 Tq clock cycles1 0 0 1 0 3 Tq clock cycles1 0 0 1 1 4 Tq clock cycles :::: : 1 1 1 0 15 Tq clock cycles 1 1 1 1 16 Tq clock cycles Module Base + 0x0004 Access: User read/write 76543210 R WUPIF CSCIF RSTAT1 RSTAT0 TSTAT1 TSTAT0 OVRIF RXF W Reset: 00000000 = Unimplemented Figure 16-8. MSCAN Receiver Flag Register (CANRFLG) Bit Time Prescaler value() fCANCLK

Freescale’s Scalable Controller Area Network (S12MSCANV3) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 489 NOTE The CANRFLG register is held in the reset state1 when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable again as soon as the initialization mode is exited (INITRQ = 0 and INITAK = 0). Write: Anytime when not in initialization mode, except RSTAT[1:0] and TSTAT[1:0] ﬂags which are read-only; write of 1 clears ﬂag; write of 0 is ignored 1. The RSTAT[1:0], TSTAT[1:0] bits are not affected by initialization mode. Table 16-11. CANRFLG Register Field Descriptions Field Description WUPIF Wake-Up Interrupt Flag — If the MSCAN detects CAN bus activity while in sleep mode (see Section 16.4.5.5, “MSCAN Sleep Mode,”) and WUPE = 1 in CANTCTL0 (seeSection 16.3.2.1, “MSCAN Control Register 0 (CANCTL0)”), the module will set WUPIF. If not masked, a wake-up interrupt is pending while this ﬂag is set.

0 No wake-up activity observed while in sleep mode

1 MSCAN detected activity on the CAN bus and requested wake-up

CAN Status Change Interrupt Flag — This ﬂag is set when the MSCAN changes its current CAN bus status due to the actual value of the transmit error counter (TEC) and the receive error counter (REC). An additional 4-bit (RSTAT[1:0], TSTAT[1:0]) status register, which is split into separate sections for TEC/REC, informs the system on the actual CAN bus status (see Section 16.3.2.6, “MSCAN Receiver Interrupt Enable Register (CANRIER)”). If not masked, an error interrupt is pending while this ﬂag is set. CSCIF provides a blocking interrupt. That guarantees that the receiver/transmitter status bits (RSTAT/TSTAT) are only updated when no CAN status change interrupt is pending. If the TECs/RECs change their current value after the CSCIF is asserted, which would cause an additional state change in the RSTAT/TSTAT bits, these bits keep their status until the current CSCIF interrupt is cleared again.

0 No change in CAN bus status occurred since last interrupt

1 MSCAN changed current CAN bus status

RSTAT[1:0] Receiver Status Bits — The values of the error counters control the actual CAN bus status of the MSCAN. As soon as the status change interrupt ﬂag (CSCIF) is set, these bits indicate the appropriate receiver related CAN bus status of the MSCAN. The coding for the bits RSTAT1, RSTAT0 is:

00 RxOK: 0 ≤ receive error counter ≤ 96

01 RxWRN: 96 < receive error counter ≤ 127

10 RxERR: 127 < receive error counter

11 Bus-off

1: transmit error counter > 255 3-2 TSTAT[1:0] Transmitter Status Bits — The values of the error counters control the actual CAN bus status of the MSCAN. As soon as the status change interrupt ﬂag (CSCIF) is set, these bits indicate the appropriate transmitter related CAN bus status of the MSCAN. The coding for the bits TSTAT1, TSTAT0 is:

00 TxOK: 0 ≤ transmit error counter ≤ 96

01 TxWRN: 96 < transmit error counter ≤ 127

10 TxERR: 127 < transmit error counter ≤ 255

11 Bus-Off: transmit error counter > 255

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16.3.2.6 MSCAN Receiver Interrupt Enable Register (CANRIER)

This register contains the interrupt enable bits for the interrupt ﬂags described in the CANRFLG register. NOTE The CANRIER register is held in the reset state when the initialization mode is active (INITRQ=1 and INITAK=1). This register is writable when not in initialization mode (INITRQ=0 and INITAK=0). The RSTATE[1:0], TSTATE[1:0] bits are not affected by initialization mode. OVRIF Overrun Interrupt Flag— This ﬂag is set when a data overrun condition occurs. If not masked, an error interrupt is pending while this ﬂag is set.

0 No data overrun condition

1 A data overrun detected

Receive Buffer Full Flag — RXF is set by the MSCAN when a new message is shifted in the receiver FIFO. This ﬂag indicates whether the shifted buffer is loaded with a correctly received message (matching identiﬁer, matching cyclic redundancy code (CRC) and no other errors detected). After the CPU has read that message from the RxFG buffer in the receiver FIFO, the RXF ﬂag must be cleared to release the buffer. A set RXF ﬂag prohibits the shifting of the next FIFO entry into the foreground buffer (RxFG). If not masked, a receive interrupt is pending while this ﬂag is set.

0 No new message available within the RxFG

1 The receiver FIFO is not empty. A new message is available in the RxFG 1 Redundant Information for the most critical CAN bus status which is “bus-off”. This only occurs if the Tx error counter exceeds a number of 255 errors. Bus-off affects the receiver state. As soon as the transmitter leaves its bus-off state the receiver state skips to RxOK too. Refer also to TSTAT[1:0] coding in this register. 2 To ensure data integrity, do not read the receive buffer registers while the RXF ﬂag is cleared. For MCUs with dual CPUs, reading the receive buffer registers while the RXF ﬂag is cleared may result in a CPU fault condition. Module Base + 0x0005 Access: User read/write Write: Anytime when not in initialization mode 76543210 R WUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE W Reset: 00000000 Figure 16-9. MSCAN Receiver Interrupt Enable Register (CANRIER) Table 16-11. CANRFLG Register Field Descriptions (continued) Field Description

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16.3.2.7 MSCAN Transmitter Flag Register (CANTFLG)

The transmit buffer empty ﬂags each have an associated interrupt enable bit in the CANTIER register. Table 16-12. CANRIER Register Field Descriptions Field Description WUPIE1 1 WUPIE and WUPE (see Section 16.3.2.1, “MSCAN Control Register 0 (CANCTL0)”) must both be enabled if the recovery mechanism from stop or wait is required. Wake-Up Interrupt Enable 0 No interrupt request is generated from this event. 1 A wake-up event causes a Wake-Up interrupt request. CSCIE CAN Status Change Interrupt Enable 0 No interrupt request is generated from this event. 1 A CAN Status Change event causes an error interrupt request. 5-4 RSTATE[1:0] Receiver Status Change Enable— These RSTAT enable bits control the sensitivity level in which receiver state changes are causing CSCIF interrupts. Independent of the chosen sensitivity level the RSTAT ﬂags continue to indicate the actual receiver state and are only updated if no CSCIF interrupt is pending. 00 Do not generate any CSCIF interrupt caused by receiver state changes. 01 Generate CSCIF interrupt only if the receiver enters or leaves “bus-off” state. Discard other receiver state changes for generating CSCIF interrupt.

10 Generate CSCIF interrupt only if the receiver enters or leaves “RxErr” or “bus-off”

2 state. Discard other receiver state changes for generating CSCIF interrupt. 11 Generate CSCIF interrupt on all state changes. 2 Bus-off state is only deﬁned for transmitters by the CAN standard (see Bosch CAN 2.0A/B protocol speciﬁcation). Because the only possible state change for the transmitter from bus-off to TxOK also forces the receiver to skip its current state to RxOK, the coding of the RXSTAT[1:0] ﬂags deﬁne an additional bus-off state for the receiver (seeSection 16.3.2.5, “MSCAN Receiver Flag Register (CANRFLG)”). 3-2 TSTATE[1:0] Transmitter Status Change Enable— These TSTAT enable bits control the sensitivity level in which transmitter state changes are causing CSCIF interrupts. Independent of the chosen sensitivity level, the TSTAT ﬂags continue to indicate the actual transmitter state and are only updated if no CSCIF interrupt is pending. 00 Do not generate any CSCIF interrupt caused by transmitter state changes. 01 Generate CSCIF interrupt only if the transmitter enters or leaves “bus-off” state. Discard other transmitter state changes for generating CSCIF interrupt. 10 Generate CSCIF interrupt only if the transmitter enters or leaves “TxErr” or “bus-off” state. Discard other transmitter state changes for generating CSCIF interrupt. 11 Generate CSCIF interrupt on all state changes. OVRIE Overrun Interrupt Enable 0 No interrupt request is generated from this event. 1 An overrun event causes an error interrupt request. RXFIE Receiver Full Interrupt Enable 0 No interrupt request is generated from this event. 1 A receive buffer full (successful message reception) event causes a receiver interrupt request.

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The CANTFLG register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable when not in initialization mode (INITRQ = 0 and INITAK = 0).

16.3.2.8 MSCAN Transmitter Interrupt Enable Register (CANTIER)

This register contains the interrupt enable bits for the transmit buffer empty interrupt ﬂags. Module Base + 0x0006 Access: User read/write1 Write: Anytime when not in initialization mode; write of 1 clears ﬂag, write of 0 is ignored 76543210 R0 0 0 00 TXE2 TXE1 TXE0 W Reset: 00000111 = Unimplemented Figure 16-10. MSCAN Transmitter Flag Register (CANTFLG) Table 16-13. CANTFLG Register Field Descriptions Field Description 2-0 TXE[2:0] Transmitter Buffer Empty— This ﬂag indicates that the associated transmit message buffer is empty, and thus not scheduled for transmission. The CPU must clear the ﬂag after a message is set up in the transmit buffer and is due for transmission. The MSCAN sets the ﬂag after the message is sent successfully. The ﬂag is also set by the MSCAN when the transmission request is successfully aborted due to a pending abort request (see Section 16.3.2.9, “MSCAN Transmitter Message Abort Request Register (CANTARQ)”). If not masked, a transmit interrupt is pending while this ﬂag is set. Clearing a TXEx ﬂag also clears the corresponding ABTAKx (see Section 16.3.2.10, “MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK)”). When a TXEx ﬂag is set, the corresponding ABTRQx bit is cleared (see Section 16.3.2.9, “MSCAN Transmitter Message Abort Request Register (CANTARQ)”). When listen-mode is active (see Section 16.3.2.2, “MSCAN Control Register 1 (CANCTL1)”) the TXEx ﬂags cannot be cleared and no transmission is started. Read and write accesses to the transmit buffer will be blocked, if the corresponding TXEx bit is cleared (TXEx = 0) and the buffer is scheduled for transmission.

0 The associated message buffer is full (loaded with a message due for transmission)

1 The associated message buffer is empty (not scheduled)

Module Base + 0x0007 Access: User read/write 76543210 R 00000 TXEIE2 TXEIE1 TXEIE0 W Reset: 00000000 = Unimplemented Figure 16-11. MSCAN Transmitter Interrupt Enable Register (CANTIER)

Freescale’s Scalable Controller Area Network (S12MSCANV3) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 493 NOTE The CANTIER register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable when not in initialization mode (INITRQ = 0 and INITAK = 0).

16.3.2.9 MSCAN Transmitter Message Abort Request Register (CANTARQ)

The CANTARQ register allows abort request of queued messages as described below. NOTE The CANTARQ register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is writable when not in initialization mode (INITRQ = 0 and INITAK = 0). Write: Anytime when not in initialization mode Table 16-14. CANTIER Register Field Descriptions Field Description 2-0 TXEIE[2:0] Transmitter Empty Interrupt Enable 0 No interrupt request is generated from this event. 1 A transmitter empty (transmit buffer available for transmission) event causes a transmitter empty interrupt request. Module Base + 0x0008 Access: User read/write Write: Anytime when not in initialization mode 76543210 R 00000 ABTRQ2 ABTRQ1 ABTRQ0 W Reset: 00000000 = Unimplemented Figure 16-12. MSCAN Transmitter Message Abort Request Register (CANTARQ) Table 16-15. CANTARQ Register Field Descriptions Field Description 2-0 ABTRQ[2:0] Abort Request — The CPU sets the ABTRQx bit to request that a scheduled message buffer (TXEx = 0) be aborted. The MSCAN grants the request if the message has not already started transmission, or if the transmission is not successful (lost arbitration or error). When a message is aborted, the associated TXE (see Section 16.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and abort acknowledge ﬂags (ABTAK, see Section 16.3.2.10, “MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK)”) are set and a transmit interrupt occurs if enabled. The CPU cannot reset ABTRQx. ABTRQx is reset whenever the associated TXE ﬂag is set.

0 No abort request

1 Abort request pending

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16.3.2.10 MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK)

The CANTAAK register indicates the successful abort of a queued message, if requested by the appropriate bits in the CANTARQ register. NOTE The CANTAAK register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1).

16.3.2.11 MSCAN Transmit Buffer Selection Register (CANTBSEL)

The CANTBSEL register allows the selection of the actual transmit message buffer, which then will be accessible in the CANTXFG register space. Module Base + 0x0009 Access: User read/write1 Write: Unimplemented 76543210 R 00000 ABTAK2 ABTAK1 ABTAK0 W Reset: 00000000 = Unimplemented Figure 16-13. MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK) Table 16-16. CANTAAK Register Field Descriptions Field Description 2-0 ABTAK[2:0] Abort Acknowledge — This ﬂag acknowledges that a message was aborted due to a pending abort request from the CPU. After a particular message buffer is ﬂagged empty, this ﬂag can be used by the application software to identify whether the message was aborted successfully or was sent anyway. The ABTAKx ﬂag is cleared whenever the corresponding TXE ﬂag is cleared. 0 The message was not aborted. 1 The message was aborted. Module Base + 0x000A Access: User read/write

1 Read: Find the lowest ordered bit set to 1, all other bits will be read as 0

Write: Anytime when not in initialization mode 76543210 R 00000 TX2 TX1 TX0 W Reset: 00000000 = Unimplemented Figure 16-14. MSCAN Transmit Buffer Selection Register (CANTBSEL)

Freescale’s Scalable Controller Area Network (S12MSCANV3) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 495 NOTE The CANTBSEL register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK=1). This register is writable when not in initialization mode (INITRQ = 0 and INITAK = 0). The following gives a short programming example of the usage of the CANTBSEL register: To get the next available transmit buffer, application software must read the CANTFLG register and write this value back into the CANTBSEL register. In this example Tx buffers TX1 and TX2 are available. The value read from CANTFLG is therefore 0b0000_0110. When writing this value back to CANTBSEL, the Tx buffer TX1 is selected in the CANTXFG because the lowest numbered bit set to 1 is at bit position 1. Reading back this value out of CANTBSEL results in 0b0000_0010, because only the lowest numbered bit position set to 1 is presented. This mechanism eases the application software’s selection of the next available Tx buffer.

LDAA CANTFLG; value read is 0b0000_0110
STAA CANTBSEL; value written is 0b0000_0110
LDAA CANTBSEL; value read is 0b0000_0010 If all transmit message buffers are deselected, no accesses are allowed to the CANTXFG registers.

16.3.2.12 MSCAN Identiﬁer Acceptance Control Register (CANIDAC)

The CANIDAC register is used for identiﬁer acceptance control as described below. Table 16-17. CANTBSEL Register Field Descriptions Field Description 2-0 TX[2:0] Transmit Buffer Select — The lowest numbered bit places the respective transmit buffer in the CANTXFG register space (e.g., TX1 = 1 and TX0 = 1 selects transmit buffer TX0; TX1 = 1 and TX0 = 0 selects transmit buffer TX1). Read and write accesses to the selected transmit buffer will be blocked, if the corresponding TXEx bit is cleared and the buffer is scheduled for transmission (see Section 16.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”).

0 The associated message buffer is deselected

1 The associated message buffer is selected, if lowest numbered bit

Module Base + 0x000B Access: User read/write Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1), except bits IDHITx, which are read-only 76543210 R0 0 IDAM1 IDAM0 W Reset: 00000000 = Unimplemented Figure 16-15. MSCAN Identiﬁer Acceptance Control Register (CANIDAC)

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The IDHITx indicators are always related to the message in the foreground buffer (RxFG). When a message gets shifted into the foreground buffer of the receiver FIFO the indicators are updated as well.

16.3.2.13 MSCAN Reserved Register

This register is reserved for factory testing of the MSCAN module and is not available in normal system operating modes. Table 16-18. CANIDAC Register Field Descriptions Field Description 5-4 IDAM[1:0] Identiﬁer Acceptance Mode — The CPU sets these ﬂags to deﬁne the identiﬁer acceptance ﬁlter organization (see Section 16.4.3, “Identiﬁer Acceptance Filter”).Table 16-19summarizes the different settings. In ﬁlter closed mode, no message is accepted such that the foreground buffer is never reloaded. 2-0 IDHIT[2:0] Identiﬁer Acceptance Hit Indicator — The MSCAN sets these ﬂags to indicate an identiﬁer acceptance hit (see Section 16.4.3, “Identiﬁer Acceptance Filter”). Table 16-20 summarizes the different settings. Table 16-19. Identiﬁer Acceptance Mode Settings IDAM1 IDAM0 Identiﬁer Acceptance Mode 0 0 Two 32-bit acceptance ﬁlters 0 1 Four 16-bit acceptance ﬁlters 1 0 Eight 8-bit acceptance ﬁlters 1 1 Filter closed Table 16-20. Identiﬁer Acceptance Hit Indication IDHIT2 IDHIT1 IDHIT0 Identiﬁer Acceptance Hit 0 0 0 Filter 0 hit 0 0 1 Filter 1 hit 0 1 0 Filter 2 hit 0 1 1 Filter 3 hit 1 0 0 Filter 4 hit 1 0 1 Filter 5 hit 1 1 0 Filter 6 hit 1 1 1 Filter 7 hit

Freescale’s Scalable Controller Area Network (S12MSCANV3) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 497 NOTE Writing to this register when in special system operating modes can alter the MSCAN functionality.

16.3.2.14 MSCAN Miscellaneous Register (CANMISC)

This register provides additional features.

16.3.2.15 MSCAN Receive Error Counter (CANRXERR)

This register reﬂects the status of the MSCAN receive error counter. Module Base + 0x000C to Module Base + 0x000D Access: User read/write 1

1 Read: Always reads zero in normal system operation modes

Write: Unimplemented in normal system operation modes 76543210 R 00000000 W Reset: 00000000 = Unimplemented Figure 16-16. MSCAN Reserved Register Module Base + 0x000D Access: User read/write1 Write: Anytime; write of ‘1’ clears ﬂag; write of ‘0’ ignored 76543210 R 0000000 BOHOLD W Reset: 00000000 = Unimplemented Figure 16-17. MSCAN Miscellaneous Register (CANMISC) Table 16-21. CANMISC Register Field Descriptions Field Description BOHOLD Bus-off State Hold Until User Request — If BORM is set in MSCAN Control Register 1 (CANCTL1), this bit indicates whether the module has entered the bus-off state. Clearing this bit requests the recovery from bus-off. Refer to Section 16.5.2, “Bus-Off Recovery,” for details.

0 Module is not bus-off or recovery has been requested by user in bus-off state

1 Module is bus-off and holds this state until user request

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Reading this register when in any other mode other than sleep or initialization mode may return an incorrect value. For MCUs with dual CPUs, this may result in a CPU fault condition. Writing to this register when in special modes can alter the MSCAN functionality.

16.3.2.16 MSCAN Transmit Error Counter (CANTXERR)

This register reﬂects the status of the MSCAN transmit error counter. NOTE Reading this register when in any other mode other than sleep or initialization mode, may return an incorrect value. For MCUs with dual CPUs, this may result in a CPU fault condition. Writing to this register when in special modes can alter the MSCAN functionality. Module Base + 0x000E Access: User read/write1 1 Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and INITAK = 1) Write: Unimplemented 76543210 R RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 W Reset: 00000000 = Unimplemented Figure 16-18. MSCAN Receive Error Counter (CANRXERR) Module Base + 0x000F Access: User read/write1 1 Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and INITAK = 1) Write: Unimplemented 76543210 R TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 W Reset: 00000000 = Unimplemented Figure 16-19. MSCAN Transmit Error Counter (CANTXERR)

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16.3.2.17 MSCAN Identiﬁer Acceptance Registers (CANIDAR0-7)

On reception, each message is written into the background receive buffer. The CPU is only signalled to read the message if it passes the criteria in the identiﬁer acceptance and identiﬁer mask registers (accepted); otherwise, the message is overwritten by the next message (dropped). The acceptance registers of the MSCAN are applied on the IDR0–IDR3 registers (see Section 16.3.3.1, “Identiﬁer Registers (IDR0–IDR3)”) of incoming messages in a bit by bit manner (see Section 16.4.3, “Identiﬁer Acceptance Filter”). For extended identiﬁers, all four acceptance and mask registers are applied. For standard identiﬁers, only the ﬁrst two (CANIDAR0/1, CANIDMR0/1) are applied. Module Base + 0x0010 to Module Base + 0x0013 Access: User read/write 1 Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1) 76543210 R AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 W Reset 00000000 Figure 16-20. MSCAN Identiﬁer Acceptance Registers (First Bank) — CANIDAR0–CANIDAR3 Table 16-22. CANIDAR0–CANIDAR3 Register Field Descriptions Field Description 7-0 AC[7:0] Acceptance Code Bits — AC[7:0] comprise a user-deﬁned sequence of bits with which the corresponding bits of the related identiﬁer register (IDRn) of the receive message buffer are compared. The result of this comparison is then masked with the corresponding identiﬁer mask register. Module Base + 0x0018 to Module Base + 0x001B Access: User read/write Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1) 76543210 R AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 W Reset 00000000 Figure 16-21. MSCAN Identiﬁer Acceptance Registers (Second Bank) — CANIDAR4–CANIDAR7

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16.3.2.18 MSCAN Identiﬁer Mask Registers (CANIDMR0–CANIDMR7)

The identiﬁer mask register speciﬁes which of the corresponding bits in the identiﬁer acceptance register are relevant for acceptance ﬁltering. To receive standard identiﬁers in 32 bit ﬁlter mode, it is required to program the last three bits (AM[2:0]) in the mask registers CANIDMR1 and CANIDMR5 to “don’t care.” To receive standard identiﬁers in 16 bit ﬁlter mode, it is required to program the last three bits (AM[2:0]) in the mask registers CANIDMR1, CANIDMR3, CANIDMR5, and CANIDMR7 to “don’t care.” Table 16-23. CANIDAR4–CANIDAR7 Register Field Descriptions Field Description 7-0 AC[7:0] Acceptance Code Bits — AC[7:0] comprise a user-deﬁned sequence of bits with which the corresponding bits of the related identiﬁer register (IDRn) of the receive message buffer are compared. The result of this comparison is then masked with the corresponding identiﬁer mask register. Module Base + 0x0014 to Module Base + 0x0017 Access: User read/write Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1) 76543210 R AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 W Reset 00000000 Figure 16-22. MSCAN Identiﬁer Mask Registers (First Bank) — CANIDMR0–CANIDMR3 Table 16-24. CANIDMR0–CANIDMR3 Register Field Descriptions Field Description 7-0 AM[7:0] Acceptance Mask Bits — If a particular bit in this register is cleared, this indicates that the corresponding bit in the identiﬁer acceptance register must be the same as its identiﬁer bit before a match is detected. The message is accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit in the identiﬁer acceptance register does not affect whether or not the message is accepted.

0 Match corresponding acceptance code register and identiﬁer bits

1 Ignore corresponding acceptance code register bit

Module Base + 0x001C to Module Base + 0x001F Access: User read/write 76543210 R AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 W Reset 00000000 Figure 16-23. MSCAN Identiﬁer Mask Registers (Second Bank) — CANIDMR4–CANIDMR7

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16.3.3 Programmer’s Model of Message Storage

The following section details the organization of the receive and transmit message buffers and the associated control registers. To simplify the programmer interface, the receive and transmit message buffers have the same outline. Each message buffer allocates 16 bytes in the memory map containing a 13 byte data structure. An additional transmit buffer priority register (TBPR) is deﬁned for the transmit buffers. Within the last two bytes of this memory map, the MSCAN stores a special 16-bit time stamp, which is sampled from an internal timer after successful transmission or reception of a message. This feature is only available for transmit and receiver buffers, if the TIME bit is set (see Section 16.3.2.1, “MSCAN Control Register 0 (CANCTL0)”). The time stamp register is written by the MSCAN. The CPU can only read these registers. Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1) Table 16-25. CANIDMR4–CANIDMR7 Register Field Descriptions Field Description 7-0 AM[7:0] Acceptance Mask Bits — If a particular bit in this register is cleared, this indicates that the corresponding bit in the identiﬁer acceptance register must be the same as its identiﬁer bit before a match is detected. The message is accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit in the identiﬁer acceptance register does not affect whether or not the message is accepted.

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Figure 16-24 shows the common 13-byte data structure of receive and transmit buffers for extended identiﬁers. The mapping of standard identiﬁers into the IDR registers is shown in Figure 16-25. All bits of the receive and transmit buffers are ‘x’ out of reset because of RAM-based implementation1. All reserved or unused bits of the receive and transmit buffers always read ‘x’. Table 16-26. Message Buffer Organization Offset Address Register Access 0x00X0 Identiﬁer Register 0 R/W 0x00X1 Identiﬁer Register 1 R/W 0x00X2 Identiﬁer Register 2 R/W 0x00X3 Identiﬁer Register 3 R/W 0x00X4 Data Segment Register 0 R/W 0x00X5 Data Segment Register 1 R/W 0x00X6 Data Segment Register 2 R/W 0x00X7 Data Segment Register 3 R/W 0x00X8 Data Segment Register 4 R/W 0x00X9 Data Segment Register 5 R/W 0x00XA Data Segment Register 6 R/W 0x00XB Data Segment Register 7 R/W 0x00XC Data Length Register R/W 0x00XD Transmit Buffer Priority Register

1 Not applicable for receive buffers

0x00XE Time Stamp Register (High Byte) R 0x00XF Time Stamp Register (Low Byte) R 1. Exception: The transmit buffer priority registers are 0 out of reset.

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Read:

For transmit buffers, anytime when TXEx ﬂag is set (see Section 16.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 16.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”).
For receive buffers, only when RXF ﬂag is set (see Section 16.3.2.5, “MSCAN Receiver Flag Register (CANRFLG)”). Write:
For transmit buffers, anytime when TXEx ﬂag is set (see Section 16.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 16.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”).
Unimplemented for receive buffers. Reset: Undeﬁned because of RAM-based implementation

16.3.3.1 Identiﬁer Registers (IDR0–IDR3)

The identiﬁer registers for an extended format identiﬁer consist of a total of 32 bits: ID[28:0], SRR, IDE, and RTR. The identiﬁer registers for a standard format identiﬁer consist of a total of 13 bits: ID[10:0], RTR, and IDE. = Unused, always read ‘x’ Figure 16-25. Receive/Transmit Message Buffer — Standard Identiﬁer Mapping Register Name Bit 7 654321 Bit 0 IDR0 0x00X0 R ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 W IDR1 0x00X1 R ID2 ID1 ID0 RTR IDE (=0) W IDR2 0x00X2 R W IDR3 0x00X3 R W = Unused, always read ‘x’ Figure 16-24. Receive/Transmit Message Buffer — Extended Identiﬁer Mapping (continued) Register Name Bit 7 654321 Bit0

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16.3.3.1.1 IDR0–IDR3 for Extended Identiﬁer Mapping

R ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 W Reset: xxxxxxxx Figure 16-26. Identiﬁer Register 0 (IDR0) — Extended Identiﬁer Mapping Table 16-27. IDR0 Register Field Descriptions — Extended Field Description 7-0 ID[28:21] Extended Format Identiﬁer — The identiﬁers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the most signiﬁcant bit and is transmitted ﬁrst on the CAN bus during the arbitration procedure. The priority of an identiﬁer is deﬁned to be highest for the smallest binary number. Module Base + 0x00X1 76543210 R ID20 ID19 ID18 SRR (=1) IDE (=1) ID17 ID16 ID15 W Reset: xxxxxxxx Figure 16-27. Identiﬁer Register 1 (IDR1) — Extended Identiﬁer Mapping Table 16-28. IDR1 Register Field Descriptions — Extended Field Description 7-5 ID[20:18] Extended Format Identiﬁer — The identiﬁers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the most signiﬁcant bit and is transmitted ﬁrst on the CAN bus during the arbitration procedure. The priority of an identiﬁer is deﬁned to be highest for the smallest binary number. SRR Substitute Remote Request — This ﬁxed recessive bit is used only in extended format. It must be set to 1 by the user for transmission buffers and is stored as received on the CAN bus for receive buffers. IDE ID Extended — This ﬂag indicates whether the extended or standard identiﬁer format is applied in this buffer. In the case of a receive buffer, the ﬂag is set as received and indicates to the CPU how to process the buffer identiﬁer registers. In the case of a transmit buffer, the ﬂag indicates to the MSCAN what type of identiﬁer to send.

0 Standard format (11 bit)

1 Extended format (29 bit)

ID[17:15] Extended Format Identiﬁer — The identiﬁers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the most signiﬁcant bit and is transmitted ﬁrst on the CAN bus during the arbitration procedure. The priority of an identiﬁer is deﬁned to be highest for the smallest binary number.

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R ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 W Reset: xxxxxxxx Figure 16-28. Identiﬁer Register 2 (IDR2) — Extended Identiﬁer Mapping Table 16-29. IDR2 Register Field Descriptions — Extended Field Description 7-0 ID[14:7] Extended Format Identiﬁer — The identiﬁers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the most signiﬁcant bit and is transmitted ﬁrst on the CAN bus during the arbitration procedure. The priority of an identiﬁer is deﬁned to be highest for the smallest binary number. Module Base + 0x00X3 76543210 R ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR W Reset: xxxxxxxx Figure 16-29. Identiﬁer Register 3 (IDR3) — Extended Identiﬁer Mapping Table 16-30. IDR3 Register Field Descriptions — Extended Field Description 7-1 ID[6:0] Extended Format Identiﬁer — The identiﬁers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the most signiﬁcant bit and is transmitted ﬁrst on the CAN bus during the arbitration procedure. The priority of an identiﬁer is deﬁned to be highest for the smallest binary number. RTR Remote Transmission Request — This ﬂag reﬂects the status of the remote transmission request bit in the CAN frame. In the case of a receive buffer, it indicates the status of the received frame and supports the transmission of an answering frame in software. In the case of a transmit buffer, this ﬂag deﬁnes the setting of the RTR bit to be sent.

0 Data frame

1 Remote frame

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16.3.3.1.2 IDR0–IDR3 for Standard Identiﬁer Mapping

R ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 W Reset: xxxxxxxx Figure 16-30. Identiﬁer Register 0 — Standard Mapping Table 16-31. IDR0 Register Field Descriptions — Standard Field Description 7-0 ID[10:3] Standard Format Identiﬁer — The identiﬁers consist of 11 bits (ID[10:0]) for the standard format. ID10 is the most signiﬁcant bit and is transmitted ﬁrst on the CAN bus during the arbitration procedure. The priority of an identiﬁer is deﬁned to be highest for the smallest binary number. See also ID bits in Table 16-32. Module Base + 0x00X1 76543210 R ID2 ID1 ID0 RTR IDE (=0) W Reset: xxxxxxxx = Unused; always read ‘x’ Figure 16-31. Identiﬁer Register 1 — Standard Mapping Table 16-32. IDR1 Register Field Descriptions Field Description 7-5 ID[2:0] Standard Format Identiﬁer — The identiﬁers consist of 11 bits (ID[10:0]) for the standard format. ID10 is the most signiﬁcant bit and is transmitted ﬁrst on the CAN bus during the arbitration procedure. The priority of an identiﬁer is deﬁned to be highest for the smallest binary number. See also ID bits in Table 16-31. RTR Remote Transmission Request — This ﬂag reﬂects the status of the Remote Transmission Request bit in the CAN frame. In the case of a receive buffer, it indicates the status of the received frame and supports the transmission of an answering frame in software. In the case of a transmit buffer, this ﬂag deﬁnes the setting of the RTR bit to be sent. ID Extended — This ﬂag indicates whether the extended or standard identiﬁer format is applied in this buffer. In the case of a receive buffer, the ﬂag is set as received and indicates to the CPU how to process the buffer identiﬁer registers. In the case of a transmit buffer, the ﬂag indicates to the MSCAN what type of identiﬁer to send.

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16.3.3.2 Data Segment Registers (DSR0-7)

The eight data segment registers, each with bits DB[7:0], contain the data to be transmitted or received. The number of bytes to be transmitted or received is determined by the data length code in the corresponding DLR register. Module Base + 0x00X2 76543210 R W Reset: xxxxxxxx = Unused; always read ‘x’ Figure 16-32. Identiﬁer Register 2 — Standard Mapping Module Base + 0x00X3 76543210 R W Reset: xxxxxxxx = Unused; always read ‘x’ Figure 16-33. Identiﬁer Register 3 — Standard Mapping Module Base + 0x00X4 to Module Base + 0x00XB 76543210 R DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 W Reset: xxxxxxxx Figure 16-34. Data Segment Registers (DSR0–DSR7) — Extended Identiﬁer Mapping Table 16-33. DSR0–DSR7 Register Field Descriptions Field Description 7-0 DB[7:0] Data bits 7-0

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16.3.3.3 Data Length Register (DLR)

This register keeps the data length ﬁeld of the CAN frame.

16.3.3.4 Transmit Buffer Priority Register (TBPR)

This register deﬁnes the local priority of the associated message buffer. The local priority is used for the internal prioritization process of the MSCAN and is deﬁned to be highest for the smallest binary number. The MSCAN implements the following internal prioritization mechanisms:

All transmission buffers with a cleared TXEx ﬂag participate in the prioritization immediately before the SOF (start of frame) is sent.
The transmission buffer with the lowest local priority ﬁeld wins the prioritization. Module Base + 0x00XC 76543210 R DLC3 DLC2 DLC1 DLC0 W Reset: xxxxxxxx = Unused; always read “x” Figure 16-35. Data Length Register (DLR) — Extended Identiﬁer Mapping Table 16-34. DLR Register Field Descriptions Field Description 3-0 DLC[3:0] Data Length Code Bits— The data length code contains the number of bytes (data byte count) of the respective message. During the transmission of a remote frame, the data length code is transmitted as programmed while the number of transmitted data bytes is always 0. The data byte count ranges from 0 to 8 for a data frame. Table 16-35 shows the effect of setting the DLC bits. Table 16-35. Data Length Codes Data Length Code Data Byte CountDLC3 DLC2 DLC1 DLC0 0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8

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In cases of more than one buffer having the same lowest priority, the message buffer with the lower index number wins.

16.3.3.5 Time Stamp Register (TSRH–TSRL)

If the TIME bit is enabled, the MSCAN will write a time stamp to the respective registers in the active transmit or receive buffer right after the EOF of a valid message on the CAN bus (seeSection 16.3.2.1, “MSCAN Control Register 0 (CANCTL0)”). In case of a transmission, the CPU can only read the time stamp after the respective transmit buffer has been ﬂagged empty. The timer value, which is used for stamping, is taken from a free running internal CAN bit clock. A timer overrun is not indicated by the MSCAN. The timer is reset (all bits set to 0) during initialization mode. The CPU can only read the time stamp registers. Module Base + 0x00XD Access: User read/write1 1 Read: Anytime when TXEx ﬂag is set (see Section 16.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 16.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”) Write: Anytime when TXEx ﬂag is set (see Section 16.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 16.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”) 76543210 R PRIO7 PRIO6 PRIO5 PRIO4 PRIO3 PRIO2 PRIO1 PRIO0 W Reset: 00000000 Figure 16-36. Transmit Buffer Priority Register (TBPR) Module Base + 0x00XE Access: User read/write1 1 Read: Anytime when TXEx ﬂag is set (see Section 16.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 16.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”) Write: Unimplemented 76543210 R TSR15 TSR14 TSR13 TSR12 TSR11 TSR10 TSR9 TSR8 W Reset: xxxxxxxx Figure 16-37. Time Stamp Register — High Byte (TSRH)

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16.4 Functional Description

16.4.1 General

This section provides a complete functional description of the MSCAN. Module Base + 0x00XF Access: User read/write1 1 Read: Anytime when TXEx ﬂag is set (see Section 16.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 16.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”) Write: Unimplemented 76543210 R TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSR0 W Reset: xxxxxxxx Figure 16-38. Time Stamp Register — Low Byte (TSRL)

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16.4.2 Message Storage

Figure 16-39. User Model for Message Buffer Organization The MSCAN facilitates a sophisticated message storage system which addresses the requirements of a broad range of network applications.

16.4.2.1 Message Transmit Background

Modern application layer software is built upon two fundamental assumptions: MSCAN Rx0 Rx1 CAN Receive / Transmit Engine Memory Mapped I/O CPU bus MSCAN Tx2 TXE2 PRIO Receiver Transmitter RxBG TxBG Tx0 TXE0 PRIO TxBG Tx1 PRIO TXE1 TxFG CPU bus Rx2 Rx3 Rx4 RXF RxFG

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Any CAN node is able to send out a stream of scheduled messages without releasing the CAN bus between the two messages. Such nodes arbitrate for the CAN bus immediately after sending the previous message and only release the CAN bus in case of lost arbitration.
The internal message queue within any CAN node is organized such that the highest priority message is sent out ﬁrst, if more than one message is ready to be sent. The behavior described in the bullets above cannot be achieved with a single transmit buffer. That buffer must be reloaded immediately after the previous message is sent. This loading process lasts a ﬁnite amount of time and must be completed within the inter-frame sequence (IFS) to be able to send an uninterrupted stream of messages. Even if this is feasible for limited CAN bus speeds, it requires that the CPU reacts with short latencies to the transmit interrupt. A double buffer scheme de-couples the reloading of the transmit buffer from the actual message sending and, therefore, reduces the reactiveness requirements of the CPU. Problems can arise if the sending of a message is ﬁnished while the CPU re-loads the second buffer. No buffer would then be ready for transmission, and the CAN bus would be released. At least three transmit buffers are required to meet the ﬁrst of the above requirements under all circumstances. The MSCAN has three transmit buffers. The second requirement calls for some sort of internal prioritization which the MSCAN implements with the “local priority” concept described in Section 16.4.2.2, “Transmit Structures.”

16.4.2.2 Transmit Structures

The MSCAN triple transmit buffer scheme optimizes real-time performance by allowing multiple messages to be set up in advance. The three buffers are arranged as shown in Figure 16-39. All three buffers have a 13-byte data structure similar to the outline of the receive buffers (see Section 16.3.3, “Programmer’s Model of Message Storage”). An additional Transmit Buffer Priority Register (TBPR) contains an 8-bit local priority ﬁeld (PRIO) (see Section 16.3.3.4, “Transmit Buffer Priority Register (TBPR)”). The remaining two bytes are used for time stamping of a message, if required (see Section 16.3.3.5, “Time Stamp Register (TSRH–TSRL)”). To transmit a message, the CPU must identify an available transmit buffer, which is indicated by a set transmitter buffer empty (TXEx) ﬂag (see Section 16.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)”). If a transmit buffer is available, the CPU must set a pointer to this buffer by writing to the CANTBSEL register (see Section 16.3.2.11, “MSCAN Transmit Buffer Selection Register (CANTBSEL)”). This makes the respective buffer accessible within the CANTXFG address space (see Section 16.3.3, “Programmer’s Model of Message Storage”). The algorithmic feature associated with the CANTBSEL register simpliﬁes the transmit buffer selection. In addition, this scheme makes the handler software simpler because only one address area is applicable for the transmit process, and the required address space is minimized. The CPU then stores the identiﬁer, the control bits, and the data content into one of the transmit buffers. Finally, the buffer is ﬂagged as ready for transmission by clearing the associated TXE ﬂag.

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The MSCAN then schedules the message for transmission and signals the successful transmission of the buffer by setting the associated TXE ﬂag. A transmit interrupt (seeSection 16.4.7.2, “Transmit Interrupt”) is generated1 when TXEx is set and can be used to drive the application software to re-load the buffer. If more than one buffer is scheduled for transmission when the CAN bus becomes available for arbitration, the MSCAN uses the local priority setting of the three buffers to determine the prioritization. For this purpose, every transmit buffer has an 8-bit local priority ﬁeld (PRIO). The application software programs this ﬁeld when the message is set up. The local priority reﬂects the priority of this particular message relative to the set of messages being transmitted from this node. The lowest binary value of the PRIO ﬁeld is deﬁned to be the highest priority. The internal scheduling process takes place whenever the MSCAN arbitrates for the CAN bus. This is also the case after the occurrence of a transmission error. When a high priority message is scheduled by the application software, it may become necessary to abort a lower priority message in one of the three transmit buffers. Because messages that are already in transmission cannot be aborted, the user must request the abort by setting the corresponding abort request bit (ABTRQ) (see Section 16.3.2.9, “MSCAN Transmitter Message Abort Request Register (CANTARQ)”.) The MSCAN then grants the request, if possible, by: 1. Setting the corresponding abort acknowledge ﬂag (ABTAK) in the CANTAAK register. 2. Setting the associated TXE ﬂag to release the buffer. 3. Generating a transmit interrupt. The transmit interrupt handler software can determine from the setting of the ABTAK ﬂag whether the message was aborted (ABTAK = 1) or sent (ABTAK = 0).

16.4.2.3 Receive Structures

The received messages are stored in a ﬁve stage input FIFO. The ﬁve message buffers are alternately mapped into a single memory area (see Figure 16-39). The background receive buffer (RxBG) is exclusively associated with the MSCAN, but the foreground receive buffer (RxFG) is addressable by the CPU (see Figure 16-39). This scheme simpliﬁes the handler software because only one address area is applicable for the receive process. All receive buffers have a size of 15 bytes to store the CAN control bits, the identiﬁer (standard or extended), the data contents, and a time stamp, if enabled (see Section 16.3.3, “Programmer’s Model of Message Storage”). The receiver full ﬂag (RXF) (see Section 16.3.2.5, “MSCAN Receiver Flag Register (CANRFLG)”) signals the status of the foreground receive buffer. When the buffer contains a correctly received message with a matching identiﬁer, this ﬂag is set. On reception, each message is checked to see whether it passes the ﬁlter (see Section 16.4.3, “Identiﬁer Acceptance Filter”) and simultaneously is written into the active RxBG. After successful reception of a valid message, the MSCAN shifts the content of RxBG into the receiver FIFO, sets the RXF ﬂag, and generates a receive interrupt 2 (see Section 16.4.7.3, “Receive Interrupt”) to the CPU. The user’s receive handler must read the received message from the RxFG and then reset the RXF ﬂag to acknowledge the interrupt and to release the foreground buffer. A new message, which can follow immediately after the IFS ﬁeld of the CAN frame, is received into the next available RxBG. If the MSCAN receives an invalid 1. The transmit interrupt occurs only if not masked. A polling scheme can be applied on TXEx also. 2. The receive interrupt occurs only if not masked. A polling scheme can be applied on RXF also.

Freescale’s Scalable Controller Area Network (S12MSCANV3) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 515 message in its RxBG (wrong identiﬁer, transmission errors, etc.) the actual contents of the buffer will be over-written by the next message. The buffer will then not be shifted into the FIFO. When the MSCAN module is transmitting, the MSCAN receives its own transmitted messages into the background receive buffer, RxBG, but does not shift it into the receiver FIFO, generate a receive interrupt, or acknowledge its own messages on the CAN bus. The exception to this rule is in loopback mode (see Section 16.3.2.2, “MSCAN Control Register 1 (CANCTL1)”) where the MSCAN treats its own messages exactly like all other incoming messages. The MSCAN receives its own transmitted messages in the event that it loses arbitration. If arbitration is lost, the MSCAN must be prepared to become a receiver. An overrun condition occurs when all receive message buffers in the FIFO are ﬁlled with correctly received messages with accepted identiﬁers and another message is correctly received from the CAN bus with an accepted identiﬁer. The latter message is discarded and an error interrupt with overrun indication is generated if enabled (see Section 16.4.7.5, “Error Interrupt”). The MSCAN remains able to transmit messages while the receiver FIFO is being ﬁlled, but all incoming messages are discarded. As soon as a receive buffer in the FIFO is available again, new valid messages will be accepted.

16.4.3 Identiﬁer Acceptance Filter

The MSCAN identiﬁer acceptance registers (see Section 16.3.2.12, “MSCAN Identiﬁer Acceptance Control Register (CANIDAC)”) deﬁne the acceptable patterns of the standard or extended identiﬁer (ID[10:0] or ID[28:0]). Any of these bits can be marked ‘don’t care’ in the MSCAN identiﬁer mask registers (see Section 16.3.2.18, “MSCAN Identiﬁer Mask Registers (CANIDMR0–CANIDMR7)”). A ﬁlter hit is indicated to the application software by a set receive buffer full ﬂag (RXF = 1) and three bits in the CANIDAC register (see Section 16.3.2.12, “MSCAN Identiﬁer Acceptance Control Register (CANIDAC)”). These identiﬁer hit ﬂags (IDHIT[2:0]) clearly identify the ﬁlter section that caused the acceptance. They simplify the application software’s task to identify the cause of the receiver interrupt. If more than one hit occurs (two or more ﬁlters match), the lower hit has priority. A very ﬂexible programmable generic identiﬁer acceptance ﬁlter has been introduced to reduce the CPU interrupt loading. The ﬁlter is programmable to operate in four different modes:

Two identiﬁer acceptance ﬁlters, each to be applied to: — The full 29 bits of the extended identiﬁer and to the following bits of the CAN 2.0B frame: – Remote transmission request (RTR) – Identiﬁer extension (IDE) – Substitute remote request (SRR) — The 11 bits of the standard identiﬁer plus the RTR and IDE bits of the CAN 2.0A/B messages. This mode implements two ﬁlters for a full length CAN 2.0B compliant extended identiﬁer. Although this mode can be used for standard identiﬁers, it is recommended to use the four or eight identiﬁer acceptance ﬁlters. Figure 16-40 shows how the ﬁrst 32-bit ﬁlter bank (CANIDAR0–CANIDAR3, CANIDMR0–CANIDMR3) produces a ﬁlter 0 hit. Similarly, the second ﬁlter bank (CANIDAR4–CANIDAR7, CANIDMR4–CANIDMR7) produces a ﬁlter 1 hit.
Four identiﬁer acceptance ﬁlters, each to be applied to:

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— The 14 most signiﬁcant bits of the extended identiﬁer plus the SRR and IDE bits of CAN 2.0B messages. — The 11 bits of the standard identiﬁer, the RTR and IDE bits of CAN 2.0A/B messages. Figure 16-41 shows how the ﬁrst 32-bit ﬁlter bank (CANIDAR0–CANIDAR3, CANIDMR0–CANIDMR3) produces ﬁlter 0 and 1 hits. Similarly, the second ﬁlter bank (CANIDAR4–CANIDAR7, CANIDMR4–CANIDMR7) produces ﬁlter 2 and 3 hits.

Eight identiﬁer acceptance ﬁlters, each to be applied to the ﬁrst 8 bits of the identiﬁer. This mode implements eight independent ﬁlters for the ﬁrst 8 bits of a CAN 2.0A/B compliant standard identiﬁer or a CAN 2.0B compliant extended identiﬁer. Figure 16-42 shows how the ﬁrst 32-bit ﬁlter bank (CANIDAR0–CANIDAR3, CANIDMR0–CANIDMR3) produces ﬁlter 0 to 3 hits. Similarly, the second ﬁlter bank (CANIDAR4–CANIDAR7, CANIDMR4–CANIDMR7) produces ﬁlter 4 to 7 hits.
Closed ﬁlter. No CAN message is copied into the foreground buffer RxFG, and the RXF ﬂag is never set. Figure 16-40. 32-bit Maskable Identiﬁer Acceptance Filter ID28 ID21 IDR0 ID10 ID3 IDR0 ID20 ID15 IDR1 ID2 IDE IDR1 ID14 ID7 IDR2 ID10 ID3 IDR2 ID6 RTR IDR3 ID10 ID3 IDR3 AC7 AC0 CANIDAR0 AM7 AM0 CANIDMR0 AC7 AC0 CANIDAR1 AM7 AM0 CANIDMR1 AC7 AC0 CANIDAR2 AM7 AM0 CANIDMR2 AC7 AC0 CANIDAR3 AM7 AM0 CANIDMR3 ID Accepted (Filter 0 Hit) CAN 2.0B Extended Identiﬁer CAN 2.0A/B Standard Identiﬁer

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Figure 16-42. 8-bit Maskable Identiﬁer Acceptance Filters CAN 2.0B Extended Identiﬁer CAN 2.0A/B Standard Identiﬁer AC7 AC0 CIDAR3 AM7 AM0 CIDMR3 ID Accepted (Filter 3 Hit) AC7 AC0 CIDAR2 AM7 AM0 CIDMR2 ID Accepted (Filter 2 Hit) AC7 AC0 CIDAR1 AM7 AM0 CIDMR1 ID Accepted (Filter 1 Hit) ID28 ID21 IDR0 ID10 ID3 IDR0 ID20 ID15 IDR1 ID2 IDE IDR1 ID14 ID7 IDR2 ID10 ID3 IDR2 ID6 RTR IDR3 ID10 ID3 IDR3 AC7 AC0 CIDAR0 AM7 AM0 CIDMR0 ID Accepted (Filter 0 Hit)

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16.4.3.1 Protocol Violation Protection

The MSCAN protects the user from accidentally violating the CAN protocol through programming errors. The protection logic implements the following features:

The receive and transmit error counters cannot be written or otherwise manipulated.
All registers which control the conﬁguration of the MSCAN cannot be modiﬁed while the MSCAN is on-line. The MSCAN has to be in Initialization Mode. The corresponding INITRQ/INITAK handshake bits in the CANCTL0/CANCTL1 registers (see Section 16.3.2.1, “MSCAN Control Register 0 (CANCTL0)”) serve as a lock to protect the following registers: — MSCAN control 1 register (CANCTL1) — MSCAN bus timing registers 0 and 1 (CANBTR0, CANBTR1) — MSCAN identiﬁer acceptance control register (CANIDAC) — MSCAN identiﬁer acceptance registers (CANIDAR0–CANIDAR7) — MSCAN identiﬁer mask registers (CANIDMR0–CANIDMR7)
The TXCAN is immediately forced to a recessive state when the MSCAN goes into the power down mode or initialization mode (see Section 16.4.5.6, “MSCAN Power Down Mode,” and Section 16.4.4.5, “MSCAN Initialization Mode”).
The MSCAN enable bit (CANE) is writable only once in normal system operation modes, which provides further protection against inadvertently disabling the MSCAN.

16.4.3.2 Clock System

Figure 16-43 shows the structure of the MSCAN clock generation circuitry. Figure 16-43. MSCAN Clocking Scheme The clock source bit (CLKSRC) in the CANCTL1 register (16.3.2.2/16-484) deﬁnes whether the internal CANCLK is connected to the output of a crystal oscillator (oscillator clock) or to the bus clock. The clock source has to be chosen such that the tight oscillator tolerance requirements (up to 0.4%) of the CAN protocol are met. Additionally, for high CAN bus rates (1 Mbps), a 45% to 55% duty cycle of the clock is required. If the bus clock is generated from a PLL, it is recommended to select the oscillator clock rather than the bus clock due to jitter considerations, especially at the faster CAN bus rates. Bus Clock Oscillator Clock MSCAN CANCLK CLKSRC CLKSRC Prescaler (1 .. 64) Time quanta clock (Tq)

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For microcontrollers without a clock and reset generator (CRG), CANCLK is driven from the crystal oscillator (oscillator clock). A programmable prescaler generates the time quanta (Tq) clock from CANCLK. A time quantum is the atomic unit of time handled by the MSCAN. Eqn. 16-2 A bit time is subdivided into three segments as described in the Bosch CAN 2.0A/B speciﬁcation. (see Figure 16-44):

SYNC_SEG: This segment has a ﬁxed length of one time quantum. Signal edges are expected to happen within this section.
Time Segment 1: This segment includes the PROP_SEG and the PHASE_SEG1 of the CAN standard. It can be programmed by setting the parameter TSEG1 to consist of 4 to 16 time quanta.
Time Segment 2: This segment represents the PHASE_SEG2 of the CAN standard. It can be programmed by setting the TSEG2 parameter to be 2 to 8 time quanta long. Eqn. 16-3 Figure 16-44. Segments within the Bit Time Tq fCANCLK Bit Rate fTq SYNC_SEG Time Segment 1 Time Segment 2 8 ... 25 Time Quanta = 1 Bit Time NRZ Signal Sample Point (single or triple sampling) (PROP_SEG + PHASE_SEG1) (PHASE_SEG2) Transmit Point

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16.4.4 Modes of Operation

16.4.4.1 Normal System Operating Modes

The MSCAN module behaves as described within this speciﬁcation in all normal system operating modes. Write restrictions exist for some registers. Table 16-36. Time Segment Syntax Syntax Description SYNC_SEG System expects transitions to occur on the CAN bus during this period. Transmit Point A node in transmit mode transfers a new value to the CAN bus at this point. Sample Point A node in receive mode samples the CAN bus at this point. If the three samples per bit option is selected, then this point marks the position of the third sample. Table 16-37. Bosch CAN 2.0A/B Compliant Bit Time Segment Settings Time Segment 1 TSEG1 Time Segment 2 TSEG2 Synchronization Jump Width SJW

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16.4.4.2 Special System Operating Modes

The MSCAN module behaves as described within this speciﬁcation in all special system operating modes. Write restrictions which exist on speciﬁc registers in normal modes are lifted for test purposes in special modes.

16.4.4.3 Emulation Modes

In all emulation modes, the MSCAN module behaves just like in normal system operating modes as described within this speciﬁcation.

16.4.4.4 Listen-Only Mode

In an optional CAN bus monitoring mode (listen-only), the CAN node is able to receive valid data frames and valid remote frames, but it sends only “recessive” bits on the CAN bus. In addition, it cannot start a transmission. If the MAC sub-layer is required to send a “dominant” bit (ACK bit, overload ﬂag, or active error ﬂag), the bit is rerouted internally so that the MAC sub-layer monitors this “dominant” bit, although the CAN bus may remain in recessive state externally.

16.4.4.5 MSCAN Initialization Mode

The MSCAN enters initialization mode when it is enabled (CANE=1). When entering initialization mode during operation, any on-going transmission or reception is immediately aborted and synchronization to the CAN bus is lost, potentially causing CAN protocol violations. To protect the CAN bus system from fatal consequences of violations, the MSCAN immediately drives TXCAN into a recessive state. NOTE The user is responsible for ensuring that the MSCAN is not active when initialization mode is entered. The recommended procedure is to bring the MSCAN into sleep mode (SLPRQ = 1 and SLPAK = 1) before setting the INITRQ bit in the CANCTL0 register. Otherwise, the abort of an on-going message can cause an error condition and can impact other CAN bus devices. In initialization mode, the MSCAN is stopped. However, interface registers remain accessible. This mode is used to reset the CANCTL0, CANRFLG, CANRIER, CANTFLG, CANTIER, CANTARQ, CANTAAK, and CANTBSEL registers to their default values. In addition, the MSCAN enables the conﬁguration of the CANBTR0, CANBTR1 bit timing registers; CANIDAC; and the CANIDAR, CANIDMR message ﬁlters. See Section 16.3.2.1, “MSCAN Control Register 0 (CANCTL0),” for a detailed description of the initialization mode.

Freescale’s Scalable Controller Area Network (S12MSCANV3) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 523 Figure 16-45. Initialization Request/Acknowledge Cycle Due to independent clock domains within the MSCAN, INITRQ must be synchronized to all domains by using a special handshake mechanism. This handshake causes additional synchronization delay (see Figure 16-45). If there is no message transfer ongoing on the CAN bus, the minimum delay will be two additional bus clocks and three additional CAN clocks. When all parts of the MSCAN are in initialization mode, the INITAK ﬂag is set. The application software must use INITAK as a handshake indication for the request (INITRQ) to go into initialization mode. NOTE The CPU cannot clear INITRQ before initialization mode (INITRQ = 1 and INITAK = 1) is active.

16.4.5 Low-Power Options

If the MSCAN is disabled (CANE = 0), the MSCAN clocks are stopped for power saving. If the MSCAN is enabled (CANE = 1), the MSCAN has two additional modes with reduced power consumption, compared to normal mode: sleep and power down mode. In sleep mode, power consumption is reduced by stopping all clocks except those to access the registers from the CPU side. In power down mode, all clocks are stopped and no power is consumed. Table 16-38 summarizes the combinations of MSCAN and CPU modes. A particular combination of modes is entered by the given settings on the CSW AI and SLPRQ/SLPAK bits. SYNC SYNC Bus Clock Domain CAN Clock Domain CPU Init Request INIT Flag INITAK Flag INITRQ sync. INITAK sync. INITRQ INITAK

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16.4.5.1 Operation in Run Mode

As shown in Table 16-38, only MSCAN sleep mode is available as low power option when the CPU is in run mode.

16.4.5.2 Operation in Wait Mode

The W AI instruction puts the MCU in a low power consumption stand-by mode. If the CSW AI bit is set, additional power can be saved in power down mode because the CPU clocks are stopped. After leaving this power down mode, the MSCAN restarts and enters normal mode again. While the CPU is in wait mode, the MSCAN can be operated in normal mode and generate interrupts (registers can be accessed via background debug mode).

16.4.5.3 Operation in Stop Mode

The STOP instruction puts the MCU in a low power consumption stand-by mode. In stop mode, the MSCAN is set in power down mode regardless of the value of the SLPRQ/SLPAK and CSW AI bits (Table 16-38).

16.4.5.4 MSCAN Normal Mode

This is a non-power-saving mode. Enabling the MSCAN puts the module from disabled mode into normal mode. In this mode the module can either be in initialization mode or out of initialization mode. See Section 16.4.4.5, “MSCAN Initialization Mode”. Table 16-38. CPU vs. MSCAN Operating Modes CPU Mode MSCAN Mode Normal Reduced Power Consumption Sleep Power Down Disabled (CANE=0) RUN CSWAI = X1 SLPRQ = 0 SLPAK = 0 1 ‘X’ means don’t care. CSWAI = X SLPRQ = 1 SLPAK = 1 CSWAI = X SLPRQ = X SLPAK = X WAIT CSWAI = 0 SLPRQ = 0 SLPAK = 0 CSWAI = 0 SLPRQ = 1 SLPAK = 1 CSWAI = 1 SLPRQ = X SLPAK = X CSWAI = X SLPRQ = X SLPAK = X STOP CSWAI = X SLPRQ = X SLPAK = X CSWAI = X SLPRQ = X SLPAK = X

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16.4.5.5 MSCAN Sleep Mode

The CPU can request the MSCAN to enter this low power mode by asserting the SLPRQ bit in the CANCTL0 register. The time when the MSCAN enters sleep mode depends on a ﬁxed synchronization delay and its current activity:

If there are one or more message buffers scheduled for transmission (TXEx = 0), the MSCAN will continue to transmit until all transmit message buffers are empty (TXEx = 1, transmitted successfully or aborted) and then goes into sleep mode.
If the MSCAN is receiving, it continues to receive and goes into sleep mode as soon as the CAN bus next becomes idle.
If the MSCAN is neither transmitting nor receiving, it immediately goes into sleep mode. Figure 16-46. Sleep Request / Acknowledge Cycle NOTE The application software must avoid setting up a transmission (by clearing one or more TXEx ﬂag(s)) and immediately request sleep mode (by setting SLPRQ). Whether the MSCAN starts transmitting or goes into sleep mode directly depends on the exact sequence of operations. If sleep mode is active, the SLPRQ and SLPAK bits are set (Figure 16-46). The application software must use SLPAK as a handshake indication for the request (SLPRQ) to go into sleep mode. When in sleep mode (SLPRQ = 1 and SLPAK = 1), the MSCAN stops its internal clocks. However, clocks that allow register accesses from the CPU side continue to run. If the MSCAN is in bus-off state, it stops counting the 128 occurrences of 11 consecutive recessive bits due to the stopped clocks. TXCAN remains in a recessive state. If RXF = 1, the message can be read and RXF can be cleared. Shifting a new message into the foreground buffer of the receiver FIFO (RxFG) does not take place while in sleep mode. It is possible to access the transmit buffers and to clear the associated TXE ﬂags. No message abort takes place while in sleep mode. SYNC SYNC Bus Clock Domain CAN Clock Domain MSCAN in Sleep Mode CPU Sleep Request SLPRQ Flag SLPAK Flag SLPRQ sync. SLPAK sync. SLPRQ SLPAK

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If the WUPE bit in CANCTL0 is not asserted, the MSCAN will mask any activity it detects on CAN. RXCAN is therefore held internally in a recessive state. This locks the MSCAN in sleep mode. WUPE must be set before entering sleep mode to take effect. The MSCAN is able to leave sleep mode (wake up) only when:

CAN bus activity occurs and WUPE = 1 or
the CPU clears the SLPRQ bit NOTE The CPU cannot clear the SLPRQ bit before sleep mode (SLPRQ = 1 and SLPAK = 1) is active. After wake-up, the MSCAN waits for 11 consecutive recessive bits to synchronize to the CAN bus. As a consequence, if the MSCAN is woken-up by a CAN frame, this frame is not received. The receive message buffers (RxFG and RxBG) contain messages if they were received before sleep mode was entered. All pending actions will be executed upon wake-up; copying of RxBG into RxFG, message aborts and message transmissions. If the MSCAN remains in bus-off state after sleep mode was exited, it continues counting the 128 occurrences of 11 consecutive recessive bits.

16.4.5.6 MSCAN Power Down Mode

The MSCAN is in power down mode (Table 16-38) when

CPU is in stop mode or
CPU is in wait mode and the CSW AI bit is set When entering the power down mode, the MSCAN immediately stops all ongoing transmissions and receptions, potentially causing CAN protocol violations. To protect the CAN bus system from fatal consequences of violations to the above rule, the MSCAN immediately drives TXCAN into a recessive state. NOTE The user is responsible for ensuring that the MSCAN is not active when power down mode is entered. The recommended procedure is to bring the MSCAN into Sleep mode before the STOP or W AI instruction (if CSW AI is set) is executed. Otherwise, the abort of an ongoing message can cause an error condition and impact other CAN bus devices. In power down mode, all clocks are stopped and no registers can be accessed. If the MSCAN was not in sleep mode before power down mode became active, the module performs an internal recovery cycle after powering up. This causes some ﬁxed delay before the module enters normal mode again.

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16.4.5.7 Disabled Mode

The MSCAN is in disabled mode out of reset (CANE=0). All module clocks are stopped for power saving, however the register map can still be accessed as speciﬁed.

16.4.5.8 Programmable Wake-Up Function

The MSCAN can be programmed to wake up from sleep or power down mode as soon as CAN bus activity is detected (see control bit WUPE in MSCAN Control Register 0 (CANCTL0). The sensitivity to existing CAN bus action can be modiﬁed by applying a low-pass ﬁlter function to the RXCAN input line (see control bit WUPM in Section 16.3.2.2, “MSCAN Control Register 1 (CANCTL1)”). This feature can be used to protect the MSCAN from wake-up due to short glitches on the CAN bus lines. Such glitches can result from—for example—electromagnetic interference within noisy environments.

16.4.6 Reset Initialization

The reset state of each individual bit is listed in Section 16.3.2, “Register Descriptions,” which details all the registers and their bit-ﬁelds.

16.4.7 Interrupts

This section describes all interrupts originated by the MSCAN. It documents the enable bits and generated ﬂags. Each interrupt is listed and described separately.

16.4.7.1 Description of Interrupt Operation

The MSCAN supports four interrupt vectors (see Table 16-39), any of which can be individually masked (for details see Section 16.3.2.6, “MSCAN Receiver Interrupt Enable Register (CANRIER)” to Section 16.3.2.8, “MSCAN Transmitter Interrupt Enable Register (CANTIER)”). Refer to the device overview section to determine the dedicated interrupt vector addresses.

16.4.7.2 Transmit Interrupt

At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message for transmission. The TXEx ﬂag of the empty message buffer is set. Table 16-39. Interrupt Vectors Interrupt Source CCR Mask Local Enable Wake-Up Interrupt (WUPIF) I bit CANRIER (WUPIE) Error Interrupts Interrupt (CSCIF , OVRIF) I bit CANRIER (CSCIE, OVRIE) Receive Interrupt (RXF) I bit CANRIER (RXFIE) Transmit Interrupts (TXE[2:0]) I bit CANTIER (TXEIE[2:0])

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16.4.7.3 Receive Interrupt

A message is successfully received and shifted into the foreground buffer (RxFG) of the receiver FIFO. This interrupt is generated immediately after receiving the EOF symbol. The RXF ﬂag is set. If there are multiple messages in the receiver FIFO, the RXF ﬂag is set as soon as the next message is shifted to the foreground buffer.

16.4.7.4 Wake-Up Interrupt

A wake-up interrupt is generated if activity on the CAN bus occurs during MSCAN sleep or power-down mode. NOTE This interrupt can only occur if the MSCAN was in sleep mode (SLPRQ = 1 and SLPAK = 1) before entering power down mode, the wake-up option is enabled (WUPE = 1), and the wake-up interrupt is enabled (WUPIE = 1).

16.4.7.5 Error Interrupt

An error interrupt is generated if an overrun of the receiver FIFO, error, warning, or bus-off condition occurrs. MSCAN Receiver Flag Register (CANRFLG) indicates one of the following conditions:

Overrun — An overrun condition of the receiver FIFO as described in Section 16.4.2.3, “Receive Structures,” occurred.
CAN Status Change — The actual value of the transmit and receive error counters control the CAN bus state of the MSCAN. As soon as the error counters skip into a critical range (Tx/Rx-warning, Tx/Rx-error, bus-off) the MSCAN ﬂags an error condition. The status change, which caused the error condition, is indicated by the TSTAT and RSTAT ﬂags (see Receiver Interrupt Enable Register (CANRIER)”).

16.4.7.6 Interrupt Acknowledge

Interrupts are directly associated with one or more status ﬂags in either theMSCAN Receiver Flag Register (CANRFLG) or the MSCAN Transmitter Flag Register (CANTFLG). Interrupts are pending as long as one of the corresponding ﬂags is set. The ﬂags in CANRFLG and CANTFLG must be reset within the interrupt handler to handshake the interrupt. The ﬂags are reset by writing a 1 to the corresponding bit position. A ﬂag cannot be cleared if the respective condition prevails. NOTE It must be guaranteed that the CPU clears only the bit causing the current interrupt. For this reason, bit manipulation instructions (BSET) must not be used to clear interrupt ﬂags. These instructions may cause accidental clearing of interrupt ﬂags which are set after entering the current interrupt service routine.

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16.5 Initialization/Application Information

16.5.1 MSCAN initialization

The procedure to initially start up the MSCAN module out of reset is as follows: 1. Assert CANE 2. Write to the conﬁguration registers in initialization mode 3. Clear INITRQ to leave initialization mode If the conﬁguration of registers which are only writable in initialization mode shall be changed: 1. Bring the module into sleep mode by setting SLPRQ and awaiting SLPAK to assert after the CAN bus becomes idle. 2. Enter initialization mode: assert INITRQ and await INITAK 3. Write to the conﬁguration registers in initialization mode 4. Clear INITRQ to leave initialization mode and continue

16.5.2 Bus-Off Recovery

The bus-off recovery is user conﬁgurable. The bus-off state can either be left automatically or on user request. For reasons of backwards compatibility, the MSCAN defaults to automatic recovery after reset. In this case, the MSCAN will become error active again after counting 128 occurrences of 11 consecutive recessive bits on the CAN bus (see the Bosch CAN 2.0 A/B speciﬁcation for details). If the MSCAN is conﬁgured for user request (BORM set inMSCAN Control Register 1 (CANCTL1)), the recovery from bus-off starts after both independent events have become true:

128 occurrences of 11 consecutive recessive bits on the CAN bus have been monitored
BOHOLD in MSCAN Miscellaneous Register (CANMISC) has been cleared by the user These two events may occur in any order.

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MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 531 Chapter 17 Pulse-Width Modulator (S12PWM8B8CV2)

17.1 Introduction

The Version 2 of S12 PWM module is a channel scalable and optimized implementation of S12 PWM8B8C Version 1. The channel is scalable in pairs from PWM0 to PWM7 and the available channel number is 2, 4, 6 and 8. The shutdown feature has been removed and the ﬂexibility to select one of four clock sources per channel has improved. If the corresponding channels exist and shutdown feature is not used, the Version 2 is fully software compatible to Version 1.

17.1.1 Features

The scalable PWM block includes these distinctive features:

Up to eight independent PWM channels, scalable in pairs (PWM0 to PWM7)
Available channel number could be 2, 4, 6, 8 (refer to device speciﬁcation for exact number)
Programmable period and duty cycle for each channel
Dedicated counter for each PWM channel
Programmable PWM enable/disable for each channel
Software selection of PWM duty pulse polarity for each channel
Period and duty cycle are double buffered. Change takes effect when the end of the effective period is reached (PWM counter reaches zero) or when the channel is disabled.
Programmable center or left aligned outputs on individual channels
Up to eight 8-bit channel or four 16-bit channel PWM resolution
Four clock sources (A, B, SA, and SB) provide for a wide range of frequencies
Programmable clock select logic

17.1.2 Modes of Operation

There is a software programmable option for low power consumption in wait mode that disables the input clock to the prescaler. In freeze mode there is a software programmable option to disable the input clock to the prescaler. This is useful for emulation. Wait: The prescaler keeps on running, unless PSWAI in PWMCTL is set to 1. Freeze: The prescaler keeps on running, unless PFRZ in PWMCTL is set to 1.

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17.1.3 Block Diagram

Figure 17-1 shows the block diagram for the 8-bit up to 8-channel scalable PWM block. Figure 17-1. Scalable PWM Block Diagram

17.2 External Signal Description

The scalable PWM module has a selected number of external pins. Refer to device speciﬁcation for exact number.

17.2.1 PWM7 - PWM0 — PWM Channel 7 - 0

Those pins serve as waveform output of PWM channel 7 - 0. Period and Duty Counter Channel 6 Clock Select PWM Clock Period and Duty Counter Channel 5 Period and Duty Counter Channel 4 Period and Duty Counter Channel 3 Period and Duty Counter Channel 2 Period and Duty Counter Channel 1Alignment Polarity Control PWM8B8C PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 Enable PWM Channels Period and Duty Counter Channel 7 Period and Duty Counter Channel 0 PWM0 PWM7 Bus Clock Maximum possible channels, scalable in pairs from PWM0 to PWM7.

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17.3 Memory Map and Register Deﬁnition

17.3.1 Module Memory Map

This section describes the content of the registers in the scalable PWM module. The base address of the scalable PWM module is determined at the MCU level when the MCU is deﬁned. The register decode map is ﬁxed and begins at the ﬁrst address of the module address offset. The ﬁgure below shows the registers associated with the scalable PWM and their relative offset from the base address. The register detail description follows the order they appear in the register map. Reserved bits within a register will always read as 0 and the write will be unimplemented. Unimplemented functions are indicated by shading the bit. NOTE Register Address = Base Address + Address Offset, where the Base Address is deﬁned at the MCU level and the Address Offset is deﬁned at the module level.

17.3.2 Register Descriptions

This section describes in detail all the registers and register bits in the scalable PWM module. Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x0000 PWME1 R PWME7 PWME6 PWME5 PWME4 PWME3 PWME2 PWME1 PWME0 W 0x0001 PWMPOL1 R PPOL7 PPOL6 PPOL5 PPOL4 PPOL3 PPOL2 PPOL1 PPOL0 W 0x0002 PWMCLK1 R PCLK7 PCLKL6 PCLK5 PCLK4 PCLK3 PCLK2 PCLK1 PCLK0 W 0x0003 PWMPRCLK PCKB2 PCKB1 PCKB0 PCKA2 PCKA1 PCKA0 W 0x0004 PWMCAE1 R CAE7 CAE6 CAE5 CAE4 CAE3 CAE2 CAE1 CAE0 W 0x0005 PWMCTL1 R CON67 CON45 CON23 CON01 PSWAI PFRZ W 0x0006 PWMCLKAB1 R PCLKAB7 PCLKAB6 PCLKAB5 PCLKAB4 PCLKAB3 PCLKAB2 PCLKAB1 PCLKAB0 W = Unimplemented or Reserved Figure 17-2. The scalable PWM Register Summary (Sheet 1 of 4)

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W 0x0008 PWMSCLA R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0009 PWMSCLB R Bit 7 6 5 4 3 2 1 Bit 0 W 0x000A RESERVED R 00 0 00000 W 0x000B RESERVED R 00 0 00000 W 0x000C PWMCNT02 R Bit 7 6 5 4 3 2 1 Bit 0 W 00 0 00000 0x000D PWMCNT12 R Bit 7 6 5 4 3 2 1 Bit 0 W 00 0 00000 0x000E PWMCNT22 R Bit 7 6 5 4 3 2 1 Bit 0 W 00 0 00000 0x000F PWMCNT32 R Bit 7 6 5 4 3 2 1 Bit 0 W 00 0 00000 0x0010 PWMCNT42 R Bit 7 6 5 4 3 2 1 Bit 0 W 00 0 00000 0x0011 PWMCNT52 R Bit 7 6 5 4 3 2 1 Bit 0 W 00 0 00000 0x0012 PWMCNT62 R Bit 7 6 5 4 3 2 1 Bit 0 W 00 0 00000 0x0013 PWMCNT72 R Bit 7 6 5 4 3 2 1 Bit 0 W 00 0 00000 0x0014 PWMPER02 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0015 PWMPER12 R Bit 7 6 5 4 3 2 1 Bit 0 W Register Name Bit 7 6 5 4 3 2 1 Bit 0 = Unimplemented or Reserved Figure 17-2. The scalable PWM Register Summary (Sheet 1 of 4)

Pulse-Width Modulator (S12PWM8B8CV2) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 535 0x0016 PWMPER22 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0017 PWMPER32 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0018 PWMPER42 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0019 PWMPER52 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x001A PWMPER62 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x001B PWMPER72 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x001C PWMDTY02 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x001D PWMDTY12 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x001E PWMDTY22 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x001F PWMDTY32 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0010 PWMDTY42 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0021 PWMDTY52 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0022 PWMDTY62 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0023 PWMDTY72 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x0024 RESERVED R 00 0 00000 W Register Name Bit 7 6 5 4 3 2 1 Bit 0 = Unimplemented or Reserved Figure 17-2. The scalable PWM Register Summary (Sheet 1 of 4)

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17.3.2.1 PWM Enable Register (PWME)

Each PWM channel has an enable bit (PWMEx) to start its waveform output. When any of the PWMEx bits are set (PWMEx = 1), the associated PWM output is enabled immediately. However, the actual PWM waveform is not available on the associated PWM output until its clock source begins its next cycle due to the synchronization of PWMEx and the clock source. NOTE The ﬁrst PWM cycle after enabling the channel can be irregular. An exception to this is when channels are concatenated. Once concatenated mode is enabled (CONxx bits set in PWMCTL register), enabling/disabling the corresponding 16-bit PWM channel is controlled by the low order PWMEx bit. In this case, the high order bytes PWMEx bits have no effect and their corresponding PWM output lines are disabled. While in run mode, if all existing PWM channels are disabled (PWMEx–0 = 0), the prescaler counter shuts off for power savings. Read: Anytime Write: Anytime 0x0025 RESERVED R 00 0 00000 W 0x0026 RESERVED R 00 0 00000 W 0x0027 RESERVED R 00 0 00000 W 1 The related bit is available only if corresponding channel exists. 2 The register is available only if corresponding channel exists. Module Base + 0x0000 76543210 R PWME7 PWME6 PWME5 PWME4 PWME3 PWME2 PWME1 PWME0 W Reset 0 0 0 00000 Figure 17-3. PWM Enable Register (PWME) Register Name Bit 7 6 5 4 3 2 1 Bit 0 = Unimplemented or Reserved Figure 17-2. The scalable PWM Register Summary (Sheet 1 of 4)

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17.3.2.2 PWM Polarity Register (PWMPOL)

The starting polarity of each PWM channel waveform is determined by the associated PPOLx bit in the PWMPOL register. If the polarity bit is one, the PWM channel output is high at the beginning of the cycle and then goes low when the duty count is reached. Conversely, if the polarity bit is zero, the output starts low and then goes high when the duty count is reached. Table 17-2. PWME Field Descriptions Note: Bits related to available channels have functional signiﬁcance. Writing to unavailable bits has no effect. Read from unavailable bits return a zero Field Description PWME7 Pulse Width Channel 7 Enable 0 Pulse width channel 7 is disabled. 1 Pulse width channel 7 is enabled. The pulse modulated signal becomes available at PWM output bit 7 when its clock source begins its next cycle. PWME6 Pulse Width Channel 6 Enable 0 Pulse width channel 6 is disabled. 1 Pulse width channel 6 is enabled. The pulse modulated signal becomes available at PWM output bit 6 when its clock source begins its next cycle. If CON67=1, then bit has no effect and PWM output line 6 is disabled. PWME5 Pulse Width Channel 5 Enable 0 Pulse width channel 5 is disabled. 1 Pulse width channel 5 is enabled. The pulse modulated signal becomes available at PWM output bit 5 when its clock source begins its next cycle. PWME4 Pulse Width Channel 4 Enable 0 Pulse width channel 4 is disabled. 1 Pulse width channel 4 is enabled. The pulse modulated signal becomes available at PWM, output bit 4 when its clock source begins its next cycle. If CON45 = 1, then bit has no effect and PWM output line 4 is disabled. PWME3 Pulse Width Channel 3 Enable 0 Pulse width channel 3 is disabled. 1 Pulse width channel 3 is enabled. The pulse modulated signal becomes available at PWM, output bit 3 when its clock source begins its next cycle. PWME2 Pulse Width Channel 2 Enable 0 Pulse width channel 2 is disabled. 1 Pulse width channel 2 is enabled. The pulse modulated signal becomes available at PWM, output bit 2 when its clock source begins its next cycle. If CON23 = 1, then bit has no effect and PWM output line 2 is disabled. PWME1 Pulse Width Channel 1 Enable 0 Pulse width channel 1 is disabled. 1 Pulse width channel 1 is enabled. The pulse modulated signal becomes available at PWM, output bit 1 when its clock source begins its next cycle. PWME0 Pulse Width Channel 0 Enable 0 Pulse width channel 0 is disabled. 1 Pulse width channel 0 is enabled. The pulse modulated signal becomes available at PWM, output bit 0 when its clock source begins its next cycle. If CON01 = 1, then bit has no effect and PWM output line 0 is disabled.

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Read: Anytime Write: Anytime NOTE PPOLx register bits can be written anytime. If the polarity is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition

17.3.2.3 PWM Clock Select Register (PWMCLK)

Each PWM channel has a choice of four clocks to use as the clock source for that channel as described below. Read: Anytime Write: Anytime NOTE Register bits PCLK0 to PCLK7 can be written anytime. If a clock select is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition. Module Base + 0x0001 76543210 R PPOL7 PPOL6 PPOL5 PPOL4 PPOL3 PPOL2 PPOL1 PPOL0 W Reset 0 0 0 00000 Figure 17-4. PWM Polarity Register (PWMPOL) Table 17-3. PWMPOL Field Descriptions Note: Bits related to available channels have functional signiﬁcance. Writing to unavailable bits has no effect. Read from unavailable bits return a zero Field Description 7–0 PPOL[7:0] Pulse Width Channel 7–0 Polarity Bits

0 PWM channel 7–0 outputs are low at the beginning of the period, then go high when the duty count is

reached.

1 PWM channel 7–0 outputs are high at the beginning of the period, then go low when the duty count is

reached. Module Base + 0x0002 76543210 R PCLK7 PCLKL6 PCLK5 PCLK4 PCLK3 PCLK2 PCLK1 PCLK0 W Reset 0 0 0 00000 Figure 17-5. PWM Clock Select Register (PWMCLK)

Pulse-Width Modulator (S12PWM8B8CV2) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 539 The clock source of each PWM channel is determined by PCLKx bits in PWMCLK and PCLKABx bits in PWMCLKAB (see Section 17.3.2.7, “PWM Clock A/B Select Register (PWMCLKAB)). For Channel 0, 1, 4, 5, the selection is shown inTable 17-5; For Channel 2, 3, 6, 7, the selection is shown inTable 17-6. Table 17-5. PWM Channel 0, 1, 4, 5 Clock Source Selection Table 17-6. PWM Channel 2, 3, 6, 7 Clock Source Selection

17.3.2.4 PWM Prescale Clock Select Register (PWMPRCLK)

This register selects the prescale clock source for clocks A and B independently. Read: Anytime Write: Anytime NOTE PCKB2–0 and PCKA2–0 register bits can be written anytime. If the clock pre-scale is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition. Table 17-4. PWMCLK Field Descriptions Note: Bits related to available channels have functional signiﬁcance. Writing to unavailable bits has no effect. Read from unavailable bits return a zero Field Description 7-0 PCLK[7:0] Pulse Width Channel 7-0 Clock Select 0 Clock A or B is the clock source for PWM channel 7-0, as shown in Table 17-5 and Table 17-6. 1 Clock SA or SB is the clock source for PWM channel 7-0, as shown in Table 17-5 and Table 17-6. PCLKAB[0,1,4,5] PCLK[0,1,4,5] Clock Source Selection 0 0 Clock A 0 1 Clock SA 1 0 Clock B 1 1 Clock SB PCLKAB[2,3,6,7] PCLK[2,3,6,7] Clock Source Selection 0 0 Clock B 0 1 Clock SB 1 0 Clock A 1 1 Clock SA Module Base + 0x0003 76543210 PCKB2 PCKB1 PCKB0 PCKA2 PCKA1 PCKA0 W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 17-6. PWM Prescale Clock Select Register (PWMPRCLK)

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17.3.2.5 PWM Center Align Enable Register (PWMCAE)

The PWMCAE register contains eight control bits for the selection of center aligned outputs or left aligned outputs for each PWM channel. If the CAEx bit is set to a one, the corresponding PWM output will be center aligned. If the CAEx bit is cleared, the corresponding PWM output will be left aligned. See detailed description of the PWM output modes. Read: Anytime Write: Anytime NOTE Write these bits only when the corresponding channel is disabled. Table 17-7. PWMPRCLK Field Descriptions Field Description 6–4 PCKB[2:0] Prescaler Select for Clock B— Clock B is one of two clock sources which can be used for all channels. These three bits determine the rate of clock B, as shown in Table 17-8. 2–0 PCKA[2:0] Prescaler Select for Clock A— Clock A is one of two clock sources which can be used for all channels. These three bits determine the rate of clock A, as shown in Table 17-8. Table 17-8. Clock A or Clock B Prescaler Selects PCKA/B2 PCKA/B1 PCKA/B0 Value of Clock A/B 0 0 0 Bus clock 0 0 1 Bus clock / 2 0 1 0 Bus clock / 4 0 1 1 Bus clock / 8 1 0 0 Bus clock / 16 1 0 1 Bus clock / 32 1 1 0 Bus clock / 64 1 1 1 Bus clock / 128 Module Base + 0x0004 76543210 R CAE7 CAE6 CAE5 CAE4 CAE3 CAE2 CAE1 CAE0 W Reset 0 0 0 00000 Figure 17-7. PWM Center Align Enable Register (PWMCAE)

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17.3.2.6 PWM Control Register (PWMCTL)

The PWMCTL register provides for various control of the PWM module. Read: Anytime Write: Anytime There are up to four control bits for concatenation, each of which is used to concatenate a pair of PWM channels into one 16-bit channel. If the corresponding channels do not exist on a particular derivative, then writes to these bits have no effect and reads will return zeroes. When channels 6 and 7are concatenated, channel 6 registers become the high order bytes of the double byte channel. When channels 4 and 5 are concatenated, channel 4 registers become the high order bytes of the double byte channel. When channels 2 and 3 are concatenated, channel 2 registers become the high order bytes of the double byte channel. When channels 0 and 1 are concatenated, channel 0 registers become the high order bytes of the double byte channel. See Section 17.4.2.7, “PWM 16-Bit Functions”for a more detailed description of the concatenation PWM Function. NOTE Change these bits only when both corresponding channels are disabled. Table 17-9. PWMCAE Field Descriptions Note: Bits related to available channels have functional signiﬁcance. Writing to unavailable bits has no effect. Read from unavailable bits return a zero Field Description 7–0 CAE[7:0] Center Aligned Output Modes on Channels 7–0 0 Channels 7–0 operate in left aligned output mode. 1 Channels 7–0 operate in center aligned output mode. Module Base + 0x0005 76543210 R CON67 CON45 CON23 CON01 PSWAI PFRZ W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 17-8. PWM Control Register (PWMCTL)

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17.3.2.7 PWM Clock A/B Select Register (PWMCLKAB)

Each PWM channel has a choice of four clocks to use as the clock source for that channel as described below. Table 17-10. PWMCTL Field Descriptions Note: Bits related to available channels have functional signiﬁcance. Writing to unavailable bits has no effect. Read from unavailable bits return a zero Field Description CON67 Concatenate Channels 6 and 7 0 Channels 6 and 7 are separate 8-bit PWMs. 1 Channels 6 and 7 are concatenated to create one 16-bit PWM channel. Channel 6 becomes the high order byte and channel 7 becomes the low order byte. Channel 7 output pin is used as the output for this 16-bit PWM (bit 7 of port PWMP). Channel 7 clock select control-bit determines the clock source, channel 7 polarity bit determines the polarity, channel 7 enable bit enables the output and channel 7 center aligned enable bit determines the output mode. CON45 Concatenate Channels 4 and 5 0 Channels 4 and 5 are separate 8-bit PWMs. 1 Channels 4 and 5 are concatenated to create one 16-bit PWM channel. Channel 4 becomes the high order byte and channel 5 becomes the low order byte. Channel 5 output pin is used as the output for this 16-bit PWM (bit 5 of port PWMP). Channel 5 clock select control-bit determines the clock source, channel 5 polarity bit determines the polarity, channel 5 enable bit enables the output and channel 5 center aligned enable bit determines the output mode. CON23 Concatenate Channels 2 and 3 0 Channels 2 and 3 are separate 8-bit PWMs. 1 Channels 2 and 3 are concatenated to create one 16-bit PWM channel. Channel 2 becomes the high order byte and channel 3 becomes the low order byte. Channel 3 output pin is used as the output for this 16-bit PWM (bit 3 of port PWMP). Channel 3 clock select control-bit determines the clock source, channel 3 polarity bit determines the polarity, channel 3 enable bit enables the output and channel 3 center aligned enable bit determines the output mode. CON01 Concatenate Channels 0 and 1 0 Channels 0 and 1 are separate 8-bit PWMs. 1 Channels 0 and 1 are concatenated to create one 16-bit PWM channel. Channel 0 becomes the high order byte and channel 1 becomes the low order byte. Channel 1 output pin is used as the output for this 16-bit PWM (bit 1 of port PWMP). Channel 1 clock select control-bit determines the clock source, channel 1 polarity bit determines the polarity, channel 1 enable bit enables the output and channel 1 center aligned enable bit determines the output mode. PSWAI PWM Stops in Wait Mode — Enabling this bit allows for lower power consumption in wait mode by disabling the input clock to the prescaler. 0 Allow the clock to the prescaler to continue while in wait mode. 1 Stop the input clock to the prescaler whenever the MCU is in wait mode. PFRZ PWM Counters Stop in Freeze Mode — In freeze mode, there is an option to disable the input clock to the prescaler by setting the PFRZ bit in the PWMCTL register. If this bit is set, whenever the MCU is in freeze mode, the input clock to the prescaler is disabled. This feature is useful during emulation as it allows the PWM function to be suspended. In this way, the counters of the PWM can be stopped while in freeze mode so that once normal program ﬂow is continued, the counters are re-enabled to simulate real-time operations. Since the registers can still be accessed in this mode, to re-enable the prescaler clock, either disable the PFRZ bit or exit freeze mode. 0 Allow PWM to continue while in freeze mode. 1 Disable PWM input clock to the prescaler whenever the part is in freeze mode. This is useful for emulation.

Pulse-Width Modulator (S12PWM8B8CV2) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 543 Read: Anytime Write: Anytime NOTE Register bits PCLKAB0 to PCLKAB7 can be written anytime. If a clock select is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition. Module Base + 0x00006 76543210 R PCLKAB7 PCLKAB6 PCLKAB5 PCLKAB4 PCLKAB3 PCLKAB2 PCLKAB1 PCLKAB0 W Reset 0 0 0 00000 Figure 17-9. PWM Clock Select Register (PWMCLKAB) Table 17-11. PWMCLK Field Descriptions Note: Bits related to available channels have functional signiﬁcance. Writing to unavailable bits has no effect. Read from unavailable bits return a zero Field Description PCLKAB7 Pulse Width Channel 7 Clock A/B Select 0 Clock B or SB is the clock source for PWM channel 7, as shown in Table 17-6. 1 Clock A or SA is the clock source for PWM channel 7, as shown in Table 17-6. PCLKAB6 Pulse Width Channel 6 Clock A/B Select 0 Clock B or SB is the clock source for PWM channel 6, as shown in Table 17-6. 1 Clock A or SA is the clock source for PWM channel 6, as shown in Table 17-6. PCLKAB5 Pulse Width Channel 5 Clock A/B Select 0 Clock A or SA is the clock source for PWM channel 5, as shown in Table 17-5. 1 Clock B or SB is the clock source for PWM channel 5, as shown in Table 17-5. PCLKAB4 Pulse Width Channel 4 Clock A/B Select 0 Clock A or SA is the clock source for PWM channel 4, as shown in Table 17-5. 1 Clock B or SB is the clock source for PWM channel 4, as shown in Table 17-5. PCLKAB3 Pulse Width Channel 3 Clock A/B Select 0 Clock B or SB is the clock source for PWM channel 3, as shown in Table 17-6. 1 Clock A or SA is the clock source for PWM channel 3, as shown in Table 17-6. PCLKAB2 Pulse Width Channel 2 Clock A/B Select 0 Clock B or SB is the clock source for PWM channel 2, as shown in Table 17-6. 1 Clock A or SA is the clock source for PWM channel 2, as shown in Table 17-6. PCLKAB1 Pulse Width Channel 1 Clock A/B Select 0 Clock A or SA is the clock source for PWM channel 1, as shown in Table 17-5. 1 Clock B or SB is the clock source for PWM channel 1, as shown in Table 17-5. PCLKAB0 Pulse Width Channel 0 Clock A/B Select 0 Clock A or SA is the clock source for PWM channel 0, as shown in Table 17-5. 1 Clock B or SB is the clock source for PWM channel 0, as shown in Table 17-5.

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The clock source of each PWM channel is determined by PCLKx bits in PWMCLK (seeSection 17.3.2.3, “PWM Clock Select Register (PWMCLK)) and PCLKABx bits in PWMCLKAB as shown inTable 17-5 and Table 17-6.

17.3.2.8 PWM Scale A Register (PWMSCLA)

PWMSCLA is the programmable scale value used in scaling clock A to generate clock SA. Clock SA is generated by taking clock A, dividing it by the value in the PWMSCLA register and dividing that by two. Clock SA = Clock A / (2 * PWMSCLA) NOTE When PWMSCLA = $00, PWMSCLA value is considered a full scale value of 256. Clock A is thus divided by 512. Any value written to this register will cause the scale counter to load the new scale value (PWMSCLA). Read: Anytime Write: Anytime (causes the scale counter to load the PWMSCLA value)

17.3.2.9 PWM Scale B Register (PWMSCLB)

PWMSCLB is the programmable scale value used in scaling clock B to generate clock SB. Clock SB is generated by taking clock B, dividing it by the value in the PWMSCLB register and dividing that by two. Clock SB = Clock B / (2 * PWMSCLB) NOTE When PWMSCLB = $00, PWMSCLB value is considered a full scale value of 256. Clock B is thus divided by 512. Any value written to this register will cause the scale counter to load the new scale value (PWMSCLB). Read: Anytime Write: Anytime (causes the scale counter to load the PWMSCLB value). Module Base + 0x0008 76543210 R Bit 7 6 5 4 3 2 1 Bit 0 W Reset 0 0 0 00000 Figure 17-10. PWM Scale A Register (PWMSCLA) Module Base + 0x0009 76543210 R Bit 7 6 5 4 3 2 1 Bit 0 W Reset 0 0 0 00000 Figure 17-11. PWM Scale B Register (PWMSCLB)

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17.3.2.10 PWM Channel Counter Registers (PWMCNTx)

Each channel has a dedicated 8-bit up/down counter which runs at the rate of the selected clock source. The counter can be read at any time without affecting the count or the operation of the PWM channel. In left aligned output mode, the counter counts from 0 to the value in the period register - 1. In center aligned output mode, the counter counts from 0 up to the value in the period register and then back down to 0. Any value written to the counter causes the counter to reset to $00, the counter direction to be set to up, the immediate load of both duty and period registers with values from the buffers, and the output to change according to the polarity bit. The counter is also cleared at the end of the effective period (see details). When the channel is disabled (PWMEx = 0), the PWMCNTx register does not count. When a channel becomes enabled (PWMEx = 1), the associated PWM counter starts at the count in the PWMCNTx register. For more detailed information on the operation of the counters, seeSection 17.4.2.4, “PWM Timer Counters”. In concatenated mode, writes to the 16-bit counter by using a 16-bit access or writes to either the low or high order byte of the counter will reset the 16-bit counter. Reads of the 16-bit counter must be made by 16-bit access to maintain data coherency. NOTE Writing to the counter while the channel is enabled can cause an irregular PWM cycle to occur. 1 This register is available only when the corresponding channel exists and is reserved if that channel does not exist. Writes to a reserved register have no functional effect. Reads from a reserved register return zeroes. Read: Anytime Write: Anytime (any value written causes PWM counter to be reset to $00).

17.3.2.11 PWM Channel Period Registers (PWMPERx)

There is a dedicated period register for each channel. The value in this register determines the period of the associated PWM channel. The period registers for each channel are double buffered so that if they change while the channel is enabled, the change will NOT take effect until one of the following occurs:

The effective period ends Module Base + 0x000C = PWMCNT0, 0x000D = PWMCNT1, 0x000E = PWMCNT2, 0x000F = PWMCNT3 Module Base + 0x0010 = PWMCNT4, 0x0011 = PWMCNT5, 0x0012 = PWMCNT6, 0x0013 = PWMCNT7 76543210 R Bit 7 6 5 4 3 2 1 Bit 0 W 00000000 Reset 0 0 0 00000 Figure 17-12. PWM Channel Counter Registers (PWMCNTx)

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The counter is written (counter resets to $00)
The channel is disabled In this way, the output of the PWM will always be either the old waveform or the new waveform, not some variation in between. If the channel is not enabled, then writes to the period register will go directly to the latches as well as the buffer. NOTE Reads of this register return the most recent value written. Reads do not necessarily return the value of the currently active period due to the double buffering scheme. See Section 17.4.2.3, “PWM Period and Duty” for more information. To calculate the output period, take the selected clock source period for the channel of interest (A, B, SA, or SB) and multiply it by the value in the period register for that channel:
Left aligned output (CAEx = 0) PWMx Period = Channel Clock Period * PWMPERx
Center Aligned Output (CAEx = 1) PWMx Period = Channel Clock Period * (2 * PWMPERx) For boundary case programming values, please refer to Section 17.4.2.8, “PWM Boundary Cases”. 1 This register is available only when the corresponding channel exists and is reserved if that channel does not exist. Writes to a reserved register have no functional effect. Reads from a reserved register return zeroes. Read: Anytime Write: Anytime

17.3.2.12 PWM Channel Duty Registers (PWMDTYx)

There is a dedicated duty register for each channel. The value in this register determines the duty of the associated PWM channel. The duty value is compared to the counter and if it is equal to the counter value a match occurs and the output changes state. The duty registers for each channel are double buffered so that if they change while the channel is enabled, the change will NOT take effect until one of the following occurs:

The effective period ends
The counter is written (counter resets to $00) Module Base + 0x0014 = PWMPER0, 0x0015 = PWMPER1, 0x0016 = PWMPER2, 0x0017 = PWMPER3 Module Base + 0x0018 = PWMPER4, 0x0019 = PWMPER5, 0x001A = PWMPER6, 0x001B = PWMPER7 76543210 R Bit 7 6 5 4 3 2 1 Bit 0 W Reset 1 1 1 11111 Figure 17-13. PWM Channel Period Registers (PWMPERx)

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The channel is disabled In this way, the output of the PWM will always be either the old duty waveform or the new duty waveform, not some variation in between. If the channel is not enabled, then writes to the duty register will go directly to the latches as well as the buffer. NOTE Reads of this register return the most recent value written. Reads do not necessarily return the value of the currently active duty due to the double buffering scheme. See Section 17.4.2.3, “PWM Period and Duty” for more information. NOTE Depending on the polarity bit, the duty registers will contain the count of either the high time or the low time. If the polarity bit is one, the output starts high and then goes low when the duty count is reached, so the duty registers contain a count of the high time. If the polarity bit is zero, the output starts low and then goes high when the duty count is reached, so the duty registers contain a count of the low time. To calculate the output duty cycle (high time as a% of period) for a particular channel:
Polarity = 0 (PPOL x =0) Duty Cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100%
Polarity = 1 (PPOLx = 1) Duty Cycle = [PWMDTYx / PWMPERx] * 100% For boundary case programming values, please refer to Section 17.4.2.8, “PWM Boundary Cases”. 1 This register is available only when the corresponding channel exists and is reserved if that channel does not exist. Writes to a reserved register have no functional effect. Reads from a reserved register return zeroes. Read: Anytime Write: Anytime Module Base + 0x001C = PWMDTY0, 0x001D = PWMDTY1, 0x001E = PWMDTY2, 0x001F = PWMDTY3 Module Base + 0x0020 = PWMDTY4, 0x0021 = PWMDTY5, 0x0022 = PWMDTY6, 0x0023 = PWMDTY7 76543210 R Bit 7 6 5 4 3 2 1 Bit 0 W Reset 1 1 1 11111 Figure 17-14. PWM Channel Duty Registers (PWMDTYx)

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17.4 Functional Description

17.4.1 PWM Clock Select

There are four available clocks: clock A, clock B, clock SA (scaled A), and clock SB (scaled B). These four clocks are based on the bus clock. Clock A and B can be software selected to be 1, 1/2, 1/4, 1/8,..., 1/64, 1/128 times the bus clock. Clock SA uses clock A as an input and divides it further with a reloadable counter. Similarly, clock SB uses clock B as an input and divides it further with a reloadable counter. The rates available for clock SA are software selectable to be clock A divided by 2, 4, 6, 8,..., or 512 in increments of divide by 2. Similar rates are available for clock SB. Each PWM channel has the capability of selecting one of four clocks, clock A, Clock B, clock SA or clock SB. The block diagram in Figure 17-15 shows the four different clocks and how the scaled clocks are created.

17.4.1.1 Prescale

The input clock to the PWM prescaler is the bus clock. It can be disabled whenever the part is in freeze mode by setting the PFRZ bit in the PWMCTL register. If this bit is set, whenever the MCU is in freeze mode (freeze mode signal active) the input clock to the prescaler is disabled. This is useful for emulation in order to freeze the PWM. The input clock can also be disabled when all available PWM channels are disabled (PWMEx-0 = 0). This is useful for reducing power by disabling the prescale counter. Clock A and clock B are scaled values of the input clock. The value is software selectable for both clock A and clock B and has options of 1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, or 1/128 times the bus clock. The value selected for clock A is determined by the PCKA2, PCKA1, PCKA0 bits in the PWMPRCLK register. The value selected for clock B is determined by the PCKB2, PCKB1, PCKB0 bits also in the PWMPRCLK register.

17.4.1.2 Clock Scale

The scaled A clock uses clock A as an input and divides it further with a user programmable value and then divides this by 2. The scaled B clock uses clock B as an input and divides it further with a user programmable value and then divides this by 2. The rates available for clock SA are software selectable to be clock A divided by 2, 4, 6, 8,..., or 512 in increments of divide by 2. Similar rates are available for clock SB.

Pulse-Width Modulator (S12PWM8B8CV2) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 549 Figure 17-15. PWM Clock Select Block Diagram 1282 4 8 16 32 64 PCKB2 PCKB1 PCKB0 M U X Clock A Clock B Clock SA Clock A/2, A/4, A/6,....A/512 Prescale Scale Divide byPFRZ Freeze Mode Signal Bus Clock Clock Select M U X Clock to PWM Ch 0 M U X Clock to PWM Ch 2 M U X Clock to PWM Ch 1 M U X Clock to PWM Ch 4 M U X Clock to PWM Ch 5 M U X Clock to PWM Ch 6 M U X Clock to PWM Ch 7 M U X Clock to PWM Ch 3 Load DIV 2PWMSCLB Clock SB Clock B/2, B/4, B/6,....B/512 M U X PCKA2 PCKA1 PCKA0 PWME7-0 Count = 1 Load DIV 2PWMSCLA Count = 18-Bit Down Counter 8-Bit Down Counter Prescaler Taps: Maximum possible channels, scalable in pairs from PWM0 to PWM7. PCLK0 PCLKAB0 PCLK1 PCLKAB1 PCLK7 PCLKAB7 PCLK6 PCLKAB6 PCLK5 PCLKAB5 PCLK4 PCLKAB4 PCLK3 PCLKAB3 PCLK2 PCLKAB2

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Clock A is used as an input to an 8-bit down counter. This down counter loads a user programmable scale value from the scale register (PWMSCLA). When the down counter reaches one, a pulse is output and the 8-bit counter is re-loaded. The output signal from this circuit is further divided by two. This gives a greater range with only a slight reduction in granularity. Clock SA equals clock A divided by two times the value in the PWMSCLA register. NOTE Clock SA = Clock A / (2 * PWMSCLA) When PWMSCLA = $00, PWMSCLA value is considered a full scale value of 256. Clock A is thus divided by 512. Similarly, clock B is used as an input to an 8-bit down counter followed by a divide by two producing clock SB. Thus, clock SB equals clock B divided by two times the value in the PWMSCLB register. NOTE Clock SB = Clock B / (2 * PWMSCLB) When PWMSCLB = $00, PWMSCLB value is considered a full scale value of 256. Clock B is thus divided by 512. As an example, consider the case in which the user writes $FF into the PWMSCLA register. Clock A for this case will be E (bus clock) divided by 4. A pulse will occur at a rate of once every 255x4 E cycles. Passing this through the divide by two circuit produces a clock signal at an E divided by 2040 rate. Similarly, a value of $01 in the PWMSCLA register when clock A is E divided by 4 will produce a clock at an E divided by 8 rate. Writing to PWMSCLA or PWMSCLB causes the associated 8-bit down counter to be re-loaded. Otherwise, when changing rates the counter would have to count down to $01 before counting at the proper rate. Forcing the associated counter to re-load the scale register value every time PWMSCLA or PWMSCLB is written prevents this. NOTE Writing to the scale registers while channels are operating can cause irregularities in the PWM outputs.

17.4.1.3 Clock Select

Each PWM channel has the capability of selecting one of four clocks, clock A, clock SA, clock B or clock SB. The clock selection is done with the PCLKx control bits in the PWMCLK register and PCLKABx control bits in PWMCLKAB register. For backward compatibility consideration, the reset value of PWMCLK and PWMCLKAB conﬁgures following default clock selection. For channels 0, 1, 4, and 5 the clock choices are clock A. For channels 2, 3, 6, and 7 the clock choices are clock B. NOTE Changing clock control bits while channels are operating can cause irregularities in the PWM outputs.

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17.4.2 PWM Channel Timers

The main part of the PWM module are the actual timers. Each of the timer channels has a counter, a period register and a duty register (each are 8-bit). The waveform output period is controlled by a match between the period register and the value in the counter. The duty is controlled by a match between the duty register and the counter value and causes the state of the output to change during the period. The starting polarity of the output is also selectable on a per channel basis. Shown below inFigure 17-16 is the block diagram for the PWM timer. Figure 17-16. PWM Timer Channel Block Diagram

17.4.2.1 PWM Enable

Each PWM channel has an enable bit (PWMEx) to start its waveform output. When any of the PWMEx bits are set (PWMEx = 1), the associated PWM output signal is enabled immediately. However, the actual PWM waveform is not available on the associated PWM output until its clock source begins its next cycle due to the synchronization of PWMEx and the clock source. An exception to this is when channels are NOTE The ﬁrst PWM cycle after enabling the channel can be irregular. Clock Source T R Q Q PPOLx From Port PWMP Data Register PWMEx To Pin Driver Gate 8-bit Compare = PWMDTYx 8-bit Compare = PWMPERx CAExT R Q Q 8-Bit Counter PWMCNTx M U X M U X (Clock Edge Sync) Up/Down Reset

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On the front end of the PWM timer, the clock is enabled to the PWM circuit by the PWMEx bit being high. There is an edge-synchronizing circuit to guarantee that the clock will only be enabled or disabled at an edge. When the channel is disabled (PWMEx = 0), the counter for the channel does not count.

17.4.2.2 PWM Polarity

Each channel has a polarity bit to allow starting a waveform cycle with a high or low signal. This is shown on the block diagram Figure 17-16 as a mux select of either the Q output or the Q output of the PWM output ﬂip ﬂop. When one of the bits in the PWMPOL register is set, the associated PWM channel output is high at the beginning of the waveform, then goes low when the duty count is reached. Conversely, if the polarity bit is zero, the output starts low and then goes high when the duty count is reached.

17.4.2.3 PWM Period and Duty

Dedicated period and duty registers exist for each channel and are double buffered so that if they change while the channel is enabled, the change will NOT take effect until one of the following occurs:

The effective period ends
The counter is written (counter resets to $00)
The channel is disabled In this way, the output of the PWM will always be either the old waveform or the new waveform, not some variation in between. If the channel is not enabled, then writes to the period and duty registers will go directly to the latches as well as the buffer. A change in duty or period can be forced into effect “immediately” by writing the new value to the duty and/or period registers and then writing to the counter. This forces the counter to reset and the new duty and/or period values to be latched. In addition, since the counter is readable, it is possible to know where the count is with respect to the duty value and software can be used to make adjustments NOTE When forcing a new period or duty into effect immediately, an irregular PWM cycle can occur. Depending on the polarity bit, the duty registers will contain the count of either the high time or the low time.

17.4.2.4 PWM Timer Counters

Each channel has a dedicated 8-bit up/down counter which runs at the rate of the selected clock source (see Section 17.4.1, “PWM Clock Select” for the available clock sources and rates). The counter compares to two registers, a duty register and a period register as shown in Figure 17-16. When the PWM counter matches the duty register, the output ﬂip-ﬂop changes state, causing the PWM waveform to also change state. A match between the PWM counter and the period register behaves differently depending on what output mode is selected as shown in Figure 17-16 and described in Section 17.4.2.5, “Left Aligned Outputs” and Section 17.4.2.6, “Center Aligned Outputs”.

Pulse-Width Modulator (S12PWM8B8CV2) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 553 Each channel counter can be read at anytime without affecting the count or the operation of the PWM channel. Any value written to the counter causes the counter to reset to $00, the counter direction to be set to up, the immediate load of both duty and period registers with values from the buffers, and the output to change according to the polarity bit. When the channel is disabled (PWMEx = 0), the counter stops. When a channel becomes enabled (PWMEx = 1), the associated PWM counter continues from the count in the PWMCNTx register. This allows the waveform to continue where it left off when the channel is re-enabled. When the channel is disabled, writing “0” to the period register will cause the counter to reset on the next selected clock. NOTE If the user wants to start a new “clean” PWM waveform without any “history” from the old waveform, the user must write to channel counter (PWMCNTx) prior to enabling the PWM channel (PWMEx = 1). Generally, writes to the counter are done prior to enabling a channel in order to start from a known state. However, writing a counter can also be done while the PWM channel is enabled (counting). The effect is similar to writing the counter when the channel is disabled, except that the new period is started immediately with the output set according to the polarity bit. NOTE Writing to the counter while the channel is enabled can cause an irregular PWM cycle to occur. The counter is cleared at the end of the effective period (seeSection 17.4.2.5, “Left Aligned Outputs”and Section 17.4.2.6, “Center Aligned Outputs” for more details).

17.4.2.5 Left Aligned Outputs

The PWM timer provides the choice of two types of outputs, left aligned or center aligned. They are selected with the CAEx bits in the PWMCAE register. If the CAEx bit is cleared (CAEx = 0), the corresponding PWM output will be left aligned. In left aligned output mode, the 8-bit counter is conﬁgured as an up counter only. It compares to two registers, a duty register and a period register as shown in the block diagram in Figure 17-16. When the PWM counter matches the duty register the output ﬂip-ﬂop changes state causing the PWM waveform to also change state. A match between the PWM counter and the period register resets the counter and the output ﬂip-ﬂop, as shown in Figure 17-16, as well as performing a load from the double buffer period and duty register to the associated registers, as described in Section 17.4.2.3, “PWM Period and Duty”. The counter counts from 0 to the value in the period register – 1. Table 17-12. PWM Timer Counter Conditions Counter Clears ($00) Counter Counts Counter Stops When PWMCNTx register written to any value When PWM channel is enabled (PWMEx = 1). Counts from last value in PWMCNTx. When PWM channel is disabled (PWMEx = 0) Effective period ends

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Changing the PWM output mode from left aligned to center aligned output (or vice versa) while channels are operating can cause irregularities in the PWM output. It is recommended to program the output mode before enabling the PWM channel. Figure 17-17. PWM Left Aligned Output Waveform To calculate the output frequency in left aligned output mode for a particular channel, take the selected clock source frequency for the channel (A, B, SA, or SB) and divide it by the value in the period register for that channel.

PWMx Frequency = Clock (A, B, SA, or SB) / PWMPERx
PWMx Duty Cycle (high time as a% of period): — Polarity = 0 (PPOLx = 0) Duty Cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100% — Polarity = 1 (PPOLx = 1) Duty Cycle = [PWMDTYx / PWMPERx] * 100% As an example of a left aligned output, consider the following case: Clock Source = E, where E = 10 MHz (100 ns period) PPOLx = 0 PWMPERx = 4 PWMDTYx = 1 PWMx Frequency = 10 MHz/4 = 2.5 MHz PWMx Period = 400 ns PWMx Duty Cycle = 3/4 *100% = 75% The output waveform generated is shown in Figure 17-18. Figure 17-18. PWM Left Aligned Output Example Waveform PWMDTYx Period = PWMPERx PPOLx = 0 PPOLx = 1 Period = 400 ns E = 100 ns Duty Cycle = 75%

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17.4.2.6 Center Aligned Outputs

For center aligned output mode selection, set the CAEx bit (CAEx = 1) in the PWMCAE register and the corresponding PWM output will be center aligned. The 8-bit counter operates as an up/down counter in this mode and is set to up whenever the counter is equal to $00. The counter compares to two registers, a duty register and a period register as shown in the block diagram in Figure 17-16. When the PWM counter matches the duty register, the output ﬂip-ﬂop changes state, causing the PWM waveform to also change state. A match between the PWM counter and the period register changes the counter direction from an up-count to a down-count. When the PWM counter decrements and matches the duty register again, the output ﬂip-ﬂop changes state causing the PWM output to also change state. When the PWM counter decrements and reaches zero, the counter direction changes from a down-count back to an up-count and a load from the double buffer period and duty registers to the associated registers is performed, as described inSection 17.4.2.3, “PWM Period and Duty”. The counter counts from 0 up to the value in the period register and then back down to 0. Thus the effective period is PWMPERx*2. NOTE Changing the PWM output mode from left aligned to center aligned output (or vice versa) while channels are operating can cause irregularities in the PWM output. It is recommended to program the output mode before enabling the PWM channel. Figure 17-19. PWM Center Aligned Output Waveform To calculate the output frequency in center aligned output mode for a particular channel, take the selected clock source frequency for the channel (A, B, SA, or SB) and divide it by twice the value in the period register for that channel.

PWMx Frequency = Clock (A, B, SA, or SB) / (2*PWMPERx)
PWMx Duty Cycle (high time as a% of period): — Polarity = 0 (PPOLx = 0) Duty Cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100% — Polarity = 1 (PPOLx = 1) Duty Cycle = [PWMDTYx / PWMPERx] * 100% As an example of a center aligned output, consider the following case: PPOLx = 0 PPOLx = 1 PWMDTYx PWMDTYx Period = PWMPERx*2 PWMPERxPWMPERx

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Clock Source = E, where E = 10 MHz (100 ns period) PPOLx = 0 PWMPERx = 4 PWMDTYx = 1 PWMx Frequency = 10 MHz/8 = 1.25 MHz PWMx Period = 800 ns PWMx Duty Cycle = 3/4 *100% = 75% Shown in Figure 17-20 is the output waveform generated. Figure 17-20. PWM Center Aligned Output Example Waveform

17.4.2.7 PWM 16-Bit Functions

The scalable PWM timer also has the option of generating up to 8-channels of 8-bits or 4-channels of 16-bits for greater PWM resolution. This 16-bit channel option is achieved through the concatenation of two 8-bit channels. The PWMCTL register contains four control bits, each of which is used to concatenate a pair of PWM channels into one 16-bit channel. Channels 6 and 7 are concatenated with the CON67 bit, channels 4 and 5 are concatenated with the CON45 bit, channels 2 and 3 are concatenated with the CON23 bit, and channels 0 and 1 are concatenated with the CON01 bit. NOTE Change these bits only when both corresponding channels are disabled. When channels 6 and 7 are concatenated, channel 6 registers become the high order bytes of the double byte channel, as shown in Figure 17-21. Similarly, when channels 4 and 5 are concatenated, channel 4 registers become the high order bytes of the double byte channel. When channels 2 and 3 are concatenated, channel 2 registers become the high order bytes of the double byte channel. When channels 0 and 1 are concatenated, channel 0 registers become the high order bytes of the double byte channel. When using the 16-bit concatenated mode, the clock source is determined by the low order 8-bit channel clock select control bits. That is channel 7 when channels 6 and 7 are concatenated, channel 5 when channels 4 and 5 are concatenated, channel 3 when channels 2 and 3 are concatenated, and channel 1 when channels 0 and 1 are concatenated. The resulting PWM is output to the pins of the corresponding low order 8-bit channel as also shown inFigure 17-21. The polarity of the resulting PWM output is controlled by the PPOLx bit of the corresponding low order 8-bit channel as well. E = 100 ns DUTY CYCLE = 75% E = 100 ns PERIOD = 800 ns

Pulse-Width Modulator (S12PWM8B8CV2) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 557 Figure 17-21. PWM 16-Bit Mode Once concatenated mode is enabled (CONxx bits set in PWMCTL register), enabling/disabling the corresponding 16-bit PWM channel is controlled by the low order PWMEx bit. In this case, the high order bytes PWMEx bits have no effect and their corresponding PWM output is disabled. PWMCNT6 PWMCNT7 PWM7 Clock Source 7 High Low Period/Duty Compare PWMCNT4 PWMCNT5 PWM5 Clock Source 5 High Low Period/Duty Compare PWMCNT2 PWMCNT3 PWM3 Clock Source 3 High Low Period/Duty Compare PWMCNT0 PWMCNT1 PWM1 Clock Source 1 High Low Period/Duty Compare Maximum possible 16-bit channels

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In concatenated mode, writes to the 16-bit counter by using a 16-bit access or writes to either the low or high order byte of the counter will reset the 16-bit counter. Reads of the 16-bit counter must be made by 16-bit access to maintain data coherency. Either left aligned or center aligned output mode can be used in concatenated mode and is controlled by the low order CAEx bit. The high order CAEx bit has no effect. Table 17-13 is used to summarize which channels are used to set the various control bits when in 16-bit mode.17.4.2.8 PWM Boundary Cases Table 17-14summarizes the boundary conditions for the PWM regardless of the output mode (left aligned or center aligned) and 8-bit (normal) or 16-bit (concatenation).

17.5 Resets

The reset state of each individual bit is listed within the Section 17.3.2, “Register Descriptions” which details the registers and their bit-ﬁelds. All special functions or modes which are initialized during or just following reset are described within this section.

The 8-bit up/down counter is conﬁgured as an up counter out of reset.
All the channels are disabled and all the counters do not count. Table 17-13. 16-bit Concatenation Mode Summary Note: Bits related to available channels have functional signiﬁcance. CONxx PWMEx PPOLx PCLKx CAEx PWMx Output CON67 PWME7 PPOL7 PCLK7 CAE7 PWM7 CON45 PWME5 PPOL5 PCLK5 CAE5 PWM5 CON23 PWME3 PPOL3 PCLK3 CAE3 PWM3 CON01 PWME1 PPOL1 PCLK1 CAE1 PWM1 Table 17-14. PWM Boundary Cases PWMDTYx PWMPERx PPOLx PWMx Output $00 (indicates no duty) >$00 1 Always low $00 (indicates no duty) >$00 0 Always high XX $00 1 (indicates no period) 1 Counter = $00 and does not count.

1 Always high

XX $00 1 (indicates no period)

0 Always low

= PWMPERx XX 1 Always high >= PWMPERx XX 0 Always low

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For channels 0, 1, 4, and 5 the clock choices are clock A.
For channels 2, 3, 6, and 7 the clock choices are clock B.

17.6 Interrupts

The PWM module has no interrupt.

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MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 561 Chapter 18 Serial Communication Interface (S12SCIV5)

18.1 Introduction

This block guide provides an overview of the serial communication interface (SCI) module. The SCI allows asynchronous serial communications with peripheral devices and other CPUs.

18.1.1 Glossary

IR: InfraRed IrDA: Infrared Design Associate IRQ: Interrupt Request LIN: Local Interconnect Network LSB: Least Signiﬁcant Bit MSB: Most Signiﬁcant Bit NRZ: Non-Return-to-Zero RZI: Return-to-Zero-Inverted RXD: Receive Pin SCI : Serial Communication Interface TXD: Transmit Pin Table 18-1. Revision History Version Number Revision Date Effective Date Author Description of Changes 05.03 12/25/2008 remove redundancy comments in Figure1-2 05.04 08/05/2009 fix typo, SCIBDL reset value be 0x04, not 0x00 05.05 06/03/2010 fix typo, Table 18-4,SCICR1 Even parity should be PT=0 fix typo, on page 18-582,should be BKDIF,not BLDIF

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18.1.2 Features

The SCI includes these distinctive features:

Full-duplex or single-wire operation
Standard mark/space non-return-to-zero (NRZ) format
Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse widths
13-bit baud rate selection
Programmable 8-bit or 9-bit data format
Separately enabled transmitter and receiver
Programmable polarity for transmitter and receiver
Programmable transmitter output parity
Two receiver wakeup methods: — Idle line wakeup — Address mark wakeup
Interrupt-driven operation with eight ﬂags: — Transmitter empty — Transmission complete — Receiver full — Idle receiver input — Receiver overrun — Noise error — Framing error — Parity error — Receive wakeup on active edge — Transmit collision detect supporting LIN — Break Detect supporting LIN
Receiver framing error detection
Hardware parity checking
1/16 bit-time noise detection

18.1.3 Modes of Operation

The SCI functions the same in normal, special, and emulation modes. It has two low power modes, wait and stop modes.

Run mode
Wait mode
Stop mode

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18.1.4 Block Diagram

Figure 18-1 is a high level block diagram of the SCI module, showing the interaction of various function blocks. Figure 18-1. SCI Block Diagram

18.2 External Signal Description

The SCI module has a total of two external pins.

18.2.1 TXD — Transmit Pin

The TXD pin transmits SCI (standard or infrared) data. It will idle high in either mode and is high impedance anytime the transmitter is disabled.

18.2.2 RXD — Receive Pin

The RXD pin receives SCI (standard or infrared) data. An idle line is detected as a line high. This input is ignored when the receiver is disabled and should be terminated to a known voltage.

18.3 Memory Map and Register Deﬁnition

This section provides a detailed description of all the SCI registers. SCI Data Register RXD Data In Data Out TXD Receive Shift RegisterInfrared Decoder Receive & Wakeup Control Data Format Control Transmit Control Baud Rate Generator Bus Clock Transmit Shift Register SCI Data Register Receive Interrupt Generation Transmit Interrupt Generation Infrared Encoder IDLE RDRF/OR TC TDRE BRKD BERR RXEDG SCI Interrupt Request

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18.3.1 Module Memory Map and Register Deﬁnition

The memory map for the SCI module is given below inFigure 18-2. The address listed for each register is the address offset. The total address for each register is the sum of the base address for the SCI module and the address offset for each register.

18.3.2 Register Descriptions

This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated ﬁgure number. Writes to a reserved register locations do not have any effect and reads of these locations return a zero. Details of register bit and ﬁeld function follow the register diagrams, in bit order. Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x0000 SCIBDH1 R IREN TNP1 TNP0 SBR12 SBR11 SBR10 SBR9 SBR8 W 0x0001 SCIBDL1 R SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 W 0x0002 SCICR11 R LOOPS SCISWAI RSRC M WAKE ILT PE PT W 0x0000 SCIASR12 R RXEDGIF 0000 BERRV BERRIF BKDIF W 0x0001 SCIACR12 R RXEDGIE 00000 BERRIE BKDIE W 0x0002 SCIACR22 R 00000 BERRM1 BERRM0 BKDFE W 0x0003 SCICR2 R TIE TCIE RIE ILIE TE RE RWU SBK W 0x0004 SCISR1 R TDRE TC RDRF IDLE OR NF FE PF W 0x0005 SCISR2 R AMAP TXPOL RXPOL BRK13 TXDIR RAF W = Unimplemented or Reserved Figure 18-2. SCI Register Summary (Sheet 1 of 2)

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18.3.2.1 SCI Baud Rate Registers (SCIBDH, SCIBDL)

Read: Anytime, if AMAP = 0. If only SCIBDH is written to, a read will not return the correct data until SCIBDL is written to as well, following a write to SCIBDH. Write: Anytime, if AMAP = 0. NOTE Those two registers are only visible in the memory map if AMAP = 0 (reset condition). The SCI baud rate register is used by to determine the baud rate of the SCI, and to control the infrared modulation/demodulation submodule. 0x0006 SCIDRH RR 8 000000 W 0x0007 SCIDRL R R 7R 6R 5R 4R 3R 2R 1R 0 W T 7T 6T 5T 4T 3T 2T 1T 0 1.These registers are accessible if the AMAP bit in the SCISR2 register is set to zero. 2,These registers are accessible if the AMAP bit in the SCISR2 register is set to one. Module Base + 0x0000 76543210 R IREN TNP1 TNP0 SBR12 SBR11 SBR10 SBR9 SBR8 W Reset 0 0 0 00000 Figure 18-3. SCI Baud Rate Register (SCIBDH) Module Base + 0x0001 76543210 R SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 W Reset 0 0 0 00100 Figure 18-4. SCI Baud Rate Register (SCIBDL) Register Name Bit 7 6 5 4 3 2 1 Bit 0 = Unimplemented or Reserved Figure 18-2. SCI Register Summary (Sheet 2 of 2)

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18.3.2.2 SCI Control Register 1 (SCICR1)

Read: Anytime, if AMAP = 0. Write: Anytime, if AMAP = 0. NOTE This register is only visible in the memory map if AMAP = 0 (reset condition). Table 18-2. SCIBDH and SCIBDL Field Descriptions Field Description IREN Infrared Enable Bit — This bit enables/disables the infrared modulation/demodulation submodule.

0 IR disabled

1 IR enabled

6:5 TNP[1:0] Transmitter Narrow Pulse Bits— These bits enable whether the SCI transmits a 1/16, 3/16, 1/32 or 1/4 narrow pulse. See Table 18-3. 4:0 7:0 SBR[12:0] SCI Baud Rate Bits — The baud rate for the SCI is determined by the bits in this register. The baud rate is calculated two different ways depending on the state of the IREN bit. The formulas for calculating the baud rate are: When IREN = 0 then, SCI baud rate = SCI bus clock / (16 x SBR[12:0]) When IREN = 1 then, SCI baud rate = SCI bus clock / (32 x SBR[12:1]) Note: The baud rate generator is disabled after reset and not started until the TE bit or the RE bit is set for the ﬁrst time. The baud rate generator is disabled when (SBR[12:0] = 0 and IREN = 0) or (SBR[12:1] = 0 and IREN = 1). Note: Writing to SCIBDH has no effect without writing to SCIBDL, because writing to SCIBDH puts the data in a temporary location until SCIBDL is written to. Table 18-3. IRSCI Transmit Pulse Width TNP[1:0] Narrow Pulse Width 11 1/4 10 1/32 01 1/16 00 3/16 Module Base + 0x0002 76543210 R LOOPS SCISWAI RSRC M WAKE ILT PE PT W Reset 0 0 0 00000 Figure 18-5. SCI Control Register 1 (SCICR1)

Serial Communication Interface (S12SCIV5) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 567 Table 18-4. SCICR1 Field Descriptions Field Description LOOPS Loop Select Bit— LOOPS enables loop operation. In loop operation, the RXD pin is disconnected from the SCI and the transmitter output is internally connected to the receiver input. Both the transmitter and the receiver must be enabled to use the loop function.

0 Normal operation enabled

1 Loop operation enabled

The receiver input is determined by the RSRC bit. SCISWAI SCI Stop in Wait Mode Bit — SCISWAI disables the SCI in wait mode.

0 SCI enabled in wait mode

1 SCI disabled in wait mode

Receiver Source Bit — When LOOPS = 1, the RSRC bit determines the source for the receiver shift register input. See Table 18-5.

0 Receiver input internally connected to transmitter output

1 Receiver input connected externally to transmitter

M Data Format Mode Bit — MODE determines whether data characters are eight or nine bits long.

0 One start bit, eight data bits, one stop bit

1 One start bit, nine data bits, one stop bit

Wakeup Condition Bit — WAKE determines which condition wakes up the SCI: a logic 1 (address mark) in the most signiﬁcant bit position of a received data character or an idle condition on the RXD pin.

0 Idle line wakeup

1 Address mark wakeup

Idle Line Type Bit — ILT determines when the receiver starts counting logic 1s as idle character bits. The counting begins either after the start bit or after the stop bit. If the count begins after the start bit, then a string of logic 1s preceding the stop bit may cause false recognition of an idle character. Beginning the count after the stop bit avoids false idle character recognition, but requires properly synchronized transmissions.

0 Idle character bit count begins after start bit

1 Idle character bit count begins after stop bit

Parity Enable Bit — PE enables the parity function. When enabled, the parity function inserts a parity bit in the most signiﬁcant bit position.

0 Parity function disabled

1 Parity function enabled

Parity Type Bit— PT determines whether the SCI generates and checks for even parity or odd parity. With even parity, an even number of 1s clears the parity bit and an odd number of 1s sets the parity bit. With odd parity, an odd number of 1s clears the parity bit and an even number of 1s sets the parity bit.

0 Even parity

1 Odd parity

Table 18-5. Loop Functions LOOPS RSRC Function 0 x Normal operation 1 0 Loop mode with transmitter output internally connected to receiver input 1 1 Single-wire mode with TXD pin connected to receiver input

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18.3.2.3 SCI Alternative Status Register 1 (SCIASR1)

Read: Anytime, if AMAP = 1 Write: Anytime, if AMAP = 1

18.3.2.4 SCI Alternative Control Register 1 (SCIACR1)

Read: Anytime, if AMAP = 1 Write: Anytime, if AMAP = 1 Module Base + 0x0000 76543210 R RXEDGIF 0 0 0 0 BERRV BERRIF BKDIF W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 18-6. SCI Alternative Status Register 1 (SCIASR1) Table 18-6. SCIASR1 Field Descriptions Field Description RXEDGIF Receive Input Active Edge Interrupt Flag — RXEDGIF is asserted, if an active edge (falling if RXPOL = 0, rising if RXPOL = 1) on the RXD input occurs. RXEDGIF bit is cleared by writing a “1” to it.

0 No active receive on the receive input has occurred

1 An active edge on the receive input has occurred

Bit Error Value — BERRV reﬂects the state of the RXD input when the bit error detect circuitry is enabled and a mismatch to the expected value happened. The value is only meaningful, if BERRIF = 1.

0 A low input was sampled, when a high was expected

1 A high input reassembled, when a low was expected

Bit Error Interrupt Flag — BERRIF is asserted, when the bit error detect circuitry is enabled and if the value sampled at the RXD input does not match the transmitted value. If the BERRIE interrupt enable bit is set an interrupt will be generated. The BERRIF bit is cleared by writing a “1” to it.

0 No mismatch detected

1 A mismatch has occurred

Break Detect Interrupt Flag — BKDIF is asserted, if the break detect circuitry is enabled and a break signal is received. If the BKDIE interrupt enable bit is set an interrupt will be generated. The BKDIF bit is cleared by writing a “1” to it.

0 No break signal was received

1 A break signal was received

R RXEDGIE 00000 BERRIE BKDIE W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 18-7. SCI Alternative Control Register 1 (SCIACR1)

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18.3.2.5 SCI Alternative Control Register 2 (SCIACR2)

Read: Anytime, if AMAP = 1 Write: Anytime, if AMAP = 1 Table 18-7. SCIACR1 Field Descriptions Field Description RSEDGIE Receive Input Active Edge Interrupt Enable— RXEDGIE enables the receive input active edge interrupt ﬂag, RXEDGIF , to generate interrupt requests.

0 RXEDGIF interrupt requests disabled

1 RXEDGIF interrupt requests enabled

Bit Error Interrupt Enable — BERRIE enables the bit error interrupt ﬂag, BERRIF , to generate interrupt requests.

0 BERRIF interrupt requests disabled

1 BERRIF interrupt requests enabled

Break Detect Interrupt Enable — BKDIE enables the break detect interrupt ﬂag, BKDIF , to generate interrupt requests.

0 BKDIF interrupt requests disabled

1 BKDIF interrupt requests enabled

W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 18-8. SCI Alternative Control Register 2 (SCIACR2) Table 18-8. SCIACR2 Field Descriptions Field Description 2:1 BERRM[1:0] Bit Error Mode — Those two bits determines the functionality of the bit error detect feature. See Table 18-9. BKDFE Break Detect Feature Enable — BKDFE enables the break detect circuitry.

0 Break detect circuit disabled

1 Break detect circuit enabled

Table 18-9. Bit Error Mode Coding BERRM1 BERRM0 Function 0 0 Bit error detect circuit is disabled 0 1 Receive input sampling occurs during the 9th time tick of a transmitted bit (refer to Figure 18-19) 1 0 Receive input sampling occurs during the 13th time tick of a transmitted bit (refer to Figure 18-19)

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18.3.2.6 SCI Control Register 2 (SCICR2)

Read: Anytime Write: Anytime 1 1 Reserved Module Base + 0x0003 76543210 R TIE TCIE RIE ILIE TE RE RWU SBK W Reset 0 0 0 00000 Figure 18-9. SCI Control Register 2 (SCICR2) Table 18-10. SCICR2 Field Descriptions Field Description TIE Transmitter Interrupt Enable Bit — TIE enables the transmit data register empty ﬂag, TDRE, to generate interrupt requests.

0 TDRE interrupt requests disabled

1 TDRE interrupt requests enabled

Transmission Complete Interrupt Enable Bit— TCIE enables the transmission complete ﬂag, TC, to generate interrupt requests.

0 TC interrupt requests disabled

1 TC interrupt requests enabled

Receiver Full Interrupt Enable Bit— RIE enables the receive data register full ﬂag, RDRF , or the overrun ﬂag, OR, to generate interrupt requests.

0 RDRF and OR interrupt requests disabled

1 RDRF and OR interrupt requests enabled

Idle Line Interrupt Enable Bit — ILIE enables the idle line ﬂag, IDLE, to generate interrupt requests.

0 IDLE interrupt requests disabled

1 IDLE interrupt requests enabled

Transmitter Enable Bit — TE enables the SCI transmitter and conﬁgures the TXD pin as being controlled by the SCI. The TE bit can be used to queue an idle preamble.

0 Transmitter disabled

1 Transmitter enabled

Receiver Enable Bit — RE enables the SCI receiver.

0 Receiver disabled

1 Receiver enabled

Table 18-9. Bit Error Mode Coding BERRM1 BERRM0 Function

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18.3.2.7 SCI Status Register 1 (SCISR1)

The SCISR1 and SCISR2 registers provides inputs to the MCU for generation of SCI interrupts. Also, these registers can be polled by the MCU to check the status of these bits. The ﬂag-clearing procedures require that the status register be read followed by a read or write to the SCI data register.It is permissible to execute other instructions between the two steps as long as it does not compromise the handling of I/O, but the order of operations is important for ﬂag clearing. Read: Anytime Write: Has no meaning or effect RWU Receiver Wakeup Bit — Standby state 0 Normal operation. 1 RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU. SBK Send Break Bit — Toggling SBK sends one break character (10 or 11 logic 0s, respectively 13 or 14 logics 0s if BRK13 is set). Toggling implies clearing the SBK bit before the break character has ﬁnished transmitting. As long as SBK is set, the transmitter continues to send complete break characters (10 or 11 bits, respectively 13 or 14 bits).

0 No break characters

1 Transmit break characters

R TDRE TC RDRF IDLE OR NF FE PF W Reset 1 1 0 00000 = Unimplemented or Reserved Figure 18-10. SCI Status Register 1 (SCISR1) Table 18-10. SCICR2 Field Descriptions (continued) Field Description

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Table 18-11. SCISR1 Field Descriptions Field Description TDRE Transmit Data Register Empty Flag — TDRE is set when the transmit shift register receives a byte from the SCI data register. When TDRE is 1, the transmit data register (SCIDRH/L) is empty and can receive a new value to transmit.Clear TDRE by reading SCI status register 1 (SCISR1), with TDRE set and then writing to SCI data register low (SCIDRL).

0 No byte transferred to transmit shift register

1 Byte transferred to transmit shift register; transmit data register empty

Transmit Complete Flag— TC is set low when there is a transmission in progress or when a preamble or break character is loaded. TC is set high when the TDRE ﬂag is set and no data, preamble, or break character is being transmitted.When TC is set, the TXD pin becomes idle (logic 1). Clear TC by reading SCI status register 1 (SCISR1) with TC set and then writing to SCI data register low (SCIDRL). TC is cleared automatically when data, preamble, or break is queued and ready to be sent. TC is cleared in the event of a simultaneous set and clear of the TC ﬂag (transmission not complete).

0 Transmission in progress

1 No transmission in progress

Receive Data Register Full Flag — RDRF is set when the data in the receive shift register transfers to the SCI data register. Clear RDRF by reading SCI status register 1 (SCISR1) with RDRF set and then reading SCI data register low (SCIDRL).

0 Data not available in SCI data register

1 Received data available in SCI data register

Idle Line Flag — IDLE is set when 10 consecutive logic 1s (if M = 0) or 11 consecutive logic 1s (if M =1) appear on the receiver input. Once the IDLE ﬂag is cleared, a valid frame must again set the RDRF ﬂag before an idle condition can set the IDLE ﬂag.Clear IDLE by reading SCI status register 1 (SCISR1) with IDLE set and then reading SCI data register low (SCIDRL).

0 Receiver input is either active now or has never become active since the IDLE ﬂag was last cleared

1 Receiver input has become idle

Note: When the receiver wakeup bit (RWU) is set, an idle line condition does not set the IDLE ﬂag. OR Overrun Flag — OR is set when software fails to read the SCI data register before the receive shift register receives the next frame. The OR bit is set immediately after the stop bit has been completely received for the second frame. The data in the shift register is lost, but the data already in the SCI data registers is not affected. Clear OR by reading SCI status register 1 (SCISR1) with OR set and then reading SCI data register low (SCIDRL).

0 No overrun

1 Overrun

Note: OR ﬂag may read back as set when RDRF ﬂag is clear. This may happen if the following sequence of events occurs: 1. After the ﬁrst frame is received, read status register SCISR1 (returns RDRF set and OR ﬂag clear); 2. Receive second frame without reading the ﬁrst frame in the data register (the second frame is not received and OR ﬂag is set); 3. Read data register SCIDRL (returns ﬁrst frame and clears RDRF ﬂag in the status register); 4. Read status register SCISR1 (returns RDRF clear and OR set). Event 3 may be at exactly the same time as event 2 or any time after. When this happens, a dummy SCIDRL read following event 4 will be required to clear the OR ﬂag if further frames are to be received. NF Noise Flag — NF is set when the SCI detects noise on the receiver input. NF bit is set during the same cycle as the RDRF ﬂag but does not get set in the case of an overrun. Clear NF by reading SCI status register 1(SCISR1), and then reading SCI data register low (SCIDRL).

0 No noise

1 Noise

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18.3.2.8 SCI Status Register 2 (SCISR2)

Read: Anytime Write: Anytime FE Framing Error Flag — FE is set when a logic 0 is accepted as the stop bit. FE bit is set during the same cycle as the RDRF ﬂag but does not get set in the case of an overrun. FE inhibits further data reception until it is cleared. Clear FE by reading SCI status register 1 (SCISR1) with FE set and then reading the SCI data register low (SCIDRL).

0 No framing error

1 Framing error

Parity Error Flag — PF is set when the parity enable bit (PE) is set and the parity of the received data does not match the parity type bit (PT). PF bit is set during the same cycle as the RDRF ﬂag but does not get set in the case of an overrun. Clear PF by reading SCI status register 1 (SCISR1), and then reading SCI data register low (SCIDRL).

0 No parity error

1 Parity error

R AMAP TXPOL RXPOL BRK13 TXDIR RAF W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 18-11. SCI Status Register 2 (SCISR2) Table 18-12. SCISR2 Field Descriptions Field Description AMAP Alternative Map — This bit controls which registers sharing the same address space are accessible. In the reset condition the SCI behaves as previous versions. Setting AMAP=1 allows the access to another set of control and status registers and hides the baud rate and SCI control Register 1.

0 The registers labelled SCIBDH (0x0000),SCIBDL (0x0001), SCICR1 (0x0002) are accessible

1 The registers labelled SCIASR1 (0x0000),SCIACR1 (0x0001), SCIACR2 (0x00002) are accessible

Transmit Polarity— This bit control the polarity of the transmitted data. In NRZ format, a one is represented by a mark and a zero is represented by a space for normal polarity, and the opposite for inverted polarity. In IrDA format, a zero is represented by short high pulse in the middle of a bit time remaining idle low for a one for normal polarity, and a zero is represented by short low pulse in the middle of a bit time remaining idle high for a one for inverted polarity.

0 Normal polarity

1 Inverted polarity

Table 18-11. SCISR1 Field Descriptions (continued) Field Description

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18.3.2.9 SCI Data Registers (SCIDRH, SCIDRL)

Read: Anytime; reading accesses SCI receive data register Write: Anytime; writing accesses SCI transmit data register; writing to R8 has no effect RXPOL Receive Polarity — This bit control the polarity of the received data. In NRZ format, a one is represented by a mark and a zero is represented by a space for normal polarity, and the opposite for inverted polarity. In IrDA format, a zero is represented by short high pulse in the middle of a bit time remaining idle low for a one for normal polarity, and a zero is represented by short low pulse in the middle of a bit time remaining idle high for a one for inverted polarity. Break Transmit Character Length — This bit determines whether the transmit break character is 10 or 11 bit respectively 13 or 14 bits long. The detection of a framing error is not affected by this bit.

0 Break character is 10 or 11 bit long

1 Break character is 13 or 14 bit long

Transmitter Pin Data Direction in Single-Wire Mode — This bit determines whether the TXD pin is going to be used as an input or output, in the single-wire mode of operation. This bit is only relevant in the single-wire mode of operation.

0 TXD pin to be used as an input in single-wire mode

1 TXD pin to be used as an output in single-wire mode

Receiver Active Flag — RAF is set when the receiver detects a logic 0 during the RT1 time period of the start bit search. RAF is cleared when the receiver detects an idle character.

0 No reception in progress

1 Reception in progress

W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 18-12. SCI Data Registers (SCIDRH) Module Base + 0x0007 76543210 R R 7R 6R 5R 4R 3R 2R 1R 0 W T7 T6 T5 T4 T3 T2 T1 T0 Reset 0 0 0 00000 Figure 18-13. SCI Data Registers (SCIDRL) Table 18-12. SCISR2 Field Descriptions (continued) Field Description

Serial Communication Interface (S12SCIV5) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 575 NOTE If the value of T8 is the same as in the previous transmission, T8 does not have to be rewritten.The same value is transmitted until T8 is rewritten In 8-bit data format, only SCI data register low (SCIDRL) needs to be accessed. When transmitting in 9-bit data format and using 8-bit write instructions, write ﬁrst to SCI data register high (SCIDRH), then SCIDRL.

18.4 Functional Description

This section provides a complete functional description of the SCI block, detailing the operation of the design from the end user perspective in a number of subsections. Figure 18-14 shows the structure of the SCI module. The SCI allows full duplex, asynchronous, serial communication between the CPU and remote devices, including other CPUs. The SCI transmitter and receiver operate independently, although they use the same baud rate generator. The CPU monitors the status of the SCI, writes the data to be transmitted, and processes received data. Table 18-13. SCIDRH and SCIDRL Field Descriptions Field Description SCIDRH Received Bit 8 — R8 is the ninth data bit received when the SCI is conﬁgured for 9-bit data format (M = 1). SCIDRH Transmit Bit 8 — T8 is the ninth data bit transmitted when the SCI is conﬁgured for 9-bit data format (M = 1). SCIDRL 7:0 R[7:0] T[7:0] R7:R0 — Received bits seven through zero for 9-bit or 8-bit data formats T7:T0 — Transmit bits seven through zero for 9-bit or 8-bit formats

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Figure 18-14. Detailed SCI Block Diagram

18.4.1 Infrared Interface Submodule

This module provides the capability of transmitting narrow pulses to an IR LED and receiving narrow pulses and transforming them to serial bits, which are sent to the SCI. The IrDA physical layer speciﬁcation deﬁnes a half-duplex infrared communication link for exchange data. The full standard includes data rates up to 16 Mbits/s. This design covers only data rates between 2.4 Kbits/s and 115.2 Kbits/s. The infrared submodule consists of two major blocks: the transmit encoder and the receive decoder. The SCI transmits serial bits of data which are encoded by the infrared submodule to transmit a narrow pulse SCI Data Receive Shift Register SCI Data Register Transmit Shift Register Register Baud Rate Generator SBR12:SBR0 Bus Transmit Control÷16 Receive and Wakeup Data Format Control Control PF FE NF RDRF IDLE TIE OR TCIE TDRE TC RAF LOOPS RWU RE PE ILT PT WAKE M Clock ILIE RIE RXD RSRC SBK LOOPS TE RSRC IREN R16XCLK Ir_RXD TXDIr_TXD R16XCLK R32XCLK TNP[1:0] IREN Transmit Encoder Receive Decoder SCRXD SCTXD Infrared Infrared TC TDRE RDRF/OR IDLE Active Edge Detect Break Detect RXD BKDFE BERRM[1:0] BKDIE BKDIF RXEDGIE RXEDGIF BERRIE BERRIF SCI Interrupt Request LIN Transmit Collision Detect

Serial Communication Interface (S12SCIV5) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 577 for every zero bit. No pulse is transmitted for every one bit. When receiving data, the IR pulses should be detected using an IR photo diode and transformed to CMOS levels by the IR receive decoder (external from the MCU). The narrow pulses are then stretched by the infrared submodule to get back to a serial bit stream to be received by the SCI.The polarity of transmitted pulses and expected receive pulses can be inverted so that a direct connection can be made to external IrDA transceiver modules that uses active low pulses. The infrared submodule receives its clock sources from the SCI. One of these two clocks are selected in the infrared submodule in order to generate either 3/16, 1/16, 1/32 or 1/4 narrow pulses during transmission. The infrared block receives two clock sources from the SCI, R16XCLK and R32XCLK, which are conﬁgured to generate the narrow pulse width during transmission. The R16XCLK and R32XCLK are internal clocks with frequencies 16 and 32 times the baud rate respectively. Both R16XCLK and R32XCLK clocks are used for transmitting data. The receive decoder uses only the R16XCLK clock.

18.4.1.1 Infrared Transmit Encoder

The infrared transmit encoder converts serial bits of data from transmit shift register to the TXD pin. A narrow pulse is transmitted for a zero bit and no pulse for a one bit. The narrow pulse is sent in the middle of the bit with a duration of 1/32, 1/16, 3/16 or 1/4 of a bit time. A narrow high pulse is transmitted for a zero bit when TXPOL is cleared, while a narrow low pulse is transmitted for a zero bit when TXPOL is set.

18.4.1.2 Infrared Receive Decoder

The infrared receive block converts data from the RXD pin to the receive shift register. A narrow pulse is expected for each zero received and no pulse is expected for each one received. A narrow high pulse is expected for a zero bit when RXPOL is cleared, while a narrow low pulse is expected for a zero bit when RXPOL is set. This receive decoder meets the edge jitter requirement as deﬁned by the IrDA serial infrared physical layer speciﬁcation.

18.4.2 LIN Support

This module provides some basic support for the LIN protocol. At ﬁrst this is a break detect circuitry making it easier for the LIN software to distinguish a break character from an incoming data stream. As a further addition is supports a collision detection at the bit level as well as cancelling pending transmissions.

18.4.3 Data Format

The SCI uses the standard NRZ mark/space data format. When Infrared is enabled, the SCI uses RZI data format where zeroes are represented by light pulses and ones remain low. See Figure 18-15 below.

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Figure 18-15. SCI Data Formats Each data character is contained in a frame that includes a start bit, eight or nine data bits, and a stop bit. Clearing the M bit in SCI control register 1 conﬁgures the SCI for 8-bit data characters. A frame with eight data bits has a total of 10 bits. Setting the M bit conﬁgures the SCI for nine-bit data characters. A frame with nine data bits has a total of 11 bits. When the SCI is conﬁgured for 9-bit data characters, the ninth data bit is the T8 bit in SCI data register high (SCIDRH). It remains unchanged after transmission and can be used repeatedly without rewriting it. A frame with nine data bits has a total of 11 bits. Table 18-14. Example of 8-Bit Data Formats Start Bit Data Bits Address Bits Parity Bits Stop Bit 1 8001 1 7011 17 1

1 The address bit identiﬁes the frame as an address

Table 18-15. Example of 9-Bit Data Formats Start Bit Data Bits Address Bits Parity Bits Stop Bit 1 9001 1 8011 18 1 (Bit M in SCICR1 Clear) Start Bit Bit 0 NEXT STOP Bit START Bit 9-Bit Data Format (Bit M in SCICR1 Set) Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 2 Bit 3 Bit 4 Bit 6 Bit 7 POSSIBLE PARITY Bit Possible Parity Bit Standard SCI Data Infrared SCI DataStandard SCI Data Infrared SCI Data

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18.4.4 Baud Rate Generation

A 13-bit modulus counter in the baud rate generator derives the baud rate for both the receiver and the transmitter. The value from 0 to 8191 written to the SBR12:SBR0 bits determines the bus clock divisor. The SBR bits are in the SCI baud rate registers (SCIBDH and SCIBDL). The baud rate clock is synchronized with the bus clock and drives the receiver. The baud rate clock divided by 16 drives the transmitter. The receiver has an acquisition rate of 16 samples per bit time. Baud rate generation is subject to one source of error:

Integer division of the bus clock may not give the exact target frequency. Table 18-16 lists some examples of achieving target baud rates with a bus clock frequency of 25 MHz. When IREN = 0 then, SCI baud rate = SCI bus clock / (16 * SCIBR[12:0]) Table 18-16. Baud Rates (Example: Bus Clock = 25 MHz) Bits SBR[12:0] Receiver Clock (Hz) Transmitter Clock (Hz) Target Baud Rate Error (%) 41 609,756.1 38,109.8 38,400 .76 81 308,642.0 19,290.1 19,200 .47 163 153,374.2 9585.9 9,600 .16 326 76,687.1 4792.9 4,800 .15 651 38,402.5 2400.2 2,400 .01 1302 19,201.2 1200.1 1,200 .01 2604 9600.6 600.0 600 .00 5208 4800.0 300.0 300 .00

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18.4.5 Transmitter

Figure 18-16. Transmitter Block Diagram

18.4.5.1 Transmitter Character Length

The SCI transmitter can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI control register 1 (SCICR1) determines the length of data characters. When transmitting 9-bit data, bit T8 in SCI data register high (SCIDRH) is the ninth bit (bit 8).

18.4.5.2 Character Transmission

To transmit data, the MCU writes the data bits to the SCI data registers (SCIDRH/SCIDRL), which in turn are transferred to the transmitter shift register. The transmit shift register then shifts a frame out through the TXD pin, after it has prefaced them with a start bit and appended them with a stop bit. The SCI data registers (SCIDRH and SCIDRL) are the write-only buffers between the internal data bus and the transmit shift register. PE PT H876543210L 11-Bit Transmit Register Stop Start TIE TDRE TCIE SBK TC Parity Generation MSB SCI Data RegistersLoad from SCIDR Shift Enable Preamble (All 1s) Break (All 0s) Transmitter Control M Internal Bus SBR12:SBR0 Baud Divider ÷ 16Bus Clock TE SCTXD TXPOL LOOPS LOOP RSRC CONTROL To Receiver Transmit Collision Detect TDRE IRQ TC IRQ SCTXD SCRXD (From Receiver)TCIE BERRIF BER IRQ BERRM[1:0]

Serial Communication Interface (S12SCIV5) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 581 The SCI also sets a ﬂag, the transmit data register empty ﬂag (TDRE), every time it transfers data from the buffer (SCIDRH/L) to the transmitter shift register.The transmit driver routine may respond to this ﬂag by writing another byte to the Transmitter buffer (SCIDRH/SCIDRL), while the shift register is still shifting out the ﬁrst byte. To initiate an SCI transmission: 1. Conﬁgure the SCI: a) Select a baud rate. Write this value to the SCI baud registers (SCIBDH/L) to begin the baud rate generator. Remember that the baud rate generator is disabled when the baud rate is zero. Writing to the SCIBDH has no effect without also writing to SCIBDL. b) Write to SCICR1 to conﬁgure word length, parity, and other conﬁguration bits (LOOPS,RSRC,M,W AKE,ILT,PE,PT). c) Enable the transmitter, interrupts, receive, and wake up as required, by writing to the SCICR2 register bits (TIE,TCIE,RIE,ILIE,TE,RE,RWU,SBK). A preamble or idle character will now be shifted out of the transmitter shift register. 2. Transmit Procedure for each byte: a) Poll the TDRE ﬂag by reading the SCISR1 or responding to the TDRE interrupt. Keep in mind that the TDRE bit resets to one. b) If the TDRE ﬂag is set, write the data to be transmitted to SCIDRH/L, where the ninth bit is written to the T8 bit in SCIDRH if the SCI is in 9-bit data format. A new transmission will not result until the TDRE ﬂag has been cleared. 3. Repeat step 2 for each subsequent transmission. NOTE The TDRE ﬂag is set when the shift register is loaded with the next data to be transmitted from SCIDRH/L, which happens, generally speaking, a little over half-way through the stop bit of the previous frame. Speciﬁcally, this transfer occurs 9/16ths of a bit time AFTER the start of the stop bit of the previous frame. Writing the TE bit from 0 to a 1 automatically loads the transmit shift register with a preamble of 10 logic 1s (if M = 0) or 11 logic 1s (if M = 1). After the preamble shifts out, control logic transfers the data from the SCI data register into the transmit shift register. A logic 0 start bit automatically goes into the least signiﬁcant bit position of the transmit shift register. A logic 1 stop bit goes into the most signiﬁcant bit position. Hardware supports odd or even parity. When parity is enabled, the most signiﬁcant bit (MSB) of the data character is the parity bit. The transmit data register empty ﬂag, TDRE, in SCI status register 1 (SCISR1) becomes set when the SCI data register transfers a byte to the transmit shift register. The TDRE ﬂag indicates that the SCI data register can accept new data from the internal data bus. If the transmit interrupt enable bit, TIE, in SCI control register 2 (SCICR2) is also set, the TDRE ﬂag generates a transmitter interrupt request.

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When the transmit shift register is not transmitting a frame, the TXD pin goes to the idle condition, logic 1. If at any time software clears the TE bit in SCI control register 2 (SCICR2), the transmitter enable signal goes low and the transmit signal goes idle. If software clears TE while a transmission is in progress (TC = 0), the frame in the transmit shift register continues to shift out. To avoid accidentally cutting off the last frame in a message, always wait for TDRE to go high after the last frame before clearing TE. To separate messages with preambles with minimum idle line time, use this sequence between messages: 1. Write the last byte of the ﬁrst message to SCIDRH/L. 2. Wait for the TDRE ﬂag to go high, indicating the transfer of the last frame to the transmit shift register. 3. Queue a preamble by clearing and then setting the TE bit. 4. Write the ﬁrst byte of the second message to SCIDRH/L.

18.4.5.3 Break Characters

Writing a logic 1 to the send break bit, SBK, in SCI control register 2 (SCICR2) loads the transmit shift register with a break character. A break character contains all logic 0s and has no start, stop, or parity bit. Break character length depends on the M bit in SCI control register 1 (SCICR1). As long as SBK is at logic 1, transmitter logic continuously loads break characters into the transmit shift register. After software clears the SBK bit, the shift register ﬁnishes transmitting the last break character and then transmits at least one logic 1. The automatic logic 1 at the end of a break character guarantees the recognition of the start bit of the next frame. The SCI recognizes a break character when there are 10 or 11(M = 0 or M = 1) consecutive zero received. Depending if the break detect feature is enabled or not receiving a break character has these effects on SCI registers. If the break detect feature is disabled (BKDFE = 0):

Sets the framing error ﬂag, FE
Sets the receive data register full ﬂag, RDRF
Clears the SCI data registers (SCIDRH/L)
May set the overrun ﬂag, OR, noise ﬂag, NF, parity error ﬂag, PE, or the receiver active ﬂag, RAF (see 3.4.4 and 3.4.5 SCI Status Register 1 and 2) If the break detect feature is enabled (BKDFE = 1) there are two scenarios The break is detected right from a start bit or is detected during a byte reception.
Sets the break detect interrupt ﬂag, BKDIF
Does not change the data register full ﬂag, RDRF or overrun ﬂag OR
Does not change the framing error ﬂag FE, parity error ﬂag PE.
Does not clear the SCI data registers (SCIDRH/L)
May set noise ﬂag NF, or receiver active ﬂag RAF. 1. A Break character in this context are either 10 or 11 consecutive zero received bits

Serial Communication Interface (S12SCIV5) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 583 Figure 18-17 shows two cases of break detect. In trace RXD_1 the break symbol starts with the start bit, while in RXD_2 the break starts in the middle of a transmission. If BRKDFE = 1, in RXD_1 case there will be no byte transferred to the receive buffer and the RDRF ﬂag will not be modiﬁed. Also no framing error or parity error will be ﬂagged from this transfer. In RXD_2 case, however the break signal starts later during the transmission. At the expected stop bit position the byte received so far will be transferred to the receive buffer, the receive data register full ﬂag will be set, a framing error and if enabled and appropriate a parity error will be set. Once the break is detected the BRKDIF ﬂag will be set. Figure 18-17. Break Detection if BRKDFE = 1 (M = 0)

18.4.5.4 Idle Characters

An idle character (or preamble) contains all logic 1s and has no start, stop, or parity bit. Idle character length depends on the M bit in SCI control register 1 (SCICR1). The preamble is a synchronizing idle character that begins the ﬁrst transmission initiated after writing the TE bit from 0 to 1. If the TE bit is cleared during a transmission, the TXD pin becomes idle after completion of the transmission in progress. Clearing and then setting the TE bit during a transmission queues an idle character to be sent after the frame currently being transmitted. NOTE When queueing an idle character, return the TE bit to logic 1 before the stop bit of the current frame shifts out through the TXD pin. Setting TE after the stop bit appears on TXD causes data previously written to the SCI data register to be lost. Toggle the TE bit for a queued idle character while the TDRE ﬂag is set and immediately before writing the next byte to the SCI data register. If the TE bit is clear and the transmission is complete, the SCI is not the master of the TXD pin Start Bit Position Stop Bit Position BRKDIF = 1 FE = 1 BRKDIF = 1 RXD_1 RXD_2 123 4567 8 91 0 123 4567 8 91 0 Zero Bit Counter Zero Bit Counter . . . . . .

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18.4.5.5 LIN Transmit Collision Detection

This module allows to check for collisions on the LIN bus. Figure 18-18. Collision Detect Principle If the bit error circuit is enabled (BERRM[1:0] = 0:1 or = 1:0]), the error detect circuit will compare the transmitted and the received data stream at a point in time and ﬂag any mismatch. The timing checks run when transmitter is active (not idle). As soon as a mismatch between the transmitted data and the received data is detected the following happens:

The next bit transmitted will have a high level (TXPOL = 0) or low level (TXPOL = 1)
The transmission is aborted and the byte in transmit buffer is discarded.
the transmit data register empty and the transmission complete ﬂag will be set
The bit error interrupt ﬂag, BERRIF, will be set.
No further transmissions will take place until the BERRIF is cleared. Figure 18-19. Timing Diagram Bit Error Detection If the bit error detect feature is disabled, the bit error interrupt ﬂag is cleared. NOTE The RXPOL and TXPOL bit should be set the same when transmission collision detect feature is enabled, otherwise the bit error interrupt ﬂag may be set incorrectly. TXD Pin RXD Pin LIN Physical InterfaceSynchronizer Stage Bus Clock Receive Shift Register Transmit Shift Register LIN Bus Compare Sample Bit Error Point Output Transmit Shift Register 0123456789 1 0 1 1 1 2 1 3 1 4 1 5 0 Input Receive Shift Register BERRM[1:0] = 0:1 BERRM[1:0] = 1:1 Compare Sample Points Sampling Begin Sampling Begin Sampling End Sampling End

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18.4.6 Receiver

Figure 18-20. SCI Receiver Block Diagram

18.4.6.1 Receiver Character Length

The SCI receiver can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI control register 1 (SCICR1) determines the length of data characters. When receiving 9-bit data, bit R8 in SCI data register high (SCIDRH) is the ninth bit (bit 8).

18.4.6.2 Character Reception

During an SCI reception, the receive shift register shifts a frame in from the RXD pin. The SCI data register is the read-only buffer between the internal data bus and the receive shift register. After a complete frame shifts into the receive shift register, the data portion of the frame transfers to the SCI data register. The receive data register full ﬂag, RDRF, in SCI status register 1 (SCISR1) becomes set, All 1s M WAKE ILT PE PT RE H876543210L 11-Bit Receive Shift Register Stop Start Data Wakeup Parity Checking MSB SCI Data Register ILIE RWU RDRF OR NF FE PE Internal Bus Bus SBR12:SBR0 Baud DividerClock IDLE RAF Recovery Logic RXPOL LOOPS Loop RSRC Control SCRXD From TXD Pin or Transmitter Idle IRQ RDRF/OR IRQ Break Detect Logic Active Edge Detect Logic BRKDFE BRKDIE BRKDIF RXEDGIE RXEDGIF Break IRQ RX Active Edge IRQ RIE

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indicating that the received byte can be read. If the receive interrupt enable bit, RIE, in SCI control register 2 (SCICR2) is also set, the RDRF ﬂag generates an RDRF interrupt request.

18.4.6.3 Data Sampling

The RT clock rate. The RT clock is an internal signal with a frequency 16 times the baud rate. To adjust for baud rate mismatch, the RT clock (see Figure 18-21) is re-synchronized:

After every start bit
After the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit samples at RT8, RT9, and RT10 returns a valid logic 1 and the majority of the next RT8, RT9, and RT10 samples returns a valid logic 0) To locate the start bit, data recovery logic does an asynchronous search for a logic 0 preceded by three logic 1s.When the falling edge of a possible start bit occurs, the RT clock begins to count to 16. Figure 18-21. Receiver Data Sampling To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7. Figure 18-17 summarizes the results of the start bit veriﬁcation samples. If start bit veriﬁcation is not successful, the RT clock is reset and a new search for a start bit begins. Table 18-17. Start Bit Veriﬁcation RT3, RT5, and RT7 Samples Start Bit Veriﬁcation Noise Flag

000 Y es 0

001 Y es 1

010 Y es 1

011 No 0

100 Y es 1

101 No 0

110 No 0

111 No 0

Qualiﬁcation Start Bit Data Sampling 11 111111 0 0 0 0 000 LSB Veriﬁcation

Serial Communication Interface (S12SCIV5) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 587 To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 18-18 summarizes the results of the data bit samples. NOTE The RT8, RT9, and RT10 samples do not affect start bit veriﬁcation. If any or all of the RT8, RT9, and RT10 start bit samples are logic 1s following a successful start bit veriﬁcation, the noise ﬂag (NF) is set and the receiver assumes that the bit is a start bit (logic 0). To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10.Table 18-19 summarizes the results of the stop bit samples. In Figure 18-22 the veriﬁcation samples RT3 and RT5 determine that the ﬁrst low detected was noise and not the beginning of a start bit. The RT clock is reset and the start bit search begins again. The noise ﬂag is not set because the noise occurred before the start bit was found. Table 18-18. Data Bit Recovery RT8, RT9, and RT10 Samples Data Bit Determination Noise Flag 000 0 0 001 0 1 010 0 1 011 1 1 100 0 1 101 1 1 110 1 1 111 1 0 Table 18-19. Stop Bit Recovery RT8, RT9, and RT10 Samples Framing Error Flag Noise Flag 000 1 0 001 1 1 010 1 1 011 0 1 100 1 1 101 0 1 110 0 1 111 0 0

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Figure 18-22. Start Bit Search Example 1 In Figure 18-23, veriﬁcation sample at RT3 is high. The RT3 sample sets the noise ﬂag. Although the perceived bit time is misaligned, the data samples RT8, RT9, and RT10 are within the bit time and data recovery is successful. Figure 18-23. Start Bit Search Example 2 In Figure 18-24, a large burst of noise is perceived as the beginning of a start bit, although the test sample at RT5 is high. The RT5 sample sets the noise ﬂag. Although this is a worst-case misalignment of perceived bit time, the data samples RT8, RT9, and RT10 are within the bit time and data recovery is successful. Reset RT Clock RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT1 RT1 RT2 RT3 RT4 RT7 RT6 RT5 RT10 RT9 RT8 RT14 RT13 RT12 RT11 RT15 RT16 RT1 RT2 RT3 Samples RT Clock RT Clock Count Start Bit RXD 11 0111 1 0 0 0 00 LSB 0 0 Reset RT Clock RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT11 RT10 RT9 RT14 RT13 RT12 RT2 RT1 RT16 RT15 RT3 RT4 RT5 RT6 RT7 Samples RT Clock RT Clock Count Actual Start Bit RXD 11 1111 0 0 0 0 LSB Perceived Start Bit

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Figure 18-26. Start Bit Search Example 5 In Figure 18-27, a noise burst makes the majority of data samples RT8, RT9, and RT10 high. This sets the noise ﬂag but does not reset the RT clock. In start bits only, the RT8, RT9, and RT10 data samples are ignored. Figure 18-27. Start Bit Search Example 6

18.4.6.4 Framing Errors

If the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming frame, it sets the framing error ﬂag, FE, in SCI status register 1 (SCISR1). A break character also sets the FE ﬂag because a break character has no stop bit. The FE ﬂag is set at the same time that the RDRF ﬂag is set.

18.4.6.5 Baud Rate Tolerance

A transmitting device may be operating at a baud rate below or above the receiver baud rate. Accumulated bit time misalignment can cause one of the three stop bit data samples (RT8, RT9, and RT10) to fall outside the actual stop bit. A noise error will occur if the RT8, RT9, and RT10 samples are not all the same logical values. A framing error will occur if the receiver clock is misaligned in such a way that the majority of the RT8, RT9, and RT10 stop bit samples are a logic zero. Reset RT Clock RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT7 RT6 RT5 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 Samples RT Clock RT Clock Count Start Bit RXD 11 111 0 1 0 LSB 11 1 1 1 00 000 00 0 No Start Bit Found Reset RT Clock RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT7 RT6 RT5 RT10 RT9 RT8 RT14 RT13 RT12 RT11 RT15 RT16 RT1 RT2 RT3 Samples RT Clock RT Clock Count Start Bit RXD 11 111 0 0 0 LSB 11 1 1 0 11 0

Serial Communication Interface (S12SCIV5) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 591 As the receiver samples an incoming frame, it re-synchronizes the RT clock on any valid falling edge within the frame. Re synchronization within frames will correct a misalignment between transmitter bit times and receiver bit times.

18.4.6.5.1 Slow Data Tolerance

Figure 18-28 shows how much a slow received frame can be misaligned without causing a noise error or a framing error. The slow stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit data samples at RT8, RT9, and RT10. Figure 18-28. Slow Data Let’s take RTr as receiver RT clock and RTt as transmitter RT clock. For an 8-bit data character, it takes the receiver 9 bit times x 16 RTr cycles +7 RTr cycles = 151 RTr cycles to start data sampling of the stop bit. With the misaligned character shown inFigure 18-28, the receiver counts 151 RTr cycles at the point when the count of the transmitting device is 9 bit times x 16 RTt cycles = 144 RTt cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 8-bit data character with no errors is: For a 9-bit data character, it takes the receiver 10 bit times x 16 RTr cycles + 7 RTr cycles = 167 RTr cycles to start data sampling of the stop bit. With the misaligned character shown inFigure 18-28, the receiver counts 167 RTr cycles at the point when the count of the transmitting device is 10 bit times x 16 RTt cycles = 160 RTt cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is:

18.4.6.5.2 Fast Data Tolerance

Figure 18-29 shows how much a fast received frame can be misaligned. The fast stop bit ends at RT10 instead of RT16 but is still sampled at RT8, RT9, and RT10. MSB Stop RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT10 RT11 RT12 RT13 RT14 RT15 RT16 Data Samples Receiver RT Clock

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Figure 18-29. Fast Data For an 8-bit data character, it takes the receiver 9 bit times x 16 RTr cycles + 10 RTr cycles = 154 RTr cycles to ﬁnish data sampling of the stop bit. With the misaligned character shown inFigure 18-29, the receiver counts 154 RTr cycles at the point when the count of the transmitting device is 10 bit times x 16 RTt cycles = 160 RTt cycles. The maximum percent difference between the receiver count and the transmitter count of a fast 8-bit character with no errors is: For a 9-bit data character, it takes the receiver 10 bit times x 16 RTr cycles + 10 RTr cycles = 170 RTr cycles to ﬁnish data sampling of the stop bit. With the misaligned character shown inFigure 18-29, the receiver counts 170 RTr cycles at the point when the count of the transmitting device is 11 bit times x 16 RTt cycles = 176 RTt cycles. The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit character with no errors is:

18.4.6.6 Receiver Wakeup

To enable the SCI to ignore transmissions intended only for other receivers in multiple-receiver systems, the receiver can be put into a standby state. Setting the receiver wakeup bit, RWU, in SCI control register 2 (SCICR2) puts the receiver into standby state during which receiver interrupts are disabled.The SCI will still load the receive data into the SCIDRH/L registers, but it will not set the RDRF ﬂag. The transmitting device can address messages to selected receivers by including addressing information in the initial frame or frames of each message. The W AKE bit in SCI control register 1 (SCICR1) determines how the SCI is brought out of the standby state to process an incoming message. The W AKE bit enables either idle line wakeup or address mark wakeup.

18.4.6.6.1 Idle Input line Wakeup (WAKE = 0)

In this wakeup method, an idle condition on the RXD pin clears the RWU bit and wakes up the SCI. The initial frame or frames of every message contain addressing information. All receivers evaluate the addressing information, and receivers for which the message is addressed process the frames that follow. Any receiver for which a message is not addressed can set its RWU bit and return to the standby state. The Idle or Next FrameStop RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT10 RT11 RT12 RT13 RT14 RT15 RT16 Data Samples Receiver RT Clock

Serial Communication Interface (S12SCIV5) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 593 RWU bit remains set and the receiver remains on standby until another idle character appears on the RXD pin. Idle line wakeup requires that messages be separated by at least one idle character and that no message contains idle characters. The idle character that wakes a receiver does not set the receiver idle bit, IDLE, or the receive data register full ﬂag, RDRF. The idle line type bit, ILT, determines whether the receiver begins counting logic 1s as idle character bits after the start bit or after the stop bit. ILT is in SCI control register 1 (SCICR1).

18.4.6.6.2 Address Mark Wakeup (WAKE = 1)

In this wakeup method, a logic 1 in the most signiﬁcant bit (MSB) position of a frame clears the RWU bit and wakes up the SCI. The logic 1 in the MSB position marks a frame as an address frame that contains addressing information. All receivers evaluate the addressing information, and the receivers for which the message is addressed process the frames that follow.Any receiver for which a message is not addressed can set its RWU bit and return to the standby state. The RWU bit remains set and the receiver remains on standby until another address frame appears on the RXD pin. The logic 1 MSB of an address frame clears the receiver’s RWU bit before the stop bit is received and sets the RDRF ﬂag. Address mark wakeup allows messages to contain idle characters but requires that the MSB be reserved for use in address frames. NOTE With the W AKE bit clear, setting the RWU bit after the RXD pin has been idle can cause the receiver to wake up immediately.

18.4.7 Single-Wire Operation

Normally, the SCI uses two pins for transmitting and receiving. In single-wire operation, the RXD pin is disconnected from the SCI. The SCI uses the TXD pin for both receiving and transmitting. Figure 18-30. Single-Wire Operation (LOOPS = 1, RSRC = 1) Enable single-wire operation by setting the LOOPS bit and the receiver source bit, RSRC, in SCI control register 1 (SCICR1). Setting the LOOPS bit disables the path from the RXD pin to the receiver. Setting the RSRC bit connects the TXD pin to the receiver. Both the transmitter and receiver must be enabled (TE = 1 and RE = 1).The TXDIR bit (SCISR2[1]) determines whether the TXD pin is going to be used as an input (TXDIR = 0) or an output (TXDIR = 1) in this mode of operation. RXD Transmitter Receiver TXD

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In single-wire operation data from the TXD pin is inverted if RXPOL is set.

18.4.8 Loop Operation

In loop operation the transmitter output goes to the receiver input. The RXD pin is disconnected from the SCI. Figure 18-31. Loop Operation (LOOPS = 1, RSRC = 0) Enable loop operation by setting the LOOPS bit and clearing the RSRC bit in SCI control register 1 (SCICR1). Setting the LOOPS bit disables the path from the RXD pin to the receiver. Clearing the RSRC bit connects the transmitter output to the receiver input. Both the transmitter and receiver must be enabled (TE = 1 and RE = 1). NOTE In loop operation data from the transmitter is not recognized by the receiver if RXPOL and TXPOL are not the same.

18.5 Initialization/Application Information

18.5.1 Reset Initialization

See Section 18.3.2, “Register Descriptions”.

18.5.2 Modes of Operation

18.5.2.1 Run Mode

Normal mode of operation. To initialize a SCI transmission, see Section 18.4.5.2, “Character Transmission”.

18.5.2.2 Wait Mode

SCI operation in wait mode depends on the state of the SCISW AI bit in the SCI control register 1 (SCICR1).

If SCISW AI is clear, the SCI operates normally when the CPU is in wait mode.
If SCISW AI is set, SCI clock generation ceases and the SCI module enters a power-conservation state when the CPU is in wait mode. Setting SCISW AI does not affect the state of the receiver enable bit, RE, or the transmitter enable bit, TE. RXD Transmitter Receiver TXD

Serial Communication Interface (S12SCIV5) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 595 If SCISW AI is set, any transmission or reception in progress stops at wait mode entry. The transmission or reception resumes when either an internal or external interrupt brings the CPU out of wait mode. Exiting wait mode by reset aborts any transmission or reception in progress and resets the SCI.

18.5.2.3 Stop Mode

The SCI is inactive during stop mode for reduced power consumption. The STOP instruction does not affect the SCI register states, but the SCI bus clock will be disabled. The SCI operation resumes from where it left off after an external interrupt brings the CPU out of stop mode. Exiting stop mode by reset aborts any transmission or reception in progress and resets the SCI. The receive input active edge detect circuit is still active in stop mode. An active edge on the receive input can be used to bring the CPU out of stop mode.

18.5.3 Interrupt Operation

This section describes the interrupt originated by the SCI block.The MCU must service the interrupt requests. Table 18-20 lists the eight interrupt sources of the SCI.

18.5.3.1 Description of Interrupt Operation

The SCI only originates interrupt requests. The following is a description of how the SCI makes a request and how the MCU should acknowledge that request. The interrupt vector offset and interrupt number are chip dependent. The SCI only has a single interrupt line (SCI Interrupt Signal, active high operation) and all the following interrupts, when generated, are ORed together and issued through that port.

18.5.3.1.1 TDRE Description

The TDRE interrupt is set high by the SCI when the transmit shift register receives a byte from the SCI data register. A TDRE interrupt indicates that the transmit data register (SCIDRH/L) is empty and that a Table 18-20. SCI Interrupt Sources Interrupt Source Local Enable Description TDRE SCISR1[7] TIE Active high level. Indicates that a byte was transferred from SCIDRH/L to the transmit shift register. TC SCISR1[6] TCIE Active high level. Indicates that a transmit is complete. RDRF SCISR1[5] RIE Active high level. The RDRF interrupt indicates that received data is available in the SCI data register. OR SCISR1[3] Active high level. This interrupt indicates that an overrun condition has occurred. IDLE SCISR1[4] ILIE Active high level. Indicates that receiver input has become idle. RXEDGIF SCIASR1[7] RXEDGIE Active high level. Indicates that an active edge (falling for RXPOL = 0, rising for RXPOL = 1) was detected. BERRIF SCIASR1[1] BERRIE Active high level. Indicates that a mismatch between transmitted and received data in a single wire application has happened. BKDIF SCIASR1[0] BRKDIE Active high level. Indicates that a break character has been received.

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new byte can be written to the SCIDRH/L for transmission.Clear TDRE by reading SCI status register 1 with TDRE set and then writing to SCI data register low (SCIDRL).

18.5.3.1.2 TC Description

The TC interrupt is set by the SCI when a transmission has been completed. Transmission is completed when all bits including the stop bit (if transmitted) have been shifted out and no data is queued to be transmitted. No stop bit is transmitted when sending a break character and the TC ﬂag is set (providing there is no more data queued for transmission) when the break character has been shifted out. A TC interrupt indicates that there is no transmission in progress. TC is set high when the TDRE ﬂag is set and no data, preamble, or break character is being transmitted. When TC is set, the TXD pin becomes idle (logic 1). Clear TC by reading SCI status register 1 (SCISR1) with TC set and then writing to SCI data register low (SCIDRL).TC is cleared automatically when data, preamble, or break is queued and ready to be sent.

18.5.3.1.3 RDRF Description

The RDRF interrupt is set when the data in the receive shift register transfers to the SCI data register. A RDRF interrupt indicates that the received data has been transferred to the SCI data register and that the byte can now be read by the MCU. The RDRF interrupt is cleared by reading the SCI status register one (SCISR1) and then reading SCI data register low (SCIDRL).

18.5.3.1.4 OR Description

The OR interrupt is set when software fails to read the SCI data register before the receive shift register receives the next frame. The newly acquired data in the shift register will be lost in this case, but the data already in the SCI data registers is not affected. The OR interrupt is cleared by reading the SCI status register one (SCISR1) and then reading SCI data register low (SCIDRL).

18.5.3.1.5 IDLE Description

The IDLE interrupt is set when 10 consecutive logic 1s (if M = 0) or 11 consecutive logic 1s (if M = 1) appear on the receiver input. Once the IDLE is cleared, a valid frame must again set the RDRF ﬂag before an idle condition can set the IDLE ﬂag. Clear IDLE by reading SCI status register 1 (SCISR1) with IDLE set and then reading SCI data register low (SCIDRL).

18.5.3.1.6 RXEDGIF Description

The RXEDGIF interrupt is set when an active edge (falling if RXPOL = 0, rising if RXPOL = 1) on the RXD pin is detected. Clear RXEDGIF by writing a “1” to the SCIASR1 SCI alternative status register 1.

18.5.3.1.7 BERRIF Description

The BERRIF interrupt is set when a mismatch between the transmitted and the received data in a single wire application like LIN was detected. Clear BERRIF by writing a “1” to the SCIASR1 SCI alternative status register 1. This ﬂag is also cleared if the bit error detect feature is disabled.

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18.5.3.1.8 BKDIF Description

The BKDIF interrupt is set when a break signal was received. Clear BKDIF by writing a “1” to the SCIASR1 SCI alternative status register 1. This ﬂag is also cleared if break detect feature is disabled.

18.5.4 Recovery from Wait Mode

The SCI interrupt request can be used to bring the CPU out of wait mode.

18.5.5 Recovery from Stop Mode

An active edge on the receive input can be used to bring the CPU out of stop mode.

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MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 599 Chapter 19 Serial Peripheral Interface (S12SPIV5)

19.1 Introduction

The SPI module allows a duplex, synchronous, serial communication between the MCU and peripheral devices. Software can poll the SPI status ﬂags or the SPI operation can be interrupt driven.

19.1.1 Glossary of Terms

19.1.2 Features

The SPI includes these distinctive features:

Master mode and slave mode
Selectable 8 or 16-bit transfer width
Bidirectional mode
Slave select output
Mode fault error ﬂag with CPU interrupt capability Revision Number Date Author Summary of Changes 05.00 24 MAR 2005 Added 16-bit transfer width feature. SPI Serial Peripheral Interface SS Slave Select SCK Serial Clock MOSI Master Output, Slave Input MISO Master Input, Slave Output MOMI Master Output, Master Input SISO Slave Input, Slave Output

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Double-buffered data register
Serial clock with programmable polarity and phase
Control of SPI operation during wait mode

19.1.3 Modes of Operation

The SPI functions in three modes: run, wait, and stop.

Run mode This is the basic mode of operation.
Wait mode SPI operation in wait mode is a conﬁgurable low power mode, controlled by the SPISW AI bit located in the SPICR2 register. In wait mode, if the SPISW AI bit is clear, the SPI operates like in run mode. If the SPISW AI bit is set, the SPI goes into a power conservative state, with the SPI clock generation turned off. If the SPI is conﬁgured as a master, any transmission in progress stops, but is resumed after CPU goes into run mode. If the SPI is conﬁgured as a slave, reception and transmission of data continues, so that the slave stays synchronized to the master.
Stop mode The SPI is inactive in stop mode for reduced power consumption. If the SPI is conﬁgured as a master, any transmission in progress stops, but is resumed after CPU goes into run mode. If the SPI is conﬁgured as a slave, reception and transmission of data continues, so that the slave stays synchronized to the master. For a detailed description of operating modes, please refer toSection 19.4.7, “Low Power Mode Options”.

19.1.4 Block Diagram

Figure 19-1 gives an overview on the SPI architecture. The main parts of the SPI are status, control and data registers, shifter logic, baud rate generator, master/slave control logic, and port control logic.

Serial Peripheral Interface (S12SPIV5) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 601 Figure 19-1. SPI Block Diagram

19.2 External Signal Description

This section lists the name and description of all ports including inputs and outputs that do, or may, connect off chip. The SPI module has a total of four external pins.

19.2.1 MOSI — Master Out/Slave In Pin

This pin is used to transmit data out of the SPI module when it is conﬁgured as a master and receive data when it is conﬁgured as slave. SPI Control Register 1 SPI Control Register 2 SPI Baud Rate Register SPI Status Register SPI Data Register Shifter Port Control Logic MOSI SCK Interrupt Control SPI MSB LSB LSBFE=1 LSBFE=0 LSBFE=0 LSBFE=1 Data In LSBFE=1 LSBFE=0 Data Out Baud Rate Generator PrescalerBus Clock Counter Clock Select SPPR 3 3SPR Baud Rate Phase + Polarity Control Master Slave SCK In SCK OutMaster Baud Rate Slave Baud Rate Phase + Polarity Control Control Control CPOL CPHA BIDIROE SPC0 Shift Sample ClockClock MODFSPIF SPTEF SPI Request Interrupt SS

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19.2.2 MISO — Master In/Slave Out Pin

This pin is used to transmit data out of the SPI module when it is conﬁgured as a slave and receive data when it is conﬁgured as master.

19.2.3 SS — Slave Select Pin

This pin is used to output the select signal from the SPI module to another peripheral with which a data transfer is to take place when it is conﬁgured as a master and it is used as an input to receive the slave select signal when the SPI is conﬁgured as slave.

19.2.4 SCK — Serial Clock Pin

In master mode, this is the synchronous output clock. In slave mode, this is the synchronous input clock.

19.3 Memory Map and Register Deﬁnition

This section provides a detailed description of address space and registers used by the SPI.

19.3.1 Module Memory Map

The memory map for the SPI is given in Figure 19-2. The address listed for each register is the sum of a base address and an address offset. The base address is deﬁned at the SoC level and the address offset is deﬁned at the module level. Reads from the reserved bits return zeros and writes to the reserved bits have no effect. Register Name Bit 7 6 5 4 3 2 1 Bit 0 SPICR1 R SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFEW SPICR2 R 0 XFRW 0 MODFEN BIDIROE 0 SPISWAI SPC0W SPIBR R 0 SPPR2 SPPR1 SPPR0 0 SPR2 SPR1 SPR0W SPISR R SPIF 0 SPTEF MODF 0 0 0 0 W SPIDRH R R15 R14 R13 R12 R11 R10 R9 R8 T15 T14 T13 T12 T11 T10 T9 T8W = Unimplemented or Reserved Figure 19-2. SPI Register Summary

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19.3.2 Register Descriptions

19.3.2.1 SPI Control Register 1 (SPICR1)

Read: Anytime Write: Anytime SPIDRL R R7 R6 R5 R4 R3 R2 R1 R0 T7 T6 T5 T4 T3 T2 T1 T0W Reserved R W Reserved R W 76543210 R SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE W Reset 0 0 0 00100 Figure 19-3. SPI Control Register 1 (SPICR1) Table 19-1. SPICR1 Field Descriptions Field Description SPIE SPI Interrupt Enable Bit — This bit enables SPI interrupt requests, if SPIF or MODF status ﬂag is set. 0 SPI interrupts disabled. 1 SPI interrupts enabled. SPE SPI System Enable Bit — This bit enables the SPI system and dedicates the SPI port pins to SPI system functions. If SPE is cleared, SPI is disabled and forced into idle state, status bits in SPISR register are reset. 0 SPI disabled (lower power consumption). 1 SPI enabled, port pins are dedicated to SPI functions. SPTIE SPI Transmit Interrupt Enable — This bit enables SPI interrupt requests, if SPTEF ﬂag is set. 0 SPTEF interrupt disabled. 1 SPTEF interrupt enabled. MSTR SPI Master/Slave Mode Select Bit — This bit selects whether the SPI operates in master or slave mode. Switching the SPI from master to slave or vice versa forces the SPI system into idle state. 0 SPI is in slave mode. 1 SPI is in master mode. Register Name Bit 7 6 5 4 3 2 1 Bit 0 = Unimplemented or Reserved Figure 19-2. SPI Register Summary

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19.3.2.2 SPI Control Register 2 (SPICR2)

Read: Anytime Write: Anytime; writes to the reserved bits have no effect CPOL SPI Clock Polarity Bit — This bit selects an inverted or non-inverted SPI clock. To transmit data between SPI modules, the SPI modules must have identical CPOL values. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. 0 Active-high clocks selected. In idle state SCK is low. 1 Active-low clocks selected. In idle state SCK is high. CPHA SPI Clock Phase Bit — This bit is used to select the SPI clock format. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. 0 Sampling of data occurs at odd edges (1,3,5,...) of the SCK clock. 1 Sampling of data occurs at even edges (2,4,6,...) of the SCK clock. SSOE Slave Select Output Enable — The SS output feature is enabled only in master mode, if MODFEN is set, by asserting the SSOE as shown in Table 19-2. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. LSBFE LSB-First Enable — This bit does not affect the position of the MSB and LSB in the data register. Reads and writes of the data register always have the MSB in the highest bit position. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. 0 Data is transferred most signiﬁcant bit ﬁrst. 1 Data is transferred least signiﬁcant bit ﬁrst. Table 19-2. SS Input / Output Selection MODFEN SSOE Master Mode Slave Mode

00 SS not used by SPI SS input

01 SS not used by SPI SS input

10 SS input with MODF feature SS input

11 SS is slave select output SS input

W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 19-4. SPI Control Register 2 (SPICR2) Table 19-1. SPICR1 Field Descriptions Field Description

Serial Peripheral Interface (S12SPIV5) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 605 Table 19-3. SPICR2 Field Descriptions Field Description XFRW Transfer Width — This bit is used for selecting the data transfer width. If 8-bit transfer width is selected, SPIDRL becomes the dedicated data register and SPIDRH is unused. If 16-bit transfer width is selected, SPIDRH and SPIDRL form a 16-bit data register. Please refer to Section 19.3.2.4, “SPI Status Register (SPISR) for information about transmit/receive data handling and the interrupt ﬂag clearing mechanism. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. 0 8-bit Transfer Width (n = 8) 1 16-bit Transfer Width (n = 16)1 1 n is used later in this document as a placeholder for the selected transfer width. MODFEN Mode Fault Enable Bit — This bit allows the MODF failure to be detected. If the SPI is in master mode and MODFEN is cleared, then the SS port pin is not used by the SPI. In slave mode, the SS is available only as an input regardless of the value of MODFEN. For an overview on the impact of the MODFEN bit on theSS port pin conﬁguration, refer to Table 19-2. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. SS port pin is not used by the SPI. 1 SS port pin with MODF feature. BIDIROE Output Enable in the Bidirectional Mode of Operation— This bit controls the MOSI and MISO output buffer of the SPI, when in bidirectional mode of operation (SPC0 is set). In master mode, this bit controls the output buffer of the MOSI port, in slave mode it controls the output buffer of the MISO port. In master mode, with SPC0 set, a change of this bit will abort a transmission in progress and force the SPI into idle state. 0 Output buffer disabled. 1 Output buffer enabled. SPISWAI SPI Stop in Wait Mode Bit — This bit is used for power conservation while in wait mode. 0 SPI clock operates normally in wait mode. 1 Stop SPI clock generation when in wait mode. SPC0 Serial Pin Control Bit 0 — This bit enables bidirectional pin conﬁgurations as shown in Table 19-4. In master mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state. Table 19-4. Bidirectional Pin Conﬁgurations Pin Mode SPC0 BIDIROE MISO MOSI Master Mode of Operation Normal 0 X Master In Master Out Bidirectional 1 0 MISO not used by SPI Master In

1 Master I/O

Normal 0 X Slave Out Slave In Bidirectional 1 0 Slave In MOSI not used by SPI

1 Slave I/O

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19.3.2.3 SPI Baud Rate Register (SPIBR)

Read: Anytime Write: Anytime; writes to the reserved bits have no effect The baud rate divisor equation is as follows: BaudRateDivisor = (SPPR + 1) • 2(SPR + 1) Eqn. 19-1 The baud rate can be calculated with the following equation: Baud Rate = BusClock / BaudRateDivisor Eqn. 19-2 NOTE For maximum allowed baud rates, please refer to the SPI Electrical Speciﬁcation in the Electricals chapter of this data sheet. 76543210 SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 W Reset 0 0 0 00000 = Unimplemented or Reserved Figure 19-5. SPI Baud Rate Register (SPIBR) Table 19-5. SPIBR Field Descriptions Field Description 6–4 SPPR[2:0] SPI Baud Rate Preselection Bits — These bits specify the SPI baud rates as shown in Table 19-6. In master mode, a change of these bits will abort a transmission in progress and force the SPI system into idle state. 2–0 SPR[2:0] SPI Baud Rate Selection Bits— These bits specify the SPI baud rates as shown inTable 19-6. In master mode, a change of these bits will abort a transmission in progress and force the SPI system into idle state. Table 19-6. Example SPI Baud Rate Selection (25 MHz Bus Clock) SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 Baud Rate Divisor Baud Rate 0 0 0 0 0 0 2 12.5 Mbit/s 0 0 0 0 0 1 4 6.25 Mbit/s 0 0 0 0 1 0 8 3.125 Mbit/s 0 0 0 0 1 1 16 1.5625 Mbit/s 0 0 0 1 0 0 32 781.25 kbit/s 0 0 0 1 0 1 64 390.63 kbit/s 0 0 0 1 1 0 128 195.31 kbit/s 0 0 0 1 1 1 256 97.66 kbit/s 0 0 1 0 0 0 4 6.25 Mbit/s 0 0 1 0 0 1 8 3.125 Mbit/s 0 0 1 0 1 0 16 1.5625 Mbit/s

Serial Peripheral Interface (S12SPIV5) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 607 0 0 1 0 1 1 32 781.25 kbit/s 0 0 1 1 0 0 64 390.63 kbit/s 0 0 1 1 0 1 128 195.31 kbit/s 0 0 1 1 1 0 256 97.66 kbit/s 0 0 1 1 1 1 512 48.83 kbit/s 0 1 0 0 0 0 6 4.16667 Mbit/s 0 1 0 0 0 1 12 2.08333 Mbit/s 0 1 0 0 1 0 24 1.04167 Mbit/s 0 1 0 0 1 1 48 520.83 kbit/s 0 1 0 1 0 0 96 260.42 kbit/s 0 1 0 1 0 1 192 130.21 kbit/s 0 1 0 1 1 0 384 65.10 kbit/s 0 1 0 1 1 1 768 32.55 kbit/s 0 1 1 0 0 0 8 3.125 Mbit/s 0 1 1 0 0 1 16 1.5625 Mbit/s 0 1 1 0 1 0 32 781.25 kbit/s 0 1 1 0 1 1 64 390.63 kbit/s 0 1 1 1 0 0 128 195.31 kbit/s 0 1 1 1 0 1 256 97.66 kbit/s 0 1 1 1 1 0 512 48.83 kbit/s 0 1 1 1 1 1 1024 24.41 kbit/s 1 0 0 0 0 0 10 2.5 Mbit/s 1 0 0 0 0 1 20 1.25 Mbit/s 1 0 0 0 1 0 40 625 kbit/s 1 0 0 0 1 1 80 312.5 kbit/s 1 0 0 1 0 0 160 156.25 kbit/s 1 0 0 1 0 1 320 78.13 kbit/s 1 0 0 1 1 0 640 39.06 kbit/s 1 0 0 1 1 1 1280 19.53 kbit/s 1 0 1 0 0 0 12 2.08333 Mbit/s 1 0 1 0 0 1 24 1.04167 Mbit/s 1 0 1 0 1 0 48 520.83 kbit/s 1 0 1 0 1 1 96 260.42 kbit/s 1 0 1 1 0 0 192 130.21 kbit/s 1 0 1 1 0 1 384 65.10 kbit/s 1 0 1 1 1 0 768 32.55 kbit/s 1 0 1 1 1 1 1536 16.28 kbit/s 1 1 0 0 0 0 14 1.78571 Mbit/s 1 1 0 0 0 1 28 892.86 kbit/s Table 19-6. Example SPI Baud Rate Selection (25 MHz Bus Clock) SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 Baud Rate Divisor Baud Rate

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19.3.2.4 SPI Status Register (SPISR)

Read: Anytime Write: Has no effect 1 1 0 0 1 0 56 446.43 kbit/s 1 1 0 0 1 1 112 223.21 kbit/s 1 1 0 1 0 0 224 111.61 kbit/s 1 1 0 1 0 1 448 55.80 kbit/s 1 1 0 1 1 0 896 27.90 kbit/s 1 1 0 1 1 1 1792 13.95 kbit/s 1 1 1 0 0 0 16 1.5625 Mbit/s 1 1 1 0 0 1 32 781.25 kbit/s 1 1 1 0 1 0 64 390.63 kbit/s 1 1 1 0 1 1 128 195.31 kbit/s 1 1 1 1 0 0 256 97.66 kbit/s 1 1 1 1 0 1 512 48.83 kbit/s 1 1 1 1 1 0 1024 24.41 kbit/s 1 1 1 1 1 1 2048 12.21 kbit/s 76543210 R SPIF 0 SPTEF MODF 0000 W Reset 0 0 1 00000 = Unimplemented or Reserved Figure 19-6. SPI Status Register (SPISR) Table 19-7. SPISR Field Descriptions Field Description SPIF SPIF Interrupt Flag — This bit is set after received data has been transferred into the SPI data register. For information about clearing SPIF Flag, please refer to Table 19-8. 0 Transfer not yet complete. 1 New data copied to SPIDR. Table 19-6. Example SPI Baud Rate Selection (25 MHz Bus Clock) SPPR2 SPPR1 SPPR0 SPR2 SPR1 SPR0 Baud Rate Divisor Baud Rate

Serial Peripheral Interface (S12SPIV5) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 609 Table 19-8. SPIF Interrupt Flag Clearing Sequence Table 19-9. SPTEF Interrupt Flag Clearing Sequence SPTEF SPI Transmit Empty Interrupt Flag — If set, this bit indicates that the transmit data register is empty. For information about clearing this bit and placing data into the transmit data register, please refer to Table 19-9. 0 SPI data register not empty. 1 SPI data register empty. MODF Mode Fault Flag— This bit is set if the SS input becomes low while the SPI is conﬁgured as a master and mode fault detection is enabled, MODFEN bit of SPICR2 register is set. Refer to MODFEN bit description in Section 19.3.2.2, “SPI Control Register 2 (SPICR2)”. The ﬂag is cleared automatically by a read of the SPI status register (with MODF set) followed by a write to the SPI control register 1. 0 Mode fault has not occurred. 1 Mode fault has occurred. XFRW Bit SPIF Interrupt Flag Clearing Sequence

0 Read SPISR with SPIF == 1 then Read SPIDRL

1 Read SPISR with SPIF == 1

1 Data in SPIDRH is lost in this case. or Byte Read SPIDRH 2 2 SPIDRH can be read repeatedly without any effect on SPIF . SPIF Flag is cleared only by the read of SPIDRL after reading SPISR with SPIF == 1. Byte Read SPIDRL or Word Read (SPIDRH:SPIDRL) XFRW Bit SPTEF Interrupt Flag Clearing Sequence

0 Read SPISR with SPTEF == 1 then Write to SPIDRL 1

1 Any write to SPIDRH or SPIDRL with SPTEF == 0 is effectively ignored.

1 Read SPISR with SPTEF == 1

2 Data in SPIDRH is undeﬁned in this case. or Byte Write to SPIDRH 13 Byte Write to SPIDRL 1 or Word Write to (SPIDRH:SPIDRL) 1 Table 19-7. SPISR Field Descriptions Field Description

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19.3.2.5 SPI Data Register (SPIDR = SPIDRH:SPIDRL)

Read: Anytime; read data only valid when SPIF is set Write: Anytime The SPI data register is both the input and output register for SPI data. A write to this register allows data to be queued and transmitted. For an SPI conﬁgured as a master, queued data is transmitted immediately after the previous transmission has completed. The SPI transmitter empty ﬂag SPTEF in the SPISR register indicates when the SPI data register is ready to accept new data. Received data in the SPIDR is valid when SPIF is set. If SPIF is cleared and data has been received, the received data is transferred from the receive shift register to the SPIDR and SPIF is set. If SPIF is set and not serviced, and a second data value has been received, the second received data is kept as valid data in the receive shift register until the start of another transmission. The data in the SPIDR does not change. If SPIF is set and valid data is in the receive shift register, and SPIF is serviced before the start of a third transmission, the data in the receive shift register is transferred into the SPIDR and SPIF remains set (see Figure 19-9). If SPIF is set and valid data is in the receive shift register, and SPIF is serviced after the start of a third transmission, the data in the receive shift register has become invalid and is not transferred into the SPIDR (see Figure 19-10). 3 SPIDRH can be written repeatedly without any effect on SPTEF . SPTEF Flag is cleared only by writing to SPIDRL after reading SPISR with SPTEF == 1. 76543210 R R15 R14 R13 R12 R11 R10 R9 R8 W T15 T14 T13 T12 T11 T10 T9 T8 Reset 0 0 0 00000 Figure 19-7. SPI Data Register High (SPIDRH) 76543210 R R7 R6 R5 R4 R3 R2 R1 R0 W T7 T6 T5 T4 T3 T2 T1 T0 Reset 0 0 0 00000 Figure 19-8. SPI Data Register Low (SPIDRL)

Serial Peripheral Interface (S12SPIV5) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 611 Figure 19-9. Reception with SPIF serviced in Time Figure 19-10. Reception with SPIF serviced too late

19.4 Functional Description

The SPI module allows a duplex, synchronous, serial communication between the MCU and peripheral devices. Software can poll the SPI status ﬂags or SPI operation can be interrupt driven. The SPI system is enabled by setting the SPI enable (SPE) bit in SPI control register 1. While SPE is set, the four associated SPI port pins are dedicated to the SPI function as:

Slave select ( SS)
Serial clock (SCK)
Master out/slave in (MOSI)
Master in/slave out (MISO) Receive Shift Register SPIF SPI Data Register Data A Data B Data A Data A Received Data B Received Data C Data C SPIF Serviced Data C Received Data B = Unspeciﬁed = Reception in progress Receive Shift Register SPIF SPI Data Register Data A Data B Data A Data A Received Data B Received Data C Data C SPIF Serviced Data C Received Data B Lost = Unspeciﬁed = Reception in progress

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The main element of the SPI system is the SPI data register. The n-bit1 data register in the master and the n-bit1 data register in the slave are linked by the MOSI and MISO pins to form a distributed 2n-bit1 register. When a data transfer operation is performed, this 2n-bit1 register is serially shifted n1 bit positions by the S-clock from the master, so data is exchanged between the master and the slave. Data written to the master SPI data register becomes the output data for the slave, and data read from the master SPI data register after a transfer operation is the input data from the slave. A read of SPISR with SPTEF = 1 followed by a write to SPIDR puts data into the transmit data register. When a transfer is complete and SPIF is cleared, received data is moved into the receive data register. This data register acts as the SPI receive data register for reads and as the SPI transmit data register for writes. A common SPI data register address is shared for reading data from the read data buffer and for writing data to the transmit data register. The clock phase control bit (CPHA) and a clock polarity control bit (CPOL) in the SPI control register 1 (SPICR1) select one of four possible clock formats to be used by the SPI system. The CPOL bit simply selects a non-inverted or inverted clock. The CPHA bit is used to accommodate two fundamentally different protocols by sampling data on odd numbered SCK edges or on even numbered SCK edges (see Section 19.4.3, “Transmission Formats”). The SPI can be conﬁgured to operate as a master or as a slave. When the MSTR bit in SPI control register1 is set, master mode is selected, when the MSTR bit is clear, slave mode is selected. NOTE A change of CPOL or MSTR bit while there is a received byte pending in the receive shift register will destroy the received byte and must be avoided.

19.4.1 Master Mode

The SPI operates in master mode when the MSTR bit is set. Only a master SPI module can initiate transmissions. A transmission begins by writing to the master SPI data register. If the shift register is empty, data immediately transfers to the shift register. Data begins shifting out on the MOSI pin under the control of the serial clock.

Serial clock The SPR2, SPR1, and SPR0 baud rate selection bits, in conjunction with the SPPR2, SPPR1, and SPPR0 baud rate preselection bits in the SPI baud rate register, control the baud rate generator and determine the speed of the transmission. The SCK pin is the SPI clock output. Through the SCK pin, the baud rate generator of the master controls the shift register of the slave peripheral.
MOSI, MISO pin In master mode, the function of the serial data output pin (MOSI) and the serial data input pin (MISO) is determined by the SPC0 and BIDIROE control bits. SS pin If MODFEN and SSOE are set, the SS pin is conﬁgured as slave select output. The SS output becomes low during each transmission and is high when the SPI is in idle state. 1. n depends on the selected transfer width, please refer to Section 19.3.2.2, “SPI Control Register 2 (SPICR2)

Serial Peripheral Interface (S12SPIV5) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 613 If MODFEN is set and SSOE is cleared, theSS pin is conﬁgured as input for detecting mode fault error. If the SS input becomes low this indicates a mode fault error where another master tries to drive the MOSI and SCK lines. In this case, the SPI immediately switches to slave mode, by clearing the MSTR bit and also disables the slave output buffer MISO (or SISO in bidirectional mode). So the result is that all outputs are disabled and SCK, MOSI, and MISO are inputs. If a transmission is in progress when the mode fault occurs, the transmission is aborted and the SPI is forced into idle state. This mode fault error also sets the mode fault (MODF) ﬂag in the SPI status register (SPISR). If the SPI interrupt enable bit (SPIE) is set when the MODF ﬂag becomes set, then an SPI interrupt sequence is also requested. When a write to the SPI data register in the master occurs, there is a half SCK-cycle delay. After the delay, SCK is started within the master. The rest of the transfer operation differs slightly, depending on the clock format speciﬁed by the SPI clock phase bit, CPHA, in SPI control register 1 (see Section 19.4.3, “Transmission Formats”). NOTE A change of the bits CPOL, CPHA, SSOE, LSBFE, XFRW, MODFEN, SPC0, or BIDIROE with SPC0 set, SPPR2-SPPR0 and SPR2-SPR0 in master mode will abort a transmission in progress and force the SPI into idle state. The remote slave cannot detect this, therefore the master must ensure that the remote slave is returned to idle state.

19.4.2 Slave Mode

The SPI operates in slave mode when the MSTR bit in SPI control register 1 is clear.

Serial clock In slave mode, SCK is the SPI clock input from the master.
MISO, MOSI pin In slave mode, the function of the serial data output pin (MISO) and serial data input pin (MOSI) is determined by the SPC0 bit and BIDIROE bit in SPI control register 2.
SS pin The SS pin is the slave select input. Before a data transmission occurs, theSS pin of the slave SPI must be low. SS must remain low until the transmission is complete. If SS goes high, the SPI is forced into idle state. The SS input also controls the serial data output pin, if SS is high (not selected), the serial data output pin is high impedance, and, if SS is low, the ﬁrst bit in the SPI data register is driven out of the serial data output pin. Also, if the slave is not selected (SS is high), then the SCK input is ignored and no internal shifting of the SPI shift register occurs. Although the SPI is capable of duplex operation, some SPI peripherals are capable of only receiving SPI data in a slave mode. For these simpler devices, there is no serial data out pin.

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When peripherals with duplex capability are used, take care not to simultaneously enable two receivers whose serial outputs drive the same system slave’s serial data output line. As long as no more than one slave device drives the system slave’s serial data output line, it is possible for several slaves to receive the same transmission from a master, although the master would not receive return information from all of the receiving slaves. If the CPHA bit in SPI control register 1 is clear, odd numbered edges on the SCK input cause the data at the serial data input pin to be latched. Even numbered edges cause the value previously latched from the serial data input pin to shift into the LSB or MSB of the SPI shift register, depending on the LSBFE bit. If the CPHA bit is set, even numbered edges on the SCK input cause the data at the serial data input pin to be latched. Odd numbered edges cause the value previously latched from the serial data input pin to shift into the LSB or MSB of the SPI shift register, depending on the LSBFE bit. When CPHA is set, the ﬁrst edge is used to get the ﬁrst data bit onto the serial data output pin. When CPHA is clear and the SS input is low (slave selected), the ﬁrst bit of the SPI data is driven out of the serial data output pin. After the nth1 shift, the transfer is considered complete and the received data is transferred into the SPI data register. To indicate transfer is complete, the SPIF ﬂag in the SPI status register is set. NOTE A change of the bits CPOL, CPHA, SSOE, LSBFE, MODFEN, SPC0, or BIDIROE with SPC0 set in slave mode will corrupt a transmission in progress and must be avoided.

19.4.3 Transmission Formats

During an SPI transmission, data is transmitted (shifted out serially) and received (shifted in serially) simultaneously. The serial clock (SCK) synchronizes shifting and sampling of the information on the two serial data lines. A slave select line allows selection of an individual slave SPI device; slave devices that are not selected do not interfere with SPI bus activities. Optionally, on a master SPI device, the slave select line can be used to indicate multiple-master bus contention. Figure 19-11. Master/Slave Transfer Block Diagram 1. n depends on the selected transfer width, please refer to Section 19.3.2.2, “SPI Control Register 2 (SPICR2) SHIFT REGISTER SHIFT REGISTER BAUD RATE GENERATOR MASTER SPI SLAVE SPI MOSI MOSI MISO MISO SCK SCK SS SSVDD

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19.4.3.1 Clock Phase and Polarity Controls

Using two bits in the SPI control register 1, software selects one of four combinations of serial clock phase and polarity. The CPOL clock polarity control bit speciﬁes an active high or low clock and has no signiﬁcant effect on the transmission format. The CPHA clock phase control bit selects one of two fundamentally different transmission formats. Clock phase and polarity should be identical for the master SPI device and the communicating slave device. In some cases, the phase and polarity are changed between transmissions to allow a master device to communicate with peripheral slaves having different requirements.

19.4.3.2 CPHA = 0 Transfer Format

The ﬁrst edge on the SCK line is used to clock the ﬁrst data bit of the slave into the master and the ﬁrst data bit of the master into the slave. In some peripherals, the ﬁrst bit of the slave’s data is available at the slave’s data out pin as soon as the slave is selected. In this format, the ﬁrst SCK edge is issued a half cycle after SS has become low. A half SCK cycle later, the second edge appears on the SCK line. When this second edge occurs, the value previously latched from the serial data input pin is shifted into the LSB or MSB of the shift register, depending on LSBFE bit. After this second edge, the next bit of the SPI master data is transmitted out of the serial data output pin of the master to the serial input pin on the slave. This process continues for a total of 16 edges on the SCK line, with data being latched on odd numbered edges and shifted on even numbered edges. Data reception is double buffered. Data is shifted serially into the SPI shift register during the transfer and is transferred to the parallel SPI data register after the last bit is shifted in. After 2n 1 (last) SCK edges:

Data that was previously in the master SPI data register should now be in the slave data register and the data that was in the slave data register should be in the master.
The SPIF ﬂag in the SPI status register is set, indicating that the transfer is complete. Figure 19-12 is a timing diagram of an SPI transfer where CPHA = 0. SCK waveforms are shown for CPOL = 0 and CPOL = 1. The diagram may be interpreted as a master or slave timing diagram because the SCK, MISO, and MOSI pins are connected directly between the master and the slave. The MISO signal is the output from the slave and the MOSI signal is the output from the master. The SS pin of the master must be either high or reconﬁgured as a general-purpose output not affecting the SPI. 1. n depends on the selected transfer width, please refer to Section 19.3.2.2, “SPI Control Register 2 (SPICR2)

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Figure 19-12. SPI Clock Format 0 (CPHA = 0), with 8-bit Transfer Width selected (XFRW = 0) tL Begin End SCK (CPOL = 0) SAMPLE I CHANGE O SEL SS (O) Transfer SCK (CPOL = 1) MSB ﬁrst (LSBFE = 0): LSB ﬁrst (LSBFE = 1): MSB LSB LSB MSB Bit 5 Bit 2 Bit 6 Bit 1 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 CHANGE O SEL SS (I) MOSI pin MISO pin Master only MOSI/MISO tT If next transfer begins here for tT, tl, tL Minimum 1/2 SCK tI tL tL = Minimum leading time before the ﬁrst SCK edge tT = Minimum trailing time after the last SCK edge tI = Minimum idling time between transfers (minimum SS high time) tL, tT, and tI are guaranteed for the master mode and required for the slave mode. 1 234 56 789 1 0 1 1 1 2 1 3 1 4 1 5 1 6SCK Edge Number End of Idle State Begin of Idle State

Serial Peripheral Interface (S12SPIV5) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 617 Figure 19-13. SPI Clock Format 0 (CPHA = 0), with 16-Bit Transfer Width selected (XFRW = 1) In slave mode, if theSS line is not deasserted between the successive transmissions then the content of the SPI data register is not transmitted; instead the last received data is transmitted. If theSS line is deasserted for at least minimum idle time (half SCK cycle) between successive transmissions, then the content of the SPI data register is transmitted. In master mode, with slave select output enabled the SS line is always deasserted and reasserted between successive transfers for at least minimum idle time.

19.4.3.3 CPHA = 1 Transfer Format

Some peripherals require the ﬁrst SCK edge before the ﬁrst data bit becomes available at the data out pin, the second edge clocks data into the system. In this format, the ﬁrst SCK edge is issued by setting the CPHA bit at the beginning of the n 1-cycle transfer operation. The ﬁrst edge of SCK occurs immediately after the half SCK clock cycle synchronization delay. This ﬁrst edge commands the slave to transfer its ﬁrst data bit to the serial data input pin of the master. 1. n depends on the selected transfer width, please refer to Section 19.3.2.2, “SPI Control Register 2 (SPICR2) tL Begin End SCK (CPOL = 0) SAMPLE I CHANGE O SEL SS (O) Transfer SCK (CPOL = 1) MSB ﬁrst (LSBFE = 0) LSB ﬁrst (LSBFE = 1) MSB LSB LSB MSB Bit 13 Bit 2 Bit 14 Bit 1 Bit 12 Bit 3 Bit 11 Bit 4 Bit 5 CHANGE O SEL SS (I) MOSI pin MISO pin Master only MOSI/MISO tT If next transfer begins here for tT, tl, tL Minimum 1/2 SCK tI tL tL = Minimum leading time before the ﬁrst SCK edge tT = Minimum trailing time after the last SCK edge tI = Minimum idling time between transfers (minimum SS high time) tL, tT, and tI are guaranteed for the master mode and required for the slave mode. 1 2 3 4 5 6 7 8 9 10111213141516SCK Edge Number End of Idle State Begin of Idle State 17181920212223242526272829303132 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 4 Bit 3 Bit 2 Bit 1 Bit 6Bit 5 Bit 7 Bit 8 Bit 9 Bit 10Bit 11Bit 12Bit 13Bit 14

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A half SCK cycle later, the second edge appears on the SCK pin. This is the latching edge for both the master and slave. When the third edge occurs, the value previously latched from the serial data input pin is shifted into the LSB or MSB of the SPI shift register, depending on LSBFE bit. After this edge, the next bit of the master data is coupled out of the serial data output pin of the master to the serial input pin on the slave. This process continues for a total of n 1 edges on the SCK line with data being latched on even numbered edges and shifting taking place on odd numbered edges. Data reception is double buffered, data is serially shifted into the SPI shift register during the transfer and is transferred to the parallel SPI data register after the last bit is shifted in. After 2n1 SCK edges:

Data that was previously in the SPI data register of the master is now in the data register of the slave, and data that was in the data register of the slave is in the master.
The SPIF ﬂag bit in SPISR is set indicating that the transfer is complete. Figure 19-14 shows two clocking variations for CPHA = 1. The diagram may be interpreted as a master or slave timing diagram because the SCK, MISO, and MOSI pins are connected directly between the master and the slave. The MISO signal is the output from the slave, and the MOSI signal is the output from the master. The SS line is the slave select input to the slave. The SS pin of the master must be either high or reconﬁgured as a general-purpose output not affecting the SPI.

Serial Peripheral Interface (S12SPIV5) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 619 Figure 19-14. SPI Clock Format 1 (CPHA = 1), with 8-Bit Transfer Width selected (XFRW = 0) tL tT for tT, tl, tL Minimum 1/2 SCK tI tL If next transfer begins here Begin End SCK (CPOL = 0) SAMPLE I CHANGE O SEL SS (O) Transfer SCK (CPOL = 1) MSB ﬁrst (LSBFE = 0): LSB ﬁrst (LSBFE = 1): MSB LSB LSB MSB Bit 5 Bit 2 Bit 6 Bit 1 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 CHANGE O SEL SS (I) MOSI pin MISO pin Master only MOSI/MISO tL = Minimum leading time before the ﬁrst SCK edge, not required for back-to-back transfers tT = Minimum trailing time after the last SCK edge tI = Minimum idling time between transfers (minimum SS high time), not required for back-to-back transfers 1 234 56 789 1 0 1 1 1 2 1 3 1 4 1 5 1 6SCK Edge Number End of Idle State Begin of Idle State

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Figure 19-15. SPI Clock Format 1 (CPHA = 1), with 16-Bit Transfer Width selected (XFRW = 1) The SS line can remain active low between successive transfers (can be tied low at all times). This format is sometimes preferred in systems having a single ﬁxed master and a single slave that drive the MISO data line.

Back-to-back transfers in master mode In master mode, if a transmission has completed and new data is available in the SPI data register, this data is sent out immediately without a trailing and minimum idle time. The SPI interrupt request ﬂag (SPIF) is common to both the master and slave modes. SPIF gets set one half SCK cycle after the last SCK edge.

19.4.4 SPI Baud Rate Generation

Baud rate generation consists of a series of divider stages. Six bits in the SPI baud rate register (SPPR2, SPPR1, SPPR0, SPR2, SPR1, and SPR0) determine the divisor to the SPI module clock which results in the SPI baud rate. The SPI clock rate is determined by the product of the value in the baud rate preselection bits (SPPR2–SPPR0) and the value in the baud rate selection bits (SPR2–SPR0). The module clock divisor equation is shown in Equation 19-3. tL Begin End SCK (CPOL = 0) SAMPLE I CHANGE O SEL SS (O) Transfer SCK (CPOL = 1) MSB ﬁrst (LSBFE = 0) LSB ﬁrst (LSBFE = 1) MSB LSB LSB MSB Bit 13 Bit 2 Bit 14 Bit 1 Bit 12 Bit 3 Bit 11 Bit 4 Bit 5 CHANGE O SEL SS (I) MOSI pin MISO pin Master only MOSI/MISO tT If next transfer begins here for tT, tl, tL Minimum 1/2 SCK tI tL tL = Minimum leading time before the ﬁrst SCK edge, not required for back-to-back transfers tT = Minimum trailing time after the last SCK edge tI = Minimum idling time between transfers (minimum SS high time), not required for back-to-back transfers 1 2 3 4 5 6 7 8 9 10111213141516SCK Edge Number End of Idle State Begin of Idle State 17181920212223242526272829303132 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 4 Bit 3 Bit 2 Bit 1 Bit 6Bit 5 Bit 7 Bit 8 Bit 9 Bit 10Bit 11Bit 12Bit 13Bit 14

Serial Peripheral Interface (S12SPIV5) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 621 BaudRateDivisor = (SPPR + 1) • 2(SPR + 1) Eqn. 19-3 When all bits are clear (the default condition), the SPI module clock is divided by 2. When the selection bits (SPR2–SPR0) are 001 and the preselection bits (SPPR2–SPPR0) are 000, the module clock divisor becomes 4. When the selection bits are 010, the module clock divisor becomes 8, etc. When the preselection bits are 001, the divisor determined by the selection bits is multiplied by 2. When the preselection bits are 010, the divisor is multiplied by 3, etc. See Table 19-6 for baud rate calculations for all bit conditions, based on a 25 MHz bus clock. The two sets of selects allows the clock to be divided by a non-power of two to achieve other baud rates such as divide by 6, divide by 10, etc. The baud rate generator is activated only when the SPI is in master mode and a serial transfer is taking place. In the other cases, the divider is disabled to decrease I DD current. NOTE For maximum allowed baud rates, please refer to the SPI Electrical Speciﬁcation in the Electricals chapter of this data sheet.

19.4.5 Special Features

19.4.5.1 SS Output

The SS output feature automatically drives the SS pin low during transmission to select external devices and drives it high during idle to deselect external devices. When SS output is selected, the SS output pin is connected to the SS input pin of the external device. The SS output is available only in master mode during normal SPI operation by asserting SSOE and MODFEN bit as shown in Table 19-2. The mode fault feature is disabled while SS output is enabled. NOTE Care must be taken when using the SS output feature in a multimaster system because the mode fault feature is not available for detecting system errors between masters.

19.4.5.2 Bidirectional Mode (MOMI or SISO)

The bidirectional mode is selected when the SPC0 bit is set in SPI control register 2 (seeTable 19-10). In this mode, the SPI uses only one serial data pin for the interface with external device(s). The MSTR bit decides which pin to use. The MOSI pin becomes the serial data I/O (MOMI) pin for the master mode, and the MISO pin becomes serial data I/O (SISO) pin for the slave mode. The MISO pin in master mode and MOSI pin in slave mode are not used by the SPI.

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The direction of each serial I/O pin depends on the BIDIROE bit. If the pin is conﬁgured as an output, serial data from the shift register is driven out on the pin. The same pin is also the serial input to the shift register.

The SCK is output for the master mode and input for the slave mode.
The SS is the input or output for the master mode, and it is always the input for the slave mode.
The bidirectional mode does not affect SCK and SS functions. NOTE In bidirectional master mode, with mode fault enabled, both data pins MISO and MOSI can be occupied by the SPI, though MOSI is normally used for transmissions in bidirectional mode and MISO is not used by the SPI. If a mode fault occurs, the SPI is automatically switched to slave mode. In this case MISO becomes occupied by the SPI and MOSI is not used. This must be considered, if the MISO pin is used for another purpose.

19.4.6 Error Conditions

The SPI has one error condition:

Mode fault error

19.4.6.1 Mode Fault Error

If the SS input becomes low while the SPI is conﬁgured as a master, it indicates a system error where more than one master may be trying to drive the MOSI and SCK lines simultaneously. This condition is not permitted in normal operation, the MODF bit in the SPI status register is set automatically, provided the MODFEN bit is set. In the special case where the SPI is in master mode and MODFEN bit is cleared, the SS pin is not used by the SPI. In this special case, the mode fault error function is inhibited and MODF remains cleared. In case Table 19-10. Normal Mode and Bidirectional Mode When SPE = 1 Master Mode MSTR = 1 Slave Mode MSTR = 0 Normal Mode SPC0 = 0 Bidirectional Mode SPC0 = 1 SPI MOSI MISO Serial Out Serial In SPI MOSI MISO Serial In Serial Out SPI MOMISerial Out Serial In BIDIROE SPI SISO Serial In Serial Out BIDIROE

Serial Peripheral Interface (S12SPIV5) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 623 the SPI system is conﬁgured as a slave, theSS pin is a dedicated input pin. Mode fault error doesn’t occur in slave mode. If a mode fault error occurs, the SPI is switched to slave mode, with the exception that the slave output buffer is disabled. So SCK, MISO, and MOSI pins are forced to be high impedance inputs to avoid any possibility of conﬂict with another output driver. A transmission in progress is aborted and the SPI is forced into idle state. If the mode fault error occurs in the bidirectional mode for a SPI system conﬁgured in master mode, output enable of the MOMI (MOSI in bidirectional mode) is cleared if it was set. No mode fault error occurs in the bidirectional mode for SPI system conﬁgured in slave mode. The mode fault ﬂag is cleared automatically by a read of the SPI status register (with MODF set) followed by a write to SPI control register 1. If the mode fault ﬂag is cleared, the SPI becomes a normal master or slave again. NOTE If a mode fault error occurs and a received data byte is pending in the receive shift register, this data byte will be lost.

19.4.7 Low Power Mode Options

19.4.7.1 SPI in Run Mode

In run mode with the SPI system enable (SPE) bit in the SPI control register clear, the SPI system is in a low-power, disabled state. SPI registers remain accessible, but clocks to the core of this module are disabled.

19.4.7.2 SPI in Wait Mode

SPI operation in wait mode depends upon the state of the SPISW AI bit in SPI control register 2.

If SPISW AI is clear, the SPI operates normally when the CPU is in wait mode
If SPISW AI is set, SPI clock generation ceases and the SPI module enters a power conservation state when the CPU is in wait mode. – If SPISWAI is set and the SPI is configured for master, any transmission and reception in progress stops at wait mode entry. The transmission and reception resumes when the SPI exits wait mode. – If SPISWAI is set and the SPI is configured as a slave, any transmission and reception in progress continues if the SCK continues to be driven from the master. This keeps the slave synchronized to the master and the SCK. If the master transmits several bytes while the slave is in wait mode, the slave will continue to send out bytes consistent with the operation mode at the start of wait mode (i.e., if the slave is currently sending its SPIDR to the master, it will continue to send the same byte. Else if the slave is currently sending the last received byte from the master, it will continue to send each previous master byte).

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Care must be taken when expecting data from a master while the slave is in wait or stop mode. Even though the shift register will continue to operate, the rest of the SPI is shut down (i.e., a SPIF interrupt willnot be generated until exiting stop or wait mode). Also, the byte from the shift register will not be copied into the SPIDR register until after the slave SPI has exited wait or stop mode. In slave mode, a received byte pending in the receive shift register will be lost when entering wait or stop mode. An SPIF ﬂag and SPIDR copy is generated only if wait mode is entered or exited during a tranmission. If the slave enters wait mode in idle mode and exits wait mode in idle mode, neither a SPIF nor a SPIDR copy will occur.

19.4.7.3 SPI in Stop Mode

Stop mode is dependent on the system. The SPI enters stop mode when the module clock is disabled (held high or low). If the SPI is in master mode and exchanging data when the CPU enters stop mode, the transmission is frozen until the CPU exits stop mode. After stop, data to and from the external SPI is exchanged correctly. In slave mode, the SPI will stay synchronized with the master. The stop mode is not dependent on the SPISW AI bit.

19.4.7.4 Reset

The reset values of registers and signals are described in Section 19.3, “Memory Map and Register Deﬁnition”, which details the registers and their bit ﬁelds.

If a data transmission occurs in slave mode after reset without a write to SPIDR, it will transmit garbage, or the data last received from the master before the reset.
Reading from the SPIDR after reset will always read zeros.

19.4.7.5 Interrupts

The SPI only originates interrupt requests when SPI is enabled (SPE bit in SPICR1 set). The following is a description of how the SPI makes a request and how the MCU should acknowledge that request. The interrupt vector offset and interrupt priority are chip dependent. The interrupt ﬂags MODF, SPIF, and SPTEF are logically ORed to generate an interrupt request.

19.4.7.5.1 MODF

MODF occurs when the master detects an error on the SS pin. The master SPI must be conﬁgured for the MODF feature (see Table 19-2). After MODF is set, the current transfer is aborted and the following bit is changed:

MSTR = 0, The master bit in SPICR1 resets. The MODF interrupt is reﬂected in the status register MODF ﬂag. Clearing the ﬂag will also clear the interrupt. This interrupt will stay active while the MODF ﬂag is set. MODF has an automatic clearing process which is described in Section 19.3.2.4, “SPI Status Register (SPISR)”.

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19.4.7.5.2 SPIF

SPIF occurs when new data has been received and copied to the SPI data register. After SPIF is set, it does not clear until it is serviced. SPIF has an automatic clearing process, which is described in Section 19.3.2.4, “SPI Status Register (SPISR)”.

19.4.7.5.3 SPTEF

SPTEF occurs when the SPI data register is ready to accept new data. After SPTEF is set, it does not clear until it is serviced. SPTEF has an automatic clearing process, which is described inSection 19.3.2.4, “SPI Status Register (SPISR)”.

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MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 627 Chapter 20 Timer Module (TIM16B8CV3)

20.1 Introduction

The basic scalable timer consists of a 16-bit, software-programmable counter driven by a ﬂexible programmable prescaler. This timer can be used for many purposes, including input waveform measurements while simultaneously generating an output waveform. Pulse widths can vary from microseconds to many seconds. This timer could contain up to 8 (0....7) input capture/output compare channels with one pulse accumulator available only on channel 7. The input capture function is used to detect a selected transition edge and record the time. The output compare function is used for generating output signals or for timer software delays. The 16-bit pulse accumulator is used to operate as a simple event counter or a gated time accumulator. The pulse accumulator shares timer channel 7 when the channel is available and when in event mode. A full access for the counter registers or the input capture/output compare registers should take place in one clock cycle. Accessing high byte and low byte separately for all of these registers may not yield the same result as accessing them in one word.

20.1.1 Features

The TIM16B8CV3 includes these distinctive features:

Up to 8 channels available. (refer to device speciﬁcation for exact number)
All channels have same input capture/output compare functionality. Table 20-1. V03.00 Jan. 28, 2009 Initial version V03.01 Aug. 26, 2009 20.1.2/20-628 Figure 20-4./20- 631 20.3.2.15/20-64 20.3.2.2/20-634, 20.3.2.3/20-635, 20.3.2.4/20-635, 20.4.3/20-651 - Correct typo: TSCR ->TSCR1; - Correct typo: ECTxxx->TIMxxx - Correct reference: Figure 20-25 -> Figure 20-30 - Add description, “a counter overﬂow when TTOV[7] is set”, to be the condition of channel 7 override event. - Phrase the description of OC7M to make it more explicit V03.02 Apri,12,2010 20.3.2.8/20-638 20.3.2.11/20-64 20.4.3/20-651 -Add Table 20-10 -update TCRE bit description -add Figure 20-31

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Clock prescaling.
16-bit counter.
16-bit pulse accumulator on channel 7 if channel 7 exists.

20.1.2 Modes of Operation

Stop: Timer is off because clocks are stopped. Freeze: Timer counter keeps on running, unless TSFRZ in TSCR1 is set to 1. Wait: Counters keeps on running, unless TSWAI in TSCR1 is set to 1. Normal: Timer counter keep on running, unless TEN in TSCR1 is cleared to 0.

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20.1.3 Block Diagrams

Figure 20-1. TIM16B8CV3 Block Diagram Prescaler 16-bit Counter Input capture Output compare 16-bit Pulse accumulator IOC0 IOC2 IOC1 IOC5 IOC3 IOC4 IOC6 IOC7 PA input interrupt PA overﬂow interrupt Timer overﬂow interrupt Timer channel 0 interrupt Timer channel 7 interrupt Registers Bus clock Input capture Output compare Input capture Output compare Input capture Output compare Input capture Output compare Input capture Output compare Input capture Output compare Input capture Output compare Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Maximum possible channels, scalable from 0 to 7. Pulse Accumulator is available only if channel 7 exists.

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Figure 20-2. 16-Bit Pulse Accumulator Block Diagram Figure 20-3. Interrupt Flag Setting Edge detector Intermodule Bus IOC7 M clockDivide by 64 Clock select CLK0 CLK1 4:1 MUX TIMCLK PACLK PACLK / 256 PACLK / 65536 Prescaled clock (PCLK) (Timer clock) Interrupt MUX (PAMOD) PACNT IOCn Edge detector 16-bit Main Timer TCn Input Capture Reg. Set CnF Interrupt

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20.2 External Signal Description

The TIM16B8CV3 module has a selected number of external pins. Refer to device speciﬁcation for exact number.

20.2.1 IOC7 — Input Capture and Output Compare Channel 7

This pin serves as input capture or output compare for channel 7 if this channel is available. This can also be conﬁgured as pulse accumulator input.

20.2.2 IOC6 - IOC0 — Input Capture and Output Compare Channel 6-0

Those pins serve as input capture or output compare for TIM168CV3 channel if the corresponding channel is available. NOTE For the description of interrupts see Section 20.6, “Interrupts”.

20.3 Memory Map and Register Deﬁnition

This section provides a detailed description of all memory and registers.

20.3.1 Module Memory Map

The memory map for the TIM16B8CV3 module is given below inFigure 20-5. The address listed for each register is the address offset. The total address for each register is the sum of the base address for the TIM16B8CV3 module and the address offset for each register. PULSE ACCUMULATOR PAD TEN CHANNEL 7 OUTPUT COMPARE OCPD TIOS7

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20.3.2 Register Descriptions

This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated ﬁgure number. Details of register bit and ﬁeld function follow the register diagrams, in bit order. Only bits related to implemented channels are valid. Register Name Bit 7 654321 Bit 0 0x0000 TIOS1 R IOS7 IOS6 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0W 0x0001 CFORC1 R 00000000 W FOC7 FOC6 FOC5 FOC4 FOC3 FOC2 FOC1 FOC0 0x0002 OC7M2 R OC7M7 OC7M6 OC7M5 OC7M4 OC7M3 OC7M2 OC7M1 OC7M0W 0x0003 OC7D2 R OC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0W 0x0004 TCNTH R TCNT15 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10 TCNT9 TCNT8W 0x0005 TCNTL R TCNT7 TCNT6 TCNT5 TCNT4 TCNT3 TCNT2 TCNT1 TCNT0W 0x0006 TSCR1 R TEN TSWAI TSFRZ TFFCA PRNT 000 W 0x0007 TTOV1 R TOV7 TOV6 TOV5 TOV4 TOV3 TOV2 TOV1 TOV0W 0x0008 TCTL11 R OM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4W 0x0009 TCTL21 R OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0W 0x000A TCTL31 R EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4AW 0x000B TCTL41 R EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0AW 0x000C TIE1 R C7I C6I C5I C4I C3I C2I C1I C0IW 0x000D TSCR21 R TOI 000 TCRE PR2 PR1 PR0W = Unimplemented or Reserved Figure 20-5. TIM16B8CV3 Register Summary (Sheet 1 of 2)

Timer Module (TIM16B8CV3) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 633 0x000E TFLG11 R C7F C6F C5F C4F C3F C2F C1F C0FW 0x000F TFLG2 R TOF 0000000 W 0x0010–0x001F TCxH–TCxL3 R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8W R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0W 0x0020 PACTL2 R0 PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAIW 0x0021 PAFLG2 R 000000 PAOVF PAIFW 0x0022 PACNTH2 R PACNT15 PACNT14 PACNT13 PACNT12 PACNT11 PACNT10 PACNT9 PACNT8W 0x0023 PACNTL2 R PACNT7 PACNT6 PACNT5 PACNT4 PACNT3 PACNT2 PACNT1 PACNT0W 0x0024–0x002B Reserved R W 0x002C OCPD1 R OCPD7 OCPD6 OCPD5 OCPD4 OCPD3 OCPD2 OCPD1 OCPD0W 0x002D Reserved R 0x002E PTPSR R PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0W 0x002F Reserved R W

1 The related bit is available only if corresponding channel exists

2 The register is available only if channel 7 exists. 3 The register is available only if corresponding channel exists. Register Name Bit 7 654321 Bit 0 = Unimplemented or Reserved Figure 20-5. TIM16B8CV3 Register Summary (Sheet 2 of 2)

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20.3.2.1 Timer Input Capture/Output Compare Select (TIOS)

Read: Anytime Write: Anytime

20.3.2.2 Timer Compare Force Register (CFORC)

Read: Anytime but will always return 0x0000 (1 state is transient) Write: Anytime 76543210 R IOS7 IOS6 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0 W Reset 00000000 Figure 20-6. Timer Input Capture/Output Compare Select (TIOS) Table 20-2. TIOS Field Descriptions Note: Bits related to available channels have functional signiﬁcance. Writing to unavailable bits has no effect. Read from unavailable bits return a zero. Field Description 7:0 IOS[7:0] Input Capture or Output Compare Channel Conﬁguration 0 The corresponding implemented channel acts as an input capture. 1 The corresponding implemented channel acts as an output compare. 76543210 R 00000000 W FOC7 FOC6 FOC5 FOC4 FOC3 FOC2 FOC1 FOC0 Reset 00000000 Figure 20-7. Timer Compare Force Register (CFORC) Table 20-3. CFORC Field Descriptions Note: Bits related to available channels have functional effect. Writing to unavailable bits has no effect. Read from unavailable bits return a zero. Field Description 7:0 FOC[7:0] Force Output Compare Action for Channel 7:0— A write to this register with the corresponding data bit(s) set causes the action which is programmed for output compare “x” to occur immediately. The action taken is the same as if a successful comparison had just taken place with the TCx register except the interrupt ﬂag does not get set. Note: A channel 7 event, which can be a counter overﬂow when TTOV[7] is set or a successful output compare on channel 7, overrides any channel 6:0 compares. If forced output compare on any channel occurs at the same time as the successful output compare then forced output compare action will take precedence and interrupt ﬂag won’t get set.

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20.3.2.3 Output Compare 7 Mask Register (OC7M)

20.3.2.4 Output Compare 7 Data Register (OC7D)

1 This register is available only when channel 7 exists and is reserved if that channel does not exist. Writes to a reserved register have no functional effect. Reads from a reserved register return zeroes. Read: Anytime Write: Anytime 76543210 R OC7M7 OC7M6 OC7M5 OC7M4 OC7M3 OC7M2 OC7M1 OC7M0 W Reset 00000000 Figure 20-8. Output Compare 7 Mask Register (OC7M) Table 20-4. OC7M Field Descriptions Field Description 7:0 OC7M[7:0] Output Compare 7 Mask — A channel 7 event, which can be a counter overﬂow when TTOV[7] is set or a successful output compare on channel 7, overrides any channel 6:0 compares. For each OC7M bit that is set, the output compare action reﬂects the corresponding OC7D bit. 0 The corresponding OC7Dx bit in the output compare 7 data register will not be transferred to the timer port on a channel 7 event, even if the corresponding pin is setup for output compare. 1 The corresponding OC7Dx bit in the output compare 7 data register will be transferred to the timer port on a channel 7 event. Note: The corresponding channel must also be setup for output compare (IOSx = 1 and OCPDx = 0) for data to be transferred from the output compare 7 data register to the timer port. 76543210 R OC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0 W Reset 00000000 Figure 20-9. Output Compare 7 Data Register (OC7D) Table 20-5. OC7D Field Descriptions Field Description 7:0 OC7D[7:0] Output Compare 7 Data — A channel 7 event, which can be a counter overﬂow when TTOV[7] is set or a successful output compare on channel 7, can cause bits in the output compare 7 data register to transfer to the timer port data register depending on the output compare 7 mask register.

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20.3.2.5 Timer Count Register (TCNT)

The 16-bit main timer is an up counter. A full access for the counter register should take place in one clock cycle. A separate read/write for high byte and low byte will give a different result than accessing them as a word. Read: Anytime Write: Has no meaning or effect in the normal mode; only writable in special modes (test_mode = 1). The period of the ﬁrst count after a write to the TCNT registers may be a different size because the write is not synchronized with the prescaler clock.

20.3.2.6 Timer System Control Register 1 (TSCR1)

Read: Anytime Write: Anytime 15 14 13 12 11 10 9 9 R TCNT15 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10 TCNT9 TCNT8 W Reset 00000000 Figure 20-10. Timer Count Register High (TCNTH) 76543210 R TCNT7 TCNT6 TCNT5 TCNT4 TCNT3 TCNT2 TCNT1 TCNT0 W Reset 00000000 Figure 20-11. Timer Count Register Low (TCNTL) 76543210 R TEN TSWAI TSFRZ TFFCA PRNT 000 W Reset 00000000 = Unimplemented or Reserved Figure 20-12. Timer System Control Register 1 (TSCR1)

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20.3.2.7 Timer Toggle On Overﬂow Register 1 (TTOV)

Read: Anytime Write: Anytime Table 20-6. TSCR1 Field Descriptions Field Description TEN Timer Enable 0 Disables the main timer, including the counter. Can be used for reducing power consumption. 1 Allows the timer to function normally. If for any reason the timer is not active, there is no ÷64 clock for the pulse accumulator because the ÷64 is generated by the timer prescaler. TSWAI Timer Module Stops While in Wait 0 Allows the timer module to continue running during wait. 1 Disables the timer module when the MCU is in the wait mode. Timer interrupts cannot be used to get the MCU out of wait. TSWAI also affects pulse accumulator. TSFRZ Timer Stops While in Freeze Mode 0 Allows the timer counter to continue running while in freeze mode. 1 Disables the timer counter whenever the MCU is in freeze mode. This is useful for emulation. TSFRZ does not stop the pulse accumulator. TFFCA Timer Fast Flag Clear All 0 Allows the timer ﬂag clearing to function normally. 1 For TFLG1(0x000E), a read from an input capture or a write to the output compare channel (0x0010–0x001F) causes the corresponding channel ﬂag, CnF , to be cleared. For TFLG2 (0x000F), any access to the TCNT register (0x0004, 0x0005) clears the TOF ﬂag. Any access to the PACNT registers (0x0022, 0x0023) clears the PAOVF and PAIF ﬂags in the PAFLG register (0x0021) if channel 7 exists. This has the advantage of eliminating software overhead in a separate clear sequence. Extra care is required to avoid accidental ﬂag clearing due to unintended accesses. PRNT Precision Timer 0 Enables legacy timer. PR0, PR1, and PR2 bits of the TSCR2 register are used for timer counter prescaler selection. 1 Enables precision timer. All bits of the PTPSR register are used for Precision Timer Prescaler Selection, and all bits. This bit is writable only once out of reset. 76543210 R TOV7 TOV6 TOV5 TOV4 TOV3 TOV2 TOV1 TOV0 W Reset 00000000 Figure 20-13. Timer Toggle On Overﬂow Register 1 (TTOV)

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20.3.2.8 Timer Control Register 1/Timer Control Register 2 (TCTL1/TCTL2)

Read: Anytime Write: Anytime Table 20-7. TTOV Field Descriptions Note: Bits related to available channels have functional signiﬁcance. Writing to unavailable bits has no effect. Read from unavailable bits return a zero. Field Description 7:0 TOV[7:0] Toggle On Overﬂow Bits — TOVx toggles output compare pin on overﬂow. This feature only takes effect when in output compare mode. When set, it takes precedence over forced output compare but not channel 7 override events. 0 Toggle output compare pin on overﬂow feature disabled. 1 Toggle output compare pin on overﬂow feature enabled. 76543210 R OM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4 W Reset 00000000 Figure 20-14. Timer Control Register 1 (TCTL1) 76543210 R OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0 W Reset 00000000 Figure 20-15. Timer Control Register 2 (TCTL2) Table 20-8. TCTL1/TCTL2 Field Descriptions Note: Bits related to available channels have functional signiﬁcance. Writing to unavailable bits has no effect. Read from unavailable bits return a zero Field Description 7:0 OMx Output Mode — These eight pairs of control bits are encoded to specify the output action to be taken as a result of a successful OCx compare. When either OMx or OLx is 1, the pin associated with OCx becomes an output tied to OCx. Note: To enable output action by OMx bits on timer port, the corresponding bit in OC7M should be cleared. For an output line to be driven by an OCx the OCPDx must be cleared. 7:0 OLx Output Level — These eight pairs of control bits are encoded to specify the output action to be taken as a result of a successful OCx compare. When either OMx or OLx is 1, the pin associated with OCx becomes an output tied to OCx. Note: To enable output action by OLx bits on timer port, the corresponding bit in OC7M should be cleared. For an output line to be driven by an OCx the OCPDx must be cleared.

Timer Module (TIM16B8CV3) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 639 Note: To enable output action using the OM7 and OL7 bits on the timer port,the corresponding bit OC7M7 in the OC7M register must also be cleared. The settings for these bits can be seen inTable 20-10. Note: in Table 20-10, the IOS7 and IOSx should be set to 1 IOSx is the register TIOS bit x, OC7Mx is the register OC7M bit x, TCx is timer Input Capture/Output Compare register, IOCx is channel x, OMx/OLx is the register TCTL1/TCTL2, OC7Dx is the register OC7D bit x. IOCx = OC7Dx+ OMx/OLx, means that both OC7 event and OCx event will change channel x value. Table 20-9. Compare Result Output Action OMx OLx Action 0 0 No output compare action on the timer output signal 0 1 Toggle OCx output line 1 0 Clear OCx output line to zero 1 1 Set OCx output line to one Table 20-10. The OC7 and OCx event priority OC7M7=0 OC7M7=1 OC7Mx=1 OC7Mx=0 OC7Mx=1 OC7Mx=0 TC7=TCx TC7>TCx TC7=TCx TC7>TCx TC7=TCx TC7>TCx TC7=TCx TC7>TCx IOCx=OC7Dx IOC7=OM7/O IOCx=OC7Dx +OMx/OLx IOC7=OM7/O IOCx=OMx/OLx IOC7=OM7/OL7 IOCx=OC7Dx IOC7=OC7D7 IOCx=OC7Dx +OMx/OLx IOC7=OC7D7 IOCx=OMx/OLx IOC7=OC7D7

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20.3.2.9 Timer Control Register 3/Timer Control Register 4 (TCTL3 and TCTL4)

Read: Anytime Write: Anytime.

20.3.2.10 Timer Interrupt Enable Register (TIE)

Read: Anytime 76543210 R EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A W Reset 00000000 Figure 20-16. Timer Control Register 3 (TCTL3) 76543210 R EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A W Reset 00000000 Figure 20-17. Timer Control Register 4 (TCTL4) Table 20-11. TCTL3/TCTL4 Field Descriptions Note: Bits related to available channels have functional signiﬁcance. Writing to unavailable bits has no effect. Read from unavailable bits return a zero. Field Description 7:0 EDGnB EDGnA Input Capture Edge Control — These eight pairs of control bits conﬁgure the input capture edge detector circuits. Table 20-12. Edge Detector Circuit Conﬁguration EDGnB EDGnA Conﬁguration 0 0 Capture disabled 0 1 Capture on rising edges only 1 0 Capture on falling edges only 1 1 Capture on any edge (rising or falling) 76543210 R C7I C6I C5I C4I C3I C2I C1I C0I W Reset 00000000 Figure 20-18. Timer Interrupt Enable Register (TIE)

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20.3.2.11 Timer System Control Register 2 (TSCR2)

Read: Anytime Write: Anytime. Table 20-13. TIE Field Descriptions Note: Bits related to available channels have functional signiﬁcance. Writing to unavailable bits has no effect. Read from unavailable bits return a zero Field Description 7:0 C7I:C0I Input Capture/Output Compare “x” Interrupt Enable — The bits in TIE correspond bit-for-bit with the bits in the TFLG1 status register. If cleared, the corresponding ﬂag is disabled from causing a hardware interrupt. If set, the corresponding ﬂag is enabled to cause a interrupt. 76543210 R TOI 000 TCRE PR2 PR1 PR0 W Reset 00000000 = Unimplemented or Reserved Figure 20-19. Timer System Control Register 2 (TSCR2) Table 20-14. TSCR2 Field Descriptions Field Description TOI Timer Overﬂow Interrupt Enable 0 Interrupt inhibited. 1 Hardware interrupt requested when TOF ﬂag set. TCRE Timer Counter Reset Enable — This bit allows the timer counter to be reset by a successful output compare 7 event. This mode of operation is similar to an up-counting modulus counter. 0 Counter reset inhibited and counter free runs. 1 Counter reset by a successful output compare 7. Note: If TC7 = 0x0000 and TCRE = 1, TCNT will stay at 0x0000 continuously. If TC7 = 0xFFFF and TCRE = 1, TOF will never be set when TCNT is reset from 0xFFFF to 0x0000. Note: TCRE=1 and TC7!=0, the TCNT cycle period will be TC7 x "prescaler counter width" + "1 Bus Clock", for a more detail explanation please refer to Section 20.4.3, “Output Compare Note: This bit and feature is available only when channel 7 exists. If channel 7 doesn’t exist, this bit is reserved. Writing to reserved bit has no effect. Read from reserved bit return a zero. PR[2:0] Timer Prescaler Select — These three bits select the frequency of the timer prescaler clock derived from the Bus Clock as shown in Table 20-15. Table 20-15. Timer Clock Selection PR2 PR1 PR0 Timer Clock 0 0 0 Bus Clock / 1

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The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter stages equal zero.

20.3.2.12 Main Timer Interrupt Flag 1 (TFLG1)

Read: Anytime Write: Used in the clearing mechanism (set bits cause corresponding bits to be cleared). Writing a zero will not affect current status of the bit. 0 0 1 Bus Clock / 2 0 1 0 Bus Clock / 4 0 1 1 Bus Clock / 8 1 0 0 Bus Clock / 16 1 0 1 Bus Clock / 32 1 1 0 Bus Clock / 64 1 1 1 Bus Clock / 128 76543210 R C7F C6F C5F C4F C3F C2F C1F C0F W Reset 00000000 Figure 20-20. Main Timer Interrupt Flag 1 (TFLG1) Table 20-16. TRLG1 Field Descriptions Note: Bits related to available channels have functional signiﬁcance. Writing to unavailable bits has no effect. Read from unavailable bits return a zero. Field Description 7:0 C[7:0]F Input Capture/Output Compare Channel “x” Flag — These flags are set when an input capture or output compare event occurs. Clearing requires writing a one to the corresponding ﬂag bit while TEN or PAEN is set to one. Note: When TFFCA bit in TSCR register is set, a read from an input capture or a write into an output compare channel (0x0010–0x001F) will cause the corresponding channel ﬂag CxF to be cleared. Table 20-15. Timer Clock Selection PR2 PR1 PR0 Timer Clock

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20.3.2.13 Main Timer Interrupt Flag 2 (TFLG2)

TFLG2 indicates when interrupt conditions have occurred. To clear a bit in the ﬂag register, write the bit to one while TEN bit of TSCR1 or PAEN bit of PACTL is set to one. Read: Anytime Write: Used in clearing mechanism (set bits cause corresponding bits to be cleared). Any access to TCNT will clear TFLG2 register if the TFFCA bit in TSCR register is set.

20.3.2.14 Timer Input Capture/Output Compare Registers High and Low 0–7

(TCxH and TCxL) 1 This register is available only when the corresponding channel exists and is reserved if that channel does not exist. Writes to a reserved register have no functional effect. Reads from a reserved register return zeroes. Depending on the TIOS bit for the corresponding channel, these registers are used to latch the value of the free-running counter when a deﬁned transition is sensed by the corresponding input capture edge detector or to trigger an output action for output compare. 76543210 R TOF 0000000 W Reset 00000000 Unimplemented or Reserved Figure 20-21. Main Timer Interrupt Flag 2 (TFLG2) Table 20-17. TRLG2 Field Descriptions Field Description TOF Timer Overﬂow Flag — Set when 16-bit free-running timer overﬂows from 0xFFFF to 0x0000. Clearing this bit requires writing a one to bit 7 of TFLG2 register while the TEN bit of TSCR1 or PAEN bit of PACTL is set to one (See also TCRE control bit explanation.) 15 14 13 12 11 10 9 0 R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 W Reset 00000000 Figure 20-22. Timer Input Capture/Output Compare Register x High (TCxH) 76543210 R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W Reset 00000000 Figure 20-23. Timer Input Capture/Output Compare Register x Low (TCxL)

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Read: Anytime Write: Anytime for output compare function.Writes to these registers have no meaning or effect during input capture. All timer input capture/output compare registers are reset to 0x0000. NOTE Read/Write access in byte mode for high byte should takes place before low byte otherwise it will give a different result. 20.3.2.15 16-Bit Pulse Accumulator Control Register (PACTL) 1 This register is available only when channel 7 exists and is reserved if that channel does not exist. Writes to a reserved register have no functional effect. Reads from a reserved register return zeroes. Read: Any time Write: Any time When PAEN is set, the Pulse Accumulator counter is enabled.The Pulse Accumulator counter shares the input pin with IOC7. 76543210 PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI W Reset 00000000 Unimplemented or Reserved Figure 20-24. 16-Bit Pulse Accumulator Control Register (PACTL) Table 20-18. PACTL Field Descriptions Field Description PAEN Pulse Accumulator System Enable — PAEN is independent from TEN. With timer disabled, the pulse accumulator can function unless pulse accumulator is disabled. 0 16-Bit Pulse Accumulator system disabled. 1 Pulse Accumulator system enabled. PAMOD Pulse Accumulator Mode — This bit is active only when the Pulse Accumulator is enabled (PAEN = 1). See Table 20-19. 0 Event counter mode. 1 Gated time accumulation mode. PEDGE Pulse Accumulator Edge Control— This bit is active only when the Pulse Accumulator is enabled (PAEN = 1). For PAMOD bit = 0 (event counter mode). SeeTable 20-19. 0 Falling edges on IOC7 pin cause the count to be increased. 1 Rising edges on IOC7 pin cause the count to be increased. For PAMOD bit = 1 (gated time accumulation mode). 0 IOC7 input pin high enables M (bus clock) divided by 64 clock to Pulse Accumulator and the trailing falling edge on IOC7 sets the PAIF ﬂag. 1 IOC7 input pin low enables M (bus clock) divided by 64 clock to Pulse Accumulator and the trailing rising edge on IOC7 sets the PAIF ﬂag.

Timer Module (TIM16B8CV3) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 645 NOTE If the timer is not active (TEN = 0 in TSCR), there is no divide-by-64 because the ÷64 clock is generated by the timer prescaler. For the description of PACLK please referFigure 20-30. If the pulse accumulator is disabled (PAEN = 0), the prescaler clock from the timer is always used as an input clock to the timer counter. The change from one selected clock to the other happens immediately after these bits are written. 3:2 CLK[1:0] Clock Select Bits — Refer to Table 20-20. PAOVI Pulse Accumulator Overﬂow Interrupt Enable 0 Interrupt inhibited. 1 Interrupt requested if PAOVF is set. PAI Pulse Accumulator Input Interrupt Enable 0 Interrupt inhibited. 1 Interrupt requested if PAIF is set. Table 20-19. Pin Action PAMOD PEDGE Pin Action 0 0 Falling edge 0 1 Rising edge 1 0 Div. by 64 clock enabled with pin high level 1 1 Div. by 64 clock enabled with pin low level Table 20-20. Timer Clock Selection CLK1 CLK0 Timer Clock 0 0 Use timer prescaler clock as timer counter clock 0 1 Use PACLK as input to timer counter clock 1 0 Use PACLK/256 as timer counter clock frequency 1 1 Use PACLK/65536 as timer counter clock frequency Table 20-18. PACTL Field Descriptions (continued) Field Description

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20.3.2.16 Pulse Accumulator Flag Register (PAFLG)

1 This register is available only when channel 7 exists and is reserved if that channel does not exist. Writes to a reserved register have no functional effect. Reads from a reserved register return zeroes. Read: Anytime Write: Anytime When the TFFCA bit in the TSCR register is set, any access to the PACNT register will clear all the ﬂags in the PAFLG register. Timer module or Pulse Accumulator must stay enabled (TEN=1 or PAEN=1) while clearing these bits.

20.3.2.17 Pulse Accumulators Count Registers (PACNT)

W Reset 00000000 Unimplemented or Reserved Figure 20-25. Pulse Accumulator Flag Register (PAFLG) Table 20-21. PAFLG Field Descriptions Field Description PAOVF Pulse Accumulator Overﬂow Flag— Set when the 16-bit pulse accumulator overﬂows from 0xFFFF to 0x0000. Clearing this bit requires writing a one to this bit in the PAFLG register while TEN bit of TSCR1 or PAEN bit of PACTL register is set to one. PAIF Pulse Accumulator Input edge Flag — Set when the selected edge is detected at the IOC7 input pin.In event mode the event edge triggers PAIF and in gated time accumulation mode the trailing edge of the gate signal at the IOC7 input pin triggers PAIF . Clearing this bit requires writing a one to this bit in the PAFLG register while TEN bit of TSCR1 or PAEN bit of PACTL register is set to one. Any access to the PACNT register will clear all the ﬂags in this register when TFFCA bit in register TSCR(0x0006) is set. 15 14 13 12 11 10 9 0 R PACNT15 PACNT14 PACNT13 PACNT12 PACNT11 PACNT10 PACNT9 PACNT8 W Reset 00000000 Figure 20-26. Pulse Accumulator Count Register High (PACNTH)

Timer Module (TIM16B8CV3) MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 647 1 This register is available only when channel 7 exists and is reserved if that channel does not exist. Writes to a reserved register have no functional effect. Reads from a reserved register return zeroes. Read: Anytime Write: Anytime These registers contain the number of active input edges on its input pin since the last reset. When PACNT overﬂows from 0xFFFF to 0x0000, the Interrupt ﬂag PAOVF in PAFLG (0x0021) is set. Full count register access should take place in one clock cycle. A separate read/write for high byte and low byte will give a different result than accessing them as a word. NOTE Reading the pulse accumulator counter registers immediately after an active edge on the pulse accumulator input pin may miss the last count because the input has to be synchronized with the bus clock ﬁrst.

20.3.2.18 Output Compare Pin Disconnect Register(OCPD)

Read: Anytime Write: Anytime All bits reset to zero. 76543210 R PACNT7 PACNT6 PACNT5 PACNT4 PACNT3 PACNT2 PACNT1 PACNT0 W Reset 00000000 Figure 20-27. Pulse Accumulator Count Register Low (PACNTL) 76543210 R OCPD7 OCPD6 OCPD5 OCPD4 OCPD3 OCPD2 OCPD1 OCPD0 W Reset 00000000 Figure 20-28. Output Compare Pin Disconnect Register (OCPD) Table 20-22. OCPD Field Description Note: Bits related to available channels have functional signiﬁcance. Writing to unavailable bits has no effect. Read from unavailable bits return a zero. Field Description OCPD[7:0} Output Compare Pin Disconnect Bits 0 Enables the timer channel port. Output Compare action will occur on the channel pin. These bits do not affect the input capture or pulse accumulator functions 1 Disables the timer channel port. Output Compare action will not occur on the channel pin, but the output compare ﬂag still become set.

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20.3.2.19 Precision Timer Prescaler Select Register (PTPSR)

Read: Anytime Write: Anytime All bits reset to zero. ... The Prescaler can be calculated as follows depending on logical value of the PTPS[7:0] and PRNT bit: PRNT = 1 : Prescaler = PTPS[7:0] + 1 Table 20-24. Precision Timer Prescaler Selection Examples when PRNT = 1 76543210 R PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0 W Reset 00000000 Figure 20-29. Precision Timer Prescaler Select Register (PTPSR) Table 20-23. PTPSR Field Descriptions Field Description 7:0 PTPS[7:0] Precision Timer Prescaler Select Bits— These eight bits specify the division rate of the main Timer prescaler. These are effective only when the PRNT bit of TSCR1 is set to 1.Table 20-24shows some selection examples in this case. The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter stages equal zero. PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0 Prescale Factor 00000000 1 00000001 2 00000010 3 00000011 4 00010011 2 0 00010100 2 1 00010101 2 2 11111100 2 5 3

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20.4 Functional Description

This section provides a complete functional description of the timer TIM16B8CV3 block. Please refer to the detailed timer block diagram in Figure 20-30 as necessary. 11111101 2 5 4 11111110 2 5 5 11111111 2 5 6 PTPS7 PTPS6 PTPS5 PTPS4 PTPS3 PTPS2 PTPS1 PTPS0 Prescale Factor

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Figure 20-30. Detailed Timer Block Diagram PRESCALER CHANNEL 0 IOC0 PIN 16-BIT COUNTER LOGIC PR[2:1:0] DIVIDE-BY-64 TC0 EDGE DETECT PACNT(hi):PACNT(lo)PAOVF PEDGE PAOVI TEN PAEN 16-BIT COMPARATOR TCNT(hi):TCNT(lo) CHANNEL 1 TC1 16-BIT COMPARATOR 16-BIT COUNTER INTERRUPT LOGIC TOF TOI C0F C1F EDGE DETECT IOC1 PIN LOGICEDGE DETECT CxF CHANNEL7 TC7 16-BIT COMPARATOR C7F IOC7 PIN LOGIC EDGE DETECT OM:OL0 TOV0 OM:OL1 TOV1 OM:OL7 TOV7 EDG1A EDG1B EDG7A EDG7B EDG0B TCRE PAIF CLEAR COUNTER PAIF PAI INTERRUPT LOGIC CxI INTERRUPT REQUEST PAOVF CH. 7 COMPARE CH.7 CAPTURE CH. 1 CAPTURE MUX CLK[1:0] PACLK PACLK/256 PACLK/65536 IOC1 PIN IOC0 PIN IOC7 PIN PACLKPACLK/256 PACLK/65536 TE CH. 1 COMPARE CH. 0COMPARE CH. 0 CAPTURE PA INPUT CHANNEL2 EDG0A channel 7 output compare IOC0 IOC1 IOC7 Bus Clock PAOVF PAOVI TOF C0F C1F C7F MUX PRE-PRESCALER PTPSR[7:0] Bus Clock 1

0 PRNT

Maximum possible channels, scalable from 0 to 7. Pulse Accumulator is available only if channel 7 exists. MUX PAMOD PEDGE

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20.4.1 Prescaler

The prescaler divides the bus clock by 1, 2, 4, 8, 16, 32, 64 or 128. The prescaler select bits, PR[2:0], select the prescaler divisor. PR[2:0] are in timer system control register 2 (TSCR2). The prescaler divides the bus clock by a prescalar value. Prescaler select bits PR[2:0] of in timer system control register 2 (TSCR2) are set to deﬁne a prescalar value that generates a divide by 1, 2, 4, 8, 16, 32, 64 and 128 when the PRNT bit in TSCR1 is disabled. By enabling the PRNT bit of the TSCR1 register, the performance of the timer can be enhanced. In this case, it is possible to set additional prescaler settings for the main timer counter in the present timer by

20.4.2 Input Capture

Clearing the I/O (input/output) select bit, IOSx, conﬁgures channel x as an input capture channel. The input capture function captures the time at which an external event occurs. When an active edge occurs on the pin of an input capture channel, the timer transfers the value in the timer counter into the timer channel registers, TCx. The minimum pulse width for the input capture input is greater than two bus clocks. An input capture on channel x sets the CxF ﬂag. The CxI bit enables the CxF ﬂag to generate interrupt requests. Timer module or Pulse Accumulator must stay enabled (TEN bit of TSCR1 or PAEN bit of PACTL register must be set to one) while clearing CxF (writing one to CxF).

20.4.3 Output Compare

Setting the I/O select bit, IOSx, conﬁgures channel x when available as an output compare channel. The output compare function can generate a periodic pulse with a programmable polarity, duration, and frequency. When the timer counter reaches the value in the channel registers of an output compare channel, the timer can set, clear, or toggle the channel pin if the corresponding OCPDx bit is set to zero. An output compare on channel x sets the CxF ﬂag. The CxI bit enables the CxF ﬂag to generate interrupt requests. Timer module or Pulse Accumulator must stay enabled (TEN bit of TSCR1 or PAEN bit of PACTL register must be set to one) while clearing CxF (writing one to CxF). The output mode and level bits, OMx and OLx, select set, clear, toggle on output compare. Clearing both OMx and OLx results in no output compare action on the output compare channel pin. Setting a force output compare bit, FOCx, causes an output compare on channel x. A forced output compare does not set the channel ﬂag. The following channel 7 feature is available only when channel 7 exists. A channel 7 event, which can be a counter overﬂow when TTOV[7] is set or a successful output compare on channel 7, overrides output compares on all other output compare channels. The output compare 7 mask register masks the bits in the output compare 7 data register. The timer counter reset enable bit, TCRE, enables channel 7 output compares to reset the timer counter. A channel 7 output compare can reset the timer counter even if the IOC7 pin is being used as the pulse accumulator input.

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Writing to the timer port bit of an output compare pin does not affect the pin state. The value written is stored in an internal latch. When the pin becomes available for general-purpose output, the last value written to the bit appears at the pin. When TCRE is set and TC7 is not equal to 0, then TCNT will cycle from 0 to TC7. When TCNT reaches TC7 value, it will last only one bus cycle then reset to 0. Note: in Figure 20-31,if PR[2:0] is equal to 0, one prescaler counter equal to one bus clock Figure 20-31. The TCNT cycle diagram under TCRE=1 condition

20.4.3.1 OC Channel Initialization

The internal register whose output drives OCx can be programmed before the timer drives OCx. The desired state can be programmed to this internal register by writing a one to CFORCx bit with TIOSx, OCPDx and TEN bits set to one. Set OCx: Write a 1 to FOCx while TEN=1, IOSx=1, OMx=1, OLx=1 and OCPDx=1 Clear OCx: Write a 1 to FOCx while TEN=1, IOSx=1, OMx=1, OLx=0 and OCPDx=1 Setting OCPDx to zero allows the internal register to drive the programmed state to OCx. This allows a glitch free switch over of port from general purpose I/O to timer output once the OCPDx bit is set to zero.

20.4.4 Pulse Accumulator

The following Pulse Accumulator feature is available only when channel 7 exists. The pulse accumulator (PACNT) is a 16-bit counter that can operate in two modes: Event counter mode — Counting edges of selected polarity on the pulse accumulator input pin, PAI. Gated time accumulation mode — Counting pulses from a divide-by-64 clock. The PAMOD bit selects the mode of operation. The minimum pulse width for the PAI input is greater than two bus clocks. TC7 0 1 ----- TC7-1 TC7 0 TC7 event TC7 event prescaler counter 1 bus clock

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20.4.5 Event Counter Mode

Clearing the PAMOD bit conﬁgures the PACNT for event counter operation. An active edge on the IOC7 pin increments the pulse accumulator counter. The PEDGE bit selects falling edges or rising edges to increment the count. NOTE The PACNT input and timer channel 7 use the same pin IOC7. To use the IOC7, disconnect it from the output logic by clearing the channel 7 output mode and output level bits, OM7 and OL7. Also clear the channel 7 output compare 7 mask bit, OC7M7. The Pulse Accumulator counter register reﬂect the number of active input edges on the PACNT input pin since the last reset. The PAOVF bit is set when the accumulator rolls over from 0xFFFF to 0x0000. The pulse accumulator overﬂow interrupt enable bit, PAOVI, enables the PAOVF ﬂag to generate interrupt requests. NOTE The pulse accumulator counter can operate in event counter mode even when the timer enable bit, TEN, is clear.

20.4.6 Gated Time Accumulation Mode

Setting the PAMOD bit conﬁgures the pulse accumulator for gated time accumulation operation. An active level on the PACNT input pin enables a divided-by-64 clock to drive the pulse accumulator. The PEDGE bit selects low levels or high levels to enable the divided-by-64 clock. The trailing edge of the active level at the IOC7 pin sets the PAIF. The PAI bit enables the PAIF ﬂag to generate interrupt requests. The pulse accumulator counter register reﬂect the number of pulses from the divided-by-64 clock since the last reset. NOTE The timer prescaler generates the divided-by-64 clock. If the timer is not active, there is no divided-by-64 clock.

20.5 Resets

The reset state of each individual bit is listed withinSection 20.3, “Memory Map and Register Deﬁnition” which details the registers and their bit ﬁelds.

20.6 Interrupts

This section describes interrupts originated by the TIM16B8CV3 block. Table 20-25 lists the interrupts generated by the TIM16B8CV3 to communicate with the MCU.

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The TIM16B8CV3 could use up to 11 interrupt vectors. The interrupt vector offsets and interrupt numbers are chip dependent.

20.6.1 Channel [7:0] Interrupt (C[7:0]F)

This active high outputs will be asserted by the module to request a timer channel 7 – 0 interrupt. The TIM block only generates the interrupt and does not service it. Only bits related to implemented channels are valid.

20.6.2 Pulse Accumulator Input Interrupt (PAOVI)

This interrupt is available only when channel 7 exists. This active high output will be asserted by the module to request a timer pulse accumulator input interrupt. The TIM block only generates the interrupt and does not service it.

20.6.3 Pulse Accumulator Overﬂow Interrupt (PAOVF)

This interrupt is available only when channel 7 exists. This active high output will be asserted by the module to request a timer pulse accumulator overﬂow interrupt. The TIM block only generates the interrupt and does not service it.

20.6.4 Timer Overﬂow Interrupt (TOF)

This active high output will be asserted by the module to request a timer overﬂow interrupt. The TIM block only generates the interrupt and does not service it. Table 20-25. TIM16B8CV1 Interrupts Interrupt Offset 1 1 Chip Dependent. 2 This feature is available only when channel 7 exists.

3 Bits related to available channels have functional signiﬁcance

Vector1 Priority1 Source Description C[7:0]F3 — — — Timer Channel 7–0 Active high timer channel interrupts 7–0 PAOVI2 — — — Pulse Accumulator Input Active high pulse accumulator input interrupt PAOVF2 — — — Pulse Accumulator Overﬂow Pulse accumulator overﬂow interrupt TOF — — — Timer Overﬂow Timer Overﬂow interrupt

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21.1 Introduction

The FTMRG16K1 module implements the following:

16Kbytes of P-Flash (Program Flash) memory
512 bytes of EEPROM memory The Flash memory is ideal for single-supply applications allowing for ﬁeld reprogramming without requiring external high voltage sources for program or erase operations. The Flash module includes a memory controller that executes commands to modify Flash memory contents. The user interface to the memory controller consists of the indexed Flash Common Command Object (FCCOB) register which is written to with the command, global address, data, and any required command parameters. The memory controller must complete the execution of a command before the FCCOB register can be written to with a new command. CAUTION A Flash word or phrase must be in the erased state before being programmed. Cumulative programming of bits within a Flash word or phrase is not allowed. Table 21-1. Revision History Revision Number Revision Date Sections Affected Description of Changes V01.04 17 Jun 2010 21.4.6.1/21-685 21.4.6.2/21-686 21.4.6.3/21-686 21.4.6.14/21-69 Clarify Erase Verify Commands Descriptions related to the bits MGSTAT[1:0] of the register FSTAT. V01.05 20 aug 2010 21.4.6.2/21-686 21.4.6.12/21-69 21.4.6.13/21-69 Updated description of the commands RD1BLK, MLOADU and MLOADF

MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 656 The Flash memory may be read as bytes and aligned words. Read access time is one bus cycle for bytes and aligned words. For misaligned words access, the CPU has to perform twice the byte read access command. For Flash memory, an erased bit reads 1 and a programmed bit reads 0. It is possible to read from P-Flash memory while some commands are executing on EEPROM memory. It is not possible to read from EEPROM memory while a command is executing on P-Flash memory. Simultaneous P-Flash and EEPROM operations are discussed in Section 21.4.5. Both P-Flash and EEPROM memories are implemented with Error Correction Codes (ECC) that can resolve single bit faults and detect double bit faults. For P-Flash memory, the ECC implementation requires that programming be done on an aligned 8 byte basis (a Flash phrase). Since P-Flash memory is always read by half-phrase, only one single bit fault in an aligned 4 byte half-phrase containing the byte or word accessed will be corrected.

21.1.1 Glossary

Command Write Sequence — An MCU instruction sequence to execute built-in algorithms (including program and erase) on the Flash memory. EEPROM Memory — The EEPROM memory constitutes the nonvolatile memory store for data. EEPROM Sector — The EEPROM sector is the smallest portion of the EEPROM memory that can be erased. The EEPROM sector consists of 4 bytes. NVM Command Mode— An NVM mode using the CPU to setup the FCCOB register to pass parameters required for Flash command execution. Phrase — An aligned group of four 16-bit words within the P-Flash memory. Each phrase includes two sets of aligned double words with each set including 7 ECC bits for single bit fault correction and double bit fault detection within each double word. P-Flash Memory — The P-Flash memory constitutes the main nonvolatile memory store for applications. P-Flash Sector — The P-Flash sector is the smallest portion of the P-Flash memory that can be erased. Each P-Flash sector contains 512 bytes. Program IFR — Nonvolatile information register located in the P-Flash block that contains the Version ID, and the Program Once ﬁeld.

21.1.2 Features

21.1.2.1 P-Flash Features

16 Kbytes of P-Flash memory composed of one 16 Kbyte Flash block divided into 32 sectors of 512 bytes

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Single bit fault correction and double bit fault detection within a 32-bit double word during read operations
Automated program and erase algorithm with verify and generation of ECC parity bits
Fast sector erase and phrase program operation
Ability to read the P-Flash memory while programming a word in the EEPROM memory
Flexible protection scheme to prevent accidental program or erase of P-Flash memory

21.1.2.2 EEPROM Features

512 bytes of EEPROM memory composed of one 512 byte Flash block divided into 128 sectors of 4 bytes
Single bit fault correction and double bit fault detection within a word during read operations
Automated program and erase algorithm with verify and generation of ECC parity bits
Fast sector erase and word program operation
Protection scheme to prevent accidental program or erase of EEPROM memory
Ability to program up to four words in a burst sequence

21.1.2.3 Other Flash Module Features

No external high-voltage power supply required for Flash memory program and erase operations
Interrupt generation on Flash command completion and Flash error detection
Security mechanism to prevent unauthorized access to the Flash memory

21.1.3 Block Diagram

The block diagram of the Flash module is shown in Figure 21-1.

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Figure 21-1. FTMRG16K1 Block Diagram

21.2 External Signal Description

The Flash module contains no signals that connect off-chip. Bus Clock Divider Clock Command Interrupt Request FCLK Protection Security Registers Flash Interface 16bit internal bus sector 0 sector 1 sector 31 4Kx39 P-Flash Error Interrupt Request CPU 256x22 sector 0 sector 1 sector 127 EEPROM Memory Controller

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21.3 Memory Map and Registers

This section describes the memory map and registers for the Flash module. Read data from unimplemented memory space in the Flash module is undeﬁned. Write access to unimplemented or reserved memory space in the Flash module will be ignored by the Flash module. CAUTION Writing to the Flash registers while a Flash command is executing (that is indicated when the value of ﬂag CCIF reads as ’0’) is not allowed. If such action is attempted the write operation will not change the register value. Writing to the Flash registers is allowed when the Flash is not busy executing commands (CCIF = 1) and during initialization right after reset, despite the value of ﬂag CCIF in that case (refer to Section 21.6 for a complete description of the reset sequence).

21.3.1 Module Memory Map

The S12 architecture places the P-Flash memory between global addresses 0x3_C000 and 0x3_FFFF as shown in Table 21-3.The P-Flash memory map is shown in Figure 21-2. Table 21-2. FTMRG Memory Map Global Address (in Bytes) Size (Bytes) Description 0x0_0000 - 0x0_03FF 1,024 Register Space 0x0_0400 – 0x0_05FF 512 EEPROM Memory 0x0_0600 – 0x0_07FF 512 FTMRG reserved area 0x0_4000 – 0x0_7FFF 16,284 NVMRES 1=1 : NVM Resource area (see Figure 21-3) 1 See NVMRES description in Section 21.4.3 0x3_8000 – 0x3_BFFF 16,384 FTMRG reserved area 0x3_C000 – 0x3_FFFF 16,384 P-Flash Memory Table 21-3. P-Flash Memory Addressing Global Address Size (Bytes) Description 0x3_C000 – 0x3_FFFF 16 K P-Flash Block Contains Flash Conﬁguration Field (see Table 21-4)

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The FPROT register, described inSection 21.3.2.9, can be set to protect regions in the Flash memory from accidental program or erase. Two separate memory regions, one growing downward from global address 0x3_FFFF in the Flash memory (called the higher region), and the remaining addresses in the Flash memory, can be activated for protection. The Flash memory addresses covered by these protectable regions are shown in the P-Flash memory map. The higher address region is mainly targeted to hold the boot loader code since it covers the vector space. Default protection settings as well as security information that allows the MCU to restrict access to the Flash module are stored in the Flash conﬁguration ﬁeld as described in Table 21-4. Figure 21-2. P-Flash Memory Map Table 21-4. Flash Conﬁguration Field Global Address Size (Bytes) Description 0x3_FF00-0x3_FF07 8 Backdoor Comparison Key Refer to Section 21.4.6.11, “Verify Backdoor Access Key Command,” and Section 21.5.1, “Unsecuring the MCU using Backdoor Key Access” 0x3_FF08-0x3_FF0B1 1 0x3FF08-0x3_FF0F form a Flash phrase and must be programmed in a single command write sequence. Each byte in the 0x3_FF08 - 0x3_FF0B reserved ﬁeld should be programmed to 0xFF.

4 Reserved

0x3_FF0C1 1 P-Flash Protection byte. Refer to Section 21.3.2.9, “P-Flash Protection Register (FPROT)” 0x3_FF0D1 1 EEPROM Protection byte. Refer to Section 21.3.2.10, “EEPROM Protection Register (EEPROT)” 0x3_FF0E1 1 Flash Nonvolatile byte Refer to Section 21.3.2.16, “Flash Option Register (FOPT)” 0x3_FF0F1 1 Flash Security byte Refer to Section 21.3.2.2, “Flash Security Register (FSEC)” Flash Conﬁguration Field P-Flash START = 0x3_C000 P-Flash END = 0x3_FFFF 0x3_F800 0x3_F000 0x3_E000 Flash Protected/Unprotected Higher Region 2, 4, 8, 16 Kbytes 16 bytes (0x3_FF00 - 0x3_FF0F) Protection Protection Movable End Fixed End

MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 661 Table 21-5. Program IFR Fields Global Address Size (Bytes) Field Description 0x0_4000 – 0x0_4007 8 Reserved 0x0_4008 – 0x0_40B5 174 Reserved 0x0_40B6 – 0x0_40B7 2 Version ID 1 1 Used to track ﬁrmware patch versions, see Section 21.4.2 0x0_40B8 – 0x0_40BF 8 Reserved 0x0_40C0 – 0x0_40FF 64 Program Once Field Refer to Section 21.4.6.6, “Program Once Command” Table 21-6. Memory Controller Resource Fields (NVMRES1=1) 1 NVMRES - See Section 21.4.3 for NVMRES (NVM Resource) detail. Global Address Size (Bytes) Description 0x0_4000 – 0x040FF 256 P-Flash IFR (see Table 21-5) 0x0_4100 – 0x0_41FF 256 Reserved. 0x0_4200 – 0x0_57FF Reserved 0x0_5800 – 0x0_59FF 512 Reserved 0x0_5A00 – 0x0_5FFF 1,536 Reserved 0x0_6000 – 0x0_6BFF 3,072 Reserved 0x0_6C00 – 0x0_7FFF 5,120 Reserved

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Figure 21-3. Memory Controller Resource Memory Map (NVMRES=1)

21.3.2 Register Descriptions

The Flash module contains a set of 20 control and status registers located between Flash module base + 0x0000 and 0x0013. In the case of the writable registers, the write accesses are forbidden during Fash command execution (for more detail, see Caution note in Section 21.3). A summary of the Flash module registers is given in Figure 21-4 with detailed descriptions in the following subsections. Address & Name 76543210 0x0000 FCLKDIV R FDIVLD FDIVLCK FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIV0 W 0x0001 FSEC R KEYEN1 KEYEN0 RNV5 RNV4 RNV3 RNV2 SEC1 SEC0 W 0x0002 FCCOBIX R0 0 0 0 0 CCOBIX2 CCOBIX1 CCOBIX0 W Figure 21-4. FTMRG16K1 Register Summary P-Flash IFR 1 Kbyte (NVMRES=1) 0x0_4000 RAM End = 0x0_59FF RAM Start = 0x0_5800 Reserved 5120 bytes Reserved 4608 bytes 0x0_6C00 0x0_7FFF 0x0_4400 Reserved 5k bytes Reserved 512 bytes

MC9S12G Family Reference Manual, Rev.1.10 Freescale Semiconductor 663 0x0003 FRSV0 R 00000000 W 0x0004 FCNFG R CCIE IGNSF FDFD FSFD W 0x0005 FERCNFG R0 0 0 0 0 0 DFDIE SFDIE W 0x0006 FSTAT R CCIF ACCERR FPVIOL MGBUSY RSVD MGSTAT1 MGSTAT0 W 0x0007 FERSTAT R0 0 0 0 0 0 DFDIF SFDIF W 0x0008 FPROT R FPOPEN RNV6 FPHDIS FPHS1 FPHS0 RNV2 RNV1 RNV0 W 0x0009 EEPROT R DPOPEN DPS4 DPS3 DPS2 DPS1 DPS0 W 0x000A FCCOBHI R CCOB15 CCOB14 CCOB13 CCOB12 CCOB11 CCOB10 CCOB9 CCOB8 W 0x000B FCCOBLO R CCOB7 CCOB6 CCOB5 CCOB4 CCOB3 CCOB2 CCOB1 CCOB0 W 0x000C FRSV1 R 00000000 W 0x000D FRSV2 R 00000000 W 0x000E FRSV3 R 00000000 W 0x000F FRSV4 R 00000000 W 0x0010 FOPT R NV7 NV6 NV5 NV4 NV3 NV2 NV1 NV0 W Address & Name 76543210 Figure 21-4. FTMRG16K1 Register Summary (continued)

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21.3.2.1 Flash Clock Divider Register (FCLKDIV)

The FCLKDIV register is used to control timed events in program and erase algorithms. All bits in the FCLKDIV register are readable, bit 7 is not writable, bit 6 is write-once-hi and controls the writability of the FDIV ﬁeld in normal mode. In special mode, bits 6-0 are writable any number of times but bit 7 remains unwritable. CAUTION The FCLKDIV register should never be written while a Flash command is executing (CCIF=0). 0x0011 FRSV5 R 00000000 W 0x0012 FRSV6 R 00000000 W 0x0013 FRSV7 R 00000000 W = Unimplemented or Reserved Offset Module Base + 0x0000 76543210 R FDIVLD FDIVLCK FDIV[5:0] W Reset 00000000 = Unimplemented or Reserved Figure 21-5. Flash Clock Divider Register (FCLKDIV) Table 21-7. FCLKDIV Field Descriptions Field Description FDIVLD Clock Divider Loaded

0 FCLKDIV register has not been written since the last reset

1 FCLKDIV register has been written since the last reset

& Name 76543210 Figure 21-4. FTMRG16K1 Register Summary (continued)

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21.3.2.2 Flash Security Register (FSEC)

The FSEC register holds all bits associated with the security of the MCU and Flash module. FDIVLCK Clock Divider Locked

0 FDIV ﬁeld is open for writing

1 FDIV value is locked and cannot be changed. Once the lock bit is set high, only reset can clear this bit and restore writability to the FDIV ﬁeld in normal mode. 5–0 FDIV[5:0] Clock Divider Bits— FDIV[5:0] must be set to effectively divide BUSCLK down to 1 MHz to control timed events during Flash program and erase algorithms.Table 21-8shows recommended values for FDIV[5:0] based on the BUSCLK frequency. Please refer to Section 21.4.4, “Flash Command Operations,” for more information. Table 21-8. FDIV values for various BUSCLK Frequencies BUSCLK Frequency (MHz) FDIV[5:0] BUSCLK Frequency (MHz) FDIV[5:0] MIN1 1 BUSCLK is Greater Than this value. MAX2 2 BUSCLK is Less Than or Equal to this value. MIN1 MAX2 1.0 1.6 0x00 16.6 17.6 0x10 1.6 2.6 0x01 17.6 18.6 0x11 2.6 3.6 0x02 18.6 19.6 0x12 3.6 4.6 0x03 19.6 20.6 0x13 4.6 5.6 0x04 20.6 21.6 0x14 5.6 6.6 0x05 21.6 22.6 0x15 6.6 7.6 0x06 22.6 23.6 0x16 7.6 8.6 0x07 23.6 24.6 0x17 8.6 9.6 0x08 24.6 25.6 0x18 9.6 10.6 0x09 10.6 11.6 0x0A 11.6 12.6 0x0B 12.6 13.6 0x0C 13.6 14.6 0x0D 14.6 15.6 0x0E 15.6 16.6 0x0F Table 21-7. FCLKDIV Field Descriptions (continued) Field Description

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