MC34830 FREESCALE | Alldatasheet
Document overview
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- PDF pages: 22
Technical content
Features
- 1080p / UXGA to 480i / VGA video buffer with 6dB gain
- Integrated input clamp
- Adjustable BW to save power
- Handles CV, Y, C, Pb, Pr, R, G, B signals
- Drives two video loads
- Single supply operation
- 3.0 to 5.5V range
- Rail to rail output
- 0.3% dG / 0.3% d θ for SD
- 0.6% THD for HD
- 0 . 1 2μA shutdown current
- Ultra thin UDFN package
- Pb-free packaging designated by suffix code EP
Applications
- Cellular phones
- DVD players
- Portable Game Players, Set-top boxes
- Laptop PCs, Desktop PCs,
- Projectors, Digital Came ras, Camcorders, Portable Media Players, Security Systems
Figure 1. 34830 Simplified Application Diagram
ORDERING INFORMATION
Range (TA) Package PC34830EP/R2 -40°C to 85°C 6-UDFN Bottom View 34830 VCC IN ENABLE OUT RFREQ GND Video cable
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Figure 2. 34830 Simplified Internal Block Diagram
Figure 3. 34830 Pin Connections Table 1. 34830 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 10.
1 VCC Power VCC Supply voltage input
2 IN Input Video Input Video Input
3 GND Ground Ground Ground return for the IC
4 RFREQ Passive Frequency Bandwidth
5 OUT Output Video Output Video output
6 EN Input Enable Low = device disabled; High = device enabled
floating. The EP is electrically connected to ground.
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ELECTRICAL CHARACTERISTICS
Table 2. Maximum Ratings permanent damage to the device.
- ESD testing is performed in accordanc e with the Human Body Model (HBM) (CZAP = 100pF, RZAP = 1500Ω), the Machine Model (MM)
(CZAP = 200pF, RZAP = 0Ω), and the Charge Device Model (CDM), Robotic (CZAP = 4.0pF).
- Pin soldering temperature limit is for 10 seconds maximum dur ation. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
- Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
Analog Integrated Circuit Device Data Freescale Semiconductor 5 34830 STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics = 5.0pF. Typical values are at TA = 27°C, unless otherwise noted.
- Referenced to input. Input clamp not active for signals C, P b, Pr, U, and V.
- Establishes output sync level.
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DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS ELECTRICAL PERFORMANCE CURVES Plots are taken under conditions VCC = 4.0V, RFREQ = 9.0kΩ, RL =150Ω, TA = 27°C, unless otherwise noted. Figure 4. Frequency Response Magnitude Figure 5. -1dB Bandwidth vs. RFREQ (kΩ) Table 4. Dynamic Electrical Characteristics = 5.0pF. Typical values are at TA = 27°C, unless otherwise noted.
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ELECTRICAL PERFORMANCE CURVES Figure 12. 480i Signal (RFREQ = 108kΩ) Figure 13. 480i 2T and Modulated 12.5T Response Figure 14. 480i Vertical/Horizontal Sync Levels (RFREQ = Figure 15. 1080i Signal Figure 16. 1080i 2T Response Figure 17. 1080i Vertical/Horizontal Sync Levels
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FUNCTIONAL PIN DESCRIPTION FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION VCC VCC is the power input terminal for the IC. A 0.1μF bypass capacitor in series with a 4.7Ω resistor to ground should be connected as close as possible to this pin to provide noise immunity. IN IN is the video signal input terminal. GND GND is the ground terminal for the IC. RFREQ The operating bandwidth of the IC is set by the value of the resistor between this terminal and ground. By selecting a value for the RFREQ resistor between 9.0kΩ and 108kΩ,the bandwidth can be set for video applications ranging from 1080p to 480i. OUT OUT is the video signal output terminal. EN EN is a logic level enable input for the IC. EN = 1 turns the IC on, and EN = 0 turns it off.
Figure 22. Functional Internal Block Diagram we can adjust the channel bandwidth. based on the state of the enable input (EN).
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FUNCTIONAL DEVICE OPERATION FUNCTIONAL INTERNAL BLOCK DESCRIPTION FUNCTIONAL DEVICE OPERATION INTRODUCTION The 34830 is a very high performance video buffer designed for high-definition (HD) video applications. The device features an innovative adjustable bandwidth circuitry that allows the user to set the bandwidth of the device through an external resistor connected to RFREQ. This feature allows the 34830 to fit in a variety of video applications giving it the flexibility to reduce power consumption when full bandwidth is not required. In this way the 34830 can support all video bandwidths, from standard definition (SD) to high definition (HD), including the 1080i as well as 1080p formats. The 34830 also features an internal input clamp that works with all sync formats and types of video signals. The clamp can work in three different modes and allows both AC- and DC-coupled input signals. The 34830 is optimized to drive a single standard video load while maintaining exceptional performance characteristics. Two video loads can also be supported by the device with a minimum tradeoff in performance specifications. The 34830 supports both AC- and DC- coupled outputs. The 34830 can be disabled with an ultra-low current consumption of 0.12μA, by driving the EN input to ground. The 34830 operates using a single supply from 3V to 5.5V, and is designed to work in the extended temperature range from -40°C to 85°C. The device is offered in a small UDFN package ideal to fit into space-critical applications. The signal path of the 34830 begins with the input clamp that DC-restores the input. The signal is then shifted up by a level shifter which brings it to the appropriate levels required for the output buffer. The level shifter also provides isolation between the very sensitive input clamp circuit and the input stage of the output buffer. The signal is then channeled to the output buffer which amplifies it with a gain of two and drives the output loads. Both the level shifter and output buffer blocks are biased through the bandwidth adjust circuitry which allows the user to set the bandwidth and quiescent power consumption according to the application at hand. INPUT CLAMP The function of the input clamp is to set the DC level of the signal at the input. The clamp can be operated in three modes. Sync Tip Clamp The clamp works in this mode for Y,CV, R, G, and B signals that are AC-coupled to the 34830. In this mode, the clamp senses the most negative level of the input signal and clamps it to ground. The clamp circuit does this by injecting current into the AC-coupling capacitor to make the voltage at the input rise. The current is disabled once the voltage has risen to the appropriate level. The clamp circuitry includes a small (2.0μA) pull-down current to guarantee operation of the clamp. Key Clamp The clamp works in this mode for C, Pb, Pr, U, and V signals that are AC-coupled to the 34830 while DC bias is set externally. In this configuration, ensure that the DC bias at the input is such that the most negative level of the signal never goes below 50mV, to avoid interference with the clamp. The DC bias at the input can be set through a resistive voltage divider after the AC-coupling capacitor ( Figure 23). In order to maximize the input signal swing, it is recommended to set the input DC bias to 0.5V. This will also maximize the swing at the output of the 34830. Transparent Clamp The clamp works in this mode for all DC-biased signals. Ensure that the most negative level of the signal is above 50mV from ground. If this requirement is not met, the signal source and clamp both try to set the level at the input, resulting in signal distortion. The input clamp becomes transparent for signals above 50mV and the signal passes through unaffected. BIAS CIRCUITRY The bias circuit sets the operating bias for 34830’s internal blocks. It includes a bandgap voltage reference, a PTAT current generator, as well as a constant current generator. These reference currents and voltages are then distributed to 34830’s internal blocks to set their respective operating points. BANDWIDTH ADJUST The 34830 features a bandwidth adjust circuit that sets the bandwidth of the channel by adjusting quiescent supply current. It consists of a PTAT current generator whose current varies with the value of an external resistor (R FREQ). This PTAT current is used to set the operating bias for the level shifter and output buffer blocks. Increasing the external resistor (R FREQ) lowers the bias current, and hence reduces both supply current and bandwidth. Decreasing the value of R FREQ increases both supply current and bandwidth. Select a value for RFREQ in the range between 9kΩ and 108kΩ, to set the bandwidth between the upper and lower limits. Refer to Figure 5. LEVEL-SHIFTER After passing through the input clamp, which restores its DC level to a known value, the signal is level-shifted up by 250mV. The level-shifting operation is done for two reasons. The first is to isolate the input of the output buffer from the sensitive clamp circuitry to prevent distortion. In this sense,
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FUNCTIONAL DEVICE OPERATION FUNCTIONAL INTERNAL BLOCK DESCRIPTION INPUT CONSIDERATIONS As explained in the Input Clamp section, the 34830 features an internal clamp that allows the device to work with both AC as well as DC-coupled input signals. To AC-couple the input signal, use a 0.1μF capacitor following the video signal source. If the signal being AC-coupled has sync, then the 34830’s clamp circuit ensures that the sync tip is detected and positioned near ground (Sync Tip Clamp). If the signal that is being AC-coupled does not have sync (Key Clamp), care must be taken to ensure that its most negative portions are not confused as being sync tips and clamped, resulting in signal distortion. In order to prevent this from happening, the user must set the DC bias at the input correctly. See the SETTING KEY CLAMP BIAS section. When the input to the 34830 goes above 50mV, the clamp circuit becomes transparent and does not have any effect on the signal being passed. This allows the 34830 to work with DC-coupled signals. To DC-couple the input signal, simply connect the video source directly to the input of the 34830. OUTPUT CONISDERATIONS The relationship between input and output for the 34830 follows the equation: Where the 250mV term is the offset provided by the internal level shifter. The 100mV term that is added to the equation represents the worst case errors and offsets that can be expected from the signal path, due to process and temperature variations. The 34830 has been optimized to drive a single standard video load. A standard video load typically consists of a 75Ω back-termination resistor, followed by a matched video cable and a 75Ω load resistor. The 34830 can drive up to 5pF of load capacitance in parallel with the video cable and load resistor. Two video loads can be supported by the 34830 with a minimum tradeoff in performance parameters. The output of the 34830 can be both AC or DC-coupled. When the output is AC-coupled the AC-coupling capacitor forms a high-pass filter with the load resistor. Ensure that the value of the AC-coupling capacitor is such that the lowest frequencies of the video signal are passed without attenuation from this filter. A typical value for the output AC- coupling capacitor is 220μF. Place the output termination resistor as close to the output as possible to minimize parasitic inductance and capacitance effects that tend to deteriorate signal quality. VOUT 2V IN 250mV+()× 100mV±=
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Figure 27. 34830 Evaluation Board Schematic Table 5. 34830 Bill of Material
- Minimize all trace inductances by reducing trace
- Make sure that a solid ground plane is available and
- Avoid traces with 90 degree bends.
- Use a 0.1 μF bypass capacitor in series with a 4.7Ω
connected to the external world.
- Try to refer all ground connections to the same point as
middle point of the ground plane. 34830 package are not violated in the application at hand. The 34830 comes in a package with an exposed pad (EP). tables. While Freescale offers component recommendations in this configuration, it is the customer’s responsibility to validate their application.
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For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below. EP SUFFIX (PB-FREE) 6-PIN 98ASA10819D ISSUE A
Analog Integrated Circuit Device Data Freescale Semiconductor 19 34830 PACKAGING PACKAGE DIMENSIONS EP SUFFIX (PB-FREE) 6-PIN 98ASA10819D ISSUE A
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EP SUFFIX (PB-FREE) 6-PIN 98ASA10819D ISSUE A
Analog Integrated Circuit Device Data Freescale Semiconductor 21 34830
REVISION HISTORY
REVISION DATE DESCRIPTION OF CHANGES 1.0 9/2008 • Initial Release
Rev. 1.0 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc., 2008. All rights reserved. How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516
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