PC34709VK

MC34709 FREESCALE | Alldatasheet

Document overview

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Technical content

Features

• Five buck converters configurable to provide up to six independent outputs for direct supply of the processor core, memory, and peripherals.
• Boost regulator for USB PHY domain on i.MX processors.
• Seven LDO regulators with internal and external pass devices for thermal budget optimization
• One low current, high accuracy, voltage reference for DDR memory
• 10-bit ADC for monitoring battery and other inputs
• Real time clock and crystal oscillator circuitry with a coin cell backup/charger
• SPI/I 2C bus for control and register interface
• Four general purpose low-voltage I/Os with interrupt capability
• Two PWM outputs

Figure 1. Simplified Application Diagram

Applications

Human Machine Interfaces (HMI) VK SUFFIX (PB-FREE) 98ASA00333D

130 MAPBGA

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Analog Integrated Circuit Device Data Freescale Semiconductor 2 34709 Table of Contents

Analog Integrated Circuit Device Data

3 Freescale Semiconductor

1 Orderable Parts

a part number search for the following device numbers. Table 1. Orderable Part Variations

1. To Order parts in Tape & Reel, add the R2 suffix to the part number.

Analog Integrated Circuit Device Data

5 Freescale Semiconductor

2 Part Identification

This section provides an explanation of the part numbers and their alpha numeric breakdown.

2.1 Description

Part numbers for the chips have fields that identify the specific part configuration. You can use the values of these fields to determine the specific part you have received.

2.2 Format and Examples

Part numbers for a given device have the following format, followed by a device example: Table 2 - Part Numbering - Analog: PC tt xxx r v PPP RR - PC34709VKR2

2.3 Fields

These tables list the possible values for each field in the part number (not all combinations are valid). Table 2: Part Numbering - Analog FIELD DESCRIPTION VALUES PC Product Category • MC- Qualified Standard

• PC- Prototype Device tt Temperature Range
• 33 = -40 °C to > 105 °C
• 34 = -40 °C to  105 °C
• 35 = -55 °C to  125 °C xxx Product Number • Assigned by Marketing r Revision • (default blank) v Variation • (default blank) RR Tape and Reel Indicator • R2 = 13 inch reel hub size

3 Internal Block Diagram

3.1 Simplified Internal Diagram

Figure 2. Simplified Internal Block Diagram

10 Bit GP

32 KHz

7 Freescale Semiconductor

4 Pin Connections

4.1 Pinout Diagram

Figure 3. Top View Ballmap

4.2 Pin Definitions

Table 3. Pin Definitions

1. Input supply to the IC core circuitry

9 Freescale Semiconductor

1. VUSB2 input using internal PMOS FET
2. VGEN2 input using internal PMOS FET

Table 3. Pin Definitions (continued)

11 Freescale Semiconductor

5 General Product Characteristics

5.1 Maximum Ratings

5.2 Thermal Characteristics

Table 4. Maximum Ratings

• Human Body Model All pins
• Charge Device Model All pins 2000 500 V (2) (2) Notes 2. ESD testing is performed in accordanc e with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 ), and the Charge Device Model (CDM), Robotic (CZAP = 4.0 pF).

Table 5. Thermal Ratings

• Single layer board (1s) - 93 °C/W (5), (6) RθJMA Junction to Ambient Natural Convection
• Four layer board (2s2p) - 53 °C/W (5), (7) RθJMA Junction to Ambient (@200 ft/min.)
• Single layer board (1s) - 80 °C/W (5), (7) RθJMA Junction to Ambient (@200 ft/min.)
• Four layer board (2s2p) - 49 °C/W (5), (7) RθJB Junction to Board - 34 °C/W (8) RθJC Junction to Case - 25 °C/W (9)

13 Freescale Semiconductor

5.2.1 Power Dissipation

ADC for specific temperature readouts, see Serial Interfaces. determined by reading the THERMxxxS bits. the sense bit assignment are listed in Table 6.

• Natural Convection - 6.0 °C/W (10) Notes 3. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause a malfunction or permanent damage to the device. 4. Freescale's Package Reflow capability m eets the Pb-free requirements for JEDEC standard J-STD-020C, for Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL). 5. Junction temperature is a function of on- chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 6. Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification. 7. Per JEDEC JESD51-6 with the board horizontal. 8. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 9. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 10. Thermal characterization parameter indicating the temperat ure difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.

Table 6. Thermal Protection Thresholds

1. Equivalent to approx. 30 mW min, 60 mW max

Table 5. Thermal Ratings (continued)

5.3 Electrical Characteristics

5.3.1 General PMIC Specifications

Table 7. General Electrical Characteristic

15 Freescale Semiconductor

1. SPIVCC is typically connected to the output of buck regulator SW5 and set to 1.800 V
2. Input has internal pull-up to VCOREDIG equivalent to 200 kOhm
3. Input state is latched in first phase of cold start, refer to Serial Interfaces for a description of the PUMS configuration
4. Input state is not latched
5. A weak pull-down represents a nominal internal pull-down of 100 nA, unless otherwise noted
6. RESETB, RESETBMCU, SDWNB, SW1PWGD, SW2PWGD have open-drain outputs, external pull-ups are required
7. SPIVCC needs to remain enabled for proper detec tion of WDI High to avoid involuntary shutdown
8. The maximum should never exceed the ma ximum rating of the pin as given in Pin Connections
9. The weak pull-down on CS is disabled if a VIH is detected at start-up to avoid extra consumption in I2C mode
10. The output drive strength is programmable

5.3.2 Current Consumption

table follows for standard use cases. Table 8. Current Consumption Summary (24) and TA = 25 °C under nominal conditions, unless otherwise noted.

• RTC Logic
• VCORE Module
• VSRTC
• 3 2 k Oscillator
• Clk32KMCU buffer active(10 pF load) 4.0 7.0 A OFF (good battery) All blocks disabled, BP>3.0 V(at 25 °C only)
• D i g i t a l C o r e
• RTC Logic
• VCORE Module
• VSRTC
• 3 2 k Oscillator
• CLK32KMCU buffer active (10 pF load)
• COINCHEN = 0 20 55 A ON Standby Low-power Mode (Standby pin asserted and ON_STBY_LP=1)
• D i g i t a l c o r e
• RTC logic
• VCORE module
• VSRTC
• CLK32KMCU/CLK32K active (10 pF load)
• 3 2 k oscillator
• I REF
• SW1, SW2, SW3, SW4A, SW4B, SW5 in PFM (23),(27)
• VDDREF, VPLL, VGEN1, VGEN2, VUSB2, VDAC in low-power mode (22),(25) 260 650 A ON Standby
• D i g i t a l c o r e
• RTC logic
• VCORE module
• VSRTC
• CLK32KMCU/CLK32K active (10 pF load)
• 3 2 k oscillator
• D i g i t a l
• I REF
• SW1, SW2, SW3, SW4A, SW4B, SW5 in PFM (23),(27)
• VDDREF, VPLL, VGEN1, VGEN2, VUSB2, VDAC on  in low-power mode (23),(25)
• P L L 370 750 A

17 Freescale Semiconductor

• D i g i t a l c o r e
• RTC logic
• VCORE module
• VSRTC CLK32KMCU/CLK32K active (10 pF)
• 3 2 k oscillator
• I REF
• SW1, SW2, SW3, SW4A, SW4B, SW5 in APS SWBST (23),(26),(27)
• VDDREF, VPLL, VGEN1, VGEN2, VUSB2, VDAC on  in low-power mode (22),(25)
• D i g i t a l
• P L L 1600 3000 A Notes 22. Equivalent to approx. 30 mW min, 60 mW max 23. Current in RTC Mode is from LICELL=2.5 V; in all other modes from BP = 3.6 V. 24. External loads are not included 25. VUSB2, VGEN2 external pass PNPs 26. SWBST in auto mode 27. SW4A output 2.5 V

and TA = 25 °C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 18 34709 General Description

6 General Description

The 34709 is the PMIC designed specifically for use with the Freescale i.MX50 and i.MX53 families. As the companion PMIC on several i.MX reference designs, it is a proven solution, which enables a faster time to market with fewer resources.

6.1 Features

• Five buck switching regulators
• Two single/dual phase buck regulators
• Three single phase buck regulators
• Up to six independent outputs
• PFM/Auto pulse skip/PWM operation mode
• Dynamic voltage scaling
• 5 V boost regulator
• Support for USB physical layer on i.MX processor (USB PHY)
• Seven LDO regulators
• Two with selectable internal or external pass devices
• Four with embedded pass devices
• One with an external PNP device
• One voltage reference for DDR memory with internal PMOS device Analog to Digital Converter
• Seven general purpose channels
• Eight dedicated channels for monitoring the charger
• Resistive touchscreen interface Auxiliary Circuits
• General purpose I/Os
• PWM outputs Clocking and Oscillators
• Real time clock
• Time and day counters
• Time of day alarm
• 32.768 kHz crystal oscillator
• Coin cell battery backup
• Coin cell charger Serial Interface
• SPI
• I 2C

19 Freescale Semiconductor

6.2 Block Diagram

Figure 4. Functional Block Diagram

6.3 Functional Description

The 34709 Power Management Integrated Circuit (PMIC) represents a complete system power solution in a single package. seven LDO regulators and one voltage reference for direct supply of the processor core, memory, and peripherals. outputs, touch-screen interface, status LED drivers, and four GPIOs.

5.0 V BOOST

10 BIT ADC CORE

7 Functional Block Description

7.1 Start-up Requirements

switching regulators that are not enabled, are discharged at the beginning of the Cold start with weak pull-downs on the output. the mode that it is programmed to in the SPI. programmable options, to avoid sneak paths, under/over-voltage issues, start-up surges, etc, without any change in hardware. Table 9 shows the initial setup for the voltage level of the switching and linear regulators, and whether they get enabled. Table 9. Power-up Defaults

21 Freescale Semiconductor

1. The SWx node are activated in APS m ode when enabled by the start-up sequencer.
2. VUSB is supplied by SWBST.

Table 10. Power-up Sequence i.MX53

0 SW2 (VCC)

3 SW3 (VDDA)

4 SW1A/B (VDDGP)

5 SW4A/B, VREFDDR (DDR/SYS)

7 SW5 (I/O), VGEN1

8 VUSB, VUSB2

9 VDAC

Table 11. Power-up Sequence i.MX50

0 SW2

1 SW3

2 SW1A/B

3 VDAC

4 SW4A/B, VREFDDR

5 SW5

6 VGEN2, VUSB2

7 VPLL

8 VGEN1

9 VUSB

7.2 Bias and References Block Description and Application

is kept powered as long as there is a valid supply and/or coin cell. Table 12 shows the main characteristics of the core circuitry.

7.3 Clocking and Oscillators

7.3.1 Clock Generation

(for example, if the crystal is not present), an internal 32 kHz oscillator will be used instead. Table 12. Core Voltages Electrical Specifications and TA = 25 °C under nominal conditions, unless otherwise noted.

• ON mode
• OFF with good battery and RTC mode 1.5 0.0 V (30) CCOREDIG VCOREDIG bypass capacitor - 1.0 - F VDDLP (DIGITAL CORE SUPPLY - LOWER POWER) VDDLP Output voltage
• ON mode with good battery
• OFF mode with good battery
• RTC mode 1.5 1.2 1.2 V (31) CDDLP VDDLP bypass capacitor - 100 - pF (32) VCORE (ANALOG CORE SUPPLY) VCORE Output voltage
• ON mode and charging
• OFF and RTC mode 2.775 0.0 V (30) CCORE VCORE bypass capacitor - 1.0 - F VREFCORE (BANDGAP / REGULATOR REFERENCE) VREFCORE Output voltage - 1.2 - V (30) Absolute accuracy - 0.5 - % Temperature drift - 0.25 - % CREFCORE VREFCORE bypass capacitor - 100 - nF Notes 30. 3.0 V < BP < 4.5 V, no external loading on VCOREDIG, VDDLP, VCORE, or REFCORE. Extended operation down to UVDET, but no system malfunction. 31. Powered by VCOREDIG 32. Maximum capacitance on V DDLP should not exceed 1000 pF, including the board capacitance.

23 Freescale Semiconductor

CLK32KMCU can be provided as a reference to the SRTC module where tamper protection is implemented.

7.3.1.1 Clocking Scheme

occasionally referred to as “32 kHz” for brevity’s sake. transition, such as a sag in the regulator output voltage or absence of a signal on the clock output pins. and an interrupt will be generated if the corresponding CLKM mask bit is cleared.

7.3.1.2 Oscillator Specifications

equivalent (such as Micro Crystal CC5V-T1A or Epson FC135) and is capable of handling its parametric variations. characteristics noted above. The oscillator accuracy depends largely on the temperature characteristics of the used crystal. 1.0 Hz timer and RTC registers; see SRTC Support for more detail. Table 13. Oscillator and Clock Main Electrical Specifications and TA = 25 °C under nominal conditions, unless otherwise noted.

• Oscillator and RTC Block from BP
• Oscillator and RTC Block from LICELL 1.8 1.8 4.5 3.6 V IINRTC Operating Current Crystal Oscillator and RTC Module
• All blocks disabled, no main battery attached, coin cell is attached to LICELL - 2.0 5.0 tSTART-RTC RTC oscillator start-up time
• Upon application of power - - 1.0 sec VRTCLO Output Low
• CLK32K Output sink 100 A
• CLK32KMCU Output source 50 A 0.0 - 0.2 V VRTCHI Output High
• CLK32K Output source 100 A
• CLK32KMCU Output sink 50 A CLK32K VCC -0.2 VSRTC-0.2 CLK32K VCC VSRTC V

7.3.2 SRTC Support

power key initiated turn on, but the processor should have the knowledge, since the RTC initiated turn on is generated locally. Figure 5. SRTC Block Diagram

• CLK32KDRV [1:0] = 00
• CLK32KDRV [1:0] = 01 (default)
• CLK32KDRV [1:0] = 10
• CLK32KDRV [1:0] = 11 6.0 2.5 3.0 2.0 ns tCKL32K MCUET CLK32KMCU Rise and Fall Time
• C L = 12 pF - 22 - ns CLK32KDC/ CLK32K MCUDC CLK32K and CLK32KMCU Output Duty Cycle
• Crystal on XTAL1, XTAL2 pins 45 - 55 RMS Output Jitter
• 1 Sigma for Gaussian distribution - - 30 ns RMS

and TA = 25 °C under nominal conditions, unless otherwise noted.

25 Freescale Semiconductor

7.3.2.1 VSRTC

SRTC module integrated on certain FSL processors. The VSRTC regulator is enabled as soon as the RTCPORB is detected. The VSRTC cannot be disabled. 0111, 1000, or 1001), VSRTC will be set to 1.2 V for all modes (on, on standby, on standby low-power mode, off, and coin cell).

7.3.2.2 Real Time Clock

crystal oscillator for the time base and is powered by the coin cell backup supply when BP has dropped below operational range. Table 14. VSRTC Electrical Specifications and TA = 25 °C under nominal conditions, unless otherwise noted.

• Valid Coin Cell range
• V a l i d B P 1.8 1.8 3.6 4.5 V ISRTC Operating Current Load Range 0.0 - 50 A COSRTC Bypass Capacitor Value - 0.1 - F VSRTC - ACTIVE MODE - DC VSRTC Output Voltage
• V SRTCINMIN < VSTRCIN < VSRTCINMAX
• I SRTCMIN < ISRTC < ISRTCMAX
• Off and coin cell mode 1.15 1.20 1.28 V VSRTC - ACTIVE MODE - DC (CONTINUED) VSRTC Output Voltage
• V SRTCINMIN < VSTRCIN < VSRTCINMAX
• I SRTCMIN < ISRTC < ISRTCMAX
• On, Standby, and Standby LPM modes 1.15 1.2 1.25 V VSRTC Output Voltage
• V SRTCINMIN < VSTRCIN < VSRTCINMAX
• I SRTCMIN < ISRTC < ISRTCMAX
• On, Standby, and Standby LPM modes 1.25 1.3 1.35 V ISRTCQ Active Mode Quiescent Current
• V SRTCINMIN < VSTRCIN < VSRTCINMAX
• I SRTC = 0 - 0.8 -

equal to the value in TODA and the DAY counter is equal to the value in DAYA, the TODAI interrupt will be generated. function is implemented with the RTCRSTI bit. A clock calibration system is provided to adjust the 32,768 cycle counter that generates the 1.0 Hz timer for RTC timing registers. calibration word can be sent via the SPI, to compensate the RTC for inaccuracy in its reference oscillator. The available correction range should be sufficient to ensure drift accuracy in compliance with standards for DRM time keeping. Note that the 32.768 kHz oscillator is not affected by RTCCAL settings; calibration is only applied to the RTC time base counter. Therefore, the frequency at the clock output CLK32K is not affected. The RTC system calibration is enabled by programming the RTCCALMODE[1:0] for desired behavior by operational mode. RTC power draw is switched to the coin cell (configured with RTCCALMODE=01). Table 15. RTC calibration Settings Table 16. RTC Calibration Enabling

00 RTC Calibration disabled (default)

01 RTC Calibration enabled in all modes except coin cell only

10 Reserved for future use. Do not use.

11 RTC Calibration enabled in all modes

27 Freescale Semiconductor

not skewed the clock beyond desired tolerances.

7.3.3 Coin Cell Battery Backup

should be placed from LICELL to ground under all circumstances. powers on, or after enabling the coin cell charger when the IC was already on. current is fixed at ICOINHI. be stopped for the BP below UVDET. The bit COINCHEN itself is only cleared when an RTCPORB occurs. Table 17. Coin Cell Voltage Specifications Table 18. Coin Cell Electrical Specifications and TA = 25 °C under nominal conditions, unless otherwise noted.

7.4 Interrupt Management

7.4.1 Control

by driving the INT pin high; this is true whether the communication interface is configured for SPI or I2C. to go low. If a new interrupt occurs while the processor clears an existing interrupt bit, the interrupt line will remain high. interrupt bit was already high, the interrupt line will go high after unmasking. The sense registers contain status and input sense bits, so the system processor can poll the current state of interrupt sources. They are read only, and not latched or clearable. later in this section. Due to the asynchronous nature of the debounce timer, the effective debounce time can vary slightly.

7.4.2 Interrupt Bit Summary

refer to the related chapters. Table 19. Interrupt, Mask and Sense Bits Sense is 1 if PWRON1 is high. Sense is 1 if PWRON2 is high.

29 Freescale Semiconductor

1. Debounce timing for the falling edge can be extended with PWRONxDBNC[1:0]; refer to Serial Interfaces for details.

7.5 Power Generation

The 34709 PMIC provides reference and supply voltages for the application processor as well as peripheral device. sufficient headroom for the LDO through the normal discharge range of the main battery. they can be configured as interrupts.

7.5.1 Power Tree

Refer to the representative tables and text specifying each supply for information on performance metrics and operating ranges. Table 20 summarizes the available power supplies.

7.5.2 Modes of Operation

Power-up Mode Select (PUMS) pins. Table 20. Power Tree Summary

Analog Integrated Circuit Device Data

31 Freescale Semiconductor

Functional Block Description Power cycling of the application is driven by the 34709 PMIC. It has the interfaces for the power buttons and dedicated signaling interfacing with the processor. It also ensures the supply of the Real Time Clock (RTC), critical internal logic, and other circuits from the coin cell, in case of brief interruptions from the main battery. A charger for the coin cell is included to ensure that it is kept topped off until needed. The 34709 PMIC provides the timekeeping, based on an integrated low-power oscillator running with a standard watch crystal. This oscillator is used for internal clocking, the control logic, and as a reference for the Regulator PLL. The timekeeping includes time of day, calendar, and alarm, and is backed up by coin cell. The clock is driven to the processor for reference and deep sleep mode clocking.

Figure 6. Power Control State Machine Flow Diagram interrupt line INT is kept low in all states except for Watchdog and On.

Analog Integrated Circuit Device Data

33 Freescale Semiconductor

Functional Block Description

7.5.2.1 Coin Cell

The RTC module is powered from either the battery or the coin cell, due to insufficient voltage at BP, and the IC is not in a Power Cut. No Turn On event is accepted in the Coin Cell state. Transition out (to the Off state) requires BP restoration with a threshold above UVDET. RESETB, and RESETBMCU are held low in this mode. The RTC module remains active (32 kHz oscillator + RTC timers), along with BP level detection to qualify exit to the Off state. VCOREDIG is off and the VDDLP regulator is on, the rest of the system is put into its lowest power configuration. If the coin cell is depleted (VSTRC drops to 0.9 V to 0.8 V while in the Coin Cell state), a complete system reset will occur. At next power application / Turn On event, the system will start-up reinitialized with all SPI bits including those that reset on RTCPORB restored to their default states.

7.5.2.2 Off (with good battery)

If the supply VALWAYS is above the UVDET threshold, only the IC core circuitry at VCOREDIG and the RTC module are powered, all other supplies are inactive. To exit the Off mode, a valid turn on event is required. No specific timer is running in this mode. RESETB and RESETBMCU are held low in this mode. If BP is below the UVDET threshold, no turn on events are accepted. If a valid coin cell is present, the core gets powered from LICELL. The only active circuitry is the RTC module and the detection VCORE module powering VCOREDIG at 1.5 V. To exit the OFF mode, a valid turn ON event is required.

7.5.2.3 Cold Start

Cold Start is entered upon a Turn On event from Off, Warm Boot, successful PCUT, or a Silent System Restart. The first 8.0 ms is used for initialization which includes bias generation, PUMSx configuration latching, and qualification of the input supply level BP. The switching and linear regulators are then powered up sequentially to limit the inrush current; see the Power-up section for sequencing and default level details. The reset signals RESETB and RESETBMCU are kept low. The Reset timer starts running when entering Cold Start. The Cold Start state is exited for the Watchdog state and both RESETB and RESETBMCU become high (open-drain output with external pull-ups) when the reset timer is expired. The input control pins WDI, and STANDBY are ignored.

7.5.2.4 Watchdog

The system is fully powered and under SPI control. RESETB and RESETBMCU are high. The Watchdog timer starts running when entering the Watchdog state. When expired, the system transitions to the On state, where WDI will be checked and monitored. The input control pins WDI and STANDBY are ignored while in the Watchdog state.

7.5.2.5 On Mode

The system is fully powered and under SPI control. RESETB and RESETBMCU are high. The WDI pin must be high to stay in this mode. The WDI IO supply voltage is referenced to SPIVCC (normally connected to SW5 = 1.8 V); SPIVCC must therefore remain enabled to allow for proper WDI detection. If WDI goes low, the system will transition to the Off state or Cold Start (depending on the configuration; refer to the section on Silent System Restart with WDI Event for details).

7.5.2.6 User Off Wait

The system is fully powered and under SPI control. The WDI pin no longer has control over the part. The Wait mode is entered by a processor request for user off by setting the USEROFFSPI bit high. This is normally initiated by the end user via the power key; upon receiving the corresponding interrupt, the system will determine if the product has been configured for User Off or Memory Hold states (both of which first require passing through User Off Wait) or just transition to Off. The Wait timer starts running when entering User Off Wait mode. This leaves the processor time to suspend or terminate its tasks. When expired, the Wait mode is exited for User Off mode or Memory Hold mode depending on warm starts being enabled or not via the WARMEN bit. The USEROFFSPI bit is being reset at this point by RESETB going low.

Analog Integrated Circuit Device Data Freescale Semiconductor 34 34709 Functional Block Description

7.5.2.7 Memory Hold and User Off (Low-power Off states)

As noted in the User Off Wait description, the system is directed into low-power Off states based on a SPI command in response to an intentional turn off by the end user. The only exit then will be a turn on event. To an end user, the Memory Hold and User Off states look like the product has been shut down completely. However, a faster start-up is facilitated by maintaining external memory in self-refresh mode (Memory Hold and User Off mode) as well as powering portions of the processor core for state retention (User Off only). The Switching regulator mode control bits allow selective powering of the buck regulators for optimizing the supply behavior in the low-power Off modes. Linear regulators and most functional blocks are disabled (the RTC module, SPI bits resetting with RTCPORB, and Turn On event detection are maintained). By way of example, the following descriptions assume the typical use case where SW1 supplies the processor core(s), SW2 is applied to the processor’s VCC domain, SW3 supplies the processors internal memory/peripherals, SW4 supplies the external memory, and SW5 supplies the I/O rail. The buck regulators are intended for direct connection to the aforementioned loads.

7.5.2.8 Memory Hold

RESETB and RESETBMCU are low, and both CLK32K and CLK32KMCU are disabled (CLK32KMCU active if DRM is set). To ensure that SW1, SW2, SW3, and SW5 shut off in Memory Hold, appropriate mode settings should be used such as SW1MHMODE, = SW2MHMODE, = SW3MHMODE, = SW5MHMODE set to = 0 (refer to the mode control description later in this section). Since SW4 should be powered in PFM mode, SW4MHMODE could be set to 1. Upon a Turn On event, the Cold Start state is entered, the default power-up values are loaded, and the MEMHLDI interrupt bit is set. A Cold Start out of the Memory Hold state will result in shorter boot times compared to starting out of the Off state, since software does not have to be loaded and expanded from flash. The start-up out of Memory Hold is also referred to as Warm Boot. No specific timer is running in this mode. Buck regulators that are configured to stay on in MEMHOLD mode by their SWxMHMODE settings will not be turned off when coming out of MEMHOLD and entering a Warm Boot. The switching regulators will be reconfigured for their default settings as selected by the PUMSx pins in the normal time slot that would affect them.

7.5.2.9 User Off

RESETB is low and RESETBMCU is kept high. The 32 kHz peripheral clock driver CLK32K is disabled; CLK32KMCU (connected to the processor’s CKIL input) is maintained in this mode if the CLK32KMCUEN and USEROFFCLK bits are both set, or if DRM is set. The memory domain is held up by setting SW4UOMODE = 1. Similarly, the SW1 and/or SW2 and/or SW3 supply domains can be configured for SWxUOMODE=1 to keep them powered through the User Off event. If one of the switching regulators can be shut down on in User Off, its mode bits would typically be set to 0. Since power is maintained for the core (which is put into its lowest power state), and since MCU RESETBMCU does not trip, the processor’s state may be quickly recovered when exiting USEROFF upon a turn on event. The CLK32KMCU clock can be used for very low frequency / low-power idling of the core(s), minimizing battery drain, while allowing a rapid recovery from where the system left off before the USEROFF command. Upon a turn on event, Warm Start state is entered, and the default power-up values are loaded. A Warm Start out of User Off will result in an almost instantaneous start-up of the system, since the internal states of the processor were preserved along with external memory. No specific timer is running in this mode.

7.5.2.10 Warm Start

Entered upon a Turn On event from User Off. The first 8.0 ms is used for initialization, which includes bias generation, PUMSx latching, and qualification of the input supply level BP. The switching and linear regulators are then powered up sequentially to limit the inrush current; see Start-up Requirements for sequencing and default level details. If SW1, SW2, SW3, SW4, and/or SW5, were configured to stay on in User Off mode by their SWxUOMODE settings, they will not be turned off when coming out of User Off and entering a Warm Start. The buck regulators will be reconfigured for their default settings as selected by the PUMSx pins in the respective time slot defined in the sequencer selection. RESETB is kept low and RESETBMCU is kept high. CLK32KMCU is kept active if CLK32KMCU was set. The reset timer starts running when entering Warm Start. When expired, the Warm Start state is exited for the Watchdog state, a WARMI interrupt is generated, and RESETB will go high.

Analog Integrated Circuit Device Data

35 Freescale Semiconductor

Functional Block Description

7.5.2.11 Internal MemHold Power Cut

As described in the Power Cut Description, a momentary power interruption will put the system into the Internal MemHold Power Cut state if PCUTs are enabled. The backup coin cell will now supply the 34709 core along with the 32 k crystal oscillator, the RTC system, and coin cell backed up registers. All regulators will be shut down to preserve the coin cell and RTC as long as possible. Both RESETB and RESETBMCU are tripped, bringing the entire system down along with the supplies and external clock drivers, so the only recovery out of a Power Cut state is to reestablish power and initiate a Cold Start. If the PCT timer expires before power is re-established, the system transitions to the Off state and awaits a sufficient supply recovery.

7.5.3 Power Control Logic

7.5.3.1 Power Cut Description

When the BP drops below the UVDET threshold, due to battery bounce or battery removal, the Internal MemHold Power Cut mode is entered and a Power Cut (PCUT) timer starts running. The backup coin cell will now supply the RTC as well as the on chip memory registers and some other power control related bits. All other supplies will be disabled. The maximum duration of a power cut is determined by the PCUT timer PCT [7:0] preset via the SPI. When a PCUT occurs, the PCUT timer will be started. The contents of PCT [7:0] does not reflect the actual count down value, but will keep the programmed value, and therefore does not have to be reprogrammed after each power cut. If power is not re-established above the 3.0 V threshold before the PCUT timer expires, the state machine transitions to the Off mode at expiration of the counter, and clears the PCUTEXB bit by setting it to 0. This transition is referred to as an “unsuccessful” PCUT. In addition the PMIC will bring the SDWNB pin low for one 32 kHz clock cycle before powering down. Upon re-application of power before expiration (a “successful PCUT”, defined as BP first rising above the UVDET threshold and then battery above the 3.0 V threshold before the PCUT timer expires), a Cold Start is engaged after the UVTIMER has expired. In order to distinguish a non-PCUT initiated Cold Start from a Cold Start after a PCUT, the PCI interrupt should be checked by software. The PCI interrupt is cleared by software or when cycling through the Off state. Because the PCUT system quickly disables the entire power tree, the battery voltage may recover to a level with the appearance of a valid supply once the battery is unloaded. However, upon a restart of the IC and power sequencer, the surge of current through the battery and trace impedances can once again cause the BP node to droop below UVDET. This chain of cyclic power down / power-up sequences is referred to as “ambulance mode”, and the power control system includes strategies to minimize the chance of a product falling into and getting stuck in ambulance mode. First, the successful recovery out of a PCUT requires the BP node to rise above LOBATT threshold, providing hysteretic margin from the LOBATT (H to L) threshold. Secondly, the number of times the PCUT mode is entered is counted with the counter PCCOUNT [3:0], and the allowed count is limited to PCMAXCNT [3:0] set through the SPI. When the contents of both become equal, then the next PCUT will not be supported and the system will go to Off mode, after the PCUT time expires. After a successful power-up after a PCUT (i.e., valid power is reestablished, the system comes out of reset, and the processor reassumes control), software should clear the PCCOUNT [3:0] counter. Counting of PCUT events is enabled via the PCCOUNTEN bit. This mode is only supported if the power cut mode feature is enabled by setting the PCEN bit. When not enabled, then in case of a power failure, the state machine will transition to the Off state. SPI control is not possible during a PCUT event and the interrupt line is kept low. SPI configuration for PCUT support should also include setting the PCUTEXPB = 1 (See Silent Restart from PCUT Event).

7.5.3.2 Silent Restart from PCUT Event

If a short duration power cut event occurs (such as from a battery bounce, for example), it may be desirable to perform a silent restart, so the system is reinitialized without alerting the user. This can be facilitated by setting the PCUTEXPB bit to “1” at booting or after a Cold Start. This bit resets on RTCPORB, therefore any subsequent Cold Start can first check the status of PCUTEXPB and the PCI bit. The PCUTEXPB is cleared to “0” when transitioning from PCUT to Off. If there was a PCUT interrupt and PCUTEXPB is still “1”, then the state machine has not transitioned through Off, which confirms that the PCT timer has not expired during the PCUT event (i.e., a successful power cut). In this case, a silent restart may be appropriate.

7.5.3.3 Silent System Restart with WDI Event

will go to Cold Start without passing through Off mode (i.e., does not generate an OFFB signal). programmable PCMAXCNT counter. an inconspicuous restart without fanfare may be more appropriate than launching into the welcoming routine. A PCUT event does not trip the WDIRESETI bit. as programmed by WDIRESET and described above.

7.5.3.4 Turn On Events

to the processor what event caused the system to power on, an interrupt bit is associated with each of the Turn On events. was already on at the time of the turn on event, the interrupt is still generated.

• Power Button Press: PWRON1, or PWRON2 pulled low with corresponding interrupts and sense bits PWRON1I or PWRON2I, and PWRON1S or PWRON2S. A power on/off button is connected from PWRONx to ground. The PWRONx can be hardware debounced through a programmable debouncer PWRONxDBNC [1:0] to avoid a response upon a very short (i.e., unintentional) key press. BP should be above UVDET to allow a power-up. The PWRONxI interrupt is generated for both the falling and the rising edge of the PWRONx pin. By default, a 30 ms interrupt debounce is applied to both falling and rising edges. The falling edge debounce timing can be extended with PWRONxDBNC[1:0] as defined in the following table. The PWRONxI interrupt is cleared by software or when cycling through the Off mode.
• Battery Attach: This occurs when BP crosses the 3.0V threshold and the UVDET rising threshold which is equivalent to attaching a charged battery or supply to the product.
• RTC Alarm: TOD and DAY become equal to the alarm setting programmed. This allows powering up a product at a preset time. BP should be above 3.0V, and BP should have crossed the UVDET rising threshold and not transitioned below the UVDET falling threshold.
• System Restart: System restart which may occur after a system reset as described earlier in this section. This is an optional function, see Turn Off Events. BP should be above 3.0 V and BP should have crossed the UVDET rising threshold and not transitioned below the UVDET falling threshold.

Table 21. PWRONx Hardware Debounce Bit Settings(34)

1. The sense bit PWRONxS is not debounced and follows the state of the PWRONx pin.

37 Freescale Semiconductor

• Global System Reset: The global reset feature powers down the part, disables the charger, resets the SPI registers to their default value including all the RTCPORB registers (except the DRM bit, and the RTC registers), and then powers back on. To enable a global reset, the GLBRST pin needs to be pulled low for greater than GLBRSTTMR [1:0] seconds and then pulled back high (defaults to 12 s). BP should be above 3.0 V.

7.5.3.5 Turn Off Events

• Power Button Press (via WDI): User shut down of a product is typically done by pressing the power button connected to the PWRONx pin. This will generate an interrupt (PWRONxI), but will not directly power off the part. The product is powered off by the processor’s response to this interrupt, which will be to pull WDI low. Pressing the power button is therefore under normal circumstances not considered as a turn off event for the state machine. However, since the button press power down is the most common turn off method for end products, it is described in this section as the product implementation for a WDI initiated Turn Off event. Note that the software can configure a user initiated power down, via a power button press for transition to a Low-power Off mode (Memory Hold or User Off) for a quicker restart than the default transition into the Off state.
• Power Button System Reset: A secondary application of the PWRONx pins is the option to generate a system reset. This is recognized as a Turn Off event. By default, the system reset function is disabled but can be enabled by setting the PWRONxRSTEN bits. When enabled, a four second long press on the power button will cause the device to go to the Off mode, and as a result, the entire application will power down. An interrupt SYSRSTI is generated upon the next power-up. Alternatively, the system can be configured to restart automatically by setting the RESTARTEN bit.
• Thermal Protection: If the die gets overheated, the thermal protection will power off the part to avoid damage. A Turn On event will not be accepted while the thermal protection is still being tripped. The part will remain in Off mode until cooling sufficiently to accept a Turn On event. There are no specific interrupts related to this other than the warning interrupts.
• Under-voltage Detection: When the voltage at BP drops below the under-voltage detection threshold UVDET, the state machine will transition to Off mode if PCUT is not enabled, or if the PCT timer expires when PCUT is enabled. The SDWNB pin is used to notify that the processor that the PMIC is going to immediately shut down. The PMIC will bring the SDWNB pin low for one 32 kHz clock cycle before powering down. This signal will then be brought back high in the power Off state.

7.5.3.6 Timers

event, the duration listed below is therefore the effective minimum time period. Table 22. Global Reset Time Settings

00 Invalid

Table 23. Timer Main Characteristics

7.5.3.6.1 Timing Diagrams

A Turn On event timing diagrams shown in Figure 7. Figure 7. Power-up Timing Diagram

7.5.3.7 Power Monitoring

The voltage at BP are monitored by detectors as summarized in Table 24. node decreases below the 2.9 V threshold, a low input supply warning will be sent to the processor via the LOWBATTI interrupt. The LOWBATTI detection threshold is debounced by the VBATTDB[2:0] SPI bits shown in Table 25. Table 24. LOWBATT Detection Thresholds

• BP (H to L)(35) 2.9 UVDET rising(36) 3.0 UVDT Falling(36) 2.65 Notes 35. 50 mV hysteresis is applied. 36. ± 4.0 % tolerance RESETB WDI INT UV Masking 8 ms 20 ms 12 ms Power Up Sequencer Turn On Verification 128 ms 2 - Cold Start 1 - Off System Core Active 3 - Watchdog 4 - On 1 - Off 3- Watchdog Power up of the system upon a Turn On Event followed by a transition to the On state if WDI is pulled high ... or transition to Off state if WDI remains low Turn On Event Sequencer time slots WDI Pulled Low = Indeterminate State ow Turn on Event is based on PWRON being pulled low 8 ms

39 Freescale Semiconductor

7.5.3.8 Power Saving

7.5.3.8.1 System Standby

in and out of such deep sleep modes. pin. The configuration of the regulators in standby is pre-programmed through the SPI. adjustments accordingly as soon as it is running.

7.5.3.8.2 Standby Delay

11), STBYDLY will delay the STANDBY initiated response for the entire IC until the STBYDLY counter expires. Table 25. VBATTDB Debounce Times Table 26. Standby Pin and Polarity Control

1. STANDBY = 0: System is not in Standby STANDBY = 1: System is in Standby

k cycle of additional delay).

7.5.4 Buck Switching Regulators

DVS control for processor power optimization, or to support technologies with a mix of device types with different voltage ratings. interfaces, which can run at the same voltage level. SW5 is used to supply the I/O domain for the system. SPI and include a PFM mode, PWM Pulse Skip, an Automatic Pulse Skipping mode, and a PWM mode. Buck modes of operation are programmable for explicitly defined or load-dependent control. mode A built in current limiter ensures that during normal operation the maximum current through the coil is not exceeded. Point of Load feedback is intended for minimizing errors due to board level IR drops.

7.5.4.1 General Control

put into PFM mode to optimize efficiency. Table 27. Delay of STANDBY- Initiated Response

00 No Delay

01 One 32 k period (default)

10 Two 32 k periods

11 Three 32 k periods

Table 28. Buck Operating Modes PFM mode. Useful at light loads for optimized efficiency. between pulse skipping and full PWM mode depending on load conditions. operation regardless of load conditions. PWMPS The regulator is alternating between pulse skipping and PWM modes, depending on the load conditions.

41 Freescale Semiconductor

will be reset to their default values defined by PUMSx settings by the start-up sequencer. Table 29 summarizes the Buck regulators programmability for Normal and Standby modes. Off mode will not be off when the start-up sequencer is started). Table 29. Switching regulator Mode Control for Normal and Standby Operation

0000 Off Off

0001 PWM Off

0010 PWMPS Off

0011 PFM Off

0100 APS Off

0101 PWM PWM

0110 PWM APS

0111 Off Off

1000 APS APS

1001 PWM PWMPS

1010 PWMPS PWMPS

1011 PWMPS APS

1100 APS PFM

1101 PWM PFM

1110 PWMPS PFM

1111 PFM PFM

Table 30. Switching regulator Control In Memory Hold

0 Off

1 PFM

1. For Memory Hold mode, an activated SWx should use the

Standby set point as programmed by SWxSTBY[4:0].

lower set point, the SW1xPWGD pin will go low and will go high again when the higher/lower set point is reached.

7.5.4.2 Switching Frequency

be programmed to 2.0 MHz or 4.0 MHz by setting the PLLX SPI bit as shown in Table 32. operation for PWM mode. The PLL can be configured for continuous operation with PLLEN = 1.

7.5.4.3 SW1

Table 31. Switching regulator Control In User Off

1. For User Off mode, an ac tivated SWx should use the

Standby set point as programmed by SWxSTBY[4:0]. Table 32. Buck Regulator Frequency Table 33. SW1 Configuration

43 Freescale Semiconductor

Figure 8. SW1 Single Phase Output Mode Block Diagram Figure 9. SW1 Dual Phase Output Mode Block Diagram

output voltage for both the SW1A and SW1B. Table 34. SW1A/B Output Voltage Programmability

45 Freescale Semiconductor

Table 35. SW1A/B Electrical Specification and TA = 25 °C under nominal conditions, unless otherwise noted.

• PWM operation, 0 < IL < IMAX
• PFM operation, 0 < IL < ILMAX 3.0 2.8 4.5 4.5 V VSW1ACC Output Voltage Accuracy
• PWM mode including ripple, load regulation, and transients
• PFM Mode, including ripple, load regulation, and transients Nom-25 Nom-25 Nom Nom Nom+25 Nom+25 mV (40) ISW1 Continuous Output Load Current, VINMIN < BP < 4.5 V
• PWM mode single/dual phase (parallel)
• SW1 in PFM mode 2000 mA ISW1PEAK Current Limiter Peak Current Detection
• V IN = 3.6 V, Current through Inductor - 4.0 - A ISW1 TRANSIENT Transient Load Change A VSW1OS- START Start-up Overshoot, IL = 0 - 25 mV tON-SW1 Turn-on Time
• Enable to 90% of end value IL = 0 - - 500 µs fSW1 Switching Frequency
• PLLX = 0
• PLLX = 1 2.0 4.0 MHz ISW1Q Quiescent Current Consumption
• PWMPS or APS Mode, IL=0 mA; device not switching
• PFM Mode, IL=0 mA 160 µA Efficiency,
• P F M , 0 . 9 V, 1.0 mA
• PWM Pulse skipping, 1.1 V, 200 mA
• PWM Pulse skipping, 1.1 V, 800 mA
• P W M , 1 . 1 V, 1600 mA % (41) Notes: 40. Transient loading for load steps of ILMAX/2. 41. Efficiency numbers at V IN = 3.6 V, excludes the quiescent current

7.5.4.4 SW2

SW2 is fully integrated synchronous Buck PWM voltage-mode control DC/DC regulator. Figure 10. SW2 Block Diagram SW2 can be programmed in step sizes of 12.5 mV as shown in Table 36. Table 36. SW2 Output Voltage Programmability

47 Freescale Semiconductor

Table 37. SW2 Electrical Specifications and TA = 25 °C under nominal conditions, unless otherwise noted.

• PWM operation, 0 < IL < IMAX
• PFM operation, 0 < IL < ILMAX 3.0 2.8 4.5 4.5 V VSW2ACC Output Voltage Accuracy
• PWM mode including ripple, load regulation, and transients
• PFM Mode, including ripple, load regulation, and transients Nom-25 Nom-25 Nom Nom Nom+25 Nom+25 mV (42) ISW2 Continuous Output Load Current, VINMIN < BP < 4.5 V
• PWM mode
• PFM mode 1000 mA ISW2PEAK Current Limiter Peak Current Detection
• V IN = 3.6 V Current through Inductor - 2.0 - A ISW2 TRANSIENT Transient Load Change
• 100 mA/µs - - 0.500 A VSW2OS- START Start-up Overshoot, IL = 0 - - 25 mV tON-SW2 Turn-on Time
• Enable to 90% of end value IL = 0 - - 500 µs

7.5.4.5 SW3

SW3 is fully integrated synchronous Buck PWM voltage mode control DC/DC regulator. Figure 11. SW3 Block Diagram SW3 can be programmed in step sizes of 25 mV as shown in Table 38.

• PLLX = 0
• PLLX = 1 2.0 4.0 MHz ISW2Q Quiescent Current Consumption
• PWMPS or APS Mode, IL=0 mA; device not switching
• PFM Mode, IL = 0 mA; device not switching 160 µA Efficiency
• P F M , 0 . 9 V, 1.0 mA
• PWM Pulse skipping, 1.2 V, 120 mA
• PWM Pulse skipping, 1.2 V, 500 mA
• P W M , 1 . 2 V, 1000 mA % (43) Notes: 42. Transient loading for load steps of ILMAX/2. 43. Efficiency numbers at V IN = 3.6 V, excludes the quiescent current.

and TA = 25 °C under nominal conditions, unless otherwise noted.

49 Freescale Semiconductor

Table 38. SW3 Output Voltage Programmability Table 39. SW3 Electrical Specification and TA = 25 °C under nominal conditions, unless otherwise noted.

• PWM operation, 0 < IL < IMAX
• PFM operation, 0 < IL < ILMAX 3.0 2.8 4.5 4.5 V VSW3ACC Output Voltage Accuracy
• PWM mode including ripple, load regulation, and transients
• PFM Mode, including ripple, load regulation, and transients Nom-3% Nom-3% Nom Nom Nom+3% Nom+3% mV (44) ISW3 Continuous Output Load Current, VINMIN < BP < 4.5 V
• PWM mode
• PFM mode 500 mA ISW3PEAK Current Limiter Peak Current Detection
• V IN = 3.6 V Current through Inductor - 1.0 - A ISW3 TRANSIENT Transient Load Change
• 100 mA/µs - - 250 mA VSW3OS- START Start-up Overshoot, IL = 100 mA/µs - - 25 mV tON-SW3 Turn-on Time
• Enable to 90% of end value IL = 0 - - 500 µs

7.5.4.6 SW4

SW4CFG pin. The SW4CFG pin is sampled at start-up.

• PLLX = 0
• PLLX = 1 2.0 4.0 MHz ISW3Q Quiescent Current Consumption
• PWMPS or APS Mode, IL=0 mA; device not switching
• PFM Mode, IL = 0 mA; device not switching 160 µA Efficiency
• P F M , 1 . 2 V, 1.0 mA
• PWM Pulse skipping, 1.2 V, 120 mA
• PWM Pulse skipping, 1.2 V, 250 mA
• P W M , 1 . 2 V, 500 mA % (45) Notes: 44. Transient loading for load steps of ILMAX/2 45. Efficiency numbers at VIN=3.6 V, Excludes the quiescent current,

Table 40. SW4A/B Configuration and TA = 25 °C under nominal conditions, unless otherwise noted.

51 Freescale Semiconductor

Figure 12. SW4A/B Separate Output Mode Block Diagram

Figure 13. SW4 Single Phase Output Mode Block Diagram

53 Freescale Semiconductor

Figure 14. SW4 Dual Phase Output Mode Block Diagram be forced into PWM mode to change the voltage. Table 41. SW4A/B Output Voltage Select

00 SW4x[4:0] See Table 42

Table 42. SW4A/B Output Voltage Programmability Table 43. SW4A/B Electrical Specifications and TA = 25 °C under nominal conditions, unless otherwise noted.

• PWM operation, 0 < IL < IMAX
• PFM operation, 0 < IL < ILMAX 3.0 2.8 4.5 4.5 V (47) VSW4ACC Output Voltage Accuracy
• PWM mode including ripple, load regulation, and transients
• PFM Mode, including ripple, load regulation, and transients Nom-3% Nom-3% Nom Nom Nom+3% Nom+3% mV (46) ISW4 Continuous Output Load Current, VINMIN < BP < 4.5 V
• PWM mode (separate)
• PWM mode single/dual phase
• PFM mode 500 1000 mA ISW4PEAK Current Limiter Peak Current Detection
• V IN = 3.6 V Current through Inductor (separate)
• Current through Inductor 1.0 2.0 A

55 Freescale Semiconductor

• Single/Dual Phase
• Separate
• 100 mA/µs 500 250 mA VSW4OS- START Start-up Overshoot, IL = 100 mA/µs - - 25 mV tON-SW4 Turn-on Time
• Enable to 90% of end value IL = 0 - - 500 µs fSW4 Switching Frequency
• PLLX = 0
• PLLX = 1 2.0 4.0 MHz ISW4Q Quiescent Current Consumption
• PWMPS or APS Mode, IL=0 mA; device not switching
• PFM Mode, IL = 0 mA; device not switching 160 µA Efficiency
• P F M , 3 . 1 5 V, 10 mA (A)
• PWM Pulse skipping, 3.15 V, 50 mA (A)
• PWM Pulse skipping, 3.15 V, 250 mA (A)
• PWM, 3.15 V, 500 mA (A)
• P F M , 1 . 2 V, 10 mA (B)
• PWM Pulse skipping, 1.2 V, 50 mA (B)
• PWM Pulse skipping, 1.2 V, 250 mA (B)
• P W M 1 . 2 V, 500 mA (B) % (48) Notes: 46. Transient loading for load steps of IL MAX / 2. 47. When SW4A/B is set to 3.0 V and above the regulator may drop out of regulation when BP nears the output voltage. 48. Efficiency numbers at V IN = 3.6 V, excludes the quiescent current.

and TA = 25 °C under nominal conditions, unless otherwise noted.

7.5.4.7 SW5

SW5 is fully integrated synchronous Buck PWM voltage mode control DC/DC regulator. Figure 15. SW5 Block Diagram power-up the regulator should be forced into PWM mode to change the voltage. Table 44. SW5 Output Voltage Programmability

57 Freescale Semiconductor

Table 45. SW5 Electrical Specifications and TA = 25 °C under nominal conditions, unless otherwise noted.

• PWM operation, 0 < IL < IMAX
• PFM operation, 0 < IL < ILMAX 3.0 2.8 4.5 4.5 V VSW5ACC Output Voltage Accuracy
• PWM mode including ripple, load regulation, and transients
• PFM Mode, including ripple, load regulation, and transients Nom-3% Nom-3% Nom Nom Nom+3% Nom+3% mV (49) ISW5 Continuous Output Load Current, VINMIN < BP < 4.5 V
• PWM mode
• PFM mode 1000 mA ISW5PEAK Current Limiter Peak Current Detection
• V IN = 3.6 V Current through Inductor - 2.0 - A ISW5 TRANSIENT Transient Load Change
• 100 mA/µs - - 500 mA VSW5 OS-START Start-up Overshoot, IL = 0 - - 25 mV tON-SW5 Turn-on Time
• Enable to 90% of end value IL = 0 - - 500 µs fSW5 Switching Frequency
• PLLX = 0
• PLLX = 1 2.0 4.0 MHz ISW5Q Quiescent Current Consumption
• PWMPS or APS Mode, IL=0 mA; device not switching
• PFM Mode, IL = 0 mA; device not switching 160 µA Efficiency
• P F M , 1 . 8 V, 1.0 mA
• PWM Pulse skipping, 1.8 V, 50 mA
• PWM Pulse skipping, 1.8 V, 500 mA
• P W M , 1 . 8 V, 1000 mA % (50) Notes 49. Transient Loading for load Steps of ILMAX/2 50. Efficiency numbers at VIN=3.6 V, Excludes the quiescent current.

7.5.4.8 Dynamic Voltage Scaling

which could cause logic disruptions on their loads.

• Normal operation: output value selected by SPI bits SWx[5:0]. Voltage transitions initiated by SPI writes to SWx[5:0] are governed by the DVS stepping rate shown in the following tables.
• Standby (Deep Sleep): can be higher or lower than normal operatio n, but is typically selected to be the lowest state retention voltage of a given process. Set by SPI bits SWxSTBY[5:0] and controlled by a Standby event. Voltage transitions initiated by Standby are governed by the SWxDVSSPEED[1:0] SPI bits shown in Table 46. The following table summarizes the set point control and DVS time stepping applied to SW1A/B and SW2. The regulator has a strong sourcing and sinking capability in the PWM mode. Therefore, the rising/falling slope is determined by the regulator in PWM mode. However, if the regulators are programmed in PFM, PWMPS, or APS mode during a DVS transition, the falling slope can be influenced by the load. Additionally, as the current capability in PFM mode is reduced, controlled DVS transitions in PFM mode could be affected. Critically timed DVS transitions are best assured with PWM mode operation. Voltage transitions programmed through SPI(SWx[4:0]) on SW3 and SW5 will step in increments of 25 mV per 4.0 s, SW4A/B will step in increments of 25 mV per 8.0 s when SW4xHI[1:0]=00, and SW4A/B will step in increments of 25 mV per 16 s when SW4xHI[1:0]≠00. Additionally, SW3, SW4/B, and SW5 include standby mode set point programmability. The following diagram shows the general behavior for the switching regulators when initiated with SPI programming or standby control. SW1 and SW2 also contain Power Good (outputs from the 34709 to the application processor). The power good signal is an active high signal. When SWxPWRGDB is high, it means that the regulators output has reached its programmed voltage. The SWxPWRGDB voltage outputs will be low during the DVS period and if the current limit is reached on the switching regulator. The SWxPWRGD will be low from a low to high or a high to low transition of the regulator output voltage. During the DVS period, the over-current condition on the switching regulator should be masked. If the current limit is reached outside of a DVS period, the SWxPWRGD pin will stay low until the current limit condition is removed.

Table 46. DVS Control Logic Table for SW1A/B and SW2

0 SWx[4:0]

1 SWxSTBY[4:0]

Table 47. DVS Speed Selection

59 Freescale Semiconductor

Figure 16. Voltage Stepping with DVS

7.5.5 Boost Switching Regulator

SWBST is a boost switching regulator with a programmable output, which defaults to 5.0 V on power-up, operating at 2.0 MHz. Figure 17. Boost Regulator Architecture SWBST output voltage programmable via the SWBST[1:0] SPI bits as shown in Table 48. Table 48. SWBST Voltage Programming

mode based on the load current. By default SWBST is powered up in Auto mode. Table 49. SWBST Mode Control

00 Off

01 PFM

10 Auto (default)

11 PWM

Table 50. SWBST Electrical Specifications and TA = 25 °C under nominal conditions, unless otherwise noted.

• 3 . 0 V < VIN < 4.5 V, 0 < IL < ILMAX Nom-4% VNOM Nom+3% V (51) VSWBSTACC Output Ripple
• 3 . 0 V < VIN < 4.5 V 0 < IL < ILMAX, excluding reverse recovery of Schottky diode - - 120 mV Vp-p SWBSTACC Average Load Regulation
• V IN = 3.6 V, 0 < IL < ILMAX - 0.5 - mV/mA VSWBST LINEAREG Average Line Regulation
• 3 . 0 V < VIN < 4.5 V IL = ILMAX - 50 - mV ISWBST Continuous Load Current
• 3 . 0 V < VIN < 4.5 V, VOUT = 5.0 V - 380 - mA ISWBSTPEAK Peak Current Limit
• At SWBSTIN, VIN = 3.6 V - 1800 - mA VSWBSTOS- START Start-up Overshoot, IL = 0 mA - - 500 mV tON-SWBST Turn-on Time
• Enable to 90% of VOUT IL = 0 - - 2.0 ms fSWBST Switching Frequency - 2.0 - MHz VSWBS TRANSIENT Transient Load Response, IL from 1.0 to 100 mA in 1.0 µs steps
• Maximum transient Amplitude - - 300 mV VSWBS TRANSIENT Transient Load Response, IL from 100 to 1.0 mA in 1.0 µs steps
• Maximum transient Amplitude - - 300 mV VSWBS TRANSIENT Transient Load Response, IL from 1.0 to 100 mA in 1.0 µs steps
• Time to settle 80% of transient - - 500 µs VSWBS TRANSIENT Transient Load Response, IL from 100 to 1.0 mA in 1.0 µs steps
• Time to settle 80% of transient - - 20 ms Efficiency, IL = ILMAX 65 80 - %

61 Freescale Semiconductor

7.5.6 Linear Regulators (LDOs)

kept powered as long as there is a valid supply and/or coin cell.

7.5.6.1 General Features

The following applies to all linear regulators, unless otherwise specified.

• Advised bypass capacitor is the Murata GRM155R60G225ME95, which comes in a 0402 case.
• In general, parametric performance specifications assume the use of low ESR X5R/X7R ceramic capacitors with 20% accuracy and 15% temperature spread, for a worst case stack up of 35% from the nominal value. Use of other types with wider temperature variation may require a larger room temperature nominal capacitance value to meet performance specs over temperature. In addition, capacitor derating as a function of DC bias voltage requires special attention. Finally, minimum bypass capacitor guidelines are provided for stability and transient performance. Larger values may be applied; performance metrics may be altered and generally improved, but should be confirmed in system applications.
• Regulators which require a minimum output capacitor ESR (those with external PNPs) can avoid an external resistor if ESR is assured with capacitor specifications or board level trace resistance.
• The output voltage tolerance specified for each of the linear r egulators include process variation, temperature range, static line regulation, and static load regulation.
• In the Low-power mode, the output performance is degraded. Only those parameters listed in the Low-power mode section are guaranteed. In this mode, the output current is limited to much lower currents than in the active mode.
• When a regulator gets disabled, the output will be pulled towa rds ground by an internal pull-down. The pull-down is also activated when RESETB goes low.

7.5.6.2 LDO Regulator Control

regulators in a Low-power mode.

• PFM or Auto mode - 35 - µA ILEAK-SWBST NMOS Off Leakage
• S W B S T I N = 4.5 V, SWBSTMODE [1:0] = 0 - 1.0 6.0 µA Notes: 51. V IN is the low side of the inductor that is connected to BP.

and TA = 25 °C under nominal conditions, unless otherwise noted.

corresponding mode bits for the operational behavior desired. regulator. Therefore, depending on the configuration selected, the automatic Low-power mode determines availability. For regulators with internal pass devices, the previous table can be simplified by elimination of the VxMODE column. Table 51. LDO Regulator Control (external pass device LDOs)

0 X X X Off

1 X 1 0 On

1. STANDBY refers to a Standby event as described earlier

Table 52. LDO Regulator Control (internal pass device LDOs)

0 X X Off

1. STANDBY refers to a Standby event as described earlier

63 Freescale Semiconductor

7.5.6.3 Transient Response Waveforms

overshoot and DC shift. This is also valid for the mode transition response. Figure 18. Transient Waveforms

7.5.6.4 Short-circuit Protection

in an overload condition are disabled.

7.5.6.5 VPLL

inputs can be connected to either BP or a 2.2 V nominal external switched mode power supply rail, to improve power dissipation. Table 53. VPLL Voltage Control Table 54. VPLL Electrical Specification and TA = 25 °C under nominal conditions, unless otherwise noted.

• VPLL all settings, BP biased
• VPLL, [1:0] = 10, 11, External Switch UVDET 1.75 2.15 1.8 2.2 4.5 4.5 4.5 V IPLL Operating current Load range - - 50 mA VPLL ACTIVE MODE – DC VPLL Output Voltage VOUT
• V INMIN < VIN < VINMAX ILMIN < IL < ILMAX VNOM – 0.05 VNOM VNOM + 0.05 V VPLL-LOPP Load Regulation
• 1 . 0 mA < IL < ILMAX For any VINMIN < VIN < VINMAX - 0.35 - mV/mA VPLL-LIPP Line Regulation
• V INMIN < VIN < VINMAX For any ILMIN < IL < ILMAX - 5.0 - mV IPLL-Q Quiescent Current
• V INMIN < VIN < VINMAX IL = 0 - 8.0 - µA IPLLLIM Current Limit
• V INMIN < VIN < VINMAX - 75 - mA VPLL ACTIVE MODE – AC VPLLPSRR PSRR, IL = 75% of ILMAX, 20 Hz to 20 kHz
• V IN = UVDET
• V IN = VNOM + 1.0 V, > UVDET dB

65 Freescale Semiconductor

7.5.6.6 VREFDDR

utilizes a voltage follower to drive the load.

• 100 Hz – 1.0 kHz
• > 1 . 0 kHz – 1.0 MHz 2.5 dB/dec V/Hz VPLL ACTIVE MODE – AC (CONTINUED) tON-VPLL Turn-on Time
• Enable to 90% of end value VIN = VINMIN, VINMAX IL = 0 - - 140 µs tOFF-VPLL Turn-off Time
• Disable to 10% of initial value VIN = VINMIN, VINMAX, IL = 0 0.05 - 10 ms VPLLOS- START Start-up Overshoot
• V IN = VINMIN, VINMAX IL = 0 - 1.0 2.0 VPLL-LO TRANSIENT Transient Load Response
• V IN = VINMIN, VINMAX - 50 70 mV VPLL-LI TRANSIENT Transient Line Response
• I L = 75% of ILMAX - 5.0 8.0 mV

Table 55. VREFDDR Electrical Specification and TA = 25 °C under nominal conditions, unless otherwise noted.

• V INMIN < VIN < VINMAX ILMIN < IL < ILMAX 0.6 VIN/2 0.9 V VREFDDRTOL Output Voltage tolerance
• V INMIN < VIN < VINMAX
• 0 . 6 mA < IL < 10 mA -1.0 - 1.0 (54) VREFDDR LOPP Load Regulation
• 1 . 0 mA < IL < ILMAX For any VINMIN < VIN < VINMAX - 5.0 - mV/mA IREFDDRQ Quiescent Current
• V INMIN < VIN < VINMAX IL = 0 - 8.0 - µA IREFDDRLIM Current Limit
• V INMIN < VIN < VINMAX - 36 - mA

and TA = 25 °C under nominal conditions, unless otherwise noted.

7.5.6.7 VUSB

FET which will support loads up to 100 mA.

• Enable to 90% of end value VIN = VINMIN, VINMAX IL = 0 - - 100 µs tOFF- VREFDDR Turn-off Time
• Disable to 10% of initial value VIN = VINMIN, VINMAX, IL = 0 0.05 - 10 ms VREFDDR ACTIVE MODE – AC (CONTINUED) VREFDDROS Start-up Overshoot
• V IN = VINMIN, VINMAX IL = 0 - 1.0 2.0 VREFDDRL TRANSIENT Transient Load Response
• V IN = VINMIN, VINMAX - 5.0 - mV Notes 54. guaranteed at 25 °C only

Table 56. VUSB Electrical Characteristics and TA = 25 °C under nominal conditions, unless otherwise noted.

• Supplied by SWBST VSWBST- 4% - VSWBST+3 V IUSB Operating Current Load Range ILMIN to ILMAX 0.0 - 100 mA VUSB ACTIVE MODE - DC VUSB Output Voltage VOUT
• V INMIN < VIN < VINMAX ILMIN < IL < ILMA VNOM - 4% 3.3 VNOM + 4% V VUSBLOPP Load Regulation
• 0 < IL < ILMAX from DM / DP, For any VINMIN < VIN < VINMAX - 1.0 - mV/mA VUSBLIPP Line Regulation
• V INMIN < VIN < VINMAX, For any ILMIN < IL < ILMAX - - 20 mV VUSBSOCP Over-current Protection threshold
• V INMIN < VIN < VINMAX, Short-circuit VOUT to ground IMAX+20% - - mA IUSBLIM Current Limit
• V INMIN < VIN < VINMAX - 180 - mA

and TA = 25 °C under nominal conditions, unless otherwise noted.

67 Freescale Semiconductor

7.5.6.8 VUSB2

NSS12100UW3TCG. For stability reasons, a small minimum ESR may be required. A short-circuit condition will shut down the VUSB2 regulator and generate an interrupt for SCPI. when working with the internal pass FET is 65 mA, and could be up to 350 mA when working with an external PNP.

• V IN = VINMIN + 100 mV 35 40 - dB VUSBNOISE Output Noise - VIN = VINMIN IL = 75% of ILMAX
• 100 Hz – 50 kHz
• > 5 0 kHz – 1.0 MHz 1.0 0.2 V/Hz

Table 57. VUSB2 Voltage Control Table 58. VUSB2 Electrical Specification and TA = 25 °C under nominal conditions, unless otherwise noted.

• Internal pass FET
• External PNP Not exceeding PNP max power 0.0 0.0 350 mA VUSB2IN Extended Input Voltage Range
• Performance may be out of specification UVDET - 4.5 V

and TA = 25 °C under nominal conditions, unless otherwise noted.

• V INMIN < VIN < VINMAX ILMIN < IL < ILMAX VNOM - 3% VNOM VNOM + 3% V VUSB2LOPP Load Regulation
• 1 . 0 mA < IL < ILMAX For any VINMIN < VIN < VINMAX - 0.25 - mV/mA VUSB2LIPP Line Regulation
• V INMIN < VIN < VINMAX For any ILMIN < IL < ILMAX - 8.0 - mV VUSB2OCP Over-current Protection threshold
• V INMIN < VIN < VINMAX Short-circuit VOUT to GND ILMAX +20% - - mA IUSB2Q Active Mode Quiescent Current, VINMIN < VIN < VINMAX
• I L = 0, Internal PMOS configuration
• V INMIN < VIN < VINMAX IL = 0, External PNP configuration µA IUSB2LIM Current Limit
• External PNP mode only
• V INMIN < VIN < VINMAX
• Current on VUSB2DRV multiplied by  of external PNP transistor (IUSB2DRV when VSUSB2DRV is forced to LDOVDD) - 4.62* - mA VUSB2 LOW-POWER MODE - DC VUSB2 Output Voltage VOUT
• V INMIN < VIN < VINMAX ILMINLP < IL < ILMAXLP VNOM - 3% VNOM VNOM + 3% V IUSB2 Current Load Range ILMINLP to ILMAXLP 0.0 - 3.0 mA IUSB2Q Low-power Mode Quiescent Current
• V INMIN < VIN < VINMAX IL = 0 - 8.0 - µA VUSB2 ACTIVE MODE - AC VUSB2PSRR PSRR, IL = 75% of ILMAX 20 Hz to 20 kHz
• V IN = VINMIN + 100 mV
• V IN = VNOM + 1.0 V dB VUSB 2NOISE Output Noise Density, VIN = VINMIN IL = 75% of ILMAX
• 100 Hz – 1.0 kHz
• > 1 . 0 kHz – 1.0 MHz 1.0 dB/dec V/Hz tON-VUSB2 Turn-on Time
• Enable to 90% of end value VIN = VINMIN, VINMAX IL = 0 - - 1.0 ms tOFF-VUSB2 Turn-off Time
• Disable to 10% of initial value VIN = VINMIN, VINMAX IL = 0 0.05 - 10 ms VUSB2OS- START Start-up Overshoot
• V IN = VINMIN, VINMAX IL = 0 - 1.0 2.0 VUSB2LO TRANSIENT Transient Load Response, VIN = VINMIN, VINMAXx
• VUSB2=01, 10, 11
• VUSB2=00 1.0 2.0 mV

and TA = 25 °C under nominal conditions, unless otherwise noted.

69 Freescale Semiconductor

• I L = 75% of ILMAX - 5.0 8.0 mV tMOD-VUSB2 Mode Transition Time
• From low-power to active and from active to low-power VIN = VINMIN, VINMAX IL = ILMAXLP - - 100 µs VUSBMODE RES Mode Transition Response
• From low-power to active and from active to low-power VIN = VINMIN, VINMAX IL = ILMAXLP - 1.0 2.0

and TA = 25 °C under nominal conditions, unless otherwise noted.

7.5.6.9 VDAC

efficiency during deep sleep modes. A short-circuit condition will shut down the VDAC regulator and generate an interrupt for SCPI. current along with an external PNP, is 250 mA. Table 59. VDAC Voltage Control Table 60. VDAC Electrical Specification and TA = 25 °C under nominal conditions, unless otherwise noted.

• Not exceeding PNP max power 0.0 - 250 mA VDACIN Extended Input Voltage Range
• Performance may be out of specification UVDET - 4.5 V VDAC ACTIVE MODE – DC VDAC Output Voltage VOUT
• V INMIN < VIN < VINMAX ILMIN < IL < ILMAX VNOM – 3% VNOM VNOM + 3% V VDACLOPP Load Regulation
• 1 . 0 mA < IL < ILMAX For any VINMIN < VIN < VINMAX - 0.20 - mV/mA VDACLIPP Line Regulation
• V INMIN < VIN < VINMAX For any ILMIN < IL < ILMAX - 5.0 - mV VDACOCP Over-current Protection threshold
• V INMIN < VIN < VINMAX Short-circuit VOUT to GND ILMAX +20% - - mA IDACQ Active Mode Quiescent Current
• V INMIN < VIN < VINMAX IL = 0 - 30 - µA

71 Freescale Semiconductor

7.5.6.10 VGEN1, VGEN2

• External PNP mode only
• V INMIN < VIN < VINMAX
• Current on VDACDRV multiplied by  of external PNP transistor (IDACDRV when VDACDRV is forced to LDOVDD) - 3.2* - mA VDAC LOW-POWER MODE – DC - VDACMODE=1 VDAC Output Voltage VOUT
• V INMIN < VIN < VINMAX ILMINLP < IL < ILMAXLP VNOM – 3% VNOM VNOM + 3% V IDAC Current Load Range ILMINLP to ILMAXLP 0.0 - 3.0 mA IDACQ Low-power Mode Quiescent Current
• V INMIN < VIN < VINMAX IL = 0 - 8.0 - µA VDAC ACTIVE MODE – AC VDACPSRR PSRR - IL = 75% of ILMAX 20 Hz to 20 kHz
• V IN = VINMIN + 100 mV
• V IN = VNOM + 1.0 V dB VDACNOISE Output Noise Density, VIN = VINMIN IL = 75% of ILMAX
• 100 Hz – 1.0 kHz
• > 1 . 0 kHz – 10 kHz
• > 1 0 kHz – 1.0 MHz -115 -126 -132 V/Hz VDACSPURS Spurs
• 32.768 kHz and harmonics - - -120 dB tON-VDAC Turn-on Time
• Enable to 90% of end value VIN = VINMIN, VINMAX IL = 0 - - 1.0 ms tOFF-VDAC Turn-off Time
• Disable to 10% of initial value VIN = VINMIN, VINMAX, IL = 0 0.05 - 10 ms VDACOS- START Start-up Overshoot
• V IN = VINMIN, VINMAX IL = 0 - 1.0 2.0 VDACLO TRANSIENT Transient Load Response
• V IN = VINMIN, VINMAX - 1.0 2.0 VDACLI TRANSIENT Transient Line Response
• I L = 75% of ILMAX - 5.0 8.0 mV tMODE-VDAC Mode Transition Time
• From low-power to active VIN = VINMIN, VINMAX IL = ILMAXLP - - 100 µs VDACMODE RES Mode Transition Response
• From low-power to active and from active to low-power VIN = VINMIN, VINMAX IL = ILMAXLP - 1.0 2.0

and TA = 25 °C under nominal conditions, unless otherwise noted.

reduced power dissipation in the pass devices. VGEN2 is powered directly from the battery. the ON Semiconductor NSS12100UW3TCG. For stability, a small minimum ESR may be required. A short-circuit condition will shut down the VGEN1 and VGEN2 regulators, and generate an interrupt for SCPI. Table 61. VGEN1 Control Register Bit Assignments Table 62. VGEN2 Control Register Bit Assignments

73 Freescale Semiconductor

Table 63. VGEN1 Electrical Specification and TA = 25 °C under nominal conditions, unless otherwise noted.

• All settings 1.75 1.8 1.85 V IGEN1 Operating Current Load Range ILMIN to ILMAX
• Not exceeding PNP max power 0.0 - 250 mA VGEN1 ACTIVE MODE – DC VGEN1 Output Voltage VOUT
• V INMIN < VIN < VINMAX ILMIN < IL < ILMAX VNOM – 3% VNOM VNOM + 3% V VGEN1LOPP Load Regulation
• 1 . 0 mA < IL < ILMAX For any VINMIN < VIN < VINMAX - 0.25 - mV/mA VGEN1LIPP Line Regulation
• V INMIN < VIN < VINMAX For any ILMIN < IL < ILMAX - 5.0 - mV VGEN1OCP Over-current Protection threshold
• V INMIN < VIN < VINMAX Short-circuit VOUT to GND ILMAX +20% - - mA IGEN1Q Active Mode Quiescent Current
• V INMIN < VIN < VINMAX IL = 0 - 12 - µA IGEN1LIM Current Limit
• V INMIN < VIN < VINMAX - 375 - mA VGEN1 ACTIVE MODE - AC VGEN1PSRR PSRR
• I L = 75% of ILMAX 20 Hz to 20 kHz VGEN1[2:0] = 000-101
• IL = 75% of ILMAX 20 Hz to 20 kHz VGEN1[2:0] = 110-111 dB VGEN 1NOISE Output Noise Density, VIN = VINMIN IL = 75% of ILMAX
• 100 Hz – 1.0 kHz
• > 1 . 0 kHz – 10 kHz
• > 1 0 kHz – 1.0 MHz -115 -126 -132 V/Hz VGEN 1SPURS Spurs
• 32.768 kHz and harmonics - - -100 dB tON-VGEN1 Turn-on Time
• Enable to 90% of end value VIN = VINMIN, VINMAX, IL = 0 - - 1.0 ms tOFF-VGEN1 Turn-off Time
• Disable to 10% of initial value VIN = VINMIN, VINMAX, IL = 0 0.01 - 10 ms VGEN1OS- START Start-up Overshoot
• V IN = VINMIN, VINMAX, IL = 0 - 1.0 2.0 VGEN1LO TRANSIENT Transient Load Response
• V IN = VINMIN, VINMAX - 1.0 2.0 VGEN1LI TRANSIENT Transient Line Response
• I L = 75% of ILMAX - 5.0 8.0 mV

• From low-power to active and from active to low-power VIN = VINMIN, VINMAX IL = ILMAXLP - - 100 µs VGEN 1MODERES Mode Transition Response
• From low-power to active and from active to low-power VIN = VINMIN, VINMAX IL = ILMAXLP - 1.0 2.0

Table 64. VGEN2 Electrical Specification and TA = 25 °C under nominal conditions, unless otherwise noted.

• All settings, BP biased VNOM +0.25 - 4.5 V IGEN2 Operating Current Load Range ILMI to ILMAX
• Internal Pass FET 0.0 - 50 mA IGEN2 Operating Current Load Range ILMIN to ILMAX
• External PNP, Not exceeding PNP max power 0.0 - 250 mA VGEN2IN Extended Input Voltage Range
• BP Biased, Performance may out of specification for output levels VGEN2 [2:0] = 010 to 111 UVDET - 4.5 mV/mA VGEN2 ACTIVE MODE - DC VGEN2 Output Voltage VOUT
• V INMIN < VIN < VINMAX ILMIN < IL < ILMAX VNOM - 3% VNOM VNOM + 3% V VGEN2LOPP Load Regulation
• 1 . 0 mA < IL < ILMAX, For any VINMIN < VIN < VINMAX - 0.20 - mV/mA VGEN2LIPP Line Regulation
• V INMIN < VIN < VINMAX For any ILMIN < IL < ILMAX - 8.0 - mV VGEN2OCP Over-current Protection threshold
• V INMIN < VIN < VINMAX Short-circuit VOUT to GND ILmax +20% - - mA IGEN2Q Active Mode Quiescent Current
• V INMIN < VIN < VINMAX IL = 0 - 30 - µA IGEN2LIM Current Limit
• External PNP mode only
• V INMIN < VIN < VINMAX
• Current on VGEN2DRV multiplied by  of external PNP transistor (IGEN2DRV when VGEN2DRV is forced to LDOVDD) - 3.4* - mA

and TA = 25 °C under nominal conditions, unless otherwise noted.

75 Freescale Semiconductor

• V INMIN < VIN < VINMAX ILMINLP < IL < ILMAXLP VNOM - 3% VNOM VNOM + 3% V IGEN2 Current Load Range ILMINLP to ILMAXLP 0.0 - 3.0 mA IGEN2Q Low-power Mode Quiescent Current
• V INMIN < VIN < VINMAX IL = 0 - 8.0 - µA VGEN2 ACTIVE MODE - AC VGEN2PSRR PSRR - IL = 75% of ILmax, 20 Hz to 20 kHz
• V IN = VINMIN + 100 mV
• V IN = VNOM + 1.0 V dB VGEN 2NOISE Output Noise Density - VIN = VINMIN IL = 75% of ILMAX
• 100 Hz – 1.0 kHz
• > 1 . 0 kHz – 10 kHz
• > 1 0 kHz – 1.0 MHz -115 -126 -132 V/Hz tON-VGEN22 Turn-on Time
• Enable to 90% of end value VIN = VINMIN, VINMAX, IL = 0 - - 1.0 ms VGEN2 ACTIVE MODE - AC (CONTINUED) tOFF-VGEN2 Turn-off Time
• Disable to 10% of initial value VIN = VINMIN, VINMAX, IL = 0 0.05 - 10 ms VGEN2OS- START Start-up Overshoot
• V IN = VINMIN, VINMAX IL = 0 - 1.0 2.0 VGEN2LO TRANSIENT Transient Load Response
• V IN = VINMIN, VINMAX - 1.0 2.0 VGEN2LI TRANSIENT Transient Line Response
• I L = 75% of ILMAX - 5.0 8.0 mV tMODE-VGEN2 Mode Transition Time
• From low-power to active VIN = VINMIN, VINMAX, IL = ILMAXLP - - 100 µs VGEN 2MODERES Mode Transition Response
• From low-power to active and from active to low-power VIN = VINMIN, VINMAX, IL = ILMAXLP - 1.0 2.0

and TA = 25 °C under nominal conditions, unless otherwise noted.

7.6 Analog to Digital Converter

The ADC core is a 10 bit converter. The ADC core and logic run at an internally generated frequency of approximately 1.33 MHz.

7.6.1 Input Selector

The ADC has 16 input channels. Table 65 gives an overview of the characteristics of each of these channels. Table 65. ADC Inputs Table 66. ADC Input Specification

77 Freescale Semiconductor

7.6.2 Control

ADCDONEI is generated. The interrupt can be masked with the ADCDONEM bit. conversions from 0 to 600 S. ADDLY3[3:0] controls the delay after the final conversion, and is only valid when ADCONT is high. ADDLY1, 2, and 3 are set to 0 by default. Table 67. ADDLYx[3:0]

7.6.3 Dedicated Readings

7.6.3.1 Channel 0 to 2 Reserve

Channel 0 to Channel 2 are reserved.

7.6.3.2 Channel 3 Die Temperature

The relation between the read out code and temperature is given in Table 68.

7.6.3.3 Channel 4 to 7 Reserved

Channel 4 to Channel 7 are reserved.

7.6.3.4 Channel 8 Coin Cell Voltage

below the coin cell disconnect threshold, the voltage at LICELL can still be read through the ADC.

7.6.3.5 Channel 9-11 ADIN9-ADIN11

There are 3 general purpose analog input channels that can be measured through the ADIN9-ADIN11 pins.

7.6.3.6 Channel 12-15 ADIN12-ADIN15

respectively mapped on ADC channels 12, 13, 14, and 15.

7.6.4 Touch Screen Interface

a reference. Several readout possibilities are offered. respectively mapped on ADC channels 12, 13, 14, and 15. Table 68. Die Temperature Voltage Reading Table 69. Coin Cell Voltage Reading Coding

79 Freescale Semiconductor

is masked. Pen detection is only active when TSEN is low. screen conversions, the ADC does not rely on TSREF and the reference is disabled. represents the voltage drop over the contact resistance created by the known current source, multiplied by 2. screen is touched with a finger or a stylus. to read channels indicated in TSSEL0, TSSEL1, and TSSEL2. When TSSTOP[2:0] = 111, all eight addresses will be read. system to be pre-biased for the change in touch screen plate polarity. It will read out as ‘0’. the ADC sequence will be overwritten by the touch screen data. the last address is converted. TSDLY1, 2, and 3 are set to 0 by default. Table 70. Touch Screen Action Select

00 Dummy to discharge TSREF cap

01 X - plate

10 Y - plate

11 Contact

Table 71. TSDLYx[3:0]

1. Enable the touch screen with TSEN
2. Select the touch screen sequence by programming the TSSEL0-TSSEL7 SPI bits.
3. Program the delay between the conversi on via the TSDLY1 and TSDLY2 settings.
4. Trigger the ADC via the TSSTART SPI bit
5. Wait for an interrupt indicating the conversion is done TSDONEI
6. And then read out the data in the ADRESULTx registers

7.6.5 ADC Specifications

Table 72. ADC Electrical Specifications and TA = 25 °C under nominal conditions, unless otherwise noted.

• Single-ended voltage readings
• Differential readings 0.0 -1.2 2.4 1.2 V tCONVERT Conversion Time per channel - - 10 s Integral Non-linearity - - 3 LSB Differential Non-linearity - - 1 LSB Zero Scale Error (Offset) - - 5 LSB Full Scale Error (Gain) - - 10 LSB Drift Over-temperature - - 1 LSB tON-OFF-ADC Turn On/Off Time - - 31 s

81 Freescale Semiconductor

7.7 Auxiliary Circuits

7.7.1 General Purpose I/Os

configuration these outputs can only be pulled up to 2.5 V maximum. Each individual GPIO has a dedicated 16-bit control register. Table 73 provides detailed bit descriptions. Table 73. GPIOLVx Control (55)

7.7.2 PWM Outputs

registers shown in Table 74.The base clock will be the 2.0 MHz divided by 32.

7.8 Serial Interfaces

1. x= 0, 1, 2, or 3 depending of the GPIO channel it is being

Table 74. PWMx Duty Cycle Programming Table 75. PWMx Clock Divider Programming

000000 Base Clock

000001 Base Clock / 2

001111 Base Clock / 16

111111 Base Clock / 64

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7.8.1 SPI Interface

integrated pull-down), then the bus configuration will be latched for SPI mode. conventions for bit positions corresponding to common functionality with previous generation FSL products.

7.8.1.1 SPI Interface Description

For a SPI read, the first bit sent to the IC must be a zero indicating a SPI read cycle. Next, the six bit address is sent MSB first. them in on the rising edge of the SPI clock. internal contents of the field addressed do not change when the 32nd CLK is sent. For a SPI write the first bit sent to the 34709 must be a one indicating a SPI write cycle. Next the six bit address is sent MSB first. transferred into the actual registers on the falling edge of the 32nd CLK. enough to clock all 24 data bits properly. To start a new SPI transfer, the CS line must be toggled low and then pulled high again. The MISO line will be tri-stated while CS is low. at the beginning of the SPI sequence. Table 76. SPI / I2C Bus Configuration

1. CS held low at Cold Start, configures the interface for SPI mode; once activated, CS functions as the SPI Chip Select.
2. CS tied to VCOREDIG at Cold St art, configures the interface for I2C mode; the pin is not used in I2C mode, other than for configuration.
3. In I 2C mode, the MOSI pin is hardwired to ground, or VCOREDIG is used to select between two possible addresses.

Figure 19. SPI Transfer Protocol Single Read/Write Access Figure 20. SPI Transfer Protocol Multiple Read/Write Access

7.8.1.2 SPI Timing Requirements

Figure 21. SPI Interface Timing Diagram

24 Bits Data

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7.8.2 I 2C Interface

7.8.2.1 I 2C Configuration

as a “SPI map” and bits as “SPI bits”; however, it should be understood that access reverts to I2C mode when configured as such. on CS will be deactivated if the high state is detected (indicating I2C mode). part can function only as an I2C slave device, not as a host.

7.8.2.2 I 2C Device ID

supports 7-bit addressing only; support is not provided for 10-bit or general Call addressing. “0”, leaving the LSB A0 for board level configuration. The designated address then is defined as: 000100-A0. Table 77. SPI Interface Timing Specifications(61)

1. This table reflects a maxi mum SPI clock frequency of 26 MHz.

7.8.2.3 I 2C Operation

“I2C specification” in the web search string field. be due to a premature STOP command from the master, for example. 3-bytes will be sent out unless a STOP command or NACK is received prior to completion. Figure 22. I2C 3-byte Write Example

87 Freescale Semiconductor

Figure 23. I2C 3-byte Read Example

7.8.3 SPI/I 2C Specification

Table 78. SPI/I2C Electrical Characteristics and TA = 25 °C under nominal conditions, unless otherwise noted.

• Output sink 100 A 0.0 - 0.2 V VMISOHI/ VINTHI Output High MISO, INT
• Output source 100 A SPIVCC-0.2 - SPIVCC V VCC-SPI SPIVCC Operating Range 1.75 - 3.6 V tMISOET MISO Rise and Fall Time, CL = 50 pF, SPIVCC = 1.8 V
• S P I D R V [1:0] = 00
• S P I D R V [1:0] = 01 (default)
• S P I D R V [1:0] = 10
• S P I D R V [1:0] = 11 6.0 2.5 3.0 2.0 ns Device Addr ess Regi ster Address Device AddressPacket Type START 0 0 R/W 1623 8 15 1623 07815 A C K STOP A C K A C K START R/W A C K A C K NA CK AP Li te Dr i ven Data (b y t e 2) Packet Type AP Lite Driven Data (b y t e 1 ) AP Lite Driven Data (b y t e 0 ) Host can also drive another Start instead of Stop 0 1Host SDA (to MISO) Slave SDA (from MISO) Host SDA (to MIS O) Slave SDA (from MISO) Continuation Device Data Device Data Device Data

7.9 Configuration Registers

7.9.1 Register Set structure

generically applicable to the register set accessible by either interface. Table 79. Register Set

0 Interrupt Status 0 16 Memory A 32 Regulator Mode 0 48 ADC5

1 Interrupt Mask 0 17 Memory B 33 GPIOLV0 Control 49 ADC6

2 Interrupt Sense 0 18 Memory C 34 GPIOLV1 Control 50 ADC7

3 Interrupt Status 1 19 Memory D 35 GPIOLV2 Control 51 Reserved

4 Interrupt Mask 1 20 RTC Time 36 GPIOLV3 Control 52 Supply Debounce

5 Interrupt Sense 1 21 RTC Alarm 37 Reserved 53 Reserved

6 Power Up Mode Sense 22 RTC Day 38 Reserved 54 Reserved

7 Identification 23 RTC Day Alarm 39 Reserved 55 PWM Control

8 Regulator Fault Sense 24 Regulator 1 A/B Voltage 40 Reserved 56 Unused

9 Reserved 25 Regulator 2 & 3 Voltage 41 Unused 57 Unused

10 Reserved 26 Regulator 4 A/B Voltage 42 Unused 58 Unused

11 Reserved 27 Regulator 5 Voltage 43 ADC 0 59 Unused

12 Unused 28 Regulator 1 & 2 Mode 44 ADC 1 60 Unused

13 Power Control 0 29 Regulator 3, 4 and 5 Mode 45 ADC 2 61 Unused

14 Power Control 1 30 Regulator Setting 0 46 ADC 3 62 Unused

15 Power Control 2 31 SWBST Control 47 ADC4 63 Unused

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7.9.2 Specific Registers

7.9.2.1 IC and Version Identification

The IC and other version details can be read via the identification bits. These are hardwired on the chip and described in Table 80.

7.9.2.2 Embedded Memory

can be maintained in these registers to validate confidence in the RTC contents when power is restored after a power cut event. Alternatively, the banks can be used for any system need for bit retention with coin cell backup. Table 80. IC Revision Bit Assignment

7.9.3 SPI/I 2C Register Map

The complete SPI bitmap is given in Table 81. Table 81. SPI/I2C Register Map

Analog Integrated Circuit Device Data

91 Freescale Semiconductor

Functional Block Description 0x05 Interrupt Sense 1 Table 87 RO hXX_XX_XX 23 22 21 20 19 18 17 16 - - - GPIOLV3S GPIOLV2S GPIOLV1S GPIOLV0S - 15 14 13 12 11 10 9 8 CLKS THERM130S THERM125S THERM120S THERM110S - - - 7 6 5 4 3 2 1 0 - - - PWRON2S PWRON1S - - - 0x06 Power Up Mode Sense Table 88 RO h00_00_XX 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - PUMS5S PUMS4S PUMS3S PUMS2S PUMS1S ICTESTS 0x07 Identification Table 89 RO h00_0X_XX 23 22 21 20 19 18 17 16 PAGE[4:0] - - - 15 14 13 12 11 10 9 8 - - - - FAB[2:0] FIN[2] 7 6 5 4 3 2 1 0 FIN[1:0] FULL_LAYER_REV[2:0] METAL_LAYER_REV[2:0] 0x08 Regulator Fault Sense Table 90 R0 h00_XX_XX 23 22 21 20 19 18 17 16 REGSCPEN - - - - - - - 15 14 13 12 11 10 9 8 - - - VGEN2FAULT VGEN1FAULT VDACFAULT VUSB2FAULT VUSBFAULT 7 6 5 4 3 2 1 0 SWBSTFAULT SW5FAULT SW4BFAULT SW4AFAULT SW3FAULT SW2FAULT RSVD SW1FAULT 0x09 To 0x0C Unused NU h00_00_00 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - - 0x0D Power Control 0 Table 93 R/W h00_00_40 23 22 21 20 19 18 17 16 COINCHEN VCOIN[2:0] - - - - 15 14 13 12 11 10 9 8 - - - - - - PCUTEXPB - 7 6 5 4 3 2 1 0 - CLK32KMCUEN USEROFFCLK DRM USEROFFSPI WARMEN PCCOUNTEN PCEN 0x0E Power Control 1 Table 94 R/W h00_00_00 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 PCMAXCNT[3:0] PCCOUNT[3:0] 7 6 5 4 3 2 1 0 PCT[7:0] 0x0F Power Control 2 Table 95 R/W h42_23_00 23 22 21 20 19 18 17 16 STBYDLY[1:0] ON_STBY_LP - - CLKDRV[1:0] - 15 14 13 12 11 10 9 8 - SPIDRV[1:0] WDIRESET - STANDBYINV GLBRSTTMR[1:0] 7 6 5 4 3 2 1 0 PWRON2DBNC[1:0] PWRON1BDBNC[1:0] - PWRON2RSTEN PWRON1RSTEN RESTARTEN

Analog Integrated Circuit Device Data Freescale Semiconductor 92 34709 Functional Block Description 0x10 Memory A Table 96 R/W h00_00_00 23 22 21 20 19 18 17 16 MEMA[23:16] 15 14 13 12 11 10 9 8 MEMA[15:8] 7 6 5 4 3 2 1 0 MEMA[7:0] 0x11 Memory B Table 97 R/W h00_00_00 23 22 21 20 19 18 17 16 MEMB[23:16] 15 14 13 12 11 10 9 8 MEMB[15:8] 7 6 5 4 3 2 1 0 MEMB[7:0] 0x12 Memory C Table 98 R/W h00_00_00 23 22 21 20 19 18 17 16 MEMC[23:16] 15 14 13 12 11 10 9 8 MEMC[15:8] 7 6 5 4 3 2 1 0 MEMC[7:0] 0x13 Memory D Table 99 R/W h00_00_00 23 22 21 20 19 18 17 16 MEMD[23:16] 15 14 13 12 11 10 9 8 MEMD[15:8] 7 6 5 4 3 2 1 0 MEMD[7:0] 0x14 RTC Time Table 100 R/W h0X_XX_XX 23 22 21 20 19 18 17 16 RTCCALMODE[1:0] RTCCAL[4:0] TOD[16] 15 14 13 12 11 10 9 8 TOD[15:8] 7 6 5 4 3 2 1 0 TOD[7:0] 0x15 RTC Alarm Table 101 R/W h01_FF_FF 23 22 21 20 19 18 17 16 RTCDIS SPARE SPARE SPARE SPARE SPARE SPARE TODA[16] 15 14 13 12 11 10 9 8 TODA[15:8] 7 6 5 4 3 2 1 0 TODA[7:0] 0x16 RTC Day Table 102 R/W h00_XX_XX 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - DAY[14:8] 7 6 5 4 3 2 1 0 DAY[7:0] 0x17 RTC Day Alarm Table 103 R/W h00_7F_FF 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - DAYA[14:8] 7 6 5 4 3 2 1 0 DAYA[7:0]

Analog Integrated Circuit Device Data

93 Freescale Semiconductor

Functional Block Description 0x18 Regulator 1A/B Voltage Table 104 R/WM hXX_XX_XX 23 22 21 20 19 18 17 16 RSVD[5:0] RSVD[5:4] 15 14 13 12 11 10 9 8 RSVD[3:0] SW1ASTBY[5:2] 7 6 5 4 3 2 1 0 SW1ASTBY[1:0] SW1A[5:0] 0x19 Regulator 2&3 Voltage Table 105 R/WM hXX_XX_XX 23 22 21 20 19 18 17 16 - SW3STBY[4:0] - SW3[4] 15 14 13 12 11 10 9 8 SW3[3:0] SW2STBY[5:2] 7 6 5 4 3 2 1 0 SW2STBY[1:0] SW2[5:0] 0x1A Regulator 4 Voltage Table 106 R/WM hXX_XX_XX 23 22 21 20 19 18 17 16 SW4BHI[1:0] SW4BSTBY[4:0] SW4B[4] 15 14 13 12 11 10 9 8 SW4B[3:0] SW4AHI[1:0] SW4ASTBY[4:3] 7 6 5 4 3 2 1 0 SW4ASTBY[2:0] SW4A[4:0] 0x1B Regulator 5 Voltage Table 107 R/WM h00_XX_XX 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - SW5TBY[4:0] - - 7 6 5 4 3 2 1 0 - - - SW5[4:0] 0x1C Regulator 1, 2 Mode Table 108 R/WM h52_80_48 23 22 21 20 19 18 17 16 PLLX PLLEN SW2DVSSPEED[1:0] SW2UOMODE SW2MHMODE SW2MODE[3:2] 15 14 13 12 11 10 9 8 SW2MODE[1:0] - - - - - - 7 6 5 4 3 2 1 0 SW1DVSSPEED[1:0] SW1AUOMODESW1AMHMODE SW1AMODE[3:0] 0x1D Regulator 3, 4, 5 Mode Table 109 R/WM h52_08_48 23 22 21 20 19 18 17 16 SW5UOMODE SW5MHMODE SW5MODE[3:0] SW4BUOMODE SW4BMHMODE 15 14 13 12 11 10 9 8 SW4BMODE[3:0] SW4AUOMODE SW4AMHMODE SW4AMODE[3:2] 7 6 5 4 3 2 1 0 SW4AMODE[1:0] SW3UOMODE SW3MHMODE SW3MODE[3:0] 0x1E Regulator Setting 0 Table 110 R/WM h00_XX_XX 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - VUSB2[1:0] VPLL[1:0] VGEN2[2] 7 6 5 4 3 2 1 0 VGEN2[1:0] VDAC[1:0] - VGEN1[2:0] 0x1F SWBST Control Table 111 R/WM h00_00_0X 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 SPARE SWBSTSTBYMODE[1:0] SPARE SWBSTMODE[1:0] SWBST[1:0]

Analog Integrated Circuit Device Data Freescale Semiconductor 94 34709 Functional Block Description 0x20 Regulator Mode 0 Table 112 R/WM h0X_XX_XX 23 22 21 20 19 18 17 16 - - - VUSB2MODE VUSB2STBY VUSB2EN VUSB2CONFIG VPLLSTBY 15 14 13 12 11 10 9 8 VPLLEN VGEN2MODE VGEN2STBY VGEN2EN VGEN2CONFIG VREFDDREN - - 7 6 5 4 3 2 1 0 - VDACMODE VDACSTBY VDACEN VUSBEN - VGEN1STBY VGEN1EN 0x21 GPIOLV0 Control Table 113 R/W h00_38_0X 23 22 21 20 19 18 17 16 - - - - - - - SPARE 15 14 13 12 11 10 9 8 SRE1 SRE0 PUS1 PUS0 PUE DSE ODE PKE 7 6 5 4 3 2 1 0 INT1 INT0 DBNC1 DBNC0 HYS DOUT DIN DIR 0x22 GPIOLV1 Control Table 114 R/W h00_38_0X 23 22 21 20 19 18 17 16 - - - - - - - SPARE 15 14 13 12 11 10 9 8 SRE1 SRE0 PUS1 PUS0 PUE DSE ODE PKE 7 6 5 4 3 2 1 0 INT1 INT0 DBNC1 DBNC0 HYS DOUT DIN DIR 0x23 GPIOLV2 Control Table 115 R/W h00_38_0X 23 22 21 20 19 18 17 16 - - - - - - - SPARE 15 14 13 12 11 10 9 8 SRE1 SRE0 PUS1 PUS0 PUE DSE ODE PKE 7 6 5 4 3 2 1 0 INT1 INT0 DBNC1 DBNC0 HYS DOUT DIN DIR 0x24 GPIOLV3 Control Table 116 R/W h00_38_0X 23 22 21 20 19 18 17 16 - - - - - - - SPARE 15 14 13 12 11 10 9 8 SRE1 SRE0 PUS1 PUS0 PUE DSE ODE PKE 7 6 5 4 3 2 1 0 INT1 INT0 DBNC1 DBNC0 HYS DOUT DIN DIR 0x25 to 0x2A Unused NU h00_00_00 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - - 0x2B ADC 0 Table 119 R/W h00_00_00 23 22 21 20 19 18 17 16 SPARE SPARE SPARE TSPENDETEN SPARE TSSTOP[2:0] 15 14 13 12 11 10 9 8 TSHOLD TSCONT TSSTART TSEN SPARE SPARE SPARE THERM 7 6 5 4 3 2 1 0 SPARE ADSTOP[2:0] ADHOLD ADCONT ADSTART ADEN 0x2C ADC 1 Table 120 R/W h00_00_00 23 22 21 20 19 18 17 16 TSDLY3[3:0] TSDLY2[3:0] 15 14 13 12 11 10 9 8 TSDLY1[3:0] ADDLY3[3:0] 7 6 5 4 3 2 1 0 ADDLY2[3:0] ADDLY1[3:0]

Analog Integrated Circuit Device Data

95 Freescale Semiconductor

Functional Block Description 0x2D ADC 2 Table 121 R/W h00_00_00 23 22 21 20 19 18 17 16 ADSEL5[3:0] ADSEL4[3:0] 15 14 13 12 11 10 9 8 ADSEL3[3:0] ADSEL2[3:0] 7 6 5 4 3 2 1 0 ADSEL1[3:0] ADSEL0[3:0] 0x2E ADC 3 Table 122 R/W h00_00_00 23 22 21 20 19 18 17 16 TSSEL7[1:0] TSSEL6[1:0] TSSEL5[1:0] TSSEL4[1:0] 15 14 13 12 11 10 9 8 TSSEL3[1:0] TSSEL2[1:0] TSSEL1[1:0] TSSEL0[1:0] 7 6 5 4 3 2 1 0 ADSEL7[3:0] ADSEL6[3:0] 0x2F ADC 4 Table 123 R/W h00_00_00 23 22 21 20 19 18 17 16 ADRESULT1[9:2] 15 14 13 12 11 10 9 8 ADRESULT1[1:0] - - ADRESULT0[9:6] 7 6 5 4 3 2 1 0 ADRESULT0[5:0] - - 0x30 ADC 5 Table 124 R/W h00_00_00 23 22 21 20 19 18 17 16 ADRESULT3[9:2] 15 14 13 12 11 10 9 8 ADRESULT3[1:0] - - ADRESULT2[9:6] 7 6 5 4 3 2 1 0 ADRESULT2[5:0] - - 0x31 ADC 6 Table 125 R/W h00_00_00 23 22 21 20 19 18 17 16 ADRESULT5[9:2] 15 14 13 12 11 10 9 8 ADRESULT5[1:0] - - ADRESULT4[9:6] 7 6 5 4 3 2 1 0 ADRESULT4[5:2] - - 0x32 ADC 7 Table 126 R/W h00_00_00 23 22 21 20 19 18 17 16 ADRESULT7[9:2] 15 14 13 12 11 10 9 8 ADRESULT7[9:2] - - ADRESULT6[9:6] 7 6 5 4 3 2 1 0 ADRESULT6[5:0] - - 0x33 Unused NU h00_00_00 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - - 0x34 Supply Debounce Table 128 R/W h03_00_00 23 22 21 20 19 18 17 16 - - - - - - DIE_TEMP_DB[1:0] 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - VBATTDB[1:0] - -

7.9.4 SPI Register’s Bit Description

Table 82. Register 0, Interrupt Status 0

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Table 83. Register 1, Interrupt Mask 0

Table 84. Register 2, Interrupt Sense 0 Table 85. Register 3, Interrupt Status 1

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Table 86. Register 4, Interrupt Mask 1

Table 87. Register 5, Interrupt Sense 1

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Table 88. Register 6, Power-up Mode Sense Table 89. Register 7, Identification

Table 90. Register 8, Regulator Fault Sense

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Table 91. Register 9, Reserved Table 92. Register 10 to 12, Unused Table 93. Register 13, Power Control 0

1. Reset by RTCPORB but not during a GLBRST (global reset)

Table 94. Register 14, Power Control 1 Table 95. Register 15, Power Control 2

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Table 96. Register 16, Memory A

Table 97. Register 17, Memory B

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Table 98. Register 18, Memory C Table 99. Register 19, Memory D

Table 100. Register 20, RTC Time

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1. Reset by RTCPORB but not during a GLBRST (global reset)

Table 101. Register 21, RTC Alarm

1. Reset by RTCPORB but not dur ing a GLBRST (global reset)

Table 102. Register 22, RTC Day

1. Reset by RTCPORB but not dur ing a GLBRST (global reset)

111 Freescale Semiconductor

Table 103. Register 23, RTC Day Alarm

1. Reset by RTCPORB but not during a GLBRST (global reset)

Table 104. Register 24, Regulator 1A/B Voltage

Table 105. Register 25, Regulator 2 & 3 Voltage Table 106. Register 26, REgulator 4A/B

113 Freescale Semiconductor

Table 107. Register 27, REgulator 5 Voltage Table 108. Register 28, Regulators 1 & 2 Operating Mode

1. SWxMODE[3:0] bits will be reset to their default values by the start-up sequencer, based on PUMS settings. An enabled switch will

default to APS mode for both Normal and Standby operation. Table 109. Register 29, Regulators 3, 4, and 5 Operating Mode

115 Freescale Semiconductor

1. SWxMODE[3:0] bits will be reset to t heir default values by the start-up sequencer, based on PUMS settings. An enabled regulator will

default to APS mode for both Normal and Standby operation. Table 110. Register 30, Regulator Setting 0 Table 111. Register 31, SWBST Control

Table 112. Register 32, Regulator Mode 0 VUSBEN 3 R/W RESETB 1 VUSB enable (PUMS4:1=[0100]).

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Table 113. Register 33, GPIOLV0 Control

Table 114. Register 34, GPIOLV1 Control

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Table 115. Register 35, GPIOLV2 Control

Table 116. Register 36, GPIOLV3 Control

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Table 117. Register 37 - 40, Reserved Table 118. Register 41 - 42, Unused

Table 119. Register 43, ADC 0 TSEN 12 R/W DIGRESETB 0 Enable the touch screen from low-power mode. TSSTART 13 R/W DIGRESETB 0 Request a start of the ADC Reading Sequencer for touch screen readings. TSCONT 14 R/W DIGRESETB 0 Run ADC reads of touch screen continuously when high or one time when low. Table 120. Register 44, ADC 1 This will allow delay before the ADC readings.

123 Freescale Semiconductor

This will allow delay between each of ADC readings in a set. ADC readings to prevent code replacement in the system. general purpose ADC readings to prevent code replacement in the system. valid between subsequent wrap around reading sequences with TSCONT mode. Table 121. Register 45, ADC 2

Table 122. Register 46, ADC 3 TSSEL00 8 R/W DIGRESETB 0 Touch screen Selection to place in ADRESULT0. TSSEL10 10 R/W DIGRESETB 0 Touch screen Selection to place in ADRESULT1. TSSEL20 12 R/W DIGRESETB 0 Touch screen Selection to place in ADRESULT2. TSSEL30 14 R/W DIGRESETB 0 Touch screen Selection to place in ADRESULT3. TSSEL40 16 R/W DIGRESETB 0 Touch screen Selection to place in ADRESULT4. TSSEL50 18 R/W DIGRESETB 0 Touch screen Selection to place in ADRESULT5. TSSEL60 20 R/W DIGRESETB 0 Touch screen Selection to place in ADRESULT6.

125 Freescale Semiconductor

TSSEL70 22 R/W DIGRESETB 0 Touch screen Selection to place in ADRESULT7. Table 123. Register 47, ADC 4

Table 124. Register 48, ADC5

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Table 125. Register 49, ADC6

Table 126. Register 50, ADC7 Table 127. Register 51, Reserved Table 128. Register 52, Supply Debounce

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Table 129. Register 53 - 54, Reserved Table 130. Register 55, PWM Control Table 131. Register 56 - 63, Unused

8 Typical Applications

component references and additional components such as filters, refer to the individual sections.

8.1 Application Diagram

Figure 24. Typical Application Schematic

32.768 KHz

131 Freescale Semiconductor

8.2 Bill of Material

Table 132. 34709 Bill of Material (69)

1 U1 1 34709 Freescale PMIC

2 C1 1 10 F TDK Battery Filter

3 C25 1 100 nF VSRTC

6 C31 1 100 pF VDDLP

7 C30 1 100 nF VCOREREF

9 C28 1 100 nF Coin cell

11 C26, C27 2 18 pF Oscillator load capacitors

12 R3, R4 2 100 k RESETB, RESETBMCU Pull-ups

13 R20 1 100 k SDWNB Pull-up

15 D7 1 Diode BAS52 Infineon Boost diode

16 C16 1 10 F 16 V Boost Output Capacitor

• 1 . 0 H VLS252010ET-1R0N (TDK)
• 1 . 0 H BRL3225T1ROM (Taiyo Yuden)
• 1.0 uH LPS4012-102NL (Coilcraft)

19 C3, C4 2 22 F Buck 1 Output Capacitor

21 D1 1 Diode BAS3010-03LRH Infineon SW1LX diode

23 C6 1 22 F Buck 2 Output Capacitor

25 D2 1 Diode BAS3010-03LRH Infineon SW2LX diode

27 C8 1 10 F Buck 3 Output Capacitor

29 D3 1 Diode BAS3010-03LRH Infineon SW3LX diode

31 C10 1 10 F Buck 4A Output Capacitor

33 D4 1 Diode BAS3010-03LRH Infineon SW4ALX diode

35 C12 1 10 F Buck 4B Output Capacitor

37 D5 1 Diode BAS3010-03LRH Infineon SW4BLX diode

39 C14 1 22 F Buck 5 Output Capacitor

41 D6 1 Diode BAS3010-03LRH Infineon SW5LX diode

45 C17 1 100 nF VREFDDR input Capacitor

133 Freescale Semiconductor

8.3.1 General board recommendations

1. It is recommended to use an 4 layer board stack-up arranged as follows:

• High-current signal
• G N D
• S i g n a l
• High-current signal 2. Allocate TOP and BOTTOM PCB Layers for POWER ROUTING (high-current signals), copper-pour the unused area. 3. Add one GND inner layer to reduce Current loops to the maximum between layers.

8.3.2 General Routing Requirements

1. Some recommended things to keep in mind for manufacturability:

• Via in pads require a 4.5 mil Minimum annular ring. Pad must be 9.0 mils larger than the hole
• Max copper thickness for lines less than 5.0 mils wide is 0.6 oz copper
• Minimum allowed spacing between line and hole pad is 3.5 mils
• Minimum allowed spacing between line and line is 3.0 mils 2. Care must be taken with SWxFB pins traces. These signals are susceptible to noise and must be routed far away from power, clock, or high-power signals, like the ones on the SWxIN, SWx, SWxLX, SWBSTIN, SWBST, and SWBSTLX pins. VDAC

46 Q2 1

48 Q1 1

52 Q3 1

1. Freescale does not assume liability, endorse, or warrant components from external manufacturers that are referenced in circuit

1. Shield feedback traces of the switching regulators and keep them as short as possible (trace them on the bottom so the

ground and power planes shield these traces).

1. Avoid coupling trace between important signal/low noise supplies (like VREFCORE, VCORE, VCOREDIG) from any

switching node (i.e. SW1ALXx, SW2LX, SW3LX, SW4ALX, SW4BLX, SW5LX, and SWBSTLX).

1. Make sure that all components related to an specific block are referenced to the corresponding ground, e.g. all

components related to the SW1 converter must referenced to GNDSW1A1 and GNDSW1A2.

8.3.3 Parallel Routing Requirements

• CLK is the fastest signal of the system, so it must be given special care. Here are some tips for routing the communication signals:
• To avoid contamination of these delicate signals by nearby high-power or high-frequency signals, it is a good practice to shield them with ground planes placed on adjacent layers. Make sure the ground plane is uniform throughout the whole signal trace length.

Figure 25. Recommended Shielding for Critical Signals.

• These signals can be placed on an outer layer of the board to reduce their capacitance in respect to the ground plane.
• The crystal connected to the XTAL1 and XTAL2 pins must not have a ground plane directly below.
• The following are clock signals: CLK, CLK32K, CLK32KMCU, XTAL1, and XTAL2. These signals must not run parallel to each other, or in the same routing layer. If it is necessary to run clock signals parallel to each other, or parallel to any other signal, then follow a MAX PARALLEL rule as follows:
• Up to one inch parallel length – 25 mil minimum separation
• Up to two inches parallel length – 50 mil minimum separation
• Up to three inches parallel length – 100 mil minimum separation
• Up to four inches parallel length – 250 mil minimum separation
• Care must be taken with these signals not to contaminate analog signals, as they are high-frequency signals. Another good practice is to trace them perpendicularly on different layers, so there is a minimum area of proximity between signals.

8.3.4 Switching Regulator Layout Recommendations

1. Per design, the 34709 is designed to operate with only one input bulk capacitor. However, it is recommended to add a

range of 100 nF and should be placed right next to or under the IC, closest to the IC pins.

1. Make high-current ripple traces low inductance (short, high W/L ratio).
2. Make high-current traces wide or copper islands.
3. Make high-current traces SYMETRICAL for dual–phase regulators (SW1, SW4).

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Figure 26. Generic Buck Regulator Architecture Figure 27. Recommended Layout for Switching Regulators.

8.4 Thermal Considerations

8.4.1 Rating Data

The thermal rating data of the packages has been simulated with the results listed in Table 5.

Analog Integrated Circuit Device Data Freescale Semiconductor 136 34709 Typical Applications forced convection on both 1s and 2s2p test boards. It is anticipated that the generic name, Theta-JA, will continue to be commonly used. The JEDEC standards can be consulted at http://www.jedec.org/

8.4.2 Estimation of Junction Temperature

An estimation of the chip junction temperature TJ can be obtained from the equation TJ = TA + (RθJA x PD) with TA = Ambient temperature for the package in °C RJA = Junction to ambient thermal resistance in °C/W PD = Power dissipation in the package in W The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. Unfortunately, there are two values in common usage: the value determined on a single layer board RθJA and the value obtained on a four layer board RθJMA. Actual application PCBs show a performance close to the simulated four layer board value although this may be somewhat degraded in case of significant power dissipated by other components placed close to the device. At a known board temperature, the junction temperature TJ is estimated using the following equation TJ = TB + (RθJB x PD) with TB = Board temperature at the package perimeter in °C RθJB = Junction to board thermal resistance in °C/W PD = Power dissipation in the package in W When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. See Functional Block Description for more details on thermal management.

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9 Packaging

The 34709 is offered in an 130 balls, 8.0x8.0 mm, 0.5 mm pitch MAPBGA package.

9.1 Package Mechanical Dimensions

www.freescale.com and perform a keyword search for the drawing’s document number. Table 133. Package Drawing Information

Figure 28. 8 x 8 Package Mechanical Dimension

139 Freescale Semiconductor

Figure 29. 8 x 8 Package Mechanical Dimension

10 Reference Section

Table 134. MC34709 Reference Documents

Analog Integrated Circuit Device Data

141 Freescale Semiconductor

Revision History

REVISION DATE DESCRIPTION OF CHANGES 1.0 8/2012

• Initial release
• Corrected doc number to MC34709, corrected part number PC34709VK
• Removed Freescale Confidential Proprietary on page 1

Document Number: MC34709 Rev. 1.0 Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits on the information in this document. Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: http://www.reg.net/v2/webservices/Freescale/Docs/TermsandConditions.htm Freescale, the Freescale logo, AltiVec, C-5, CodeTest, CodeWarrior, ColdFire, C-Ware, Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, Qorivva, StarCore, and Airfast, BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, MagniV, MXC, Platform in a Package, Processor expert, QorIQ Qonverge, QUICC Engine, Ready Play, SMARTMOS, TurboLink, Vybrid, and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc. How to Reach Us: Home Page: freescale.com Web Support: freescale.com/support