MC33HB2000 NXP | Alldatasheet
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Technical content
10 A H-bridge, SPI programmable brushed DC motor driver
1 General description
motor control applications within the specified current and voltage limits. The MC33HB2000 is able to control inductive loads with peak currents greater than 10 A. an analog feedback signal proportional to the load current.
2 Simplified application diagram
Figure 1. Simplified application diagram
3 Features and benefits
- Advanced diagnostic reporting via a serial peripheral interface (SPI): charge pump undervoltage, overvoltage, and undervoltage on VPWR, short to ground and short to VPWR for each output, open load, temperature warning and overtemperature shutdown
- Thermal management: Excellent thermal resistance of <1.0 °C/W between junction and case (exposed pad)
- Eight selectable slew rates via the SPI: 0.25 V/μs to more than 16 V/μs for EMI and thermal performance optimization
NXP Semiconductors MC33HB2000 Data sheet: advance information Rev. 6.0 — 9 August 2018
- Four selectable current limits via the SPI: 5.4/7.0/8.8/10.7 A covering a wide range of
applications
- Three package sizes available in SOIC, PQFN and HVQFN to meet footprint and application requirement
- Can be operated without SPI with default slew rate of 2.0 V/μs and a 7.0 A current limit threshold
- Highly accurate real-time current feedback through a current mirror output signal with less than 5.0 % error
- Drives inductive loads in a full H-bridge or Half-bridge configuration
- Overvoltage protection places the load in high-side recirculation (braking) mode with notification in H-bridge mode
- Wide operating range: 5.0 V to 28 V operation
- Low RDS(on) integrated MOSFETs: Maximum of 235 mΩ (TJ = 150 °C) for each MOSFET
- Internal protection for overtemperature, undervoltage, and short-circuit by signaling the error condition and disabling the outputs
- I/O pins can withstand up to 36 V
- AEC-Q100 grade 1 qualified
4 Applications
- Electronic throttle control
- Exhaust gas recirculation control (EGR)
- Turbo, swirl and whirl and waste flap control
- Electric pumps, motor control and auxiliaries
5 Ordering information
This section describes the part numbers available to be purchased along with their differences. Table 1. Orderable parts [1] To order parts in tape and reel, add the R2 suffix to the part number. numbers for this device, go to http://www.nxp.com and perform a part number search.
6 Internal block diagram
Figure 2. Internal block diagram
7 Pinning information
7.1 Pinning
Figure 3. Pin configuration for 32-pin SOICW Figure 4. Pin configuration for 32-pin PQFN
Figure 5. Pin configuration for 28-pin HVQFN
7.2 Pin description
For functional description of each pin see Section 7.3 "Functional pin description". Table 2. Pin description referenced 0.25 % of the high-side output current.
NXP Semiconductors MC33HB2000 Data sheet: advance information Rev. 6.0 — 9 August 2018 Symbol 32-pin SOICW 32-pin PQFN 28-pin HVQFN Pin function Definition PGND 15, 16, 17, 18 20, 21, 22, 23 16, 17, 18, 19, GND Power ground for OUT1 and OUT2[1] OUT2 22, 23 27, 28 22, 23 A_Out Source of HS2 and drain of LS2 CCP 26 31 26 A_Out External reservoir capacitor connection for the internal charge pump; connected to VPWR CS_B 27 32 27 D_In SPI control chip select bar input pin VDDQ 28 1 28 Supply Logic level bias MISO 29 2 1 D_Out Provides digital data from HB2000 to the MCU SCLK 30 3 2 D_In SPI control clock input pin MOSI 31 4 3 D_In SPI control data input pin from MCU DGND 32 5 4 GND Ground for logic[1] EP EP EP EP GND Thermal exposed pad – connected to substrate[1] [1] All PGND, AGND, DGND and EP pins must be connected together with very low-impedance on the PCB.
7.3 Functional pin description
7.3.1 Logic bias input (VDDQ)
VDDQ supplies a level shifted bias voltage for the logic level outputs designed to be read by the microprocessor/microcontroller. This pin applies the logic supply voltage to MISO making the output logic levels compliant to logic systems from 3.3 V to 5.0 V. See Section 10.3 "VDDQ digital output supply voltage" for more details.
7.3.2 Supply voltage (VPWR)
VPWR is the power supply input for the H-bridge. The input voltage range with full performance is from 8.0 V to 28 V. In either case, the maximum allowable transient voltage during the event such as load dump is 40 V. Exceeding this limit could result in an avalanche breakdown, as discussed in Section 11.3 "Output avalanche protection". A Zener clamp and/or an appropriately valued capacitor are common methods of limiting the transient. This pin must be externally protected against application of a reverse voltage through an external inverted N-channel MOSFET, diode or switched relay.
7.3.3 Outputs (OUT1 and OUT2)
The OUT1 and OUT2 outputs drive the bi-directional DC motor. Each output has two internal N-channel MOSFETs connected in a Half-bridge configuration between VPWR and ground. Only one internal MOSFET is ON at one time for each output. The turn ON/ OFF slew times are determined by the selected SPI slew time register contents.
7.3.4 Inputs (IN1 and IN2)
The IN1 and IN2 inputs determine the direction of current flow in the H-Bridge by directing the PWM input to one of the low-side MOSFETs (see Table 21). When a change in the current direction is commanded via the microprocessor/microcontroller, the PWM switches from one low-side MOSFET to the other without shoot-through current
NXP Semiconductors MC33HB2000 Data sheet: advance information Rev. 6.0 — 9 August 2018 in the H-Bridge. Both MOSFETs cannot be turned ON simultaneously in the same Half- bridge.
7.3.5 Enable inputs (ENBL)
The ENBL pin at logic [0] disables all four of the output drivers (outputs tri-stated) and the part goes into Sleep mode. The ENBL pin at logic [1] enables the part functionality.
7.3.6 Disable inputs (DIS)
The DIS pin at logic [1] disables all four of the output drivers (outputs tri-stated) and the part goes into Standby mode. However, it does not put the part in Sleep mode. The DIS pin is at logic [0] does not inhibit the output.
7.3.7 Current recopy (CFB)
High-side FETs have a current recopy feature through an internal current-mirror which supplies 1/400th of the load current. The current recopy has better than 5.0 % accuracy for load currents between 2.0 A and 10 A. An external resistor may be connected to the CFB pin (RCFB), which sets current to voltage gain. The circuit operates properly in the presence of high-frequency noise. An external capacitor is used to provide filtering. Tie to GND through a resistor if not used.
7.3.8 Charge pump capacitor (CCP)
This pin is the charge pump output pin for connecting the external charge pump reservoir capacitor. A typical value is 100 nF. The capacitor must be connected from the CCP pin to the VPWR pin. The part does not operate properly without the external reservoir capacitor.
7.3.9 Serial peripheral interface (SPI)
The MC33HB2000 has a serial peripheral interface consisting of Chip Select (CS_B), Serial Clock (SCLK), Master IN Slave Out (MISO), and Master Out Slave In (MOSI). This device is configured as a SPI slave and is daisy-chainable (single CS_B for multiple SPI slaves). See Section 9.6 "16-bit SPI interface" for detailed information on the SPI.
7.3.9.1 Serial clock (SCLK)
The SCLK input is the clock signal input for synchronization of serial data transfer. This pin has TTL/CMOS level compatible input voltages, which allows proper operation with microprocessors using a 3.3 V to 5.0 V supply. When CS_B is asserted low, the MOSI data reads on the SCLK falling edge and the MISO data is updated on the SCLK rising edge.
7.3.9.2 Serial data output (MISO)
The MISO is the SPI data out pin. When CS_B is asserted (low), the MSB is the first bit of the word transmitted on MISO and the LSB is the last bit of the word transmitted on
active, the output is “rail to rail”, depending on the voltage at the VDDQ pin.
7.3.9.3 Serial data input (MOSI)
using a 3.3 V to 5.0 V supply.
7.3.9.4 Chip select (CS_B)
7.3.10 Status fault (FS_B)
8 General product characteristics
8.1 Maximum ratings
Table 3. Maximum ratings permanent damage to the device.
8.2 Thermal characteristics
Table 4. Thermal ratings
[1] The circuit specification describes IC operation within the parametric operating range defined in the electrical characteristic table. or permanent damage to the device. enter 33xxx), and review parametrics. temperature, air flow, power dissipation of other components on the board, and board thermal resistance. [5] Per JEDEC JESD51-2 with natural convection for horizontally oriented board. Board meets JESD51-9 specification for 1s or 2s2p board, respectively. [7] Thermal resistance between the die and the solder pad on the bottom of the package. Interface resistance is ignored. [8] Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters (Ψ) are not available, the thermal characterization parameter is written as Psi-JT. [9] Per JEDEC JESD51-6 with forced convection for horizontally oriented board. Board meets JESD51-9 specification for 1s or 2s2p board, respectively.
8.3 Operating conditions
following data, unless otherwise noted. Table 5. Nominal operation into and negative out of the specified pin. TJ = −40 °C to 150 °C, unless otherwise specified.
Table 6. Supply current consumption VPWR = 5.0 V to 28 V, TJ = −40 °C to 150 °C, unless otherwise specified.
8.3.1 Reverse battery
current must be populated in the application, as shown in Figure 22 (with a diode).
8.3.2 Digital I/Os characteristics
Table 7. Digital I/Os characteristics VPWR = 5.0 V to 28 V, TJ = −40 °C to 150 °C, unless otherwise specified.
NXP Semiconductors MC33HB2000 Data sheet: advance information Rev. 6.0 — 9 August 2018
9 General IC functional description and application information
9.1 Introduction
The MC33HB2000 is a programmable H-bridge, power integrated circuit (IC) designed to drive DC motors or bi-directional solenoid controlled actuators, such as throttle control or exhaust gas recirculation actuators. It is particularly well suited for the harsh environment found in automotive power train systems. The MC33HB2000 is designed to specifically address the ISO 26262 safety standard requirements. The key characteristic of this versatile driver is configurability. The selectable slew rate permits the customer to choose the slew rate needed for performance and noise suppression. The Serial Peripheral Interface (SPI) allows the system microprocessor to clear the fault register, select a programmable current limit, and select the slew rate. The MC33HB2000 is designed to drive a bi-directional DC motor using pulse-width modulation (PWM) for speed and torque control. A current mirror output provides an analog feedback signal proportional to the load current. SPI diagnostic reporting includes, open load, short-to-battery, short-to-ground, die temperature range, overvoltage, and undervoltage.
9.2 Features
- Advanced diagnostic reporting via the serial peripheral interface (SPI) – Charge pump undervoltage – Overvoltage and undervoltage on VPWR – Short to ground as well as short to VPWR for each output – Open load – Temperature warning – Overtemperature shutdown
- Excellent thermal resistance of <1.0 °C/W between junction and case (exposed pad)
- Eight selectable slew rates via the SPI from 0.25 V/μs to more than 16 V/μs, giving the user flexibility to perform trade-offs between low EMI and better thermal performance
- Active current limiting with four selectable current limits via the SPI: 5.4/7.0/8.8/10.7 A covering a wide range of applications
- Can be operated without SPI with default slew rate of 2.0 V/μs and a 7.0 A current limit threshold. See Figure 22 for operation without SPI.
- Efficient thermal management scheme by reducing the switching losses to ensure continuous operation and availability of the part under harsh operating conditions
- Accurate real-time current feedback through a current mirror output signal with less than 5.0 % error
- Configurable for full H-bridge or Half-bridge operation through the SPI
- Overvoltage protection places the load in high-side recirculation (braking) mode and signal the error condition in H-bridge mode
- Wide operating range: 5.0 V to 28 V operation
- Low RDS(on) integrated MOSFETs: Maximum 235 mΩ (TJ = 150 °C) for each MOSFET
- Internal protection for short-circuit, overtemperature, and undervoltage by signaling the error condition and disabling the outputs
- I/O pins can withstand up to 36 V
9.3 Functional block diagram
Figure 6. Functional block diagram
9.4 Functional description
9.4.1 H-bridge output drivers (OUT1 and OUT2)
9.4.2 Analog control, protection, and diagnostics
sense is available to the MCU as an analog current proportional to the load current. warning sets a flag in the SPI register when the device is approaching a protection limit. keeping the average current at the selected limit. charge pump undervoltage detection.
NXP Semiconductors MC33HB2000 Data sheet: advance information Rev. 6.0 — 9 August 2018
9.4.3 MCU interface and output control
The SPI and control logic signals are compatible with both 5.0 V and 3.3 V logic systems. The SPI provides an easy to configure interface for the MCU through programmable control of output slew rates, current limits, enabling/disabling of outputs, SPI equivalent of inputs (VIN1 and VIN2), and mode of operation (H-bridge/half-bridge). The status register makes detailed diagnostics available for protective and warning functions. The output drivers are controlled by the input signals ENBL, DIS, IN1, and IN2 using the parallel inputs and VIN1, VIN2, as well as EN using the SPI control.
9.5 Modes of operation
9.5.1 Description
The operating modes are:
- Sleep mode All MC33HB2000 functions are disabled. The current consumption does not exceed the sleep-state current specification.
- Standby mode All MC33HB2000 logic are fully operational with the outputs in a high-impedance state.
- Normal mode All MC33HB2000 functions are fully operational. Any detected faults transition the device to Fault mode.
- Fault mode Certain of functions are forced off and FS_B signal is latched to logic [0] indicating a fault.
Figure 7. Operating mode state diagram power-up sequence is initiated as illustrated in Figure 8.
Figure 8. Regulators power-up and power-down sequences deactivate. On Power-down, FS_B is activated until the internal supplies are disabled.
9.5.2 Electrical characteristics
Table 8. Electrical characteristics VPWR = 5.0 V to 28 V, TJ = −40 °C to 150 °C, unless otherwise specified. [1] ENBL is a digital input and has the characteristics defined in Table 7.
9.6.1 Description
- Full duplex, 4-wire synchronous communication
- Slave mode operation only
- Fixed SCLK polarity and phase requirements
- Fixed 16-bit command word
- SCLK operation up to 10 MHz The SPI communication works as follows:
Figure 9. SPI dynamic diagram edge, and transitions on the rising edge of SCLK. the content bits are ignored. See Table 9 for detail on timing parameters. malfunction in the communication that may come up due to hardware or software failure.
9.6.2 Electrical characteristics
Table 9. Electrical characteristics VDDQ = 3.13 V to 5.25 V, TJ = −40 °C to 150 °C, unless otherwise specified.
9.6.3 SPI fault reporting
fault status register latches a fault at the time a fault is detected.
9.6.3.1 Clearing the fault status
occurs, this is referred to as “clr_flt” throughout this document. Table 10. Timing parameters for clearing fault status status with a ‘1’ in this bit location.
9.6.3.2 SPI framing error detection
- The number of clock pulses within CS_B low is not more than 0 and an integer multiple of 16
- Register 00 is addressed for a Write operation
9.6.4 SPI mapping
Table 11. SPI register selection Table 12. Device identification (Reserved) RV0-RV3 reserved bits. Bit 4 is the device identifier. Table 13. Status [1] The default value for all bits (bit 0 to bit 11) in status register is 0 if no fault is detected in the device. Table 14. Status bits description
11 FRM SPI framing error
10 CP_U Charge pump undervoltage
9 UV VPWR undervoltage
8 OV VPWR overvoltage
7 SCP2 Short-circuit to power output 2
6 SCP1 Short-circuit to power output 1
5 SCG2 Short-circuit to ground output 2
4 SCG1 Short-circuit to ground output 1
3 OL Open load
2 OC Overcurrent - current limit has been activated
1 TW Thermal warning
0 OT Overtemperature shutdown
Table 15. Fault status mask [1] The SPI bits in “Read” section show the default values. active when this fault is active.
- 1 = Disable overvoltage protection (OV bit is warning only)
- 0 = Enable overvoltage protection in Full Bridge mode
Table 16. Configuration and control [1] The SPI bits in “Read” section show the default values. Table 17. Configuration and control bits description
12 CL Check for open load (in Full Bridge Standby mode)
- 1 = Enabled on transition from Standby to Normal mode. Execute test in Standby on transition to 1
- 0 = Disable test
11 TM Thermal Management mode
- 1 = Enable change of current limit frequency by control of tB when OTW state
- 0 = Disable change of current limit frequency by OTW, tB shall be set to the slowest setting
NXP Semiconductors MC33HB2000 Data sheet: advance information Rev. 6.0 — 9 August 2018 Bit Bit name Description
10 AL Active Current Limit mode
- 1 = Enable active current limit when overcurrent ILIM threshold has been exceeded
- 0 = Disable active current limit. Exceeding overcurrent ILIM threshold set OC flag but does not control outputs
9 ILIM1 ILIM Bit 1
8 ILIM0 ILIM Bit 0
7 SR2 Slew Rate Bit 2
6 SR1 Slew Rate Bit 1
5 SR0 Slew Rate Bit 0
4 EN Disable Outputs
- 1 = ENABLE output control when ENBL pin is high and DIS pin is low
- 0 = DISABLE output control and tri-state outputs
3 MODE Input Control mode[1]
- 1 = H-bridge control mode
- 0 = Half-bridge control mode
2 INPUT Active INPUT Control mode
- 1 = SPI control of outputs by way of VIN1 and VIN2, IN1 pin and IN2 pin are disabled
- 0 = Parallel control of outputs by way of IN1 pin and IN2 pin, VIN1 and VIN2 are disabled
1 VIN2 Virtual Input 2 (SPI equivalent of IN2)
- 1 = ON equivalent to IN2 pin at logic high in parallel mode
- 0 = OFF equivalent to IN2 pin at logic low in parallel mode
0 VIN1 Virtual Input 1 (SPI equivalent of IN1)
- 1 = ON equivalent to IN1 pin at logic high in parallel mode
- 0 = OFF equivalent to IN1 pin at logic low in parallel mode [1] When MODE=0 (Half-bridge mode): Active Current Limit mode is disabled, OV is a warning only, SC acts independent on each output, open load is disabled.
9.7 Protection and supervision
The MC33HB2000 includes supervision features which enable advanced diagnostics by monitoring the VPWR undervoltage, VPWR overvoltage and die temperature.
9.7.1 VPWR undervoltage detection
9.7.1.1 Description
When VPWR is less than VPWR_FUV longer than tVPWR all output transistors turn off and remain off until VPWR increases above the VPWR_FUV threshold by VPWR_UVHYS. While ramping up the voltage on VPWR, when VPWR increases to a voltage greater than VPWR_FUV + VPWR_UVHYS for at least tVPWR, the MC33HB2000 starts unrestricted operation.
9.7.1.2 Electrical characteristics
Table 18. VPWR_UV electrical characterization TJ = −40 °C to 150 °C, unless otherwise specified.
9.7.2 VPWR overvoltage detection
are turned on to drain the energy in the load. not reset until clr_flt conditions are satisfied.
9.7.2.1 Electrical characteristics
Table 19. VPWR_OV electrical characterization TJ = −40 °C to 150 °C, unless otherwise specified.
9.7.3 Die temperature
9.7.3.1 Description
The MC33HB2000 has temperature sensors near the center of each power device. Section 10.4.1.4 "Active current limit regulation".
after the temperature reduces THYS below the threshold.
9.7.3.2 Electrical characteristics
Table 20. OT electrical characterization VPWR = 5.0 V to 28 V, unless otherwise specified. [1] Guaranteed by characterization.
9.7.4 Truth table
Table 21. Truth table [2] When the SPI bit INPUT = 1, the SPI bit VIN1 behaves the same as IN1 and SPI bit VIN2 behaves the same as IN2. [3] Default response for FS_B, SPI programming may change the default behavior. their original operating condition, FS_B remains low until clr_flt clears the status register. register. In Half-bridge mode an overvoltage event does not change the output state. status flag is latched to a logic LOW. To reset from this condition requires the toggling of either DIS, ENBL, or VPWR or flt_clr from the SPI. Figure 10. Output operating configurations
Figure 11. H-bridge operation with ENBL = 1 and DIS = 0 Figure 12. Half-bridge operation with ENBL = 1 and DIS = 0
9.8 Error handling
Table 22. Error handling
10 Functional block description
10.1 Oscillator
A single clock module is used for all systems and filter timing.
10.1.1 Frequency modulation
electromagnetic compatibility (EMC) performance. Table 23. Frequency electrical characteristics VPWR = 5.0 V to 28 V, TJ = −40 °C to 150 °C, unless otherwise specified.
10.2 Charge pump
10.2.1 Description
supply. The maximum external load which can be connected to the CCP pin is 20 μA.
is modulated by means of the spread spectrum modulation of the main clock. Table 24. Charge pump electrical characteristics VPWR = 5.0 V to 28 V, TJ = −40 °C to 150 °C, unless otherwise specified. [1] A 20 V X7R capacitor with at least ≤ ±20 % tolerance is recommended.
10.3 VDDQ digital output supply voltage
10.3.1 Description
Figure 13. Digital output buffer supply this pin is shorted to ground or left open, the SPI MISO reports 0000h. Table 25. VDDQ electrical characterizations VDDQ = 3.13 V to 5.25 V, TJ = −40 °C to 150 °C, unless otherwise specified.
10.4 H-bridge and Half-bridge operation
10.4.1 Description
The H-bridge output control is defined by the SPI bit.
- In parallel mode, the physical inputs IN1 and IN2 control the OUT1 and OUT2 respectively
- In SPI mode, VIN1 and VIN2 control the Half-bridge outputs similar to physical inputs H-bridge control
- In parallel mode, the physical input IN1 controls direction and IN2 controls PWM
- In SPI mode, VIN1 and VIN2 control the H-Bridge outputs similar to physical inputs This device provides active recirculation through the opposing FET of each Half-bridge. Embedded protections avoid cross conduction. In Half-bridge mode, active current limit, overvoltage protection, and open load detection features are disabled. For overvoltage, there is OV warning only. Moreover, unlike H-bridge control mode, the short-circuit protection acts independently on each output. A more detailed explanation of output characteristic with respect to inputs in H-bridge as well as Half-bridge mode is explained in Section 9.7.4 "Truth table". The differences in fault priorities between the two modes is described in section Section 10.4.1.1 "H-bridge and Half-bridge fault priority".
10.4.1.1 H-bridge and Half-bridge fault priority
Table 26. H-Bridge mode fault priority
Table 27. Half-bridge mode fault priority Table 28. Fault priority description
10.4.1.2 Current recopy
10.4.1.3 Slew rate selection
setting which switches the outputs as fast as possible.
10.4.1.4 Active current limit regulation
Figure 14 presents the simplified current regulation loop.
Figure 14. Simplified current regulated loop for ILIM The active current limit threshold is selectable by the SPI in four steps from 5.0 A to 10 A. exceeds the threshold set by the current limit comparator. output to switch OFF immediately switches OFF the output and resets the ILIM circuit.
Figure 15. ILIM timing and thermal response
10.4.1.5 Open load detection in standby mode
- The device is transitioning from STBY mode to Normal mode and the CL bit is high.
- The device is in STBY mode and receives a command changing the CL bit setting
of the test, the results may not be valid.
- The circuit turns on both low-side output FETs, to discharge any residual charge
OUT2 is functional and provides normal short-circuit protection and diagnostics.
- In second stage, the circuit turns off the OUT1 low-side FET and applies an internal
Figure 16. Open load detection circuit
10.4.1.6 Open load detection in active mode
Figure 18. On the other hand, an open load is not detected if the energy stored in the shoot through phase of Figure 17. Figure 17. Open load detection circuit for active mode
Figure 18. Open load circuit operation status which is only cleared by detecting the load is not open or leaving Normal mode.
10.4.1.7 Short-circuit detection
described in Section 9.6.3.1 "Clearing the fault status".
10.4.2 Electrical characteristics
Table 29. H-bridge electrical characterization VPWR = 5.0 V to 28 V, TJ = −40 °C to 150 °C, unless otherwise specified.
NXP Semiconductors MC33HB2000 Data sheet: advance information Rev. 6.0 — 9 August 2018 Symbol Parameter Min. Typ. Max. Unit SR OUTx rising and falling slew rate, from 10 % to 90 % of VPWR, measured with 1.0 A resistive load at VPWR = 14 V SPI SR = 000 SPI SR = 001 SPI SR = 010 SPI SR = 011 SPI SR = 100 (default) SPI SR = 101 SPI SR = 110 SPI SR = 111 11.2 5.6 2.8 1.4 0.7 0.35 0.15 bypass 8.0 4.0 2.0 1.0 0.5 0.25 20.8 10.4 5.2 2.6 1.3 0.65 0.35 V/μs CURRENT SENSE IRATIO Current recopy ratio ILOAD < 2.0 A
2.0 A ≤ ILOAD < 10 A
2.5 2.5 mA IERROR Load current error, ILOAD < 2.0 A −0.100 — 0.100 A IERROR Load current error, 2.0 A ≤ ILOAD < 10 A −5.0 — 5.0 % dI/dt Load current slew rate 0.5 — — A/μs FAULT DETECTION AND CURRENT LIMIT REGULATION ILIM Current limit threshold current SPI ILIM = 00 SPI ILIM = 01 (default) SPI ILIM = 10 SPI ILIM = 11 4.0 6.0 7.3 9.0 5.4 7.0 8.8 10.7 6.8 8.0 10.3 12.5 A tB Blanking time TJ < OTW TJ ≥ OTW 256 μs SHORT-CIRCUIT SHUTDOWN ISC_LS Low-side short-circuit detection threshold current ILIM + 3.0 — ILIM + 8.0 A ISC_HS High-side short-circuit detection threshold current ILIM + 4.0 — ILIM + 9.0 A tSC Short-circuit detection filter time 5.0 — 10 μs OPEN LOAD DETECTION VOP Open load detection voltage threshold 0.6 — 0.8 V IOL Out1 pull-up current 0.8 — 1.3 mA tOP_LSD Open load detection filter time 93 — 118 μs VOLATH Open load active mode threshold VOLA = VOUTx − VPWR 160 — 360 mV [1] In an application, RDS(on) depends on charge pump loading and timing limitations, including slew rate and duty cycle. These factors determine the enhancement level of the device’s integrated high-side FETs during switching. [2] Guaranteed by characterization
Figure 19. Disable delay timing Figure 20. Output delay timing Figure 21. Slew rate
11 Applications
11.1 Introduction
schematic without SPI interface to MCU and reverse battery protection through a diode. battery" for details on reverse battery protection.
11.2 Application diagram
Figure 22. Simplified minimum application schematic (Reverse battery protection using a
Figure 23. Simplified typical application schematic (Reverse battery protection with an
11.3 Output avalanche protection
the disable logic. This could result in an unclamped inductive discharge. bridge mode, this problem is mitigated by internal overvoltage protection.
Figure 24. Output avalanche protection
12 Packaging
12.1 Package mechanical dimensions
Table 30. Package outline
NXP Semiconductors MC33HB2000 Data sheet: advance information Rev. 6.0 — 9 August 2018
NXP Semiconductors MC33HB2000 Data sheet: advance information Rev. 6.0 — 9 August 2018
NXP Semiconductors MC33HB2000 Data sheet: advance information Rev. 6.0 — 9 August 2018
NXP Semiconductors MC33HB2000 Data sheet: advance information Rev. 6.0 — 9 August 2018
NXP Semiconductors MC33HB2000 Data sheet: advance information Rev. 6.0 — 9 August 2018
NXP Semiconductors MC33HB2000 Data sheet: advance information Rev. 6.0 — 9 August 2018
NXP Semiconductors MC33HB2000 Data sheet: advance information Rev. 6.0 — 9 August 2018 HVQFN 28 lead with inspectable fillets (6X6X1.0mm)
NXP Semiconductors MC33HB2000 Data sheet: advance information Rev. 6.0 — 9 August 2018
NXP Semiconductors MC33HB2000 Data sheet: advance information Rev. 6.0 — 9 August 2018 Revision Date Description of changes 1.0 7/2014 • Initial release 2.0 2/2016 • Updated the ILIM and short-circuit thresholds
- Added thermal resistance data
- Added the specification for forward voltage drop for the output FET body diode
- Updated data sheet document format and style 5/2016 • Updated data sheet document form and style
- Updated max. value for 33HB2000EK Junction to Package Top - Natural Convection ΨJT in Table 4
- Updated the values for oscillator frequency in Table 23
- Updated min. value for open load detection filter time in Table 29 3.0 9/2016 • Corrected typo in Table 12 4.0 10/2017 • Added new part number PC33HB2000ES to Table 1
- Added note in Section 9.6.1 "Description" as per CIN 201709035I
- Updated Table 2 (added description for 28-pin HVQFN)
- Updated Table 4 (added thermal resistance data for MC33HB2000ES)
- Added new package drawings 5.0 7/2018 • Corrected Figure 9
- Updated description of parametrics in Table 9 6.0 8/2018 • Added AEC-Q100 grade 1 qualified to Section 1 and Section 3
NXP Semiconductors MC33HB2000 Data sheet: advance information Rev. 6.0 — 9 August 2018
14 Legal information
14.1 Data sheet status
Document status[1][2] Product status[3] Definition [short] Data sheet: product preview Development This document contains certain information on a product under development. NXP reserves the right to change or discontinue this product without notice. [short] Data sheet: advance information Qualification This document contains information on a new product. Specifications and information herein are subject to change without notice. [short] Data sheet: technical data Production This document contains the product specification. NXP Semiconductors reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
14.2 Definitions
Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a technical data data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the technical data data sheet.
14.3 Disclaimers
Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
NXP Semiconductors MC33HB2000 Data sheet: advance information Rev. 6.0 — 9 August 2018 Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.
14.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. SafeAssure — is a trademark of NXP B.V. SMARTMOS — is a trademark of NXP B.V.
NXP Semiconductors MC33HB2000 Data sheet: advance information Rev. 6.0 — 9 August 2018 Tables Figures Fig. 8. Regulators power-up and power-down Fig. 11. H-bridge operation with ENBL = 1 and DIS Fig. 12. Half-bridge operation with ENBL = 1 and DIS Fig. 22. Simplified minimum application schematic (Reverse battery protection using a diode Fig. 23. Simplified typical application schematic (Reverse battery protection with an external inverted N-channel MOSFET and operation
NXP Semiconductors MC33HB2000 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © NXP B.V. 2018. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 9 August 2018 Document identifier: MC33HB2000