MC33981 MOTOROLA | Alldatasheet
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Features
Single 4.0 m Ω RDS(ON) Maximum High-Side Switch PWM Capability up to 60 kHz with Duty Cycle from 5% to 100% Very Low Standby Current Slew Rate Control with External Capacitor Overcurrent and Overtemperature Pr otection, Undervoltage Shutdown and Fault Reporting Reverse Battery Protection Gate Drive Signal for External Low-Side N-Channel MOSFET with Protection Features Output Current Monitoring Temperature Feedback HIGH-SIDE SWITCH 4.0 mΩ
ORDERING INFORMATION
Range (TA) Package PC33981PNA/R2 -40°C to 125°C 16 PQFN
33981 Simplified Application Diagram
SCALE 1:1 Bottom View PNA SUFFIX CASE 1402-02 16-TERMINAL PQFN (12 X 12) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
33981 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Figure 1. 33981 Simplified Internal Block Diagram Freescale Semiconductor, Inc.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33981 TERMINAL DEFINITIONS Functional descriptions of some of these terminals can be found in the System/Application Information section beginning on page 19. Terminal Terminal Name Formal Name Definition 1 CSNS Output Current Monitoring This terminal is used to output a current proportional to the high-side OUT current and is used externally to generate a ground-referenced voltage for the microcontroller (MCU) to monitor OUT current. 2 TEMP Temperature Feedback This terminal reports an analog value proportional to the temperature of the GND flag (terminal 13). It is used by the MCU to monitor board temperature.
3 EN Enable
(Active High) This is an input used to place the device in a low current sleep mode. This terminal has an passive internal pulldown. 4 INHS Serial Input High Side The input terminal is used to di rectly control the OUT. This input has an active internal pulldown current source and requires CMOS logic levels.
5 FS Fault Status
(Active Low) This is an open drain-configured output requiring an external pull-up resistor to VDD (5.0 V) for fault reporting. When a device fault condition is detected, this terminal is active LOW. 6 INLS Serial Input Low Side The input terminal is used to directly control an external low-side N-channel MOSFET and has an active internal pulldown current source and requires CMOS logic levels. It can be controlled independently of the INHS depending of CONF terminal. 7 CONF Configuration Input This input terminal is used to manage the cross-conduction between the internal high- side N-channel MOSFET and the external low-side N-channel MOSFET. The terminal has an active internal pullup current source. When CONF is at 0 V, the two MOSFETs are controlled independently. When CONF is at 5.0 V, the two MOSFETs cannot be on at the same time. 8 OCLS Low-Side Overload This terminal sets the V DS protection level of the external low-side MOSFET. This terminal has an active internal pullup current source. It must be connected to an external resistor. 9 DLS Drain Low Side This terminal is the drain of the external low-side N-channel MOSFET. Its monitoring allows for protection features. 10 GLS Low-Side Gate This terminal is an output used to drive the gate of the external low-side N-channel MOSFET. 11 SR Slew Rate Control A capacitor connected between this terminal and the ground is used to control the output slew rate. CSNS INHS FS INLS CONF OCLS EN TEMP DLS GLS SR CBOOT OUT OUT VPWR Transparent Top View of Package GND Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
14 V PWR Positive Power Supply This terminal connects to the positive power supply and is the source input of operational power for the device. The VPWR terminal is a backside surface mount tab of the package. 15, 16 OUT Output Protected high-side power output to the load. Output terminals must be connected in parallel for operation. TERMINAL DEFINITIONS (continued) Functional descriptions of some of these terminals can be found in the System/Application Information section beginning on page 19. Terminal Terminal Name Formal Name Definition Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33981 MAXIMUM RATINGS All voltages are with respect to ground unless otherwise noted. Rating Symbol Value Unit ELECTRICAL RATINGS Power Supply Voltage Steady-State VPWR -16 to 41 V Input/Output Terminals Voltage (Note 1) VIN -0.3 to 7.0 V Output Voltage V OUT -5.0 to 41 V Continuous Output Current (Note 2) I OUT 40 A CSNS Input Clamp Current I CSNS 10 mA SR Voltage VSR -0.3 to 54 V Temperature Feedback Voltage V TEMP -0.3 to 5.0 V CBOOT Voltage CBOOT -0.3 to 54 V OCLS Voltage V OCLS -0.3 to 7.0 V Low-Side Gate Voltage V GLS -0.3 to 15 V Low-Side Drain Voltage V DLS -5.0 to 41 V ESD Voltage Human Body Model (Note 3) Machine Model (Note 4) VESD1 VESD2 ±2000 ±200 V Output Clamp Energy (Note 5) ECL TBD J THERMAL RATINGS Operating Temperature Ambient Junction TA TJ -40 to 125 -40 to 150 Storage Temperature T STG -55 to 150 °C Thermal Resistance (Note 6) Junction to Power Die Case Junction to Ambient RθJC RθJA 1.0 °C/W Peak Terminal Reflow Temperature During Solder Mounting (Note 7) TSOLDER 240 °C Power Dissipation (TA = 25°C) (Note 8) PD TBD W Notes 1. Exceeding voltage limits on INHS, INLS, CONF, CSNS, FS, TEMP, and EN terminals may cause a malfunction or permanent damage to the device. 2. Continuous high-side output rating as long as maximum junction temperature is not exceeded. Calculation of maximum output current using package thermal resistance is required. 3. ESD1 testing is performed in accordance with the Human Body Model (C ZAP = 100 pF, RZAP = 1500 Ω). 4. ESD2 testing is performed in accordance with the Machine Model (C ZAP = 200 pF, RZAP = 0 Ω) and in accordance with the system module specification with a capacitor > 0.01 µF connected from OUT to GND. 5. Active clamp energy using single-pulse method (L = 16 mH, R L = 0, VPWR = 12 V, TJ = 150°C). 6. Device mounted on a 2s2p test board per JEDEC JESD51-2. 7. Terminal soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 8. Maximum power dissipation at indicated ambient temperature in free air with no heatsink used. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit POWER INPUT Battery Supply Voltage Range Fully Operational Extended VPWR 6.0 4.5 V VPWR Supply Current Output ON, IOUT = 0 A IPWR(ON) 1 0 mA VPWR Supply Current Output OFF, EN = 5.0 V, OUT Connected to GND IPWR(SBY) 1 0 mA Sleep State Supply Current (VPWR < 14 V, EN = 0V ) TJ = 25°C TJ = 125°C IPWR(SLEEP) 5.0 µA Undervoltage Shutdown V PWR(UV) 2.0 4.0 V Undervoltage Hysteresis V PWR(UVHYS) 0 . 3 V POWER OUTPUT Output Drain-to-Source ON Resistance (IOUT = 20 A, TJ = 25°C) VPWR = 6.0 V VPWR = 10.0 V VPWR = 13 V RDS(ON) 6.0 5.0 4.0 mΩ Output Drain-to-Source ON Resistance (I OUT = 20 A, TJ = 150°C) VPWR = 6.0 V VPWR = 9.0 V VPWR = 13 V RDS(ON) 10.2 8.5 6.8 mΩ Output Drain-to-Source ON Resistance (IOUT = 20 A, TJ = 25°C) VPWR = - 13 V RDS(ON) 8 . 0 mΩ Output Overcurrent Detection Level I OCH 100 A Current Sense Ratio 9.0 V < VPWR < 16 V, CNS < 4.5V CSR 1/20000 Current Sense Ratio (CSR) Accuracy Output Current 5.0 A 10 A 30 A CSR_ACC -20 -14 -12 Current Sense Voltage Clamp ICCNS = 15 mA VCL(CSNS) 4.5 6.0 7.0 V Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33981 STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5 . 5V , 6 . 0V≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit POWER OUTPUT (continued) Overtemperature Shutdown T SD 160 175 190 °C Overtemperature Shutdown Hysteresis (Note 9) T SD(HYS) 5.0 20 °C Low-Side Gate VPWR = 6.0 V VPWR = 9.0 V VPWR = 13 V VPWR = 27 V VGSLS 6.0 9.0 V Low-Side Gate Current C = 4.7 nF I GSLS 1 0 0 mA Low-Side Overload Detection Level versus Low-Side Drain Voltage VOCLS - VDLS VDS_LS 5 0 mV Temperature Feedback TJ = 25°C TFeed TBD 4.75 TBD V Temperature Feedback Derating DT Feed - 1 2 m V / ° C CONTROL INTERFACE Input Logic High Voltage (Note 10) VIH 0.7 VDD Input Logic Low Voltage (Note 10) VIL 0.2 VDD Input Logic Voltage Hysteresis (Note 10) VIN(HYS) 100 350 750 mV Input Logic Active Pulldown Current (INHS, INLS) IDWN 5.0 20 µA Input Logic Pulldown Resistor (EN) RDWN 100 200 400 k Ω Input Active Pullup Current (OCLS) IOCLSp 1 0 0 µA Input Active Pullup Current (CONF) I CONF 1 0 µA FS Tri-State Capacitance (Note 9) CSO 20 pF FS Low-State Output Voltage VSOL 0 . 2 0 . 4 V Notes 9. Parameter is guaranteed by process monitoring but is not production tested. 10. Upper and lower logic threshold voltage range appl ies to EN, CONF, INHS, and INLS input signals. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
DYNAMIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit CONTROL INTERFACE AND POWER OUTPUT TIMING CBOOT Charge Blanking Time (Note 11) tON 20 µs Output Rising Slew Rate (Note 12) VPWR = 14 V CGATE = 6.8 nF, from 10% to 90% of VOUT, SR Capacitor = 4.7 nF SRR V/µs Output Falling Slew Rate (Note 12) VPWR = 14 V CGATE = 6.8 nF, from 90% to 10% of VOUT, SR Capacitor = 4.7 nF SRF V/µs Output Turn-ON Delay Time (Note 13) tDLY(ON) 200 ns Output Turn-OFF Delay Time tDLY(OFF) 400 ns Input Switching Frequency (Note 14) fPWM 60 kHz Notes 11. Refer to the paragraph entitled Sleep Mode on page 19. 12. Parameter is guaranteed by process monitoring but is not production tested. 13. Turn-ON delay time measured from rising edge of INHS that turns the output ON to V OUT = 0.5 V with RL= 5.0 Ω resistive load. 14. Turn-OFF delay time measured from falling edge of INHS that turns the output OFF to V OUT = VPWR -0.5 V with RL= 5.0 Ω resistive load. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
Table 1. Functional Truth Table in Normal Mode and the low side are both on. and the low side are both off. Table 2. Functional Truth Table in Fault Mode removed 33981 recovers its normal mode. a logic [0] at INLS for at least 200 µs. Freescale Semiconductor, Inc.
Figure 2. Time Delays Freescale Semiconductor, Inc.
Figure 3. Overtemperature on Output Freescale Semiconductor, Inc.
Figure 4. Overtemperature on Bootstrap Circuit or on Low-Side Gate Drive Freescale Semiconductor, Inc.
Figure 7. Overcurrent on Output Figure 8. Normal Mode. Cross-Conduction Management Freescale Semiconductor, Inc.
Figure 11. Cross-Conduction with Low Side Figure 12. Overtemperature on OUT Freescale Semiconductor, Inc.
Figure 15. RDS(ON) versus Temperature Figure 16. Sleep State Supply Current versus VPWR at 150°C Freescale Semiconductor, Inc.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33981 SYSTEM/APPLICATION INFORMATION INTRODUCTION The 33981 is a high-frequency self-protected silicon 4.0 mΩ RDS(ON) high-side switch used to replace electromechanical relays, fuses, and discrete devices in power management applications. The 33981 can be controlled by pulse-width modulation (PWM) with a frequency up to 60 kHz. It is designed for harsh environments, and it includes self-recovery features. The 33981 is suitable for loads with high inrush current, as well as motors and all types of resistive and inductive loads. A dedicated parallel input is available for an external low-side control with protection features and cross-conduction management. FUNCTIONAL DESCRIPTION Sleep Mode Sleep mode is the state of the 33981 when the EN is logic [0]. In this mode, OUT, the gate driver for the external MOSFET, and all unused internal circuitry are off to minimize current draw. The 33981 will go to the normal operating mode when the EN terminal is logic [1]. The INHS and INLS commands will be disabled typically 20 µs after the EN transitions to logic [1] to enable the charge of the bootstrap capacitor. Fault Logic This 33981 indicates the faults below as they occur by driving the FS terminal to logic [0]: Overtemperature Overcurrent fault on OUT Overload fault on the external low-side MOSFET The FS terminal will return to logic [1] when the overtemperature fault condition is removed. The two other faults are latched. Undervoltage The latched faults are reset when the VPWR voltage is below VPWR(UV). Overtemperature Fault The 33981 incorporates overtemperature detection and shutdown circuitry on OUT. Overtemperature detection also protects the bootstrap circuit (CBOOT terminal) and the low-side gate driver (GLS terminal). Overtemperature detection occurs when OUT is in the ON or OFF state and GLS is at high or low level. For OUT, an overtemperature fault condition results in OUT turning OFF until the temperature falls below TSD. This cycle will continue indefinitely until the offending load is removed. Figure 12, page 16, shows an overtemperature on OUT. An overtemperature fault on the bootstrap circuit or on the low-side gate drive results in OUT turning OFF and the GLS going to 0 V until the temperature falls below TSD. This cycle will continue indefinitely until the offending load is removed. FS terminal transition to logic [1] will be disabled typically 15 µs after to enable the charge of the bootstrap capacitor. Figure 13, page 17, shows an overtemperature on the bootstrap circuit or on the low-side gate drive. As the temperature increases, TEMP voltage decreases until thermal shutdown. Overtemperature faults force the TEMP terminal to 0 V. Overcurrent Fault on High Side The OUT terminal has a 100 A overcurrent high-detection level for maximum device protection. If at any time the current reaches this level, OUT will stay OFF and the CSNS terminal will go to 0 V. The OUT terminal is reset by a logic [0] at the INHS terminal for at least 200 µs. When INHS goes to 0 V, CSNS goes to 5.0 V. In Figure 11, page 16, the OUT terminal is short-circuited to 0 V. When the current reaches IOCH, OUT is turned OFF within 10 µs owing to internal logic circuit. Overload Fault on Low Side This fault detection is active when INLS is logic [1]. Low-side overload protection does not measure the current directly but rather its effects on the low-side MOSFET. When VGLS > VGSH and VDLS > VDSH for at least 2.5 µs, the GLS terminal goes to
0 V and the OCLS internal current source is disconnected and
OCLS goes to 0 V. The GLS terminal and the OCLS terminal are reset by a logic [0] at the INLS terminal for at least 200 µs. When connected to an external resistor, the OCLS terminal with its internal current source sets the VDSH level. By changing the external resistance, the protection level can be adjusted depending on low-side characteristics. A 3.3 kΩ resistor gives a VDSH level of 3.3 V typical. This protection circuitry measures the voltage between the drain of the low side (DLS terminal) and the 33981 ground (GND terminal). It also uses the voltage across the external resistance connected to the OCLS terminal and the GND terminal. For this reason it is key that the low-side source, the 33981 ground, and the external resistance ground connection are connected together in order to prevent false error detection due to ground shifts. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
current recirculates in the external low side. bootstrap capacitor. A typical value for this capacitor is 100 nF. An internal charge pump allows continuous MOSFET drive. off to minimize current consumption. GND is used to control the slew rate at the OUT terminal. is protected against short by a local overtemperature sensor. temperature coefficient of 10 mV/K. conditions until the maximum junction rating is reached. As Figure 17 shows, it is essential to protect this power line. line could be another solution but with a more complex drive. Figure 17. Reverse Battery Protection Freescale Semiconductor, Inc.
M M 2.2 2.20 0.05 C0.1 C0.05 C SEATING PLANE 42.0 1.95 0.00 121 (10X 0.4) M0.1 C M0.05 C A B C A B0.1 4.6 5.0 C0.1 A B 9X 0.9 2X 1.075 6X 2.05 1.55 1.85 3.55 (2) 6X 0.8 0.4 2X 1.28 0.88
6 PLACES
0.15 0.05(10X 0.5) (0.5) 10.7 10.3 C0.1 A B 11.2 10.8 (2X 0.75) 4X 1.45 1.05 C0.1 A B 5.5 5.1 C0.1 A B 2.25 1.75 (10X 0.25) 2.5 2.1 6X 1.1 0.6 2X 0.95 0.55 M0.1 C M0.05 C A B 10X 0.6 0.2 1516 PIN 1 INDEX AREA B C0.1 2X C0.1 A12 112 1615 PIN NUMBER REF . ONL Y DET AIL G CASE 1402-02 NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. THE COMPLETE JEDEC DESIGNA TOR FOR THIS 5. MINIMUM MET AL GAP SHOULD BE 0.25MM. P ACKAGE IS: HF-PQFP-N. 4. COPLANARITY APPLIES TO LEADS AND CORNER LEADS. DETAIL G VIEW ROTATED 90˚ CLOCKWISE VIEW M-M PNA SUFFIX 16-TERMINAL PQFN NONLEADED PACKAGE CASE 1402-02 ISSUE B Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33981 NOTES Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
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