33926 FREESCALE | Alldatasheet
Document overview
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Technical content
Features
- 8.0 V to 28 V Continuous Oper ation (Transient Operation from
5.0 V to 36 V)
- 225 m Ω maximum RDS(ON) @ 150°C (each H-Bridge MOSFET)
- 3.0 V and 5.0 V TTL / CMOS Logic Compatible Inputs
- Overcurrent Limiting (Regulatio n) via Internal Constant-Off- Time PWM
- Output Short Circuit Protection (Short to VPWR or Ground)
- Temperature-Dependant Current-Limit Threshold Reduction
- All Inputs have an Internal Source/Sink to Define the Default (Floating Input) States
- Sleep Mode with Current Draw < 50 µA (with Input s Floating or Set to Match Default Logic States)
Figure 1. 33926 Simplified Application Diagram
ORDERING INFORMATION
Range (TA) Package PC33926PNB/R2 - 40°C to 125°C 32 PQFN SCALE 2:1 PNB SUFFIX 98ARL10579D 32-PIN PQFN Bottom View 33926 AUTOMOTIVE THROTTLE H-BRIDGE ACTUATOR/ MOTOR EXCITER SF FB IN1 IN2 INV SLEW EN VPWR CCP OUT1 OUT2 PGND AGND MCU 33926 VPWRVDD MOTOR
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Figure 2. 33926 Simplified Internal Block Diagram
Figure 3. 33926 Pin Connections Table 1. 33926 Pin Definitions A functional description of each pin can be found in the Functional Description section beginning on page 11. directly soldered down to a wide, thick, low resistance supply plane on the PCB. main heatsinking path for the device.
8 FB Analog
9, 17, 25 NC No Connect No internal connection is made to this pin.
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H-Bridge Output 1 Source of high-side MOSFET1 and drain of low-side MOSFET1.
16 D2 Logic Input Disable Input 2
21 SF Logic
26 D1 Logic Input Disable Input 1
input with ~80 µA source so default condition = disabled. H-Bridge Output 2 Source of high-side MOSFET2 and drain of low-side MOSFET2.
32 CCP Analog
for the proper performance of the device. Table 1. 33926 Pin Definitions (continued) A functional description of each pin can be found in the Functional Description section beginning on page 11.
Analog Integrated Circuit Device Data Freescale Semiconductor 5 33926
ELECTRICAL CHARACTERISTICS
Table 2. Maximum Ratings permanent damage to the device. These parameters are not production tested.
- Device will survive repetitive transient over voltage conditions for durations not to exceed 500 ms @ duty cycle not to exceed 10%.
External protection is required to prevent device damage in case of a reverse battery condition.
- Exceeding the maximum input voltage on IN1, IN2, EN, INV, SLEW, D1, or D2 may cause a malfunction or permanent damage to the
- Exceeding the pullup resistor voltage on the open drain SF pin may cause permanent damage to the device.
- Continuous output current capability is dependent on suffi cient package heatsinking to keep junction temperature ≤ 150°C.
- ESD1 testing is performed in accordance with the Human Body Model (C ZAP = 100 pF, RZAP = 1500 Ω), ESD2 testing is performed in
accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω), and the Charge Device Model (CDM), Robotic (CZAP = 4.0pF).
- The limiting factor is junction temperatur e, taking into account the power dissipation, thermal resistance, and heat sinking provided. Brief
- Pin soldering temperature limit is for 10 seconds maximum dura tion. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
- Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
MC33xxxD enter 33xxx), and review parametrics.
- Exposed heatsink pad plus the power and ground pins comprise the main heat conduction paths. The actual RθJB (junction-to-PC board)
< 5.0°C/W for maximum current at 70°C ambient. Module thermal design must be planned accordingly.
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STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
- Device specificati ons are characterized over the range of 8.0 V ≤ VPWR ≤ 28 V. Continuous operation above 28 V may degrade device
reliability. Device is operational down to 5.0 V, but below 8.0 V the output resistance may increase by 50 percent.
- Device will survive the transient overvolt age indicated for a maximum duration of 500 ms. Transient not to be repeated more than once
- I PWR(sleep) is with Sleep mode activated and EN, D2, INV, SLEW = logic [0], and IN1, IN2, D1 = logic [1] or with these inputs left floating.
- SLEW Input Voltage Threshold parameters are guaranteed by design.
Analog Integrated Circuit Device Data Freescale Semiconductor 7 33926 STATIC ELECTRICAL CHARACTERISTICS POWER OUTPUTS OUT1, OUT2 Output-ON Resistance (15), ILOAD = 3.0A VPWR = 8.0V, TJ = 25°C VPWR = 8.0V, TJ = 150°C VPWR = 5.0V, TJ = 150°C RDS(ON) 120 225 325 mΩ Output Current Regulation Threshold TJ < 150 °C TJ > 160 °C (Fold back Region - see Figure 10) (14) ILIM 5.2 6.5 4.2 8.0 A High-Side Short Circuit Detection Threshold (Short Circuit to Ground) (14) ISCH 11 13 16 A Low-Side Short Circuit Detection Threshold (Short Circuit to VPWR) (14) ISCL 9.0 11 14 A Output Leakage Current (16), Outputs off, VPWR = 28V VOUT = VPWR VOUT = Ground IOUTLEAK –60 100 µA Output MOSFET Body Diode Forward Voltage Drop IOUT = 3.0 A VF – – 2.0 V Overtemperature Shutdown (14) Thermal Limit @ TJ Hysteresis @ TJ TLIM THYS 175 200 HIGH-SIDE CURRENT SENSE FEEDBACK Feedback Current (pin FB sourcing current) (17) I OUT = 0 mA I OUT = 300 mA I OUT = 500 mA I OUT = 1.5 A I OUT = 3.0 A I OUT = 6.0 A I FB 0.0 0.0 0.35 2.86 5.71 11.43 270 0.775 3.57 7.14 14.29 750 1.56 4.28 8.57 17.15 µA µA mA mA mA mA STATUS FLAG (18) Status Flag Leakage Current (19) V SF = 5.0 V ISFLEAK – – 5.0 µA Status Flag SET Voltage (20) I SF = 300 µA VSFLOW – – 0.4 V Notes 14. This parameter is Guaranteed By Design. 15. Output-ON resistance as measured from output to VPWR and from output to GND. 16. Outputs switched OFF via D1 or D2. 18. Status Flag output is an open drain output requiring a pullup resistor to logic VDD. 19. Status Flag Leakage Current is measured with Status Flag HIGH and not SET. 20. Status Flag Set Voltage measured with Status Flag LOW and SET with I FS = 300 µA. Maximum allowable sink current from this pin is < | 500 µA | . Maximum allowable pullup voltage < 7.0 V. Table 3. Static Electrical Characteristics (continued) values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
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DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
- The maximum PWM frequency is obtained when the device is set to Fast Slew Rate via the SLEW pin. PWM-ing when SLEW is set to
- The internal current limit circuitry produces a constant-OFF -time Pulse Width Modulation of the output current. The output load’s
frequency during current limit.
- * Output Delay is the time duration from 1.5V on the IN1 or IN2 input signal to the 20% or 80% point (dependent on the transition direction)
response signal. See Figure 4, page 9.
- The time during which the internal constant-OFF time PWM current regulation circuit has tri-stated the output bridge.
- The time during which the current regulation threshold is i gnored so that the short-circuit detection threshold comparators may have time
- * Disable Delay Time measurement is defined in Figure 5, page 9.
- Rise Time is from the 10% to the 90% level and Fall Time is from the 90% to the 10% level of the output signal with V PWR = 14 V,
RLOAD = 3.0 ohm. See Figure 6, page 9.
- Load currents ramping up to the current r egulation threshold become limited at the ILIM value (see Figure 7). The short circuit currents
is limited to non-repetitive transient events of duration not to exceed 30 seconds (see Figure 9).
- Parameter is Guaranteed By Design.
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Figure 8. Short Circuit Detection Turn-OFF Time tFAULT Figure 9. Output Current Limiting Foldback Region Current Limit Threshold Foldback. exceed 30 s maximum duration.
Analog Integrated Circuit Device Data Freescale Semiconductor 11 33926 FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION Numerous protection and operational features (speed, torque, direction, dynamic breaking, PWM control, and closed-loop control) make the 33926 a very attractive, cost- effective solution for controlling a broad range of small DC motors. The 33926 outputs are capable of supporting peak DC load currents of up to 5.0 A from a 28 VPWR source. An internal charge pump and gate drive circuitry are provided that can support external PWM frequencies up to 20 kHz. The 33926 has an analog feedback (current mirror) output pin (the FB pin) that provides a constant-current source ratioed to the active high-side MOSFETs’ current. This can be used to provide “real time” monitoring of output current to facilitate closed-loop operation for motor speed/torque control, or for the detection of open load conditions. Two independent inputs, IN1 and IN2, provide control of the two totem-pole half-bridge outputs. An input invert, INV, changes IN1 and IN2 to LOW = true logic. Two different output slew rates are selectable via the SLEW input. Two independent disable inputs, D1 and D2, provide the means to force the H-Bridge outputs to a high impedance state (all H- Bridge switches OFF). An EN pin controls an enable function that allows the IC to be placed in a power-conserving Sleep mode. The 33926 has Output Current Limiting (via Constant OFF-Time PWM Current Regulation), Output Short-Circuit Detection with Latch-OFF, and Overtemperature Detection with Latch-OFF. Once the device is latched-OFF due to a fault condition, either of the Disable inputs (D1 or D2), VPWR, or EN must be “toggled” to clear the status flag. Current limiting (Load Current Regulation) is accomplished by a constant-OFF time PWM method using current limit threshold triggering. The current limiting scheme is unique in that it incorporates a junction temperature- dependent current limit threshold. This means that the current limit threshold is “reduced to around 4.2 A” as the junction temperature increases above 160°C. When the temperature is above 175°C, overtemperature shutdown (latch-OFF) will occur. This combination of features allows the device to continue operating for short periods of time (< 30 seconds) with unexpected loads, while still retaining adequate protection for both the device and the load. FUNCTIONAL PIN DESCRIPTION POWER GROUND AND ANALOG GROUND (PGND AND AGND) The power and analog ground pins should be connected together with a very low impedance connection. POSITIVE POWER SUPPLY (VPWR) VPWR pins are the power supply inputs to the device. All VPWR pins must be connected together on the printed circuit board with as short as possible traces, offering as low impedance as possible between pins. STATUS FLAG (SF) This pin is the device fault status output. This output is an active LOW open drain structure requiring a pullup resistor to VDD. The maximum VDD is < 7.0 V. Refer to Table 5, Truth Table, page 14 for the SF Output status definition. INPUT INVERT (INV) The Input Invert Control pin sets IN1 and IN2 to LOW = TRUE. This is a Schmitt trigger input with ~ 80 µA sink; the default condition is non-inverted. If IN1 and IN2 are set so that the current is being commanded to flow through the load attached between OUT1 and OUT2, changing the logic level at INV will have the effect of reversing the direction of current commanded. Thus, the INV input may be used as a “forward/ reverse” command input. If both IN1 and IN2 are the same logic level, then changing the logic level at INV will have the effect of changing the bridge’s output from freewheeling high to freewheeling low or vice versa. SLEW RATE (SLEW) The SLEW pin is the logic input that selects fast or slow slew rate. Schmitt trigger input with ~ 80 µA sink so the default condition is SLOW. When SLEW is set to SLOW, PWM-ing should be limited to frequencies less than 11 kHz in order to allow the internal high-side driver circuitry time to fully enhance the high-side MOSFETs. INPUT 1,2 AND DISABLE INPUT 1,2 (IN1, IN2, AND D1, D2) These pins are input control pins used to control the outputs. These pins are 3.0 V/ 5.0 V CMOS-compatible inputs with hysteresis. IN1 and IN2 independently control OUT1 and OUT2, respectively. D1 and D2 are complementary inputs used to tri-state disable the H-Bridge outputs. When either D1 or D2 is SET (D1 = logic HIGH or D2 = logic LOW) in the disable state, outputs OUT1 and OUT2 are both tri-state disabled; however, the rest of the device circuitry is fully operational and the supply IPWR(STANDBY) current is reduced to a few mA. Refer to Table 3, Static Electrical Characteristics, page 6.
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FUNCTIONAL PIN DESCRIPTION H-BRIDGE OUTPUT (OUT1, OUT2) These pins are the outputs of the H-Bridge with integrated free-wheeling diodes. The bridge output is controlled using the IN1, IN2, D1, and D2 inputs. The outputs have PWM current limiting above the ILIM threshold. The outputs also have thermal shutdown (tri-state latch-OFF) with hysteresis as well as short circuit latch-OFF protection. A disable timer (time t b) is incorporated to distinguish between load currents that are higher than the ILIM threshold and short circuit currents. This timer is activated at each output transition. CHARGE PUMP CAPACITOR (CCP) This pin is the charge pump output pin and connection for the external charge pump reservoir capacitor. The allowable value is from 30 nF to 100 nF. This capacitor must be connected from the CCP pin to the VPWR pin. The device cannot operate properly without the external reservoir capacitor. ENABLE INPUT (EN) The EN pin is used to place the device in a Sleep mode so as to consume very low currents. When the EN pin voltage is a logic LOW state, the device is in the Sleep mode. The device is enabled and fully operational when the EN pin voltage is logic HIGH. An internal pulldown resistor maintains the device in Sleep mode in the event EN is driven through a high impedance I/O or an unpowered microcontroller, or the EN input becomes disconnected. FEEDBACK (FB) The 33926 has a feedback output (FB) for “real time” monitoring of H-Bridge high-side output currents to facilitate closed-loop operation for motor speed and torque control. The FB pin provides current sensing feedback of the H-Bridge high-side drivers. When running in the forward or reverse direction, a ground-referenced 0.24% of load current is output to this pin. Through the use of an external resistor to ground, the proportional feedback current can be converted to a proportional voltage equivalent and the controlling microcontroller can “read” the current proportional voltage with its analog-to-digital converter (ADC). This is intended to provide the user with only first-order motor current feedback for motor torque control. The resistance range for the linear operation of the FB pin is 100 < RFB < 300 W. If PWM-ing is implemented using the disable pin inputs (either D1 or D2), a small filter capacitor (~1.0 µF) may be required in parallel with the RFB resistor to ground for spike suppression.
Figure 10. Operating States
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Figure 11. 33926 Power Stage Operation Table 5. Truth Table HIGH, X = HIGH or LOW, and Z = High Impedance. All output power transistors are switched off.
- In the event of an undervoltage condition, the outputs tri-state and status flag is SET logic LOW. Upon undervoltage recovery, status
flag is reset automatically or automatically cleared and the outputs are restored to their original operating condition.
- When a short circuit or overtemperature condition is detected, the power outputs are tri-state latched-OFF independent of the input
signals and the status flag is latched to logic LOW. To reset from this condition requires the toggling of either D1, D2, EN, or VPWR.
exceeds 160 °C, the ILIM threshold decreases to 4.2 A. gear-reduction train to be handled. permitted only for non-repetitive durations < 30 seconds. prolonged operation in the current-foldback region. overtemperature threshold limit minus the hysteresis. will also reset the 33926 from the fault condition. capacitor with sufficiently low ESR (see Figure 12). Figure 12. Avalanche Protection
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the VPWR by-pass capacitor may need to be substantially larger. Figure 13. 33926 Typical Application Schematic
Analog Integrated Circuit Device Data Freescale Semiconductor 17 33926 PACKAGING PACKAGE DIMENSIONS PACKAGING PACKAGE DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using the 98Axxxxxxxxx listed below. PNB SUFFIX 32-PIN PQFN PLASTIC PACKAGE 98ARL10579D ISSUE B
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application, and packaging information is provided in the datasheet. heat source (P), a single junction temperature (TJ), and thermal resistance (RθJA). according to the standards listed below. Figure 14. Surface Mount for Power PQFN Table 6. Thermal Performance Comparison
- Per JEDEC JESD51-2 at natural convection, still air
- 2s2p thermal test board per JEDEC JESD51-5 and
- Per JEDEC JESD51-8, with the board temperature on the
center trace near the center lead.
- Single layer thermal test board per JEDEC JESD51-3 and
- Thermal resistance between the die junction and the
bottom side, remaining surfaces insulated.
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Figure 15. Thermal Test Board
Figure 16. Device on Thermal Test Board RθJA Figure 17. Transient Thermal Resistance RθJA,
1 W Step response, Device on Thermal Test Board Area A = 600 (mm2)
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REVISION HISTORY
1.0 3/2006 • Converted to Freescale format, Implemented changes listed below.
- Implemented revision history page. 2.0 9/2006 • Updated Figure 2. 33926 Simplified Internal Block Diagram.
- Revised Table2. Maximum Ratings
- Continuous Output Current changed fr om 5.5A to 5.0A (Parameter changed in the text through the document).
- ESD Voltage: added Charge Device Model.
- Peak Pin Reflow Temperature During Sol der Mounting changed from 260 to 250 deg.C.
- Revised Table 3. Static Electrical Characteristics
- Output Current Regulation Threshold: Min value changed from 5.5A to 5.2A.
- High-Side Short Circuit Detection Thres hold - Parameter Guaranteed by Design.
- Low-Side Short Circuit Detection Threshold - Parameter Guaranteed by Design.
- Feedback Current: Parameter values updated.
- Status Flag SET Voltage: Max value changed from 1.0V to 0.4V.
- Revised Table 4. Dynamic Electrical Characteristics
- Output OFF Delay: Max. value changed from 18 µs to 12 µs.
- Output Rise and Fall Time: Max value changed from 8.0 µs to 6.0 µs.
- Short Circuit / Overtemperature Turn-OFF (Latch-OFF) Time: Typ and Max values changed from
- Charge Pump Operating Frequency: Typ 7 MHz, new parameter added into the table. Note 25: condition changed from Iout = 3.0A to Rload = 600 ohm.
- Added Figure 10. 33926 Power Stage Operation.
- Updated Figure 11. 33926 Typi cal Application Schematic.
- Updated the Freescale format to the prevailing form and style
- Added thermal addendum. 3.0 10/2006 • Corrected minor typos formatti ng throughout the document.
- Corrected labels on the Internal Block Diagram
- Added “These parameters are not production tested” to the Maximum Ratings heading
- Changed the values for Logic Input Voltage (2) and SF Output (3)
- Made corrections on note (4), (7), and (10) for Maximum Ratings
- Changed labels or values for Sleep State Supply Current (12), Undervoltage Lockout Thresholds, Charge Pump Voltage (CP Capacitor = 33 nF), No PWM, Input Voltage (IN1, IN2, D1, D2, INV, SLEW) (13), Logic Input Currents, VPWR = 8.0V, Output-ON Resistance (15), ILOAD = 3.0A, Output Current Regulation Threshold, Output Leakage Current (16), Outputs off, VPWR = 28V, Feedback Current (pin FB sourcing current) (17), and Status Flag Leakage Current (19) in the Static Electrical Characteristics
- Added Charge Pump Voltage (CP Capacitor = 33 nF), PWM = 20kHz, Slew Rate = Fast and Operating Input Voltage (EN, IN1, IN2, D1, D2, INV, SLEW) in the Static Electrical Characteristics
- Added note This parameter is Guaranteed By Design. to Static Electrical Characteristics
- Changed labels or values for ILIM Output Constant-OFF Time (24), ILIM Blanking Time (25), Output Rise and Fall Time (27) and Short Circuit / Overtemperature Turn-OFF (Latch-OFF) Time (28) (29) in the Dynamic Electrical Characteristics
- Made changes or corrections to note (24), (27), (28), and (29) for Dynamic Electrical Characteristics
- Made corrections to Figure 4, Output Delay Time, Figure 5, Disable Delay Time, and Figure 6, Output Switching Time in Timing Diagrams
- Added Figure 7, Current Limit Blanking Time and Constant-OFF Time and Figure 8, Short Circuit Detection Turn-OFF Time tFAULT in Timing Diagrams
- Added paragraph Output Avalanche Protection and Figure 12, Avalanche Protection to Protection and diagnostic features
- Made minor label changes to Figure 13, 33926 Typical Application Schematic
Analog Integrated Circuit Device Data Freescale Semiconductor 23 33926 4.0 12/2006 • Corrected minor typographic errors on pages 2, 7, 9, 11, 15, and 16.
- Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from Maximum Ratings on page 5.
- Added notes Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. on page 5 and Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. on page 5 REVISION DATE DESCRIPTION
Rev. 4.0 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc., 2007. All rights reserved. How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516
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