33892 FREESCALE | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 28

Technical content

Features

  • D u a l 1 0 mΩ and Dual 35 mΩ High-Side Switches
  • Operating Voltage Range of 6.0 V to 27 V with Standby Current < 5.0 µA
  • SPI Control of Overcurrent Limit, Overcurrent Fault Blanking Time, Output-OFF Open Load Detection, Output ON/OFF Control, Watchdog Timeout, Slew Rates, and Fault Status Reporting
  • SPI Status Reporting of Overcurrent, Open and Shorted Loads, Overtemperature, Undervoltage and Overvoltage Shutdown, Fail-Safe Terminal Status, and Program Status
  • Analog Current Feedback with Selectable Ratio
  • Enhanced 16 V Reverse Polarity V PWR Protection PNC SUFFIX CASE 1558-02 24-TERMINAL PQFN QUAD INTELLIGENT HIGH-SIDE SWITCH

ORDERING INFORMATION

Range (TA) Package PC33892PNC/R2 -40°C to 125°C 24 PQFN

33892 Simplified Application Diagram

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

33892 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

Figure 1. 33892 Simplified Internal Block Diagram

3.0 MHz

Freescale Semiconductor, Inc.

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33892 Transparent Top View of Package VPWR 17 20 GND 2114 15 11 2410 1VDD SO GND HS3 HS1 HS1 HS0 HS0 HS2 FSI CSNS IN0 SI SCLK CS RST GND WAKE FS IN3 IN2 IN1 23456789 TERMINAL FUNCTION DESCRIPTION Terminal Terminal Name Formal Name Definition IN1 IN2 IN3 IN0 Serial Inputs The IN0–IN3 high-side input terminals are used to directly control HS0–HS3 high-side output terminals, respectively. An SPI register determines if each input is activated or if the input logic state is ORed or ANDed with the SPI instruction. These terminals are to be driven with 5.0 V CMOS levels, and they have an internal active pull-down current source.

4 FS Fault Status

(Active Low) This terminal is an open drain configured output requiring an external pull-up resistor to VDD for fault reporting. If a device fault condition is detected, this terminal is active LOW. Specific device diagnostic faults are reported via the SPI SO terminal.

5 WAKE Wake This terminal is an input that cont rols the device mode and watchdog timeout feature

if enabled. An internal clamp protects this terminal from high damaging voltages when the output is current limited with an external resistor. This input has an internal passive pull-down. 6, 13, 15 GND Ground These terminals are the ground for the logic and analog circuitry of the device. 7R S T Reset This terminal is an input used to initialize the device configuration and fault registers, as well as place the device in a low-current sleep mode. The terminal also starts the watchdog timer when transitioning from logic [0] to logic [1]. This terminal should not be allowed to be logic [1] until VDD is in regulation. This terminal has an internal passive pull-down.

8 CS Chip Select

(Active Low) This terminal is an input terminal connected to a chip select output of a master microcontroller (MCU). The MCU determines which device is addressed (selected) to receive data by pulling the CS terminal of the selected device logic LOW, thereby enabling SPI communication with the device. Other unselected devices on the serial link having their CS terminals pulled up logic HIGH disregard the SPI communication data sent. This terminal has an internal active pull-up current source and requires CMOS logic levels. 9 SCLK Serial Clock This terminal is an input terminal connected to the MCU providing the required bit shift clock for SPI communication. It transitions one time per bit transferred at an operating frequency, fSPI, defined by the communication interface. The 50 percent duty cycle CMOS level serial clock signal is idle between command transfers. The signal is used to shift data into and out-of the device. This terminal has an internal active pull-down. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

10 SI Serial Input This terminal is a command data i nput terminal connected to the SPI Serial Data

Output of the MCU or to the SO terminal of the previous device of a daisy chain of devices. The input requires CMOS logic level signals and incorporates an internal active pull-down. Device control is facilitated by the input's receiving the MSB first of a serial 8-bit control command. The MCU ensures data is available upon the falling edge of SCLK. The logic state of SI present upon the rising edge of SCLK loads that bit command into the internal command shift register. This terminal has an internal active pull-down.

11 V DD Digital Drain Voltage

(Power) This terminal is an external voltage input terminal used to supply power to the SPI circuit. In the event VDD is lost, an internal supply provides power to a portion of the logic, ensuring limited functionality of the device. 12 SO Serial Output This terminal is an output terminal connected to the SPI Serial Data Input terminal of the MCU or to the SI terminal of the next device of a daisy chain of devices. This output will remain tri-stated (high-impedance OFF condition) so long as the CS terminal of the device is logic HIGH. SO is only active when the CS terminal of the device is asserted logic LOW. The generated SO output signals are CMOS logic levels. SO output data is available on the falling edge of SCLK and transitions immediately on the rising edge of SCLK. 16 V PWR Positive Power Supply This terminal c onnects to the positive power supply and is the source of operational power for the device. The VPWR contact is the backside surface mount tab of the package. HS3 HS2 High-Side Outputs Protected 35 m Ω high-side power output terminals to the load. 17, 18 19, 20 HS1 (Note 1) HS0 (Note 2) High-Side Outputs Protected 10 m Ω high-side power output terminals to the load.

22 FSI Fail-Safe Input The value of the resistance connected between this terminal and ground determines

the state of the outputs after a Watchdog timeout occurs. Depending on the resistance value, either all outputs are OFF or the output HSO only is ON. If the FSI terminal is left to float up to a logic [1] level, then the outputs HS0 and HS2 will turn ON when in the Fail-Safe state. When the FSI terminal is connected to GND, the Watchdog circuit and Fail-Safe operation are disabled. This terminal incorporates an active internal pull- up.

23 CSNS Output Current

The Current Sense terminal sources a current proportional to the designated HS0– HS3 output. That current is fed into a ground referenced resistor and its voltage is monitored by an MCU's A/D. The channel to be monitored is selected via the SPI. This terminal can be tri-stated through SPI. Notes 1. HS1 output (17 and 18) must be connected externally on the PCB as close as possible to the terminals. 2. HS0 output (19 and 20) must be connected externally on the PCB as close as possible to the terminals. TERMINAL FUNCTION DESCRIPTION (continued) Terminal Terminal Name Formal Name Definition Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33892 MAXIMUM RATINGS All voltages are with respect to ground unless otherwise noted. Rating Symbol Value Unit Operating Voltage Range Steady-State VPWR(SS) -16 to 41 V VDD Supply Voltage V DD 0 to 5.5 V Input/Output Voltage (Note 3) V IN[0:3], RST, FSI, CSNS, SI, SCLK, CS, FS -0.3 to 7.0 V SO Output Voltage (Note 3) V SO -0.3 to VDD+0.3 V WAKE Input Clamp Current I CL(WAKE) 2.5 mA CSNS Input Clamp Current I CL(CSNS) 10 mA Output Current (Note 4) I HS0, IHS1 25 A Output Current (Note 4) I HS2, IHS3 12 A Output Clamp Energy (Note 5) E CL0, ECL1 TBD J Output Clamp Energy (Note 5) E CL2, ECL3 TBD J Storage Temperature T STG -55 to 150 °C Operating Ambient Temperature T A -40 to 125 °C Operating Junction Temperature T J -40 to 150 °C Thermal Resistance Junction to Case Junction to Ambient RθJC RθJA <1.0 TBD °C/W ESD Voltage Human Body Model (Note 6) Machine Model (Note 7) VESD1 VESD2 ±2000 ±200 V Terminal Soldering Temperature (Note 8) T SOLDER 240 °C Notes 3. Exceeding voltage limits on IN[0:3], RST, FSI, CSNS, SI, SO, SCLK, CS, or FS terminals may cause a malfunction or permanent damage to the device. 4. Continuous high-side output current rati ng so long as maximum junction temperature is not exceeded. Calculation of maximum output current using package thermal resistance is required. 5. Active clamp energy using single-pulse method (L = 16 mH, R L = 0 Ω, VPWR = 12 V, TJ = 150°C). 6. ESD1 testing is performed in accordance with the Human Body Model (C ZAP = 100 pF, RZAP = 1500 Ω). 7. ESD2 testing is performed in accordance with the Machine Model (C ZAP = 200 pF, RZAP = 0 Ω) and in accordance with the system module specification with a capacitor > 0.01 µF connected from high-side outputs to GND. 8. Terminal soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit POWER INPUT Battery Supply Voltage Range Fully Operational VPWR 6.0 – 27 V VPWR Operating Supply Current Outputs ON, IHS[0:3] =0A IPWR(on) –– 2 0 mA VPWR Supply Current Outputs OFF, Open Load Detection Disabled, WAKE > 0.7 VDD, RST = VLOGIC HIGH IPWR(sby) –– 5 . 0 mA Sleep State Supply Current (VPWR < 14 V, RST < 0.5 V, WAKE < 0.5 V) TJ = 25°C TJ = 85°C IPWR(sleep) µA VDD Supply Voltage V DD(on) 4.5 5.0 5.5 V VDD Supply Current No SPI Communication

3.0 MHz SPI Communication

IDD(on) 1.0 5.0 mA VDD Sleep State Current I DD(sleep) –– 5 . 0 µA Overvoltage Shutdown Threshold V PWR(OV) 28 32 36 V Overvoltage Shutdown Hysteresis V PWR(OVHYS) 0.2 0.8 1.5 V Undervoltage Shutdown Threshold (Note 9) V PWR(UV) 4.75 5.24 5.75 V Undervoltage Hysteresis (Note 10) V PWR(UVHYS) –0 . 2 5 – V Undervoltage Power-ON Reset V PWR(UVPOR) –– 5 . 0 V Notes 9. Output will automatically recover to instructed state when V PWR voltage is restored to normal so long as the VPWR degradation level did not go below the undervoltage power-ON reset threshold. This applies to all internal device logic that is supplied by VPWR and assumes that the external VDD supply is within specification. 10. This applies when the undervoltage fault is not latched (IN = 0). Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33892 STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit OUTPUTS HS0 AND HS1 Output Drain-to-Source ON Resistance (IHS[0:1] = 10 A, TJ = 25°C) VPWR = 6.0 V VPWR = 10 V VPWR = 13 V RDS(ON)25 mΩ Output Drain-to-Source ON Resistance (IHS[0:1] = 10 A, TJ = 150°C) VPWR = 6.0 V VPWR = 10 V VPWR = 13 V RDS(ON)150 mΩ Output Source-to-Drain ON Resistance (Note 11) IHS = 15 A, TJ = 25°C, VPWR = -12 V RSD(ON) –1 0 2 0 mΩ Output Overcurrent High Detection Levels (9.0 V < VPWR < 16 V) SOCH = 0 SOCH = 1 IOCH0 IOCH1 100 120 A Overcurrent Low Detection Levels (SOCL[2:0], 9.0 V < VPWR < 16 V) 000 001 010 011 100 101 110 111 IOCL0 IOCL1 IOCL2 IOCL3 IOCL4 IOCL5 IOCL6 IOCL7 14.6 13.0 11.5 10.0 8.4 6.9 5.4 3.8 18.2 16.3 14.4 12.5 10.5 8.6 6.7 4.8 22.8 20.4 15.7 13.2 10.8 8.4 6.0 A Current Sense Ratio (9.0 V < VPWR < 16 V, CSNS < 4.5 V) DICR D2 = 0 DICR D2 = 1 CSR0 CSR1 Current Sense Ratio (CSR0) Accuracy Output Current 5.0 A 10 A 12.5 A 15 A 20 A 25 A CSR0_ACC -20 -14 -13 -12 -13 -13 Notes 11. Source-Drain ON Resistance (Reverse Drain-to -Source ON Resistance) with negative polarity VPWR. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit OUTPUTS HS0 AND HS1 (continued) Current Sense Ratio (CSR1) Accuracy Output Current 5.0 A 10 A 12.5 A 15 A 20 A 25 A CSR1_ACC -25 -19 -18 -17 -18 -18 Maximum Current Sense Clamp Voltage ICSNS = 15 mA VCL(MAXCSNS) 4.5 6.0 7.0 V Open Load Detection Current (Note 12) I OLDC 30 – 100 µA Output Fault Detection Threshold Output Programmed OFF VOFD(THRES) 2.0 3.0 4.0 V Output Negative Clamp Voltage 0.5 A < = IHS < = 2.0 A, Output OFF VCL -20 – – V Overtemperature Shutdown (Note 13) TA = 125°C, Output OFF TSD 150 175 190 Overtemperature Shutdown Hysteresis (Note 13) T SD(HYS) 5.0 – 20 °C OUTPUTS HS2 AND HS3 Output Drain-to-Source ON Resistance (IHS[2:3] = 5.0 A, TJ = 25°C) VPWR = 6.0 V VPWR = 10 V VPWR = 13 V RDS(ON)25 mΩ Output Drain-to-Source ON Resistance (IHS[2:3] = 5.0 A, TJ = 150°C) VPWR = 6.0 V VPWR = 10 V VPWR = 13 V RDS(ON)150 mΩ Output Source-to-Drain ON Resistance (Note 14) IHS = 15 A, TJ = 25°C, VPWR = -12 V RDS(ON) –3 5 7 0 mΩ Output Overcurrent High Detection Levels (9.0 V < VPWR < 16 V) SOCH = 0 SOCH = 1 IOCH0 IOCH1 A Notes 12. Output OFF Open Load Detection Current is the current required to flow through the load for the purpose of detecting the existence of an open load condition when the specific output is commanded OFF. 13. Guaranteed by process monitoring. Not production tested. 14. Source-Drain ON Resistance (Reverse Drain-to -Source ON Resistance) with negative polarity VPWR. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33892 STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit OUTPUTS HS2 AND HS3 (continued) Overcurrent Low Detection Levels (SOCL[2:0], 9.0 V < VPWR < 16 V) 000 001 010 011 100 101 110 111 IOCL0 IOCL1 IOCL2 IOCL3 IOCL4 IOCL5 IOCL6 IOCL7 7.2 6.5 5.7 5.0 4.2 3.4 2.6 1.9 9.1 8.15 7.2 6.25 5.25 4.3 3.35 2.4 9.8 8.7 7.5 6.3 5.2 4.1 2.9 A Current Sense Ratio (9.0 V < VPWR < 16 V, CSNS < 4.5 V) DICR D2 = 0 DICR D2 = 1 CSR2 CSR3 Current Sense Ratio (CSR2) Accuracy Output Current 2.0 A 5.0 A 10 A 12.5 A 15 A 20 A CSR2_ACC -20 -14 -13 -12 -13 -13 Current Sense Ratio (CSR3) Accuracy Output Current 5.0 A 10 A 12.5 A 15 A 20 A 25 A CSR3_ACC -25 -19 -18 -17 -18 -18 Maximum Current Sense Clamp Voltage ICSNS = 15 mA VCL(MAXCSNS) 4.5 6.0 7.0 V Open Load Detection Current (Note 15) I OLDC 30 – 100 µA Output Fault Detection Threshold Output Programmed OFF VOFD(THRES) 2.0 3.0 4.0 V Output Negative Clamp Voltage 0.5 A < = IHS < = 2.0 A, Output OFF VCL -20 – – V Overtemperature Shutdown (Note 16) TA = 125°C, Output OFF TSD 150 175 190 Overtemperature Shutdown Hysteresis (Note 16) T SD(HYS) 5.0 – 20 °C Notes 15. Output OFF Open Load Detection Current is the current required to flow through the load for the purpose of detecting the existence of an open load condition when the specific output is commanded OFF. 16. Guaranteed by process monitoring. Not production tested. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5 . 5V , 6V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit CONTROL INTERFACE Input Logic High Voltage (Note 17) VIH 0.7VDD – – V Input Logic Low Voltage (Note 17) VIL – – 0.2VDD V Input Logic Voltage Hysteresis (Note 17) VIN(HYS) 100 350 750 mV Input Logic Pull-Down Current (SCLK, IN, SI, IN[0:3]) IDWN 5.0 – 20 µA RST Input Voltage Range VRST 4.5 5.0 5.5 V SO, FS Tri-State Capacitance (Note 18) CSO – – 20 pF Input Logic Pull-Down Resistor (RST) and WAKE IDWN 100 200 400 kΩ Input Capacitance (Note 19) CIN – 4.0 12 pF Wake Input Clamp Voltage (Note 20) ICL(WAKE) < 2.5 mA VCL(WAKE) 7.0 – 14 V Wake Input Forward Voltage ICL(WAKE) = -2.5 mA VF(WAKE) -2.0 – -0.3 V SO High-State Output Voltage IOH = 1.0 mA VSOH 0.8VDD – – V FS, SO Low-State Output Voltage IOL = -1.6 mA VSOL – 0.2 0.4 V SO Tri-State Leakage Current CS > 0.7 VDD ISO(LEAK) -5.0 0 5.0 µA Input Logic Pull-Up Current (Note 21) CS, VIN > 0.7 VDD IUP 5.0 – 20 µA FSI Input terminal External Pull-Down Resistance (Note 22) FSI Disabled, HS[0:3] Indeterminate FSI Enabled, all HS OFF FSI Enabled, HS0 ON, HS[1:3] OFF FSI Enabled, HS0 and HS2 ON, HS1 and HS3 OFF RFS RFSdis RFSoffoff RFSonoff RFSonon 6.0 6.5 Infinite 1.0 7.0 kΩ Notes 17. Upper and lower logic threshold voltage range applies to SI, CS, SCLK, RST, IN[0:3], and WAKE input signals. The WAKE and RST signals may be supplied by a derived voltage referenced to VPWR. 18. Parameter is guaranteed by process monitoring but is not production tested. 19. Input capacitance of SI, CS, SCLK, RST, and WAKE. This parameter is guaranteed by process monitoring but is not production tested. 20. The current must be limited by a series resistance when using voltages > 7.0 V. 21. Pull-up current is with CS OPEN. CS has an active internal pull-up to VDD. 22. The selection of the RFS must take into consideration the tolerance, temperature coefficient and lifetime duration to assure that the resistance value will always be within the desired (specified) range. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33892 DYNAMIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit POWER OUTPUT TIMING HS0, HS1, HS2, AND HS3 Output Rising Slow Slew Rate A (DICR D3 = 0) (Note 23)

9.0 V < VPWR < 16 V

SRRA_SLOW 0.1 0.3 0.5 V/µs Output Rising Slow Slew Rate B (DICR D3 = 0) (Note 24) SRRB_SLOW 0.015 0.05 0.15 V/µs Output Rising Fast Slew Rate A (DICR D3 = 1) (Note 23) SRRA_FAST 0.2 0.5 1.5 V/µs Output Rising Fast Slew Rate B (DICR D3 = 1) (Note 24) SRRB_FAST 0.015 0.05 0.5 V/µs Output Falling Slow Slew Rate A (DICR D3 = 0) (Note 23) SRFA_SLOW 0.1 0.3 0.5 V/µs Output Falling Slow Slew Rate B (DICR D3 = 0) (Note 24) SRFB_SLOW 0.015 0.05 0.15 V/µs Output Falling Fast Slew Rate A (DICR D3 = 1) (Note 23) SRFA_FAST 0.4 1.0 2.0 V/µs Output Falling Fast Slew Rate B (DICR D3 = 1) (Note 24) SRFB_FAST 0.05 0.175 0.6 V/µs Output Turn-ON Delay Time in Fast/Slow Slew Rate (Note 25) DICR = 0, DICR = 1 tDLY(ON) 2.0 30 200 µs Output Turn-OFF Delay Time in Slow Slew Rate Mode (Note 26) DICR = 0 tDLY_SLOW(OFF) 40 460 1000 µs Output Turn-OFF Delay Time in Fast Slew Rate Mode (Note 26) DICR = 1 tDLY_FAST(OFF) 20 120 400 µs Direct Input Switching Frequency (DICR D3 = 0) fPWM – – 300 Hz Overcurrent Low Detection Blanking Time (OCLT[1:0]) tOCL0 tOCL1 tOCL2 tOCL3 108 434 0.08 155 620 0.15 202 806 0.25 ms Notes parameters are guaranteed by process monitoring. parameters are guaranteed by process monitoring. 25. Turn-ON delay time measured from ri sing edge of any signal (IN[0:3], SCLK, CS) that would turn the output ON to VHS = 0.5 V with RL = 5.0 Ω resistive load. 26. Turn-OFF delay time measured from fa lling edge of any signal (IN[0:3], SCLK, CS) that would turn the output OFF to VHS = VPWR-0.5 V with RL =5 . 0Ω resistive load. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

POWER OUTPUT TIMING HS0, HS1, HS2, AND HS3 (continued) Overcurrent High Detection Blanking Time tOCH 1.0 10 20 µs CS to CSNS Valid Time (Note 27) CNSVAL – – 10 µs Watchdog Timeout (WD[1:0]) (Note 28) tWDTO0 tWDTO1 tWDTO2 tWDTO3 496 248 2000 1000 620 310 2500 1250 806 403 3250 1625 ms Notes 27. Time necessary for the CSNS to be with ±5% of the targeted value. 28. Watchdog timeout delay measured from the rising edge of WAKE or RST from a sleep state condition, to output turn-ON with the output driven OFF and FSI floating. The values shown are for WDR setting of [00]. The accuracy of tWDTO is consistent for all configured watchdog timeouts. DYNAMIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33892 DYNAMIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5 . 5V , 6 . 0V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit SPI INTERFACE CHARACTERISTICS Maximum Frequency of SPI Operation fSPI – – 3.0 MHz Required Low State Duration for RST (Note 29) tWRST – 50 350 ns Rising Edge of CS to Falling Edge of CS (Required Setup Time) (Note 30) tCS – – 300 ns Rising Edge of RST to Falling Edge of CS (Required Setup Time) (Note 30) tENBL – – 5.0 µs Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) (Note 30) tLEAD – 50 167 ns Required High State Duration of SCLK (Required Setup Time) (Note 30) tWSCLKh – – 167 ns Required Low State Duration of SCLK (Required Setup Time) (Note 30) tWSCLKl – – 167 ns Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) (Note 30) tLAG – 50 167 ns SI to Falling Edge of SCLK (Required Setup Time) (Note 31) tSI(SU) – 25 83 ns Falling Edge of SCLK to SI (Required Setup Time) (Note 31) tSI(HOLD) – 25 83 ns SO Rise Time CL = 200 pF tRSO – 25 50 ns SO Fall Time CL = 200 pF tFSO – 25 50 ns SI, CS, SCLK, Incoming Signal Rise Time (Note 31) tRSI – – 50 ns SI, CS, SCLK, Incoming Signal Fall Time (Note 31) tFSI – – 50 ns Time from Falling Edge of CS to SO Low Impedance (Note 32) tSO(EN) – – 145 ns Time from Rising Edge of CS to SO High Impedance (Note 33) tSO(DIS) – 65 145 ns Time from Rising Edge of SCLK to SO Data Valid (Note 34) 0.2 VDD ≤ SO ≥ 0.8 VDD, CL = 200 pF tVALID – 65 105 ns Notes 29. RST low duration measured with outputs enabled and going to OFF or disabled condition. 30. Maximum setup time required for the 33892 is the minimum guaranteed time needed from the microcontroller. 31. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing. 32. Time required for output status data to be available for use at SO. 1.0 k Ω on pull-up on CS. 33. Time required for output status data to be terminated at SO. 1.0 k Ω on pull-up on CS. 34. Time required to obtain valid data out from SO following the rise of SCLK. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Figure 2. Output Slew Rate and Time Delays Figure 3. Overcurrent Shutdown Freescale Semiconductor, Inc.

Figure 4. Overcurrent Low and High Detection Figure 5. Input Timing Switching Characteristics

0.7 VDD

0.2 VDD

Freescale Semiconductor, Inc.

Figure 6. SCLK Waveform and Valid SO Data Delay Time Freescale Semiconductor, Inc.

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33892 SYSTEM/APPLICATION INFORMATION INTRODUCTION The 33892 is one in a family of devices designed for low- voltage automotive and industrial lighting and motor control applications. Its four low RDS(ON) MOSFETs (two 10 mΩ, two 35 mΩ) can control the high sides of four separate resistive or inductive loads or serve as high-side switches for a pair of DC motors. Programming, control, and diagnostics are accomplished using a 16-bit SPI interface. Additionally, each output has its own parallel input for PWM control if desired. The 33892 allows the user to program via the SPI the fault current trip levels and duration of acceptable lamp inrush or motor stall intervals. Such programmability allows tight control of fault currents and can protect wiring harnesses and circuit boards as well as loads. The 33892 is packaged in a power-enhanced 10 x 10 PQFN package with exposed tabs. FUNCTIONAL DESCRIPTION SPI Protocol Description The SPI interface has a full duplex, three-wire synchronous data transfer with four I/O lines associated with it: Serial Input (SI), Serial Output (SO), Serial Clock (SCLK), and Chip Select (CS). The SI/SO terminals of the 33892 follow a first-in first-out (D15 to D0) protocol, with both input and output words transferring the most significant bit (MSB) first. All inputs are compatible with 5.0 V CMOS logic levels. The SPI lines perform the following functions: Serial Input (SI) This is a serial interface (SI) command data input terminal. Each SI bit is read on the falling edge of SCLK. A 16-bit stream of serial data is required on the SI terminal, starting with D15 to D0. The internal registers of the 33892 are configured and controlled using a 5-bit addressing scheme described in Table 1, page 18. Register addressing and configuration are described in Table 2, page 19. The SI input has an internal pull- down, IDWN. Serial Output (SO) The SO data terminal is a tri-stateable output from the shift register. The SO terminal remains in a high-impedance state until the CS terminal is put into a logic [0] state. The SO data is capable of reporting the status of the output, the device configuration, and the state of the key inputs. The SO terminal changes state on the rising edge of SCLK and reads out on the falling edge of SCLK. Fault and input status descriptions are provided in Table 9, page 22. Serial Clock (SCLK) The SCLK terminal clocks the internal shift registers of the 33892 device. The serial input (SI) terminal accepts data into the input shift register on the falling edge of the SCLK signal while the serial output (SO) terminal shifts data information out of the SO line driver on the rising edge of the SCLK signal. It is important the SCLK terminal be in a logic low state whenever CS makes any transition. For this reason, it is recommended the SCLK terminal be in a logic [0] whenever the device is not accessed (CS logic [1] state). SCLK has an internal pull-down. When CS is logic [1], signals at the SCLK and SI terminals are ignored and SO is tri-stated (high impedance) (see Figure 7, page 18). Chip Select (CS) The CS terminal enables communication with the master microcontroller (MCU). When this terminal is in a logic [0] state, the device is capable of transferring information to, and receiving information from, the MCU. The 33892 latches in data from the Input Shift registers to the addressed registers on the rising edge of CS. The 33892 transfers status information from the power output to the Shift register on the falling edge of CS. The SO output driver is enabled when CS is logic [0]. CS should transition from a logic [1] to a logic [0] state only when SCLK is a logic [0]. CS has an internal pull-up, IUP. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Figure 7. Single 16-Bit Word SPI Communication SPI communication is accomplished using 16-bit messages. configure and control the outputs and their protection features. in a message that is not 16 bits will be ignored. configure the device and to control the state of the outputs. Table 2, page 19, summarizes the SI registers.

  1. RSTB is in a logic H state during the above operation.
  2. DO, D1, D2, ... , and D15 relate to the most recent ordered entry of program data into the LUX IC
  3. OD0, OD1, OD2, ..., and OD15 relate to the first 16 bits of ordered fault and status data out of the LUX IC
  4. RST is a logic [1] state during the above operation.
  5. D15–D0 relate to the most recent ordered entry of data into the device.
  6. OD15–OD0 relate to the first 16 bits of ordered fault and status data out of the device.

Table 1. SI Message Bit Assignment D10–D8 Register address bits. Freescale Semiconductor, Inc.

addresses and their impact on device operation. D[4:0] determine the content of the first sixteen bits of SO data. output switch and a logic [0] turns it OFF. terminals of several devices share the same A/D converter. output overcurrent low and high detection levels, respectively. based on the state of the D12–D11 bits ( Table 3). level to one of two levels, as outlined in Table 5, page 20. Table 2. Serial Input Address and Configuration Bit Map s=Output selection with the bits A1A0 as defined in Table 3. Table 3. Channel Selection Freescale Semiconductor, Inc.

the D12–D11 bits (refer to Table 3, page 19). device will latch off within 20 µs. state bits D12–D11 (refer to Table 3, page 19). disable the output from direct control. to the corresponding message bits when addressing the OCR0. default value [0] is used to select the low ratio (Table 7). under- and overvoltage are active (default value). Table 4. Overcurrent Low Detection Levels Table 5. Overcurrent High Detection through bits D12–D11; refer to Table 3, page 19. Table 6. Overcurrent Low Detection bits D12–D11; refer to Table 3, page 19. Table 7. Current Sense Ratio bits D12–D11; refer to Table 3, page 19. Freescale Semiconductor, Inc.

programmed at the beginning of a new count sequence. with SPI during normal operation. chaining devices as well as message verification. viz., Fault, SOCHLR, CDTOLR, and DICR registers. changed with an updated STATR write.

  • The previous SPI communication was determined to be invalid. In this case, the status will be reported as though the invalid SPI communication never occurred.
  • Battery transients below 6. 0 V resulting in an under- voltage shutdown of the outputs may result in incorrect data loaded into the status register. The SO data transmitted to the MCU during the first SPI communication following an undervoltage VPWR condition should be ignored.
  • The RST terminal transition from a logic [0] to [1] while the WAKE terminal is at logic [0] may result in incorrect data loaded into the Status register. The SO data transmitted to the MCU during the first SPI communication following this condition should be ignored. Serial Output Bit Assignment The 16 bits of serial output data depend on the previous serial input message, as explained in the following paragraphs. Table 9, page 22, summarizes SO returned data for bits OD15 through OD0.
  • Bit OD15 is the MSB; it refl ects the state of the Watchdog bit from the previously clocked-in message.
  • Bit OD14 remains logic [0] except when an undervoltage condition occurred.
  • Bit OD13 remains logic [0] except when an overvoltage condition occurred.
  • Bits OD[12:8] reflect the state of the bits SOA[4:0] from the previously clocked in message.
  • Bits OD[7:4] give the fault stat us flag of the outputs HS3, HS2, HS1, and HS0, respectively.
  • The contents of bits OD[3:0] depend on bits D[4:0] from the most recent STATR command SOA[4:0] as explained in the paragraphs following the table.

Table 8. Watchdog Timeout Freescale Semiconductor, Inc.

selected with the bits A1A0 (Table 10). for channel from HS3 to HS0, respectively. bits for channels HS3 to HS0, respectively. CDTOLR register for the output selected with A1A0. DICR register for the output selected with A1A0. outputs HS2 and HS0, respectively, in case of Fail-Safe state. not. OD0 returns the state of the WAKE terminal. terminals IN3 to IN0, respectively. Table 9. Serial Output Bit Map Description

10 OD9 OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0

s=Output selection with the bits A 1A0 as defined in Table 3, page 19. Table 10. Channel-Specific Fault Register Freescale Semiconductor, Inc.

contained in succeeding paragraphs. SPI-configurable features of the device are as if set to logic [0].

  • V PWR is within the normal voltage range.
  • RST terminal is logic [1].
  • No fault has occurred. Fail-Safe Mode Fail-Safe Mode and Watchdog If the FSI input is not grounded, the watchdog timeout detection is active when either the WAKE or RST input terminal transitions from logic [0] to [1]. The WAKE input is capable of being pulled up to VPWR with a series of limiting resistance limiting the internal clamp current according to the specification. The Watchdog timeout is a multiple of an internal oscillator and is specified in the Table 8, page 21. As long as the WD bit (D15) of an incoming SPI message is toggled within the minimum watchdog timeout period (WDTO), based on the programmed value of the WDR, the device will operate normally. If an internal watchdog timeout occurs before the WD bit, the device will revert to a Fail-Safe mode until the device is reinitialized. During the Fail-Safe mode, the outputs will be ON or OFF depending upon the resistor RFS connected to the FSI pin, regardless of the state of the various direct inputs and modes (Table 12). In the Fail-Safe mode, the SPI register content is retained except for overcurrent high and low detection levels and timing, which are reset to their default value (SOCL, SOCH, and OCTL). Then the watchdog, overvoltage, overtemperature, and overcurrent circuitry (with default value) are fully operational. The Fail-Safe mode can be detected by monitoring the WDTO bit D2 of the WD register. This bit is logic [1] when the device is in Fail-Safe mode. The device can be brought out of the Fail-Safe mode by transitioning the WAKE and RST pins from logic [1] to logic [0] or forcing the FSI pin to logic [0]. Table 11 summarizes the various methods for resetting the device from the latched Fail-Safe mode. If the FSI pin is tied to GND, the Watchdog Fail-Safe operation is disabled.

Table 11. Fail-Safe Operation and Transitions Table 12. Output State During

0 Fail-Safe Mode Disabled

6.0 All HS OFF

15 HS0 ON

30 HS0 and HS2 ON

Freescale Semiconductor, Inc.

If the external 5.0 V supply is not within specification, or even disconnected, all register content is reset. The outputs can still be driven by the direct inputs IN[0:3]. The 33892 uses the battery input to power the output MOSFET-related current sense circuitry and any other internal logic providing fail-safe device operation with no VDD supplied. In this state, the watchdog, overvoltage, overtemperature, and overcurrent circuitry are fully operational with default values. Fault Mode The 33892 indicates the faults below as they occur by driving the FS terminal to [0]:

  • Overtemperature fault
  • Overvoltage and Undervoltage fault
  • Open load fault
  • Overcurrent fault (high and low) The FS terminal will automatically return to [1] when the fault condition is removed, except for overcurrent and in some cases undervoltage. Fault information is retained in the fault register and is available (and reset) via the SO terminal during the first valid SPI communication (refer to Table 10, page 22). Overtemperature Fault (Non-Latching) The 33892 incorporates overtemperature detection and shutdown circuitry in the output structure. Overtemperature detection is enabled when the output is in the ON state. For the output, an overtemperature fault (OTF) condition results in the faulted output turning OFF until the temperature falls below the TSD(HYS). This cycle will continue indefinitely until action is taken by the MCU to shut OFF the output, or until the offending load is removed. When experiencing this fault, the OTF fault bit will be set in the status register and cleared after either a valid SPI read or a power reset of the device. Overvoltage Fault (Non-Latching) The 33892 shuts down the output during an overvoltage fault (OVF) condition on the VPWR terminal. The output remains in the OFF state until the overvoltage condition is removed. When experiencing this fault, the OVF fault bit is set in the bit D1 and cleared after either a valid SPI read or a power reset of the device. The overvoltage protection can be disabled through SPI (bit OV_DIS). When disabled, the returned SO bit OD13 still reflects any overvoltage condition (overvoltage warning). Undervoltage Shutdown (Latching or Non-Latching) The output latches OFF at some battery voltage between 4.75 V and 5.75 V. As long as the VDD level stays within the normal specified range, the internal logic states within the device will be sustained. This ensures that when the battery level then returns above 5.75 V, the 33892 can be returned to the state that it was in prior to the low VPWR excursion. Once the output latches OFF, the outputs must be turned OFF and ON again to re-enable them. In the case IN[1:0]=0, this fault is non- latched. The undervoltage protection can be disabled through SPI (bit UV_DIS). When disabled, the returned SO bit OD14 still reflects any undervoltage condition (undervoltage warning). Open Load Fault (Non-Latching) The 33892 incorporates open load detection circuitry on the output. Output open load fault (OLF) is detected and reported as a fault condition when the output is disabled (OFF). The open load fault is detected and latched into the status register after the internal gate voltage is pulled low enough to turn OFF the output. The OLF fault bit is set in the status register. If the open load fault is removed, the status register will be cleared after reading the register. The open load protection can be disabled trough SPI (bit OL_DIS). Overcurrent Fault (Latching) The 33892 has eight programmable overcurrent low detection levels (IOCL) and two programmable overcurrent high detection levels (IOCH) for maximum device protection. The two selectable, simultaneously active overcurrent detection levels, defined by IOCH and IOCL, are illustrated in Figure 4, page 15. The eight different overcurrent low detection levels (IOCL0, IOCL1, IOCL2, IOCL3, IOCL4, IOCL5, IOCL6, and IOCL7) are illustrated in Figure 4. If the load current level ever reaches the selected overcurrent low detection level and the overcurrent condition exceeds the programmed overcurrent time period (tOCx), the device will latch the output OFF. If, at any time, the current reaches the selected IOCH level, then the device will immediately latch the fault and turn OFF the output, regardless of the selected tOCLx driver. For both cases, the device output will stay off indefinitely until the device is commanded OFF and then ON again. Reverse Battery The output survives the application of reverse voltage as low as -16 V. Under these conditions, the output’s gate is enhanced to keep the junction temperature less than 150°C. The ON resistance of the output is fairly similar to that in the Normal mode. No additional passive components are required. Ground Disconnect Protection In the event the 33892 ground is disconnected from load ground, the device protects itself and safely turns OFF the output regardless of the state of the output at the time of disconnection. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33892 PACKAGE DIMENSIONS M M DETAIL G VIEW A VIEW M M PIN 1 INDEX AREA 0.1 C C0.1 A B 17 18 19 20 PIN NUMBER REF. ONLY PIN NUMBER REF. ONLY 12 1 0 20 19 18 17 3.0 2.7 4.45 4.05 2.45 2.05

0.1 ACB

1.43 0.93 1.3 0.8 (0.25) (0.75) 2.2 1.82X 9.70 9.30 7.2 6.8 (1.25) (0.1)(0.25) 0.5 2.525 (0.25) (0.25) 2.3 1.82X 4.95 4.65 2X 0.65 1.375 3.2 5.85 1.65 1.352X (0.25) NOTES: ALL DIMENSIONS ARE IN MILLIMETERS. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. THE COMPLETE JEDEC DESIGNATOR FOR THIS PACKAGE IS: HF-PQFP-N. COPLANARITY APPLIES TO LEADS AND CORNER LEADS. METAL PADS CONNECTED TO THE GND. MINIMUM METAL GAP SHOULD BE 0.25MM. PNC SUFFIX 24-TERMINAL POWER QFN NON-LEADED PACKAGE CASE 1558-02 ISSUE A SHEET 1 OF 2 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

0.05 0.00 (0.4) (0.65) DETAIL G VIEW ROTATED 90˚ CW 0.05 C C0.1 C SEATING PLANE 2.20 1.952.2 2.0 2.8 2.6 0.6 0.2

2 PLACES

1.0 0.6 2.5 3.025 0.90 0.658X

0.1 M ACB

0.05 M C

0.47 0.33 2.0 1.6 (0.25) 1.8 1.3 0.325 3.5 16X 1.20 0.952X 1.20 0.956X (0.05) (0.2) 0.3±0.2 X0.3±0.2 0.25±0.2 X0.25±0.2 9X 0.65 iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33892 NOTES Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution: P.O. Box 5405, Denver, Colorado 80217. 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1 Minami-Azabu. Minato-ku, Tokyo 106-8573 Japan. 81-3-3440-3569 Hong Kong. 852-26668334 TECHNICAL INFORMATION CENTER: 1-800-521-6274 MC33892 Motorola reserves the right to make changes without further noti ce to any products herein. Motorola makes no warranty, represen tation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limit ation consequential or incidental damages. “Typical” parameters can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other appl ication in which the failur e of the Motorola product could create a situation where persona l injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and h old Motorola and its officers, employees, subsidiaries, affiliate s, and distributors harmless against all cl aims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc . Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. MOTOROLA and the Stylized M Logo are registered in the US Patent and Trademark Office. All other product or service names are t he property of their respective owners. © Motorola, Inc. 2004 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...