MC33887 MOTOROLA | Alldatasheet
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Features
5.0 V to 40 V Continuous Operation 120 m Ω RDS(ON) H-Bridge MOSFETs TTL/CMOS Compatible Inputs PWM Frequencies up to 10 kHz Active Current Limiting (Regulation) via Internal Constant OFF-Time PWM (with Temperature-Dependent Threshold Reduction) Output Short Circuit Protection (Short to V+ or Short to GND) Undervoltage Shutdown Fault Status Reporting Sleep Mode with Current Draw ≤50 µA (Inputs Floating or Set to Match Default Logic States) Pb-Free Packaging Designated by Suffix Codes VW and PNB
5.0 A H-BRIDGE WITH LOAD
ORDERING INFORMATION
Range (TA) Package MC33887DH/R2 -40°C to 125°C -40°C to 125°C -40°C to 125°C
20 HSOP
VW (Pb-FREE) SUFFIX CASE 979-04 20-TERMINAL HSOP PNB (Pb-FREE) SUFFIX CASE 1503-01 36-TERMINAL PQFN
33887 Simplified Application Diagram
iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
33887 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Figure 1. 33887 Simplified Internal Block Diagram Freescale Semiconductor, Inc.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33887 ENAGND IN2 C CP OUT2 OUT2 PGND PGND FS OUT1 OUT1 FB PGND PGND IN1 Tab Tab HSOP TERMINAL DEFINITIONS A functional description of each terminal can be found in the System/Application Information section, page 19. Terminal Terminal Name Formal Name Definition 1 AGND Analog Ground Low-current analog signal ground. 2 FS Fault Status for H-Bridge Open drain active LOW Fault Status output requiring a pullup resistor to 5.0 V. 3 IN1 Logic Input Control 1 Logic input control of OUT1 (i.e., IN1 logic HIGH = OUT1 HIGH). 4, 5, 16 V+ Positive Power Supply Positive supply connections 6, 7 OUT1 H-Bridge Output 1 Output 1 of H-Bridge. 8 FB Feedback for H-Bridge Current sensing feedback output providing ground referenced 1/375th (0.00266) of H-Bridge high-side current. 912 PGND Power Ground High-current power ground. 13 D2 Disable 2 Active LOW input used to simultaneously tri-state disable both H-Bridge outputs. When D2 is Logic LOW, both outputs are tri-stated. 14, 15 OUT2 H-Bridge Output 2 Output 2 of H-Bridge. 17 CCP Charge Pump Capacitor External reservoir capacitor connection for internal charge pump capacitor. 18 D1 Disable 1 Active HIGH input used to simultaneously tri-state disable both H-Bridge outputs. When D1 is Logic HIGH, both outputs are tri-stated. 19 IN2 Logic Input Control 2 Logic input control of OUT2 (i.e., IN2 logic HIGH = OUT2 HIGH). 20 EN Enable Logic input Enable control of device (i.e., EN logic HIGH = full operation, EN logic LOW = Sleep Mode). Tab/Pad Thermal Interface Exposed Pad Thermal Interface Exposed pad thermal interface for sinking heat from the device. Note Must be DC-coupled to analog ground and power ground via very low impedance path to prevent injection of spurious signals into IC substrate. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
19 NC10NC
Transparent Top View of Package PQFN TERMINAL DEFINITIONS A functional description of each terminal can be found in the System/Application Information section, page 19. Terminal Terminal Name Formal Name Definition 1, 7, 10, 16, 19, 28, 31 NC No Connect No internal connection to this terminal.
2 D1 Disable 1 Active HIGH input used to simultaneously tri-state disable both H-Bridge
outputs. When D1 is Logic HIGH, both outputs are tri-stated. 3 IN2 Logic Input Control 2 Logic input control of OUT2 (i.e., IN2 logic HIGH = OUT2 HIGH). 4 EN Enable Logic input Enable control of device (i.e., EN logic HIGH = full operation, EN logic LOW = Sleep Mode). 5, 6, 12, 13, 34, 35 V+ Positive Power Supply Positive supply connections. 8 AGND Analog Ground Low-current analog signal ground.
9 FS Fault Status for H-Bridge Open drain active LOW Fault Status output requiring a pullup resistor to
5.0 V. 11 IN1 Logic Input Control 1 Logic input control of OUT1 (i.e., IN1 logic HIGH = OUT1 HIGH). 14, 15, 17, 18 OUT1 H-Bridge Output 1 Output 1 of H-Bridge.
20 FB Feedback for H-Bridge Current feedback output providing ground referenced 1/375th ratio of
H-Bridge high-side current. 2126 PGND Power Ground High-current power ground.
27 D2 Disable 2 Active LOW input used to simultaneously tri-state disable both H-Bridge
outputs. When D2 is Logic LOW, both outputs are tri-stated. 29, 30, 32, 33 OUT2 H-Bridge Output 2 Output 2 of H-Bridge. 36 CCP Charge Pump Capacitor External reservoir capacitor connection for internal charge pump capacitor. Pad Thermal Interface Exposed Pad Thermal Interface Exposed pad thermal interface for sinking heat from the device. Note Must be DC-coupled to analog ground and power ground via very low impedance path to prevent injection of spurious signals into IC substrate. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33887 PGND NC NC NC NC NC C CP IN2 EN NC NC NC OUT2 OUT2 OUT2 OUT2 NC NC PGND PGND PGND PGND NC NC NC NC NC IN1 FS AGND NC NC NC NC OUT1 OUT1 OUT1 OUT1 NC NC FB PGND PGND PGND .35 Transparent Top View of Package SOICW-EP TERMINAL DEFINITIONS A functional description of each terminal can be found in the System/Application Information section, page 19. Terminal Terminal Name Formal Name Definition 14, 5154 PGND Power Ground High-current power ground. 57, 9, 14, 1922, 27 29, 3336, 41, 46, 4850 NC No Connect No internal connection to this terminal.
8 D2 Disable 2 Active LOW input used to simultaneously tri-state disable both H-Bridge
outputs. When D2 is Logic LOW, both outputs are tri-stated. 1013 OUT2 H-Bridge Output 2 Output 2 of H-Bridge. 15 18, 3740 V+ Positive Power Supply Positive supply connections. 23 CCP Charge Pump Capacitor External reservoir capacitor connection for internal charge pump capacitor.
24 D1 Disable 1 Active HIGH input used to simultaneously tri-state disable both H-Bridge
outputs. When D1 is Logic HIGH, both outputs are tri-stated. 25 IN2 Logic Input Control 2 Logic input control of OUT2 (i.e., IN2 logic HIGH = OUT2 HIGH). 26 EN Enable Logic input Enable control of device (i.e., EN logic HIGH = full operation, EN logic LOW = Sleep Mode). 30 AGND Analog Ground Low-current analog signal ground.
31 FS Fault Status for H-Bridge Open drain active LOW Fault Status output requiring a pullup resistor to
5.0 V. 32 IN1 Logic Input Control 1 Logic input control of OUT1 (i.e., IN1 logic HIGH = OUT1 HIGH). 4245 OUT1 H-Bridge Output 1 Output 1 of H-Bridge.
47 FB Feedback for H-Bridge Current feedback output providing ground referenced 1/375th ratio of
H-Bridge high-side current. Pad Thermal Interface Exposed Pad Thermal Interface Exposed pad thermal interface for sinking heat from the device. Note Must be DC-coupled to analog ground and power ground via very low impedance path to prevent injection of spurious signals into IC substrate. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
All voltages are with respect to ground unless otherwise noted. Rating Symbol Value Unit ELECTRICAL RATINGS Supply Voltage V+ 40 V Input Voltage (Note 1) VIN -0.3 to 7.0 V FS Status Output (Note 2) V FS 7.0 V Continuous Current (Note 3) IOUT 5.0 A DH Suffix HSOP ESD Voltage Human Body Model (Note 4) Each Terminal to AGND Each Terminal to PGND Each Terminal to V+ Each I/O to All Other I/Os Machine Model (Note 5) V ESD1 VESD1 VESD1 VESD1 VESD2 ±1000 ±1500 ±2000 ±2000 ±200 V VW Suffix HSOP ESD Voltage Human Body Model (Note 4) Machine Model (Note 5) V ESD1 VESD2 ±2000 ±200 V PQFN ESD Voltage Human Body Model (Note 4) Machine Model (Note 5) VESD1 VESD2 ±2000 ±200 V SOICW-EP ESD Voltage Human Body Model (Note 4) Machine Model (Note 5) VESD1 VESD2 ±1600 ±200 V THERMAL RATINGS Storage Temperature T STG -65 to 150 °C Operating Temperature (Note 6) Ambient Junction TA TJ -40 to 125 -40 to 150 Peak Package Reflow Temperature During Solder Mounting (Note 7) HSOP PQFN SOICW-EP TSOLDER 220 260 240 Notes 1. Exceeding the input voltage on IN1, IN2, EN, D1, or D2 may cause a malfunction or permanent damage to the device. 2. Exceeding the pullup resistor voltage on the open Drain FS terminal may cause permanent damage to the device. 3. Continuous current capability so long as junction temperature is ≤ 150°C. 4. ESD1 testing is performed in accordance with the Human Body Model (C ZAP = 100 pF, RZAP = 1500 Ω). 5. ESD2 testing is performed in accordance with the Machine Model (C ZAP = 200 pF, RZAP = 0 Ω). 6. The limiting factor is junction temperat ure, taking into account the power dissipation, thermal resistance, and heat sinking provided. Brief nonrepetitive excursions of junction temperature above 150°C can be tolerated as long as duration does not exceed 30 seconds maximum. (nonrepetitive events are defined as not occurring more than once in 24 hours.) 7. Terminal soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33887 THERMAL RESISTANCE (AND PACKAGE DISSIPATION) RATINGS (Note 8), (Note 9), (Note 10), (Note 11) Junction-to-Board (Bottom Exposed Pad Soldered to Board) HSOP (6.0 W) PQFN (4.0 W) SOICW-EP (2.0 W) R θJB ~5.0 ~4.3 ~8.0 °C/W Junction-to-Ambient, Natural Convection, Single-Layer Board (1s) (Note 12) HSOP (6.0 W) PQFN (4.0 W) SOICW-EP (2.0 W) R θJA ~41 ~TBD ~62 °C/W Junction-to-Ambient, Natural Convection, Four-Layer Board (2s2p) (Note 13) HSOP (6.0 W) PQFN (4.0 W) SOICW-EP (2.0 W) RθJMA ~30 ~21.3 ~TBD °C/W Junction-to-Case (Exposed Pad) (Note 14) HSOP (6.0 W) PQFN (4.0 W) SOICW-EP (2.0 W) RθJC ~0.5 ~0.9 ~1.5 °C/W Notes 8. The limiting factor is junction temperat ure, taking into account the power dissipation, thermal resistance, and heat sinking. 9. Exposed heatsink pad plus the power and ground terminals comprise the main heat conduction paths. The actual RθJB (junction-to-PC board) values will vary depending on solder thickness and composition and copper trace thickness. Maximum current at maximum die temperature represents ~16 W of conduction loss heating in the diagonal pair of output MOSFETs. Therefore, the RθJC-total must be less than 5.0 °C/W for maximum load at 70°C ambient. Module thermal design must be planned accordingly. 10. Thermal resistance between the die and the printed circuit boar d per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 11. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 12. Per SEMI G38-87 and JEDEC JESD51-2 with t he single-layer board (JESD51-3) horizontal. 13. Per JEDEC JESD51-6 with the board horizontal. 14. Indicates the average thermal resistance between the die and the exposed pad surface as measured by the cold plate method (MIL SPEC- 883 Method 1012.1) with the cold plate temperature used for the case temperature. MAXIMUM RATINGS (continued) All voltages are with respect to ground unless otherwise noted. Rating Symbol Value Unit Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 5.0 V ≤ V+ ≤ 28 V and -40°C ≤ TA ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit POWER SUPPLY Operating Voltage Range (Note 15) V+ 5.0 40 V Sleep State Supply Current (Note 16) IOUT = 0 A, VEN = 0 V IQ(sleep) 2 5 5 0 µA Standby Supply Current IOUT = 0 A, VEN = 5.0 V IQ(standby) 2 0 mA Threshold Supply Voltage Switch-OFF Switch-ON Hysteresis (thres-OFF) V+(thres-ON) V+(hys) 4.15 4.5 150 4.4 4.75 4.65 5.0 V V mV CHARGE PUMP Charge Pump Voltage V+ = 5.0 V
8.0 V ≤ V+ ≤ 40 V
3.35 V CONTROL INPUTS Input Voltage (IN1, IN2, D1, D2) Threshold HIGH Threshold LOW Hysteresis VIH VIL VHYS 3.5 0.7 1.0 1.4 V Input Current (IN1, IN2, D1) VIN - 0.0 V IINP -200 -80 µA Input Current (D2, EN) V D2 = 5.0 V IINP 2 5 1 0 0 µA Notes 15. Specifications are characte rized over the range of 5.0 V ≤ V+ ≤ 28 V. Operation >28 V will cause some parameters to exceed listed min/max values. Refer to typical operating curves to extrapolate values for operation >28 V but ≤ 40 V. 16. I Q(sleep) is with sleep mode function enabled. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33887 STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 5.0 V ≤ V+ ≤ 28 V and -40°C ≤ TA ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit POWER OUTPUTS (OUT1, OUT2) Output ON-Resistance (Note 17)
5.0 V ≤ V+ ≤ 28 V, TJ = 25°C
8.0 V ≤ V+ ≤ 28 V, TJ = 150°C
RDS(ON) 120 225 300 mΩ Active Current Limiting Threshold (via Internal Constant OFF-Time PWM) on Low-Side MOSFETs (Note 18) I LIM 5.2 6.5 7.8 A High-Side Short Circuit Detection Threshold I SCH 11 A Low-Side Short Circuit Detection Threshold I SCL 8.0 A Leakage Current (Note 19) VOUT = V+ VOUT = Ground IOUT(leak) 100 200 µA Output MOSFET Body Diode Forward Voltage Drop IOUT = 3.0 A VF 2 . 0 V Overtemperature Shutdown Thermal Limit Hysteresis TLIM THYS 175 225 HIGH-SIDE CURRENT SENSE FEEDBACK Feedback Current IOUT = 0 mA IOUT = 500 mA IOUT = 1.5 A IOUT = 3.0 A IOUT = 6.0 A IFB 1.07 3.6 7.2 14.4 1.33 4.0 8.0 600 1.68 4.62 9.24 18.48 µA mA mA mA mA FAULT STATUS (Note 20) Fault Status Leakage Current (Note 21) VFS = 5.0 V IFS(leak) 1 0 µA Fault Status SET Voltage (Note 22) IFS = 300 µA VFS(LOW) 1 . 0 V Notes 17. Output-ON resistance as measured from output to V+ and ground. 18. Active current limitation applies only for the low-side MOSFETs. 19. Outputs switched OFF with D1 or D2. 20. Fault Status output is an open Drain output requiring a pullup resistor to 5.0 V. 21. Fault Status Leakage Current is measured with Fault Status HIGH and not SET. 22. Fault Status Set Voltage is measured with Fault Status LOW and SET with IFS = 300 µA. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
DYNAMIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 5.0 V ≤ V+ ≤ 28 V and -40°C ≤ TA ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit TIMING CHARACTERISTICS PWM Frequency (Note 23) fPWM 1 0 k H z Maximum Switching Frequency During Active Current Limiting (Note 24) fMAX 2 0 k H z Output ON Delay (Note 25) V+ = 14 V td(ON) 1 8 µs Output OFF Delay (Note 25) V+ = 14 V td(OFF) 1 8 µs ILIM Output Constant-OFF Time for Low-Side MOSFETs (Note 26), (Note 27) ta 15 20.5 26 µs ILIM Blanking Time for Low-Side MOSFETs (Note 28), (Note 27) tb 12 16.5 21 µs Output Rise and Fall Time (Note 29) V+ = 14 V, IOUT = 3.0 A tf, tr 2.0 5.0 8.0 µs Disable Delay Time (Note 30) td(disable) 8 . 0 µs Power-ON Delay Time (Note 31) tpod 1 . 0 5 . 0 m s Wake-Up Delay Time (Note 31) twud 1 . 0 5 . 0 m s Output MOSFET Body Diode Reverse Recovery Time (Note 32) trr 100 ns Notes 23. The outputs can be PWM-controlled from an external source. This is typically done by holding one input high while applying a PWM pulse train to the other input. The maximum PWM frequency obtainable is a compromise between switching losses and switching frequency. See Typical Switching Waveforms, Figures 11 through 18, pp. 1516. 24. The Maximum Switching Frequency during active current limiting is internally implemented. The internal current limit circuitry produces a constant-OFF-time pulse-width modulation of the output current. The output loads inductance, capacitance, and resistance characteristics affect the total switching period (OFF-time + ON-time) and thus the PWM frequency during current limit. 25. Output Delay is the time duration from the midpoint of the IN1 or IN2 input signal to the 10% or 90% point (dependent on the transition direction) of the OUT1 or OUT2 signal. If the output is transitioning HIGH-to-LOW, the delay is from the midpoint of the input signal to the 90% point of the output response signal. If the output is transitioning LOW-to-HIGH, the delay is from the midpoint of the input signal to the 10% point of the output response signal. See Figure 2, page 11. 26. I LIM Output Constant-OFF Time is the time during which the internal constant-OFF time PWM current regulation circuit has tri-stated the output bridge. 27. Load currents ramping up to the current regulation threshold become limited at the I LIM value. The short circuit currents possess a di/dt that ramps up to the ISCH or ISCL threshold during the ILIM blanking time, registering as a short circuit event detection and causing the shutdown circuitry to force the output into an immediate tri-state latch-OFF. See Figures 6 and 7, page 12. Operation in Current Limit mode may cause junction temperatures to rise. Junction temperatures above ~160°C will cause the output current limit threshold to progressively fold back, or decrease with temperature, until ~175°C is reached, after which the TLIM thermal latch-OFF will occur. Permissible operation within this foldback region is limited to nonrepetitive transient events of duration not to exceed 30 seconds. See Figure 5, page 11. 28. I LIM Blanking Time is the time during which the current regulation threshold is ignored so that the short-circuit detection threshold comparators my have time to act. 29. Rise Time is from the 10% to the 90% level and Fall Time is from the 90% to the 10% level of the output signal. See Figure 4, page 11. 30. Disable Delay Time is the time duration from the midpoint of the D (disable) input signal to 10% of the output tri-state response. See Figure 3, page 11. 31. Parameter has been characteri zed but not production tested. 32. Parameter is guaranteed by design but not production tested. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
Figure 6. Operating States Figure 7. Example Short Circuit Detection Detail on Low-Side MOSFET 0.0 and output is latched-off. Freescale Semiconductor, Inc.
Figure 10. Typical Quiescent Supply Current Versus V+ Freescale Semiconductor, Inc.
Figure 15. Output Voltage and Current vs. Input Voltage at Figure 16. Output Voltage and Current vs. Input Voltage at Figure 17. Output Voltage and Current vs. Input Voltage at Figure 18. Output Voltage and Current vs. Input Voltage at Freescale Semiconductor, Inc.
Table 1. Truth Table X = HIGH or LOW, and Z = High impedance (all output power transistors are switched off).
- In the case of an undervoltage condition, the outputs tri-state and the fault status is SET logic LOW. Upon undervoltage recovery, fault status
is reset automatically or automatically cleared and the outputs are restored to their original operating condition.
- When a short circuit or overtemperature condition is detected, the power outputs are tri-state latched-OFF independent of the input signals
and the fault status flag is SET logic LOW. Freescale Semiconductor, Inc.
SYSTEM/APPLICATION INFORMATION INTRODUCTION Numerous protection and operational features (speed, torque, direction, dynamic braking, PWM control, and closed- loop control), in addition to the 5.0 A current capability, make the 33887 a very attractive, cost-effective solution for controlling a broad range of small DC motors. In addition, a pair of 33887 devices can be used to control bipolar stepper motors. The 33887 can also be used to excite transformer primary windings with a switched square wave to produce secondary winding AC currents. As shown in Figure 1, Simplified Internal Block Diagram, page 2, the 33887 is a fully protected monolithic H-Bridge with Enable, Fault Status reporting, and High-Side current sense feedback to accommodate closed-loop PWM control. For a DC motor to run, the input conditions need be as follows: Enable input logic HIGH, D1 input logic LOW, D2 input logic HIGH, FS flag cleared (logic HIGH), one IN logic LOW and the other IN logic HIGH (to define output polarity). The 33887 can execute dynamic braking by simultaneously turning on either both high- side MOSFETs or both low-side MOSFETs in the output H-Bridge; e.g., IN1 and IN2 logic HIGH or IN1 and IN2 logic LOW. The 33887 outputs are capable of providing a continuous DC load current of 5.0 A from a 40 V V+ source. An internal charge pump supports PWM frequencies to 10 kHz. An external pullup resistor is required at the FS terminal for fault status reporting. The 33887 has an analog feedback (current mirror) output terminal (the FB terminal) that provides a constant-current source ratioed to the active high-side MOSFET. This can be used to provide real time monitoring of load current to facilitate closed-loop operation for motor speed/torque control. Two independent inputs (IN1 and IN2) provide control of the two totem-pole half-bridge outputs. Two disable inputs (D1 and D2) provide the means to force the H-Bridge outputs to a high- impedance state (all H-Bridge switches OFF). An EN terminal controls an enable function that allows the 33887 to be placed in a power-conserving sleep mode. The 33887 has undervoltage shutdown with automatic recovery, active current limiting, output short-circuit latch-OFF, and overtemperature latch-OFF. An undervoltage shutdown, output short-circuit latch-OFF, or overtemperature latch-OFF fault condition will cause the outputs to turn OFF (i.e., become high impedance or tri-stated) and the fault output flag to be set LOW. Either of the Disable inputs or V+ must be toggled to clear the fault flag. Active current limiting is accomplished by a constant OFF- time PWM method employing active current limiting threshold triggering. The active current limiting scheme is unique in that it incorporates a junction temperature-dependent current limit threshold. This means the active current limiting threshold is ramped down as the junction temperature increases above 160°C, until at 175°C the current will have been decreased to about 4.0 A. Above 175°C, the overtemperature shutdown (latch-OFF) occurs. This combination of features allows the device to remain in operation for 30 seconds at junction temperatures above 150°C for nonrepetitive unexpected loads. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33887 FUNCTIONAL TERMINAL DESCRIPTION PGND and AGND Power and analog ground terminals should be connected together with a very low impedance connection. V+ terminals are the power supply inputs to the device. All V+ terminals must be connected together on the printed circuit board with as short as possible traces offering as low impedance as possible between terminals. V+ terminals have an undervoltage threshold. If the supply voltage drops below a V+ undervoltage threshold, the output power stage switches to a tri-state condition and the fault status flag is SET and the Fault Status terminal voltage switched to a logic LOW. When the supply voltage returns to a level that is above the threshold, the power stage automatically resumes normal operation according to the established condition of the input terminals and the fault status flag is automatically reset logic HIGH. Fault Status (FS) The FS terminal is the device fault status output. This output is an active LOW open drain structure requiring a pullup resistor to 5.0 V. Refer to Table 1, Truth Table, page 17. IN1, IN2, D1, and D2 These terminals are input control terminals used to control the outputs. These terminals are 5.0 V CMOS-compatible inputs with hysteresis. The IN1 and IN2 independently control OUT1 and OUT2, respectively. D1 and D2 are complementary inputs used to tri-state disable the H-Bridge outputs. When either D1 or D2 is SET (D1 = logic HIGH or D2 = logic LOW) in the disable state, outputs OUT1 and OUT2 are both tri- state disabled; however, the rest of the device circuitry is fully operational and the supply IQ(standby) current is reduced to a few milliamperes. Refer to Table 1, Truth Table, and STATIC ELECTRICAL CHARACTERISTICS table, page 8. OUT1 and OUT2 These terminals are the outputs of the H-Bridge with integrated output MOSFET body diodes. The bridge output is controlled using the IN1, IN2, D1, and D2 inputs. The low-side MOSFETs have active current limiting above the ILIM threshold. The outputs also have thermal shutdown (tri-state latch-OFF) with hysteresis as well as short circuit latch-OFF protection. A disable timer (time tb) incorporated to detect currents that are higher than current limit is activated at each output activation to facilitate hard short detection (see Figure 7, page 12). CCP A filter capacitor (up to 33 nF) can be connected from the charge pump output terminal and PGND. The device can operate without the external capacitor, although the CCP capacitor helps to reduce noise and allows the device to perform at maximum speed, timing, and PWM frequency. EN The EN terminal is used to place the device in a sleep mode so as to consume very low currents. When the EN terminal voltage is a logic LOW state, the device is in the sleep mode. The device is enabled and fully operational when the EN terminal voltage is logic HIGH. An internal pulldown resistor maintains the device in sleep mode in the event EN is driven through a high impedance I/O or an unpowered microcontroller, or the EN input becomes disconnected. FB The 33887 has a feedback output (FB) for real time monitoring of H-Bridge high-side current to facilitate closed- loop operation for motor speed and torque control. The FB terminal provides current sensing feedback of the H-Bridge high-side drivers. When running in the forward or reverse direction, a ground referenced 1/375th (0.00266) of load current is output to this terminal. Through the use of an external resistor to ground, the proportional feedback current can be converted to a proportional voltage equivalent and the controlling microcontroller can read the current proportional voltage with its analog-to-digital converter (ADC). This is intended to provide the user with motor current feedback for motor torque control. The resistance range for the linear operation of the FB terminal is 100 <RFB <200 Ω. If PWM-ing is implemented using the disable terminal inputs (either D1 or D2), a small filter capacitor (1.0µF or less) may be required in parallel with the external resistor to ground for fast spike suppression. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
If an output short circuit condition is detected, the power outputs tri-state (latch-OFF) independent of the input (IN1 and IN2) states, and the fault status output flag is SET logic LOW. If the D1 input changes from logic HIGH to logic LOW, or if the D2 input changes from logic LOW to logic HIGH, the output bridge will become operational again and the fault status flag will be reset (cleared) to a logic HIGH state. The output stage will always switch into the mode defined by the input terminals (IN1, IN2, D1, and D2), provided the device junction temperature is within the specified operating temperature range. Active Current Limiting The maximum current flow under normal operating conditions is internally limited to ILIM (5.2 A to 7.8 A). When the maximum current value is reached, the output stages are tri- stated for a fixed time (ta) of 20 µs typical. Depending on the time constant associated with the load characteristics, the current decreases during the tri-state duration until the next output ON cycle occurs (see Figures 7 and 13, page 12 and page 15, respectively). The current limiting threshold value is dependent upon the device junction temperature. When -40°C ≤ TJ ≤ 160°C, ILIM is between 5.2 A to 7.8 A. When TJ exceeds 160°C, the ILIM current decreases linearly down to 4.0 A typical at 175°C. Above 175°C the device overtemperature circuit detects TLIM and overtemperature shutdown occurs (see Figure 5, page 11). This feature allows the device to remain operational for a longer time but at a regressing output performance level at junction temperatures above 160°C. Overtemperature Shutdown and Hysteresis If an overtemperature condition occurs, the power outputs are tri-stated (latched-OFF) and the fault status flag is SET to logic LOW. To reset from this condition, D1 must change from logic HIGH to logic LOW, or D2 must change from logic LOW to logic HIGH. When reset, the output stage switches ON again, provided that the junction temperature is now below the overtemperature threshold limit minus the hysteresis. Note Resetting from the fault condition will clear the fault status flag.
PACKAGE INFORMATION
The 33887 packages are designed for thermal performance. The significant feature of these packages is the exposed pad on which the power die is soldered. When soldered to a PCB, this pad provides a path for heat flow to the ambient environment. The more copper area and thickness on the PCB, the better the power dissipation and transient behavior will be. Example Characterization on a double-sided PCB: bottom side area of copper is 7.8 cm2; top surface is 2.7 cm2 (see Figure 19); grid array of 24 vias 0.3 mm in diameter. Figure 19. PCB Test Layout Figure 20. 33887 Thermal Response, HSOP Package Freescale Semiconductor, Inc.
DETAIL Y(1.600) L W W q ccc C ccc D D SEATING PLANE DATUM PLANE A A2 DETAIL Y C H BOTTOM VIEW EXPOSED HEATSINK AREA DIM MIN MAX MILLIMETERS A 3.100 3.350 A1 0.050 BSC A2 3.100 3.250 D 15.800 16.000 D1 12.270 12.470 D2 0.900 1.100 E 13.950 14.450 E1 10.900 11.100 E2 2.500 2.700 E3 7.000 7.200 L 0.840 1.100 L1 0.350 BSC b 0.400 0.520 b1 0.400 0.482 c 0.230 0.310 c1 0.230 0.280 e 1.270 BSC h --- 1.100 q 0 8 aaa 0.200 bbb 0.200 E4 2.700 2.900 ccc 0.100 NOTES: 1. CONTROLLING DIMENSION: MILLIMETER. 2. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DA TUM PLANE -H- IS LOCA TED A T BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY A T THE BOTTOM OF THE P ARTING LINE. 4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.150 PER SIDE. DIMENSIONS D AND E1 DO INCLUDE MOLD MISMA TCH AND ARE DETERMINED A T DA TUM PLANE -H-. 5. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.178 TOT AL IN EXCESS OF THE b DIMENSION A T MAXIMUM MA TERIAL CONDITION. 6. DA TUMS -A- AND -B- TO BE DETERMINED A T DA TUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE TIEBAR PROTRUSIONS. ALLOWABLE TIEBAR PROTRUSIONS ARE 0.150 PER SIDE. X 45˚ h E D e18X e/2 BMbbb C 1110 A B PIN ONE ID SECTION W-W b c AMaaa C DH SUFFIX VW (Pb-FREE) SUFFIX 20-TERMINAL HSOP PLASTIC PACKAGE CASE 979-04 ISSUE C Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33887 M M DETAIL G PIN 1 INDEX AREA 0.1 C C0.1
0.1 ACB
3.2 36 19 10 PIN 1 INDEX A B 6.5 5.5 6.5 5.5 3.2 0.4 1.08 0.94 32X 0.60 0.4532X
0.1 M ACB
0.05 M C
4.3 40X (0.175) 4.3 2X40X 0.9 0.7 0.37 0.23 4 PLACES 2.2 2.0 2.20 1.95 0.05 0.00 (0.8) (0.55) DETAIL G VIEW ROTATED 90˚ CW C0.1
0.05 C 4
C SEATING PLANE 0.6 0.42X NOTES: ALL DIMENSIONS ARE IN MILLIMETERS. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. THE COMPLETE JEDEC DESIGNATOR FOR THIS PACKAGE IS: F-PQFP-N. COPLANARITY APPLIES TO LEADS AND CORNER LEADS. PNB (Pb-FREE) SUFFIX 36-TERMINAL PQFN NON-LEADED PACKAGE CASE 1503-01 ISSUE O Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
17.8 7.4 27 28 B C7.6 18.0 10.3 5.15
0.3 A B C
0.10 A 2.35 SEATING PLANE 0.65 A 54X 52X 2.65 0.9 SECTION B-B R0.08 MIN 0.1 0.00.50˚ 0.25 GAUGE PLANE MIN (1.43) NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. DA TUMS B AND C TO BE DETERMINED A T THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY . 4. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GA TE BURRS. MOLD FLASH, PROTRUSION OR GA TE BURRS SHALL NOT EXCEED 0.15 MM PER SIDE. THIS DIMENSION IS DETERMINED A T THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY . 5. THIS DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH AND PROTRUSIONS SHALL NOT EXCEED 0.25 MM PER SIDE. THIS DIMENSION IS DETERMINED A T THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY . 6. THIS DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46 MM. DAMBAR CANNOT BE LOCA TED ON THE LOWER RADIUS OR THE FOOT . MINIMUM SP ACE BETWEEN PROTRUSION AND ADJACENT LEAD SHALL NOT LESS THAN 0.07 MM. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPL Y TO THE FLA T SECTION OF THE LEAD BETWEEN 0.1 MM AND 0.3 MM FROM THE LEAD TIP . 9. THE P ACKAGE TOP MAY BE SMALLER THAN THE P ACKAGE BOTTOM. THIS DIMENSION IS DETERMINED A T THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GA TE BURRS AND INTER-LEAD FLASH, BUT INCLUDING ANY MISMA TCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY . A A CC (0.29) 0.38 0.30 (0.25) PLATING BASE METAL SECTION A-A ROTATED 90˚ CLOCKWISE 0.25 0.22 M0.13 CAB 4.8 4.3
0.30 CAB
4.8 4.3 54-TERMINAL SOICW EXPOSED PAD PLASTIC PACKAGE CASE 1390-01 ISSUE B Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33887 NOTES Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33887 NOTES Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
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