MC33879 MOTOROLA | Alldatasheet
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Designed to Operate 5.5 V < VPWR < 26.5 V 16-Bit SPI for Control and Fault Reporting, 3.3 V/5.0 V Compatible Outputs Are Current Limited (0.5 A to 1.0 A) to Drive Incandescent Lamps Output Voltage Clamp, +45 V (Low Side) and -20 V (High Side) During Inductive Switching On/Off Control of Open Load Detect Current (LED Application) Internal Reverse Battery Protection on V PWR Loss of Ground or Supply Will Not Energize Loads or Damage IC Maximum 5.0 µA I PWR Standby Current at 13.0 V VPWR R DS(ON) of 1.0 Ω at 25°C Typical Short Circuit Detect and Current Limit with Automatic Retry Independent Overtem perature Protection Motorola Now Offers Pb-Free Packaging with the Suffix EK CONFIGURABLE OCTAL SERIAL SWITCH WITH OPEN LOAD DETECT CURRENT DISABLE EK (Pb-FREE) SUFFIX DWB SUFFIX CASE 1437-01 32-LEAD SOICW-EP
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Range (TA) Package PC33879DWB/R2 -40°C to 125°C 32 SOICW-EP PC33879EK/R2 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
33879 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Figure 1. 33879 Simplified Internal Block Diagram Freescale Semiconductor, Inc.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33879 PIN FUNCTION DESCRIPTION Pin Pin Name Formal Name Definition 1G N D Ground Digital ground. 2V DD Logic Supply Voltage Logic supply for SPI interface. With VDD low the device will be in sleep mode. 3S 8 Source Output 8 Output eight MOSFET source pins. 4, 8, 9, 24, 25, 30 NC Not Connected No internal connection to this pin. 5D 8 Drain Output 8 Output eight MOSFETdrain pin. 6S 2 Source Output 2 Output two MOSFET source pin. 7D 2 Drain Output 2 Output two MOSFET drain pin. 10 S1 Source Output 1 Output one MOSFET source pin. 11 D1 Drain Output 1 Output one MOSFET drain pin. 12 D6 Drain Output 6 Output six MOSFET drain pin. 13 S6 Source Output 6 Output six MOSFET source pin. 14 IN6 Command Input 6 PWM direct control input pin for output 6. IN6 is OR with SPI bit. 15 EN Enable Input IC Enable. Active high. With EN low, the device is in sleep mode. 16 SCLK SPI Clock SPI control clock input pin. 17 DI Serial Data Input SPI control data input pin from MCU to the 33879. Logic [1] activates output. 18 CS SPI Chip Select SPI control chip select input pin from MCU to the 33879. Logic [0] allows data to be transferred in. 19 IN5 Command Input 5 PWM direct control input pin for output 5. IN5 is OR with SPI bit. 20 S5 Source Output 5 Output five MOSFET source pin. 21 D5 Drain Output 5 Output five MOSFET drain pin. 22 D3 Drain Output 3 Output three MOSFET drain pin. 23 S3 Source Output 3 Output three MOSFET source pin. 26 D4 Drain Output 4 Output four MOSFET drain pin. 27 S4 Source Output 4 Output four MOSFET source pin. 28 D7 Drain Output 7 Output seven MOSFET drain pin. 29 S7 Source Output 7 Output seven MOSFET source pin. 31 V PWR Battery Input Power supply pin to the 33879. V PWR has internal reverse battery protection. 32 DO Serial Data Output SPI control data output pin from the 33879 to the MCU. DO=0 no fault, DO=1 specific output has fault. DO1 NC NC CS DI IN5 VPWR NC GND NC NC EN SCLK IN6 NC V DD Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
All voltages are with respect to ground unless otherwise noted. Rating Symbol Value Unit VDD Supply Voltage (Note 1) VDD -0.3 to 7.0 V DC CS, DI, DO, SCLK, IN5, IN6, and EN (Note 1) -0.3 to 7.0 V DC VPWR Supply Voltage (Note 1) VPWR -16 to 40 V DC Output Clamp Energy (Note 2) ECLAMP 50 mJ ESD Voltage Human Body Model (Note 3) Machine Model (Note 4) VESD1 VESD2 ±2000 ±200 V Storage Temperature T STG -55 to 150 °C Operating Case Temperature T C -40 to 125 °C Operating Junction Temperature T J -40 to 150 °C Maximum Junction Temperature T J -40 to 150 °C Power Dissipation (Note 5) PD 1.7 W Thermal Resistance Junction-to-Ambient Between the Die and the Exposed Die Pad RθJA RθJC 1.2 °C/W Notes 1. Exceeding these limits may cause malfunction or permanent damage to the device. 2. Maximum output clamp energy capability at 150 °C junction temperature using single non-repetitive pulse method with I = 350 mA. 3. ESD1 testing is performed in accordance with the Human Body Model (C ZAP = 100 pF, RZAP = 1500 Ω). 4. ESD2 testing is performed in accordance with the Machine Model (C ZAP = 200 pF, RZAP = 0 Ω). 5. Maximum power dissipation at T A = 25°C with no heatsink used. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33879 STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions of 3.1 V ≤ VDD ≤ 5.5 V, 5.5 V ≤ VPWR ≤ 18 V, -40°C ≤ TC ≤ 125°C unless otherwise noted. Where applicable, typical values reflect the parameters approximate average value with VPWR = 13 V, TA = 25°C. Characteristic Symbol Min Typ Max Unit POWER INPUT Supply Voltage Range Fully Operational VPWR(fo) 5.5 26.5 V Supply Current I PWR(on) 1 42 4 m A Sleep State Supply Current VDD or EN ≤ 0.8 V, VPWR = 13 V IPWR(ss) 2 . 05 . 0 µA Sleep State Supply Current EN ≤ 0.8 V, VDD = 5.5 V IVDD(ss) 2 . 05 . 0 µA VPWR Overvoltage Shutdown Threshold Voltage V PWR(OV) 27 28.5 32 V VPWR Overvoltage Shutdown Hysteresis Voltage V PWR(OV-hys) 0.2 1.5 2.5 V VPWR Undervoltage Shutdown Threshold Voltage V PWR(UV) 3.0 4.0 5.0 V VPWR Undervoltage Shutdown Hysteresis Voltage V PWR(UV-hys) 300 500 700 mV Logic Supply Voltage V DD 3.1 5.5 V Logic Supply Current I DD 250 400 700 µA Logic Supply Sleep State Threshold Voltage V DD(SS) 0.8 2.5 3.0 V Logic Supply Sleep State Hysteresis (Note 6) VDD(SS-hys) 0.3 1.5 V Notes 6. This parameter is guaranteed by design but is not production tested. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
Drain-to-Source ON Resistance IOUT = 0.350 A, TJ = 125°C, VPWR = 13 V IOUT = 0.350 A, TJ = 25°C, VPWR = 13 V IOUT = 0.350 A, TJ = -40°C, VPWR = 13 V RDS (ON) 1.0 1.4 Ω Output Self Limiting Current High-Side and Low-Side Configurations I OUT(LIM) 0.5 1.0 A Output Fault Detection Voltage Threshold (Note 7) Outputs Programmed OFF VOUT(flt-th) 2.5 3.5 4.2 V Output Fault Detection Current @ Threshold, High-Side Configuration Outputs Programmed OFF IOUT(flt-th) 35 55 70 µA Output Fault Detection Current @ Threshold, Low-Side Configuration Outputs Programmed OFF IOUT(flt-th) 20 30 50 µA Output OFF Open Load Detection Current, High-Side Configuration VDrain = 16 V, VSource = 0 V, Outputs Programmed OFF IOCO 65 100 160 µA Output OFF Open Load Detection Current, Low-Side Configuration VDrain = 16 V, VSource = 0 V, Outputs Programmed OFF IOCO 40 75 135 µA Output Clamp Voltage Low-Side Drive ID = 10 mA VOC(LSD) 40 45 55 V Output Clamp Voltage High-Side Drive IS = -10 mA VOC(HSD) -15 -20 -25 V Output Leakage Current High-Side and Low-Side Configurations VDD = 0 V, VDrain = 16 V, VSource = 0 V IOUT(LKG) 7 . 0 µA Output Leakage Current Low-Side Configuration VDD = 5.0 V, VDrain = 16 V, VSource = 0 V, Open Load Detection Current Disabled IOUT(LKG) 5 µA Output Leakage Current High-Side Configuration VDD = 5.0 V, VDrain = 16 V, VSource = 0 V, Open Load Detection Current Disabled IOUT(LKG) 2 0 µA Overtemperature Shutdown (Note 8) TLIM 155 185 °C Overtemperature Shutdown Hysteresis (Note 8) TLIM(hys) 5.0 10 15 °C Notes 7. Output fault detection thresholds with outputs programmed OFF. Output fault detect thresholds are the same for output open and shorts. 8. This parameter is guaranteed by des ign but is not production tested. STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions of 3.1 V ≤ VDD ≤ 5.5 V, 5.5 V ≤ VPWR ≤ 18 V, -40°C ≤ TC ≤ 125°C unless otherwise noted. Where applicable, typical values reflect the parameters approximate average value with VPWR = 13 V, TA = 25°C. Characteristic Symbol Min Typ Max Unit Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33879 STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions of 3.1 V ≤ VDD ≤ 5.5 V, 5.5 V ≤ VPWR ≤ 18 V, -40°C ≤ TC ≤ 125°C, unless otherwise noted. Typical values, where applicable, reflect the parameters approximate average value with VPWR = 13 V, TA = 25°C Characteristic Symbol Min Typ Max Unit DIGITAL INTERFACE Input Logic High-Voltage Thresholds (Note 9) VIH 0.7 x VDD V DD + 0.3 V Input Logic Low-Voltage Thresholds (Note 9) VIL GND - 0.3 0.2 x V DD V IN5, IN6, EN Input Logic Current IN5, IN6, EN = 0 V IIN5, IIN6, IEN -10 10 µA IN5, IN6 Pull-Down Current 0.8 V to 5.0 V IIN5, IIN6, 30 45 100 µA EN Pull-Down Current EN = 5.0 V IEN 30 45 100 µA SCLK, DI Input, Tri-State DO Output 0 V to 5.0 V ISCK, IDI, ITriDO -10 10 µA CS Input Current CS = VDD ICS -10 10 µA CS Pull-Up Current CS = 0 V ICS -30 -100 µA CS Leakage Current to VDD CS = 5.0 V, VDD = 0 V ICS(LKG) 1 0 µA DO High-State Output Voltage IDO-HIGH = -1.6 mA VDOHIGH VDD - 0.4 V DD V DO Low-State Output Voltage IDO-LOW = 1.6 mA VDOLOW 0 . 4 V Input Capacitance on SCLK, DI, Tri-State DO, IN5, IN6, EN (Note 10) CIN 20 pF Notes 9. Upper and lower logic threshold voltage levels apply to DI, CS, SCLK, IN5, IN6, and EN. 10. This parameter is guaranteed by design but not production tested. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
DYNAMIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions of 3.1 V ≤ VDD ≤ 5.5 V, 5.5 V ≤ VPWR ≤ 18 V, -40°C ≤ TC ≤ 125°C unless otherwise noted. Where applicable, typical values reflect the parameters approximate average value with VPWR = 13 V, TA = 25°C. Characteristic Symbol Min Typ Max Units POWER OUTPUT TIMING Output Slew Rate Low-Side Configuration (Note 11) RLOAD = 620 Ω, CL = 200 pF tSR(rise) 0.1 0.5 1.0 V/µs Output Slew Rate Low-Side Configuration (Note 11) RLOAD = 620 Ω, CL = 200 pF tSR(fall) 0.1 0.5 1.0 V/µs Output Rise Time High-Side Configuration (Note 11) RLOAD = 620 Ω, CL = 200 pF tSR(rise) 0.1 0.3 1.0 V/µs Output Fall Time High-Side Configuration (Note 11) RLOAD = 620 Ω, CL = 200 pF tSR(fall) 0.1 0.3 1.0 V/µs Output Turn ON Delay Time, High-Side and Low-Side Configuration (Note 12) tDLY(on) 1.0 15 50 µs Output Turn OFF Delay Time, High-Side and Low-Side Configuration (Note 12) tDLY(off) 1.0 30 100 µs Output Fault Delay Time (Note 13) tFAULT 100 300 µs Power-ON Reset Delay Delay Time Required from Rising Edge of EN and VDD to SPI Active tPOR 100 µs Low-State Duration on VDD or EN for Reset VDD or EN ≤ 0.2 V tRESET 100 µs Notes 11. Output slew rate respectively measured across a 620 Ω resistive load at 10 to 90 percent and 90 to 10 percent voltage points. CL Capacitor is connected from Drain or Source output to Ground. 12. Output turn ON and OFF delay time measured from 50 percent rising edge of CS to the beginning of the 10 and 90 percent transition points. 13. Duration of fault before fault bit is set. Dura tion between access times must be greater than 300 µs to read faults. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33879 DIGITAL INTERFACE TIMING (Note 14) Recommended Frequency of SPI Operation (Note 14) fSPI 4 . 0 M H z Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) t LEAD 100 ns Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) t LAG 50 ns DI to Falling Edge of SCLK (Required Setup Time) t DI(su) 16 ns Falling Edge of SCLK to DI (Required Hold Time) t DI(HOLD) 20 ns DI, CS, SCLK Signal Rise Time (Note 15) tr(DI) 5 . 0 n s DI, CS, SCLK Signal Fall Time (Note 15) tf(DI) 5 . 0 n s Time from Falling Edge of CS to DO Low Impedance (Note 16) tDO(EN) 55 ns Time from Rising Edge of CS to DO High Impedance (Note 17) tDO(DIS) 55 ns Time from Rising Edge of SCLK to DO Data Valid (Note 18) tVALID 2 55 5 n s Notes 15. Rise and Fall time of incoming DI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing. 16. Time required for output status data to be available for use at DO pin. 17. Time required for output status data to be terminated at DO pin 18. Time required to obtain valid data out from DO following the rise of SCLK. DYNAMIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions of 3.1 V ≤ VDD ≤ 5.5 V, 5.5 V ≤ VPWR ≤ 18 V, -40°C ≤ TC ≤ 125°C unless otherwise noted. Where applicable, typical values reflect the parameters approximate average value with VPWR = 13 V, TA = 25°C. Characteristic Symbol Min Typ Max Units Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
Figure 2. SPI Timing Diagram Figure 3. Valid Data Delay Time and Valid Time Test Circuit Figure 4. Valid Data Delay Time and Valid Time Waveforms Figure 5. Enable and Disable Time Waveforms
0.7 VDD
0.2 VDD
Freescale Semiconductor, Inc.
Figure 6. IPWR vs. Temperature Figure 7. Sleep State IPWR vs. Temperature Figure 8. Sleep State IPWR vs. VPWR Figure 9. RDS(ON) vs. Temperature at 350 mA Figure 10. RDS(ON) vs. VPWR at 350 mA
1.4 TA = 25°C
Freescale Semiconductor, Inc.
Figure 11. Open Load Detection Current at Threshold Figure 12. Open Load Detection Threshold vs. Freescale Semiconductor, Inc.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33879 SYSTEM/APPLICATION INFORMATION FUNCTIONAL PIN DESCRIPTION CS Pin The system MCU selects the 33879 with which to communicate through the use of the chip select CS pin. Logic low on CS enables the data output (DO) driver and allows data to be transferred from the MCU to the 33879 and vice versa. Data clocked into the 33879 is acted upon on the rising edge of CS. To avoid any spurious data, it is essential the high-to-low transition of the CS signal occur only when SPI clock (SCLK) is in a logic low state. SCLK Pin The SCLK pin clocks the internal shift registers of the 33879. The serial data input (DI) pin is latched into the input shift register on the falling edge of the SCLK. The serial data output (DO) pin shifts data out of the shift register on the rising edge of the SCLK signal. False clocking of the shift register must be avoided to ensure validity of data. It is essential that the SCLK pin be in a logic low state when the CS pin makes any transition. For this reason, it is recommended the SCLK pin is commanded to a logic low state when the device is not accessed (CS in logic high state). With CS in a logic high state, signals present on SCLK and DI are ignored and the DO output is tri-state. DI Pin The DI pin is used for serial instruction data input. DI information is latched into the input register on the falling edge of SCLK. A logic high state present on DI will program a specific output on. The specific output will turn on with the rising edge of the CS signal. Conversely, a logic low state present on the DI pin will program the output off. The specific output will turn off with the rising edge of the CS signal. To program the eight outputs and Open Load Detection Current on or off, send the DI data beginning with the Open Load Detection Current bits, followed by output eight, output seven, and so on to output one. For each falling edge of the SCLK while CS is logic low, a data bit instruction (on or off) is loaded into the shift register per the data bit DI state. Sixteen bits of entered information is required to fill the input shift register. DO Pin The DO pin is the output from the shift register. The DO pin remains tri-state until the CS pin is in a logic low state. All faults on the 33879 device are reported as logic [1] through the DO data pin. Regardless of the configuration of the driver, open loads and shorted loads are reported as logic [1]. Conversely, normal operating outputs with non-faulted loads are reported as logic [0]. Outputs programmed with Open Load Detection Current disabled will report logic [0] in the off state. The first eight positive transitions of SCLK will report logic [0] followed by the status of the eight output drivers. The DI/DO shifting of data follows a first-in, first-out protocol with both input and output words transferring the most significant bit (MSB) first. EN Pin The EN pin on the 33879 enables the device. With the EN pin high, output drivers may be activated and open/short fault detection performed and reported. With the EN pin low, all outputs become inactive, Open Load Detection Current is disabled, and the device enters sleep mode. The 33879 will perform Power-ON Reset on rising edge of the enable signal. IN5 and IN6 Pins The IN5 and IN6 command inputs allow outputs five and six to be used in PWM applications. The IN5 and IN6 pins are OR-ed with the Serial Peripheral Interface (SPI) command input bits. For SPI control of outputs five and six, the IN5 and IN6 pins should be grounded or held low by the microprocessor. When using IN5 or IN6 to PWM the output, the control SPI bit must be logic [0]. Maximum PWM frequency for each output is 2.0 kHz. VDD Pin The VDD input pin is used to determine logic levels on the microprocessor interface (SPI) pins. Current from VDD is used to drive DO output and the pull-up current for CS. VDD must be applied for normal mode operation. The 33879 device will perform Power-ON Reset with the application of VDD. VPWR Pin The VPWR pin is battery input and Power-ON Reset to the 33879 IC. The VPWR pin has internal reverse battery protection. All internal logic current is provided from the VPWR pin. The 33879 will perform Power-ON Reset with the application of VPWR. D1D8 Pins The D1 to D8 pins are the open-drain outputs of the 33879. For high-side drive configurations, the drain pins are connected to battery supply. In low-side drive configurations, the drain pins are connected to the low side of the load. All outputs may be configured individually as desired. When configured as low-side drive, the 33879 limits the positive inductive transient to 45 V. S1S8 Pins The S1 to S8 pins are the source outputs of the 33879. For high-side drive configurations, the source pins are connected directly to the load. In low-side drive configurations, the source is connected to ground. All outputs may be configured individually as desired. When high-side drive is used, the 33879 will limit the negative inductive transient to negative 20 V. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
the 33879 is shown in Figure 1 on page 2. provide fast inductive turn-off and transient protection. basic SPI configuration between an MCU and one 33879. Figure 13. SPI Interface with Microcontroller
- Data from the MCU is clocked daisy chain through each
transferred to the MCU via the Master In Slave Out (MISO) line. is then transferred to the output driver. Figure 14. 33879 SPI System Daisy Chain Figure 15. Parallel Input SPI Control
16 Bits16 Bits
8 Outputs 8 Outputs 8 Outputs
8 Outputs
Freescale Semiconductor, Inc.
- The MSB is sent and received first. As Table 1 shows,
which the fault is communicated to the microprocessor. Table 1. Command Register Definition 0 = Bits 0 to 7, Output commanded OFF. 0 = Bits 8 to 15, Open Load Detection Current OFF. 1 = Bits 0 to 7, Output commanded ON. 1 = Bits 8 to 15 Open Load Detection Current ON. Table 2. Fault Register Definition 0 = Bits 0 to 7, No Fault at Output. Bits 8 to 15 will always return 0. Table 3. Fault Operation
00000000 O U T 8
Overtemperature Fault reported by serial output (DO) pin. Overcurrent DO pin reports short to battery/supply or overcurrent condition. Output ON Open Load Fault Not reported. Output OFF Open Load Fault DO pin reports output OFF open load condition only with Open Load Detection Current enabled. DO pin will report 0 for Output OFF Open Load Fault with Open Load Detection Current disabled. outputs assuming the previous state upon recovery from overvoltage. recovery from overtemperature. Freescale Semiconductor, Inc.
The 33879 device has been designed with ultra-low sleep mode currents. The device may enter sleep mode via the EN pin or the VDD pin. In the sleep mode (EN or VDD ≤ 0.8 V), the current consumed by the VPWR pin is less than 5.0 µA. Placing the 33879 in sleep mode resets the internal registers to the Power-ON Reset state. The reset state is defined as all outputs off and Open Load Detection Current disabled. To place the 33879 in the sleep mode, either command all outputs off and apply logic low to the EN input pin or remove power from the VDD supply pin. Prior to removing VDD from the device, it is recommended that all control inputs from the MCU be low. Paralleling of Outputs Using MOSFETs as an output switch conveniently allows the paralleling of outputs for increased current capability. RDS(ON) of MOSFETs have an inherent positive temperature coefficient that provides balanced current sharing between outputs without destructive operation. This mode of operation may be desirable in the event the application requires lower power dissipation or the added capability of switching higher currents. Performance of parallel operation results in a corresponding decrease in RDS(ON) while the output OFF Open Load Detection Currents and the output current limits increase correspondingly. Paralleling outputs from two or more different IC devices is possible but not recommended. Fault Logic Operation Fault logic of the 33879 device has been greatly simplified over other devices using SPI communications. As command word one is being written into the shift register, a fault status word is being simultaneously written out and received by the MCU. Regardless of the configuration, with no outputs faulted and Open Load Detection Current enabled, all status bits being received by the MCU will be zero. When outputs are faulted (off state open circuit or on state short circuit/overtemperature), the status bits being received by the MCU will be one. The distinction between open circuit fault and short/ overtemperature is completed via the command word. For example, when a zero command bit is sent and a one fault is received in the following word, the fault is open/short-to-battery for high-side drive or open/short-to-ground for low-side drive. In the same manner, when a one command bit is sent and a one fault is received in the following word, the fault is a short-to- ground/overtemperature for high-si de drive or short-to-battery/ overtemperature for low-side drive. The timing between two write words must be greater than 300µs to allow adequate time to sense and report the proper fault status. SPI Integrity Check Checking the integrity of the SPI communication with the initial power-up of the VDD and EN pins is recommended. After initial system start-up or reset, the MCU will write one 32-bit pattern to the 33879. The first 16 bits read by the MCU will be 8 logic [0]s followed by the fault status of the outputs. The second 16 bits will be the same bit pattern sent by the MCU. By the MCU receiving the same bit pattern it sent, bus integrity is confirmed. Please note the second 16-bit pattern the MCU sends to the device is the command word and will be transferred to the outputs with rising edge of CS. Important A SCLK pulse count strategy has been implemented to ensure integrity of SPI communications. SPI messages consisting of 16 SCLK pulses and multiples of 8 clock pulses thereafter will be acknowledged. SPI messages consisting of other than 16 + multiples of 8 SCLK pulses will be ignored by the device. Overtemperature Fault Overtemperature detection and shutdown circuits are specifically incorporated for each individual output. The shutdown following an overtemperature condition is independent of the system clock or any other logic signal. Each independent output shuts down at 155°C to 185°C. When an output shuts down owing to an overtemperature fault, no other outputs are affected. The MCU recognizes the fault by a one in the fault status register. After the 33879 device has cooled below the switch point temperature and 15°C hysteresis, the output will activate unless told otherwise by the MCU via SPI to shut down. Overvoltage Fault An overvoltage condition on the VPWR pin will cause the device to shut down all outputs until the overvoltage condition is removed. When the overvoltage condition is removed, the outputs will resume their previous state. This device does not detect an overvoltage on the VDD pin. The overvoltage threshold on the VPWR pin is specified as 27 V to 30 V, with 1.0 V typical hysteresis. A VPWR overvoltage detection is global, causing all outputs to be turned OFF. Output OFF Open Load Fault An output OFF open load fault is the detection and reporting of an open load when the corresponding output is disabled (input bit programmed to a logic low state). The Output OFF Open Load fault is detected by comparing the drain-to-source voltage of the specific MOSFET output to an internally generated reference. Each output has one dedicated comparator for this purpose. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
EK (Pb-FREE) SUFFIX DWB SUFFIX 32-LEAD SOIC WIDE BODY EXPOSED PAD PLASTIC PACKAGE CASE 1437-01 ISSUE O NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TO LERANCING PER ASME Y14.5M, 1994. 3. DATUMS B AND C TO BE DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 4. THIS DIMENSION DOES NO T INCLUDE MOLD FLASH, PROTRUSION OR GATE BURRS. MOLD FLASH, PROTRUSION OR GATE BURRS SHALL NOT EXCEED 0.15 mm PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 5. THIS DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH AND PROTRUSIONS SHALL NOT EXCEED 0.25 mm PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 6. THIS DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.4 mm PER SIDE. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD SHALL NOT LESS THAN 0.07 mm. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 mm AND 0.3 mm FROM THE LEAD TIP . 9. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. THIS DIMENSION IS DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTER-LEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. CL10.9 7.4 16 17 0.10 A 2.35 SEATING PLANE 0.9 SECTION B-B 0.65 R0.08 MIN B A PIN 1 ID (0.29) 0.38 0.25 (0.203) PLATING BASE METAL SECTION A-A ROTATED 90 CLOCKWISE° 0.19 0.22
0.13 M CA M B
A C7.6 11.1 10.3 5.15 A 32X 30X 2.65 0.3 A 2X 16 TIPS B C BB 0.1 0.0 0.50° 0°0.25 GAUGE PLANE MIN 5.7 4.7 5.3 6.4
0.3 A B C
iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33879 NOTES Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
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