PC33813AE

33813 FREESCALE | Alldatasheet

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Technical content

Document Number: MC33813 Rev. 1.0, 8/2012 Freescale Semiconductor Product Preview © Freescale Semiconductor, Inc., 2012. All rights reserved. *This document contains certain information on a new product. Specifications and information herein are subject to change without notice. One Cylinder Small Engine Control IC The 33813 is an engine control analog power IC intended for one cylinder motorcycle and other small engine control applications. The IC consists of five integrated low side drivers, two pre-drivers, a Variable Reluctance Sensor (VRS) input circuit, a voltage pre-regulator using an external pass transistor, and two 5.0 volt internal regulators, one for the microcontroller unit (MCU) VCC supply and the other for use as a protected sensor supply. Also included is an MCU reset control circuit with watchdog, an ISO 9141 K-line interface for diagnostic communication and a Serial Peripheral Interface (SPI). The five low side drivers are intended for driving a fuel injector, a lamp, two relays or other loads, and a tachometer. The pre- driver is intended to drive IGBT or MOSFET transistors to control ignition coils, and/or a HEGO heater. The device is packaged in a 48 pin LQFP- EP with an exposed pad. Features:

• Operates over a supply voltage range of 4.5 V  VPWR  36 V
• Logic stability guaranteed down to 2.5 V
• One fuel injector driver - typical of 1.3 A
• One ignition IGBT or general purpose gate pre-driver
• One O2 sensor (HEGO) heater general purpose gate pre-driver
• Relay 1 driver, typically 2.0 A, can be used for fuel pump control
• Relay 2 driver, typically 1.0 A, can be used as power relay control
• Lamp driver, typically 1.0 A can also be used to drive an LED
• V PROT protected sensor supply tracks VCC +5.0 V regulator
• MCU reset generator -system integrity monitor (watchdog)
• V PP pre-regulator provides power for VCC and VPROT regulators
• Independent fault protection with all faults reported via the SPI
• ISO 9141 K-line interface for communicating diagnostic messages
• Start-up / shut-down control and power sequence logic
• Interfaces directly to MCU using a 5.0 V SPI and logic I/O
• Differential / single-ended VRS conditioning circuit with auto/manual selected thresholds and filter times with digital and tachometer outputs

Figure 1. 33813 Simplified Application Diagram

Applications

Small Engine Control for:

• Lawn Mowers
• Motor Scooters
• Small Motorcycles
• Lawn Trimmers
• Snow Blowers
• Chain Saws
• Gasoline-driven Electrical Generators
• Outboard Motors ONE CYLINDER SMALL ENGINE CONTROL IC VPWR SPI VRSOUT MRX MC33813 SPI VBAT O2HOUT LAMPOUT MCU RESETB INJOUT1 ROUT1 Relay 1 MIL O2 Heater VBAT VBAT Injector RESETB Crankshaft VRS VRSP VRSN VCC MTX INJIN1 O2HINGPIO KEYSW ROUT2 VPPSENS GND +5.0 V IGNIN1 IGNOUT1 ISO9141 ISO9141 IGNFB1 O2HFBVPPREF VBAT Keyswitch Relay 2VPROT

5.0 V Sensor Supply

(Power) (Fuel Pump)TACHOUT TACHOMETER VCC BATSW IGNSENSP IGNSENSN O2HSENSP O2HSENSN GPIO GPIO RIN1 RIN2 GPIO

1 Orderable Parts

Table 1. Orderable Part Variations

1. To Order parts in Tape & Reel, add the R2 suffix to the part number.

Analog Integrated Circuit Device Data Freescale Semiconductor 3 33813 Table of Contents

2 Internal Block Diagram

Figure 2. Simplified Internal Block Diagram

3 Pin Connections

3.1 Pinout Diagram

Figure 3. 33813 Pin Connections

3.2 Pin Definitions

Table 2. 33813 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 24.

1 O2HFB Input O2 Sensor Heater

2 O2HOUT Output O2 Sensor Heater

3 IGNSENSP Input Ignition Current

4 IGNSENSN Input Ignition Current

5 O2HSENSN Input O2 Heater Current

6 O2HSENSP Input O2 Heater Current

7 VRSOUT Output VRS Conditioned

5.0 V Logic Level Output from conditioned VRS differential inputs VRSP,

8 VRSP Input Variable Reluctance

Sensor attached to the crankshaft toothed wheel.

9 VRSN Input Variable Reluctance

Sensor attached to the crankshaft toothed wheel. that the device is being addressed.

11 VPWR Supply Input Main Voltage Supply

SO pins while being addressed by the CSB. 13 SI Input SPI Data Input The SI input pin is used to receive serial data into the device from the MCU.

14 VPPREF Output VPP Reference Base

15 GND Ground Ground Ground pin, return for all voltage supplies

16 SO Output SPI Data Output The SO output pin is used to transmit serial data from the device to the MCU.

17 VCC Supply VCC Supply

for 5.0 Volt MCUs. It is short-circuit and over-current protected.

18 VPPSENS Input Voltage Sense from

19 RESETB Output RESETB Output to

5.0 V Logic level reset signal used to reset the MCU during under and over-

20 VPROT Output Sensor Supply

intended to supply sensors which are located off of the ECU board.

22 RGND2 Ground ROUT2 Power

a SPI controlled low side driver, or oscillator output.

27 MRX Output Low Side Driver

28 MTX Input ISO9141 MCU Data

A functional description of each pin can be found in the Functional Pin Description section beginning on page 24.

34 O2HIN Input O2 Sensor Heater

present in a different package. pin is not present in a different package. pin is not present in a different package. the PWREN bit in the SPI register is also low.

38 INJGND2 Ground Injector Driver

Ground connection for injector low side driver. Must be tied to VPWR ground.

40 RGND1 Ground ROUT1 Power

Ground connection for ROUT 1 low side driver. Must be tied to VPWR ground.

42 INJGND1 Ground Injector Driver 1

43 INJOUT1 Output Injector Driver 1

44 ISO9141 Input/Output ISO9141 K-Line

Input is a ratiometric VPWR level threshold comparator.

45 IGNFB1 Input Feedback from

46 IGNOUT1 Output Ignition Output 1 Output to gate of IGBT or GPGD for ignition # 1

A functional description of each pin can be found in the Functional Pin Description section beginning on page 24.

4 Electrical Characteristics

4.1 Maximum Ratings

Table 3. MAXIMUM RATINGS

• T JUNCTION = 150 °C IOC_INJX – 1.3 A Output Continuous Current (ROUT1)
• T JUNCTION = 150 °C IOC_R1 – 2.0 A Output Continuous Current (ROUT2)
• T JUNCTION = 150 °C IOC_R2 – 1.0 A Output Continuous Current (LAMPOUT)
• T JUNCTION = 150 °C IOC_LAMP – 1.0 A Output Continuous Current (TACHOUT)
• T JUNCTION = 150 °C IOC_TACH – 50 mA Maximum Voltage for VRSN and VRSP inputs to ground VVRS_IN -0.5 6.0 VDC Maximum Current for VRSN and VRSP inputs (internal diodes limit voltage) IVRSX_IN – 15 mA Output Clamp Energy (INJOUT1, ROUT1)(Single Pulse)
• T JUNCTION = 150 °C, IOUT = 1.0 A ECLAMP TBD 100 mJ Output Clamp Energy (INJOUT1)(Continuous Pulse)
• T JUNCTION = 125 °C, IOUT = 1.0 A, TBD kHz (Max Injector frequency is 70 Hz) ECLAMP TBD TBD mJ

• Maximum current into VRSN pin or VRSP pin and IC Ground IVRS_IN -15 +15 mA THERMAL RATINGS Operating Temperature (Automotive grade version)
• Ambient
• Junction
• C a s e TA TJ TC -40 -40 -40 125 150 125 Storage Temperature TSTG -55 150 C Power Dissipation (TA  25 C) PD – 3.0 W Peak Package Reflow Temperature During Reflow(4), (5) TPPRT – Note 5 °C THERMAL RESISTANCE AND PACKAGE DISSIPATION RATINGS Thermal Resistance
• Junction-to-Ambient (LQFP-48-EP Package) (Single Layer Board)
• Junction-to-Case (LQFP-48-EP Package) RJA RJC 2.4 2.4 C/W Notes 2. ESD data available upon request. (Items in red are not associated with any parameter) 3. ESD1 testing is performed in accordance with the Human B ody Model (AEC-Q100-002) and the Machine Model (AEC-Q100-003). 4. Pin soldering temperature limit is for 10 seconds maximum durat ion. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 5. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts (i.e. MC33xxxD enter 33xxx), and review parametrics.

4.2 Static Electrical Characteristics

Table 4. Power Input Static Electrical Characteristics noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25 C.

• Logic Stable Range
• Full Operational Range
• Full Parameter Specification Range VPWR (FO) VPWR (FO) VPWR (FP) 2.5 4.5 6.0 V Supply Current
• All Outputs Disabled (Normal Mode). Excludes base current to the external PNO. IVPWR (ON) – 10.0 14.0 mA Sleep State Supply Current (Must have PWREN & KEYSW  0.8 V for sleep state),
• V PWR = 18 V IVPWR (SS) – 10 20 VPWR Over-voltage Shutdown Threshold Voltage (OV Reset)(7) VPWR(OV) 37.5 39 42 V VPWR Over-voltage Shutdown Hysteresis Voltage VPWR (OV-HYS) 0.5 1.5 3.0 V VCC Power On Reset Voltage Threshold (POR Power On Reset), rising VT VCC(POR) 3.9 4.5 4.9 V VCC Under-voltage Shutdown Threshold Voltage (UV Reset)(8), falling VT VCC(UV) 2.9 3.7 3.9 V VCC POR and Under-voltage Shutdown Hysteresis Voltage VCC(UV/POR- HYS) 100 – – mV VCC POR and Under-voltage Non-overlap (POR-UV) VCC, NONOVERLAP 0.8 1.0 1.2 V VOLTAGE PRE- REGULATOR OUTPUT (VPPREF, VPPSENS) VPPREF Output Voltage (measured with VPPREF shorted to VPPSENS and no external output transistor) VPPREF 5.85 6.5 7.15 V VPPREF Output Current (includes external PNP current) IVPPREF – -5.0 – mA VPPREF Current Limit (VPWR-VPP = 5.5 V TJ = 25 °C) IVPPCL -5 -15 -20 mA Output Capacitance External (ceramic) VOCE 2.2 – 25 F VPPSENS Input Current (VPWR-VPP = 5.5 V TJ=25 °C) IVPPSENS – – 3.0 mA Line Regulation IVCC = 100 mA, IVPROT = 50 mA 9.0 V< VPWR < 18 V and Diodes Inc. FZT753TA PNP REGLINE_VPP – 2.0 25 mV Dropout Voltage (Minimal Input/Output Voltage, tracks input below) IVCC = 100 mA, IVPROT = 50 mA and Diodes Inc. FZT753TA PNP VDROPOUT_PP – 1.05 1.4 V VOLTAGE REGULATOR OUTPUTS (VCC, VPROT) VCC Output Voltage 0  IVCC IVCC_C 6.0 V< VPWR < 18 V VCC 4.9 5.0 5.1 V VCC Output Current Continuous IVCC_C – – 200 mA Notes 6. Over-voltage thresholds minimu m and maximum include hysteresis. 7. Under-voltage thresholds minimu m and maximum include hysteresis. 8. Device is functional provided T J is less than 150 C. Some table parameters may be out of specification.

• V DRAIN = 18 V, Outputs Programmed OFF I(OFF)OCO 40 75 115 Output OFF Open Load Detection Current Tachout 10 – 30 A Output Leakage Current
• V DRAIN = 24 V, Open Load Detection Disabled and Output commanded OFF IOUT (LKG) – – 20 A Over-temperature Shutdown (OT) (10) TLIM 155 – 185 C Over-temperature Shutdown Hysteresis(11) TLIM (HYS) 5.0 10 15 C Output Clamp Voltage
• I D = 20 mA VOC 48 53 58 V INJOUT1 Drain-to-Source ON Resistance
• I OUT = 1.0 A TJ = 125 °C, VPWR = 13 V
• I OUT = 1.0 A TJ = 25 °C, VPWR = 13 V
• I OUT = 1.0 A TJ = -40 °C, VPWR = 13 V RDS (ON)_INJx RDS (ON)_INJx RDS (ON)_INJx 0.4 0.6 Continuous current (not to exceed) IOUT(CC)_INJ x – – 1.3 A Output Self Limiting Current IOUT (LIM)_INJx 1.6 – 3.0 A Notes 10. This parameter is guaranteed by desi gn, however it is not production tested. 11. Programmable via SPI but vari able with magnitude input frequency

noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25 C.

• I OUT = 700 mA, TJ = 150 C, VPWR = 13 V RDS (ON)_R1 – 0.3 0.4 Continuous current (not to exceed) IOUT(CC)_ R1 – – 2.0 A Output Self-limiting Current (Has inrush current timer) IOUT (LIM)_R1 3.0 – 6.0 A ROUT2 Driver Drain-to-Source ON Resistance
• I OUT = 350 mA, TJ = 150 C, VPWR = 13 V RDS (ON)_R2 – – 1.5 Continuous current (not to exceed) IOUT(CC)_R2 – – 1.0 Output Self-limiting Current IOUT (LIM)_R2 1.2 – 2.4 LAMPOUT Driver Drain-to-Source ON Resistance
• I OUT = 1.0 A, TJ = 150 C, VPWR = 13 V RDS (ON)_LAMP – – 1.5 Continuous current IOUT(CC)_LAMP – - 1.0 A Output Self-limiting Current (Has inrush current timer) IOUT (LIM)_ LAMP 1.2 – 2.4 A TACHOUT Driver Drain-to-Source ON Resistance
• I OUT = 50 mA, TJ = 150 C, VPWR = 13 V RDS (ON)_TACH – – 20 Continuous current (not to exceed) IOUT(CC)_TACH – – 50 mA Output Current Shutdown IOUT (SHUTDO WN)_TACH 60 – 110 mA ALL PRE-DRIVERS (IGNOUT1, AND O2HOUT) Pre-driver Output Voltage (typical values measured at VPWR = 13 V
• I GD = 500 A
• I GD = -500 A VGS(ON) VGS(OFF) 4.8 0.0 8.0 0.375 9.0 0.5 V IGNOUTx Output Source Current (IGNOUT1 and IGNOUT2 by default)
• @ 1 . 0 VGD 3.0, VPWR = 13 V IIGN_GD_H 10 – – mA Output OFF Open Load Detection Current
• V DRAIN = 18 V, Outputs Programmed OFF I(OFF)OCO 40 75 115 GPGD Output Source Current (O2HOUT by default) @ 1.0 VGD 3.0, VPWR = 13 V IGPGD_GD_H 10 – – mA Output Fault Detection Voltage Threshold
• (For IGNOUTX AT IGNFBX PIN NOT AT INPUT OF 10:1 DIVIDER)
• (for 02HOUT @HFB pin)
• I GD = 500 A
• I GD = -500 A VIGNFB (FLT-TH) VGPGD(FLT_TH) 100 1.0 250 2.5 400 4.0 mV V Output Clamp Voltage VCLAMP 48 53 60 V

noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25 C.

• Steady State Condition (20% only valid for VRS DAC thresholds 110 mV and higher. All other thresholds guaranteed monotonic only.) AccuTHRESH – – 20 % Input Bias Current VRSP and VRSN (2.5 V common mode must be off) IBIASRSX -5.0 – 5.0 µA VRS Positive Clamp Voltage at ICLAMP = 10 mA VCLAMP_P 5.4 – 6.0 V VRS Negative Clamp Voltage at ICLAMP = 10 mA VCLAMP_N -0.44 – -0.22 V Notes 12. This parameter is guaranteed by desi gn, however it is not production tested.

noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25 C.

• KEYSW = 0 V I LOGIC_SS -10 – 10 Input Logic Pull-down Current INJIN1, RIN1, RIN2, SI, SCLK,IGNIN1, O2HIN
• 0.8 V to 5.0 V ILOGIC_PD 30 50 100 SCLK Input Current
• V SCLK = VCC I SCLK -10 – 10 SO Tri-state Output (in tri-state mode, CSB = 1)
• 0 V to 5.0 V I TRISO -10 – 10 CSB Input Current
• CSB = VCC ICSB -10 – 10 Input Logic Pull-up Current - CSB and MTX
• 0.0 to 4.2 V ILOGIC_PJ -30 -50 -100 CSB Leakage Current to VCC
• CSB = 5.0 V, KEYSW = 0.0 V ICSB(LKG) – – 10 SO, MRX High-state Output Voltage (CSB =0 for SO)
• I SO-HIGH = -1.0 mA VSO_HIGH VMRX_HIGH VCC - 0.4 – – V SO, MRX Low-state Output Voltage (CSB =0 for SO)
• I SO-LOW = 1.0 mA VSO_LOW VMRX_HIGH – – 0.4 V BATSW High-state Output Voltage ISO-HIGH = -10 mA VBATSW_HIGH VCC - 1.0 – – V BATSW Low-state Output Voltage ISO-LOW = 10 mA VBATSW_LOW – – 1.0 V KEYSW High-state Input Voltage VKEYSW_HIGH 4.5 - VPWR V KEYSW Low-state Input Voltage VKEYSW_LOW -0.3 - 2.5 V KEYSW Hysteresis VKEYSW_HYS 100 – – mV VRS Low-state Output Voltage IVRS-LOW= 1.0 mA VVRSOUT_LOW – – 0.4 V VRS Low-state Output Voltage IVRS-LOW= 1.0 mA VVRSOUT_HIGH VCC -0.4 – 5.0 V RESET Low-state Output Voltage IRESET-LOW= 1.0 mA VRESET_LOW – – 0.4 V Notes 13. This parameter is guaranteed by desi gn, however it is not production tested. 14. Programmable via SPI but vari able with magnitude input frequency.

noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25 C.

noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25 C.

4.3 Dynamic Electrical Characteristics

Table 5. Dynamic Electrical Characteristics (15) noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25 C.

• V CC  0.2 V t RESET 1.0 – – Power on RESET pulse width t(POR) 100 - - s WATCHDOG TIMER Maximum Time Value Watchdog can be loaded with (default time) WDMAX – – 10 sec. Minimum Time Value Watchdog can be loaded with WDMIN 1.0 – – ms Reset Pulse Width when Watchdog times out WDRESET 100 – – s VRS CONDITIONING INPUT Output Blanking Time Programming Range  (% of previous out pulse 0 to 15/32 in 1/32 steps, 15/32 = 46.9%) OUTPUTBLANK 0 – 50 % Output Deglitch Filter Time (1/128 of the previous output pulse) OUTPUTDEGLI TCH – 1.0 – % Delay from CSB to Change in VRS Comparator Threshold - GBD DELAYTHRESH – – 10 s Delay from CSB to Change in VRS Output Blank Time - GBD DELAYOBT – – 10 s ISO9141 TRANSCEIVER Typical ISO9141 Data Rate ISOBR – 10 – kbps Turn OFF Delay MTX Input to ISO Output tTXDF – – 2.0 s Turn ON/OFF Delay ISO Input to MRX Output tRXDF, tRXDR – – 1.0 s Rise and Fall Time MRX Output (measured from 10% to 90%) tRXR, tRXF – – 1.0 s Maximum Rise and Fall Time MTX Input (measured from 10% to 90%) tTXR, tTXF – – 1.0 s ALL LOW SIDE DRIVERS Output ON Current Limit Fault Filter Timer tSC1 30 60 90 µs Output Retry Timer tREF 7.0 10 13 ms Inrush Current Delay Timer tINRUSH 7.0 10 13 ms Output OFF Open Circuit Fault Filter Timer t(OFF)OC 100 – 400 µs Output Slew Rate ZLOAD = 14 and10 mHVLOAD = 14 V t SR(RISE) 1.0 5.0 10 V/s Output Slew Rate INJOUT1, ROUT1, ROUT2 and LAMPOUT
• Z LOAD = 14 and10 mH, VLOAD = 14 V t SR(FALL) 1.0 5.0 10 V/s Propagation Delay (Input Rising Edge OR CSB to Output Falling Edge)
• Input at 50% VDD to Output voltage 90% of VLOAD (INJ1, ROUT1, ROUT2, LAMP) tPHL – 1.0 5.0 µs Propagation Delay (Input Rising Edge OR CSB to Output Falling Edge)
• Input at 50% VDD to Output voltage 90% of VLOAD (TACHOMETER) tPHL – 1.0 6.0 µs Notes

• Input at 50%VDD to Output voltage 10% of VLOAD (INJ1, ROUT1, ROUT2, LAMP) tPLH – 1.0 5.0 µs Propagation Delay (Input Rising Edge OR CSB to Output Falling Edge)
• Input at 50%VDD to Output voltage 10% of VLOAD (TACHOMETER) tPLH – 1.0 6.0 µs Output Slew Rate, Tachout
• R LOAD = 500 VLOAD = 14 V t SR(FALL) 6.0 – 14 V/s ALL GATE PRE-DRIVER (IGN1 AND O2H) Output OFF Open-circuit Fault Filter Timer t(OFF)OC 100 – 400 µs Over-current (short-circuit) Fault Filter Timer tSC 30 – 90 µs Propagation Delay (Input Rising Edge OR CSB to Output Rising Edge)
• Input at 50%VDD to Output voltage 10% of VGS(ON) tPLH – 1.0 5.0 µs Propagation Delay (Input Falling Edge OR CSB to Output Falling Edge)
• Input at 50%VDD to Output voltage 90% of VGS(ON) tPHL – 1.0 5.0 µs SPI DIGITAL INTERFACE TIMING (16) Falling Edge of CSB to Rising Edge of SCLK
• Required Setup Time t LEAD 100 – – ns Falling Edge of SCLK to Rising Edge of CSB
• Required Setup Time t LAG 50 – – ns SI to Rising Edge of SCLK
• Required Setup Time t SI (SU) 16 – – ns Rising Edge of SCLK to SI
• Required Hold Time t SI (HOLD) 20 – – ns SI, CSB, SCLK Signal Rise Time (17) t R (SI) – 5.0 – ns SI, CSB, SCLK Signal Fall Time (17) t F (SI) – 5.0 – ns Time from Falling Edge of CSB Low-impedance (18) t SO (EN) – – 55 ns Time from Rising Edge off CSB to SO High-impedance (19) t SO (DIS) – – 55 ns Time from Falling Edge of SCLK to SO Data Valid (20) t VALID – 25 55 ns Sequential Transfer Rate
• Time required between data transfers tSTR – – 1.0 µs Notes 17. Rise and Fall time of incoming SI, CSB, and SCLK signals sugges ted for design consideration to prevent occurrence of double pulsing. 18. Time required for valid output status data to be available on SO pin. 19. Time required for output states data to be terminated at SO pin. 20. Time required to obtain valid data out from SO following the fall of SCLK with 200 pF load.

noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25 C.

4.4 Timing Diagrams

Figure 4. Timing Diagram

4.5 Typical Electrical Characteristics

Figure 5. IPWR vs. Temperature

0.7 VDD

0.2 VDD

Figure 14. Typical Electrical Specifications

Figure 15. Typical Electrical Specifications (continued)

Analog Integrated Circuit Device Data Freescale Semiconductor 24 33813

5 General IC Functional De scription and Application

5.1 Functional Pin Description

5.1.1 VPWR Supply Input

The VPWR pin is the battery input to the 33813 IC. The VPWR pin requires external reverse battery and adequate transient voltage protection. All IC analog current and internal logic current is provided from the VPWR pin. An over-voltage comparator monitors this pin and when an over-voltage condition is present all outputs and voltage regulators are shut off for protection. The VPWR pin should be bypassed to ground, as close to the IC as possible, with a 0.1 µF ceramic capacitor.

5.1.2 VPPREF Output

The VPPREF output pin is used to drive the base of an external regulator PNP pass transistor. The output of this VPP regulator supplies the input voltage to the two internal 5.0 Volt regulators. The VPP regulator is a low drop-out (LDO) regulator that provides a regulated output voltage when the input is greater than its specified voltage level, and follows the input voltage when it is below its specified voltage level. It is not recommended that this voltage be brought off of the module PC board, because it may not have adequate protection to prevent damage to the PNP pass transistor under short-to-ground or short-to-battery conditions.

5.1.3 VPPSENS Input

The VPPSENS pin is used to monitor the VPP pre-regulator output voltage from the external pass transistor’s collector, and to supply the input voltage to the VCC and VPROT regulators. The VPPSENS pin should be bypassed to ground, as close to the IC as possible, with a 0.1 µF ceramic capacitor and a higher value electrolytic capacitor in parallel. 5.1.4 VCC Output (5.0 V Supply) The VCC regulator obtains its input voltage from the VPP pre-regulator. The VCC output supplies 5.0 V power to the system MCU and other on-board peripherals. A Power On Reset (POR) circuit monitors the VCC output voltage level. When the VCC voltage exceeds the VCC(POR) threshold, the RESETB line is held low for an additional delay time, t(POR), and then brought to a logic one level. An under-voltage (UV) circuit monitors the output of the VCC regulator and when the voltage goes below the VCC(UV) threshold for more than the VCC filter time, t(VCC-UV), the RESETB line is asserted to a logic zero state and remains there until the POR condition is met. 5.1.5 VPROT Output (5.0 V Protected Supply) The VPROT regulator obtains its input voltage from the VPP pre-regulator and its reference voltage from the VCC output. VPROT tracks VCC and is protected against shorts to ground, shorts to battery, over-current and over-temperature. The VPROT output supplies 5.0 V power to any external sensors and other off-board peripherals. The VPROT regulator on/off state can be controlled via a bit in the SPI Control Registers. The VPROT output should be protected against ESD by means of a 0.1 µF ceramic capacitor on the output and a higher value electrolytic capacitor in parallel.

Analog Integrated Circuit Device Data Freescale Semiconductor 25 33813

5.1.6 GND

The GND pin provides the ground reference for the VPWR, VPP, VPROT and VCC supplies. The GND pin is used as a return for both the power supplies as well as power ground for some of the lower current output drivers. The higher current output drivers have their own ground pins. All ground pins (INJGND1, INJGND2, RGND1, and RGND2) and the exposed pad must be directly connected to this pin and the negative battery terminal. There is no separate ground pin associated with the LAMPOUT driver, it shares a ground with ROUT2.

5.1.7 SCLK Input

The serial clock (SCLK) pin clocks the internal SPI shift register of the 33813. The SI data is latched into the input shift register on the rising edge of SCLK signal. The SO pin shifts status bits out on the falling edge of SCLK. The SO data is available for the MCU to read on the rising edge of SCLK. With CSB in a logic high state, signals on the SCLK and SI pins will be ignored and the SO pin will be in a high-impedance state. The SCLK signal consists of a 50% duty cycle with CMOS logic levels referenced to VCC. All SPI transfers consist of exactly 16 SCLK pulses. If any more or less than 16 clock pulses are received within one frame of CSB going low and then high, a SPI error is reported in the SPI Status Register. The SPI error bit will also be set whenever an invalid SPI message is received, even though it may contain 16-bits.

5.1.8 CSB Input

The system MCU selects which slave is 33813 to receive SPI communication using separate chip select (CSB) pins. With the CSB in a logic low state, SPI words may be sent to the 33813 via the serial input (SI) pin, and status information is received by the MCU via the serial output (SO) pin. The falling edge of CSB enables the SO output and transfers status information into the SO buffer. The rising edge of the CSB initiates the following operation: 1. Disables the SO driver (high-impedance) 2. Activates the received command word, allowing the 33813 to activate/deactivate output drivers. To avoid any spurious data, it is essential that the high-to-low and low-to-high transitions of the CSB signal occur only when SCLK is in a logic low state. Internal to the 33813 device is an active pull-up to VCC on CSB. In cases where voltage exists on CSB without the application of VCC, no current will flow from CSB to the VCC pin. This input requires CMOS logic levels referenced to VCC and has an internal active pull-up current source.

5.1.9 SI Input

The SI pin is used for serial instruction data input. SI information is latched into the input register on the rising edge of SCLK and the input data transitions on the falling edge of SCLK. A logic high state present on SI will program a one in the command word on the rising edge of the CSB signal. To program a complete word, 16 bits of information must be entered into the device. This input requires CMOS logic levels referenced to VCC.

5.1.10 SO Output

The SO pin is the output from the SPI shift register. The SO pin remains high-impedance until the CSB pin transitions to a logic low state. All normal operating drivers are reported as zero, all faulted drivers are reported as one. The negative transition of CSB enables the SO driver. The SI / SO shifting of the data follows a first-in-first-out protocol, with both input and output words transferring the most significant bit (MSB) first. The serial output data is available to be latched by the MCU on the rising edge of SCLK. The SO data transitions on falling edge of the SCLK. This output provides CMOS logic levels referenced to VCC.

Analog Integrated Circuit Device Data Freescale Semiconductor 26 33813

5.1.11 KEYSW Input

KEYSW is the input from the vehicle ignition keyswitch. This signal is at VBAT (12 V) when the key is inserted and turned to the ON position. When the key is in the OFF position and/or removed from the keyswitch, this input is pulled to ground by an internal pull-down resistor. When this signal is low, and the PWREN SPI Control register bit is also low, the 33813 is in the sleep mode. If the PWREN SPI control register bit is logic one, when the KEYSW goes low, only the outputs are turned off (except ROUT2 if the Shut Down Disable bit is set). When the PWREN SPI Control register bit also goes to zero, the entire circuit enters Sleep mode. When KEYSW signal goes high, it wakes up the IC, turns on the VPP regulator and a Power On Reset signal is generated. This pin is internally protected against a reverse battery condition by an internal diode. The state of the KEYSW input is also available as a bit in the SPI Status Register.

5.1.12 PWREN SPI Control Register BIT

The PWREN signal is a bit in the SPI Control Register that, along with KEYSW, BATSW, and the ROUT2 output can provide the power start-up logic of the vehicle. The purpose of the PWREN signal is allow the MCU to control the shutdown of power to itself when the user turns off the KEYSW. This may be necessary to allow the MCU the time required to perform its pre-shutdown routines. When the MCU wants to shutdown the power supplies in the 33813, it must write a logic zero (0) to the PWREN bit in the SPI Control register. Only the state of the PWREN bit in the SPI Control register will control the shutdown of the 33813 power supplies.

5.1.13 BATSW Output

The BATSW output pin is a 5.0 V logic level output that by default is an indication of the state of the KEYSW input. When KEYSW is at VBAT (12 V) level the BATSW output is a logic 1 (5.0 V), and when KEYSW is at ground (0 V) level, BATSW is at a logic 0. The BATSW output may be used to inform the MCU that the user is trying to shutdown the vehicle. The BATSW output can also be used to control an LS driver, such as the Relay 2 driver, by connecting the BATSW output to the RIN2 input. In certain packaged options of the 33813, the BATSW signal is not brought out to a pin. In this case, the BATSW signal can still be determined by the MCU by reading the state of BATSW bit in the SPI Status register. The MCU can then control the ROUT2 (Relay 2 output) by setting the “RIN2” bit in the SPI Control register. If the BATSW signal is not needed by the MCU or to control the Relay 2 output, it can also be configured as a low current LED high side driver controlled through the SPI interface. As a high side driver, BATSW can also be PWM’d to allow an LED to be dimmed. A bit in the SPI Battery Switch Logic Output Configuration register called “HSD”, controls whether the BATSW output will be a simple high side driver, or will be controlled by KEYSW as indicated above. If the BATSW output is used to control an LED, the LED cathode should be tied to ground and the LED anode should be connected to the BATSW pin through an external resistor. The value of the external resistor should be 340 ohms or greater. Care must be taken if the BATSW output is sent off-board due to the chance of shorts to the battery or shorts to ground, for which the output is not protected. At a minimum, this output should be protected by a diode, the current limit resistor, and an ESD capacitor (0.01 µF ceramic).

5.1.14 Using ROUT2 as a Power Relay

The ROUT2 (Relay 2 Output) can be used to drive a power relay. The RIN2 input or the RIN2 bit in the SPI Control register can be used to turn the ROUT2 output on or off as desired. The BATSW output can be connected to the RIN2 input to control the power relay, or the MCU can chose to control the RIN2 bit in the SPI Control register to actuate the power relay. The ROUT2 output is unique in that it can be kept turned on even after KEYSW is turned off (as long as the PWREN bit is still set to a one) by setting the shut down disable (SDD) bit in the ROUT2 Configuration register.

5.1.15 ISO9141 Transceive r (MTX, MRX, ISO9141)

the MCU. There is only one bit in the SPI Status register to indicate an over-temperature fault from the ISO9141 functional block. There are no Configuration or Control registers associated with this functional block.

5.1.16 Tachometer (TACHOUT)

1. Output the same signal as VRSOUT divided by a 1 to 32 programmable divider,
2. Output a PWM signal wit h a frequency and duty cycle programmable via the SPI, or
3. Output one of 8 fixed frequencies as indicated in Table 6.

device. The retry option works similarly to the other low side drivers. In the LSD mode bit 4 of the SPI Configuration register controls the turn on or turn off of the Open Load detect current sink. Table 6. TACHOUT SPI Configuration Register

01 Oscillator Output

10 Low Side Driver (LSD)

11 Same as 10 above

Table 7. TACHOUT SPI Configuration Register

5.1.17 INJIN1 Input

the SPI when either Injector driver is being used for purposes other than injector drive.

5.1.18 INJOUT1 Driver Outputs

output is forced off during all RESET events.

5.1.19 RIN1, RIN2 Inputs

for purposes other than relay drive.

5.1.20 ROUT1, ROUT2 Driver Outputs

words in the SPI Control register. The ROUT2 relay output can be configured in SPI to drive a power relay controlled by the BATSW signal.

5.1.21 LAMPOUT Driver Output

to prevent “ghosting”. The LAMPOUT SPI configuration register contains the following bits. Table 8. TACHOUT SPI Configuration Register

provided by the MCU on the input pin of the corresponding output driver.

5.1.22 VRSP, VRSN Inputs, VRSOUT Output

be divided and sent to the TACHOUT pin to drive a tachometer. Table 9. LAMPOUT SPI Configuration Register Table 10. PWM Duty Cycles

11 On ext pin : 100 Internal

Table 11. SPI VRS Manual Configuration Register

5.1.23 Controls for the VRSN and VRSP Inputs

5.0 kOhm directly across the pickup coil is also useful to minimize high frequency ringing.

5.1.24 GND VRSN Bit

this bit is zero (0) indicating that the differential mode is selected. zero (0), indicating that the internal 2.5 Volt reference voltage is connected to the VRSN and VRSP inputs.

5.1.26 Selecting the Input Th reshold and Blanking Time

register and the 33813 will use the values found in the SPI VRS configuration register.

5.1.27 Input Comparator Threshold Values

as described previously for the threshold D/A.

5.1.28 Blanking Time Definitions

The values for the one shot blanking, as a percentage of the last high output pulse period is shown in Table 12.

5.1.29 Manual and Automatic Modes

The SPI VRS miscellaneous configuration register has a bit to enable the automatic selection of the comparator threshold (bit 7). At this time, the operation of automatic mode remains TBD.

5.1.30 VRS Peak Detector

input pulses. Status bits reflect the last detected peak and only read 0000 after a POR or SPI reset command. Table 12. SPI VRS Manual Configuration Register

5.1.31 VRS Deglitching Filters

configuration register. This bit is, by default, zero (0), meaning that the deglitch filters are disabled.

5.1.32 High/Low Reference Bit

default for this bit is zero (0), indicating the use of a crankshaft wheel with a missing tooth (or teeth).

5.1.33 Disable VRS Bit

conditioning circuitry is active. Table 13. Peak Detector Output in SPI VRS Status Register

Analog Integrated Circuit Device Data Freescale Semiconductor 33 33813

5.1.34 Clamp Active Status Bits

There are two clamp active status bits in the SPI VRS status register. One is for the low pulse clamp and the other is for the high pulse clamp. When either of these bits are a one (1), it indicates that the peak voltage for that part of the input waveform has exceeded the clamp voltage and is being clamped to the high or low voltage limit. These status bits can be used to indicate that the engine has attained the speed necessary to switch from “cranking” values for the threshold and blanking (in the SPI VRS control register) to the “running” values. (in the SPI VRS configuration register).

5.1.35 Pre-driver Operation

There are three identical pre-drivers in the 33813. Each pre-driver can be configured as either an ignition (IGBT) pre-driver or a general purpose gate driver (GPGD). By default, one pre-driver is configured as a GPGD (O2HOUT) and two pre-drivers are configured as ignition (IGNOUT1) pre-drivers. A bit in each of the SPI Configuration registers, for each pre-driver, defines whether the pre-driver behaves as an ignition or a GPGD pre-driver. It should be noted that there are only two current measurement circuits, ISGNSENSP/N and O2SENSP/N. When both pre-drivers are used as GPGD, then IGNSENSP/N is associated with the IGNOUT1 pre-driver only, and the O2SENSP/N is associated with the O2OUT pre-driver.

5.1.36 O2HIN Input

The O2HIN pin is the parallel input that controls the O2HOUT pre-driver output. The O2HIN pin is a 5.0 V logic level input with a built-in pull-down to ground to prevent accidental actuation of the pre-driver output if the connection to the pin is lost. As a default, the O2HIN input is ORed with the O2HOUT control bit in the SPI ON/OFF control word. This is to allow the O2HOUT to be controlled by either the O2HIN (parallel input) or via the SPI.

5.1.37 O2HOUT Pre-driver Output with Drain Feedback Input O2HFB

The O2HOUT output is a pre-driver output that controls the gate of a MOSFET to drive a heater on an O2 (Lamda) sensor. The pre-driver is capable of driving most power MOSFETs. The O2HOUT output and associated drain feedback pin O2HFB provide short to battery, over-current protection for the external driver MOSFET. More accurate current control can be provided by placing a current sense resistor between the O2SENSP and O2SENSN pins. Output-off open circuit (OL) and output-on over-current (OC) faults are detected and annunciated via the SPI.

5.1.38 IGNIN1 Input

The IGNIN1 pin is the parallel inputs that control the IGNOUT1 pre-driver output. The IGNIN1 pin is a 5.0 V logic level input with a built-in pull-down to ground to prevent accidental actuation of a pre-driver output if the connection to the pin is lost. As a default, the IGNIN1 input is ORed with the IGNOUT1 control bit in the SPI ON/OFF control word. This is to allow the IGNOUT1 to be controlled by either the IGNIN1 (parallel input) or via the SPI.

5.1.39 IGNOUT1 Pre-driver Output, with Feedback IGNFB1 and Current

The IGNOUT1 output is a pre-driver output that drives an IGBT that controls the ignition coil current to produce a spark. The IGNOUT1 output and its feedback pins IGNFB1 provide short to battery and one shared current sense resistor provides over- current protection for the external driver transistors. When used as an IGBT driver, a 10:1 voltage divider (9R:1R) must be used on the feedback pins to prevent the 400 Volt flyback from damaging the IC. If two Ignition pre-drivers are not required, they can be reconfigured, via the SPI, as general purpose gate drivers (GPGDs) used to drive ordinary MOSFETs.

Analog Integrated Circuit Device Data Freescale Semiconductor 34 33813 More accurate current control can be provided by placing a current sense resistor between the IGNSENSP and IGNSENSN pins. When both pre-drivers are used as ignition (IGBT) pre-drivers, the both pre-drivers can share one current sense resistor. The input controls will determine the value of the current sense threshold voltage across the current sense resistor. When either one of the inputs is ON, the threshold voltage will be VSENS-TH, but when both inputs are ON simultaneously, the threshold will be raised to 2VSENS-TH to compensate for both pre-drivers being ON.

5.1.40 RESETB

The RESETB pin is a 5.0 volt logic, low level output that is used to reset the MCU. The RESETB pin is an open drain output. Without power on the 33813 circuit, the RESETB pin is held low by an internal pull-down resistor. In a typical application, the RESETB pin must be pulled up externally by a pull-up resistor to VCCWhen power is applied to the circuit and the voltage on the VCC pin reaches the lower voltage threshold, the RESETB pin will remain at a low level (open drain FET turned on) for a period of time equal to the time value WDRESET. After this time period, the RESETB pin will go high and stay high until a reset pulse is generated due to any of the following events: 1. A watchdog timer timeout event occurs, 2. An under-voltage event on VCC occurs, or 3. An over-voltage event on VPWR occurs. A Power On Reset (POR) is always provided upon power ON (i.e. anytime the IC goes from sleep state to active state).

5.1.41 Disabling the Watchdog Timer

Since a watchdog reset occurs, by default 10 seconds after the POR, if the MCU needs to programmed in-circuit, a means of disabling the watchdog must be provided to avoid interrupting the MCU programming procedure. This disable mechanism can be a jumper between the RESETB pin of the 33813 and the MCU’s Reset input pin, or via an isolation resistor placed between the RESETB pin on the 33813 and the MCU’s reset input pin that allows the MCU’s reset pin to be pulled high independently of the 33813 RESETB. The watchdog can also be disabled via a bit in the SPI WD configuration register.

5.1.42 Internal Reset

There is a bit in the SPI control register that is labelled “Reset”. When this bit is set to a one (1) by the MCU, it will instruct the 33813 to perform an internal reset. This reset will NOT toggle the RESETB output pin, but will cause all internal registers to be initialized back to their default values, including clearing the reset bit in the SPI control register.

5.2 MCU SPI Interface Description

The 33813 device directly interfaces to a 5.0 V micro controller unit (MCU) using a 16-bit serial peripheral interface (SPI) protocol. SPI serial clock frequencies up to 8.0 MHz may be used when programming and reading output status information (production tested at 1.0 MHz). Figure 16 illustrates the SPI configuration between an MCU and one 33813. Data is sent to the 33813 device through the SI input pin. As data is being clocked into the SI pin, other data is being clocked out of the device by the SO output pin. The response data received by the MCU during SPI communication depends on the previous SPI message sent to the device. The SPI can be used to read or write data to the configuration and control registers and to read or write the data contained in the status registers. The MCU is only allowed to read or clear bits (write zeros) in the status register unless the POST enable bit in the control register is set. When the POST enable bit is set the MCU can read and write zeros or ones to the status register. Note that the MCU must clear the POST enable bit before operation is resumed or the status register will not be updated with fault indications.

5.2.1 SPI Integrity Check

whenever any SPI message error is detected. Figure 16. SPI Interface with Microprocessor demonstrates the configuration. Figure 17. SPI Parallel Interface (Only) with Microprocessor

Analog Integrated Circuit Device Data Freescale Semiconductor 36 33813

5.3 Functional Device Operation

5.3.1 Power Supply

The 33813 is designed to operate from VPWRMIN to VPWRMAX on the VPWR pin. The VPWR pin supplies power to all internal regulators, and analog and logic circuit blocks.

5.3.1.1 V PP Pre-regulator

The VPP pre-regulator supplies the input voltage to the VCC and VPROT regulators. It uses an external PNP transistor as a pass element. This allows the user to choose the PNP’s size and package considerations to meet the system requirements. The amount of power that the external PNP transistor will have to dissipate depends on the maximum voltage the system can be expected to run at and the maximum expected current drawn from the VCC and VPROT regulators. The VPPSENS pin is used to feedback the value of the VPP voltage for regulation. Since the VPP regulator is not intended to supply off-the-board loads, there is no short to ground or short to battery protection on the output of the external PNP.

5.3.1.2 V CC Regulator

The VCC regulator output is used for supplying 5.0 Volts to the MCU, and for setting communication threshold levels via the internal SPI SO driver. The VCC regulator contains an internal pass transistor which is protected against over-current.

5.3.1.3 V PROT Regulator

The protected output VPROT is a tracking regulator uses the VCC output as a reference. Since it is expected that the VPROT regulator will supply 5.0 Volts to external sensors in the vehicle, it is well protected against shorts to battery, shorts to ground and over-current. The VPROT supply is enabled at power-on but can be disabled via the SPI control register.

5.3.2 Power ON Reset (POR)

Applying VPWR and bringing KEYSW high (VBAT) will generate a Power On Reset (POR) and place the device in the Normal operating state. The Power On Reset circuit incorporates a timer to prevent high frequency transients from causing an erroneous POR. Upon enabling the device (KEYSW High), outputs will be activated based on the initial state of the control register or parallel input. All three supplies, VPP, VCC, and VPROT, are enabled when KEYSW is brought high.

Figure 18. 33813 Functional State Diagram

5.3.3 SLEEP State

level to the KEYSW pin will force the device to exit the Sleep state and generate a POR. Table 14. Operational States

Analog Integrated Circuit Device Data Freescale Semiconductor 38 33813

5.3.4 NORMAL State

The default NORMAL state is entered when power is applied to the VPWR and the KEYSW pins. Note that the device is designed to have VPWR present before KEYSW is brought high. It is acceptable to bring VPWR and KEYSW high simultaneously, however it is not recommended to bring KEYSW high while VPWR is low. SPI register settings from Power-ON Reset (POR) are as follows:

• All outputs turned off.
• Off State open load detection enabled (LSD)
• Default values in the SPI Configurat ion, Control, and Status registers.

5.3.5 Power On Self-test (POST)

At power on, after a POR, it may be desired to go through an initial Power On Self-test routine to ensure that the SPI is working correctly and the status registers in the 33813 are viable. After a POR, all the registers in the 33813 contain their “default” values, as indicated in the SPI register tables later in this document. The watchdog is also set to its default timeout value of 10 seconds, so any POST routine must be accomplished within this time frame or a WD reset may occur. To perform a POST routine, the MCU should first send a SPI message to set the POST enable bit in the SPI control register 1, bit 6. Once this bit is set, the status registers are disconnected from the analog and logic portions of the 33813, and are connected only to the SPI circuitry. The POST can then write various data patterns to the status registers and verify that none of the bits are “stuck” or otherwise unworking. Note that bits in the status register labelled “x” are not implemented and when testing these bits may result in erroneous data. After testing all the status registers and confirming that they are viable, the status registers can be set back to their default values by clearing the POST Enable bit back to 0. The POST enable bit allows the MCU to write ones (1s) to the Status registers. Normally, the status register can only be cleared to zeros by the MCU and written ones by the 33813 internal logic. This was designed to prevent the MCU from missing any reported fault bits, and for the 33813, to prevent system status errors that could result from the MCU erroneously writing a one (1) to a fault bit. Once the POST enable bit is set back to a zero (0) by the MCU, the Status register returns to the condition where the 33813 can only write ones(1s) to it and the MCU can only write zeros (0s) to it. Again, it is important to note that any POST routine should be designed to take less than 10 seconds to avoid a watchdog reset from occurring and truncating the POST routine because the WD reset will clear the POST Enable bit as well. The 33813 IC has two modes of operation, Normal mode, and Sleep mode.

5.3.6 Watchdog (WD)

5.3.6.1 Watchdog Normal Operation

The watchdog is a programmable timer that is used to monitor the operation of the MCU. When the MCU is executing code properly, it’s program code should contain instructions to periodically send a SPI message to the watchdog SPI control register to refresh the watchdog. The watchdog timer, once refreshed, will reload the time interval value stored in the SPI watchdog configuration register and begin counting time again. Under normal operating conditions this sequence will continue until the MCU shuts down, typically, when the KEYSW is turned off.

5.3.6.2 Watchdog Fault Operation

In the event that something goes wrong during the MCU program execution, such as an unexpected breakpoint or other program hang-up such as the execution of a HALT instruction, the watchdog may not be refreshed. When the WD time interval value programmed in the SPI Configuration register elapses, the watchdog will issue a RESETB pulse. This RESETB pulse will cause the MCU to restart it’s program and correct operation should be restored. After any RESETB (power-on or other), the watchdog SPI configuration register will contain the default value for the refresh time, 10 seconds. The watchdog is also enabled by default. The MCU, in it’s initialization (start-up) code, can choose to change this default value and/or disable the watchdog by sending a SPI command to write new information in the watchdog SPI configuration register.

5.3.6.3 Watchdog SPI Configuration Register

There are seven bits in the watchdog SPI configuration register which define the time value that is loaded into the watchdog timer. may be set at one time. Setting more than one bit will result in the highest multiplier value getting precedence. Bit 7 is the watchdog enable(1) or disable(0) bit. 1.0 ms. to 10 seconds can be programmed into the watchdog.

5.3.6.4 Watchdog SPI Control Register

The watchdog relies on Bit 7 of the watchdog SPI control register being written as a one (1) to refresh the watchdog timer (i.e. a time value to temporarily set a different value in the watchdog timer for the next cycle. new temporary time value is again written to the watchdog SPI Control Register. Register to refresh the watchdog periodically (must be <200 ms). Table 15. Watchdog SPI Configuration Register Table 16. Watchdog SPI Control Register Table 17. Watchdog SPI Configuration Register Table 18. Watchdog SPI Control Register

5.3.7 Low Side Drivers (LSD)

5.3.7.1 LSD Input Logic Control

separate OR/AND select bit is found in the SPI configuration registers to accomplish this selection.

5.3.7.2 Pulse Width Modulation Mode

The external PWM duty cycles (D/C) are provided by the MCU on the input pin of the corresponding output driver.

5.3.7.3 LSD Output Protection

then automatically control the output to protect the output device from damage.

5.3.7.4 Over-current (OC) Protection

(OT) on the output device is reached. the over-current threshold is reached. The output will not turn on again until the output is commanded off and then on again. Table 19. External PWM Duty Cycles

from being set and the over-current protection from shutting off the output for tINRUSH time rather than tSC.

5.3.7.5 Temperature Limit (OT) Protection

state is commanding the output to be on. The TLIM hysteresis value is specified in the static parameter table. always enabled and is always a retry operation. rating of a single output driver.

5.3.7.6 Output Driver Diagnostics

for a single bit in one register to detect the presence of any fault in the circuit.

5.3.7.7 Open Load Pull-down Cu rrent Enable/Disable Bit

5.3.7.8 Open Load and Shor t to Battery Strategy

when the device is in the on state. The open load and short to battery fault threshold voltage is fixed and cannot be modified via the SPI.

5.3.7.9 Short to Ground Strategy

short to ground is detected it is annunciated via a bit in the appropriate SPI status register. Table 20. Inrush Delay Bit

Analog Integrated Circuit Device Data Freescale Semiconductor 42 33813

5.3.8 SPI REGISTER DEFINITIONS

There are three basic SPI register types: Configuration Registers - used to set the operating modes and parameters for the 33813 functional blocks. Each output can be configured by setting the individual bits in the configuration register for that output according to the descriptions in the previous functional descriptions for each particular output. Control Registers - used to turn outputs on and off and set the PWM duty cycle for outputs that are used as PWM outputs. Also used to set the temporary operating parameters for the watchdog timer and the VRS circuit. Status Registers - used to annunciate faults and other values that the MCU may need to act upon. Each output and functional block has a status register associated with it and the individual fault bits for each of the faults monitored are contained in these registers. An “Any Fault” bit, bit 7, is the OR of all the individual fault bits in the register and indicates that one or more of the fault bits is set. There is a system-wide “Any Fault” bit in the power supply and Any Fault Status register 13, (Bit 7) whose state is the OR of all the other “Any Fault” bits in the other status registers. The MCU can monitor this system-wide Any Fault bit to discover if any of the outputs has a fault condition present. Once the MCU detects the system-wide Any Fault bit =1, then it must interrogate the all the other Status registers to determine the actual fault(s) that are present. Once a fault bit in any status register is set, by the 33813 circuit, it can only be cleared by the MCU or by any of the reset actions including a software reset. Non-fault bits in the status register can be set and cleared by the 33813 circuit. All existing bits in the status register, bits not marked as “x” can only be cleared by the MCU when the POST bit is zero (0). When the POST bit is one (1), the MCU can read or write any existing bit in the status register. Non-existing bits, marked with an “x” in the table cannot be changed from the default zero (0) value.

5.3.8.1 Existing and Non-existi ng Bits in the SPI Registers

Entries in the following SPI registers marked with an “x” are non-existent bits. They are set to zero (0) by default and cannot be changed by reading or writing to them. They should be ignored when testing registers during POST. System On/Off Indicators One of the registers in the status register contains the On/Off status indication of the six LSDs and three pre-driver outputs (The TACHOUT output is the only output not annunciated in this register). The output is consider to be On (1) whenever all of the following conditions are true: 1. The output is commanded on via the Input pin or/and SPI bit, subject to the OR/AND logic condition selected. 2. There are no over-current (OC), short to battery (SB), or over-temperature (OT) faults present. 3. If PWM is enabled, the PWM control is set to a value greater than 0%. 4. There is no reset condition present. (OV, UV, WD, SW) 5. The 33813 is in the Normal state. (i.e. KEYSW =1) Note: For ROUT2, the 33813 can be in either the Normal state or the Pre-shutdown state if the shutdown disable (SDD) bit is set and PWREN=1. If all of the five conditions above are true, the System On/Off bit for that output will be on (1). If any of the five conditions above are false, the System On/Off bit for that output will be off (0).

5.3.8.2 Model Code and Revision Number

One status register is reserved for reporting the model code and revision of the 33813 circuits. The model code for the 33813 is 010. The revision code is the current version number for the circuit. This register is read-only.

5.3.9 SPI Command Summary

The SPI commands are defined as 16 bits with 4 address control bits and 12 command data bits. There are 7 separate commands that are used to set the operational parameters of device. The operational parameters are stored internally in 8-bit registers. Write commands write the data contained in the present SPI word whereas read commands have to wait until the next SPI command is sent to read the data requested.

any time while the device is in the Normal state. Messages sent are acted upon on the rising edge of the CSB input.

5.3.10 SPI Commands

• Do a SPI Check verification
• Read the contents of the SPI configuration registers
• Write the contents of the SPI configuration registers
• Read the contents of the SPI status registers
• Write the contents of t he SPI status registers
• Read the contents of the SPI control registers
• Write the contents of t he SPI control registers

5.3.10.1 SPI Registers

The SPI interface consists of a block of four 8-bit read/write registers.

• Configuration Registers - These registers allow the MCU to configure the various parameters and options for the various functional blocks.
• Control Registers - These registers are used to command the outputs on and off and set the PWM duty cycle values.
• Status Registers - These registers report back faults and other conditions of the various functional blocks. The following acronyms are use in the SPI table:
• OC = over-current, could be short to battery (SB)
• OV = over-voltage
• OT = over-temperature
• OL = open load
• SG = short to ground
• PWM = pulse width modulation

Table 21. SPI Command Messages

• DC = duty cycle The following conventions are used in the SPI register tables:
• All default selections are in BOLD fonts
• Non-default selections are in normal font
• The first selection listed is the default selection
• The binary values shown, (0 or 1) are the default values after a reset has occurred.

Table 22. SPI Configuration Registers

10 A Watchdog Parameters Enable/

11 B VRS Manual

12 C VRS Automatic

13 D VRS Miscellaneous

Table 23. SPI Control Registers

9 A Ignition 1 Pre-driver X PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0

10 B Not Used X X X X X X X X

121 C Watchdog WDRFSH Load

12 D VRS Conditioner Threshold

Table 24. SPI Status Registers

10 A Watchdog State Enable/

11 B VRS Conditioner

13 D Power Supply and

14 E System On/Off

15 F Model Code/ Revision

6 Typical Applications

6.0.1 Output OFF Open Load Fault

specific MOSFET output to an internally generated reference. Each output has one dedicated comparator for this purpose. respond with logic 0. The device will only shut down the pull-down current in Sleep mode or when disabled via the SPI. load fault, however, will be latched in the output SO response register for the MCU to read.

6.0.2 Low Voltage Operation

specification and status reported on SO pin is not guaranteed.

6.0.3 Low Side Injector Driver Voltage Clamp

current area under the current curve (IA) times the clamp voltage (VCL) (see Figure 19). Figure 19. Output Voltage Clamping

6.0.4 Reverse Battery Protection

The 33813 device requires external reverse battery protection on the VPWR pin. desired, a diode must be placed in series with the load.

50 V)Drain-to-Source Clamp

7 Packaging

7.1 Package Mechanical Dimensions

www.freescale.com and perform a keyword search for the drawing’s document number. Table 25. Mechanical Dimensions

Analog Integrated Circuit Device Data Freescale Semiconductor 50 33813 AE SUFFIX 48-PIN LQFP-EP 98ASA00173D ISSUE A Dimensions shown are provided for reference ONLY (For Layout and Design, refer to the Package Outline Drawing listed in the 98A Reference Documents table)

Analog Integrated Circuit Device Data Freescale Semiconductor 51 33813 AE SUFFIX 48-PIN LQFP-EP 98ASA00173D ISSUE A

Analog Integrated Circuit Device Data Freescale Semiconductor 52 33813 AE SUFFIX 48-PIN LQFP-EP 98ASA00173D ISSUE A

Analog Integrated Circuit Device Data Freescale Semiconductor 53 33813

8 Revision History

REVISION DATE DESCRIPTION OF CHANGES 1.0 8/2012 • Initial release

• Removed Freescale Confidential Proprietary on page 1

Document Number: MC33813 Rev. 1.0 Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits on the information in this document. Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: http://www.reg.net/v2/webservices/Freescale/Docs/TermsandConditions.htm Freescale, the Freescale logo, AltiVec, C-5, CodeTest, CodeWarrior, ColdFire, C-Ware, Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, Qorivva, StarCore, and Airfast, BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, MagniV, MXC, Platform in a Package, Processor expert, QorIQ Qonverge, QUICC Engine, Ready Play, SMARTMOS, TurboLink, Vybrid, and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2012 Freescale Semiconductor, Inc. How to Reach Us: Home Page: freescale.com Web Support: freescale.com/support