MC33772SM NXP | Alldatasheet
Document overview
- Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 10
Technical content
Features
- 5 . 0 V ≤ VPWR ≤ 30 V operation, 40 V transient
- 3 to 6 cells management
- Isolated 2.0 Mbps differential communication or 4.0 Mbps SPI
- Addressable on initialization
- Synchronized cell voltage/current measurement with Coulomb count
- Total stack voltage measurement
- Seven GPIO/temperature sensor inputs
- 5 . 0 V at 5.0 mA reference supply output
- Automatic over/undervolt age & temperature detection routable to fault pin
- Integrated Sleep mode over/undervoltage & temperature monitoring
- Onboard 300 mA passive cell balancing with diagnostics
- Hot plug capable
- Detection of internal and external faults, as open lines, shorts, and leakages
- Single chip ASIL C capable
- Fully compatible with the MC33771 for max 14 cells
Figure 1. Simplified application diagram of SPI communication context
Applications
- Automotive: 12 V and high-voltage battery packs
- E-bikes, e-scooters
- Energy storage systems
- Uninterruptible power supply (UPS) AE SUFFIX (PB-FREE) 98ASA00173D 48-PIN LQFP-EP Battery Reference VCOM Battery Reference
6 Cell
CB6:5_C CT1 MC33772 RDTX _OUT+ RDTX_OUT- VCOM SDA GPIO1 VPWR2 CT5 CTREF CB1 CB2:1_C CGND VANA AGND FAULT DGND SDL SO CSB SPI_COM_EN RESET SI/RDTX _IN+ SCLK/RDTX _IN- GPIO2 GPIO3 GPIO4 GPIO0 GPIO5 GPIO6 ISENSE+ ISENSE- GNDSUB GNDFLG CTn CBn MCU GPIOx CSB MISO MOSI SCLK VPRE VPRE GNDCP VCP
2 NXP Semiconductors
Figure 2. Simplified application diagram of twisted pair line communication with isolation transformers
Figure 3. Simplified internal block diagram Table 1. Orderable part variations
- To order parts in Tape & Reel, add the R2 suffix to the part number.
4 NXP Semiconductors
Figure 4. 33772 pinout diagram Table 2. 33772 pin definitions
35 RDTX_OUT+ Receive/transmit output positive 44 ISENSE- Current measurement input–
36 AN0/GPIO0 General purpose analog input or GPIO 45 AGND Analog ground, terminate to GNDSUB
37 AN1/GPIO1 General purpose analog input or GPIO 46 DGND Digital ground, terminate to GNDSUB
39 AN3/GPIO3 General purpose analog input or GPIO 48 GNDSUB
41 AN5/GPIO5 General purpose analog input or GPIO
Table 3. Key parameters GND = 0 V, unless otherwise stated. Typical values refer to VPWR = 24 V, TA = 25 °C, unless otherwise noted. Before starting any development, it is recommended to request a copy of the full 33772 data sheet.
- Normal mode, Cell Balance OFF, ADC Inactive, Communication Inactive, IVCOM = 0 mA 5.8 mA IVPWR(CBON) Supply Current adder to set all 6 Cell Balance switches ON 0.97 mA IVPWR(ADC) Delta Supply Current to perform ADC conversions (addend)
- ADC1-A,B continuously converting
- ADC2 continuously converting 2.9 1.17 mA IVPWR(SS) Supply Current in Sleep mode, Communication Inactive, Cell Balance OFF, Oscillator Monitor ON
- SPI mode
- TPL mode μA tVPWR(FILTER) VPWR OV, LV, UV Filter 50 μs VPRE power supply VVPRE(UV_TH) Undervoltage Threshold for VCP minus VPRE 4.25 V VCP power supply VCP(UV_TH) Undervoltage Threshold for VCP minus VPRE 1.5 V VCOM power supply VCOM VCOM Output Voltage 5.0 V VCOM(UV) VCOM Undervoltage Fault Threshold 4.5 V VCOM_HYS VCOM Undervoltage Hysteresis 100 mV VDDIO power supply tVCOM(FLT_TIMER) VCOM Undervoltage Fault Timer 10 μs tVCOM(RETRY) VCOM Fault Retry Timer 10 ms RVCOM(SS) VCOM Sleep Mode Pull-down Resistor 2.0 k Ω
Table 2. 33772 pin definitions (continued)
6 NXP Semiconductors
- Decouple with 47 nF X7R 0603 or 0402 2.65 V VANA(UV) VANA Undervoltage Fault Threshold 2.4 V VANA_HYS VANA Undervoltage Hysteresis 50 mV tVANA(FLT_TIMER) VANA Undervoltage Fault Timer 11 μs VANA (OV) VANA Overvoltage Fault Threshold 2.8 V tVANA(RETRY) VANA Fault Retry Timer 10 ms RVANA_RPD VANA Sleep Mode Pull-down Resistor 1.0 k Ω ADC1-A, ADC1-B CTn(LEAKAGE) Cell Terminal Input Leakage Current 10 nA CTn(FV) Cell Terminal Input Current - Functional Verification 1.0 mA CTN Cell Terminal Input Current During Conversion 100 nA RPD Cell Terminal Open Load Detection Pull-down Resistor 950 Ω VVPWR_RES VPWR Terminal Measurement Resolution 2.4415 mV/LSB VCT_ANx_RES Cell Voltage and ANx Resolution in 15-bits MEAS_xxxx registers 152.5925 μV/LSB tVCONV Single Channel Net Conversion Time
- 16-Bit Resolution 25.36 μs VV_NOISE • 16-Bit Resolution 400 μVrms ADC2/current sense module IISENSE_OL ISENSE Open Load injected current 130 μA VISENSE_OL ISENSE Open Load detection threshold 460 mV V2RES ADC Resolution 0.6 μV/LSB VPGA_SAT PGA saturation half-range
- Gain = 256
- Gain = 64
- Gain = 16
- Gain = 4 4.9 19.5 78.1 150.0 mV V PGA_ITH Voltage threshold for PGA gain increase
- Gain = 256
- Gain = 64
- Gain = 16
- Gain = 4 2.344 9.375 37.50 mV VPGA_DTH Voltage threshold for PGA gain decrease
- Gain = 256
- Gain = 64
- Gain = 16
- Gain = 4 4.298 17.188 68.750 mV tPGA_SETTLE PGA settling time after a chopper event 14.0 μs tICONV ADC Conversion Time including PGA settling time
- 16-Bit Resolution 37.67 μs VI_NOISE Noise at 16-bit Conversion 3.01 μVrms
Table 3. Key parameters (continued) GND = 0 V, unless otherwise stated. Typical values refer to VPWR = 24 V, TA = 25 °C, unless otherwise noted. Before starting any development, it is recommended to request a copy of the full 33772 data sheet.
- Clamp Energy tbd 11 V VOUT(FLT_TH) Output Fault Detection Voltage Threshold
- Balance OFF (Open Load)
- Balance ON (Shorted Load) 0.55 V RPD_CB Output OFF Open Load Detection Pull-down Resistor
- Balance OFF, Open Load Detect Disabled 2.0 k Ω RDS(on) Drain-to-Source ON Resistance
- I OUT = 300 mA, TJ = 105 °C
- I OUT = 300 mA, TJ = 25 °C
- I OUT = 300 mA, TJ = -40 °C 0.5 0.4 Ω tON Cell Balance Driver Turn On
- R L = 15 Ω 350 μs tOFF Cell Balance Driver Turn Off
- R L = 15 Ω 200 μs tBAL_DEGLICTH Short/Open Detect Filter Time 20 μs Internal temperature measurement IC_TEMP1_RES IC Temperature Resolution 0.032 K/LSB TSD_TH Thermal Shutdown 170 °C TSD_HYS Thermal Shutdown Hysteresis 10 °C General purpose input/output GPIOx VOL(TH) Analog Input Open Pin Detect Threshold 0.15 V ROPENPU Internal Open detection Pull-down Resistor 5.0 k Ω GPIO0 WU De-glitch Filter 50 μs GPIO0 Daisy Chain De-glitch Filter both edges 20 μs GPIO2 Convert Trigger De-glitch Filter 2.0 μs Reset input tRESETFLT RESET De-glitch Filter 100 μs RRESET_PD Input Logic Pull-down (RESET) 100 k Ω SPI_COM_EN input VHYS Input Hysteresis 125 mV RSPI_COM_EN_PD Input Pull-down Resistor (SPI_COM_EN) 100 k Ω Bus switch for TPL communication RXTERM Bus Termination Resistor (open resistor when bus switch is closed) 300 Ω Remark: if the bus switch is closed, the termination resistor is open, else the termination resistor is connected. At the end of the daisy chain the switch must be open, so the transmission line is properly terminated.
GND = 0 V, unless otherwise stated. Typical values refer to VPWR = 24 V, TA = 25 °C, unless otherwise noted. Before starting any development, it is recommended to request a copy of the full 33772 data sheet.
8 NXP Semiconductors
- SI/RDTX_IN+, SCLK/RDTX_IN-, CSB, SDA, SCL 80 mV RSCLK_PD Input Logic Pull-down Resistance (SCLK/RDTX_IN-, SI/RDTX+) 20 k Ω R_PU Input Logic Pull-up Resistance to VCOM (CSB, SDA, SCL) 100 k Ω CSBWU_FLT CSB Wake-up De-glitch Filter, Low to High Transition 50 μs System timing tCELL_CONV Time needed to acquire all 6 cell voltages and the current after an on demand conversion
- 16-Bit Resolution 208 μs tSYNC V/I time synchronization
- ADC1-A,B at 16-Bit, ADC2 at 16-Bit 113 μs tWAKE_DELAY Time between wake pulses 600 μs tIDLE Idle time out after POR 60 s tWAKE_INIT Wake-up signaling time out after POR 0.75 s tDIAG Diagnostic Mode Time-out 1.0 s tEOC SOC to Data Ready (includes post processing of data)
- 16-Bit Resolution 520 μs tSETTLE Time after SOC to begin converting with ADC1-A,b 12.28 μs tCLST_TPL Time needed to send a SOC command and read back 6 cell voltages, 7 temperatures, 1 current, 1 Coulomb counter with TPL communication working at 2.0 Mbps and ADC1-A,B configured as follows:
- 16-Bit Resolution 1.16 ms tCLST_SPI Time needed to send a SOC command and read back 6 cell voltages, 7 temperatures, 1 current, 1 Coulomb counter with SPI communication working at 4.0 Mbps and ADC1-A,B configured as follows:
- 16-Bit Resolution 0.86 ms tI2C_ACCESS EEPROM Access Time, EEPROM Write (depends on device selection) 5.0 ms tWAVE_DC_BITx Daisy Chain Duty Cycle OFF Time
- t WAVE_DC_BITx = 00 500 μs tWAVE_DC_BITx Daisy Chain Duty Cycle OFF Time
- t WAVE_DC_BITx = 01 1.0 ms tWAVE_DC_BITx Daisy Chain Duty Cycle OFF Time
- t WAVE_DC_BITx = 10 10 ms tWAVE_DC_BITx Daisy Chain Duty Cycle OFF Time
- t WAVE_DC_BITx = 11 100 ms tWAVE_DC_ON Daisy Chain Duty Cycle ON Time 500 μs tSLEEP Time out to enter Sleep Mode in the absence of TPL communication 1024 ms
GND = 0 V, unless otherwise stated. Typical values refer to VPWR = 24 V, TA = 25 °C, unless otherwise noted. Before starting any development, it is recommended to request a copy of the full 33772 data sheet.
- Driver tri-state 2.5 V Revision Date Description of changes 2.0 8/2016 • Added revision history table.
GND = 0 V, unless otherwise stated. Typical values refer to VPWR = 24 V, TA = 25 °C, unless otherwise noted. Before starting any development, it is recommended to request a copy of the full 33772 data sheet.
Information in this document is provided solely to enable system and software implementers to use NXP products. There are no expressed or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. NXP reserves the right to make changes without further notice to any products herein. NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation, consequential or incidental damages. "Typical" parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each customer application by the customer's technical experts. NXP does not convey any license under its patent rights nor the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the following address: http://www.nxp.com/terms-of-use.html. How to Reach Us: Home Page: NXP.com Web Support: http://www.nxp.com/support NXP , the NXP logo, Freescale, the Freescale logo and SMARTMOS are trademarks of NXP B.V. All other product or service names are the property of their respective owners. All rights reserved. © 2016 NXP B.V. Document Number: MC33772SM Rev. 2.0