33710 FREESCALE | Alldatasheet
Document overview
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- PDF pages: 17
Technical content
Features
- Efficient 5.0 V / 3.3 V Buck Regulator
- Low Noise LDO Regulator (mode-selected 3.3V, 2.5V,1.8V, or 1.5V)
- On-Chip Thermal Shutdown Circuitry
- Supervisory Functions (Power-ON Reset and Error Reset Circuitry)
- Sequenced I/O and Core Voltages
- Pb-Free Packaging Designated by Suffix Code EW
Figure 1. 34710 Simplified Application Diagram
ORDERING INFORMATION
Range (TA) Package *PC33710EW / R2 -40°C to 105° 32 SOICW-EP MC34710EW/R2 0°C to 85°C 32 SOICW-EP 34710 *Device in development. Electrical parameters being defined. MCU 34710 VSWITCH VFB LINB+ VCORE VB RST GND CP1 MODE0 MODE1 MODE2 CP2
13 V to 32 V
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Figure 2. 34710 Simplified Internal Block Diagram
Figure 3. 34710 Terminal Connections Table 1. 34710 Terminal Definitions 1 RST Reset Reset Reset is an open drain output only. Input Mode Control These input terminals control VFB and VCORE output voltages. NC NC No Connects No internal connection to this terminal. 13 GND Ground Ground Ground.
23 VCORE Output Core Voltage
Core regulator output voltage.
25 LINB+ Input Core Voltage
Core regulator input voltage.
26 VFB Input VI/O Switching
Feedback terminal for VI/O switching regulator and internal logic supply.
27 VSWITCH Output VI/O Switching
VI/O switching regulator switching output.
28 B+ Input Power Supply
29 VB Output Boost Voltage Boost voltage storage node.
30 CP2 Passive
Charge pump capacitor connection 2.
31 CP1 Passive
Charge pump capacitor connection 1.
32 CT Passive
Reset delay adjustment capacitor.
Analog Integrated Circuit Device Data
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All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Rating Symbol Max Unit ELECTRICAL RATINGS Input Power Supply Voltage IB+ = 0.0 A VB+ -0.3 to 36 V Terminal Soldering Temperature (1) TSOLDER 260 °C Power Dissipation (2) PD 3.0 W ESD Standoff Voltage Non-Operating, Unbiased, Human Body Model (3) VESD1 ±2000 V Thermal Resistance Junction-to-Ambient (4) Junction-to-Ambient (2) Junction-to-Exposed-Pad RθJA RθJA RθJC 2.0 °C/W THERMAL RATINGS Operating Ambient Temperature TA 0 to 85 °C Operating Junction Temperature TJ 0 to 105 °C Input Power Supply Voltage IB+ = 0.0 A to 3.0 A VB+ 13 to 32 V Quiescent Bias Current from B+ (5) VB+ = 13 V to 32 V IB+(Q) 7.5 mA VI /O SWITCHING REGULATOR (6) Maximum Output Voltage Startup Overshoot (COUT = 330 µF) Mode0 = 0 Mode0 = Open VI / O(STARTUP) 5.4 3.6 V Maximum Output Current TA = 0°C to 105°C IVI/O 700 mA Notes 1. Soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 2. With 2.0 in 2 of copper heatsink. 3. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω). 4. With no additional heatsinking. 5. Maximum quiescent power dissipation is 0.25 W. 6. 13 V ≤ VB+ ≤ 32 V and - 20°C ≤ TJ ≤ 145°C unless otherwise noted.
Analog Integrated Circuit Device Data Freescale Semiconductor 5 34710 MAXIMUM RATINGS VCORE LINEAR REGULATOR (7) Maximum Output Voltage Startup Overshoot (COUT = 10 µF) (8) Mode2=Low, Mode1=Low, Mode0=Low Mode2=Open, Mode1=Low, Mode0=Don’t Care Mode2=Low, Mode1=Open, Mode0=Don’t Care Mode2=Open, Mode1=Open, Mode0=Don’t Care VCORE (STARTUP) 3.6 2.7 2.0 1.65 V Maximum Output Current TJ = 0°C to 105°C, VLINB+ ≤ VCORE (NOM) + 0.8 V (9) IVCORE 500 mA Notes 7. 13 V ≤ VB+ ≤ 32 V and - 20°C ≤ TJ ≤ 145°C unless otherwise noted. 8. Refer to Table 2, page 9. 9. Pulse testing with low duty cycle used. MAXIMUM RATINGS (continued) All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Rating Symbol Max Unit
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STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 4.75 V ≤ VIO ≤ 5.25 V, 13 V ≤ VB+ ≤ 32 V, and 0°C ≤ TJ ≤ 105°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit SWITCHING REGULATOR (VI/O, MODE0) Logic Supply Voltage (IVI/O = 25 to 700 mA) Mode0 = 0 Mode0 = Open (floating) VI / O 4.8 3.15 5.0 3.25 5.2 3.45 V Output On Resistance VB+ = 13 V to 32 V RDS(ON) 0.5 1.0 2.0 Ω Soft Start Threshold Voltage Mode0 = any VI / O(SOFT) – 2.5 3.1 V Current Limit Threshold (TJ = 25°C to 100°C) Normal Operation Soft Start, V I / O ≤ 2.5 V ILIMIT (OP) ILIMIT (SOFT) 1.9 1.0 2.4 2.9 1.9 A Minimum Voltage Allowable on VSWITCH Terminal TJ = 25°C to 100°C VVSWITCH (MIN) -0.5 – – V LINEAR REGULATOR (VCORE, MODE 1, 2, 3, 4) Supply Voltage (IVCORE = 5.0 mA) (10) Mode2=Low, Mode1=Don’t Care, Mode0=Low Mode2=Low, Mode1=Don’t Care, Mode0=Open Mode2=Open, Mode1=Don’t Care, Mode0=Low Mode2=Open, Mode1=Don’t Care, Mode0=Open VCORE (NOM) 3.15 2.45 1.7 1.425 3.3 2.5 1.8 1.5 3.45 2.75 2.05 1.575 V Supply Voltage (I VCORE = 500 mA) (10) Mode2=Low, Mode1=Don’t Care, Mode0=Low Mode2=Low, Mode1=Don’t Care, Mode0=Open Mode2=Open, Mode1=Don’t Care, Mode0=Low Mode2=Open, Mode1=Don’t Care, Mode0=Open VCORE (NOM) 3.0 2.2 1.55 1.33 3.4 2.6 1.9 1.53 V VCORE Dropout Voltage VCORE = VCORE (NOM), IVCORE = 0.5 A IVCORE(DROPOUT) – 0.5 0.8 V Normal Current Limit Threshold TJ = 25°C to 100°C, VLINB+ = VCORE (NOM) + 1.0 V ILIMIT 600 800 1000 mA Notes 10. Refer to Table 2, page 9.
Analog Integrated Circuit Device Data Freescale Semiconductor 7 34710 STATIC ELECTRICAL CHARACTERISTICS MODE TERMINALS OPERATING VOLTAGES Mode Control Terminals Low Voltage VIL(Moden) – – 0.825 V Mode Control Terminals High Voltage VIH (Moden) 2.6 – – V Mode Control Terminals Voltage with Input Floating VB+ = 13 V to 14 V VMode(FLOAT) 7.0 8.0 13 V SUPERVISOR CIRCUITRY (RST, VCORE) Minimum Function VB+ for Charge Pump and Oscillator Running VB+ (MIN) – – 9.0 V Minimum VB+ for RST Assertion, VB+ Rising VB+(ASSERT) – 1.9 2.2 V RST Low Voltage VB+ = 2.0 V, IRST ≤ 5.0 mA VOL – 0.25 0.4 V RST VI / O Threshold VI / O Rising VI / O Falling VI / OT+ VI / OT- VI/O (NOM) - 300 mV VI/O(NOM) - 50 mV V RST Hysteresis for VI / O VHYSVI/O 10 – 100 mV RST VCORE Threshold VCORE Rising VCORE Falling VCORET+ VCORET- VCORE (NOM) - 300 mV VCORE (NOM) - 30 mV V RST Hysteresis for VCORE VB+ = 13 V to 32 V VHYS CORE 10 50 100 mV VCORE - VI / O for VCORE Shutdown VB+ = 13 V to 32 V VCORE (SHUTDOWN) 0.5 – 0.9 V Thermal Shutdown Temperature TJ Rising TJ (TSD) – – 170 Overtemperature Hysteresis TJ (HYSTERESIS) – 20 – °C VB CHARGE PUMP Boost Voltage (11) VB+ = 12 V, Ivb = 0.5 mA VB+ = 32 V, Ivb = 0.5 mA VB VB VB+ 8 VB+ 10 VB+ 9 VB+ 12 VB+ 10 VB+ 14 V Notes 11. Bulk capacitor ESR ≤ 10 milliohms STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 4.75 V ≤ VIO ≤ 5.25 V, 13 V ≤ VB+ ≤ 32 V, and 0°C ≤ TJ ≤ 105°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted. Characteristic Symbol Min Typ Max Unit
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DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 4.75 V ≤ VIO ≤ 5.25 V, 13 V ≤ VB+ ≤ 32 V, and 0°C ≤ TJ ≤ 105°C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted Characteristic Symbol Min Typ Max Unit VI /O SWITCHING REGULATOR Duty Cycle D 45 49 55 % Switching Rise and Fall Time Load Resistance = 100 Ω, VB+ = 30 V tR , tF 20 35 50 ns SUPERVISOR CIRCUITRY (RST) RST Delay Cdelay = 0.1 µF t DELAY 40 60 80 ms RST Filter Time VB+ = 9.0 V t FILTER 2.0 4.0 8.0 µs RST Fall Time CL = 100 pF, RPULLUP = 4.7 kΩ, 90% to 10% t F – 25 75 ns C Delay Charge Current Threshold Voltage ICDLY VTHCD 2.0 1.7 3.5 2.0 5.0 2.2 µA V INTERNAL OSCILLATOR Charge Pump and VI / O Switching Regulator Operating Frequency VB+ = 12 V to 32 V f OP 140 170 260 kHz
operating from the internal ~200 kHz oscillator. general chip bias circuitry. by the VI/O regulator output or from an independent supply. Terminals for the Charge Pump capacitor. and requires an external pull-up resistor. prevent RST oscillations during chip power-on. Regulator and the output of the regulator application. Regulator. It has internal high side FET. Table 2. VI /O and VCORE Regulator Open indicates terminal is not connected externally (i.e. floating).
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FUNCTIONAL TERMINAL DESCRIPTION SUPERVISORY FUNCTIONS Supervisory Circuitry The supervisory circuitry provides control of the RST line, an open drain signal, based on system operating conditions monitored by the 34710. VI /O, VCORE, VB+, and thermal shutdown (TSD) detectors in various parts of the chip are monitored for error conditions. VI /O, VCORE, VB+, and thermal shutdown have both positive- and negative-going thresholds for triggering the reset function. The supervisor circuitry also ensures that the regulator outputs follow a predetermined power-up and power-down sequence. Specifically, the sequencing ensures that V I /O is never less than 0.9 V below VCORE. This means that VCORE - VI /O will be clamped at 0.5 V, and that the VCORE regulator operation will be suppressed during startup and shutdown to ensure that V CORE - VI /O = 0.9 V. VB Charge Pump The high-side MOSFET in the switching regulator (buck converter) requires a gate drive supply voltage that is biased higher than the B+ voltage, and this boosted voltage is provided by the internal charge pump and stored in a capacitor between the VB pin and the B+ pin. The charge pump operates directly from the B+ supply, and uses an internal oscillator operating at 200 kHz. Internal Oscillator The internal oscillator provides a 200 kHz square wave signal for charge pump operation and for the buck converter.
Figure 4. Typical Application Diagram
2.5 V, then no series resistance would be required, even at
the maximum output current of 500 mA.
13 V - 32 V
1 K C1
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di/dt switching transients from causing EMI/RFI. Figure 5. Typical PCB Layout power inductor, rectifier, and filter components. Figure 6. Bottom Copper Layout an immediate path to ground from the top copper circuitry. Figure 7. Top Copper Layout with the component placement. potential for coupling noise transients into adjacent circuitry. Figure 8. Output Plane of Buck Converter
Analog Integrated Circuit Device Data Freescale Semiconductor 13 34710 TYPICAL APPLICATIONS This layout provides the lowest possible impedance as well as lowest possible dc resistance for the power routing. Note that the power path and its return should be placed, if possible, on top of each other on different layers or opposite sides of the pcb. Small ceramic capacitors are placed in parallel with the Aluminum electrolytics so that the overall bulk filtering presents a low ESL to the high di/dt switching currents. Alternatively, special low ESL/ESR switching-grade electrolytics may be used. An additional feature of the MC34710 is the 32 SOICW-EP exposed pad package. The package allows heat to be conducted from the die down through the exposed metal pad underneath the package and into the copper of the pcb. In order to best take advantage of this feature, a grid array of thru-hole vias should be placed in the area corresponding to the exposed pad, and these vias then should then connect to a large ground plane of copper to dissipate the heat into the ambient environment. An example of these vias can be seen in the previous figures of a typical pcb layout.
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EW (Pb-FREE) SUFFIX 32-LEAD SOICW-EXPOSED PAD PLASTIC PACKAGE 98ASA10627D ISSUE O
Analog Integrated Circuit Device Data Freescale Semiconductor 15 34710 PACKAGING PACKAGE DIMENSIONS EW (Pb-FREE) SUFFIX 32-LEAD SOICW-EXPOSED PAD PLASTIC PACKAGE 98ASA10627D ISSUE O
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REVISION HISTORY
REVISION DATE DESCRIPTION OF CHANGES 2.0 3/2006 • Converted to Freescale format
- Updated Maximum Ratings, Static and Dynamic Characteristics tables.
- Updated packaging drawing
- Changed terminal VI/O_OUT to VFB
- Implemented Revision History page 3.0 3/2006 • Updated format from Preliminary to Advance Information.
- Format and style corrections to match standard template.
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