33702 MOTOROLA | Alldatasheet

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Technical content

Features

  • Operating Voltage: 2.8 V to 6.0 V
  • High-Accuracy Output Voltages
  • Fast Transient Response
  • Switcher Output Current Up to 3.0 A
  • Undervoltage Lockout
  • Power Sequencing
  • Programmable Watchdog Timer
  • Voltage Margining via I 2C™ Bus
  • Overcurrent Protection
  • Reset with Programmable Power-ON Delay
  • Enable Inputs I2C is a trademark of Phillips Corporation. POWER SUPPLY INTEGRATED CIRCUIT Oth er Circuits ADDR LDRV LDO LFB CS RT RES ET VDDH (I/Os) VDDL (Core)SW MPC85xx PGND IN V EN1 MC3 3703 2.8 V to 1 3. 5 V In put VIN2 VBST VBD CLKSYN CLKSEL FREQ Optional PORESET 0 . 8t o5 . 0V 0.8 to 5.0 V (Adjustable) (Adjustable) VIN1 EN2 GND BOOT SDA SCL VOUT VBST SR 33702 VIN2 VIN1 VBD VBST VOUT VLDO = VOUT = MPC8XXX 2.8 V to 6.0 V DWB SUFFIX CASE 1324-02 32-LEAD SOICW Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

33702 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

Figure 1. 33702 Simplified Block Diagram Freescale Semiconductor, Inc.

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33702 PIN FUNCTION DESCRIPTION Pin Pin Name Formal Name Definition 1 FREQ Oscillator Frequency This selection switcher pin can be adjusted by connecting external resistor RF to the FREQ pin. The default switching frequency (FREQ pin left open or tied to VDDI) is set to 300 kHz. 2 INV Inverting Input Buck Controller Error Amplifier inverting input. 3 VOUT Output Voltage Output voltage of the buck converter. Input pin of the switching regulator power sequence control circuit. 4, 5 VIN2 Input Voltage 2 Buck regulator power input. Drain of the high-side power MOSFET. 6, 7 SW Switch Buck regulator switching node. This pin is connected to the inductor. 8, 9 24, 25 GND Ground Analog ground of the IC, thermal heatsinking. 10, 11 PGND Power Ground Buck regulator power ground. 12 VBD Boost Drain Drain of the internal boost regulator power MOSFET. 13 VBST Boost Voltage Internal boost regulator output voltage. The internal boost regulator provides a 20 mA output current to supply the drive circuits for the integrated power MOSFETs and the external N-channel power MOSFET of the linear regulator. The voltage at the VBST pin is 8.0 V nominal. 14 BOOT Bootstrap Bootstrap capacitor input. 15 SDA Serial Data I2C bus pin. Serial data. 16 SCL Serial Clock I2C bus pin. Serial clock. 17 LCMP Linear Compensation Linear regulator compensation pin. 18 LFB Linear Feedback Linear regulator feedback pin. 19 LDO Linear Regulator Input pin of the linear regulator power sequence control circuit. 20 CS Current Sense Current sense pin of the LDO. Overcurrent protection of the linear regulator external power MOSFET. The voltage drop over the LDO current sense resistor RS is sensed between the CS and LDO pins. The LDO current limit can be adjusted by selecting the proper value of the current sensing resistor RS. 21 LDRV Linear Drive LDO gate drive of the external pass N-channel MOSFET. 22 VIN1 Input Voltage 1 The input supply pin for the integrated circuit. The internal circuits of the IC are supplied through this pin. CLKSYN1 EN2 EN1 ADDR GND GND VDD1 VIN1 LDRV CS LFB LCMP LDO RT CLKSEL RESET FREQ VIN2 SW SW GND GND PGND PGND VBD VBST SDA SCL BOOT VIN2 INV VOUT Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

23 VDDI Power Supply Internal supply voltage. 26 ADDR Address I2C address selection. This pin can be either left open, tied to VDDI, or grounded through a 10 kΩ resistor. 27 EN1 Enable 1 Enable 1 Input. The combination of the logic state of the Enable 1 and Enable 2 inputs determine operation mode and type of power sequencing of the IC. 28 EN2 Enable 2 Enable 2 Input. The combination of the logic state of the Enable 1 and Enable 2 inputs determine operation mode and type of power sequencing of the IC.

29 RT Reset Timer This pin allows programming the Power-ON Reset delay by means of an external RC

network. 30 RESET Reset Overbar The Reset Control circuit monitors both the switching regulator and the LDO feedback voltages. It is an open drain output and has to be pulled up to some supply voltage (e.g., the output of the LDO) by an external resistor. 31 CLKSEL Clock Selection This pin sets the CLKSYN pin either as an oscillator output or synchronization input pin. The CLKSEL pin is also used for the I2C address selection. 32 CLKSYN Clock Synchronization Oscillator output/synchronization input pin. PIN FUNCTION DESCRIPTION (continued) Pin Pin Name Formal Name Definition Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33702 MAXIMUM RATINGS All voltages are with respect to ground unless otherwise noted. Rating Symbol Value Unit Supply Voltage V IN1, VIN2 -0.3 to 7.0 V Switching Node SW -1.0 to 7.0 V Buck Regulator Bootstrap Input (BOOT - SW) BOOT -0.3 to 8.5 V Boost Regulator Output V BST -0.3 to 8.5 V Boost Regulator Drain V BD -0.3 to 9.5 V RESET Drain Voltage RESET -0.3 to 7.0 V Enable Pins (EN1, EN2) – -0.3 to 7.0 V Logic Pins (SDA, SCL, CLKSYN) – -0.3 to 7.0 V Analog Pins (INV, VOUT, RESET) – -0.3 to 7.0 V Analog Pins (LDRV, LFB, LDO, LCMP, CS) – -0.3 to 8.5 V Analog Pins (CLKSEL, ADDR, RT, FREQ, VDDI) – -0.3 to 3.6 V ESD Voltage Human Body Model (Note 1) Machine Model (Note 2) VESD1 VESD2 ±2000 ±200 V Storage Temperature T STG -65 to 150 °C Power Dissipation (TA = 85°C) (Note 3) PD TBD W Lead Soldering Temperature (Note 4) T SOLDER 260 °C Maximum Junction Temperature T JMAX 125 °C Thermal Resistance, Junction to Ambient (Note 5) RθJA 68 °C/W Thermal Resistance, Junction to Base (Note 6) RθJB 18 °C/W OPERATING CONDITIONS Supply Voltage (VIN1, VIN2)V IN1, VIN2 2.8 to 6.0 V Operational Package Temperature (Ambient Temperature) T A -40 to 85 °C Notes 1. ESD1 testing is performed in accordance with the Human Body Model (C ZAP=100 pF, RZAP=1500 Ω). 2. ESD2 testing is performed in ac cordance with the Machine Model (CZAP=200 pF, RZAP=0 Ω). 3. Maximum power dissipation at indicated junction temperature. 4. Lead soldering temperature limit is for 10 seconds maximum durati on. Contact Motorola Sales Office for device immersion soldering time/ temperature limits. 5. Thermal resistance measured in accordance with EIA/JESD51-2. 6. Theoretical thermal resistance from the die junction to the exposed pins. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions -40°C ≤ TJ ≤ 125°C unless otherwise noted. Input voltages VIN1 = VIN2 = 3.3 V using the typical application circuit (see Figure 20) unless otherwise noted. Characteristic Symbol Min Typ Max Unit GENERAL Operating Voltage Range (VIN1, VIN2) VIN 2.8 – 6.0 V Start-Up Voltage Threshold (Boost Switching) VST –1 . 6 1 . 8 V VBST Undervoltage Lockout VBST_UVLO –6 . 0– V Input DC Supply Current (Normal Operation Mode, Enabled) IIN –6 0– m A VIN1 Pin Input Supply Current (EN1 = EN2 = 0) IIN1 –9 . 0– m A VIN2 Pin Input Leakage Current (EN1 = EN2 = 0) IIN2 –T B D– µA VDDI Internal Supply Voltage VDDI 3.0 – 3.3 V VDDI Maximum Output Current IDDI –T B D– µA BUCK CONVERTER Buck Converter Output Voltage Range IVOUT = 30 mA to 3.0 A, VIN1 = VIN2 = 2.8 V to 6.0 V VOUT 0.8 – 5.0 V Buck Converter Feedback Voltage Includes Load Regulation Error VINV 0.784 0.8 0.816 V Buck Converter Voltage Margining Step VMVO –1 . 0– % Buck Converter Line Regulation VIN1 = VIN2 = 2.8 V to 6.0 V, IVOUT = 3.0 A REGLNVO -1.0 – 1.0 Buck Converter Load Regulation IVOUT = 30 mA to 3.0 A REGLDVO -1.0 – 1.0 VOUT Input Leakage Current VOUT = 5.0 V IVOUTLK –T B D– µA High-Side Power MOSFET Q1 RDS(ON) ID = 1.0 A, TA = 25°C, VBST = 8.0 V RDS(ON) –– 5 0 mΩ Low-Side Power MOSFET Q2 RDS(ON) ID = 1.0 A, TA = 25°C, VBST = 8.0 V RDS(ON) –– 5 0 mΩ Buck Converter Peak Current Limit (High Level) IH_LIM 3.4 4.5 6.0 A Buck Converter Valley Current Limit (Low Level) IL_LIM 1.7 2.25 3.0 A VOUT Pull-Down MOSFET Q3 Current Limit TA = 25°C, VBST = 8.0 V IQ3_LIM –2 . 0– A VOUT Pull-Down MOSFET Q3 RDS(ON) ID = 1.0 A, TA = 25°C, VBST = 8.0 V RDS(ON) –– 1 . 0 Ω Thermal Shutdown (Switcher, VOUT FET) TSD 150 170 190 °C Thermal Shutdown Hysteresis TSDHys –1 5– ° C Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33702 ERROR AMPLIFIER (BUCK CONVERTER) Input Impedance (Note 7) RIN – 500 – k Ω Output Impedance (Note 7) ROUT – 150 – Ω DC Open Loop Gain (Note 7) AVOL –8 0– d B Gain Bandwidth Product (Note 7) GBW – 35 – MHz Slew Rate (Note 7) SR – 200 – V/ µs Output Voltage Swing – High Level VIN1 > 3.3 V, IOEA = -1.0 mA (Note 7) VEA_OH –2 . 0– V Output Voltage Swing – Low Level IOEA = -1.0 mA (Note 7) VEA_OL –0 . 4– V Slope Compensation Ramp (Note 7) VSCRamp –0 . 6– V OSCILLATOR Oscillator Low Level Output Voltage (Pin CLKSYN), CLKSEL Open VOSC_OL –– 0 . 4 V Oscillator High Level Output Voltage (Pin CLKSYN), CLKSEL Open VOSC_OH 3.0 – – V Oscillator Input Voltage Threshold (Pin CLKSYN), CLKSEL Grounded VOSC_IH 1.2 1.6 2.0 V Oscillator Frequency Adjusting Reference Voltage (FREQ) VFREQ –1 . 2 9– V Oscillator Frequency Adjusting Resistor Range RFREQ 100 – 200 k Ω BOOST REGULATOR Boost Regulator Output Voltage IBST = 20 mA, VIN1 = VIN2 = 2.8 V to 6.0 V VBST 7.5 8.0 8.5 V Boost Regulator Start-Up Voltage VIN_BSU –1 . 6 1 . 8 V Boost Regulator Peak Current Limit (Power FET Peak Current) IP_BD 0.75 1.0 1.5 A Boost Regulator Power FET Valley Current Limit (Low Level) IL_BD 450 600 800 mA Boost Power FET RDS(ON) IBD = 1.0 A, TA = 25°C RDS(ON) – 150 400 mΩ Boost Regulator Recommended Output Capacitor CBST –1 0– µF Boost Regulator Recommended Output Capacitor Maximum ESR ESRCBST – 100 – m Ω Notes 7. Design information only. It is not production tested. STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions -40°C ≤ TJ ≤ 125°C unless otherwise noted. Input voltages VIN1 = VIN2 = 3.3 V using the typical application circuit (see Figure 20) unless otherwise noted. Characteristic Symbol Min Typ Max Unit Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

LINEAR REGULATOR (LDO) LDO Output Voltage Range VIN1 = VIN2 = 2.8 V to 6.0 V, ILDO = 10 mA to 1000 mA VLDO 0.8 – 5.0 V LDO Feedback Voltage, LFB Pin Connected to LDO Pin VIN1 = VIN2 = 2.8 V to 6.0 V, ILDO = 10 mA to 1000 mA. Includes Load Regulation Error VLDO 0.784 0.8 0.816 V LDO Voltage Margining Step Size VMLDO –1 . 0– % LDO Line Regulation VIN1 = VIN2 = 2.8 V to 6.0 V, ILDO = 1000 mA REGLNVLDO -1.0 – 1.0 LDO Load Regulation ILDO = 10 mA to 1000 mA REGLDVLDO -1.0 – 1.0 LDO Ripple Rejection, Dropout Voltage VDO = 1.0 V, VRIPPLE = +1.0 V p-p Sinusoidal, f = 300 kHz, ILDO = 500 mA VLDO_RR –4 0– dB LDO Maximum Dropout Voltage (VIN - VLDO) VLDO = 2.5 V, ILDO = 1000 mA VDO –– T B D V LDO Current Sense Comparator Threshold Voltage (VCS - VLDO) VCSTH 35 45 55 mV LDO Pin Input Current ILDO 1.6 2.0 2.4 mA LDO Feedback Input Current (LFB Pin) ILFB -5.0 – 5.0 µA LDO Drive Output Current (LDRV Pin) ILDRV 2.0 3.6 5.0 mA LDO Drive Current Limit (LDRV Pin) IDRLIM –3 . 6– m A CS Pin Input Leakage Current VCS = 5.0 V ICSLK 50 – 300 µA LDO Error Amplifier Input Impedance (LFB Pin) RIN –T B D– Ω LDO Error Amplifier Output Impedance (LCMP Pin) ROUT –T B D– Ω LDO Pull-Down MOSFET Q4 Current Limit TA = 25°C, VBST = 8.0 V (LDO Pin) IQ4_LIM –- 2 . 0– A LDO Pull-Down MOSFET Q4 RDS(ON) ID = 1.0 A, TA = 25°C, VBST = 8.0 V RDS(ON) –– 1 . 0 Ω LDO Recommended Output Capacitance CLDO –1 0– µF LDO Recommended Output Capacitor ESR ESRCLDO –T B D– m Ω Thermal Shutdown (LDO Pull-Down FET Q4) TSD 150 170 190 °C Thermal Shutdown Hysteresis TSDHys –1 5– ° C STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions -40°C ≤ TJ ≤ 125°C unless otherwise noted. Input voltages VIN1 = VIN2 = 3.3 V using the typical application circuit (see Figure 20) unless otherwise noted. Characteristic Symbol Min Typ Max Unit Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33702 CONTROL AND SUPERVISORY CIRCUITS Enable (EN1, EN2) Input Voltage Threshold VTH_EN 1.2 1.6 2.0 V Enable (EN1, EN2) Input Voltage Threshold Hysteresis VIHYS –0 . 1– V Enable (EN1, EN2) Pull-Down Resistance RPU 30 60 120 k Ω RESET Low-Level Output Voltage, IOL = 5.0 mA VOL –– 0 . 4 V RESET Leakage Current, OFF State, Pulled Up to 5.0 V ILKG-RST –– 1 0 µA RESET Undervoltage Threshold on VOUT (∆VOUT/VOUT) (Note 8) VOUTITh -10 -7.5 -5.0 % RESET Overvoltage Threshold on VOUT (∆VOUT/VOUT) (Note 8) VOUTITh 5.0 7.5 10 % RESET Undervoltage Threshold on VLDO (∆VLDO/VLDO) (Note 8) VLDOITh -10 -7.5 -5.0 % RESET Overvoltage Threshold on VLDO (∆VLDO/VLDO) (Note 8) VLDOITh 5.0 7.5 10 % Reset Timer Voltage Threshold VTH-RT TBD 1.2 TBD V Reset Timer Source Current IS-RT 2 0–3 0 m A Reset Timer Leakage Current ILKG-RT -1.0 – 1.0 µA Reset Timer Saturation Voltage, Reset Timer Current = 300 µA VSAT-RT – 100 TBD mV Maximum Value of the Reset Timer Capacitor Ct –– 4 7 µF CLKSEL Threshold Voltage VthCLKS 1.2 1.6 2.0 V CLKSEL Pull-Up Resistance RPU-CLKS 60 120 240 k Ω ADDR Threshold Voltage VthADDR 1.2 1.6 2.0 V ADDR Pull-Up Resistance RPU-ADDR 60 120 240 k Ω SDA, SCL Pins I2C Bus (STANDARD) Input Threshold Voltage VIth 1.3 – 1.7 V Input Voltage Threshold Hysteresis VIHYS –0 . 2– V SDA, SCL Input Current, Input Voltage = 0.4 V to 6.0 V II –– 1 0 µA SDA Low-Level Output Voltage, 3.0 mA Sink Current VOL –– 0 . 4 V SCA, SCL Capacitance CI – – 10 pF Notes 8. This parameter does not include the toler ance of the external resistor divider. STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions -40°C ≤ TJ ≤ 125°C unless otherwise noted. Input voltages VIN1 = VIN2 = 3.3 V using the typical application circuit (see Figure 20) unless otherwise noted. Characteristic Symbol Min Typ Max Unit Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

DYNAMIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions -40°C ≤ TJ ≤ 125°C unless otherwise noted. Input voltages VIN1 = VIN2 = 3.3 V using the typical application circuit (see Figure 20) unless otherwise noted. Characteristic Symbol Min Typ Max Unit BUCK CONVERTER Duty Cycle Range (Normal Operation) D 0 – 90 % Switching Node SW Rise Time (Note 9) ILOAD = 3.0 A tRISE – TBD – ns Switching Node SW Fall Time (Note 9) ILOAD = 3.0 A tFALL – TBD – ns Maximum Deadtime (Note 9) tD –T B D– n s Buck Control Loop Propagation Delay (Note 9) VINV < 0.8 V to VSW > 90% of High Level or VINV > 0.8 V to VSW < 10% of Low Level tPD –5 0– ns Soft Start Duration (Power Sequencing Disabled, EN1 = 1, EN2 = 1) t SS 200 350 800 µs Fault Condition Timeout t FAULT –1 0– m s Retry Timer Cycle t Ret – 100 – ms OSCILLATOR Oscillator Default Frequency (Switching Frequency), FREQ Pin Open f OSC 270 300 330 kHz Oscillator Frequency Range f OSC 200 400 kHz Oscillator Frequency Accuracy RF = 100 kΩ fOSC 360 400 440 kHz Oscillator Frequency Accuracy RF = 200 kΩ fOSC 180 200 220 kHz Oscillator Output Signal Duty Cycle (Square Wave, 180° Out-of-Phase with the Internal Suitable Oscillator) DOSC –5 0– Synchronization Pulse Minimum Duration t SYNC 300 – – ns BOOST REGULATOR Boost Regulator FET Maximum ON Time t ON –2 4– µs Boost Regulator Control Loop Propagation Delay (Note 9) tBST_PD –5 0– n s Boost Switching Node VBD Rise Time (Note 9) IBST = 20 mA tB_RISE –1 5 4 0 ns Boost Switching Node VBD Fall Time (Note 9) IBST = 20 mA tB_FALL –1 5 4 0 ns Notes 9. Design Information only. Not production tested. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Figure 2. Definition of Time on the I2C Bus application circuit (see Figure 20) unless otherwise noted.

  1. Design Information only. Not production tested.
  2. The device provides an internal hold time of at least 300 ns for the SDA signal (refer to the VIH_MIN of the SCL signal) to bridge the undefined

region of the falling edge of SCL. Freescale Semiconductor, Inc.

Figure 3. Buck RDS(ON) (Temp) Figure 4. FOSC (RF) Figure 5. Buck Efficiency Figure 6. ILIM (Temp) Figure 7. Vref (Temp) Figure 8. RT Timer (Rt, Ct) Freescale Semiconductor, Inc.

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33702 SYSTEM/APPLICATION INFORMATION INTRODUCTION The 33702 power supply integrated circuit provides the means to efficiently supply the Power QUICC and other families of Motorola microprocessors. It incorporates a high- performance synchronous buck regulator, supplying the microprocessor’s core, and a low dropout (LDO) linear regulator providing the microprocessor I/O and bus voltages. This device incorporates many advanced features; e.g., precisely maintained up/down power sequencing, ensuring the proper operation and protection of the CPU and power system. At the same time, it provides high flexibility of configuration, allowing the maximum optimization of the power supply system. FUNCTIONAL DESCRIPTION Switching Regulator The switching regulator is a high-frequency (300 kHz default, adjustable in the range from 200 kHz to 400 kHz), synchronous buck converter driving integrated high-side and low-side N-channel power MOSFETs. The switching regulator output voltage is adjustable by means of an external resistor divider to provide the required output voltage within plus/minus two percent accuracy, and it is intended to directly power the core of the microprocessor. The buck controller utilizes a Sensorless PWM Current Mode Control topology to achieve excellent line rejection, stabilize the feedback loop, and provide cycle-by- cycle current limiting. A typical bootstrap technique is used to provide voltage necessary to properly enhance the high-side MOSFET gate. When the regulator is supplied only from low-input voltage (e.g., single +3.3 V supply rail), the bootstrap capacitor is charged from the internal boost regulator output VBST through an external diode. This arrangement allows the 33702 to operate from very low input voltage and also comply with the power sequencing requirements of the supplied microcontroller. To avoid destruction of the supplied circuits, a current limit with retry capability was implemented in the switching regulator. When an overcurrent condition occurs and the switch current reaches the peak current limit value, the main (high-side) switch is turned off until the inductor current decays to the valley value, which is one-half of the peak current limit. If an overcurrent condition exists for 10 ms, the buck regulator control circuit shuts the switcher OFF and the switcher retry timer starts to time out. When the timer expires after 100 ms, the switcher engages the start-up sequence and runs for 10 ms, repeatedly checking for the overcurrent condition. During the current limited operation (e.g., in case of short circuit on the switching regulator output), the switching regulator operation is not synchronized to the oscillator frequency. The output voltage VOUT can be adjusted by means of an external resistor divider connected to the feedback control pin INV. The switching regulator output voltage can be adjusted in the range of 0.8 V to 5.0 V, but the VOUT output voltage is always lower than the input voltage to the regulator. Power-up, power-down, and fault management are coordinated with the linear regulator. Thermal Shutdown To increase the overall safety of the system designed with the 33702, an internal thermal shutdown function has been incorporated into the switching regulator circuit. The 33702 senses the temperature of the buck regulator main switching FET (high-side FET Q1; see Figure 1), the low-side (synchronous FET Q2), and control circuit. If the temperature of any of the monitored components exceeds the limit of safe operation (thermal shutdown), the switching regulator will be shut down. After the temperature falls below the value given by the thermal shutdown hysteresis window, the switcher will retry to operate again. The VOUT pull-down FET Q3 has an independent thermal shutdown control. When the Q3 temperature exceeds the thermal shutdown limit, the Q3 will be turned off without affecting the switcher operation. Soft Start A switching regulator soft start feature is incorporated in the 33702. The soft start is active each time the IC is enabled, VIN is reapplied, or after a fault retry. Other transient events do not activate the soft start. Boost Regulator A boost regulator provides a high voltage necessary to properly drive the buck regulator power MOSFETs, especially during the low input voltage condition. The LDO regulator external N-channel MOSFET gate is also powered from the boost regulator. In order to properly enhance the high-side MOSFETs when only a +3.3 V supply rail powers the integrated circuit, the boost regulator provides an output voltage of 8.0 V nominal value. The 33702 boost regulator uses a simple hysteretic current control technique, which allows fast power-up and does not require any compensation. When the boost regulator main power switch (low side) is turned on, the current in the inductor starts to ramp up. After the inductor current reaches the upper current limit (nominally set at 1.0 A), the low-side switch is turned off and the current charges the output capacitor through the internal rectifier. When the inductor current falls below the valley current limit value (nominally 600 mA), the low-side switch is turned on again, starting the next switching cycle. After Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

the boost regulator output capacitor reaches its regulation limit, the low-side switch is turned off until the output voltage falls below the regulation limit again. Oscillator A 300 kHz (default) oscillator sets the switching frequency of the buck regulator. The frequency of the oscillator can be adjusted between 200 kHz and 400 kHz by an optional external resistor RF connected from the FREQ pin of the integrated circuit to ground. See Figure 4 for frequency resistor selection. The CLKSYN pin can be configured either as an oscillator output when the CLKSEL pin is left open or it can be used as a synchronization input when the CLKSEL pin is grounded. The oscillator output signal is a square wave logic signal with 50 percent duty cycle, 180 degrees out-of-phase with the internal clock signal. This allows opposite phase synchronization of two 3370x devices. When the CLKSYN pin is used as synchronization input (CLKSEL pin grounded), the external resistor RF chosen from the chart in Figure 4 should be used to synchronize the internal slope compensation ramp to the external clock. Operation is only recommended between 200 kHz and 400 kHz. The supplied synchronization signal does not need to be 50 percent duty cycle. Minimum pulse width is 300 ns. Low Dropout Linear Regulator (LDO) The adjustable low dropout linear regulator (LDO) is capable of supplying a 1.0 A output current. It has a current limit with retry capability. When the voltage measured across the current sense resistor reaches the 45 mV threshold, the control circuit limits the current for 1.0 ms and if the overcurrent condition still exists the linear regulator is turned off. At the same time the overcurrent condition is detected, the Retry Timer starts to time out. When the timer expires after 100 ms, the LDO tries to power up again for 1.0 ms, repeatedly checking for the overcurrent condition. The current limit of the LDO can be set by using the following formula: ILIM = 45 mV/R S Where RS is the LDO current sense resistor, connected between the CS pin and the LDO pin output (see Figure 20). When no current sense resistor is used, it is still possible to detect the overcurrent condition by tying the current sense pin CS to the VBST voltage. In this case, the overcurrent condition is sensed by saturation of the linear regulator driver buffer. The output voltage of the LDO can be adjusted by means of an external resistor divider connected to the feedback control pin LFB. The linear regulator output voltage can be adjusted in the range of 0.8 V to 5.0 V, but the LDO output voltage is always lower than the input voltage to the regulator. Power-up, power- down, and fault management are coordinated with the switching regulator. Thermal Shutdown The LDO pull-down FET Q4 has an independent thermal shutdown control. When the Q4 temperature exceeds the thermal shutdown limit, the Q4 will be turned off without affecting the LDO operation. Voltage Margining The 33702 includes a voltage margining feature accessed through the I2C bus. Voltage margining allows for independent adjustment of the Switcher VOUT voltage and the linear output VLDO. Each can be adjusted up and down in 1% steps to a range of ±7%. This feature allows for worst case system validation; i.e., determining the design margin. Margining details are described in the section entitled I2C Bus Operation, beginning on page 19 of this datasheet. RESET The RESET pin is an open drain output. The Reset Control circuit supervises both output voltages—the linear regulator output VLDO and the switching regulator output VOUT. When either of these two regulators is out of regulation (high or low), the RESET pin is pulled low. There is a 20 µs delay filter preventing erroneous resets. During power-up sequencing, RESET is held low until the Reset Timer times out. Reset Timer Power-Up Delay (RT) The Reset Timer Power-Up Delay (RT) pin is used to set the delay between the time when the LDO and switcher outputs are active and stable and the release of the RESET output. An external resistor and capacitor are used to program the timer. The power-up delay can be obtained by using the following formula: TD = 10 ms + RtCt Where Rt is the Reset Timer programming resistor and Ct is the Reset Timer programming capacitor, both connected in parallel from RT to ground. Note Observe the maximum Ct value and expect reduced accuracy if Rt is less than 10 kΩ. Watchdog Timer A watchdog function is available via I2C bus communication. It is possible to select either window watchdog or time-out watchdog operation, as illustrated in Figure 9 on page 15. Watchdog time-out starts when the watchdog function is activated via I2C bus sending a Watchdog Programming command byte, thus determining watchdog operation (window or time-out) and period duration (refer to Table 1, page 15). If the watchdog is cleared by receiving a new Watchdog Programming command through the I2C bus, the watchdog timer is reset and the new time-out period begins. If the watchdog time expires, the RESET will become active (LOW) for a time determined by the RC components of the RT timer plus 10 ms. After a watchdog time-out, the function is no longer active. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Figure 9. Watchdog Operation Table 1. Watchdog Programming Command Byte RC components of the RT timer plus 10 ms. Power Sequencing mode selection. Table 2. Operating Mode Selection Figure 10. Standard Power Up/Down Sequence Figure 11. Standard Power Up/Down Sequence

01100000 W D O F F

01101010 W D 8 0 m s

01101011 W D 2 0 m s

01101110 W D 8 0 m s

01101111 W D 2 0 m s

  1. The Watchdog feature will be turned

1.0 V/ms

3.3 V Input Supply (I/O Voltage)

1.8 V Core Voltage

3.3 V I/O Voltage (VLDO)

1.8 V Core Voltage (VOUT)

Freescale Semiconductor, Inc.

Figure 12. Inverted Power Up/Down Sequence in +5.0 V page 15, shows the Power Sequencing mode selection. Figure 12. Table 2 shows the Power Sequencing mode

33702 POWER SEQUENCING

  1. I/O supply voltage not to exceed core voltage by more than
  2. Core supply voltage not to exceed I/O voltage by more

boost regulator storage capacitor.

  1. LDO > VOUT + 1.8 V, turn off LDO. The LDO can be

exceeds the switcher output voltage by more than 1.8 V.

  1. LDO > VOUT + 1.9 V, shunt LDO to ground. If turning off
  2. LDO < VOUT + 1.7 V, cancel (1) and (2) above, re-enable
  3. LDO < VOUT - 0.2 V, turn off switcher. The switcher can
  4. LDO < VOUT - 0.3 V, turn on Sync (LS) FET and 1.0 Ω
  5. LDO > VOUT , reset (4) and (5) above. Normal operation

3.3 V I/O Voltage (VOUT)

1.8 V Core Voltage(VLDO)

Freescale Semiconductor, Inc.

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33702 Inverted Power Sequencing Control Comparators monitor voltage differences between the switcher (VOUT pin) and LDO (LDO pin) outputs as follows: 1. VOUT > LDO + 1.8 V, turn off VOUT . The switcher VOUT can be forced off. This occurs whenever the VOUT output voltage exceeds the LDO output voltage by more than 1.8 V. 2. VOUT > LDO + 1.9 V, shunt VOUT to ground. If turning off the switcher VOUT is insufficient and the VOUT output voltage exceeds the LDO output voltage by more than 1.9 V, a 1.0 Ω shunt FET is turned on that discharges the VOUT load capacitor to ground. The shunt FET is used for LDO output shorts to ground and for power-down in case of VIN1 ≠ VIN2 with LDO output falling faster than the VOUT. 3. VOUT < LDO + 1.7 V, cancel (1) and (2) above, re-enable VOUT. Normal operation resumes when the VOUT output voltage is less than 1.7 V above the LDO output voltage. 4. VOUT < LDO - 0.2 V, turn off LDO. The LDO can be forced off. This occurs whenever the VOUT is less than VLDO - 0.2 V. 5. VOUT < LDO - 0.3 V, turn on the 1.0 Ω LDO sink FET. This occurs when the LDO output voltage exceeds the VOUT output by more than 300 mV. 6. VOUT > LDO, reset (4) and (5) above. Normal operation resumes when VOUT > LDO. Standard Operating Mode 1. Single 3.3 V Supply, V IN = VIN1 = VIN2 = 3.3 V The 3.3 V supplies the microprocessor I/O voltage, the switcher supplies core voltage (e.g., 1.8 V nominal), and the LDO operates independently (see Figure 10, page 15). Power sequencing depends only on the normal switcher intrinsic operation to control the Buck High-Side FET. Power Up When VIN is rising, initially VOUT will be below the regulation point and the Buck High-Side FET will be on. In order not to exceed the 2.0 V differential requirement between the I/O (VIN) and the core (VOUT), the switcher must start up at 2.0 V or less and be able to maintain the 2.0 V or less differential. The maximum slew rate for VIN is 1.0 V/ms. Power Down When VIN is falling, VOUT will be below the regulation point; therefore the Buck High-Side FET will be on. In the case where VOUT is falling faster than VIN, the Buck High-Side FET will attempt to maintain VOUT. In the case where VIN is falling faster than VOUT, the Buck High-Side FET is also on, and the VOUT load capacitor will be discharged through the Buck High-Side FET to VIN. Thus, provided VIN does not fall too fast, the core voltage (VOUT) will not exceed the I/O voltage (VIN) by more than a maximum of 0.4 V. Shorted Load 1. VOUT shorted to ground. This will cause the I/O voltage to exceed the core voltage by more than 2.0 V. No load protection. 2. VIN shorted to ground. Until the switcher load capacitance is discharged, the core voltage will exceed the I/O voltage by more than 0.4 V. By the intrinsic operation of the switcher, the load capacitor will be discharged rapidly through the Buck High-Side FET to VIN. 3. VOUT shorted to supply. No load protection. 33702 protected by current limit and thermal limit. 2. Single 5.0 V Supply, V IN1 = VIN2, or Dual Supply VIN1 ≠ VIN2 The LDO supplies the microprocessor I/O voltage. The switcher supplies the core (e.g., 1.8 V nominal) (see Figure 11, page 15). Power Up This condition depends upon the regulator current limit, load current and capacitance, and the relative rise times of the VIN1 and VIN2 supplies. There are 2 cases: 1. LDO rises faster than VOUT. The LDO uses control methods (1) and (2) described in the Methods of Control section, page 16. 2. VOUT rises faster than LDO. The switcher uses control methods (4) and (5) described in the Methods of Control section, page 16. Power Down This condition depends upon the regulator load current and capacitance and the relative fall times of the VIN1 and VIN2 supplies. There are 2 cases: 1. VOUT falls faster than LDO. The LDO uses control methods (1) and (2) described in the Methods of Control section, page 16. In the case VIN1 = VIN2, the intrinsic operation will turn on both the Buck High-Side FET and the LDO external Pass FET, and will discharge the LDO load capacitor into the VIN supply. 2. LDO falls faster than VOUT. The switcher uses control methods (4) and (5) described in the Methods of Control section, page 16. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

  1. VOUT shorted to ground. The LDO uses method (1) and (2) described in the Methods of Control section, page 16. 2. LDO shorted to ground. The switcher uses control methods (4) and (5) described in the Methods of Control section, page 16. 3. VIN1 shorted to ground. This is equivalent to the LDO output shorted to ground. 4. VIN2 shorted to ground. This is equivalent to the switcher output shorted to ground. 5. VOUT shorted to supply. No load protection. 33702 protected by current limit and thermal limit. 6. LDO shorted to supply. No load protection. 33702 protected by current limit and thermal limit. Inverted Operating Mode 1. Single 3.3 V Supply, V IN = VIN1 = VIN2 = 3.3 V The 3.3 V supplies the microprocessor I/O voltage, the LDO supplies core voltage (e.g., 1.8 V nominal), and the switcher VOUT operates independently. Power sequencing depends only on the normal LDO intrinsic operation to control the Pass FET. Power Up When VIN is rising, initially LDO will be below the regulation point and the Pass FET will be on. In order not to exceed the

2.0 V differential requirement between the I/O (VIN) and the

core (LDO), the LDO must start up at 2.0 V or less and be able to maintain the 2.0 V or less differential. The maximum slew rate for VIN is 1.0 V/ms. Power Down When VIN is falling, LDO will be below the regulation point; therefore the Pass FET will be on. In the case where LDO is falling faster than VIN, the Pass FET will attempt to maintain LDO. In the case where VIN is falling faster than LDO, the Pass FET is also on, and the LDO load capacitor will be discharged through the Pass FET to VIN. Thus, provided VIN does not fall too fast, the core voltage (LDO) will not exceed the I/O voltage (VIN) by more than maximum of 0.4 V. Shorted Load 1. LDO shorted to ground. This will cause the I/O voltage to exceed the core voltage by more than 2.0 V. No load protection. 2. VIN shorted to ground. Until the LDO load capacitance is discharged, the core voltage will exceed the I/O voltage by more than 0.4 V. By the intrinsic operation of the LDO, the load capacitor will be discharged rapidly through the Pass FET to VIN. 3. LDO shorted to supply. No load protection. 2. Single 5.0 V Supply, V IN1 = VIN2, or Dual Supply VIN1 ≠ VIN2 The switcher VOUT supplies the microprocessor I/O voltage. The LDO supplies the core (e.g., 1.8 V nominal) (see Figure 12, page 16). Power Up This condition depends upon the regulator current limit, load current and capacitance, and the relative rise times of the VIN1 and VIN2 supplies. There are 2 cases: 1. VOUT rises faster than LDO. The switcher VOUT uses control methods (4) and (5) described in the Methods of Control section, page 17. 2. LDO rises faster than VOUT . The LDO uses control methods (1) and (2) described in the Methods of Control section, page 17. Power Down This condition depends upon the regulator load current and capacitance and the relative fall times of the VIN1 and VIN2 supplies. There are 2 cases: 1. LDO falls faster than VOUT . The VOUT uses control methods (4) and (5) described in the Methods of Control section, page 17. In the case VIN1 = VIN2 the intrinsic operation will turn both the Buck High-Side FET and the LDO external Pass FET, and will discharge the VOUT load capacitor into the VIN supply. 2. VOUT falls faster than LDO. The LDO uses control methods (1) and (2) described in the Methods of Control section, page 17. Shorted Load 1. LDO shorted to ground. The VOUT uses methods (4) and (5) described in the Methods of Control section, page 17. 2. VOUT shorted to ground. The LDO uses control methods (1) and (2) described in the Methods of Control section. 3. VIN1 shorted to ground. This is equivalent to the LDO output shorted to ground. 4. VIN2 shorted to ground. This is equivalent to the switcher VOUT output shorted to ground. 5. LDO shorted to supply. No load protection. 6. VOUT shorted to supply. No load protection. 33702 protected by current limit and thermal limit. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Figure 13. Communication Using 7-Bit Address the CLKSEL pin and the ADDR pin. configuration of the oscillator synchronization CLKSYN pin. assigned to each individual part to assure its unique address. portion of the device address. Figure 14. Address Bit Definition for 7-Bit Address sequence. Actions performed by the slave device are grayed. Figure 15. Data Transfer for Write Operations The address field is selected from the list in Table 4. Figure 16. Command Byte Table 4. Address Field Definitions definitions for the entire set of operation options. Table 3. Definition of Selectable Portion of Device Address

001 Voltage Margining W

010 Not Used –

011 Watchdog W

Freescale Semiconductor, Inc.

Table 5. Command Byte Definitions Security in Writing Commands in sequence after the first command, one for each supply. Figure 17. Voltage Margining Programming Note x bits are defined in Table 5. options listed in Table 5. Also see Figure 18. Figure 18. Watchdog Timer Programming Note x bits are defined in Table 5.

  1. The Watchdog feature will be turned ON automatically

Table 6. First Command Definitions Freescale Semiconductor, Inc.

APPLICATION INFORMATION

Figure 20. Simplified Block Diagram and Typical Application Freescale Semiconductor, Inc.

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33702 PACKAGE DIMENSIONS NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TO LERANCING PER ASME Y14.5M, 1994. 3. DATUMS B AND C TO BE DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 4. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURRS. MOLD FLASH, PROTRUSION OR GATE BURRS SHALL NOT EXCEED 0.15 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 5. THIS DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH AND PROTRUSIONS SHALL NOT EXCEED 0.25 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 6. THIS DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.4 MM PER SIDE. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD SHALL NOT LESS THAN 0.07 MM. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 MM AND 0.3 MM FROM THE LEAD TIP. 9. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. THIS DIMENSION IS DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTER-LEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. CL10.9 7.4 16 17 0.10 A 2.35 SEATING PLANE 0.9 SECTION B-B 0.65 R0.08 MIN B A PIN 1 ID (0.29) 0.38 0.25 (0.203) PLATING BASE METAL SECTION A-A ROTATED 90 CLOCKWISE° 0.19 0.22

0.13 M CA M B

A C7.6 11.1 10.3 5.15 A 32X 30X 2.65 0.3 A 2X 16 TIPS B C BB 0.29 0.13 0.50° 0°0.25 GAUGE PLANE MIN DWB SUFFIX 32-LEAD SOIC WIDE BODY PLASTIC PACKAGE CASE 1324-02 ISSUE A Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center Motorola Literature Distribution 3-20-1 Minami-Azabu. Minato-ku, Tokyo 106-8573, Japan P.O. Box 5405, Denver, Colorado 80217 81-3-3440-3569 1-800-521-6274 or 480-768-2130 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong 852-26668334 HOME PAGE: http://motorola.com/semiconductors MC33702/D Information in this document is provided solely to enable system and software implem enters to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further noti ce to any products herein. Motorola makes no warranty, represen tation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or s pecifications can and do vary in different applications and actual performance may var y over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola pro ducts are not designed, intended, or authorized for use as compon ents in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and di stributors harmless against all claims, costs, damages, and expenses , and reasonable attorney fees arising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. MOTOROLA and the Stylized M Logo are registered in the US Patent and Trademark Office. All other product or service names are t he property of their respective owners. © Motorola, Inc. 2003 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...