DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 13
Technical content
/C0084/C0077/C0083/C0050/C0055/C0067/C0050/C0053/C0054 /C0051/C0050/C0055/C0054/C0056 /C0066/C0089 /C0056/C0262/C0066/C0073/C0084 /C0085/C0086 /C0069/C0082/C0065/C0083/C0065/C0066/C0076/C0069 /C0084/C0077/C0083/C0050/C0055/C0080/C0067/C0050/C0053/C0054 /C0051/C0050/C0055/C0054/C0056 /C0066/C0089 /C0056/C0262/C0066/C0073/C0084 /C0080/C0082/C0079/C0071/C0082/C0065/C0077/C0077/C0065/C0066/C0076/C0069 /C0082/C0069/C0065/C0068/C0262/C0079/C0078/C0076/C0089 /C0077/C0069/C0077/C0079/C0082/C0073/C0069/C0083 SMLS256H− SE PTEMBER 1984 − REVISED NOVEMBER 1997 1POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 /C0068Organization...3 2 7 6 8 b y 8 Bits /C0068Single 5-V Power Supply /C0068Pin Compatible With Existing 256K MOS ROMs, PROMs, and EPROMs /C0068All Inputs /Outputs Fully TTL Compatible /C0068Max Access/Min Cycle Time VCC ± 10% ’27C/PC256-10 100 ns ’27C/PC256-12 120 ns ’27C/PC256-15 150 ns ’27C/PC256-17 170 ns ’27C/PC256-20 200 ns ’27C/PC256-25 250 ns /C0068Power Saving CMOS Technology /C0068Very High-Speed SNAP! Pulse Programming /C00683-State Output Buffers /C0068400-mV Minimum DC Noise Immunity With Standard TTL Loads /C0068Latchup Immunity of 250 mA on All Input and Output Lines /C0068Low Power Dissipation (VCC = 5.5 V) − Active. . . 165 mW Worst Case − Standby. . . 1.4 mW Worst Case (CMOS Input Levels) /C0068Temperature Range Options /C0068256K EPROM Available With MIL-STD-883C Class B High Reliability Processing (SMJ27C256)
description
The TMS27C256 series are 32768 by 8-bit (262144-bit), ultraviolet (UV) light erasable, electrically programmable read-only memories (EPROMs). The TMS27PC256 series are 32768 by 8-bit (262144-bit), one-time programmmable (OTP) electrically programmable read-only memories (PROMs). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 321 3 2 3 1 43 0 15 16 17 18 1920 PIN NOMENCLATURE A0−A14 Address Inputs DQ0−DQ7 Inputs (programming)/Outputs E Chip Enable/Powerdown G Output Enable GND Ground NC No Internal Connection NU Make No External Connection VCC 5-V Power Supply VPP 13-V Power Supply† J PACKAGE (TOP VIEW) VPP A12 DQ0 DQ1 DQ2 GND V CC A14 A13 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 A8 A11 NC G A10 E DQ7 DQ6 NC DQ0 DQ1 DQ2 NU DQ3 DQ4 A12 V NU V A14 A13 FM PACKAGE (TOP VIEW) DQ5 CC GND PP † Only in program mode /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 Copyright 1997, Texas Instruments Incorporated
2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TMS27PC256 are pin compatible with 28-pin 256K MOS ROMs, PROMs, and EPROMs. plastic leaded chip-carrier package using 1,25-mm (50-mil) lead spacing (FM suffix). FML suffixes) and − 40°C to 85°C (JE and FME suffixes). See Table 1. All package styles conform to JEDEC standards. Table 1. Temperature Range Suffixes programming algorithm uses a VPP of 13 V and a VCC of 6.5 V for a nominal programming time of four seconds. programmed singly, in blocks, or at random.
TTL level except for VPP during programming (13 V for SNAP! Pulse), and 12 V on A9 for the signature mode. Table 2. Operation Modes pins. Output data is accessed at pins DQ0 through DQ7. Latchup immunity on the TMS27C256 and TMS27PC256 is a minimum of 250 mA on all inputs and outputs. without compromising performance or packing density.
- A typical 12-mW/cm2, filterless UV lamp erases the device in 21
should be covered with an opaque label.
4 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
are programmed into the desired locations. Logic lows programmed into an OTP PROM cannot be erased. time varies as a function of the programmer used. Data is presented in parallel (eight bits) on pins DQ0 to DQ7. Once addresses and data are stable, E is pulsed. pulses per byte are provided before a failure is recognized. can be programmed when the devices are connected in parallel. Locations can be programmed in any order. Programming can be inhibited by maintaining a high level input on the E pin. Programmed bits can be verified with VPP = 13 V when G = VIL and E = VIH. A0 high selects the device code 04, as shown in Table 3. Table 3. Signature Mode
Figure 1. SNAP! Pulse Programming Flowchart
/C0084/C0077/C0083/C0050/C0055/C0067/C0050/C0053/C0054 /C0051/C0050/C0055/C0054/C0056 /C0066/C0089 /C0056/C0262/C0066/C0073/C0084 /C0085/C0086 /C0069/C0082/C0065/C0083/C0065/C0066/C0076/C0069 /C0084/C0077/C0083/C0050/C0055/C0080/C0067/C0050/C0053/C0054 /C0051/C0050/C0055/C0054/C0056 /C0066/C0089 /C0056/C0262/C0066/C0073/C0084 /C0080/C0082/C0079/C0071/C0082/C0065/C0077/C0077/C0065/C0066/C0076/C0069 /C0082/C0069/C0065/C0068/C0262/C0079/C0078/C0076/C0089 /C0077/C0069/C0077/C0079/C0082/C0073/C0069/C0083 SMLS256H− SEPTEMBER 1984 − REVISED NOVEMBER 1997
6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
logic symbol† [PWR DWN] EN A A A A A A A A A10 A11 A12 A13 A14 E G EPROM 32 768 × 8 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 A 0 32 767 A 0 32 767 A A A A A A A A [PWR DWN] EN A10 A11 A12 A13 A14 E G OTP PROM 32 768 × 8 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 † These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for J package. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to GND.
/C0084/C0077/C0083/C0050/C0055/C0067/C0050/C0053/C0054 /C0051/C0050/C0055/C0054/C0056 /C0066/C0089 /C0056/C0262/C0066/C0073/C0084 /C0085/C0086 /C0069/C0082/C0065/C0083/C0065/C0066/C0076/C0069 /C0084/C0077/C0083/C0050/C0055/C0080/C0067/C0050/C0053/C0054 /C0051/C0050/C0055/C0054/C0056 /C0066/C0089 /C0056/C0262/C0066/C0073/C0084 /C0080/C0082/C0079/C0071/C0082/C0065/C0077/C0077/C0065/C0066/C0076/C0069 /C0082/C0069/C0065/C0068/C0262/C0079/C0078/C0076/C0089 /C0077/C0069/C0077/C0079/C0082/C0073/C0069/C0083 SMLS256H− SE PTEMBER 1984 − REVISED NOVEMBER 1997 7POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 recommended operating conditions MIN NOM MAX UNIT VCC Supply voltage Read mode (see Note 2) 4.5 5 5.5 VVCC Supply voltage SNAP! Pulse programming algorithm 6.25 6.5 6.75 V VPP Supply voltage Read mode VCC −0.6 VCC +0.6 VVPP Supply voltage SNAP! Pulse programming algorithm 12.75 13 13.25 V VIH High-level dc input voltage TTL 2 VCC +1 VVIH High-level dc input voltage CMOS VCC − 0.2 VCC +1 V VIL Low-level dc input voltage TTL − 0.5 0.8 VVIL Low-level dc input voltage CMOS − 0.5 0.2 V TA Operating free-air temperature ’27C256-_ _JL ’27PC256-_ _FML 0 70 °C TA Operating free-air temperature ’27C256-_ _JE ’27PC256-_ _FME −4 0 85 °C NOTE 2: V CC must be applied before or at the same time as VPP and removed after or at the same time as VPP. The device must not be inserted into or removed from the board when VPP or VCC is applied. electrical characteristics over recommended ranges of operating conditions PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT VOH High-level dc output voltage IOH = − 2.5 mA 3.5 VVOH High-level dc output voltage IOH = − 20 µA VCC − 0.1 V VOL Low-level dc output voltage IOL = 2.1 mA 0.4 VVOL Low-level dc output voltage IOL = 20 µA 0.1 V II Input current (leakage) VI = 0 V to 5.5 V ±1 µA IO Output current (leakage) VO = 0 V to VCC ±1 µA IPP1 VPP supply current VPP = VCC = 5.5 V 1 10 µA IPP2 VPP supply current (during program pulse) VPP = 13 V 35 50 mA ICC1 VCC supply current TTL-input level VCC = 5.5 V, E = VIH 250 500 AICC1 VCC supply current (standby) CMOS-input level VCC = 5.5 V, E = VCC 100 250 µA ICC2 VCC supply current (active) VCC = 5.5 V, E = VIL, tcycle = minimum cycle time, outputs open 15 30 mA capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz† PARAMETER TEST CONDITIONS MIN TYP ‡ MAX UNIT C i Input capacitance VI = 0, f = 1 MHz 6 10 pF C o Output capacitance VO = 0, f = 1 MHz 10 14 pF † Capacitance measurements are made on a sample basis only. ‡ Typical values are at TA = 25°C and nominal voltages.
/C0084/C0077/C0083/C0050/C0055/C0067/C0050/C0053/C0054 /C0051/C0050/C0055/C0054/C0056 /C0066/C0089 /C0056/C0262/C0066/C0073/C0084 /C0085/C0086 /C0069/C0082/C0065/C0083/C0065/C0066/C0076/C0069 /C0084/C0077/C0083/C0050/C0055/C0080/C0067/C0050/C0053/C0054 /C0051/C0050/C0055/C0054/C0056 /C0066/C0089 /C0056/C0262/C0066/C0073/C0084 /C0080/C0082/C0079/C0071/C0082/C0065/C0077/C0077/C0065/C0066/C0076/C0069 /C0082/C0069/C0065/C0068/C0262/C0079/C0078/C0076/C0089 /C0077/C0069/C0077/C0079/C0082/C0073/C0069/C0083 SMLS256H− SEPTEMBER 1984 − REVISED NOVEMBER 1997
8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
switching characteristics over recommended range of operating conditions PARAMETER TEST CONDITIONS (SEE NOTES 3 AND 4) ’27C256-10 ’27PC256-10 ’27C256-12 ’27PC256-12 ’27C256-15 ’27PC256-15 UNITPARAMETER (SEE NOTES 3 AND 4) MIN MAX MIN MAX MIN MAX UNIT ta(A) Access time from address 100 120 150 ns ta(E) Access time from chip enable C = 100 pF, 100 120 150 ns ten(G) Output enable time from G C L = 100 pF,
1 Series 74 TTL Load, 55 55 75 ns
Output disable time from G or E, whichever occurs first†
1 Series 74 TTL Load,
Input tr ≤ 20 ns, Input tf ≤ 20 ns 0 45 0 45 0 60 ns tv(A) Output data valid time after change of address, E, or G, whichever occurs first† Input tf ≤ 20 ns 0 0 0 ns PARAMETER TEST CONDITIONS (SEE NOTES 3 AND 4) ’27C256-17 ’27PC256-17 ’27C256-20 ’27PC256-20 ’27C256-25 ’27PC256-25 UNITPARAMETER (SEE NOTES 3 AND 4) MIN MAX MIN MAX MIN MAX UNIT ta(A) Access time from address 170 200 250 ns ta(E) Access time from chip enable C = 100 pF, 170 200 250 ns ten(G) Output enable time from G C L = 100 pF,
1 Series 74 TTL Load, 75 75 100 ns
Output disable time from G or E, whichever occurs first† Input tr ≤ 20 ns, Input tf ≤ 20 ns 0 60 0 60 0 60 ns tv(A) Output data valid time after change of address, E, or G, whichever occurs first† Input tf ≤ 20 ns 0 0 0 ns † Value calculated from 0.5 V delta to measured level. This parameter is only sampled and not 100% tested. NOTES: 3. For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and 0.8 V for logic low) (see Figure 2). 4. Common test conditions apply for the tdis except during programming. switching characteristics for programming: VCC = 6.50 V and VPP = 13 V (SNAP! Pulse), TA = 25°C (see Note 3) PARAMETER MIN MAX UNIT tdis(G) Output disable time from G 0 130 ns ten(G) Output enable time from G 150 ns NOTE 3: For all switching characteristics, the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and 0.8 V for logic low). timing requirements for programming MIN NOM MAX UNIT th(A) Hold time, address 0 µs th(D) Hold time, data 2 µs tw(IPGM) Pulse duration, initial program 95 100 105 µs tsu(A) Setup time, address 2 µs tsu(G) Setup time, G 2 µs tsu(E) Setup time, E 2 µs tsu(D) Setup time, data 2 µs tsu(VPP) Setup time, VPP 2 µs tsu(VCC) Setup time, VCC 2 µs
NOTE A: C L includes probe and fixture capacitance.
2 V 2 V
2 V for logic high and 0.8 V for logic low for both inputs and outputs. Figure 2. AC Testing Output Load Circuit Figure 3. Read-Cycle Timing
10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Figure 4. Program-Cycle Timing (SNAP! Pulse Programming)
/C0084/C0077/C0083/C0050/C0055/C0067/C0050/C0053/C0054 /C0051/C0050/C0055/C0054/C0056 /C0066/C0089 /C0056/C0262/C0066/C0073/C0084 /C0085/C0086 /C0069/C0082/C0065/C0083/C0065/C0066/C0076/C0069 /C0084/C0077/C0083/C0050/C0055/C0080/C0067/C0050/C0053/C0054 /C0051/C0050/C0055/C0054/C0056 /C0066/C0089 /C0056/C0262/C0066/C0073/C0084 /C0080/C0082/C0079/C0071/C0082/C0065/C0077/C0077/C0065/C0066/C0076/C0069 /C0082/C0069/C0065/C0068/C0262/C0079/C0078/C0076/C0089 /C0077/C0069/C0077/C0079/C0082/C0073/C0069/C0083 SMLS256H− SE PTEMBER 1984 − REVISED NOVEMBER 1997 11POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 FM (R-PQCC-J32) PLASTIC J-LEADED CHIP CARRIER 4040201-4/B 03/95 0.020 (0,51) 0.015 (0,38) Seating Plane 0.140 (3,56) 0.132 (3,35) 0.123 (3,12) 0.129 (3,28) 0.043 (1,09) 0.049 (1,24) 0.008 (0,20) NOM 0.595 (15,11) 0.553 (14,05) 0.585 (14,86) TYP 0.030 (0,76) 0.547 (13,89) 301 0.495 (12,57) 0.453 (11,51) 0.485 (12,32) 0.447 (11,35) 0.050 (1,27) 0.004 (0,10) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-016
/C0084/C0077/C0083/C0050/C0055/C0067/C0050/C0053/C0054 /C0051/C0050/C0055/C0054/C0056 /C0066/C0089 /C0056/C0262/C0066/C0073/C0084 /C0085/C0086 /C0069/C0082/C0065/C0083/C0065/C0066/C0076/C0069 /C0084/C0077/C0083/C0050/C0055/C0080/C0067/C0050/C0053/C0054 /C0051/C0050/C0055/C0054/C0056 /C0066/C0089 /C0056/C0262/C0066/C0073/C0084 /C0080/C0082/C0079/C0071/C0082/C0065/C0077/C0077/C0065/C0066/C0076/C0069 /C0082/C0069/C0065/C0068/C0262/C0079/C0078/C0076/C0089 /C0077/C0069/C0077/C0079/C0082/C0073/C0069/C0083 SMLS256H− SEPTEMBER 1984 − REVISED NOVEMBER 1997
12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
J (R-CDIP-T) CERAMIC SIDE-BRAZE DUAL-IN-LINE PACKAGE 4040084/B 04/95 B C 0.018 (0,46) MIN 0.125 (3,18) MIN 0.022 (0,56) 0.008 (0,20) Seating Plane A WIDE A PINS DIM MAX MIN NARR MIN MAX B C MAX MIN NARR WIDE NARR WIDE WIDE NARR
24 PIN SHOWN
0.045 (1,14) 0.065 (1,65) 0.090 (2,29) 0.060 (1,53) Lens Protrusion 0.010 (0,25) MAX 0.175 (4,45) 0.140 (3,56) 0.100 (2,54) 0°−/C0257 10° NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.
(TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for
applications
design. Customers are responsible for their products and components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. TI products are not authorized for use in safety-critical (such as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications. TI products are neither designed nor intended for use in military/aerospace "enhanced plastic." Only products designated by TI as military-grade meet military specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI products are neither designed nor intended for use in automotive requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Clocks and Timers www.ti.com/clocks Digital Control www.ti.com/digitalcontrol Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security RFID www.ti-rfid.com Telephony www.ti.com/telephony RF/IF and ZigBee Solutions www.ti.com/lprf Video Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright 2008, Texas Instruments Incorporated