PC2119RU/2

PCF2119X-2 PHILIPS | Alldatasheet

Document overview

• Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 60

Technical content

Datasheet sections

• 1 FEATURES
• 1.1 Note
• 2 APPLICATIONS
• 3 GENERAL DESCRIPTION
• 4 ORDERING INFORMATION
• 5 BLOCK DIAGRAM
• 6 PAD INFORMATION
• 6.1 Pad functions
• 7 FUNCTIONAL DESCRIPTION
• 7.1 LCD supply voltage generator
• 7.2 Programming ranges
• 7.3 LCD bias voltage generator
• 7.4 Oscillator
• 7.5 External clock
• 7.6 Power-on reset
• 7.7 Power-down mode
• 7.8 Registers
• 7.9 Busy flag
• 7.10 Address Counter (AC)
• 7.11 Display Data RAM (DDRAM)
• 7.12 Character Generator ROM (CGROM)
• 7.13 Character Generator RAM (CGRAM)
• 7.14 Cursor control circuit
• 7.15 Timing generator
• 7.16 LCD row and column drivers
• 7.17 Reset function
• 8 INSTRUCTIONS
• 8.1 Clear display
• 8.2 Return home
• 8.3 Entry mode set
• 8.4 Display control (and partial power-down mode)
• 8.5 Cursor or display shift
• 8.6 Function set
• 8.7 Set CGRAM address
• 8.8 Set DDRAM address
• 8.9 Read busy flag and read address
• 8.10 Write data to CGRAM or DDRAM
• 8.11 Read data from CGRAM or DDRAM
• 9 EXTENDED FUNCTION SET
• 9.1 New instructions
• 9.2 Icon control
• 9.5 Normal/icon mode operation
• 9.6 Screen configuration
• 9.7 Display configuration
• 9.8 TC1 and TC2
• 9.9 Set V
• 9.10 Reducing current consumption
• 10 INTERFACES TO MPU
• 10.1 Parallel interface
• 11 LIMITING VALUES
• 12 HANDLING
• 13 DC CHARACTERISTICS
• 14 AC CHARACTERISTICS
• 15 TIMING CHARACTERISTICS
• 16 APPLICATION INFORMATION
• 16.1 General Application Information
• 17 BONDING PAD LOCATIONS
• 18 DEFINITIONS
• 19 LIFE SUPPORT APPLICATIONS
• 20 PURCHASE OF PHILIPS I

Product specification File under Integrated Circuits, IC12 28. August 2000 INTEGRATED CIRCUITS PCF2119x-2 LCD controllers/drivers

1. August 2000 3 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2

1 FEATURES

• Single-chip LCD controller/driver
• 2-line display of up to 16 characters + 160 icons, or 1-line display of up to 32 characters + 160 icons
• 5 × 7 character format plus cursor; 5× 8 for kana (Japanese) and user defined symbols
• Icon mode: reduced current consumption while displaying icons only
• Icon blink function
• On-chip: – Configurable 4 (3, 2) * voltage multiplier generating LCD supply voltage, independent of VDD , programmable by instruction (external supply also possible) – Temperature compensation of on-chip generated V LCD :−0.16 to−0.24 %/K (programmable by instruction) – Generation of intermediate LCD bias voltages – Oscillator requires no external components (external clock also possible).
• Display Data RAM: 80 characters
• Character Generator ROM: 240, 5× 8 characters
• Character Generator RAM: 16, 5× 8 characters; 4 characters used to drive 160 icons, 8 characters used if icon blink feature is used in application
• 4 or 8-bit parallel bus and 2-wire I 2C-bus interface
• CMOS compatible
• 18 row and 80 column outputs
• Multiplex rates 1 : 18 (for normal operation), 1 : 9 (for single line operation) and 1 : 2 (for icon only mode)
• Uses common 11 code instruction set (extended)
• Logic supply voltage range, VDD1 − VSS = 1.5 to 5.5 V (chip may be driven with two battery cells)
• HVgen supply voltage range, VDD2,3 − VSS = 2.2 to 4.0V
• Display supply voltage range, VLCD − VSS = 2.2 to 6.5 V
• Direct mode to save current consumption for icon mode and Mux 1 : 9 (depending on VDD2 value and LCD liquid properties)
• Very low current consumption (20 to 200µA): – Icon mode: <25µA – Power-down mode: <2µA.

1.1 Note

Icon mode is used to save current. When only icons are displayed, a much lower operating voltage VLCD can be used and the switching frequency of the LCD outputs is reduced. In most applications it is possible to use V DD as VLCD .

2 APPLICATIONS

• Telecom equipment
• Portable instruments
• Point-of-sale terminals.

3 GENERAL DESCRIPTION

The PCF2119x is a low power CMOS LCD controller and driver, designed to drive a dot matrix LCD display of 2-line by 16 or 1-line by 32 characters with 5× 8 dot format. All necessary functions for the display are provided in a single chip, including on-chip generation of LCD bias voltages, resulting in a minimum of external components and lower system current consumption. The PCF2119x interfaces to most microcontrollers via a 4 or 8-bit bus or via the 2-wire I 2C-bus. The chip contains a character generator and displays alphanumeric and kana (Japanese) characters. The letter ‘x’ in PCF2119x characterizes the built-in character set. Various character sets can be manufactured on request.

4 ORDERING INFORMATION

PC2119RU/2 − chip with bumps in tray − PC2119SU/2 − chip with bumps in tray − PC2119VU/2 − chip with bumps in tray −

1. August 2000 4 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2

5 BLOCK DIAGRAM

Fig.1 Block diagram. handbook, full pagewidth MGK891 CURSOR AND DATA CONTROL SHIFT REGISTER 5 × 12 BIT DATA LATCHES COLUMN DRIVERS CHARACTER GENERATOR RAM (128 × 5) (CGRAM)

16 CHARACTERS

(CGROM)

240 CHARACTERS

(DDRAM)

80 CHARACTERS/BYTES

(AC) INSTRUCTION DECODER INSTRUCTION REGISTER ROW DRIVERS SHIFT REGISTER 18-BIT BIAS VOLTAGE GENERATOR VLCD GENERATOR BUSY FLAG DATA REGISTER (DR) I/O BUFFER OSCILLATOR TIMING GENERATOR DISPLAY ADDRESS COUNTER VDD1 VLCD2 VSS1 VLCD1 12, 13 14, 15 8, 9 T2 7 T3 129 136 1, 2 VDD2 3, 4 C1 to C80 R17DUP R1 to R18 OSC PD PCF2119x DB1 to DB3 DB0/SA0 DB4 to DB7 E R/W RS SCL SDA 144 131 POR130 7 7 137 to 139 118 to 127, 106 to 92 87 to 73, 71 to 57, 52 to 38, 16 to 25 27 to 34, 116 to 109, 26, 117 140 to 143 132, 133 1281351345 VSS2 10, 11 46...51 39...45 7...14 15...18 22...29 30...37 157 164 158 159 172 55...63 145...153 10464...103 105...1444 1...6 VDD1 VLCDSENSE 38 DB3/SA0

1. August 2000 5 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2

6 PAD INFORMATION

The identification of each pad and its location is given in Chapter 18.

6.1 Pad functions

Table 1 Pad function description Note 1. When the I2C-bus is used, the parallel interface pad E must be at logic 0. In the I2C-bus read mode DB0 - DB2 and DB3 - DB7 should be connected to VDD1 or left open-circuit. a) When the parallel bus is used, pads SCL and SDA must be connected to VSS1 or VDD1 ; they must not be left open-circuit. b) If the 4-bit interface is used without reading out from the PCF2119x (i.e. R/W is set permanently to logic 0), the unused ports DB0 to DB4 can either be set to VSS1 or VDD1 instead of leaving them open-circuit. SYMBOL DESCRIPTION VDD1 Logic supply voltage VDD2,3 High voltage generator supply voltages (always put VDD2 = VDD3 ). VSS1 This is the ground pad for all except the high voltage generator. VSS2 This is the ground pad for the high voltage generator. VLCD1 This input is used for the generation of the LCD bias levels. VLCD2 This is the VLCD output pad if VLCD is generated internally. This pad must be connected to VLCD1 . VLCDSENSE This input (VLCD ) is used for the voltage multiplier’s regulation circuitry. This pad must be connected to VLCD2 . E The data bus clock input is set HIGH to signal the start of a read or write operation; data is clocked in or out of the chip on the negative edge of the clock; note 1. T1 These are three test pads. T1 and T2 must be connected to VSS1 ; T3 is left open-circuit and is not user accessible.T2 R1 to R18; R17DUP LCD row driver outputs R1 to R18; these pads output the row select waveforms to the display; R17 and R18 drive the icons. R17 has two pads R17 and R17DUP. C1 to C80 LCD column driver outputs C1 to C80. SCL I 2C-bus serial clock input; note 1. POR External power-on reset input. PD PD selects the chip power-down mode; for normal operation PD = 0. SDA I 2C-bus serial data input/output; note 1. R/W This is the read/write input. R/ W selects either the read (R/W = 1) or write (R/W = 0) operation. This pad has an internal pull-up resistor. RS The RS input selects the register to be accessed for read and write. RS = 0, selects the instruction register for write and the busy flag and address counter for read. RS = 1, selects the data register for both read and write. This pad has an internal pull-up resistor. DB0 to DB7 The 8-bit bidirectional data bus (3-state) transfers data between the system controller and the PCF2119x. DB7 may be used as the busy flag, signalling that internal operations are not yet completed. In 4-bit operations the 4 higher order lines DB7 to DB4 are used; DB3 to DB0 must be left open-circuit. Data bus line DB3 has an alternative function (SA0), when selected this is the I 2C-bus address pad. Each data line has its own internal pull-up resistor; note 1. OSC Oscillator or external clock input. When the on-chip oscillator is used this pad must be connected to VDD1.

1. August 2000 6 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2

7 FUNCTIONAL DESCRIPTION

7.1 LCD supply voltage generator

The LCD supply voltage may be generated on-chip. The voltage generator is controlled by two internal 6-bit registers: V A and VB. The nominal LCD operating voltage at room temperature is given by the relationship:

7.2 Programming ranges

Programmed value: 1 to 63. Voltage: 1.90 to 6.86 V. Tref=2 7°C. Values producing more than 6.5 V at operating temperature are not allowed. Operation above this voltage may damage the device. When programming the operating voltage the V LCD temperature coefficient must be taken into account. Values below 2.2 V are below the specified operating range of the chip and are therefore not allowed. Value 0 for VA and VB switches the generator off (i.e. VA = 0 in character mode, VB = 0 in icon mode). Usually register VA is programmed with the voltage for character mode and register VB with the voltage for icon mode. V OP(nom) integer value of register 0.08×() 1.82+= When V LCD is generated on-chip the VLCD pads should be decoupled to VSS with a suitable capacitor. The generated VLCD is independent of VDD and is temperature compensated. When the voltage generator and the direct mode are switched off, an external voltage may be supplied at connected pads V LCD1,2. VLCD1,2 may be higher or lower than VDD . During direct mode (program DM register bit) the internal voltage generator is turned off and the VLCD output voltage is directly connected to VDD2 . This reduces the current consumption during icon mode and Mux 1 : 9 (depending on V DD2 value and LCD liquid properties). The LCD supply voltage generator ensures that, as long as VDD is in the valid range (2.2 to 4 V), the required peak voltage VOP = 6.5 V can be generated at any time.

7.3 LCD bias voltage generator

The intermediate bias voltages for the LCD display are also generated on-chip. This removes the need for an external resistive bias chain and significantly reduces the system current consumption. The optimum value of V LCD depends on the multiplex rate, the LCD threshold voltage th) and the number of bias levels. Using a 5-level bias scheme for 1 : 18 maximum rate allows VLCD < 5 V for most LCD liquids. The intermediate bias levels for the different multiplex rates are shown in Table 2. These bias levels are automatically set to the given values when switching to the corresponding multiplex rate. Table 2 Bias levels as a function of multiplex rate Note 1. The values in the above table are given relative to V op − Vss, e.g. 3/4 means 3/4× (Vop − Vss). MULTIPLEX RATE NUMBER OF LEVELS V1 V2 V3 V4 V5 V6 1:1 8 5 V op 3/4(1) 1/2 1/2 1/4 V ss 1:9 5 V op 3/4 1/2 1/2 1/4 V ss 1:2 4 V op 2/3 2/3 1/3 1/3 V ss

1. August 2000 7 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2

7.4 Oscillator

The on-chip oscillator provides the clock signal for the display system. No external components are required and the OSC pad must be connected to V DD .

7.5 External clock

If an external clock is to be used this is input at the OSC pad. The resulting display frame frequency is given by: Only in the power-down state is the clock allowed to be stopped (OSC connected to VSS ), otherwise the LCD is frozen in a DC state.

7.6 Power-on reset

The PC2119x must be reset externally. This is an internal synchronous reset that requires 3 OSC cycles to be executed after release of the external reset signal. If no external reset is performed, the chip might start-up in an unwanted state. The external reset is active high.

7.7 Power-down mode

The chip can be put into power-down mode by applying an external active high level to the PD pad. In power-down mode all static currents are switched off (no internal oscillator, no bias level generation and all LCD outputs are internally connected to V SS ). During power-down, information in the RAMs and the chip state are preserved. Instruction execution during power-down is possible when pad OSC is externally clocked.

7.8 Registers

The PCF2119x has two 8-bit registers, an Instruction Register (IR) and a Data Register (DR). The Register Select signal (RS) determines which register will be accessed. The instruction register stores instruction codes such as ‘display clear’ and ‘cursor shift’, and address information for the Display Data RAM (DDRAM) and Character Generator RAM (CGRAM). f frame fOSC The instruction register can be written to but not read from by the system controller. The data register temporarily stores data to be read from the DDRAM and CGRAM. When reading, data from the DDRAM or CGRAM corresponding to the address in the instruction register is written to the data register prior to being read by the ‘read data’ instruction.

7.9 Busy flag

The busy flag indicates the internal status of the PCF2119x. A logic 1 indicates that the chip is busy and further instructions will not be accepted. The busy flag is output to pad DB7 when RS = 0 and R/ W = 1. Instructions should only be written after checking that the busy flag is at logic 0 or waiting for the required number of cycles.

7.10 Address Counter (AC)

The address counter assigns addresses to the DDRAM and CGRAM for reading and writing and is set by the commands ‘set CGRAM address’ and ‘set DDRAM address’. After a read/write operation the address counter is automatically incremented or decremented by 1. The address counter contents are output to the bus (DB6 to DB0) when RS = 0 and R/ W=1 .

7.11 Display Data RAM (DDRAM)

The DDRAM stores up to 80 characters of display data represented by 8-bit character codes. RAM locations which are not used for storing display data can be used as general purpose RAM. The basic RAM to display addressing scheme is shown in Fig.2. With no display shift the characters represented by the codes in the first

32 RAM locations starting at address 00H in line 1 are

displayed. Figures 3 and 4 show the display mapping for right and left shift respectively. When data is written to or read from the DDRAM wrap-around occurs from the end of one line to the start of the next line. When the display is shifted each line wraps around within itself, independently of the others. Thus all lines are shifted and wrapped around together. The address ranges and wrap-around operations for the various modes are shown in Table 3. Table 3 Address space and wrap-around operation MODE 1 × 32 2 × 16 1 × 9 Address space 00 to 4F 00 to 27; 40 to 67 00 to 27 Read/write wrap-around (moves to next line) 4F to 00 27 to 40; 67 to 00 27 to 00 Display shift wrap-around (stays within line) 4F to 00 27 to 00; 67 to 40 27 to 00

1. August 2000 8 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2 Fig.2 DDRAM to display mapping: no shift. handbook, full pagewidth 00 01 02 03 04 1D 1E 1F 20 21 4C 4D 4E 4F non-displayed DDRAM addresses 64 65 66 6740 41 42 43 44 4D 4E 4F 50 51 00 01 02 03 04 0D 0E 0F 10 11 24 25 26 27 non-displayed DDRAM address line 1 line 2 MGK892 DDRAM address 2-line display/MUX 1 : 9 mode 12345 3 0 3 1 3 2 12345 1 4 1 5 1 6 12345 1 4 1 5 1 6 display position DDRAM address 1-line display handbook, halfpage MGL536 27 00 01 02 03 67 40 41 42 43 0C 0D 0E 4C 4D 4E DDRAM address line 1 line 2 2-line display/MUX 1 : 9 mode 1 2 3 4 5 14 15 16 1 2 3 4 5 10 11 12 Fig.3DDRAM to display mapping: right shift Fig.4DDRAM to display mapping; left shift handbook, halfpage 01 04 05 41 42 43 44 45 0E 0F 10 4E 4F 50 DDRAM address line 1 line 2 2-line display/MUX 1 : 9 mode 1 2 3 4 5 30 31 32 1 2 3 4 5 14 15 16 1 2 3 4 5 14 15 16 01 04 05 02 03 02 03 1E 1F 20 display position DDRAM address 1-line display MGK894

1. August 2000 9 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2

7.12 Character Generator ROM (CGROM)

The Character Generator ROM generates 240 character patterns in a 5× 8 dot format from 8-bit character codes. Figure 6 to 8 show the character sets that are currently implemented.

7.13 Character Generator RAM (CGRAM)

Up to 16 user defined characters may be stored in the Character Generator RAM. Some CGRAM characters (see Fig.17) are also used to drive icons (6 if icons blink and both icon rows are used in the application; 3 if no blink but both icon rows are used in the application; 0 if no icons are driven by the icon rows). The CGROM and CGRAM use a common address space, of which the first column is reserved for the CGRAM (see Fig.6). Figure 9 shows the addressing principle for the CGRAM.

7.14 Cursor control circuit

The cursor control circuit generates the cursor (underline and/or cursor blink as shown in Fig.5 at the DDRAM address contained in the address counter. When the address counter contains the CGRAM address the cursor will be inhibited.

7.15 Timing generator

The timing generator produces the various signals required to drive the internal circuitry. Internal chip operation is not disturbed by operations on the data buses.

7.16 LCD row and column drivers

The PCF2119x contains 18 row and 80 column drivers, which connect the appropriate LCD bias voltages in sequence to the display in accordance with the data to be displayed. R17 and R18 drive the icon rows. The bias voltages and the timing are selected automatically when the number of lines in the display is selected. Figures 10 to 13 show typical waveforms. Unused outputs should be left unconnected. Fig.5 Cursor and blink display examples. MGA801cursor 5 x 7 dot character font alternating display cursor display example blink display example

1. August 2000 10 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2 Fig.6 Character set ‘R’ in CGROM. handbook, full pagewidth MGL535 xxxx 1111 16 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 11110000 upper 4 bitslower 4 bits xxxx 0000 xxxx 0001 xxxx 0010 xxxx 0011 xxxx 0100 xxxx 0101 xxxx 0110 xxxx 0111 xxxx 1000 xxxx 1001 xxxx 1010 xxxx 1011 xxxx 1100 xxxx 1101 xxxx 1110 15

1. August 2000 11 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2 Fig.7 Character set ‘S’ in CGROM. handbook, full pagewidth MGL534 xxxx 1111 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 11110000 upper 4 bitslower 4 bits xxxx 0000 xxxx 0001 xxxx 0010 xxxx 0011 xxxx 0100 xxxx 0101 xxxx 0110 xxxx 0111 xxxx 1000 xxxx 1001 xxxx 1010 xxxx 1011 xxxx 1100 xxxx 1101 xxxx 1110

1. August 2000 12 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2 Fig.8 Character set ‘V’ in CGROM. handbook, full pagewidth MGL597 xxxx 1111 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 11110000 upper 4 bitslower 4 bits xxxx 0000 xxxx 0001 xxxx 0010 xxxx 0011 xxxx 0100 xxxx 0101 xxxx 0110 xxxx 0111 xxxx 1000 xxxx 1001 xxxx 1010 xxxx 1011 xxxx 1100 xxxx 1101 xxxx 1110

1. August 2000 13 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2 Fig.9 Relationship between CGRAM addresses, data and display patterns. Character code bits 0 to 3 correspond to CGRAM address bits 3 to 6. CGRAM address bits 0 to 2 designate the character pattern line position. The 8th line is the cursor position and display is performed by logical OR with the cursor. Data in the 8th position will appear in the cursor position. Character pattern column positions correspond to CGRAM data bits 0 to 4, as shown in Fig.6. As shown in Figs 6 and 7, CGRAM character patterns are selected when character code bits 4 to 7 are all logic 0. CGRAM data = logic 1 corresponds to selection for display. Only bits 0 to 5 of the CGRAM address are set by the ‘set CGRAM address’ command. Bit 6 can be set using the ‘set DDRAM address’ command in the valid address range or by using the auto-increment feature during CGRAM write. All bits 0 to 6 can be read using the ‘read busy flag and address counter’ command. handbook, full pagewidth MGE995 76543210 6543210 43210 higher order bits lower order bits lower order bits higher order bits lower order bits higher order bits 00000000 0000000 0 001 000 010 000 011 0 100 0 00 101 00 0 110 000 111 00000 000 000 001 0 0 0 010 00 00011 100 101 00 00 110 00 00 111 00000 001 00000001 0001 00000010 00001111 00001111 00001111 00001111 010 0000 100 101 110 11 1 character codes (DDRAM data) CGRAM address character patterns (CGRAM data) 43210 000 111 000 00 10 00 0 1 000 1111 000 101 000 111 11 11 01 0 0 010 0100 000 character code (CGRAM data) character pattern example 1 cursor position character pattern example 2

1. August 2000 14 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2 Fig.10 MUX 1 : 18 LCD waveforms; character mode. handbook, full pagewidth MGE996 state 1 (ON) state 2 (OFF) frame n + 1 frame n 123 1 8123 1 8 ROW 1 VLCD V3/V4 VSS ROW 9 VLCD V3/V4 VSS ROW 2 VLCD V3/V4 VSS COL1 VLCD V3/V4 VSS COL2 VLCD V3/V4 VSS

0 Vstate 1

0.5VOP 0.25VOP −0.25VOP −0.5VOP −VOP

0 Vstate 2

0.5VOP 0.25VOP −0.25VOP −0.5VOP −VOP

1. August 2000 15 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2 Fig.11 MUX1:9 LCD waveforms; character mode. R10 to 18 to be left open. handbook, full pagewidth MGK900 state 1 (ON) state 2 (OFF) frame n + 1 frame n 19 1 9 ROW 1 VLCD V3/V4 VSS ROW 2 VLCD V3/V4 VSS ROW 3 VLCD V3/V4 VSS COL1 VLCD V3/V4 VSS COL2 VLCD V3/V4 VSS

0.5VOP 0.25VOP −0.25VOP −0.5VOP −VOP 0.5VOP 0.25VOP −0.25VOP −0.5VOP −VOP

1. August 2000 16 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2 Fig.12 MUX 1 : 2 LCD waveforms; icon mode. handbook, full pagewidth MGE997 frame n + 1 frame n VLCD VSS VLCD VSS VLCD VSS VLCD VSS VLCD VSS VLCD VSS VLCD VSS COL 4 OFF/OFF COL 3 ON/ON COL 2 OFF /ON COL 1 ON/OFF ROW 1 to 16 ROW 18 ROW 17 only icons are driven (MUX 1 : 2)

1. August 2000 17 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2 Fig.13 MUX 1 : 2 LCD waveforms; icon mode. VON(rms) = 0.745VOP VOFF(rms) = 0.333VOP D V ON V OFF handbook, full pagewidth MGE998 frame n + 1 frame n VOP 2/3 VOP 1/3 VOP −1/3 VOP −2/3 VOP −VOP VOP 2/3 VOP 1/3 VOP −1/3 VOP −2/3 VOP −VOP VOP 2/3 VOP 1/3 VOP −1/3 VOP −2/3 VOP −VOP state 3 COL 1 - ROW 1 to 16 state 2 COL 2 - ROW 17 state 1 COL 1 - ROW 17 state 3 (OFF) R17 R18 R1-16 VPIXEL state 1 (ON) state 2 (OFF)

1. August 2000 18 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2

7.17 Reset function

The PCF2119x must be reset externally when power is turned on. The reset executes a ‘clear display’, requiring 165 oscillator cycles. After the reset the chip has the state shown in Table 4. Table 4 State after reset STEP FUNCTION CONTROL BIT STATE CONDITION 1 clear display 2 entry mode set I/D = 1 +1 (increment) S = 0 no shift 3 display control D = 0 display off C = 0 cursor off B = 0 cursor character blink off 4 function set DL = 1 8-bit interface M = 0 1-line display H = 0 normal instruction set SL = 0 MUX 1 : 18 mode 5 default address pointer to DDRAM; the Busy Flag (BF) indicates the busy state (BF = 1) until initialization ends; the busy state lasts 2 ms; the chip may also be initialized by software; see Tables 18 and 19 6 icon control IM, IB, DM = 000 icons, icon blink and direct mode disabled 7 display/screen configuration L = 0; P = 0; Q = 0 default configurations LCD temperature coefficient TC1 = 0; TC2 = 0 default temperature coefficient 9 set V LCD VA = 0; VB = 0 (VLCD generator off)

10 I 2C-bus interface reset

11 Set HVgen stages S1, S0 = 10 HVgen set to 3 internal stages

(4 * voltage multiplier)

1. August 2000 19 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2

8 INSTRUCTIONS

Only two PCF2119x registers, the Instruction Register (IR) and the Data Register (DR) can be directly controlled by the MPU. Before internal operation, control information is stored temporarily in these registers, to allow interfacing to various types of MPUs which operate at different speeds or to allow interface to peripheral control ICs. The PCF2119x operation is controlled by the instructions shown in Table 6 together with their execution time. Details are explained in subsequent sections. Instructions are of 4 types, those that: 1. Designate PCF2119x functions such as display format, data length, etc. 2. Set internal RAM addresses 3. Perform data transfer with internal RAM 4. Others. In normal use, category 3 instructions are used most frequently. However, automatic incrementing by 1 (or decrementing by 1) of internal RAM addresses after each data write lessens the MPU program load. The display shift in particular can be performed concurrently with display data write, enabling the designer to develop systems in minimum time with maximum programming efficiency. During internal operation, no instructions other than the ‘read busy flag’ and ‘read address’ instructions will be executed. Because the busy flag is set to a logic 1 while an instruction is being executed, check to ensure it is a logic 0 before sending the next instruction or wait for the maximum instruction execution time, as given in Table 6. An instruction sent while the busy flag is logic 1 will not be executed. Table 5 Instruction set for I 2C-bus commands Note 1. R/W is set together with the slave address. CONTROL BYTE COMMAND BYTE I 2C-BUS COMMANDS C o R S 000000D B 7 D B 6 D B 5 D B 4 D B 3 D B 2 D B 1 D B 0 note 1

1. August 2000 20 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Table 6 Instruction set with parallel bus commands; note 1 INSTRUCTION RS R/ W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DESCRIPTION REQUIRED CLOCK CYCLES H=0o r1 N O P 0000000000 n o operation 3 Function set 00001 D L 0 M S L H sets interface Data Length (DL) and number of display lines (M); single line/MUX 1 : 9 (SL), extended instruction set control (H) Read busy flag and address counter 0 1 BF A C reads the Busy Flag (BF) indicating internal operating is being performed and reads address counter contents Read data 1 1 read data reads data from CGRAM or DDRAM 3 Write data 1 0 write data writes data from CGRAM or DDRAM 3 H=0 Clear display 0000000001 clears entire display and sets DDRAM address 0 in address counter 165 Return home 0000000010 sets DDRAM address 0 in address counter; also returns shifted display to original position; DDRAM contents remain unchanged Entry mode set 00000001 I / D S sets cursor move direction and specifies shift of display; these operations are performed during data write and read Display control 0000001D C B sets entire display on/off (D), cursor on/off (C) and blink of cursor position character (B); D = 0 (display off) puts chip into the power-down mode Cursor/display shift

000001 S / C R / L 00 moves cursor and shifts display without changing

CG sets CGRAM address; bit 6 is to be set by the command ‘set DDRAM address’; look at the description of the commands Set DDRAM address 001 A DD sets DDRAM address 3

1. August 2000 21 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Note 1. X = don’t care. H=1 Reserved 0000000001 d o not use − Screen configuration 000000001L set screen configuration 3 Display configuration 00000001P Q set display configuration 3 Icon control 0000001 I M I B D M set icon mode (IM), icon blink (IB), direct mode(DM) 3 Temperature control

00000100 T C 1 T C 2 set temperature coefficient (TCx) 3

Set HVgen stages 00010000 S 1 S 0 set internal HVgen stages (S1,S0 = 11 not allowed)3 Set VLCD 0 0 1 V voltage store V LCD in register VA or VB (V) 3 INSTRUCTION RS R/ W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DESCRIPTION REQUIRED CLOCK CYCLES

1. August 2000 22 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2 Table 7 Explanations of symbols used in Table 6 Table 8 Explanation of TC1 and TC2 used in Table 6 Table 9 Explanation of S1 and S0 used in Table 6 BIT STATE LOGIC 0 LOGIC 1 I/D decrement increment S display freeze display shift D display off display on C cursor off cursor on B cursor character blink off: character at cursor position does not blink cursor character blink on: character at cursor position blinks S/C cursor move display shift R/L left shift right shift DL 4 bits 8 bits H use basic instruction set use extended instruction set L (no impact, if M = 1 or SL = 1) left/right screen: standard connection (as in PCF2114) left/right screen: mirrored connection (as in PCF2116) 1st 16 characters of 32: columns are from 1 to 80 1st 16 characters of 32: columns are from 1 to 80 2nd 16 characters of 32: columns are from 1 to 80 2nd 16 characters of 32: columns are from 80 to 1 P column data: left to right (as in PCF2116); column data is displayed from 1 to 80 column data: right to left; column data is displayed from 80 to 1 Q row data: top to bottom (as in PCF2116); row data is displayed from 1 to 16 and icon row data is in 17 and 18 row data: bottom to top; row data is displayed from 16 to 1 and icon row data is in 18 and 17 IM character mode; full display icon mode; only icons displayed IB icon blink disabled icon blink enabled DM direct mode disabled direct mode enabled V set V A set VB M (no impact, if SL = 1) 1-line by 32 display 2-line by 16 display SL MUX 1 : 18 (1 × 32 or 2× 16 character display) MUX 1 : 9 (1× 16 character display) C 0 last control byte; see Table 5 another control byte follows after data/command TC1 TC2 DESCRIPTION

00 V LCD temperature coefficient 0

10 V LCD temperature coefficient 1

01 V LCD temperature coefficient 2

11 V LCD temperature coefficient 3; for ranges for TC see Chapter 13

0 0 set internal HVgen stages to 1 (2 * voltage multiplier) 0 1 set internal HVgen stages to 2 (3 * voltage multiplier) 1 0 set internal HVgen stages to 3 (4 * voltage multiplier) 1 1 do not use

1. August 2000 23 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2 Fig.14 4-bit transfer example. MGA804 RS E DB7 R/W DB6 DB5 DB4 instruction write busy flag and address counter read data register read IR7 IR3 BF AC3 DR7 DR3 IR6 IR2 AC6 AC2 DR6 DR2 IR5 IR1 AC5 AC1 DR5 DR1 IR4 IR0 AC4 AC0 DR4 DR0 Fig.15 An example of 4-bit data transfer timing sequence. IR7, IR3: instruction 7th, 3rd bit. AC3: address counter 3rd bit. D7, D3: data 7th, 3rd bit. MGA805 RS E internal DB7 R/W internal operation IR7 IR3 AC3 D7 D3 not busyAC3busy instruction write busy flag check busy flag check instruction write

1. August 2000 24 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2 Fig.16 Example of busy flag checking timing sequence. MGA806 instruction write busy flag check busy flag check busy flag check instruction write internal operation RS E internal DB7 R/W data busy busy not busy data

8.1 Clear display

‘Clear display’ writes character code 20H into all DDRAM addresses (the character pattern for character code 20H must be a blank pattern), sets the DDRAM address counter to logic 0 and returns the display to its original position, if it was shifted. Thus, the display disappears and the cursor or blink position goes to the left edge of the display. Sets entry mode I/D = 1 (increment mode). S of entry mode does not change. The instruction ‘clear display’ requires extra execution time. This may be allowed by checking the Busy Flag (BF) or by waiting until the 165 clock cycles have elapsed. The latter must be applied where no read-back options are foreseen, as in some Chip-On-Glass (COG) applications.

8.2 Return home

‘Return home’ sets the DDRAM address counter to logic 0 and returns the display to its original position if it was shifted. DDRAM contents do not change. The cursor or blink position goes to the left of the first display line. I/D and S of entry mode do not change.

8.3 Entry mode set

8.3.1 I/D

When I/D = 1 (0) the DDRAM or CGRAM address increments (decrements) by 1 when data is written into or read from the DDRAM or CGRAM. The cursor or blink position moves to the right when incremented and to the left when decremented. The cursor underline and cursor character blink are inhibited when the CGRAM is accessed. 8.3.2 S When S = 1, the entire display shifts either to the right (I/D = 0) or to the left (I/D = 1) during a DDRAM write. Thus it appears as if the cursor stands still and the display moves. The display does not shift when reading from the DDRAM, or when writing to or reading from the CGRAM. When S = 0, the display does not shift.

1. August 2000 25 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2

8.4 Display control (and partial power-down mode)

8.4.1 D The display is on when D = 1 and off when D = 0. Display data in the DDRAM is not affected and can be displayed immediately by setting D to a logic 1. When the display is off (D = 0) the chip is in partial power-down mode:

• The LCD outputs are connected to V SS
• The LCD generator and bias generator are turned off. Three oscillator cycles are required after sending the ‘display off’ instruction to ensure all outputs are at VSS , afterwards OSC can be stopped. If the oscillator is running during partial power-down mode (‘display off’) the chip can still execute instructions. Even lower current consumption is obtained by inhibiting the oscillator (OSC = V SS ). To ensure IDD <1 µA, the parallel bus pads DB7 to DB0 should be connected to VDD ; RS and R/W to VDD or left open-circuit and PD to VDD . Recovery from power-down mode: PD back to logic 0, if necessary OSC back to VDD and send a ‘display control’ instruction with D = 1. 8.4.2 C The cursor is displayed when C = 1 and inhibited when C = 0. Even if the cursor disappears, the display functions I/D, etc. remain in operation during display data write. The cursor is displayed using 5 dots in the 8th line (see Fig.5). 8.4.3 B The character indicated by the cursor blinks when B = 1. The cursor character blink is displayed by switching between display characters and all dots on with a period of approximately 1 second, with The cursor underline and the cursor character blink can be set to display simultaneously. f blink fOSC

8.5 Cursor or display shift

‘Cursor/display shift’ moves the cursor position or the display to the right or left without writing or reading display data. This function is used to correct a character or move the cursor through the display. In 2-line displays, the cursor moves to the next line when it passes the last position (40) of the line. When the displayed data is shifted repeatedly all lines shift at the same time; displayed characters do not shift into the next line. The Address Counter (AC) content does not change if the only action performed is shift display, but increments or decrements with the ‘cursor shift’.

8.6 Function set

8.6.1 DL (

PARALLEL MODE ONLY ) Sets interface data width. Data is sent or received in bytes (DB7 to DB0) when DL = 1 or in two nibbles (DB7 to DB4) when DL = 0. When 4-bit width is selected, data is transmitted in two cycles using the parallel bus. In a 4-bit application DB3 to DB0 should be left open-circuit (internal pull-ups). Hence in the first ‘function set’ instruction after power-on M, SL and H are set to logic 1. A second ‘function set’ must then be sent (2 nibbles) to set M, SL and H to their required values. ‘Function set’ from the I 2C-bus interface sets the DL bit to logic 1. 8.6.2 M Selects either 1-line by 32 display (M = 0) or 2-line by 16 display (M = 1). 8.6.3 SL Selects MUX 1 : 9, 1-line by 16 display (independent of M and L). Only rows 1 to 8 and 17 are to be used. All other rows must be left open-circuit. The DDRAM map is the same as in the 2-line by 16 display mode, however, the second line is not displayable.

1. August 2000 26 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2 8.6.4 H When H = 0 the chip can be programmed via the standard 11 instruction codes used in the PCF2116 and other LCD controllers. When H = 1 the extended range of instructions will be used. These are mainly for controlling the display configuration and the icons.

8.7 Set CGRAM address

‘Set CGRAM address’ sets bits 5 to 0 of the CGRAM address A CG into the address counter (binary A5 to A0). Data can then be written to or read from the CGRAM. Attention: the CGRAM address uses the same address register as the DDRAM address and consists of 7 bits (binary A6 to A0). With the ‘set CGRAM address’ command, only bits 5 to 0 are set. Bit 6 can be set using the ‘set DDRAM address’ command first, or by using the auto-increment feature during CGRAM write. All bits 6 to 0 can be read using the ‘read busy flag’ and ‘read address’ command. When writing to the lower part of the CGRAM, ensure that bit 6 of the address is not set (e.g. by an earlier DDRAM write or read action).

8.8 Set DDRAM address

‘Set DDRAM address’ sets the DDRAM address A DD into the address counter (binary A6 to A0). Data can then be written to or read from the DDRAM.

8.9 Read busy flag and read address

‘Read busy flag’ and ‘read address’ read the Busy Flag (BF) and Address Counter (AC). BF = 1 indicates that an internal operation is in progress. The next instruction will not be executed until BF = 0. It is recommended that the BF status is checked before the next write operation is executed. At the same time, the value of the address counter expressed in binary A6 to A0 is read out. The address counter is used by both CGRAM and DDRAM, and its value is determined by the previous instruction.

8.10 Write data to CGRAM or DDRAM

‘Write data’ writes binary 8-bit data D7 to D0 to the CGRAM or the DDRAM. Whether the CGRAM or DDRAM is to be written into is determined by the previous ‘set CGRAM address’ or ‘set DDRAM address’ command. After writing, the address automatically increments or decrements by 1, in accordance with the entry mode. Only bits D4 to D0 of CGRAM data are valid, bits D7 to D5 are ‘don’t care’.

8.11 Read data from CGRAM or DDRAM

‘Read data’ reads binary 8-bit data D7 to D0 from the CGRAM or DDRAM. The most recent ‘set address’ command determines whether the CGRAM or DDRAM is to be read. The ‘read data’ instruction gates the content of the Data Register (DR) to the bus while E is HIGH. After E goes LOW again, internal operation increments (or decrements) the AC and stores RAM data corresponding to the new AC into the DR. There are only three instructions that update the data register:

• ‘set CGRAM address’
• ‘set DDRAM address’
• ‘read data’ from CGRAM or DDRAM. Other instructions (e.g. ‘write data’, ‘cursor/display shift’, ‘clear display’ and ‘return home’) do not modify the data register content.

1. August 2000 27 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2

9 EXTENDED FUNCTION SET INSTRUCTIONS AND

FEATURES

9.1 New instructions

H = 1, sets the chip into alternate instruction set mode.

9.2 Icon control

The PCF2119x can drive up to 160 icons. See Fig.17 for CGRAM to icon mapping. 9.3 IM When IM = 0, the chip is in character mode. In the character mode characters and icons are driven (MUX 1 : 18). The V LCD generator, if used, produces the VLCD voltage programmed in register VA. When IM = 1, the chip is in icon mode. In the icon mode only the icons are driven (MUX 1 : 2) and the VLCD voltage generator, if used, produces the VLCD voltage as programmed in register VB. 9.4 IB Icon blink control is independent of the cursor/character blink function. When IB = 0, icon blink is disabled. Icon data is stored in CGRAM character 0 to 3 (4× 8 × 5 = 160 bits for 160 icons). When IB = 1, icon blink is enabled. In this case each icon is controlled by two bits. Blink consists of two half phases (corresponding to the cursor on and off phases called even and odd phases hereafter). Icon states for the even phase are stored in CGRAM characters 0 to 3 (4× 8 × 5 = 160 bits for 160 icons). These bits also define icon state when icon blink is not used. Icon states for the odd phase are stored in CGRAM character 4 to 7 (another 160 bits for the 160 icons). When icon blink is disabled CGRAM characters 4 to 6 may be used as normal CGRAM characters. Table 10Blink effect for icons and cursor character blink PARAMETER EVEN PHASE ODD PHASE Cursor character blink block (all on) normal (display character) Icons state 1: CGRAM character 0 to 2 state 2: CGRAM character 4 to 6

1. August 2000 28 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2 Fig.17 CGRAM to icon mapping. CGRAM data bit = logic 1 turns the icon on, data bit = logic 0 turns the icon off. Data in character codes 0 to 3 define the icon state when icon blink is disabled or during the even phase when icon blink is enabled. Data in character codes 4 to 7 define the icon state during the odd phase when icon blink is enabled (not used for icons when icon blink is disabled). handbook, full pagewidth MGK999 156-160 odd (blink) 18/76-80 0 0 0 0 0 1 1 1 icon view 0 1 1 1 1 1 1 0 0 1 1 0 1-5 odd (blink) 17/1-5 0 0 0 0 0 1 0 00 1 0 0 0 0 0 0 0 0 0 0 156-160 even 18/76-80 0 0 0 0 0 0 1 1 0 0 1 1 1 1 1 1 1 1 0 1 81-85 even 18/1-5 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 0 76-80 even 17/76-80 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 1 11-15 even 17/11-15 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 0 6-10 even 17/6-10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1-5 even 17/1-5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 7 6 5 4 3 2 1 0 MSB LSB LSB MSB MSB LSB 6 5 4 3 2 1 0 4 3 2 1 0 icon no. phase ROW/COL character codes CGRAM address CGRAM data handbook, full pagewidth COL 1 to 5 12345 81 82 83 84 85 display: ROW 17 – ROW 18 – block of 5 columns COL 6 to 10 6789 1 0 86 87 88 89 90 COL 76 to 80 76 77 78 79 80 156 157 158 159 160 MGL249

1. August 2000 29 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2

9.5 Normal/icon mode operation

9.6 Direct mode

When DM = 0, the chip is not in direct mode. Either the internal voltage generator or an external voltage may be used to achieve the necessary V LCD value. When DM = 1, the chip is in direct mode. The internal voltage generator is turned off and the VLCD output is directly connected to the HVgen supply voltage VDD2 . The direct mode can be used to reduce the current consumption when the required VLCD output voltage is close to the VDD2 supply voltage. This can be the case in icon mode or in Mux 1:9 (depending on LCD liquid properties).

9.7 Voltage multiplier control

S[1:0} A software configurable voltage multiplier is incorporated and can be set via the “Set HVgen stages” command. The voltage multiplier control can be used to reduce current consumption by disconnecting internal voltage multiplier stages (depending on the required V LCD output voltage).

9.8 Screen configuration

L: default is L = 0. L = 0: the two halves of a split screen are connected in a standard way i.e. column 1/81, 2/82 to 80/160. L = 1: the two halves of a split screen are connected in a mirrored way i.e. column 1/160, 2/159 to 80/81. This allows single layer PCB or glass layout.

9.9 Display configuration

P, Q: default is P, Q = 0. P = 1: mirrors the column data. Q = 1: mirrors the row data. IM CONDITION V LCD 0 character mode generates V A 1 icon mode generates V B

9.10 TC1 and TC2

Default is TC1 and TC2 = 0. This selects the default temperature coefficient for the internally generated VLCD . TC1 and TC2 = 10, 01 and 11 selects alternative temperature coefficients 1, 2 and 3 respectively.

9.11 Set V

The VLCD value is programmed by instruction. Two on-chip registers hold VLCD values for the character mode and the icon mode respectively (VA and VB). The generated VLCD value is independent of VDD , allowing battery operation of the chip. VLCD programming: 1. Send ‘function set’ instruction with H = 1 2. Send ‘set V LCD ’ instruction to write to voltage register: a) DB7, DB6 = 10: DB5 to DB0 are VLCD of character mode (VA) b) DB7, DB6 = 11: DB5 to DB0 are VLCD of icon mode (VB) c) DB5 to DB0 = 000000 switches VLCD generator off (when selected) d) During ‘display off’ and power-down the VLCD generator is also disabled. 3. Send ‘function set’ instruction with H = 0 to resume normal programming.

9.12 Reducing current consumption

Reducing current consumption can be achieved by one of the options given in Table 11. When V LCD lies outside the VDD range and must be generated, it is usually more efficient to use the on-chip generator than an external regulator. Table 11Reducing current consumption Table 12Use of the V A and VB registers ORIGINAL MODE ALTERNATIVE MODE Character mode Icon mode (control bit IM) Display on Display off (control bit D) HV generator operating Direct mode Any mode Power-down (PD pad) MODE V A VB Normal operation VLCD character mode VLCD icon mode

1. August 2000 30 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2

10 INTERFACES TO MPU

10.1 Parallel interface

The PCF2119x can send data in either two 4-bit operations or one 8-bit operation and can thus interface to 4-bit or 8-bit microcontrollers. In 8-bit mode data is transferred as 8-bit bytes using the 8 data lines DB7 to DB0. Three further control lines E, RS and R/ W are required; see Section 6.1. In 4-bit mode data is transferred in two cycles of 4 bits each using pads DB7 to DB4 for the transaction. The higher order bits (corresponding to DB7 to DB4 in 8-bit mode) are sent in the first cycle and the lower order bits (DB3 to DB0 in 8-bit mode) in the second. Data transfer is complete after two 4-bit data transfers. It should be noted that two cycles are also required for the busy flag check. 4-bit operation is selected by instruction, see Figs 14 to 16 for examples of bus protocol. In 4-bit mode, pads DB3 to DB0 must be left open-circuit. They are pulled up to V DD internally.

10.2 I2C-bus interface

The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are the Serial Data line (SDA) and the Serial Clock Line (SCL). Both lines must be connected to a positive supply via pull-up resistors. Data transfer may be initiated only when the bus is not busy. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH level signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. 10.2.1 I 2C-BUS PROTOCOL Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The addressing is always carried out with the first byte transmitted after the START procedure. The I 2C-bus configuration for the different PCF2119x read and write cycles is shown in Figs 22 to 24. The slow down feature of the I 2C-bus protocol (receiver holds SCL LOW during internal operations) is not used in the PCF2119x. 10.2.2 D EFINITIONS

• Transmitter: the device which sends the data to the bus
• Receiver: the device which receives the data from the bus
• Master: the device which initiates a transfer, generates clock signals and terminates a transfer
• Slave: the device addressed by a master
• Multi-master: more than one master can attempt to control the bus at the same time without corrupting the message
• Arbitration: procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to do so and the message is not corrupted
• Synchronization: procedure to synchronize the clock signals of two or more devices. Fig.18 System configuration. MGA807 SDA SCL MASTER TRANSMITTER/ RECEIVER MASTER TRANSMITTER SLAVE TRANSMITTER/ RECEIVER SLAVE RECEIVER MASTER TRANSMITTER/ RECEIVER

1. August 2000 31 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2 Fig.19 Bit transfer. handbook, full pagewidth MBC621 data line stable; data valid change of data allowed SDA SCL Fig.20 Definition of START and STOP conditions. handbook, full pagewidth MBC622 SDA SCL P STOP condition SDA SCL S START condition Fig.21 Acknowledgement on the I2C-bus. handbook, full pagewidth MBC602 S START condition 9821 clock pulse for acknowledgement not acknowledge acknowledge DATA OUTPUT BY TRANSMITTER DATA OUTPUT BY RECEIVER SCL FROM MASTER

1. August 2000 32 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... handbook, full pagewidth MGK899 S A S P011101 0A slave address CONTROL BYTE A1 Co DATA BYTE A CONTROL BYTE A R/W Co update data pointer 1 byte n ≥ 0 bytes2n ≥ 0 bytes DATA BYTE A acknowledgement from PCF2119x RS RS S A 011101 0 PCF2119x slave address R/W Fig.22 Master transmits to slave receiver; write mode.

1. August 2000 33 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Fig.23 Master reads after setting word address; writes word address, set RS; ‘read data’. (1) Last data byte is a dummy byte (may be omitted). th MGG003 S A S 011101 0 A slave address CONTROL BYTE A1 Co DATA BYTE A CONTROL BYTE A R/W Co Co update data pointer update data pointer 1 byte n ‡ 0 bytes n bytes last byte 2n 0 bytes DATA BYTE (1) A acknowledgement S A S 1A DATA BYTE A 1 P SLAVE ADDRESS DATA BYTE acknowledgement acknowledgement no acknowledgement R/W RS RS

1. August 2000 34 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2 Fig.24 Master reads slave immediately after first byte; read mode (RS previously defined). dbook, full pagewidth MGG004 Co update data pointer update data pointer n bytes last byte S A S 1A DATA BYTE A 1 P SLAVE ADDRESS DATA BYTE acknowledgement from PCF2113x acknowledgement from master no acknowledgement from master R/W Fig.25 I2C-bus timing diagram. dbook, full pagewidth SDA MGA728 SDA SCL tSU;STA tSU;STO tHD;STA tBUF tLOW tHD;DAT tHIGHtr tf tSU;DAT

1. August 2000 35 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2

11 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

12 HANDLING

Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices (see“Handling MOS Devices”). SYMBOL PARAMETER MIN. MAX. UNIT VDD1 Logic supply voltage −0.5 +6.5 V VDD2,3 High voltage generator supply voltages −0.5 +4.5 V VLCD LCD supply voltage −0.5 +7.5 V VI(VDD) / VO(VDD) input/output voltage (any VDD related input/output) −0.5 V DD + 0.5 V VI(VLCD) / VO(VLCD) input/output voltage (any VLCD related input/output)−0.5 V LCD + 0.5 V II DC input current −10 +10 mA IO DC output current −10 +10 mA IDD , ISS and ILCD VDD1,2,3, VSS1,2 or VLCD current −50 +50 mA VHMB electrostatic handling voltage according Human Body Model (C=100pF, R=1.5kOhm) 1.8 kV VMM electrostatic handling voltage according Machine Model(c=200pF, L=0.75uH) 150 V Ptot total power dissipation − 400 mW PO power dissipation per output − 100 mW Tstg storage temperature −65 +150 °C

1. August 2000 36 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2

13 DC CHARACTERISTICS

specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDD1 Logic supply voltage 1.5 − 5.5 V VDD2,3 High voltage generator supply voltages internal VLCD generation (VDD2,3 < VLCD ) 2.2 − 4.0 V VLCD LCD supply voltage 2.2 − 6.5 V ISS ground supply current external V LCD ; note 1 ISS1 ground supply current 1 − 70 120 µA ISS3 ground supply current 3 V DD =3V ; VLCD = 5 V; note 2− 35 80 µA ISS4 ground supply current 4 icon mode; V DD =3V ; VLCD = 2.5 V; note 2 − 25 45 µA ISS5 ground supply current 5 power-down mode; V DD =3V ; VLCD = 2.5 V; DB7 to DB0, RS and R/W = 1; OSC = 0; PD = 1 − 0.5 5 µA ISS ground supply current internal V LCD ; note 1and 3 ISS6 ground supply current 6 − 190 400 µA ISS8 ground supply current 8 V DD =3V ; VLCD = 5 V; note 2− 135 400 µA ISS9 ground supply current 9 icon mode; V DD = 2.5 V; VLCD = 2.5 V; note 2 − 85 −µ A Logic VIL LOW-level input voltage V SS1 − 0.3VDD1 V VIH HIGH-level input voltage 0.7V DD1 − VDD1 V VIL(osc) LOW-level input voltage pad OSC VDD = VDDmin , VDDmax VSS1 − VDD1 − 1.2 V VIH(osc) HIGH-level voltage pad OSC V DD = VDDmin , VDDmax VDD1 − 0.1 − VDD1 V IOL(DB) LOW-level output current pads DB7 to DB0 VOL = 0.4 V; VDD1 = 5 V 1.6 4 − mA IOH(DB) HIGH-level output current pads DB7 to DB0 VOH =4V ; VDD1 =5V −1 −8 − mA Ipu pull-up current pads DB7 to DB0 VI=V SS1 , VDDmin , VDDmax 0.04 0.15 1 µA IL leakage current V I=V DD1,2,3 or VSS1,2 −1 − +1 µA

1. August 2000 37 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2 Notes 1. LCD outputs are open-circuit; inputs at VDD or VSS ; bus inactive. 2. Tamb =2 5°C; fOSC = 200 kHz. 3. LCD outputs are open-circuit; HV generator is on; load current IVLCD (at VLCD )=5 µA. 4. Resistance of output terminals (R1 to R18 and C1 to C80) with a load current of 10µA; outputs measured one at a time; external VLCD ; VLCD = 3 V, VDD1,2,3 = 3 V. 5. LCD outputs open-circuit; external VLCD . I2C-bus SDA AND SCL VIL2 LOW-level input voltage 0 − 0.3VDD V VIH2 HIGH-level input voltage 0.7V DD − 5.5 V ILI input leakage current V I=V DD or VSS −1 − +1 µA C i input capacitance − 5- p F IOL (SDA) low-level output current SDA V OL = 0.4 V ; VDD > 2V V OL = 0.2VDD ; VDD < 2V mA mA LCD outputs R O(ROW) row output resistance pads R1 to R18 note 4 − 10 30 k Ω R O(COL) column output resistance pads C1 to C80 note 4 − 15 40 k Ω Vbias(tol) bias tolerance pads R1 to R18 and C1 to C80 note 5 − 20 130 mV VVLCD(tol) VLCD tolerance T amb =2 5°C; note 3 VLCD <3V −− 160 mV VLCD <4V −− 200 mV VLCD <5V −− 260 mV VLCD <6V −− 340 mV TC0 V LCD temperature coefficient 0 −− 0.16 − %/K TC1 V LCD temperature coefficient 1 −− 0.18 − %/K TC2 V LCD temperature coefficient 2 −− 0.21 − %/K TC3 V LCD temperature coefficient 3 −− 0.24 − %/K SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1. August 2000 38 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2

14 AC CHARACTERISTICS

1. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD . 2. C B = total capacitance of one bus line in pF. 3. Tested on a sample basis. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT fFR LCD frame frequency (internal clock) V DD = 5.0 V 45 95 147 Hz fOSC oscillator frequency (not available at any pad) 140 250 450 kHz fOSC(ext) external clock frequency 140 − 450 kHz tOSCST oscillator start-up time after power-down note 3 − 200 300 µs tW(R,PD) reset and power down high level pulse width 1 us tSW(R,PD) tolerable spike width on PD and Reset pads 90 ns Bus timing characteristics: parallel interface;note 1 W RITE OPERATION (WRITING DATA FROM MPU TO PCF2119 X) Tcy(en) enable cycle time 500 −− ns tW(en) enable pulse width 220 −− ns tsu(A) address set-up time 50 −− ns th(A) address hold time 25 −− ns tsu(D) data set-up time 60 −− ns th(D) data hold time 25 −− ns R EAD OPERATION (READING DATA FROM PCF2119 XT O MPU) Tcy(en) enable cycle time 500 −− ns tW(en) enable pulse width 220 −− ns tsu(A) address set-up time 50 −− ns th(A) address hold time 25 −− ns td(D) data delay time V DD1 > 2.2 V −− 150 ns VDD1 > 1.5 V −− 250 ns th(D) data hold time 5 − 100 ns Timing characteristics: I2C-bus interface;note 1 fSCL SCL clock frequency −− 400 kHz tLOW SCL clock low period 1.3 −−µ s tHIGH SCL clock high period 0.6 −−µ s tSU;DAT data set-up time 100 −− ns tHD;DAT data hold time 0 −− ns tr SCL, SDA rise time note 2, 3 15 + 0.1 CB − 300 ns tf SCL, SDA fall time note 2, 3 15 + 0.1 C B − 300 ns C B capacitive bus line load −− 400 pF tSU;STA set-up time for a repeated START condition 0.6 −−µ s tHD;STA START condition hold time 0.6 −−µ s tSU;STO set-up time for STOP condition 0.6 −−µ s tSW tolerable spike width on bus −− 50 ns tBUF Bus free time between STOP and START condition 1.3 us

1. August 2000 39 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2

15 TIMING CHARACTERISTICS

Fig.26 Parallel bus write operation sequence; writing data from MPU to PCF2119x. handbook, full pagewidth RS E DB0 to DB7 V V V V V V V V V V V V V T IH1 IL1 IH1 IL1 IH1 IL1 IL1 IL1 IH1 IL1 IH1 IL1VIL1 VIH1 IL1 cy(en) tsu(D) h(D)t tW(en) th(A) th(A)tsu(A) valid data MBK474 R/W Fig.27 Parallel bus read operation sequence; reading data from PCF2119x to MPU. handbook, full pagewidth RS R/W E DB0 to DB7 V V V V V V V V V V IH1 IL1 IH1 IL1 IH1 IL1 IH1 IL1 VOL1 VOH1 IL1 Tcy(en) h(D)t tW(en) th(A) th(A)tsu(A) IH1 VOL1 VOH1 td(D) VIH1 MBK475

1. August 2000 40 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2

16 APPLICATION INFORMATION

16.1 General application information

The required minimum value for the external capacitors in an application with the PCF2119x-2 are: C ext for VLCD /VSS1,2 = min. 100nF, for VDD1,2,3 / VSS1,2 = 470nF. Higher capacitor values are recommended for ripple reduction. For COG applications the recommended ITO track resistance is to be minimized for the I/O and supply connections. Optimized values for these tracks are below 50 Ohm for the supply and below 100 Ohm for the I/O connections. Higher track resistance reduces performance and increase current consumption. To avoid accidental triggering of power-on reset (especially in COG applications), the supplies must be adequately decoupled. Depending on power supply quality, V DD1 may have to be rised above the specified minimum. Fig.28 Direct connection to 8-bit MPU; 8-bit bus. handbook, full pagewidth PCF2119x MGK895 P80CL51 2 × 16 CHARACTER LCD DISPLAY PLUS 160 ICONS16 C1 to C80 80 2RSP20 P21 EP22 DB7 to DB0P17 to P10 R17, R18 R1 to R16 R/W Fig.29 Direct connection to 8-bit MPU; 4-bit bus. handbook, full pagewidth PCF2119x MGK896 P80CL51 2 × 16 CHARACTER LCD DISPLAY PLUS 160 ICONS16 C1 to C80 80 2RSP10 P11 EP12 DB7 to DB4P17 to P14 R17, R18 R1 to R16 R/W

1. August 2000 41 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2 Fig.30 Typical application using parallel interface. handbook, full pagewidth MGK897 PCF2119x 2 × 16 CHARACTER LCD DISPLAY PLUS 160 ICONS16 C1 to C80 80 2OSC RSDB7 to DB0 E 100 nF 100 nF R17, R18 R1 to R16 VDD VSS VDD VLCD VSS R/W Fig.31 Application using I2C-bus interface. handbook, full pagewidth VDDVDD SCL SDA MASTER TRANSMITTER PCF84C81A; P80CL410 PCF2119x 2 × 16 CHARACTER LCD DISPLAY PLUS 160 ICONS16 C1 to C80 80 2OSC SCL SDA DB3/SAO 100 nF 100 nF R17, R18 R1 to R16 VDD VDD VSS VDD VLCD VSS PCF2119x 1 × 32 CHARACTER LCD DISPLAY PLUS 160 ICONS16 C1 to C80 80 2OSC SCL SDA DB3/SAO 100 nF 100 nF R17, R18 R1 to R16 VSS VDD VSS VDD VLCD VSS MGK898

1. August 2000 42 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2

16.2 Charge pump characteristic

In Fig. 32 - 34 typical graphs of the total power consumption of the PCF2119-2 using the internal charge pump are given. They are obtained under the following conditions :

• ambient temperature 25C
• VDD1 = VDD2 = VDD3 = 2.2 (min), 2.7 (typ), 4V (max)
• normal mode
• Fosc = internal oscillator
• MUX 1:18
• typical load current IVLCD = 10 uA For each multiplication factor there is a separate line. A line ends where it is not possible to get a higher voltage under its conditions (a higher multiplication factor is needed to get higher voltages). Connecting different displays may result in different current consumptions. This affects the efficiency and the optimal multiplication factor to be used to generate a certain output voltage. Fig.32 Typical charge pump characteristic for VDD = 2.2 V. 2 x 3 x 4 x Vop [V]

1. August 2000 43 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2 Fig.33 Typical charge pump characteristic for VDD = 2.7 V. 2 x 3 x 4 x Vop [V] Fig.34 Typical charge pump characteristic for VDD = 4 V. 2 x 3 x 4 x Vop [V]

1. August 2000 44 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2 16.3 8-bit operation, 1-line display using external reset Table 14 shows an example of a 1-line display in 8-bit operation. The PCF2119x functions must be set by the ‘function set’ instruction prior to display. Since the DDRAM can store data for 80 characters, the RAM can be used for advertising displays when combined with display shift operation. Since the display shift operation changes display position only and the DDRAM contents remain unchanged, display data entered first can be displayed when the ‘return home’ operation is performed. 16.4 4-bit operation, 1-line display using external reset The program must set functions prior to a 4-bit operation, see Table 13. When power is turned on, 8-bit operation is automatically selected and the PCF2119x attempts to perform the first write as an 8-bit operation. Since nothing is connected to DB0 to DB3, a rewrite is then required. However, since one operation is completed in two accesses of 4-bit operation, a rewrite is required to set the functions (see Table 13 step 3). Thus, DB4 to DB7 of the ‘function set’ are written twice. 16.5 8-bit operation, 2-line display For a 2-line display, the cursor automatically moves from the first to the second line after the 40th digit of the first line has been written. Thus, if there are only 8 characters in the first line, the DDRAM address must be set after the 8th character is completed (see Table 6). It should be noted that both lines of the display are always shifted together; data does not shift from one line to the other. 16.6 I 2C-bus operation, 1-line display A control byte is required with most commands (see Table 17). Table 134-bit operation, 1-line display example; using external reset STEP INSTRUCTION DISPLAY OPERATION 1 power supply on (PCF2119x is initialized by the external reset) initialized; no display appears 2 function set RS R/ W DB7 DB6 DB5 DB4 sets to 4-bit operation; in this instance operation is handled as 8-bits by initialization and only this instruction completes with one write 000010 3 function set 000010 sets to 4-bit operation, selects 1-line display and V LCD =V 0; 4-bit operation starts from this point and resetting is needed 000000 4 display on/off control 000000 _ turns on display and cursor; entire display is blank after initialization001110 5 entry mode set 000000 _ sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the DD/CGRAM; display is not shifted 000110 6 ‘write data’ to CGRAM/DDRAM

100101 P_ writes ‘P’; the DDRAM has already been selected

by initialization at power-on; the cursor is incremented by 1 and shifted to the right 100000

1. August 2000 45 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Table 148-bit operation, 1-line display example; using external reset (character set ‘A’) STEP INSTRUCTION DISPLAY OPERATION 1 power supply on (PCF2119x is initialized by the external reset) initialized; no display appears 2 function set RS R/ W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 sets to 8-bit operation, selects 1-line display and VLCD =V 00000110000 3 display mode on/off control 0000001110 _ turns on display and cursor; entire display is blank after initialization 4 entry mode set 0000000110 _ sets mode to increment the address by 1 and to shift the cursor to the right at the time of the write to the DD/CGRAM; display is not shifted 5 ‘write data’ to CGRAM/DDRAM

1001010000 P_ writes ‘P’; the DDRAM has already been selected by

initialization at power-on; the cursor is incremented by 1 and shifted to the right 6 ‘write data’ to CGRAM/DDRAM

1001001000 PH_ writes ‘H’

7t o1 1 | 12 ‘write data’ to CGRAM/DDRAM

1001010011 PHILIPS_ writes ‘S’

0000000111 PHILIPS_ sets mode for display shift at the time of write

14 ‘write data’ to CGRAM/DDRAM

1000100000 HILIPS _ writes space

15 ‘write data’ to CGRAM/DDRAM

1001001101 ILIPS M_ writes ‘M’

16 |

1. August 2000 46 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 17 ‘write data’ to CGRAM/DDRAM

1001001111 MICROKO writes ‘O’

0000010000 MICROK O shifts only the cursor position to the left

0000010000 MICRO KO shifts only the cursor position to the left

20 ‘write data’ to CGRAM/DDRAM

1001000011 ICROC O writes ‘C’ correction; the display moves to the left

0000011100 MICROCO shifts the display and cursor to the right

0000010100 MICROCO_ shifts only the cursor to the right

23 ‘write data’ to CGRAM/DDRAM

1001001101 ICROCOM_ writes ‘M’

24 | 25 return home 0000000010 PHILIPS M returns both display and cursor to the original position (address 0) STEP INSTRUCTION DISPLAY OPERATION

1. August 2000 47 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Table 158-bit operation, 1-line display and icon example; using external reset (character set ‘A’) STEP INTRODUCTION DISPLAY OPERATION 1 power supply on (PCF2119x is initialized by the external reset) initialized; no display appears 2 function set RS R/ W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 sets to 8-bit operation, selects 1-line display and VLCD =V 00000110000 3 display mode on/off control 0000001110 _ turns on display and cursor; entire display is blank after initialization 4 entry mode set 0000000110 _ sets mode to increment the address by 1 and to shift the cursor to the right at the time of the write to the DD/CGRAM; display is not shifted 5 set CGRAM address 0001000000 _ sets the CGRAM address to position of character 0; the CGRAM is selected 6 ‘write data’ to CGRAM/DDRAM 1000001010 _ writes data to CGRAM for icon even phase; icons appears 7 | 8 set CGRAM address 0001110000 _ sets the CGRAM address to position of character 4; the CGRAM is selected 9 ‘write data’ to CGRAM/DDRAM 1000001010 _ writes data to CGRAM for icon odd phase 10 | 11 function set 0000110001 _ sets H = 1 12 icon control 0000001010 _ icons blink 13 function set 0000110001 _ sets H = 0

1. August 2000 48 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 14 set DDRAM address 0 0 1 0 0 0 0 0 0 0 sets the DDRAM address to the first position; DDRAM is selected 15 ‘write data’ to CGRAM/DDRAM

1001010000 P_ writes ‘P’; the cursor is incremented by 1 and shifted to the

16 ‘write data’ to CGRAM/DDRAM 17 to 20 | 21 return home

0000000010 PHILIPS returns both display and cursor to the original position

(address 0) STEP INTRODUCTION DISPLAY OPERATION

1. August 2000 49 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Table 168-bit operation, 2-line display example; using external reset STEP INTRODUCTION DISPLAY OPERATION 1 power supply on (PCF2119x is initialized by the external reset) initialized; no display appears 2 function set RS R/ W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 sets to 8-bit operation; selects 2-line display and voltage generator off0000110100 3 display on/off control 0000001110 _ turns on display and cursor; entire display is blank after initialization 4 entry mode set 0000000110 _ sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the CG/DDRAM; display is not shifted 5 ‘write data’ to CGRAM/DDRAM

initialization at power-on; the cursor is incremented by 1 and shifted to the right 6t o1 0 | 11 ‘write data’ to CGRAM/DDRAM

0011000000 PHILIPS

sets DDRAM address to position the cursor at the head of the 2nd line 13 ‘write data’ to CGRAM/ DDRAM

1001001101 PHILIPS

writes ‘M’ 14 to 19 |

1. August 2000 50 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 20 ‘write data’ to CGRAM/DDRAM

1001001111 PHILIPS

MICROCO_ writes ‘O’ 21 ‘write data’ to CGRAM/DDRAM

0000000111 PHILIPS

MICROCO_ sets mode for display shift at the time of write 22 ‘write data’ to CGRAM/DDRAM

1001001101 HILIPS

ICROCOM_ writes ‘M’; display is shifted to the left; the first and second lines shift together 23 | 24 return home

0000000010 PHILIPS

returns both display and cursor to the original position (address 0) STEP INTRODUCTION DISPLAY OPERATION

1. August 2000 51 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Table 17Example of I2C-bus operation; 1-line display (using external reset, assuming SA0 = VSS ; note 1) STEP I 2C BYTE DISPLAY OPERATION 1I 2C-bus start initialized; no display appears 2 slave address for write SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/ W Ack during the acknowledge cycle SDA will be pulled-down by the PCF2119x011101001 3 send a control byte for ‘function set’ Co RS 0 0 0 0 0 0 Ack control byte sets RS for following data bytes 000000001 4 function set DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack selects 1-line display and V LCD =V 0; SCL pulse during acknowledge cycle starts execution of instruction001X00001 5 display on/off control DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack _ turns on display and cursor; entire display shows character 20H (blank in ASCII-like character sets)000011101 6 entry mode set DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack _ sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the DDRAM or CGRAM; display is not shifted 000001101 2C start _ for writing data to DDRAM, RS must be set to 1; therefore a control byte is needed 8 slave address for write SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/ W Ack _ 011101001 9 send a control byte for ‘write data’ Co RS 0 0 0 0 0 0 Ack _ 010000001 10 ‘write data’ to DDRAM DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack P_ writes ‘P’; the DDRAM has been selected at power-up; the cursor is incremented by 1 and shifted to the right010100001 11 ‘write data’ to DDRAM DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack PH_ writes ‘H’ 010010001

1. August 2000 52 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 12 to 15 | 16 ‘write data’ to DDRAM DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack PHILIPS_ writes ‘S’ 010100111 17 (optional I 2C stop) I2C start + slave address for write (as step 8) PHILIPS_ 18 control byte Co RS 0 0 0 0 0 0 Ack PHILIPS_ 100000001 19 return home DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack PHILIPS sets DDRAM address 0 in address counter (also returns shifted display to original position; DDRAM contents unchanged); this instruction does not update the Data Register (DR) 000000101 20 I 2C start PHILIPS 21 slave address for read SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/ W Ack PHILIPS during the acknowledge cycle the content of the DR is loaded into the internal I2C-bus interface to be shifted out; in the previous instruction neither a ‘set address’ nor a ‘read data’ has been performed; therefore the content of the DR was unknown; the R/W has to be set to 1 while still in I 2C-write mode 011101011 22 control byte for read Co RS 0 0 0 0 0 0 Ack PHILIPS DDRAM content will be read from following instructions 011000001 23 ‘read data’: 8× SCL + master acknowledge; note 2 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack PH ILIPS 8 × SCL; content loaded into interface during previous acknowledge cycle is shifted out over SDA; MSB is DB7; during master acknowledge content of DDRAM address 01 is loaded into the I 2C-bus interface XXXXXXXX0 STEP I 2C BYTE DISPLAY OPERATION

1. August 2000 53 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Notes 1. X = don’t care. 2. SDA is left at high-impedance by the microcontroller during the read acknowledge. 24 ‘read data’: 8× SCL + master acknowledge; note 2 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack PHI LIPS 8 × SCL; code of letter ‘H’ is read first; during master acknowledge code of ‘I’ is loaded into the I2C interface010010000 25 ‘read data’: 8× SCL + no master acknowledge; note 2 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack PHILIPS no master acknowledge; after the content of the I2C-bus interface register is shifted out no internal action is performed; no new data is loaded to the interface register, data register is not updated, address counter is not incremented and cursor is not shifted 010010011 26 I 2C stop PHILIPS STEP I 2C BYTE DISPLAY OPERATION

1. August 2000 54 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Table 18Initialization by instruction, 8-bit interface (note 1) Note 1. X = don’t care. STEP DESCRIPTION power-on or unknown state wait 2 ms after external reset has been applied RS R/ W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BF cannot be checked before this instruction 0 0 0 0 1 1 X X X X function set (interface is 8 bits long) wait 2 ms RS R/ W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BF cannot be checked before this instruction 0 0 0 0 1 1 X X X X function set (interface is 8 bits long) wait more than 40µs RS R/ W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BF cannot be checked before this instruction 0 0 0 0 1 1 X X X X function set (interface is 8 bits long) BF can be checked after the following instructions; when BF is not checked, the waiting time between instructions is the specified instruction time (see Table 3) RS R/ W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 function set (interface is 8 bits long); specify the number of display lines 0000110M 0H 0 0 0 0 0 0 1 0 0 0 display off 0 0 0 0 0 0 0 0 0 1 clear display 0 0 0 0 0 0 0 1 I/D S entry mode set Initialization ends

1. August 2000 55 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Table 19Initialization by instruction, 4-bit interface; not applicable for I2C-bus operation STEP DESCRIPTION power-on or unknown state Wait 2 ms after external reset has been applied RS R/ W DB7 DB6 DB5 DB4 BF cannot be checked before this instruction 000011 function set (interface is 8 bits long) Wait 2 ms RS R/ W DB7 DB6 DB5 DB4 BF cannot be checked before this instruction 000011 function set (interface is 8 bits long) Wait 40µs RS R/ W DB7 DB6 DB5 DB4 BF cannot be checked before this instruction 000011 function set (interface is 8 bits long) | BF can be checked after the following instructions; when BF is not checked, the waiting time between instructions is the specified instruction time (see Table 3) RS R/ W DB7 DB6 DB5 DB4 function set (set interface to 4 bits long) 000010 interface is 8 bits long 000010 function set (interface is 4 bits long) 0 0 0 M 0 H specify number of display lines 000000 001000 display off 000000 clear display 000001 000000 entry mode set

0001 I / D S

1. August 2000 56 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2

17 DEVICE PROTECTION DIAGRAM

LCD-O/’P’S PROTECTION OF HV SUPPLIES AND I/O’S I2C PADS CONTROL-PINS PROTECTION OF I/O’S VSS2 VSS1 VDD1 VSS1 VDD2 VSS2 VDD3 VSS1 VLCDSENSE, VLCD2, VLCD1 VSS1 VLCDIN VSS1 VDD1 VSS1 VDD1 VSS1 E, T1, T2, T3, POR, PD RW, RS, DB0-DB7, OSC Fig.35 ESD protection diagram

1. August 2000 57 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2

18 BONDING PAD LOCATIONS

Fig.36 Bonding pad locations. X Y 168 167 166 165 164 163 162 161 160 159 158 157 156 155 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 152 151 153 154 dummy (Vss1) ROW15 ROW14 ROW13 ROW12 ROW11 ROW10 COL2 COL3 COL4 COL5 COL6 COL7 COL8 COL9 COL10 COL11 COL12 COL13 COL14 COL17 COL18 COL19 COL20 COL21 COL22 COL23 COL24 COL25 COL26 COL27 COL28 COL29 COL30 COL31 COL32 COL33 COL34 COL35 COL36 COL37 COL38 COL39 COL42 COL43 COL44 COL45 COL46 COL47 COL48 COL49 COL50 COL51 COL52 COL53 COL54 COL55 COL56 COL57 COL58 COL59 COL60 COL61 COL62 COL63 COL64 COL67 COL68 COL69 COL70 COL71 COL72 COL73 COL74 COL75 COL76 COL77 COL78 COL79 ROW2 ROW3 ROW4 ROW5 ROW6 ROW7 SCL POR PD SDA SDA RW RS DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 OSC VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD2 VDD3 VDD3 VDD3 VDD3 E VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS1 VSS2 VSS2 VSS2 VSS2 VSS2 VLCDout VLCDout VLCDout VLCDout VLCDout VLCDout VLCDout VLCDin VLCDin VLCDin VLCDin VLCDin VSS2 VLCDsense VLCDindummy (Vss1) VSS1 ROW16 ROW1 ROW9 ROW8 ROW17 ROW17 Repeated COL80 COL66 COL65 COL41 COL40 COL16 COL15 ROW18 COL1 PC2119-2 SCL PC2119-2 Chip size : 1.81 mm x 7.64 mm

1. August 2000 58 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2 Fig.37 Tray details. handbook, full pagewidth MGR977 A 1,1 1,2 2,1 3,1 x,1 x,y1,y 2,2 1,3 E x y F D B Fig.38 Tray alignment. The orientation of the IC in a pocket is indicated by the position of the IC type name on the die surface with respect to the chamfer on the upper left corner of the tray. Refer to the bonding pad location diagram for the orientating and position of the type name on the die surface. MGR978 handbook, halfpage PCF2119-1 PC2119-2 Table 20Dimensions for Fig.37 DIM. DESCRIPTION VALUE A pocket pitch, x direction 10.16 mm B pocket pitch, y direction 4.45 mm C pocket width, x direction 7.74 mm D pocket width, y direction 1.91 mm E tray width, x direction 50.8 mm F tray width, y direction 50.8 mm x number of pockets in x direction y number of pockets in y direction

1. August 2000 59 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2 Table 21Bonding pad locations Dimensions inµm; all x/y coordinates are referenced to centre of chip; see Fig.36 SYMBOL PAD x y VDD1 1 745 - 274 VDD1 2 745 − 204 VDD1 3 745 - 134 VDD1 4 745 - 64 VDD1 5 745 6 VDD1 6 745 76 VDD2 7 745 146 VDD2 8 745 216 VDD2 9 745 286 VDD2 10 745 356 VDD2 11 745 426 VDD2 12 745 496 VDD2 13 745 566 VDD2 14 745 636 VDD3 15 745 706 VDD3 16 745 776 VDD3 17 745 846 VDD3 18 745 916 E 19 745 986 T1 20 745 1196 T2 21 745 1406 V SS1 22 745 1616 VSS1 23 745 1686 VSS1 24 745 1756 VSS1 25 745 1826 VSS1 26 745 1896 VSS1 27 745 1966 VSS1 28 745 2036 VSS1 29 745 2106 VSS2 30 745 2176 VSS2 31 745 2246 VSS2 32 745 2316 VSS2 33 745 2386 VSS2 34 745 2456 VSS2 35 745 2666 VLCDSENSE 36 745 2736 VLCD2 37 745 2806 VLCD2 38 745 2876 VLCD2 39 745 2946 VLCD2 40 745 3016 VLCD2 41 745 3086 VLCD2 42 745 3156 VLCD2 43 745 3226 VLCD1 44 745 3296 VLCD1 45 745 3366 VLCD1 46 745 3436 VLCD1 47 745 3506 VLCD1 48 745 3576 VLCD1 49 745 3646 Dummy (V SS1 ) 50 - 745 3576 R8 51 - 745 3506 R7 52 - 745 3436 R6 53 - 745 3366 R5 54 - 745 3296 R4 55 - 745 3226 R3 56 - 745 3156 R2 57 - 745 3086 R1 58 - 745 3016 R17 59 - 745 2946 C80 60 - 745 2876 C79 61 - 745 2806 C78 62 - 745 2736 C77 63 - 745 2666 C76 64 - 745 2596 C75 65 - 745 2526 C74 66 - 745 2456 C73 67 - 745 2386 C72 68 - 745 2316 C71 69 - 745 2246 C70 70 - 745 2176 C69 71 - 745 2106 C68 72 - 745 2036 C67 73 - 745 1966 C66 74 - 745 1896 C65 75 - 745 1756 C64 76 - 745 1686 C63 77 - 745 1616 C62 78 - 745 1546 C61 79 - 745 1476 C60 80 - 745 1406 C59 81 - 745 1336 C58 82 - 745 1266 C57 83 - 745 1196 C56 84 - 745 1126 C55 85 - 745 1056 C54 86 - 745 986 C53 87 - 745 916 C52 88 - 745 846 C51 89 - 745 776 C50 90 - 745 706 SYMBOL PAD x y

1. August 2000 60 Philips Semiconductors Product specification LCD controllers/drivers PCF2119x-2 C49 91 - 745 636 C48 92 - 745 566 C47 93 - 745 496 C46 94 - 745 426 C45 95 - 745 356 C44 96 - 745 286 C43 97 - 745 216 C42 98 - 745 146 C41 99 - 745 76 R17DUP 100 - 745 6 C40 101 - 745 - 64 C39 102 - 745 - 134 C38 103 - 745 - 204 C37 104 - 745 - 274 C36 105 - 745 - 344 C35 106 - 745 - 414 C34 107 - 745 - 484 C33 108 - 745 - 554 C32 109 - 745 - 624 C31 110 - 745 - 694 C30 111 - 745 - 764 C29 112 - 745 - 834 C28 113 - 745 - 904 C27 114 - 745 - 974 C26 115 - 745 - 1044 C25 116 - 745 - 1114 C24 117 - 745 - 1184 C23 118 - 745 - 1254 C22 119 - 745 - 1324 C21 120 - 745 - 1394 C20 121 - 745 - 1464 C19 122 - 745 - 1534 C18 123 - 745 - 1604 C17 124 - 745 - 1674 C16 125 - 745 - 1744 C15 126 - 745 - 1884 C14 127 - 745 - 1954 C13 128 - 745 - 2024 C12 129 - 745 - 2094 C11 130 - 745 - 2164 C10 131 - 745 - 2234 C9 132 - 745 - 2304 C8 133 - 745 - 2374 C7 134 - 745 - 2444 C6 135 - 745 - 2514 C5 136 - 745 - 2584 C4 137 - 745 - 2654 C3 138 - 745 - 2724 C2 139 - 745 - 2794 SYMBOL PAD x y Table 22Bump size C1 140 - 745 - 2864 R18 141 - 745 - 2934 R9 142 - 745 - 3004 R10 143 - 745 - 3074 R11 144 - 745 - 3144 R12 145 - 745 - 3214 R13 146 - 745 - 3284 R14 147 - 745 - 3354 R15 148 - 745 - 3424 R16 149 - 745 - 3494 Dummy (V SS1 ) 150 - 745 - 3704 SCL 151 745 - 3704 SCL 152 745 - 3634 T3 153 745 - 3494 POR 154 745 - 3424 PD 155 745 - 3214 SDA 156 745 - 3004 SDA 157 745 - 2934 W 158 745 - 2584 RS 159 745 - 2374 DB0 160 745 - 2164 DB1 161 745 - 1954 DB2 162 745 - 1744 DB3 / SA0 163 745 - 1534 DB4 164 745 - 1324 DB5 165 745 - 1114 DB6 166 745 - 904 DB7 167 745 - 694 OSC 168 745 - 484 Rec. Pat. 1 169 745 - 2689 Rec. Pat. 2 169 745 2561 Rec. Pat. 3 169 -745 3681 Rec. Pat. 4 170 -745 - 3599 PARAMETER VALUE UNIT Type galvanic pure Au − Bump width 50 ±6 µm Bump length 90 ±6 µm Bump height 17.5 ±5 µm Height difference in one die <2 µm Convex deformation <5 µm Pad size, aluminium 62 × 100 µm Passivation opening CBB 36× 76 µm Wafer thickness 380 ±25 µm SYMBOL PAD x y