Power Management

PC13892VK/R2

Freescale Semiconductor...

Power Management and User Interface IC

Manufacturer: Freescale Semiconductor...

Document: 75 Pages / 3Mb

Request Quote Download Datasheet Read online HTML view

More from Freescale Semiconductor... Browse P parts

Online Datasheet

Read PC13892VK/R2 online.

13892 FREESCALE | Alldatasheet

Document overview

Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 75

Technical content

Features

Battery charger system for wa ll charging and USB charging
10 bit ADC for monitoring battery and other inputs, plus a coulomb counter support module
4 adjustable output buck converters for direct supply of the processor core and memory
12 adjustable output LDOs with internal and external pass devices
2 boost converters for supply ing LCD backlight and RGB LEDs
Serial backlight drivers for displays and keypad, plus RGB LED drivers
Power control logic with proce ssor interface and event detection
Real time clock and crystal oscillat or circuitry, with coin cell backup and support for external secure real time clock on a companion system processor IC
Touch screen interface
SPI/I 2C bus interface for control and register access.
Two package offering in 7 x 7mm and 12 x 12mm.

Figure 1. 13892 Typical Operating Circuit

ORDERING INFORMATION

Range (TA) Package PC13892VK/R2* -30°C to 85°C 7x7 PC13892VL/R2* 12x12 PC13892JVK/R2 7x7 PC13892JVL/R2 12x12 * ITC effected products CALENDAR USB Li Ion Battery Adapter IRDA Camera AP Aud& Pwr Mgmt TV Out Camera MC13892 Power Mgmt & User Interface i.MX51 Apps Processor NVR DRAM BT (+FM) Display Backlight SPI/I2C SSI UI RTC Touch Screen MMC APAud Audio IC Mic Inputs Stereo Loudspeakers Line In/Out UI Backlight Stereo headphones Light Sensor Thermistor Power Power Coin Cell Battery Charger LED RGB Color Indicators CALENDARCALENDAR USB Li Ion Battery Adapter IRDA Camera AP Aud& Pwr Mgmt TV Out Camera MC13892 Power Mgmt & User Interface i.MX51 Apps Processor NVR DRAM BT (+FM) Display Backlight SPI/I2C SSI UIUI RTC Touch Screen MMC APAud Audio IC Mic Inputs Stereo Loudspeakers Line In/Out UI Backlight Stereo headphones Light Sensor Thermistor Power Power Coin Cell Battery Charger LED RGB Color Indicators

2 Freescale Semiconductor

available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. Table 1. Device Variations

available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. Figure 2. 13892 Simplified Internal Block Diagram

4 Freescale Semiconductor

available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. Figure 3. 13892VK Pin Connections

available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. Figure 4. 13892VL Pin Connections Table 2. 13892 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 39.

6 Freescale Semiconductor

available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages.

Battery current sensing point 2
Battery supply voltage sense
Output to battery supplied accesories
Input supply to the IC core circuitry
Application supply voltage sense

Table 2. 13892 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 39.

available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages.

Charge current sensing point 2

A functional description of each pin can be found in the Functional Pin Description section beginning on page 39.

8 Freescale Semiconductor

available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. A functional description of each pin can be found in the Functional Pin Description section beginning on page 39.

available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages.

Input regulator camera using internal PMOS
Drive output regulator for camera voltage

A functional description of each pin can be found in the Functional Pin Description section beginning on page 39.

10 Freescale Semiconductor

available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages.

Drive VGEN3 output regulator

A functional description of each pin can be found in the Functional Pin Description section beginning on page 39.

Analog Integrated Circuit Device Data Freescale Semiconductor 11 13892

ELECTRICAL CHARACTERISTICS

USB Input Voltage applies to UVBUS pin only
ESD testing is performed in accordance with the Human Body Model (HBM) (C ZAP = 100 pF, RZAP = 1500 Ω), the Machine Model (MM)

(CZAP = 200 pF, RZAP = 0 Ω), and the Charge Device Model (CDM), Robotic (CZAP = 4.0 pF).

Pin soldering temperature limit is for 10 seconds maximum dura tion. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device.

Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow

and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.

Analog Integrated Circuit Device Data

12 Freescale Semiconductor

5 Regulators(6)

VPLL, VIOHI, VGEN2, VAUDIO, VVIDEO

Analog Integrated Circuit Device Data Freescale Semiconductor 13 13892 STATIC ELECTRICAL CHARACTERISTICS Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. Table 5. Static Electrical Characteristics (Continued) all other modes from BP = 3.6 V. External loads are not included.

Analog Integrated Circuit Device Data

14 Freescale Semiconductor

STATIC ELECTRICAL CHARACTERISTICS Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. BUCK CONVERTERS Operating Input Voltage PWM operation, 0 < IL < IMAX PFM operation, 0 < IL < IMAX Extended PWM or PFM operation(7) VSWIN 3.0 2.8 UVDET 4.65 4.65 4.65 V Output Voltage Range Switcher 1 Switchers 2, 3, and 4 VSW1 0.6 0.6 1.375 1.850 V Output Accuracy PWM mode including ripple, load regulation, and transients (8) PFM Mode, including ripple, load regulation, and transients VSWLOPP VSWLIPPI Nom-50 Nom-50 Nom Nom Nom+50 Nom+50 mV SW1-SW2 Output Delta Voltage SW1 and SW2 both programmed for 1.250 V, PWM mode, IL = 0.5*ILMAX ΔVSW - - 25 mV Maximum Continuous Load Current, IMAX, VINMIN<BP<4.65 V(11) SW1 in PWM mode with SWILIMB=0 with SWILIMB=1(10) SW2 in PWM mode SW3 in PWM mode SW4 in PWM mode SW1, SW2, SW3, SW4 in PFM mode ISW1 ISW2 ISW3 ISW4 ISW1, 2, 3, 4 900 1050 800 800 800 mA Current Limiter Peak Current Detection, VIN = 3.6 V, Current through inductor(9) SW1 SW2-4 ISWPK 920 850 1700 1700 mA Start-up Overshoot, IL = 0 - - 25 mV Effective Quiescent Current Consumption(11) PWM Mode, IL=0 mA; device not switching PFM Mode, IL=0 mA; device not switching ISWQS 100 µA Automatic Mode Change Threshold, Switchover between PFM and PWM modes AMCTH - 50 - mA Efficiency PFM, 0.9 V, 1.0 mA PFM, 01.8 V, 1.0 mA PWM Pulse Skipping, 1.25 V, 50 mA PWM Pulse Skipping, 1.8 V, 50 mA PWM, 1.25 V, 500 mA PWM, 1.8 V, 500 mA Notes 7. In the extended operating range the performance may be degraded 8. Transient loading for load steps of ILmax/2 9. No current limiter interaction for SW1 up to 920 mA and for SW2-4 up to 850 mA . 10. In this mode, current limit protection is disabl ed. Therefore, the load on SW1 should not exceed 1.05 A 11. Guaranteed by design. all other modes from BP = 3.6 V. External loads are not included.

Analog Integrated Circuit Device Data Freescale Semiconductor 15 13892 STATIC ELECTRICAL CHARACTERISTICS Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. BUCK CONVERTERS (CONTINUED) External Components, Used as a condition for all other parameters Inductor for SW2, SW3, SW4(11) Inductor for SW1(11) Inductor Resistance Bypass Capacitor for SW2, SW3, SW4(13) Bypass Capacitor for SW1(14) Bypass Capacitor ESR Input Capacitor(15) LSW234 LSW1 RWSW COSW234 COSW1 ESRSW -20% -20% -35% -35% 5.0 1.0 2.2 1.5 2x22 4.7 +20% +20% 0.16 +35% +35% µH µH Ω µF µF mΩ µF SWBST Average Output Voltage(16) 3.0 V < VIN < 4.65 (1), 0 < IL < ILMAX (17) VBST Nom-5% 5.0 Nom+5% V Output Ripple(11) 3.0 V < VIN < 4.65, 0 < IL < ILMAX, Excluding reverse recovery of Schottky diode VBSTPP - - 120 mVpp Average Load Regulation VIN = 3.6 V, 0 < IL < ILMAX VBSTLOR - - 0.5 mV/mA Average Line Regulation 3.0 V < VIN < 4.65 V, IL = ILMAX VBSTLIR - - 50 mV Notes 12. Preferred device TDK VLS252012 series at 2.5x2.0 mm footprint and 1.2 mm max height 13. Preferably 0603 style 6.3 V rated X5R/X7R type at 35% total make tolerance, temperature spread and DC bias derating such as TDK C1608X5R0J106M 14. Preferably 0805 style 6.3 V rated X5R/X7R type at 35% total make tolerance, temperature spread and DC bias derating such as TDK C2012X5R0J226M 15. Preferably 0603 style 6.3 V rated X5R/X7R type at 35% total make tolerance, temperature spread and DC bias derating such as TDK C1608X5R0J475 16. Output voltage when configured to supply VBUS in OTG mode can be as high as 5.75 V 17. Vin is the low side of the inductor that is connected to BP. all other modes from BP = 3.6 V. External loads are not included.

Analog Integrated Circuit Device Data

16 Freescale Semiconductor

STATIC ELECTRICAL CHARACTERISTICS Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. SWBST (CONTINUED) Maximum Continuous Load Current ILMAX 3.0 V < VIN < 4.65, VOUT = 5.0 V IBST 300 - - mA Peak Current Limit(11) At SWBSTIN; VIN = 3.6 V BSTPK 700 - 1500 mA Start-up Overshoot IL = 0 mA VBSTOS - - 500 mV Efficiency, IL = ILMAX SWBSTEFF 65 80 - % Bias Current Consumption(11) IBSTBIAS - 390 1200 µA External Components - Used as a condition for all other parameters Inductor(18) Inductor Resistance Inductor saturation current at 30% loss in inductance value Bypass Capacitor(19) Bypass Capacitor ESR at resonance Input Capacitor Diode current capability Diode current capability LBST R_WBST ILSAT COBST ESRBST CBSTD IBSTDPK IBSTDPK -20% 1.0 -60% 1.0 1.0 850 1500 2.2 4.7 +20% 0.2 +35% µH Ω A µF mΩ µF mAdc mApk NMOS Off Leakage, SWBSTIN = 4.5 V, SWBSTEN = 0(11) IBSTIK - 1.0 5.0 µA SWLEDOUT Output Voltage Range at VSWLED(11) VSWLED BP - 25.5 V Current Load capability(11) VSWLED = 25.5 V ILED 30 - 60 mA LED Driver Headroom 8.0 V< VSWLED < 25.5 V VLEDHR 0.3 - 0.6 V External Components Inductor Capacitor(20) Input Capacitor LLED COLED 2.2 3.3 4.7 (30 V) Or 2x10 (16 V) in series 4.7 µH µF Notes 18. Preferred device TDK VLS252012 series at 2.5x2.0 mm footprint and 1.2 mm max height 19. Applications of SWBST should take into account impact of tolerance and voltage derating on the bypass capacitor at the output level. 20. The typical value represents the nominal rated value of the capacitor and takes into account the strong derating as a function of DC voltage. all other modes from BP = 3.6 V. External loads are not included.

Analog Integrated Circuit Device Data Freescale Semiconductor 17 13892 STATIC ELECTRICAL CHARACTERISTICS Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. VVIDEO Operating Input Voltage Range VINMIN to VINMAX VINVIDEO VNOM+0.2 - 4.65 V Operating Current Load Range ILMIN to ILMAX (Not exceeding PNP max power) IVIDEO 0 -- 250/350 mA Extended input voltage range (performance may be out of specification) UVDET - 4.65 V Minimum Bypass Capacitor Value Used as a condition for all other parameters COVIDEO 1.1 2.2 - µF Bypass Capacitor ESR 10 kHz -1.0 MHz ESRVIDEO 20 - 100 mΩ VVIDEO ACTIVE MODE DC Output Voltage VOUT Vinmin < VIN < VINMAX, ILMIN < IL < ILMAX ΔVVIDEO VNOM – VNOM VNOM + 3% V Load Regulation 1.0 mA < IL < ILMAX, For any VINMIN < VIN < VINMAX VVIDEOLOPP - - 0.20 mV/mA Line Regulation VINMIN < VIN < VINMAX, For any ILMIN < IL < ILMAX VVIDEOLIPP - 5.0 8.0 mV Short-circuit Protection Threshold VINMIN < VIN < VINMAX, Short-circuit VOUT to GND IVIDEOSHT ILMAX+20 - - mA Active Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0 IVIDEOQS - 30 45 µA VVIDEO LOW POWER MODE DC - VVIDEOMODE=1 Output Voltage VOUT VINMIN < VIN < VINMAX, ILMINLP < IL < ILMAXLP ΔVVIDEOLO VNOM – VNOM VNOM + 3% V Current Load Range ILminlp to ILMAXLP IVIDEOLO 0.0 - 3.0 mA Low Power Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0 IVIDEOQSLO - 8.0 10.5 µA VAUDIO Operating Input Voltage Range VINMIN to VINMAX VAUDIO VNOM+0.2 - 4.65 V Operating Current Load Range ILMIN to ILMAX IAUDIO 0 - 150 mA Extended input voltage range (performance may be out of specification) UVDET - 4.65 V Minimum Bypass Capacitor Value COAUDIO 0.65 2.2 - µF Bypass Capacitor ESR 10 kHz -1.0 MHz ESRAUDIO 0 - 0.1 Ω all other modes from BP = 3.6 V. External loads are not included.

Analog Integrated Circuit Device Data

18 Freescale Semiconductor

STATIC ELECTRICAL CHARACTERISTICS Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. VAUDIO ACTIVE MODE DC Output Voltage VOUT (VINMIN < VIN < VINMAX, ILMIN < IL < ILmax) VAUDIO VNOM – VNOM VNOM + 3% V Load Regulation (1.0 mA < IL < ILMAX, For any VINMIN < VIN < VINMAX) VAUDIOLOR - - 0.25 mV/mA Line Regulation VINMIN < VIN < VINMAX, For any ILMIN < IL < ILMAX VAUDIOLIR - 5.0 8.0 mV Short-circuit Protection Threshold VINMIN < VIN < VINMAX, Short circuit VOUT to GND IAUDIOSHT ILMAX+20 - - mA Active Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0 IAUDIOQS - 8.0 10.5 µA VPLL AND VDIG Operating Input Voltage Range VINMIN to VINMAX VDIG, VPLL all settings, BP biased VPLL, VDIG [1:0] = 00,01 VPLL, VDIG [1:0] = 10, 11, External Switcher VINPLL, VINDIG UVDET 1.75 2.15 SW4 = 1.8 2.2 4.65 4.65 4.65 V Operating Current Load Range ILMIN to ILMAX IPLL, IDIG 0 - 50 mA Minimum Bypass Capacitor Value Used as a condition for all other parameters COPLL, CODIG 0.65 2.2 - µF Bypass Capacitor ESR 10 kHz -1.0 MHz ESRPLL, ESRDIG 0 - 0.1 Ω VPLL AND VDIG ACTIVE MODE DC (ONLY FOR 2.475, 2.7, AND 2.775 STEPS) Output Voltage VOUT VINMIN < VIN < VINMAX, ILMIN < IL < ILMAX VPLL, VDIG VNOM – 0.05 VNOM VNOM + 0.05 V Load Regulation 1.0 mA < IL < ILMAX for any VINMIN < VIN < VINMAX VPLLLOR, VDIGLOR - - 0.35 mV/mA Line Regulation VINMIN < VIN < VINMAX for any ILMIN < IL < ILMAX VPLLLIR, VDIGLIR - 5.0 8.0 mV Active Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0 IPLLLQS, IDIGLQS - 8.0 10.5 µA VIOHI Operating Input Voltage Range VINMIN to VINMAX VNOM = 2.775 V VINIOHI VNOM+0.2 - 4.65 V Operating Current Load Range ILMIN to ILMAX IIOHI 0 - 100 mA Extended Input Voltage Range (Performance may be out of specification) VINIOHIEXT UVDET - 4.65 V Minimum Bypass Capacitor Value COIOHI 0.65 2.2 - µF Bypass Capacitor ESR 10 kHz -1.0 MHz ESRIOHI 0 - 100 mΩ all other modes from BP = 3.6 V. External loads are not included.

Analog Integrated Circuit Device Data Freescale Semiconductor 19 13892 STATIC ELECTRICAL CHARACTERISTICS Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. VIOHI ACTIVE MODE DC Output Voltage VOUT - (VNOM = 2.775) VINMIN < VIN < VINMAX, ILMIN < IL < ILMAX VIOH VNOM – VNOM VNOM + 3% V Load Regulation 1.0 mA < IL < ILMAX, for any VINMIN < VIN < VINMAX VIOHLOR - - 0.35 mV/mA Line Regulation VINMIN < VIN < VINMAX, for any ILMIN < IL < ILMAX VIOHLIR - 5.0 8.0 mV Active Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0 IIOHQS - 8.0 10.5 µA VCAM Operating Input Voltage Range VINMIN to VINMAX VINCAM VNOM +0.25 - 4.65 V Operating Current Load Range ILMIN to ILMAX Internal pass FET External PNP ICAM 250 mA Extended Input Voltage Range Performance may be out of specification VINCAMEXT UVDET - 4.65 Minimum Bypass Capacitor Value Internal pass device External PNP (not exceeding PNP max power) COCAM 0.65 1.1 2.2 2.2 µF Bypass Capacitor ESR 10 kHz -1.0 MHz ESRCAM 20 - 100 mΩ VCAM ACTIVE MODE DC Output Voltage VOUT (VNOM = 2.775) VINMIN < VIN < VINMAX, ILMIN < IL < ILMAX VCAM VNOM – VNOM VNOM + 3% V Load Regulation 1.0 mA < IL < ILMAX, for any VINMIN < VIN < VINMAX VCAMLOR - - 0.25 mV/mA Line Regulation VINMIN < VIN < VINMAX, for any ILMIN < IL < ILMAX VCAMLIR - 5.0 8.0 mV Short-circuit Protection Threshold VINMIN < VIN < VINMAX, Short-circuit VOUT to GND ICAMSHT ILMAX+20 - - mA Active Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0, Internal PMOS configuration VINMIN < VIN < VINMAX, IL = 0, External PNP configuration ICAMQS µA all other modes from BP = 3.6 V. External loads are not included.

Analog Integrated Circuit Device Data

20 Freescale Semiconductor

STATIC ELECTRICAL CHARACTERISTICS Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. VCAM LOW POWER MODE DC Output Voltage VOUT VINMIN < VIN < VINMAX, ILMINLP < IL < ILMAXLP VCAMLO VNOM – VNOM VNOM + 3% V Current Load Range ILMINLP to ILMAXLP ICAMLO 0 - 3.0 mA Low Power Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0 ICAMQSLO - 8.0 10.5 µA VSD Operating Input Voltage Range VINMIN to VINMAX VSD[2:0]=010 to 111 VSD[2:0]=010 to 111, Extended Operation VSD[2:0]=000, 001 [000] BP Supplied VSD[2:0]=000 External Switcher Supplied VINSD VNOM+0.2 UVDET UVDET 2.15 2.20 4.65 4.65 4.65 4.65 V Operating Current Load Range ILMIN to ILMAX Not exceeding PNP max power ISD 0 - 250 mA Extended Input Voltage Range Performance may be out of specification for output levels VSD[2:0]=010 or greater VINSDEXT UVDET - 4.65 V Minimum Bypass Capacitor Value COSD 1.1 2.2 - µF Bypass Capacitor ESR 10 kHz -1.0 MHz ESRSD 20 - 100 mΩ VSD ACTIVE MODE DC Output Voltage VOUT VINMIN < VIN < VINMAX, ILMIN < IL < ILMAX VSD VNOM – VNOM VNOM + 3% V Load Regulation 1.0 mA < IL < ILMAX, for any VINMIN < VIN < VINMAX VSDLOR - - 0.25 mV/mA Line Regulation VINMIN < VIN < VINMAX, for any ILMIN < IL < ILMAX VSDLIR - 5.0 8.0 mV Short-circuit Protection Threshold VINMIN < VIN < VINMAX, Short-circuit VOUT to GND ISDSHT ILMAX+20 - - mA Active Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0 ISDQS - 30 45 µA all other modes from BP = 3.6 V. External loads are not included.

Analog Integrated Circuit Device Data Freescale Semiconductor 21 13892 STATIC ELECTRICAL CHARACTERISTICS Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. VSD LOW POWER MODE DC - VSDMODE=1 Output Voltage VOUT VINMIN < VIN < VINMAX, ILMINLP < IL < ILMAXLP VSDLO VNOM – VNOM VNOM + 3% V Current Load Range ILMINLP to ILMAXLP ISDLO 0 - 3.0 mA Low Power Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0 ISDQSLO - 8.0 10.5 µA VUSB GENERAL Operating Input Voltage Range VINMIN to VINMAX Supplied by VBUS Supplied by SWBST VINUSB 4.4 5.0 5.25 5.75 V Operating Current Load Range ILMIN to ILMAX IUSB 0 - 100 mA Bypass Capacitor Value Range COUSB 0.65 2.2 - µF Bypass Capacitor ESR 10 kHz -1.0 MHz ESRUSB 0 - 0.1 Ω VUSB ACTIVE MODE DC Output Voltage VOUT VINMIN < VIN < VINMAX, ILMIN < IL < ILMAX VUSB VNOM –

3.3 VNOM + 4%

V Load Regulation 0 < IL < ILMAX from DM/DP for any VINMIN < VIN < VINMAX VUSBLOR - - 1.0 mV/mA Line Regulation VINMIN < VIN < VINMAX, for any ILMIN < IL < ILMAX VUSBLIR - - 20 mV Short-circuit Protection Threshold VINMIN < VIN < VINMAX, Short-circuit VOUT to GND VUSBSHT ILMAX+20 - - mA VUSB2 Operating Input Voltage Range VINMIN to VINMAX Extended operation VINUSB2 VNOM +0.25 UVDET 4.65 4.65 V Operating Current Load Range ILMIN to ILMAX IUSB2 0 - 50 mA Minimum Bypass Capacitor Value Used as a condition for all other parameters COUSB2 0.65 2.2 - µF Bypass Capacitor ESR 10 kHz -1.0 MHz ESRUSB2 0 - 0.1 Ω all other modes from BP = 3.6 V. External loads are not included.

Analog Integrated Circuit Device Data

22 Freescale Semiconductor

STATIC ELECTRICAL CHARACTERISTICS Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. VUSB2 ACTIVE MODE DC Output Voltage VOUT VINMIN < VIN < VINMAX, ILMIN < IL < ILMAX VUSB2 VNOM – VNOM VNOM + 3% V Load Regulation 1.0 mA < IL < ILMAX, for any VINMIN < VIN < VINMAX VUSB2LOR - - 0.35 mV/mA Line Regulation VINMIN < VIN < VINMAX, for any ILMIN < IL < ILMAX VUSB2LIR - 5.0 8.0 mV Active Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0 IUSB2QS - 8.0 13 µA UVBUS Operating Input Voltage Range VINMIN to VINMAX (11) UREGIN supplied by SWBST VINUVBUS 4.75 5.0 5.25 V Operating Current Load Range ILMIN to ILMAX IUVBUS 0 - 100 mA Minimum Bypass Capacitor Value COUVBUS (21) (21) 6.5 (22) µF Bypass Capacitor ESR 10 kHz -1.0 MHz VINUVBUS (21) (21) (22) Ω UVBUS ACTIVE MODE DC Output Voltage Vout - (VNOM = 2.775) VINMIN < VIN < VINMAX, ILMIN < IL < ILMAX VUVBUS 4.4 5.0 5.25 V VGEN1 Operating Input Voltage Range VINMIN to VINMAX All settings, BP biased VGEN1=00,01, External switcher supplied VINGEN1 UVDET < VNOM +0.25 1.75 SW4 = 1.8 4.65 4.65 V Operating Current Load Range ILMIN to ILMAX (not exceeding PNP max power) IGEN1 0 - 200 mA Extended input voltage range (BP biased, performance may be out of specification for output levels VGEN1[1:0]=10 to 11) UVDET - 4.65 V Minimum Bypass Capacitor Value COGEN1 0.65 2.2 +35% µF Bypass Capacitor ESR 10 kHz -1.0 MHz ESRGEN1 20 - 100 mΩ Notes 21. Filtering is shared with CHRGRAW (shorted at board level). 2.2 µF is typically included at the CHRGRAW pin. 22. 6.5 µF is the maximum allowable capacitance on VBUS including all tolerances of filtering capacitance on VBUS and CHRGRAW (which are shorted at the board level). all other modes from BP = 3.6 V. External loads are not included.

Analog Integrated Circuit Device Data Freescale Semiconductor 23 13892 STATIC ELECTRICAL CHARACTERISTICS Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. VGEN1 ACTIVE MODE DC Output Voltage VOUT VGEN1=00, 01, VINMIN < VIN < VINMAX ILMIN < IL < ILMAX VGEN1=10, 11, VINMIN < VIN < VINMAX ILMIN < IL < ILMAX VGEN1 VNOM – 0.05 VNOM – VNOM VNOM VNOM + 0.05 VNOM + 3% V Load Regulation 1.0 mA < IL < ILMAX, for any VINMIN < VIN < VINMAX VGEN1LOR - - 0.25 mV/mA Line Regulation VINMIN < VIN < VINMAX, for any ILMIN < IL < ILMAX VGEN1LIR - 5.0 8.0 mV Short-circuit Protection Threshold VINMIN < VIN < VINMAX, Short-circuit VOUT to GND VGEN1SHT ILMAX+20 - - mA Active Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0 IGEN1QS - 20 45 µA VGEN1 LOW POWER MODE DC - VGEN1MODE=1 Output Voltage VOUT - VINMIN < VIN < VINMAX, ILMINLP < IL < ILMAXLP VGEN1=00, 01 VGEN1=10, 11 VGEN1LO VNOM – 0.05 VNOM – VNOM VNOM VNOM + 0.05 VNOM + 3% V Current Load Range ILMINLP to ILMAXLP IGEN1LO 0 - 3.0 mA Low Power Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0 IGEN1QSLO - 8.0 10.5 µA VGEN2 GENERAL Operating Input Voltage Range VINMIN to VINMAX All settings, BP biased VGEN2=000,001, External switcher supplied VINGEN2 UVDET< VNOM+0.2 2.15 2.2 4.65 4.65 V Operating Current Load Range ILMIN to ILMAX (Not exceeding PNP max power) IGEN2 0 - 350 mA Extended input voltage range (BP biased, performance may be out of specification for output levels VGEN2[2:0]=100 to 111) UVDET - 4.65 V Minimum Bypass Capacitor Value COGEN2 1.1 2.2 +35% µF Bypass Capacitor ESR 10 kHz -1.0 MHz ESRGEN2 20 - 100 mΩ all other modes from BP = 3.6 V. External loads are not included.

Analog Integrated Circuit Device Data

24 Freescale Semiconductor

STATIC ELECTRICAL CHARACTERISTICS Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. VGEN2 ACTIVE MODE DC Output Voltage VOUT VGEN2=000, 001, 010, VINMIN < VIN < VINMAX ILMIN < IL < ILMAX VGEN2=011, 100, 101, 110, 111, VINMIN < VIN < VINMAX ILMIN < IL < ILMAX VGEN2 VNOM – 0.05 VNOM – VNOM VNOM VNOM + 0.05 VNOM + 3% V Load Regulation 1.0 mA < IL < ILMAX, For any VINMIN < VIN < VINMAX VGEN2LOR - - 0.20 mV/mA Line Regulation VINMIN < VIN < VINMAX, For any ILMIN < IL < ILMAX VGEN2LIR - 5.0 8.0 mV Short-circuit Protection Threshold VINMIN < VIN < VINMAX, Short-circuit VOUT to GND VGEN2SHT ILMAX+20 - - mA Active Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0 IGEN2QS - 35 45 uA VGEN2 LOW POWER MODE DC - VGEN2MODE=1 Output Voltage VOUT - VINMIN < VIN < VINMAX, ILMINLP < IL < ILMAXLP VGEN2=000 to 010 VGEN2=011 to 111 VGEN2LO VNOM – 0.05 VNOM – VNOM VNOM VNOM + 0.05 VNOM + 3% V Current Load Range ILMINLP to ILMAXLP IGEN2LO 0 - 3.0 mA Low Power Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0 IGEN2QSLO - 8.0 10.5 µA VGEN3 GENERAL Operating Input Voltage Range VINMIN to VINMAX VGEN3CONFIG, VGEN3=01, 11 VGEN3CONFIG, VGEN3=00, 10 VINGEN3 VNOM+0.2 UVDET 4.65 4.65 V Operating Current Load Range ILMIN to ILMAX Internal Pass FET External PNP (Not exceeding PNP max power) IGEN3 200 mA Minimum Bypass Capacitor Value Internal pass device External pass device COGEN3 0.65 1.1 2.2 2.2 µF Bypass Capacitor ESR 10 kHz -1.0 MHz ESRGEN3 20 - 100 mΩ all other modes from BP = 3.6 V. External loads are not included.

Analog Integrated Circuit Device Data Freescale Semiconductor 25 13892 STATIC ELECTRICAL CHARACTERISTICS Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. VGEN3 ACTIVE MODE DC Output Voltage VOUT VGEN2=000, 001, 010, VINMIN < VIN < VINMAX ILMIN < IL < ILMAX VGEN3 VNOM – VNOM VNOM + 3% V Load Regulation 1.0 mA < IL < ILMAX, For any VINMIN < VIN < VINMAX VGEN3LOR - - 0.40 mV/mA Line Regulation VINMIN < VIN < VINMAX, For any ILMIN < IL < ILMAX VGEN3SHT - 5.0 8.0 mV VGEN3 ACTIVE MODE DC (CONTINUED) Short-circuit Protection Threshold VINMIN < VIN < VINMAX, Short circuit VOUT to GND VGEN3SHT ILMAX+20 - - mA Active Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0, Internal PMOS configuration VINMIN < VIN < VINMAX, IL=0, external PNP configuration IGEN3QS µA VGEN3 LOW POWER MODE DC Output Voltage VOUT - (Accuracy) VINMIN < VIN < VINMAX, ILMINLP < IL < ILMAXLP VGEN3LO VNOM-3% VNOM VNOM+3% V Current Load Range ILMINLP to ILMAXLP IGEN3LO 0 1.0 3.0 mA Low Power Mode Quiescent Current VINMIN < VIN < VINMAX, IL = 0 IGEN3QSLO - 8.0 10.5 µA CHARGE PATH REGULATOR Input Operating Voltage - CHRGRAW VINCHRG BATTMIN - 20 V Output Voltage Trimming Accuracy VCHRG[2:0]=011, Charge current 50 mA at T=25°C BPTRIM - - 0.35 Output Voltage Spread - VCHRG[2:0]=011, 1XX Charge current 1.0 mA to 100 mA Charge current 100 mA and above BPSP -1.0 -3.0 1.0 1.0 Current Limit Tolerance (23) ICHRG[3:0]=0001 ICHRG[3:0]=0100 ICHRG[3:0]=0110 All other settings ΔILIM 360 500 400 560 440 620 mA mA mA Start-up Overshoot - Unloaded BPOS-START - - 2.0 % Notes 23. Excludes spread and tolerance due to board and 100 mOhm sense resistor tolerances. all other modes from BP = 3.6 V. External loads are not included.

Analog Integrated Circuit Device Data

26 Freescale Semiconductor

STATIC ELECTRICAL CHARACTERISTICS Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. CHARGE PATH REGULATOR (CONTINUED) Transient Overshoot Charge current 1.0 mA to 1.0 A, Rise time 5.0 us BPOS - - 2.0 % Configuration Input Capacitance - CHRGRAW(24) Load Capacitor - BPSNS(24) Cable length CINCHRG CBP LC 2.2 µF µF m THERMAL Thermal Warning Lower Threshold TWL 95 100 105 °C Thermal Warning Higher Threshold TWH 115 120 125 °C Thermal Warning Hysteresis(25) TWHY 2.0 - 4.0 °C Thermal Protection Threshold TPT 130 140 150 °C BACKLIGHT LED DRIVERS Absolute Accuracy - All current settings - - 15 % Matching - At 400 mV, 21 mA - - 3 % Leakage - LEDxDC[5:0]=000000 - - 1 µA SIGNALING LED DRIVERS Absolute Accuracy - All current settings - - 15 % Matching - At 400 mV, 21 mA - - 3 % Leakage - LEDxDC[5:0]=000000 - - 1 µA UVBUS - GENERAL Operating Input Voltage Range VINMIN to VINMAX (26) VINUSB supplied by SWBST 4.75 5 5.25 V Operating Current Load Range ILMIN to ILMAX 0 100 mA Minimum Bypass Capacitor Value (27) (27) 6.5 (28) µF Bypass Capacitor ESR - 10 kHz-1.0 MHz (27) (27) (28) W ACTIVE MODE DC Output Voltage VOUT - (VNOM = 2.775), VINMIN < VIN < VINMAX, ILMIN < IL < ILMAX 4.4 5.0 5.25 V Short-circuit Protection Threshold ** - VINMIN < VIN < VINMAX, Short-circuit VOUT to ground ILMAX+20 - - mA Notes 24. An additional derating of 35% is allowed. 25. Equivalent to approx. 30 mW min, 60 mW max 26. Guaranteed by design. 27. Filtering is shared with CHRGRAW (shorted at board leve l). 2.2 uF is typically included at the CHRGRAW pin. 28. 6.5 uF is the maximum allowable capacitance on VBUS including all tolerances of filtering capacitance on VBUS and CHRGRAW (which are shorted at the board level). all other modes from BP = 3.6 V. External loads are not included.

Analog Integrated Circuit Device Data Freescale Semiconductor 27 13892 STATIC ELECTRICAL CHARACTERISTICS Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. ADC Conversion Current 1 mA Converter Core Input Range Single ended voltage readings Differential readings -1.2 2.4 1.2 V Maximum Input Voltage(29) Channels ADIN5, ADIN6 and ADIN7 BP V Integral Nonlinearity 3 LSB Differential Nonlinearity 1 LSB Zero Scale Error (Offset) Before auto calibration After auto calibration LSB Full Scale Error (Gain) Before auto calibration After auto calibration LSB Drift Over-temperature (30) - Including scaling 1 LSB Source Impedance No bypass capacitor at input Bypass capacitor at input 10 nF KΩ Input Buffer Offset - BUFFEN=1 -5 5 mV Input Buffer Range - BUFFEN=1 0.02 2.4 V Notes 29. ADIN5, 6 and 7 inputs must not exceed BP voltage. 30. Guaranteed by design. all other modes from BP = 3.6 V. External loads are not included.

Analog Integrated Circuit Device Data

28 Freescale Semiconductor

Analog Integrated Circuit Device Data Freescale Semiconductor 29 13892 DYNAMIC ELECTRICAL CHARACTERISTICS Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. DYNAMIC ELECTRICAL CHARACTERISTICS Table 6. Dynamic Electrical Characteristics values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

1.0 Sigma for Gaussian distribution

Output jitter exhibits a Gaussian distribution

Analog Integrated Circuit Device Data

30 Freescale Semiconductor

Analog Integrated Circuit Device Data Freescale Semiconductor 31 13892 DYNAMIC ELECTRICAL CHARACTERISTICS Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. VVIDEO ACTIVE MODE - AC (CONTINUED) Transient Line Response IL = 75% of ILMAX VVIDEOTLIR - 5.0 8.0 mV Mode Transition Time From low power to active, VIN = VINMIN, VINMAX, IL =ILMAXLP VVIDEOtMOD + - - 100 µs Mode Transition Response(36) From low power to active and from active to low power, VIN = VINMIN, VINMAX, IL = ILMAXLP VVIDEOMTR - 1.0 2.0 PSRR - IL = 75% of ILMAX, 20 Hz to 20 kHz VIN = VINMIN + 100 mV, > UVDET VIN = VNOM + 1.0 V, > UVDET VAUDIOPSS R 35 dB Output Noise - VIN = VINMIN, IL = 0.75*ILmax 100 Hz – 1.0 kHz >1.0 kHz – 10 kHz >10 kHz – 1.0 MHz VAUDIOON -114 -124 -129 dBV/√Hz Spurs 32.768 kHz and harmonics VAUDIOSP - - -120 dB Turn-on Time Enable to 90% of end value, VIN = VINMIN, VINMAX, IL = 0 VAUDIOtON - - 1.0 ms Turn-off Time Disable to 10% of initial value, VIN = VINMIN, VINMAX, IL = 0 VAUDIOtOFF 0.1 - 10 ms Start-up Overshoot VIN = VINMIN, VINMAX, IL = 0 VAUDIOOS - 1.0 2.0 Transient Load Response - See Transient Response Waveforms on page 56, VIN = VINMIN, VINMAX VAUDIOTLOR - 1.0 2.0 Transient Line Response - See Transient Response Waveforms on page 56 IL = 75% of ILMAX VAUDIOTLIR - 5.0 8.0 mV VPLL AND VDIG ACTIVE MODE - AC PSRR - IL = 75% of ILMAX, 20 Hz to 20 kHz VIN = UVDET VIN = VNOM + 1.0 V, > UVDET VPLLPSSR dB Output Noise - VIN = VINMIN, IL = 0.75*ILMAX 100 Hz – 1.0 kHz >1 kHz – 1.0 MHz VPLLON 2.5 dB/dec µV/√Hz Spurs 32.768 kHz and harmonics VPLLSP - - -85 dB Notes 36. Guaranteed by design. values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

Analog Integrated Circuit Device Data

32 Freescale Semiconductor

DYNAMIC ELECTRICAL CHARACTERISTICS Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. VPLL AND VDIG ACTIVE MODE - AC (CONTINUED) Turn-on Time Enable to 90% of end value, VIN = VINMIN, VINMAX, IL = 0 VPLLtON - - 100 µs Turn-off Time Disable to 10% of initial value, VIN = VINMIN, VINMAX, IL = 0 VPLLtOFF 0.1 - 10 ms Start-up Overshoot VIN = VINMIN, VINMAX, IL = 0 VPLLOS, - 1.0 2.0 % VDIGOS - 2.0 4.0 % Transient Load Response - See Transient Response Waveforms on page 56 VIN = VINMIN, VINMAX VPLLTLOR, VDIGTLOR - 50 70 mV Transient Line Response - See Transient Response Waveforms on page 56 IL = 75% of ILMAX VPLLTLIR, VDIGTLIR - 5.0 8.0 mV VIOHI ACTIVE MODE - AC PSRR - IL = 75% of ILMAX, 20 Hz to 20 kHz VIN = VINMIN + 100 mV, > UVDET VIN = VNOM + 1.0 V, > UVDET VIOHIPSSR dB Output Noise - VIN = VINMIN, IL = 0.75*ILMAX 100 Hz – 1.0 kHz >1.0 kHz – 1.0 MHz VIOHION 1.0 dB/dec µV/√Hz Spurs 32.768 kHz and harmonics VIOHISP - - -100 dB Turn-on Time Enable to 90% of end value, VIN = VINMIN, VINMAX, IL = 0 VIOHItON - - 1.0 ms Turn-off Time Disable to 10% of initial value, VIN = VINMIN, VINMAX, IL = 0 VIOHItOFF 0.1 - 10 ms Start-up Overshoot VIN = VINMIN, VINMAX, IL = 0 VIOHIOS - 1.0 2.0 Transient Load Response - See Transient Response Waveforms on page 56 VIN = VINMIN, VINMAX VIOHITLOR - 1.0 2.0 Transient Line Response - See Transient Response Waveforms on page 56 IL = 75% of ILMAX VIOHITLIR - 5.0 8.0 mV Mode Transition Time - See Transient Response Waveforms on page 56 From low power to active, VIN = VINMIN, VINMAX, IL = ILMAXLP VIOHIMTR - - 10 µs Mode Transition Response From low power to active and from active to low power, VIN = VINMIN, VINMAX, IL = ILMAXLP VIOHIMTR - 1.0 2.0 values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 33 13892 DYNAMIC ELECTRICAL CHARACTERISTICS Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. VCAM ACTIVE MODE - AC PSRR - IL = 75% of ILMAX, 20 Hz to 20 kHz VIN = VINMIN + 100 mV VIN = VNOM + 1.0 V VCAMPSSR dB Output Noise - VIN = VINMIN, IL = 0.75*ILMAX 100 Hz – 1.0 kHz >1.0 kHz – 1.0 MHz VCAMON 1.0 dB/dec µV/√Hz Spurs 32.768 kHz and harmonics VCAMSP - - -100 dB Turn-on Time (Enable to 90% of end value, VIN = VINMIN, VINMAX, IL = 0) VCAMtON - - 1.0 ms Turn-off Time (Disable to 10% of initial value, VIN = VINMIN, VINMAX, IL = 0) VCAMtOFF 0.1 - 10 ms Start-up Overshoot (VIN = VINMIN, VINMAX, IL = 0) VCAMOS - 1.0 2.0 % Transient Load Response - See Transient Response Waveforms on page 56 VIN = VINMIN, VINMAX VCAM=01, 10, 11 VCAM=00 VCAMLOR 1.0 2.0 mV Transient Line Response - See Transient Response Waveforms on page 56 IL = 75% of ILMAX VCAMLIR - 5.0 8.0 mV Mode Transition Time - See Transient Response Waveforms on page 56 From low power to active, VIN = VINMIN, VINMAX, IL = ILMAXLP VCAMtMOD - - 100 µs Mode Transition Response From low power to active and from, active to low power, VIN = VINMIN, VINMAX, IL = ILMAXLP VCAMMTR - 1.0 2.0 VSD ACTIVE MODE - AC PSRR - IL = 75% of ILMAX, 20 Hz to 20 kHz VIN = VINMIN + 100 mV VIN = VNOM + 1.0 V VSDPSSR dB Output Noise - VIN = VINMIN, IL = 75% of ILMAX 100 Hz – 1.0 kHz >1.0 kHz – 10 kHz >10 kHz – 1.0 MHz VSDON -115 -126 -132 dBV/√Hz Spurs (32.768 kHz and harmonics) VSDSP - - -100 dB Turn-on Time (Enable to 90% of end value, VIN = VINMIN, VINMAX, IL = 0) VSDtON - - 1.0 ms Turn-off Time (Disable to 10% of initial value, VIN = VINMIN, VINMAX, IL = 0) VSDtOFF 0.1 - 10 ms Start-up Overshoot VIN = VINMIN, VINMAX, IL = 0 VSDOS - 1.0 2.0 values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

Analog Integrated Circuit Device Data

34 Freescale Semiconductor

100 Hz – 50 kHz

50 kHz – 1.0 MHz VUSBON 1.0 0.2 µV/√Hz VUSB2 ACTIVE MODE - AC PSRR - IL = 75% of ILMAX, 20 Hz to 20 kHz VIN = VINMIN + 100 mV VIN = VNOM + 1.0 V VUSB2PSSR dB Output Noise - VIN = VINMIN, IL = 0.75*ILMAX 100 Hz – 1.0 kHz >1.0 kHz – 1.0 MHz VUSB2ON 0.2 dB/dec µV/√Hz Spurs 32.768 kHz and harmonics VUSB2SP - - -100 dB Turn-on Time(37) Enable to 90% of end value, VIN = VINMIN, VINMAX, IL = 0 VUSB2tON - - 100 µs Turn-off Time(37) Disable to 10% of initial value, VIN = VINMIN, VINMAX, IL = 0 VUSBtOFF 0.1 - 10 ms Start-up Overshoot VIN = VINMIN, VINMAX, IL = 0 VUSB2OS - 1.0 2.0 Transient Load Response - See Transient Response Waveforms on page 56 VIN = VINMIN, VINMAX VUSB2TLOR - 1.0 2.0 Transient Line Response - See Transient Response Waveforms on page 56 IL = 75% of ILMAX VUSB2TLIR - 5.0 8.0 mV Notes 37. Guaranteed by design.

values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 35 13892 DYNAMIC ELECTRICAL CHARACTERISTICS Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. UVBUS ACTIVE MODE DC Turn-on Time(38) VBUS Rise Time per USB OTG with max loading of 6.5 µF+10 µF UVBUStON - - 100 ms Turn-off Time(38) Disable to 0.8 V, per USB OTG specification parameter VA_SESS_VLD, VIN = VINMIN, VINMAX, IL=0 UVBUStOFF - - 1.3 sec VGEN1 ACTIVE MODE - AC PSRR - IL = 75% of ILMAX, 20 Hz to 20 kHz VIN = UVDET VIN = VNOM + 1.0 V, > UVDET VGEN1PSS R 35 dB Output Noise - VIN = VINMIN, IL = 0.75*ILMAX 100 Hz – 1.0 kHz >1.0 kHz – 10 kHz >10 kHz – 1.0 MHz VGEN1ON -115 -126 -132 dBV/√Hz Spurs 32.768 kHz and harmonics VGEN1SP - - -100 dB Turn-on Time Enable to 90% of end value VIN = VINMIN, VINMAX, IL = 0 VGEN1tON - - 1.0 ms Turn-off Time Disable to 10% of initial value VIN = VINMIN, VINMAX, IL = 0 VGEN1tOFF 0.1 - 10 ms Start-up Overshoot VIN = VINMIN, VINMAX, IL = 0 VGEN1OS - 1.0 2.0 Transient Load Response - See Transient Response Waveforms on page 56 VIN = VINMIN, VINMAX - VGEN1[1:0]=10 to 11 - VGEN[1:0]=00 to 01 VGEN1TLOR 1.0 2.0 mV Transient Line Response - See Transient Response Waveforms on page 56 IL = 75% of ILMAX VGEN1TLIR - 5.0 8.0 mV Mode Transition Time - See Transient Response Waveforms on page 56 From low power to active VIN = VINMIN, VINMAX, IL = ILMAXLP VGEN1tMOD - - 100 µs Mode Transition Response - See Transient Response Waveforms on page 56 From low power to active and from active to low power VIN = VINMIN, VINMAX, IL = ILMAXLP VGEN1MTR - 1.0 2.0 Notes 38. Guaranteed by design. values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

Analog Integrated Circuit Device Data

36 Freescale Semiconductor

DYNAMIC ELECTRICAL CHARACTERISTICS Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. VGEN2 ACTIVE MODE - AC PSRR - IL = 75% of ILMAX, 20 Hz to 20 kHz VIN = VINMIN + 100 mV VIN = VNOM + 1.0 V VGEN2PSS R 35 dB Output Noise - VIN = VINMIN, IL = ILMAX 100 Hz – 1.0 kHz >1.0 kHz – 10 kHz >10 kHz – 1.0 MHz VGEN2ON -115 -126 -132 dBV/√Hz Spurs (32.768 kHz and harmonics) VGEN2SP - - -100 dB Turn-on Time Enable to 90% of end value VIN = VINMIN, VINMAX, IL = 0 VGEN2tON - - 1.0 ms Turn-off Time (Disable to 10% of initial value VIN = VINMIN, VINMAX, IL = 0) VGEN2tOFF 0.1 - 10 ms VGEN2 ACTIVE MODE - AC Start-up Overshoot VIN = VINMIN, VINMAX, IL = 0 VGEN2OS - 1.0 2.0 Transient Load Response(39) - See Transient Response Waveforms on page 56 VIN = VINMIN, VINMAX - VGEN2[2:0]=100 to 111 - VGEN2[2:0]=000 to 011 VGEN2TLOR 1.0 3.0 mV Transient Line Response - See Transient Response Waveforms on page 56 IL = 75% of ILMAX VGEN2TLIR - 5.0 8.0 mV Mode Transition Time - See Transient Response Waveforms on page 56 From low power to active VIN = VINMIN, VINMAX, IL = ILMAXLP VGEN2tMOD - - 100 µs Mode Transition Response - See Transient Response Waveforms on page 56 From low power to active and from active to low power VIN = VINMIN, VINMAX, IL = ILMAXLP VGEN2MTR - 1.0 2.0 VGEN3 ACTIVE MODE - AC PSRR IL = 75% of ILMAX, 20 Hz to 20 kHz, VIN = VINMIN +100 mV Vin=Vnom+1V VGEN3PSS R 35 dB Output Noise - VIN = VINMIN, IL = 75% of ILMAX 100 Hz – 1.0 kHz >1.0 kHz – 1.0 MHz VGEN3ON 1.0 dB/dec µV/√Hz Spurs 32.768 kHz and harmonics VGEN3SP - - -100 dB Notes 39. Guaranteed by design. values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 37 13892 DYNAMIC ELECTRICAL CHARACTERISTICS Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. VGEN3 ACTIVE MODE - AC (CONTINUED) Turn-on Time Enable to 90% of end value VIN = VINMIN, VINMAX, IL = 0 VGEN3tON - - 1.0 ms Turn-off Time Disable to 10% of initial value VIN = VINMIN, VINMAX, IL = 0 VGEN3tOFF 0.1 - 5.0 ms Start-up Overshoot VIN = VINMIN, VINMAX, IL = 0 VGEN3OS - 1.0 2.0 Transient Load Response VIN = VINMIN, VINMAX - VGEN3=1 - VGEN3=0 VGEN3TLOR 1.0 2.0 mV Transient Line Response (IL = 75% of ILMAX) VGEN3TLIR - 5.0 8.0 mV Mode Transition Time From low power to active VIN = VINMIN, VINMAX, IL = ILMAXLP VGEN3tMOD - - 100 µs Mode Transition Response From low power to active and from active to low power, VIN = VINMIN, VINMAX, IL = ILMAXLP VGEN3MTR - 1.0 2.0 UVBUS - ACTIVE MODE DC Turn-On Time (40) - VBUS Rise Time por USB OTG with max loading of 6.5 µF+10 µF - - 100 ms Turn-Off Time (40) - Disable to 0.8 V, per USB OTG specification parameter VA_SESS_VLD VIN = VINMIN, VINMAX, IL=0 - - 1.3 sec ADC Conversion Time per Channel - PLLX[2:0]=100 10 µs Turn On Delay If Switcher PLL was active If Switcher PLL was inactive µs TOUCH SCREEN Turn-on Time (40) - 90% of output 500 µs Notes 40. Guaranteed by design. values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.

Analog Integrated Circuit Device Data

38 Freescale Semiconductor

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. TIMING DIAGRAMS Figure 5 and Table 7 summarize the SPI electrical and timing requirements. The SPI input and output levels are set independently via the SPIVCC pin by connecting it to the desired supply. This would typically be tied to SW4 programmed for 1.80 V. The strength of the MISO driver is programmable through the SPIDRV[1:0] bits. Figure 5. Timing Requirements Table 7. Timing Parameter Description

This table reflects a maxi mum SPI clock frequency of 26 MHz. Slew rate for SPI MISO output driver is programmable from 0.16 to

0.66 V/ns

Analog Integrated Circuit Device Data Freescale Semiconductor 39 13892 FUNCTIONAL DESCRIPTION INTRODUCTION Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL PIN DESCRIPTION CHARGER CHRGRAW 1. Charger input. The charger voltage is measured through an ADC at this pin. The UVBUS pin must be shorted to CHRGRAW in cases where the charger is being supplied from the USB cable. The minimum voltage for this pin depends on BATTMIN threshold value (see Battery Management). 2. Output to battery supplied accessories. The battery voltage can be applied to an accessory by enabling the charge path for the accessory via the CHRGRAW pin. To accomplish this, the charger needs to be configured in reverse supply mode. CHRGCTRL1 Driver output for charger path FET M1. CHRGCTRL2 Driver output for charger path FET M2. CHRGISNS Charge current sensing point 1. The charge current is read by monitoring the voltage drop over the charge current 100 mΩ sense resistor connected between CHRGISNS and BPSNS. BPSNS 1. BP sense point. BP voltage is sensed at this pin and compared with the voltage at CHRGRAW. 2. Charge current sensing point 2. The charge current is read by monitoring the voltage drop over the charge current 100 mΩ sense resistor. This resistor is connected between CHRGISNS and BPSNS. BP This pin is the application supply point, the input supply to the IC core circuitry. The application supply voltage is sensed through an ADC at this pin. BATTFET Driver output for battery path FET M3. If no charging system is required, the pin BATTFET must be floating. When single path is implemented, it must be connected to ground. BATTISNS Battery current sensing point 1. The current flowing out of and into the battery can be read via the ADC by monitoring the voltage drop over the sense resistor between BATT and BATTISNS. BATT Battery positive terminal. Battery current sensing point 2. The supply voltage of the battery is sensed through an ADC on this pin. The current flowing out of and into the battery can be read via the ADC by monitoring the voltage drop over the sense resistor between BATT and BATTISNS. BATTISNSCC Accumulated current counter current sensing point. This is the coulomb counter current sense point. It should be connected directly to the 0.020 Ω sense resistor via a separate route from BATTISNS. The coulomb counter monitors the current flowing in/out of the battery by integrating the voltage drop over the BATTISNCC and the BATT pin. CFP AND CFM Accumulated current filter cap plus and minus terminals respectively. The coulomb counter will require a 10 µF output capacitor connected between these pins to perform a first order filtering of the signal across R1. CHRGSE1B An unregulated wall charger configuration can be built in which case this pin must be pulled low. When charging through USB, it can be left open since it is internally pulled up to VCORE. The recommendation is to place an external FET that can pull it low or left it open, depending on the charge method. CHRGLED Trickle LED driver output 1. Since normal LED control via the SPI bus is not always possible in the standalone operation, a current sink is provided at the CHRGLED pin. This LED is to be connected between this pin and CHRGRAW. GNDCHRG Ground for charger interface.

Analog Integrated Circuit Device Data

40 Freescale Semiconductor

FUNCTIONAL PIN DESCRIPTION Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. LED DRIVERS SWLEDOUT Boost converter output for serial LED drive. It provides up to 25.5 V for supplying LED strings driven by LEDMD, LEDAD and LEDKP. GNDSWLED Ground for boost converter for serial LED drive LEDMD, LEDAD, AND LEDKP LEDMD - Main display backlight LED driver output. LEDAD - Auxiliary display backlight LED driver output. LEDKP - Keypad lighting LED driver output. Independent programmable current sink channels. LED strings must be connected from SWLEDOUT (anodes) to these pins (cathodes). When parallel strings are ganged together on a driver channel, ballasting resistance is recommended to help balance the currents in each leg. LEDR, LEDG AND LEDB General purpose LED driver output Red, Green and Blue respectively. Each channel provides flexible LED intensity control. These pins can also be used as general purpose open drain outputs for logic signaling, or as generic PWM generator outputs. GNDLED E5 Ground for LED drivers IC CORE VCORE Regulated supply output for the IC analog core circuitry. It is used to define the PUMS VIH level during initialization. The bandgap and the rest of the core circuitry are supplied from VCORE. Place a 2.2 μF capacitor from this pin to GNDCORE. VCOREDIG Regulated supply output for the IC digital core circuitry. No external DC loading is allowed on VCOREDIG. VCOREDIG is kept powered as long as there is a valid supply and/or coin cell. Place a 2.2 μF capacitor from this pin to GNDCORE. REFCORE Main bandgap reference. All regulators use the main bandgap as the reference. The main bandgap is bypassed with a capacitor at REFCORE. No external DC loading is allowed on REFCORE. Place a 100 nF capacitor from this pin to GNDCORE. GNDCORE Ground for the IC core circuitry. POWER GATING PWGTDRV1 AND PWGTDRV2 Power Gate Drivers. PWGTDRV1 is provided for power gating peripheral loads sharing the processor core supply domain(s) SW1, and/or SW2, and/or SW3. In addition, PWGTDRV2 provides support to power gate peripheral loads on the SW4 supply domain. In typical applications, SW1, SW2, and SW3 will both be kept active for the processor modules in state retention, and SW4 retained for the external memory in self refresh mode. SW1, SW2, and SW3 power gating FET drive would typically be connected to PWGTDRV1 (for parallel NMOS switches). SW4 power gating FET drive would typically be connected to PWGTDRV2. When low power Off mode is activated, the power gate drive circuitry will be disabled, turning off the NMOS power gate switches to isolate the maintained supply domains from any peripheral loading. SWITCHERS SW1IN, SW2IN, SW3IN AND SW4IN Switchers 1, 2, 3, and 4 input. Connect these pins to BP to supply Switchers 1, 2, 3, and 4. SW1FB, SW2FB, SW3FB AND SW4FB Switchers 1, 2, 3, and 4 feedback. Switchers 1, 2, 3, and 4 output voltage sense respectively. Connect these pins to the farther point of each of their respective SWxOUT pin, in order to sense and maintain voltage stability. SW1OUT Switcher 1 output. Buck switcher for processor core(s). GNDSW1 Ground for Switcher 1. SW2OUT Switcher 2 output. Buck switcher for processor SOG, etc. GNDSW2 Ground for Switcher 2. SW3OUT Switcher 3 output. Buck switcher for internal processor memory and peripherals. GNDSW3 Ground for switcher 3.

Analog Integrated Circuit Device Data Freescale Semiconductor 41 13892 FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. SW4OUT Switcher 4 output. Buck switcher for external memory and peripherals. GNDSW4 Ground for switcher 4. DVS1 AND DVS2 Switcher 1 and 2 DVS input pins. Provided for pin controlled DVS on the buck switchers targeted for processor core supplies. The DVS pins may be reconfigured for Switcher Increment / Decrement (SID) mode control. When transitioning from one voltage to another, the output voltage slope is controlled in steps of 25 mV per time step. These pins must be set high in order for the DVS feature to be enabled for each of switchers 1 or 2, or low to disable it. SWBSTIN Switcher BST input. The 2.2 μH switcher BST inductor must be connected here. SWBSTOUT Power supply for gate driver for the internal power NMOS that charges SWBST inductor. It must be connected to BP . SWBSTFB Switcher BST feedback. When SWBST is configured to supply the UVBUS pin in OTG mode the feedback will be switched to sense the UVBUS pin instead of the SWBSTFB pin. GNDSWBST Ground for switcher BST. REGULATORS VINIOHI Input of VIOHI regulator. Connect this pin to BP in order to supply VIOHI regulator. VIOHI Output regulator for high voltage IO. Fixed 2.775 V output for high voltage level interface. VINPLL AND VINDIG The input of the regulator for processor PLL and Digital regulators respectively. VINDIG and VINPLL can be connected to either BP or a 1.8 V switched mode power supply rail, such as from SW4 for the two lower set points of each regulator (the 1.2 and 1.25 V output for VPLL, and 1.05 and 1.25 V output for VDIG). In addition, when the two upper set points are used (1.50 and 1.8V outputs for VPLL, and 1.65 and 1.8V for VDIG), they can be connected to either BP or a 2.2V nominal external switched mode power supply rail, to improve power dissipation. VPLL Output of regulator for processor PLL. Quiet analog supply (PLL, GPS). VDIG Output regulator Digital. Low voltage digital (DPLL, GPS). VVIDEODRV Drive output for VVIDEO external PNP transistor. VVIDEO Output regulator TV DAC. This pin must be connected to the collector of the external PNP transistor of the VVIDEO regulator. VINAUDIO Input regulator VAUDIO. Typically connected to BP. VAUDIO Output regulator for audio supply. VINUSB2 Input regulator VUSB2. This pin must always be connected to BP even if the regulators are not used by the application. VUSB2 Output regulator for powering USB PHY. VINCAMDRV 1. Input regulator camera using internal PMOS FET. Typically connected to BP. 2. Drive output regulator for camera voltage using external PNP device. In this case, this pin must be connected to the base of the PNP in order to drive it. VCAM Output regulator for the camera module. When using an external PNP device, this pin must be connected to its collector. VSDDRV Drive output for the VSD external PNP transistor. VSD Output regulator for multi-media cards such as micro SD, RS-MMC. VGEN1DRV Drive output for the VGEN1 external PNP transistor.

Analog Integrated Circuit Device Data

42 Freescale Semiconductor

FUNCTIONAL PIN DESCRIPTION Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. VGEN1 Output of general purpose 1 regulator. VGEN2DRV Drive output for the VGEN2 external PNP transistor. VGEN2 Output of general purpose 2 regulator. VINGEN3DRV 1. Input for the VGEN3 regulator when no external PNP transistor used. Typically connected to BP. 2. Drive output for VGEN3 in case an external PNP transistor is used on the application. In this case, this pin must be connected the base of the PNP transistor. VGEN3 Output of general purpose 3 regulator. VSRTC Output regulator for the SRTC module on the processor. The VSRTC regulator provides the CLK32KMCU output level (1.2 V). Additionally, it is used to bias the Low Power SRTC domain of the SRTC module integrated on certain FSL processors. GNDREG1 Ground for regulators 1. GNDREG2 Ground for regulators 2. GNDREG3 Ground for regulators 3. GPO1 General purpose output 1. Intended to be used for battery thermistor biasing. In this case, connect a 10 KΩ resistor from GPO1 to ADIN5, and one from ADIN5 to GND. GPO2 General purpose output 2. GPO3 General purpose output 3. GPO4 General purpose output 4. It can be configured for a muxed connection into Channel 7 of the GP ADC. CONTROL LOGIC LICELL Coin cell supply input and charger output. The LICELL pin provides a connection for a coin cell backup battery or supercap. If the main battery is deeply discharged, removed, or contact-bounced (i.e., during a power cut), the RTC system and coin cell maintained logic will switch over to the LICELL for backup power. This pin also works as a current- limited voltage source for battery charging. A small capacitor should be placed from LICELL to ground under all circumstances. XTAL1 32.768 kHz Oscillator crystal connection 1. XTAL2 32.768 kHz Oscillator crystal connection 2. GNDRTC Ground for the RTC block. CLK32K 32 kHz Clock output for peripherals. At system start-up, the 32 kHz clock is driven to CLK32K (provided as a peripheral clock reference), which is referenced to SPIVCC. The CLK32K is restricted to state machine activation in normal on mode. CLK32KMCU 32 kHz Clock output for processor. At system start-up, the 32 kHz clock is driven to CLK32KMCU (intended as the CKIL input to the system processor) referenced to VSRTC. The driver is enabled by the start-up sequencer and the CLK32KMCU is programmable for Low Power Off mode control by the state machine. RESETB AND RESETBMCU Reset output for peripherals and processor respectively. These depend on the Power Control Modes of operation (See Functional Device Operation on page 48). These are meant as reset for the processor, or peripherals in a power up condition, or to keep one in reset while the other is up and running.

available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. Start (depending on the configuration). internal logic to qualify and respond to the pin level changes. can make adjustments accordingly, as soon as it is running. signaled to the processor by driving the INT pin high. that it is in effect a parallel path for the power key. Table 8. Standby Control Pins

STANDBY = 0: System is not in Standby; STANDBY=1: Syst em is in Standby and Standby programmability is activated.

44 Freescale Semiconductor

available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. Table 9. Power Up Defaults

The switchers SWx are activated in PWM pulse ski pping mode allowed when enabled by the startup sequencer.
USB supplies VUSB, is only enabled if 5.0 V is present on UVBUS.
The following supplies are not included in the matrix, since they are not intended for activation by the start-up sequencer: VCAM,

VGEN1, VGEN3, VVIDEO, and VAUDIO.

available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. pin as summarized in the following table. mode. Once activated, CS functions as the SPI Chip Select. weak pull-down is integrated on the CS pin). possible addresses (A0 address selection). signal (bi-directional serial data line). Table 10. Power Up Sequence

0 SW2 SW2

1 SW4 VGEN2

2 VIOHI SW4

3 VGEN2 VIOHI, VSD

4 SW1 SWBST, VUSB(50)

5 SW3 SW1

6 VPLL VPLL

7 VDIG SW3

8 VDIG

9 VUSB(49), VUSB2 VUSB2

Time slots may be included for blocks which are defined by the PUMS pins as disabled, to allow for potential activation.
The following supplies are not included in the matrix, since they are not intended for activation by the start-up sequencer: VCAM,
USB supplies VUSB, is only enabled if 5.0 V is present on UVBUS.

46 Freescale Semiconductor

available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. floating, grounded, or factory mode condition on the UID pin.

USB transceiver cable interface.

external USB transceiver IC. defined as the power rail of the USB cable (+5.0 V). Note: The ADIN5/6/7 inputs must not exceed BP. biased from one of the general purpose IOs such as GPO1. thermistor check function is used. the PA thermistor is connected here. respectively mapped on ADC channels 4, 5, 6, and 7. plate is connected to ground (TSY1). Table 11. UID Pin Levels

UID maximum voltage is 5.25 V

Analog Integrated Circuit Device Data Freescale Semiconductor 47 13892 FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. TSREF Touch Screen Reference regulator. This regulator is powered from VCORE. In applications not supporting touch screen, the TSREF can be used as a low current general purpose regulator, or it can be kept disabled and the bypass capacitor omitted. ADTRIG ADC trigger input. A rising edge on this pin will start an ADC conversion. GNDADC Ground for A to D circuitry. THERMAL GROUNDS GNDSUB1-9 Non critical signal grounds and thermal heat sinks.

Analog Integrated Circuit Device Data

48 Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. FUNCTIONAL DEVICE OPERATION PROCESSOR LOGIC INTERFACING CLOCK GENERATION A system clock is generated for internal digital circuitry as well as for external applications utilizing the clock output pins. A crystal oscillator is used for the 32.768 kHz time base and generation of related derivative clocks. If the crystal oscillator is not running (for example, if the crystal is not present), an internal 32 kHz oscillator will be used instead. Support is also provided for an external Secure Real Time Clock (SRTC), which may be integrated on a companion system processor IC. For media protection in compliance with Digital Rights Management (DRM) system requirements, the CLK32KMCU can be provided as a reference to the SRTC module, where tamper protection is implemented. The internal 32kHz oscillator is an integrated backup for the crystal oscillator and provides a 32.768 kHz nominal frequency at 20% accuracy if running. The internal oscillator only runs if a valid supply is available at BP and would not be used as long as the crystal oscillator is active. In absence of a valid supply at the BP supply node (for instance due to a dead battery), the crystal oscillator continues running supplied from the coin cell battery until the coin cell is depleted. All control functions will run off the crystal derived frequency, occasionally referred to as “32 kHz” for brevity’s sake. The crystal oscillator has been optimized for use in conjunction with the Micro Crystal CC7V-T1A- 32.768 kHz-9.0 pF-30 ppm or equivalent (such as the Micro Crystal CC5V-T1A or Epson FC135) is capable of handling its parametric variations. The electrical characteristics of the 32 kHz crystal oscillator are given in Tables 4 and 6, taking into account the crystal characteristics noted previously. The oscillator accuracy depends largely on the temperature characteristics of the used crystal. Application circuits can be optimized for required accuracy by adapting the external crystal oscillator network (via component accuracy and/or tuning). Additionally, a clock calibration system is provided to adjust the 32,768 cycle counter that generates the 1.0 Hz timer and RTC registers; see the RTC section for more detail. SRTC SUPPORT AND VSRTC When configured for DRM mode (SPI bit DRM=1), the CLK32KMCU driver will be kept enabled through all operational states to ensure that the SRTC module always has its reference clock. If DRM=0, the CLK32KMCU driver will not be maintained in the Off state. It is also necessary to provide a means for the processor to do an RTC initiated wake-up of the system if it has been programmed for such capability. This can be accomplished by connecting an open drain NMOS driver to the PWRON pin of 13892 so that it is in effect a parallel path for the power key. The 13892 will not be able to discern the turn on event from a normal power key initiated turn on, but the processor should have the knowledge since the RTC initiated turn on is generated locally. The VSRTC regulator provides the CLK32KMCU output level. It is also used to bias the Low Power SRTC domain of the SRTC module integrated on certain FSL processors. The VSRTC regulator is enabled as soon as the RTCPORB is detected. The VSRTC cannot be disabled. VSRTC REAL TIME CLOCK A Real Time Clock (RTC) is provided with time and day counters as well as an alarm function. The RTC utilizes the 32.768 kHz crystal oscillator for the time base, and is powered by the coin cell backup supply when BP has dropped below operational range. In configurations where the SRTC is used, the RTC can be disabled to conserve current drain by setting the RTCDIS bit to a 1 (defaults on at power up). TIME AND DAY COUNTERS The 32.768 kHz clock is divided down to a 1.0 Hz time tick which drives a 17 bit Time Of Day (TOD) counter. The TOD counter counts the seconds during a 24 hour period from 0 to 86,399 and will then roll over to 0. When the roll over occurs, it increments the 15 bit DAY counter. The DAY counter can count up to 32767 days. The 1.0 Hz time tick can be used to generate a 1.0 Hz interrupt if unmasked. TIME OF DAY ALARM A Time Of Day Alarm (TODA) function can be used to turn on the application and alert the processor. If the application is already on, the processor will be interrupted. The TODA and DAYA registers are used to set the alarm time. When the TOD counter is equal to the value in TODA and the DAY counter is equal to the value in DAYA, the TODAI interrupt will be generated. TIMER RESET As long as the supply at BP is valid, the real time clock will be supplied from VCORE. If not, it can be backed up from a coin cell via the LICELL pin. When the backup voltage drops below RTCUVDET, the RTCPORB reset signal is generated and the contents of the RTC will be reset. Additional registers backed up by coin cell will also reset with RTCPORB. To inform the processor that the contents of the RTC are no longer valid due to the reset, a timer reset interrupt function is implemented with the RTCRSTI bit.

available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. the ADC reading of the coin cell voltage to yield zero. coin cell will be reduced in order to save power. accessed through an SPI interface in a typical application. Table 12. 13892 Coin Cell Battery Electrical Characteristics Table 13. 13892 Muxed Pin Options for SPI and I2C Interfaces (SPI Functions)

CS held low at Cold Start configures the interface for SPI mode; once activated,

CS functions as the SPI Chip Select.

50 Freescale Semiconductor

available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. well as information on external signals. 1 write/read_b bit, 6 address bits, 1 null bit, and 24 data bits. 2C mode when configured as such. communication interface is configured for SPI or I2C. becomes inactive, the interrupt will remain set until cleared. debounce time can vary slightly. Table 14. Muxed Pin Options for SPI and I2C Interfaces (I2C Functions)

CS tied to VCORE at Cold Start configures interface for I 2C mode; the pin is not used in I2C mode other than for configuration.
In I 2C mode, the MOSI pin hard wired to ground or VCORE is used to select between two possible addresses.

52 Freescale Semiconductor

available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. Figure 7. Buck Switch Diagram converters permit a 100% duty cycle operation. maintaining a constant switching frequency. for both the Normal and Standby operation. the switcher voltage to its normal programmed set point. feature limits the inrush current at startup. due to board level IR drops.

Analog Integrated Circuit Device Data Freescale Semiconductor 53 13892 FUNCTIONAL DEVICE OPERATION Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. skipping feature improves efficiency by reducing dynamic switching losses simply by switching less often. In its lowest power mode, the switcher can regulate using hysteresis control known as a Pulse Frequency Modulation (PFM) control scheme. The frequency spectrum will be a function of input and output voltage, loading, and the external components. Due to its spectral variance and lighter drive capability, PFM mode is generally reserved for non-active radio modes and Deep Sleep operation. CURRENT LIMITER A built in current limiter ensures that during normal operation the maximum current through the coil is not exceeded (refer to Electrical Characteristics). This current limiter can be disabled by SPI bits. SWITCHING FREQUENCY A PLL generates the switcher system clocking from the 32.768 kHz crystal oscillator reference. To allow for spectral optimization for reduction of spurious influence in a radion environment, the PLL can be programmed via SPI from a multiplication factor of 84 to 105, in steps of 3. BOOST CONVERTERS SWBST SWBST is a boost switching regulator with a fixed 5.0 V output. It runs at 2/3 of the switcher PLL frequency. SWBST supplies the VUSB regulator for the USB system in OTG mode, as well as the VBUS voltage at the UVBUS pin. When SWBST is configured to supply the UVBUS pin in OTG mode, the feedback will be switched to sense the UVBUS pin instead of the SWBSTFB pin. Therefore, when driving the VBUS for OTG mode, the output of the switcher may rise to 5.75 V to compensate for the voltage drops in the internal switches. Note that the parasitic leakage path for a boost switcher will cause the output voltage SWBSTOUT and SWBSTFB to sit at a Schottky drop below the battery voltage, whenever SWBST is disabled. The switching NMOS transistor is integrated on-chip. An external fly back Schottky diode, inductor, and capacitor are required. Figure 8. 13892 SWBST Block Diagram.

Analog Integrated Circuit Device Data

54 Freescale Semiconductor

available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. for the mode transition response. Table 15. Core Circuitry Main Characteristics

3.0 V < BP < 4.65 V, no external loading on VCOREDIG, VCORE, or REFCORE. Extended operation down to UVDET with VCORE

down to UVDET, but no system malfunction.

The core is in On mode when charging, or when the state machi ne of the IC is not in the Off mode, nor in the power cut mode. Otherwise,

56 Freescale Semiconductor

available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. Figure 10. Transient Response Waveforms used to optimize power efficiency during deep sleep modes. FET and has a dedicated input supply pin VINAUDIO. depends on the external pass device.

Analog Integrated Circuit Device Data Freescale Semiconductor 57 13892 FUNCTIONAL DEVICE OPERATION Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. PERIPHERAL INTERFACING IC interfaces in the lineups generally fall in two categories: low voltage IO primarily associated with the AP IC and certain peripherals at the SPIVCC level (powered from SW4), and a higher voltage interface level associated with other peripherals not compatible with the 1.8 V SPIVCC. VIOHI is provided at a fixed nominal output voltage 2.775 V level (VNOM as referred in Table 4) for such interfaces, and may also be applied to other system needs within the guidelines of the regulator specifications. The input VINIOHI is not only used by the VIOHI regulator, but also by other blocks. Therefore it should always be connected to BP, even if the VIOHI regulator is not used by the system. VIOHI has an internal PMOS pass FET which will support loads up to 100 mA. CAMERA The camera module is supplied by the regulator VCAM. This allows for powering the entire module independent of the rest of other parts of the system, as well as to select from a number of VCAM output levels for camera vendor flexibility. In applications with a dual camera, it is anticipated that only one of the two cameras is active at a time, allowing the VCAM supply to be shared between them. VCAM has an internal PMOS pass FET, which will support up to 2Mpixel Camera modules (<65 mA). To support higher resolution cameras, an external PNP is provided. The external PNP configuration is offered to avoid excess on-chip power dissipation at high loads and large differential between BP and output settings. For lower current requirements, an integrated PMOS pass FET is included. The input pin for the integrated PMOS option is shared with the base current drive pin for the PNP option. The nominal output voltage of this regulator (VNOM as referred in Table 4) is SPI configurable, and can be 2.5, 2.6, 2.75, or 3.0 V. The output current when working with the internal pass FET is 65 mA, and could be up to 250 mA when working with an external PNP. MULTI-MEDIA CARD SUPPLY This supply domain is generally intended for user accessible multi-media cards such as Micro-SD (TransFlash), RS-MMC, and the like. An external PNP is utilized for this LDO to avoid excess on-chip power dissipation at high loads and large differential between BP and output settings. The external PNP device is always connected to the BP line in the application. VSD may also be applied to other system needs within the guidelines of the regulator specifications. At the 1.8 V set point, the VSD regulator can be powered from and external buck switcher (2.2 V typ) for an efficiency advantage and reduced power dissipation in the pass devices. This regulator can be configured for nominal output voltages (VNOM as referred in Table 4) of 1.8, 2.00, 2.60, can draw a current of 250 mA. USB SUPPLY The VUSB regulator is used to supply a nominal output voltage (VNOM as referred in Table 4) of 3.3 V to the external USB PHY. The UVBUS line of the USB interface is supplied by the host, in the case of host mode operation, or by the integrated VBUS generation circuit, in the case of USB OTG mode operation. The VBUS circuit is powered from the SWBST boost supply, to ensure OTG current sourcing compliance through the normal discharge range of the main battery. The VUSB regulator can be supplied from the VBUS wire of the USB cable (power rail of the USB cable), when supplied by a host, in the case of host mode operation, or by the SWBST voltage for OTG mode operation. The SWBST voltage supplies the VUSB regulator from the VINUSB pin, which is internally connected to SWBST, and also to the UVBUS pin to drive the VBUS on this mode (as long as VBUSEN pin is logic high =1). When UVBUS/CHARGRAW is detected in host mode, the USB regulators, VUSB and VUSB2 should be automatically enabled. It will be up to the processor to determine what type of device is connected, either a USB host or a wall charger, and take appropriate action. The VUSB and VUSB2 regulators can be enabled independent of OTG or Host Mode by setting the individual SPI enable bits, VUSBEN and VUSB2EN respectively. Since UVBUS can be shared with the charger input at the board level, the UVBUS node must be able to withstand the same high voltages as the charger. In over-voltage conditions, the VUSB regulator is disabled. USB supplies characteristics are shown in Tables 4 and 6. Note: When VUSBIN =1 , UVBUS will be connected via internal switches to VINUSB and incur some current drain on that pin, as much as 270 μA maximum, so care must be taken to disable this path and set this SPI bit (VUSBIN) to 0 to minimize current drain, even if SWBST and/or VUSB are disabled. VUSB REGULATOR VUSB2 is implemented with an integrated PMOS pass FET and has a dedicated supply pin VINUSB2. The pin VINUSB2 should always be connected to BP, even in case the regulators are not used by the application. The nominal output voltage of this regulator (VNOM as referred in Table 4) can be programmed to be 2.400, 2.600, 2.700, and 2.775 V with a load capability of 50 mA. GEN1, GEN2 AND GEN3 REGULATORS General purpose LDOs VGEN1, VGEN2, and VGEN3 are provided for expansion of the power tree, to support peripheral devices which could include WLAN, BT, GPS, or other functional modules. All the regulators include programmable set points for system flexibility. At the 1.2 V and 1.5 V set points, both VGEN1 and VGEN2 can be powered from an external buck switcher (2.2 V typ), for an

58 Freescale Semiconductor

available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. capability of 200 mA when working with an external PNP. that the GPO driver stage is at high impedance at power up. The 13892 supports single path and serial path charging. the battery and therefore always has to be present and valid. as for measuring the battery thermistor and die temperature. Table 16. 13892 General Purpose Outputs Electrical Characteristics

available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. Figure 11. 13892 Charge Path M2 become non-conducting if the charger voltage is too high. charge LED indicator are optional. voltage and programmable current limit. output voltage is programmable by SPI from 3.8 to 4.45 V. current is programmable by SPI from 0 to 1600 mA. additional cause for charger removal detection. protection circuit to reconnect the battery cell. value decreases over temperature.

Analog Integrated Circuit Device Data

60 Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. CHARGE LED INDICATOR Since normal LED control via the SPI bus is not always possible in the standalone operation, a current sink is provided at the CHRGLED pin. The driver at CHRGLED serves as the trickle (sign of life) LED and will be activated when standalone charging is started, and will remain on also when the device is powered on, until the charger is programmed by SPI. MODES OF OPERATION REVERSE SUPPLY MODE The battery voltage can be applied to an external accessory via the charge path. The path is only established if the normal charge path is disabled. The turn on of M1 and M2 is intentionally slow. The current through the accessory supply path is monitored via the charge path sense resistor R2. It can be read out via the ADC. The accessory supply path is disabled and an interrupt CHGSHORTI is generated when the slow threshold or the fast threshold is crossed. The reverse path is disabled when a current reversal occurs, and an interrupt CHREVI is generated. This function operates up to 40°C. STANDALONE CHARGING A standalone charge mode of operation is provided to minimize software interaction. It also allows that a completely discharged battery can be revived without processor control. This is especially important when charging from a USB host or when the optional transistor M3 is not placed. SOFTWARE CONTROLLED CHARGING The charger can also be operated under software control. In this mode, full control of the charger settings is assumed by software; the state machine will no longer determine the mode of charging. FACTORY MODE In factory mode, power is provided to the application with no battery present. It is not a situation which should occur in the field. The factory mode is differentiated from a USB Host by, in addition to a valid VBUS, a UID being pulled high to VBUS level during the attach, See Connectivity (USB Interface) on page 63. USB LOW POWER BOOT USB low power boot allows the application to boot with a dead battery within the 100 mA USB budget, until the processor has negotiated for the full current capability. This mode expedites the charging of the dead battery and allows the software to bring up the LCD display screen with the message “Charging battery”. PROTECTION FUNCTIONS OVER-VOLTAGE PROTECTION In order to protect the application, the voltage at the CHRGRAW pin is monitored. When crossing the threshold (16 V high to low and low to high), the charge path regulator will be turned off by opening the mosfets connected to pins CHRGCTRL1 and CHRGCTRL2. An interrupt CHGFAULTI is generated with the associated CHGFAULTM mask bit. In order to ensure immediate protection, the control of M1, M2, and M3 occurs in real time. The UVBUS pin is also protected against over-voltages. This will occur at much lower levels then for CHRGRAW. When a VBUS over-voltage is detected the internal circuitry of the USB block is disconnected. An USBOVI is generated in this case. When the maximum voltage of the IC is exceeded, damage will occur to the IC, and the state of the mosfets connected to pins CHRGCTRL1 and CHRGCTRL2 cannot be guaranteed. If one wants to protect against these failure conditions, additional protection will be required. The same is valid for charger polarity inversion protection. OVER-POWER DISSIPATION PROTECTION Since the charge path operates in a linear fashion, the dissipation can be significant and care must be taken to ensure that the external pass FETs M1 and M2 are not over dissipating when charging. By default, the charge system will protect against this by a built in power limitation circuit.This circuit will monitor the voltage drop between CHRGRAW and CHRGISNS, and the current through the external sense resistor connected between CHRGISNS and BPSNS. When required, a duty cycle is applied to the FETs connected on CHRGCTRL1 and CHRGCTRL2, and thus the charge current, in order to stay within the power budget. At the same time the FET connected to BATTFET pin is forced to conduct to keep the application powered. In case of excessive supply conditions, the power limiter minimum duty cycle may not be sufficiently small to maintain the actual power dissipation within budget. In that case, the charge path will be disabled and the CHGFAULTI interrupt generated. The power budget can be programmed by the SPI through the PLIM[1:0] bits, which establishes a power limit from 600 to 1200 mW in 200 mV steps. The power dissipation limiter can be disabled by setting the PLIMDIS bit. In this case, it is advised to use close software control to estimate the dissipated power in the external pass FETs. The power limiter is automatically disabled in serial path factory mode and in reverse mode. Since a charger attachment can be a Turn On event when a product is initially in the Off state, any nondefault settings that are intended for PLIM[1:0] and PLIMDIS should be programmed early in the configuration sequence to ensure proper supply conditions adapted to the application. To avoid any false detection during power up, the power limiter output is blanked at the start of the charge cycle. As a safety

Analog Integrated Circuit Device Data Freescale Semiconductor 61 13892 FUNCTIONAL DEVICE OPERATION Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. precaution, the power dissipation is monitored and the desired duty cycle is estimated. When this estimated duty cycle falls below the power limiter minimum duty cycle, the charger circuit will be disabled. ADC SUBSYSTEM The ADC core is a 10 bit converter. The ADC core and logic run on 2/3 of the switcher PLL generated frequency, so approximately 2.0 MHz. If an ADC conversion is requested while the PLL is not active, it will be automatically enabled by the ADC. A 32.768 kHz equivalent time base is derived from the 2.0 MHz clock to time ADC events. The ADC is supplied from VCORE. The ADC core has an integrated auto calibration circuit which reduces the offset and gain errors. The switcher PLL is programmable, so when the switcher frequency is changed, the frequency applied to the ADC converter will change accordingly. Although the conversion time is inversely proportional to the PLLX[2:0] setting, this will not influence the ADC performance. The locally derived 32.768 kHz will remain constant in order to not influence the different timings depending on this time base. The ADC Subsystem has 8 channels: Channel 0 Battery Voltage: The battery voltage is read at the BATT pin at channel 0. Channel 1 Battery Current: The current flowing out of and into the battery can be read via the ADC by monitoring the voltage drop over the sense resistor between BATT and BATTISNSCC. Channel 2 Application Supply: The application supply voltage is read at the BP pin at channel 2. Channel 3 Charger Voltage: The charger voltage is measured at the CHRGRAW pin at channel 3. Channel 4 Charger Current: The charge current is read by monitoring the voltage drop over the charge current sense resistor. This resistor is connected between CHRGISNS and BPSNS. Channel 5 ADIN5, Battery Thermistor and Battery Detect: On channel 5, ADIN5 may be used as a general purpose input, but in a typical application, ADIN5 is used to read out the battery pack thermistor. The thermistor will have to be biased with an external pull-up to a voltage rail greater than the ADC input range. In order to save current when the thermistor reading is not required, it can be biased from one of the general purpose IOs such as GPO1. A resistor divider network should assure the resulting voltage falls within the ADC input range, especially when the thermistor check function is used. When the application is on and supplied by the charger, a battery removal can be detected by a battery thermistor presence check. When the thermistor terminal becomes high-impedance, the battery is considered being removed. This detection function is available at the ADIN5 input. Channel 6 ADIN6 and Coin Cell Voltage: On channel 6, ADIN6 may be used as a general purpose unscaled input but in a typical application, the PA thermistor is connected here. In addition, on channel 6, the voltage of the coin cell connected to the LICELL pin can be read. Channel 7 ADIN7 and ADIN7B, UID and Die Temperature: On channel 7, ADIN7 may be used as a general purpose input. In a typical application, an ambient light sensor is connected here. A second general purpose input ADIN7B is available. In the application, a second ambient light sensor is supposed to be connected here. In addition, on channel 7, the voltage of the USB ID line connected to the UID pin and the die temperature can be read. COULOMB COUNTER As discussed previously, the current into and from the battery can be read out through the general purpose ADC as a voltage drop over the R1 sense resistor. Together with the battery voltage reading the battery capacity can be estimated. A more accurate battery capacity estimation can be obtained by using the integrated Coulomb Counter. The Coulomb Counter (or CC) monitors the current flowing in/out of the battery by integrating the voltage drop across the battery current sense resistor R1, followed by an A to D conversion. The result of the A to D conversion is used to increase/decrease the contents of a counter that can be read out by software.

62 Freescale Semiconductor

available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. Figure 12. 13892 Coulomb Counter Block Diagram. only after a long debounce of 1.0 second. indicating the conversion is done, and then read out the data. Table 17. 13892 Touch Screen ADC Readings

0 X position

1 X position

2 Dummy

3 Y position

4 Y position

5 Dummy

6 Contact resistance

7 Contact resistance

Analog Integrated Circuit Device Data Freescale Semiconductor 63 13892 FUNCTIONAL DEVICE OPERATION Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. The dummy conversion inserted between the different readings is to allow the references in the system to be pre- biased for the change in touch screen plate polarity and will read out as ‘0’. MODES OF OPERATION In inactive mode, the inputs TSX1, TSX2, TSY1, and TSY2 can be used as general purpose inputs. They are respectively mapped on ADC channels 4, 5, 6, and 7. In interrupt mode, a voltage is applied to the X-plate (TSX2) via a weak current source to VCORE, while the Y- plate is connected to ground (TSY1). When the two plates make contact both will be at a low potential. This will generate a pen interrupt TSI to the processor. This detection does not make use of the ADC core or the TSREF regulator, so both can remain disabled. In touch screen mode, the XY coordinate pairs and the contact resistance are read. The X-coordinate is determined by applying TSREF over the TSX1 and TSX2 pins while performing a high-impedance reading on the Y-plate through TSY1. The Y-coordinate is determined by applying TSREF between TSY1 and TSY2 while reading the TSX1 pin. The contact resistance is measured by applying a known current into the TSY1 terminal of the touch screen and through the terminal TSX2, which is grounded. The voltage difference between the two remaining terminals TSY2 and TSX1 is measured by the ADC, and equals the voltage across the contact resistance. Measuring the contact resistance helps in determining if the touch screen is touched with a finger or stylus. LED DRIVERS FOR LIGHTING SYSTEM BACKLIGHT LED DRIVERS The lighting system includes backlight drivers for main display, auxiliary display, and keypad. The backlight LEDs are configured in series and supplied from an inductive boost supply See Boost Converters on page 53. Three additional drivers are provided for RGB or general purpose signaling. Ramp up and ramp down patterns are implemented in hardware to reduce the burden of real time software control via the SPI, to orchestrate dimming and soft start lighting effects. These patterns are guaranteed by design. The current level is programmable in a low range mode and in a high range mode from 0 to 21 mA and from 0 to 42 mA respectively. This facilitates the current setting, in case two or more serial LED strings are connected in parallel to the same driver, or when using super bright LEDs. The boost switcher SWLED supplying the backlight LEDs is shared between all three backlight drivers. However, a maximum of only two backlight drivers can be activated at the same time, for instance the main display plus keypad. If all three backlight drivers are enabled meaning none of the duty cycles equals 0/32, then none of the drivers will be activated. SIGNALING LED DRIVERS The signaling LED drivers LEDR, LEDG, and LEDB are independent current sink channels. Each driver channel features programmable current levels from 0 to 21 mA as well as programmable PWM duty cycle settings. By a combination of level and PWM settings, each channel provides flexible LED intensity control. By driving LEDs of different colors, color mixing can be achieved. Blue LEDs or bright green LEDs require more headroom than red and normal green signal LEDs. In the application, a 5.0 V or equivalent supply rail is therefore required. This is provided by the integrated boost converter SWBST. As with the backlight driver channels, the signaling LED drivers include ramp up and ramp down patterns are implemented in hardware. In addition, programmable blink rates are provided. Blinking is obtained by lowering the PWM repetition rate of each of the drivers, while the on period is determined by the duty cycle setting. To avoid high frequency spur coupling in the application, the switching edges of the output drivers are softened." CONNECTIVITY (USB INTERFACE) The 13892 contains the regulators required to supply the PHY contained in the i.MX51, i.MX37, i.MX35, and i.MX27 processors. The regulators used to power the external PHY in the i.MX51 and i.MX37 are VUSB, VUSB2, and VUSB for the i.MX35 and i.MX27 processors. The IC also provides the 5.0 V supply for USB OTG operation. The USB interface may be used for portable product battery charging. Finally included are comparators/detectors for VBUS and ID detection. VBUS is the power rail of the USB cable that must be connected to the UVBUS pin. The USB interface is illustrated in Figure 13.

64 Freescale Semiconductor

available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. Figure 13. 13892 USB Interface Block Diagram for each UID condition as well. order to allow a portable device to take the role of a USB host. the VUSBIN pin as long as VBUSEN pin is a logic high = 1.

Detecting the attachment and removal of USB devices.
Managing control flow between the host and USB devices.
Managing data flow between the host and USB devices.
Collecting status and activity statistics.
Providing power to attached USB devices. When working in host mode, VUSB is supplied from the VBUS wire of the USB cable (VBUS). Parameter Condition Min Typ Max Units VBUS input impedance As A_device 40 100 KΩ UID 220K Pull-up(57) IDPUCNTRL=0, Resistor to VCORE 132 220 308 KΩ UID Pull-up(57) IDPUCNTRL=1, Current source from VCORE 4.75 5 5.25 uA UID Parallel Pull-up(57) ID100KPU=1, Resistor to VCORE 60 100 140 KΩ Notes 57. Note that the UID Pull-ups are not mutually exclusive of each other, they are independently controlled by their enable bits and thus multiple pull-ups can be engaged simultaneously.

Analog Integrated Circuit Device Data

66 Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. OPERATIONAL MODES The following are text descriptions of the power states of the system with additional details of the state machine to complement Figure 14. Note that SPI control is only possible in the Watchdog, On, and User Off Wait states, and that the interrupt line INT is kept low in all states except for Watchdog and On. OFF If the supply at BP is above the UVDET threshold, only the IC core circuitry at VCOREDIG and the RTC module are powered. All other supplies are inactive. To exit the Off mode, a valid turn on event is required. No specific timer is running in this mode. If the supply at BP is below the UVDET threshold, no turn on events are accepted. If a valid coincell is present, the core gets its power from LICELL. The only active circuitry is the RTC module, and the BP greater than UVDET detection. COLD START This is entered upon a Turn On event from Off, Warm Boot, successful PCUT, or Silent System Restart. The first 8.0 ms are used for initialization which includes bias generation, PUMS / configuration latching, and qualification of the input supply level BP. The switchers and regulators are then powered up sequentially to limit the inrush current. The reset signals RESETB and RESETBMCU are kept low. The Reset timer starts running when entering Cold Start. The input control pins WDI and STANDBYx are ignored. WATCHDOG The system is fully powered and under SPI control. RESETB and RESETBMCU are high. The Watchdog timer starts running when entering the Watchdog state. When expired, the system transitions to the On state, where WDI will be checked and monitored. The input control pins WDI and STANDBYx are ignored while in the Watchdog state. ON The system is fully powered and under SPI control. RESETB and RESETBMCU are high. The WDI pin must be high to stay in this mode. USER OFF WAIT The system is fully powered and under SPI control. The WDI pin no longer has control over the part. The Wait mode is entered by a processor request for User Off. The Wait timer starts running when entering User Off Wait mode. This leaves the processor time to suspend or terminate its tasks. MEMORY HOLD AND USER OFF (LOW POWER OFF STATES) As noted in the User Off Wait description, the system is directed into low power Off states, based on a SPI command in response to an intentional Turn Off by the end user. The only exit then will be a Turn On event. To an end user, the Memory Hold and User Off states look like the product has been shut down completely. However, a faster startup is facilitated by maintaining external memory in self-refresh mode (Memory Hold and User Off mode), as well as powering portions of the processor core for state retention (User Off only). MEMORY HOLD RESETB and RESETBMCU are low, and both CLK32K and CLK32KMCU are disabled (CLK32KMCU active if DRM is set). Upon a Turn On event, the Cold Start state is entered, the default power up values are loaded, and the MEMHLDI interrupt bit is set. A Cold Start out of the Memory Hold state will result in shorter boot times compared to starting out of the Off state, since software does not have to be loaded and expanded from flash. The startup out of Memory Hold is also referred to as Warm Boot. No specific timer is running in this mode. USER OFF RESETB is low and RESETBMCU is kept high. The 32 kHz peripheral clock driver CLK32K is disabled; CLK32KMCU (connected to the processor’s CKIL input) is maintained in this mode, if the CLK32KMCUEN and USEROFFCLK bits are both set, or if DRM is set. Any peripheral loading on SW1 and/or SW2 should be isolated from the output node(s) by the PWGT1 switch, which opens in both low power Off modes, due to the RESETB transition. In this way, leakage is minimized from the power domain, maintaining the processor core. Since power is maintained for the core (which is put into its lowest power state), and since MCU RESETBMCU does not trip, the processor’s state may be quickly recovered when exiting USEROFF upon a Turn On event. The CLK32KMCU clock can be used for very low frequency / low power idling of the core(s), minimizing battery drain while allowing a rapid recovery from where the system left off before the USEROFF command. Upon a Turn On event, Warm Start state is entered, and the default power up values are loaded. A Warm Start out of User Off will result in an almost instantaneous startup of the system, since the internal states of the processor were preserved along with external memory. No specific timer is running in this mode. WARM START Entered with a Turn On event from User Off. The first 8.0 ms is used for initialization which includes bias generation, PUMS latching, and qualification of the input

Analog Integrated Circuit Device Data Freescale Semiconductor 67 13892 FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. supply level BP. The switches and regulators are then powered up sequentially to limit the inrush current. RESETB is kept low and RESETBMCU is kept high. CLK32KMCU is kept active if CLK32KMCU was set. The reset timer starts running when entering Warm Start. When expired, the Warm Start state is exited for the Watchdog state, a WARMI interrupt is generated, and RESETB will go high. INTERNAL MEMHOLD POWER CUT Power Cut description: When the supply at BP drops below the UVDET threshold due to battery bounce or battery removal, the Internal MemHold Power Cut mode is entered and a Power Cut (PCUT) timer starts running. The backup coin cell will now supply the RTC as well as the on chip memory registers and some other power control related bits. All other supplies will be disabled. Internal MemHold Power Cut: As previously described, a momentary power interruption will put the system into the Internal MemHold Power Cut state if PCUTs are enabled. The backup coin cell will now supply 13892’s core along with the 32 k crystal oscillator, the RTC system and coin cell backed up registers. All regulators and switchers will be shut down to preserve the coin cell and RTC as long as possible. Both RESETB and RESETBMCU are tripped, bringing the entire system down along with the supplies and external clock drivers, so the only recovery out of a Power Cut state is to reestablish power and initiate a Cold Start. POWER SAVING SYSTEM STANDBY A product may be designed to go into DSM after periods of inactivity, such as if a music player completes a play list and no further activity is detected, or if a gaming interface sits idle for an extended period. Two Standby pins are provided for board level control of timing in and out of such deep sleep modes. When a product is in DSM it may be able to reduce the overall platform current by lowering the switcher output voltage, disabling some regulators, or forcing GPOx low. This can be obtained by SPI configuration of the Standby response of the circuits along with control of the Standby pins. To ensure that shared resources are properly powered when required, the system will only be allowed into Standby when both the application processor (which typically controls the STANDBY pin) and peripherals (which typically control the STANDBYSEC pin) allow it—this is referred to as a Standby event. REGULATOR MODE CONTROL The regulators with embedded pass devices (VDIG, VPLL, VIOHI, VUSB, VUSB2, and VAUDIO) operate in two modes: a normal mode, and a low power mode. The transition between both modes occurs automatically, based on the load current. Therefore, no specific control is required to put these regulators in a low power mode (i.e., “On” implies an adaptive mode control” based on load current). Bits are reserved in case the automatic scheme shows to be insufficient. The regulators with external pass devices (VSD, VVIDEO, VGEN1, and VGEN2) can also operate in a normal and low power mode. However, since a load current detection cannot be performed for these regulators, the transition between both modes is not automatic, and is controlled by setting the corresponding mode bits for the operational behavior desired. The regulators VGEN3, and VCAM can be configured for using the internal pass device or external pass device as explained in LDOs on page 54. Therefore, depending on the configuration selected, the automatic low power mode is or is not available. BUCK SWITCHERS Operational modes of the Buck switchers can be controlled by direct SPI programming, altered by the state of the STANDBY pins, by direct state machine influence (i.e., entering Off or low power Off states, for example), or by load current magnitude when so configured. Available modes include PWM with No Pulse Skipping (PWM), PWM with Pulse Skipping (PWMPS), Pulse Frequency Mode (PFM), and Off. The transition between the two modes PWMPS and PFM can occur automatically based on the load current (auto). Therefore, no specific control is required to put the switchers in a low power mode. When the buck switchers are not configured in the auto mode, power savings may be achieved by disabling the switchers when not needed, or running them in PFM mode, if loading conditions are light enough. SW1, SW2, SW3, and SW4 can be configured for mode switching with STANDBY or autonomously, based on load current with adaptive mode control (Auto). Additionally, provisions are made for maintaining PFM operation in USEROFF and MEMHOLD modes, to support state retention for faster startup from the low power Off modes, for Warm Start or Warm Boot. POWER GATING SYSTEM The low power Off states are provided to allow faster system booting from two pseudo Off conditions: Memory Hold, which keeps external memory powered for self refresh, and User Off, which keeps the processor powered up for state retention. For reduced current drain in low power Off states, parts of the system can benefit from power gating, to isolate the minimum essentials for such operational modes. It is also necessary to ensure that the power budget on backed up domains is within the capabilities of switchers in PFM mode. An additional benefit of power gating peripheral loads during system startup is to enable the processor core to complete booting and begin running software before additional supplies or peripheral devices are powered. This allows system software to bring up the additional supplies and close power gating switches in the most optimum order

Analog Integrated Circuit Device Data

68 Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. to avoid problems with supply sequencing or transient current surges. The power gating switch drivers and integrated control are included for optimizing the system power tree. The power gate drivers could be used for other general power gating as well. The text herein assumes the standard application of PWGT1 for core supply power gating and PWGT2 for Memory Hold power gating. USER OFF POWER GATING User Off configuration maintains PFM mode switchers on both the processor and external memory power domains. PWGTDRV1 is provided for power gating peripheral loads sharing the processor core supply domain(s) SW1, and/or SW2, and/or SW3. In addition, PWGTDRV2 provides support to power gate peripheral loads on the SW4 supply domain. In a typical application, SW1, SW2, and SW3 will be kept active for the processor modules in state retention, and SW4 will be retained for the external memory in self refresh mode. SW1, SW2, and SW3 power gating FETs drive would typically be connected to PWGTDRV1 (for parallel NMOS switches). The SW4 power gating FET drive would typically be connected to PWGTDRV2. When low power Off mode is activated, the power gate drive circuitry will be disabled, turning off the NMOS power gate switches, to isolate the maintained supply domains from any peripheral loading. MEMORY HOLD POWER GATING As with the User Off power gating strategy described previously, Memory Hold power gating is intended to allow isolation of the SW4 power domain to selected circuitry in low power modes, while cutting off the switcher domain from other peripheral loads. The only difference is that processor supplies SW1, and/or SW2, and/or SW3 are shut down in Memory Hold, so just the external memory is maintained in self-refresh mode. An external NMOS is to be placed between the direct- connected memory supply and any peripheral loading. The PWGTDRV2 pin controls the gate of the external NMOS, and is normally pulled up to a charge pumped voltage (~5.0 V). During Memory Hold or User Off, PWGTDRV2 will go low to turn off the NMOS switch and isolate memory on the SW4 power domain. POWER DISSIPATION During operation, the temperature of the die should not exceed the maximum junction temperature. Depending on the operating ambient temperature and the total internal dissipation, this limit can be exceeded. To optimize the thermal management scheme and avoid overheating, the 13892 provides a thermal management system. The thermal protection is based on a circuit with a voltage output that is proportional to the absolute temperature. This voltage can be read out via the ADC for precise temperature readouts (See Functional Device Operation). THERMAL PROTECTION Thermal protection is integrated to power off the 13892 and disable the charger circuitry in case of over dissipation. This thermal protection will act above the maximum junction temperature to avoid any unwanted power downs. The protection is debounced by one period of the 32kHz clock in order to suppress any (thermal) noise. This protection should be considered as a fail-safe mechanism and therefore the application design should be dimensioned such that this protection is not tripped under normal conditions. The temperature thresholds are listed in the last section of Table 4.

available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. Figure 15. 13892 Typical Application

Analog Integrated Circuit Device Data

70 Freescale Semiconductor

Analog Integrated Circuit Device Data Freescale Semiconductor 71 13892 PACKAGING PACKAGE DIMENSIONS Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. VK SUFFIX 139-PIN 98ASA10820D REVISION 0

Analog Integrated Circuit Device Data

72 Freescale Semiconductor

Analog Integrated Circuit Device Data Freescale Semiconductor 73 13892 PACKAGING PACKAGE DIMENSIONS Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages. UNRELEASED DOCUMENT PDF CREATED: 11 JUL 2008, 2:23 PM VL SUFFIX 186-PIN 98ASA10849D REVISION 0

Analog Integrated Circuit Device Data

74 Freescale Semiconductor

REVISION HISTORY

How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516

2100 East Elliot Road

Tempe, Arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7

81829 Muenchen, Germany

+44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor China Ltd. Exchange Building 23F No. 118 Jianguo Road Chaoyang District Beijing 100022 China +86 10 5879 8000 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. All rights reserved. MC13892 Rev. 2.0 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: MC13892VK and MC13892VL in 139, 186 MAPBGA packages.

Product Information

PC13892VK/R2 specifications and overview.

Summary

Power Management and User Interface IC

Description

Power Management and User Interface IC

Source title PC13892VK/R2 Datasheet(PDF) - Freescale Semiconductor, Inc

Related Parts

More parts from the same family.

Browse manufacturer