MC13180 MOTOROLA | Alldatasheet
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PC13180FC PC13180FC QFN-48
Package Information
(QFN-48) This document contains information on a product under dev elopment. Motorola reserves the right to change or discontinue this product without notice. © Motorola, Inc., 2002. All rights reserved. The MC13180 2.4 GHz Low Power Wireless Transceiver for Bluetooth™ is a part of the comprehensive Bluetooth platform from Motorola that provides a complete, low-power Bluetooth Radio System for Bluetooth Class 1 or 2 power systems. The design is based on Motorola's third-generation Bluetooth architecture that has set the industry standard for interoperability, complete functionality, and compliance with the Bluetooth specification. When combined with a specified Motorola baseband controller such as the MC71000 or MC9328MX1, a complete Bluetooth solution can be realized. The MC13180 provides a unique combination of sensitivity, excellent C/I performance, and low power consumption. These performance parameters are extremely important to maintaining a robust link in high RF interference environments such as mobile phones, high density Bluetooth networks, 802.11b networks, microwave ovens, etc.
- Power Supply Range: 2.5 to 3.1 V
- Low Current Drain in Transmit (27 mA Peak) or Receive (37 mA Peak) Mode
- Minimum External Components
- Low IF Receiver with On -Chip Filters
- Fully Integrated Demodulator with A/D
- Direct Launch Transmitter
- M u l t i -Accumulator, Dual-Port, Fractional-N Synthesizer
- RSSI with A/D
- Bluetooth Class I Compatible
- Crystal Independent (12 to 15 MHz) Reference Oscillator or 12 to 26 MHz if supplied externally Product Preview MC13180PP/D Rev. 2, 08/2002
2.4 GHz Low Power
for Bluetooth™
Applications
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Figure 1. Simplified Block Diagram This device contains 81,604 active transistors.
24 MHz
2.5 GHz
Figure 2. Device Pinout
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Electrical Characteristics
1 Electrical Characteristics
Table 1. Maximum Ratings NOTES: 1. Maximum Ratings are those values beyond which damage to the device may occur. Conditions and Electrical Characteristics tables.
- Meets Human Body Model (HBM) ≤2.0 kV and Machine Model (MM) ≤200 V except RF & I/O Pins = 50 V MM,
RF Pins = 100 V HBM, and I/O Pins <500 V. RF pins have no ESD protection. Additional ESD data available upon request. Table 2. Recommended Operating Conditions Table 3. Digital DC Electrical Specifications
MOTOROLA MC13180 Product Preview 5 Radio Power Supply Current Transmit, 1 Slot Transmit, 3 Slot Transmit, 5 Slot Transmit, Continuous ICCRFtx1 ICCRFtx3 ICCRFtx5 ICCRFtxc mA Radio Power Supply Current Receive, 1 Slot Receive, 3 Slot Receive, 5 Slot Receive, Continuous ICCRFrx1 ICCRFrx3 ICCRFrx5 ICCRFrxc 47.5 mA Output Voltage Low SDATA, CLK, FS, RFDATA ILoad = 0 µA ILoad = 100 µA VOL 0.2 x VDDINT mV V Output Voltage High SDATA, CLK, FS, RFDATA ILoad = 0 µA ILoad = 100 µA V OH 0.8 x VDDINT 1.78 V Output Voltage Low EPAEN, GPO ILoad = 0 µA ILoad = 100 µA VOL 0.2 x VCCRF mV V Output Voltage High EPAEN, GPO ILoad = 0 µA ILoad = 100 µA V OH 0.8 x VCCRF 2.68 V Input Voltage Low RES, CE, SDATA, SCK, RFDATA, RTXEN VIL -0 0 . 3 x VDDINT V Input Voltage High RES, CE, SDATA, SCK, RFDATA, RTXEN VIH 0.7 x VDDINT VDDINT -V Input Current RES, CE, SDATA, SCK, RFDATA, RTXEN, Vin = 0 V or 1.8 V Iin -± 1 . 0-µ A Table 3. Digital DC Electrical Specifications (Continued)
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Table 4. EPA DAC Electrical Specifications Table 5. Digital AC Electrical Specifications
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RSSI Conversion Value, (R4/6 and R9/8 = 1) RF level at LNA input to maintain conversion value of: 1000 1111 RSSI -60 -56 -70 -52 -66 dBm RSSI Resolution (R4/6 and R9/8 = 1) RSSI res -1 . 8- d B / b i t RSSI Dynamic Range 20 - - dB RSSI Average Supply Current (R4/6 and R9/8 = 1) -4 0- µA Table 7. Transmitter AC Electrical Specifications Register bit settings according to Figure 4, TA = -20 to 85°C, unless otherwise noted. Measurements made at PAout. Table 6. Receiver AC Electrical Specifications (Continued)
MOTOROLA MC13180 Product Preview 9 Transmitter Center Frequency Drift One-slot packet Three-slot packet Five-slot packet -25 -40 -40 ±3.0 ±6.0 ±6.0 ±25 ±40 ±40 kHz Maximum Frequency Drift Dmax - 3.0 20 20 kHz/ 50 µs PA Output Impedance S22 See Table 23 dB Table 8. Receiver AC Electrical Specifications Register bit settings according to Figure 4, TA = -20 to 85°C, unless otherwise noted. Measurements made at PAout. Table 7. Transmitter AC Electrical Specifications (Continued) Register bit settings according to Figure 4, TA = -20 to 85°C, unless otherwise noted. Measurements made at PAout.
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Table 9. MC7100/MC13180 Receive Characteristics Table 10. Reference Oscillator Receive Characteristics
26 MHz, R11/0 = 0 or 1)
MOTOROLA MC13180 Product Preview 11 Input Bias Voltage (Base) - 1.2 - V Start-up Time (using Crystal) T WAIT -7 . 5- m s Table 11. Data Clock Electrical Specifications Table 12. SPI AC Electrical Specifications Table 10. Reference Oscillator Receive Characteristics (Continued)
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Figure 3. Test Circuit
13 MHz
2.45 GHz
MOTOROLA MC13180 Product Preview 13 Figure 4. Register Map
16 Bit Frac-N Numerator Divide Value - num
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Figure 4 Register Map (continued) $13 $14 $15 $16 $17 $18 $19 $1A $1B $1C Read Only $1D Read Only M SB RSSI Conversion LSB $1E Read Only Bit 3:0 of Part Num ber LSB M anuf. ID (continuation code) M SB M anuf. ID (non-continuation code) LSB $1F Read Only M SB Version Num ber LSB M SB Bit 15:4 of Part Num ber
2 Pin Connections
Table 13. Pin Function Description
1 GNDLNA GNDLNA, Negative supply
2 RFIN RFIN
3 GNDLNA GNDLNA, Negative supply
48 VCCLNA VCCLNA, Positive supply
GNDLNA at the pin of the IC.
4 EPAEN EPAEN
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7 GNDPA GNDPA, Negative Supply
6 PA+ PA +
Positive differential PA output. matching network is desired.
8 PA - PA -
Negative differential PA output. matching network is desired.
9 GPO GPO
control an external T/R Switch.
10 EPADAC EPADAC
Table 13. Pin Function Description (Continued)
11 TIN + TIN +
This pin is for factory use only. It can be grounded or left open.
12 TIN - TIN -
This pin is for factory use only. It can be grounded or left open.
13 TOUT + TOUT +
This pin is for factory use only.
14 TOUT - TOUT -
This pin is for factory use only.
15 GNDLIM GNDLIM, Negative supply
16 VCCLIM VCCLIM, Positive supply
GNDLIM at the pin of the IC.
17 GNDDEM GNDDEM, Negative supply
18 VCCDEM VCCDEM, Positive supply
GNDDEM at the pin of the IC.
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19 GNDX GNDX
Reference oscillator ground.
20 BASE BASE
21 EMM EMM
Reference oscillator emitter.
22 COLL COLL
Reference oscillator collector. The collector is tied to VCC.
23 DCVCO DCVCO
24 DCCP DCCP
25 VCCDC VCCDC
26 RTXEN RTXEN
Shown for 13 MHz reference oscillator.
27 RFDATA RFDATA
28 FS FS
29 CLK CLK
30 SCK SCK
27 VDDINT
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31 SDATA SDATA
32 CE CE
33 RES RES
34 VDDINT VDDINT
Digital interface supply voltage.
35 VDD VDD
36 VSS VSS
31 VDDINT
38 GNDCP GNDCP
37 VCCCP VCCCP
Main frac-N charge pump VCC.
39 MLPF MLPF
41 GNDPRE GNDPRE
40 VCCPRE
42 VCCVCO VCCVCO
GNDVCO at the pin of the IC.
43 GNDVCO
44 GNDMOD GNDMOD
45 VCCMOD VCCMOD
47 GNDMIX GNDMIX
46 VCCMIX VCCMIX
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Figure 5. Equivalent Internal Circuit for Pins 5, 6, 7, and 8
3 Typical DC Performance Characteristics
Figure 6. Logic Interface Current versus Logic Figure 7. Continuous Transmit Current versus Figure 8. Continuous Transmit Current versus Figure 9. Continuous Receive Current versus Figure 10. Continuous Receive Current versus Temperature
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4 Functional Description
Note: In the following description, control bits contained in the MC13180 register map for various functions will be identified by register number and bit number(s). For example, bit R4/8 references bit 8 of register 4 while R5/9 -3 identifies bits 9 through 3, inclusive, of register 5 (decimal notation). Unless otherwise noted, a default register map configuration as listed in Figure 4 is assumed.
4.1 Overview
The MC13180 is a complete RF transceiver for Bluetooth applications. The device, when coupled with an MC71000 controller or any controller containing an integrated Joint Detection/Minimum Length Sequence Estimator (JD/MLSE) digital decoder, exhibits superior RF performance with small size and low cost. Only minimal external components are required to complete the RF link of a Bluetooth system.
4.2 MC13180 States
Figure 11 illustrates the various states which the MC13180 can assume. A description of each state follows.
4.3 OFF State
In the OFF state, no power is being applied to the V CCRF or VDDINT of the device. During this state, all digital inputs should be held at ground to avoid forward biasing internal ESD diodes.
4.4 POWER UP State
During this state, power is applied to the device in an orderly fashion. All digital inputs should continue to be held at ground. Since V DDINT of the device must always be less than or equal to the V CCRF supplied to the device, it is generally desired to first allow the VCCRF to rise and stabilize, then follow with applying the V DDINT supply. This prevents internal protection diodes from forward biasing. SPI operations are not allowed during this state.
4.5 RESET State
The RESET state can be entered at any time from any state with the exception of the OFF and POWER UP states. During the RESET state, SPI operations are forbidden. The RESET state places the entire contents of the internal register map into a known condition. All digital outputs are active and driven to a logic low. The SDATA I/O pin is configured as an input, and the RFDATA I/O pin is configured as an output. The crystal oscillator is inactive and therefore the CLK output remains at a static low level.
4.6 CONFIG State
Once the RES pin is de-asserted, the crystal oscillator and data clock PLL of the device become active. The CLK output will attempt to synthesize a clock frequency based upon the crystal oscillator frequency and values loaded into the data clock N and R registers. These values assume an initial reference frequency of 13 MHz and the data clock values are initialized from reset to synthesize 24 MHz from this reference.
MOTOROLA MC13180 Product Preview 25 During the Config state, any address location can be read or written. The Sleep Enable, Tx Enable, and Rx Enable bits of the register map must remain at a logic zero, otherwise the register map is typically loaded with user defined default values.
4.7 WAIT XTAL State
During this state, the crystal oscillator and data clock PLL are stabilizing. If an external reference oscillator is being used, the data clock PLL must still be allowed to settle. Stability will be achieved after T WAIT, at which time the Idle state is entered.
4.8 IDLE State
In the Idle state, the CLK output supplies a synthesized 24 MHz output. Any SPI operation is allowed during this state. RSSI information is typically read during the Idle state.
4.9 TX CONFIG State
During this state, the contents of the register map are set for any desired transmit information, including the transmit channel setting. The Tx Enable (R2/14) bit of the register map is also asserted which places the RFDATA pin into the input state at the completion of the SPI write cycle.
4.10 TX WARM UP
The MC13180 begins a series of internal warm up sequences once the RTXEN pin is asserted. SPI operations are forbidden during this state.
4.11 TX MODE
Data presented to the RFDATA pin is transmitted to the PA output of the device. SPI operations are forbidden during this state. The TX mode is ended by de -asserting the RTXEN pin or by going into the RESET state. SPI operations are not permitted until T TXDIS µs after the RTXEN pin is de-asserted.
4.12 RX CONFIG State
During this state, the contents of the register map are set for any desired receive information, including the receive channel setting. The Rx Enable (R2/13) bit of the register map is also asserted which places the RFDATA pin into the output state at the completion of the SPI write cycle.
4.13 RX WARM UP
The MC13180 begins a series of internal warm up sequences once the RTXEN pin is asserted. SPI operations are forbidden during this state.
4.14 RX MODE
Digitized and oversampled data from the desired receive channel is presented to the RFDATA pin and framed by the FS signal. Data is aligned to the rising edge of the CLK output. SPI operations are forbidden during this state. The RX mode is ended by de -asserting the RTXEN pin or by going into the RESET state. SPI operations are not permitted until TRXDIS µs after the RTXEN pin is de-asserted.
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4.15 SLEEP State
driven to a logic low level. Figure 11. State Diagram
1.65 V ≤ VDDINT ≤ VCCRF
MOTOROLA MC13180 Product Preview 27
4.16 Receive Data Path
The MC13180 is placed into the receive mode from the idle mode by asserting the RTXEN pin after setting the Receive Enable bit (R2/13), clearing the Transmit Enable bit (R2/14), and clearing the Narrow Bandwidth Enable bit (R2/12) (See Figure 12). The RFDATA pin of the device is configured as an output as soon as these bit conditions are loaded into the register map. The baseband interface signals used in the receive mode are shown in Table 14. The interface signal levels are internally translated to/from V DDINT to VDD. To initiate a receive cycle, the user will set the local oscillator frequency of the device in conjunction with the High/Low Injection Enable bit. Optionally, other address map values may be written or read. During this “SPI” cycle, the device's RTXEN must be de -asserted. After time TSUSPI, the RTXEN pin can be asserted. This initiates a sequence internal to the MC13180 which places it into the receive mode. Serialized, A/D data will appear at the RFDATA pin, framed by the FS pin, after TpropFS. The data represents a 6-Bit, 2’s-complement digital value and is sampled four times for every data bit. Once the receive cycle is complete, the RTXEN pin is de -asserted and the MC13180 begins an internal power down sequence.
4.17 Transmit Data Path
The MC13180 is placed into the transmit mode from the idle mode by setting the Transmit Enable bit (R2/ 14), setting the Narrow Bandwidth Enable bit (R2/12), and clearing the Receive Enable bit (R2/13) of the address map, then asserting the RTXEN pin of the device (see Figure 12). The RFDATA pin of the device is configured as an input as soon as these bit conditions are loaded into the register map. The baseband interface signals used in the transmit mode are shown in Table 14. The interface signal levels are internally translated to/from V DDINT to VDD. To initiate a transmit cycle, the user will normally set the desired channel frequency and mode bits mentioned above. Optionally, other address map values may be written or read. During this “SPI” cycle, the device's RTXEN must be de -asserted, ensuring that the device remains in idle mode. After time TSUSPI, the RTXEN pin can be asserted. This initiates a sequence internal to the MC13180 which places it into the transmit mode. Data to be transmitted must be set and stable no later than Tstb after the assertion of RTXEN. The RF data will be present at the PA output after RTXEN time, T XLAT. Subsequent serial data can then continue to be presented to the MC13180 via the RFDATA pin, and the CLK of the device (divided by 24) can be used as the system clock to synchronize the data transfer. Once the data stream has been transmitted and the time T hold is met, the RTXEN pin is de-asserted and the MC13180 begins an internal power down sequence. Since RF power is still present at the PA output, no SPI operations or additional cycles can be performed for at least T TXDIS µs. At this time, RF power is at a substantially low enough level as to not produce undesired emissions.
4.18 Transmit Synchronization Delay
A programmable delay exists between the rising edge of RTXEN and the first available bit of data. This delay range is TXsync and is set via SPI bits of Transmit Synchronization Time Delay Value (R8/15 -8) where the value represents the delay in microseconds. Packet data is seen at the antenna approximately 2.5 µs after this delay. Refer to Figure 12 for the corresponding timing diagram. All Bluetooth packets require a minimum of four preamble bits of pattern 0101 or 1010. For minimum power consumption, set the delay to TXsync minimum. If additional settling time or preamble bits are required, manipulate the delay as necessary, up to TXsync maximum.
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4.19 Main Loop Bandwidth
manner maximizes radio performance. Note that this bit is externally gated by the sequence manager. Table 14. Data Direction and Signal Description for the MC13180 Baseband Interface
Figure 12. TX and RX Cycle Timing
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4.20 Serial Peripheral Interface (SPI)
levels are internally translated to/from VDDINT to VDD. the device SPI and transfers the contents of the SPI shift register to the decoded address when de -asserted. SPI devices to be cascaded together without requiring an additional chip enable line. address field represent the target address to which information will be transferred. target address. A SPI write to address zero resets all register map values to their initial (reset) condition. address. The next five bits of the address field will be the target address to be read. reading on the falling edge of SCK. follow this condition can cause severe performance degradation. Figure 13. SPI Register Map
4.21 Crystal Oscillator
-10). Typical stray capacitance is on the order of 1.0 pF. Trim (R6/14-10) to zero to reduce the load on the external source. Additional characteristic data is shown in Figures 14 through 19. Table 15. Examples of Programmable XTAL Trim Capacitances Figure 14. Oscillator Open Loop Gain versus Figure 15. Oscillator Negative Resistance versus
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4.22 Data Clock Operation
proves to be adequate for any value of external reference frequency that is an integral multiple of 20 kHz. More details about PLL loop filters can be obtained from Motorola application note AN1253/D. Figure 16. Oscillator Negative Resistance versus Figure 17. Oscillator Negative Resistance versus Figure 18. Crystal Start-up Time versus Capacitor Figure 19. Crystal Frequency Pulling versus
13 MHz Crystal Reference
intial frequency for R/14-10 = 12 (decimal).
represent frefInternal and achieve CLK. Table 16 provides the appropriate values for various f refExternals. Additional data clock characteristic data is shown in Figures 21 and 22. Figure 20. General Model for the PLL Table 16. Data Clock R and N Counter Values for 20 kHz frefInternal with 1.0 kHz LBW
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4.23 Main Synthesizer Operation
corner frequency of approximately 140 kHz. fdev is the nominal transmit ROM frequency deviation (typically 157500 Hz). where the INT function is the integer portion of the result and REM is the remainder portion of the result. Accuracy to at least 10 decimal places is suggested. Figure 21. Data Clock Start-up Time versus Figure 22. Data Clock Start-up Time versus
4.24 Transmit ROM Operation
operation, the output of the LUT is constantly held to the value contained in R1C1. where the INT function is the integer portion of the result. Table 19 lists all values of RxCx for supported reference frequencies.
4.25 M-Dual Port Multiplier and B-Dual Port Multiplier
output of the LUT is fed to a digital multiplier prior to being presented to the input of the modulation DAC. Table 17. LUT RxCx Constants
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15-8), determines the slope, and B-Dual Port Digital Multiplier Value (R8/7-0), determines the intercept. Table 19 contains slope and intercept point values across all supported input reference frequencies.
4.26 Dual-Port Programmable Delay (R7/15-11)
Delay = 10.5 / (frefExternal) - 28 ns. Consult Table 18 for the closest available value. Table 19 lists all values of the programmable delay for supported reference frequencies. Table 18. Dual-Port Programmable Delay Values
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Table 19. Register Settings and Component Values versus Reference Frequency
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Table 19. Register Settings and Component Values versus Reference Frequency (Continued)
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Figure 23. Main PLL Synthesizer Block Diagram
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4.27 Receiver
serial data through the entire 2.4 GHz Industrial, Scientific and Medical (ISM) band. detailed discussion of each of the functional blocks within the receiver follows.
4.28 LNA
source impedance (usually 50 Ω). is active or disabled. During a receive cycle, the S11 of the LNA is shown in Table 20. The LNA can be matched to 50 Ω by a simple capacitor/inductor network as shown in Figure 24. becomes the value shown in Table 21. Table 20. S11 for LNA During Receive Table 21. S11 for LNA Disabled
provides a nominal 6.7 dB of power gain when properly matched.
4.29 High/Low Image Reject Mixer (I/R Mixer)
-chip Voltage Controlled Oscillator (VCO). Figure 25. High-Side and Low-Side Mixer Injection The mixer delivers approximately 15.8 dB of voltage gain and 22 dB of image rejection.
4.30 Post Mixer Amplifier (PMA)
dB of additional gain prior to feeding the signal into the bandpass filter.
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4.31 Bandpass Filter (BPF)
advantages are increased sensitivity, adjacent channel interference performance and ease of manufacture. referenced as the JD/MLSE, and is incorporated into all Motorola Bluetooth basebands. -assertion of the RTXEN pin or during any Idle or Transmit mode.
4.32 Limiter with Received Signal Strength Indicator (RSSI)
Idle mode. The RSSI is updated approximately 40 µs after TpropFS during a receive cycle (see Figure 12). Figure 26. RF Level versus RSSI at Temperature Figure 27. RF Level versus RSSI at V CCRF
4.34 Receiver Characteristics
the PCB ground layer. Refer to Figure 48 for additional information. Figures 28 through 34 show typical performance of the receiver for various conditions. Figure 28. Receive Sensitivity versus Figure 29. Blocking Performance versus Figure 30. C/I Performance for Channel 3 (2.405 GHz, High-Side Injection) Figure 31. C/I Performance for Channel 75 (2.477 GHz, Low-Side Injection)
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4.35 Transmitter
Figure 32. C/I Performance for Channel 39 (2.441 GHz, High-Side Injection) Figure 33. C/I Performance for Channel 39 (2.441 GHz, High-Side Injection) Figure 34. C/I Performance versus Temperature
4.36 Programmable LPA
The output power of the LPA can be varied by programming PA Bias Adjust (R5/2 -0) in the register map. detail. Figures 35 and 36 provide additional LPA characteristic data.
4.37 Ramp Generator
µs. Increasing the output power exponentially is useful to avoid splattering and minimize load pulling.
4.38 External Balun
and 42 show the physical dimensions and characteristics of this network. Table 23 shows the output impedance, S22 of the PA during active and inactive cycles. Table 22. RF Power Out versus PA Bias Adjust
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Figure 37. Balun Physical Dimensions Figure 35. RF Output Power versus Carrier Figure 36. RF Output Power versus Temperature Table 23. S22 for PA During Transmit
4.39 External Antenna Switch
Information General Purpose Output and External Power Amplifier for further discussion.
4.40 General Purpose Output (GPO) Pin
4.41 External Power Amplifier Enable (EPAEN) Pin
The External Power Amplifier Enable (EPAEN) output of MC13180 is located at Pin 4 of the device. EPAEN is not required for the desired application, it may be disabled by setting R11/6 to zero. Figure 38. Ramp Generator (Transmit Cycle) Timing Diagram
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5 Applications Information
5.1 General Purpose Output (GPO)
The GPO must be set to a logic one during a transmit cycle and set to a logic zero during a receive cycle via a SPI write operation, when driving an external antenna switch as shown in Figure 42. When the GPO is not actively used to drive a peripheral, R2/8 in the address register map is considered a don't care.
5.2 General Purpose Output Invert (GPO Invert)
The MC13180 General Purpose Output (GPO) Invert bit (R3/6) can be used to invert the output value of GPO located at Pin 9 of the device. The default setting for GPO Invert is zero (i.e., no inversion). When it is set to one, the GPO output pin assumes the inverted value of GPO in the register map location R2/8. This is a useful feature when an inverter is not available. It can serve as a complement to GPO Invert.
5.3 External Power Amplifier Enable (EPAEN)
The External Power Amplifier Enable (EPAEN) bit, R6/15, can be used in two applications. It may serve as a complementary driver to a dual -port antenna. This is accomplished when External PA Enable Invert, R3/10, is set to a logic one. In this configuration, EPAEN assumes the inverted value of GPO, which is the second driver for the antenna switch. EPAEN may also assist in Class 1 operation by setting bit R11/6 to a logic high. This setting allows the MC13180 to drive an external power amplifer. Setting bits R11/6 and R3/10 to zero disables EPAEN.
5.4 External Power Amplifier DAC (EPADAC)
The Bluetooth specification for Class 1 Power implementation requires power control from 4.0 dBm (or less) to 20 dBm (max) power. The MC13180 external power amplifier digital to analog converter (EPADAC) output (Pin 10) provides a voltage reference for power control of an external power amplifier (PA), if desired. The EPADAC output is enabled when External PA DAC Enable (R11/7) is set to one. Setting R11/7 to zero pulls the EPADAC output to ground. When enabled, the EPADAC output voltage is controlled by the PA DAC setting (R3/5 -0). The minimum EPADAC output voltage is 0 Vdc and the maximum output voltage is 3.2 Vdc. The 6-bit resolution of the PA DAC setting corresponds to approximately 50 mV/bit. When using a VCCRF < 3.2 Vdc, the maximum EPADAC output voltage is reduced to V CCRF (i.e., the full-scale output of the PA DAC is referenced to 3.2 V). To obtain optimum functionality of EPADAC with an external PA, this feature should be utilized with the External PA Enable. Refer to the Applications Information section for additional usage information. The output of the EPADAC, when enabled, is gated by the MC13180 sequence manager. During a Sleep, Idle, or RX cycle, the output is set to zero volts. The programmed value of the output voltage is only achieved during an active TX cycle as shown in Figure 38.
5.5 PIN Implementation of Antenna Switch
An alternative approach to using an RF switch is to utilize a PIN diode technique as shown in Figure 39. When both PIN diodes are in the high resistance (i.e., un -biased) state, the transmitter is isolated from the antenna and LNA input. Conversely, when both PIN diodes are in the low resistance (i.e., forward -biased)
set low. For transmit mode, GPO is set high. mode, moderate current consumption while in transmit mode, high receiver isolation, and low cost. Figure 39. PIN Implementation of Antenna Switch
5.6 Class 1 Operation
(R11/7), must be set to one.This line is generally decoupled with a small capacitor value ( ≈ 0.1 µF). Approximately 44 µs is available to fully charge this capacitor (see Figure 38).
5.7 Manufacturer Code
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Figure 41. Manufacturer Identification Code NOTE: MC13180 is used at 2.7 V, therefore EPAEN and EPADAC are 2.7 V lines that feed into the MRFIC2408. The MRFIC2408 is specified to operate at 3.0 V or above but is functional at 2.7 V with a slight degradation in performance.
4 Bits 16 Bits 4 Bits =0 7 Bits
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Figure 42. Application Evaluation Schematic
2.4 GHz BPF
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Figure 42 Application Evaluation Schematic (Continued) C25 N/C C22 100n C29 100n R10 N/C U3 TC1073-2.7VCT713 VIN GND SHDN ERROR BYPASS VOUT R11 N/C C39 RF DC Pwr 1 2 3 4 C18 6.8p C24 6.8p C26 100n C31 100n C23 2.2n R12 N/C C28 100n C38 1µF C40 470p VccMOD Vdd VccPA Vcc VccRF VccLNA VccCP VccDC VccDEMO VccMIX VccVCO VccPRE VccLIM VccRF VccXTAL For TC1071VCT Only J1 I/O Conn. 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 R13 N/C R14 N/C CLK FS NRES RTXEN NCEN SPICK RFDataIO SPID VddINT VddINT 1.0 µ MicroChip NOTE: R10 can be utilized as a regulator bypass. R11, R12, and C25 can be utilized for alternative regulator configurations.
6 Application Evaluation Printed Circuit Boards
Figure 43. Application Evaluation PCB Assembly Diagram Table 24. Application Evaluation PCB Bill of Materials
0402 N/C
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U6 SC-706 RF Switch AS179-92 Alpha Indust. Table 24. Application Evaluation PCB Bill of Materials (Continued)
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Figure 48. Recommended QFN Ground Flag Configuration intermodulation and C/I performance.
7 Packaging
Figure 49. Outline Dimensions for QFN-48
- DIMENSIONS ARE IN MILLIMETERS.
- INTERPRET DIMENSIONS AND TOLERANCES PER ASME
- THE COMPLETE JEDEC DESIGNATOR FOR THIS PACKAGE
- CORNER CHAMFER MAY NOT BE PRESENT. DIMENSIONS
OF OPTIONAL FEATURES ARE FOR REFERENCE ONLY.
- CORNER LEADS CAN BE USED FOR THERMAL OR
LEADS ARE NOT INCLUDED IN THE LEAD COUNT.
- COPLANARITY APPLIES TO LEADS, CORNER LEADS, AND
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