SN54LVT18502_08 TI1 | Alldatasheet
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3.3-V ABT SCAN TEST DEVICE WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS669 – JULY 1996 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Member of the Texas Instruments SCOPE Family of Testability Products /C0068Member of the Texas Instruments Widebus Family /C0068State-of-the-Art 3.3-V ABT Design Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V V CC ) /C0068Supports Unregulated Battery Operation Down to 2.7 V /C0068UBT (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode /C0068Bus Hold on Data Inputs Eliminates the Need for External Pullup Resistors /C0068Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture /C0068SCOPE Instruction Set – IEEE Standard 1149.1-1990 Required Instructions and Optional CLAMP and HIGHZ – Parallel-Signature Analysis at Inputs – Pseudo-Random Pattern Generation From Outputs – Sample Inputs/Toggle Outputs – Binary Count From Outputs – Device Identification – Even-Parity Opcodes /C0068Packaged in 68-Pin Ceramic Quad Flat (HV) Packages Using 25-mil Center-to-Center Spacings 1B4 1B5 1B6 GND 1B7 1B8 1B9 V CC NC 2B1 2B2 2B3 2B4 GND 2B5 2B6 2B7 1A3 1A4 1A5 GND 1A6 1A7 1A8 1A9 NC V CC 2A1 2A2 2A3 GND 2A4 2A5 2A6 V NC TMS 1CLKBA 1A2 1A1 1OEAB GND 1LEAB 1CLKAB TDO NC TCK 2CLKBA 2LEBA 2A9 GND 2OEAB 2LEAB 2CLKAB TDI 2A7 2A8 1LEBA 1OEBA GND 2OEBA 2B9 2B8 GND 1B1 1B2 1B3 HV PACKAGE (TOP VIEW) CCV CC NC – No internal connection 28 29 30 31 32 33 34 87 6 5493 1 6 8 6 7 2 35 36 37 38 39 66 65 64 63 62 61 40 41 42 43 Copyright 1996, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SCOPE, Widebus, and UBT are trademarks of Texas Instruments Incorporated. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
3.3-V ABT SCAN TEST DEVICE WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS669 – JULY 1996
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description
The SN54LVT18502 scan test device with 18-bit universal bus transceivers is a member of the Texas Instruments SCOPE testability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface. Additionally, this device is designed specifically for low-voltage (3.3-V) V CC operation, but with the capability to provide a TTL interface to a 5-V system environment. In the normal mode, this device is an 18-bit universal bus transceiver that combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, or clocked modes. It can be used either as two 9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPE universal bus transceivers. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A-bus data is latched while CLKAB is held at a static low or high logic level. Otherwise, if LEAB is low, A-bus data is stored on a low-to-high transition of CLKAB. When OEAB is low, the B outputs are active. When OEAB is high, the B outputs are in the high-impedance state. B-to-A data flow is similar to A-to-B data flow, but uses the OEBA, LEBA, and CLKBA inputs. In the test mode, the normal operation of the SCOPE universal bus transceivers is inhibited and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990. Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN54LVT18502 is characterized for operation over the full military temperature range of –55°C to 125°C. FUNCTION TABLE † (normal mode, each register) INPUTS OUTPUT OEAB LEAB CLKAB A B L L L X B0‡ L L ↑ LL L L ↑ HH L HX LL L HX HH H X X X Z † A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, and CLKBA. ‡ Output level before the indicated steady-state input conditions were established
3.3-V ABT SCAN TEST DEVICE WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS669 – JULY 1996 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 functional block diagram 2A1 Boundary-Control Register Bypass Register Identification Register Boundary-Scan Register Instruction Register TAP Controller 2LEBA 2CLKBA 2OEBA TDI TMS TCK 2B1 TDO 2OEAB 2LEAB 2CLKAB 1A1 1LEBA 1CLKBA 1OEBA 1B1 1OEAB 1LEAB 1CLKAB VCC VCC One of Nine Channels One of Nine Channels VCC VCC VCC VCC
3.3-V ABT SCAN TEST DEVICE WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS669 – JULY 1996
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1A1–1A9, 2A1–2A9 Normal-function A-bus I/O ports. See function table for normal-mode logic. 1B1–1B9, 2B1–2B9 Normal-function B-bus I/O ports. See function table for normal-mode logic. 1CLKAB, 1CLKBA, 2CLKAB, 2CLKBA Normal-function clock inputs. See function table for normal-mode logic. GND Ground 1LEAB, 1LEBA, 2LEAB, 2LEBA Normal-function latch enables. See function table for normal-mode logic. 1OEAB , 1OEBA, 2OEAB , 2OEBA Normal-function output enables. See function table for normal-mode logic. An internal pullup at each terminal forces the terminal to a high level if left unconnected. TCK Test clock. One of four terminals required by IEEE Standard 1149.1-1990. Test operations of the device are synchronous to TCK. Data is captured on the rising edge of TCK and outputs change on the falling edge of TCK. TDI Test data input. One of four terminals required by IEEE Standard 1149.1-1990. TDI is the serial input for shifting data through the instruction register or selected data register. An internal pullup forces TDI to a high level if left unconnected. TDO Test data output. One of four terminals required by IEEE Standard 1149.1-1990. TDO is the serial output for shifting data through the instruction register or selected data register. TMS Test mode select. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the device through its TAP controller states. An internal pullup forces TMS to a high level if left unconnected. VCC Supply voltage
control signals for the test structures in the device. Figure 1 shows the TAP-controller state diagram. boundary-control register, a 1-bit bypass register, and a 32-bit device identification register. Figure 1. TAP-Controller State Diagram
3.3-V ABT SCAN TEST DEVICE WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS669 – JULY 1996
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The TAP controller is a synchronous finite state machine that provides test-control signals throughout the device. The state diagram shown in Figure 1 is in accordance with IEEE Standard 1149.1-1990. The TAP controller proceeds through its states based on the level of TMS at the rising edge of TCK. As shown, the TAP controller consists of 16 states. There are six stable states (indicated by a looping arrow in the state diagram) and ten unstable states. A stable state is a state the TAP controller can retain for consecutive TCK cycles. Any state that does not meet this criterion is an unstable state. There are two main paths through the state diagram: one to access and control the selected data register and one to access and control the instruction register. Only one register can be accessed at a time. Test-Logic-Reset The device powers up in the Test-Logic-Reset state. In the stable Test-Logic-Reset state, the test logic is reset and is disabled so that the normal logic function of the device is performed. The instruction register is reset to an opcode that selects the optional IDCODE instruction, if supported, or the BYPASS instruction. Certain data registers can also be reset to their power-up values. The state machine is constructed such that the TAP controller returns to the Test-Logic-Reset state in no more than five TCK cycles if TMS is left high. TMS has an internal pullup resistor that forces it high if left unconnected or if a board defect causes it to be open circuited. For the SN54LVT18502, the instruction register is reset to the binary value 10000001, which selects the IDCODE instruction. Bits 47–44 in the boundary-scan register are reset to logic 1, ensuring that these cells that control A-port and B-port outputs, are set to benign values (i.e., if test mode were invoked the outputs would be at the high-impedance state). Reset value of other bits in the boundary-scan register should be considered indeterminate. The boundary-control register is reset to the binary value 010, which selects the PSA test operation. Run-Test/Idle The TAP controller must pass through the Run-Test/Idle state (from Test-Logic-Reset) before executing any test operations. The Run-Test/Idle state also can be entered following data-register or instruction-register scans. Run-Test/Idle is a stable state in which the test logic can be actively running a test or can be idle. The test operations selected by the boundary-control register are performed while the TAP controller is in the Run-Test/Idle state. Select-DR-Scan, Select-lR-Scan No specific function is performed in the Select-DR-Scan and Select-lR-Scan states, and the TAP controller exits either of these states on the next TCK cycle. These states allow the selection of either data-register scan or instruction-register scan. Capture-DR When a data-register scan is selected, the TAP controller must pass through the Capture-DR state. In the Capture-DR state, the selected data register can capture a data value as specified by the current instruction. Such capture operations occur on the rising edge of TCK, upon which the TAP controller exits the Capture-DR state.
3.3-V ABT SCAN TEST DEVICE WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS669 – JULY 1996 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Shift-DR Upon entry to the Shift-DR state, the data register is placed in the scan path between TDI and TDO. On the first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to the logic level present in the least-significant bit of the selected data register. While in the stable Shift-DR state, data is serially shifted through the selected data register on each TCK cycle. The first shift occurs on the first rising edge of TCK after entry to the Shift-DR state (i.e., no shifting occurs during the TCK cycle in which the TAP controller changes from Capture-DR to Shift-DR or from Exit2-DR to Shift-DR). The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-DR state. Exit1-DR, Exit2-DR The Exit1-DR and Exit2-DR states are temporary states that end a data-register scan. It is possible to return to the Shift-DR state from either Exit1-DR or Exit2-DR without recapturing the data register. On the first falling edge of TCK after entry to Exit1-DR, TDO goes from the active state to the high-impedance state. Pause-DR No specific function is performed in the stable Pause-DR state, in which the TAP controller can remain indefinitely. The Pause-DR state suspends and resumes data-register scan operations without loss of data. Update-DR If the current instruction calls for the selected data register to be updated with current data, such update occurs on the falling edge of TCK, following entry to the Update-DR state. Capture-IR When an instruction-register scan is selected, the TAP controller must pass through the Capture-IR state. In the Capture-IR state, the instruction register captures its current status value. This capture operation occurs on the rising edge of TCK, upon which the TAP controller exits the Capture-IR state. For the SN54LVT18502, the status value loaded in the Capture-IR state is the fixed binary value 10000001. Shift-IR Upon entry to the Shift-IR state, the instruction register is placed in the scan path between TDI and TDO. On the first falling edge of TCK, TDO goes from the high-impedance state to the active state. TDO enables to the logic level present in the least-significant bit of the instruction register. While in the stable Shift-IR state, instruction data is serially shifted through the instruction register on each TCK cycle. The first shift occurs on the first rising edge of TCK after entry to the Shift-IR state (i.e., no shifting occurs during the TCK cycle in which the TAP controller changes from Capture-IR to Shift-IR or from Exit2-IR to Shift-IR). The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-IR state. Exit1-IR, Exit2-IR The Exit1-IR and Exit2-IR states are temporary states that end an instruction-register scan. It is possible to return to the Shift-IR state from either Exit1-IR or Exit2-IR without recapturing the instruction register. On the first falling edge of TCK after entry to Exit1-IR, TDO goes from the active state to the high-impedance state. Pause-IR No specific function is performed in the stable Pause-IR state, in which the TAP controller can remain indefinitely. The Pause-IR state suspends and resumes instruction-register scan operations without loss of data. Update-IR The current instruction is updated and takes effect on the falling edge of TCK, following entry to the Update-IR state.
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Update-DR), the shadow latches are updated from the shift register. data-register scans, and the source of data to be captured into the selected data register during Capture-DR. defined for SCOPE devices but are not supported by this device default to BYPASS. binary value 10000001, which selects the IDCODE instruction. The IR order of scan is shown in Figure 2. Figure 2. Instruction Register Order of Scan
high-impedance state). Reset values of other BSCs should be considered indeterminate. Table 1. Boundary-Scan Register Configuration
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(RUNT) instruction to implement additional test operations not included in the basic SCOPE instruction set. reset to the binary value 010, which selects the PSA test operation. The BCR order of scan is shown in Figure 3. Figure 3. Boundary-Control Register Order of Scan Capture-DR, the bypass register captures a logic 0. The bypass register order of scan is shown in Figure 4. Figure 4. Bypass Register Order of Scan
part number, and version of this device. (during Capture-DR state) in the IDR to identify this device as Texas Instruments SN54LVT18502. The IDR order of scan is from TDI through bits 31–0 to TDO. Table 2 shows the IDR bits and their significance. Table 2. Device-Identification Register Configuration
31 VERSION3 27 PARTNUMBER15 11 MANUFACTURER10 †
30 VERSION2 26 PARTNUMBER14 10 MANUFACTURER09 †
29 VERSION1 25 PARTNUMBER13 9 MANUFACTURER08 †
28 VERSION0 24 PARTNUMBER12 8 MANUFACTURER07 †
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Table 3. Instruction-Register Opcodes
00000000 EXTEST Boundary scan Boundary scan Test
10000001 IDCODE Identification read Device identification Normal
10000010 SAMPLE/PRELOAD Sample boundary Boundary scan Normal
00000011 BYPASS ‡ Bypass scan Bypass Normal
10000100 BYPASS ‡ Bypass scan Bypass Normal
00000101 BYPASS ‡ Bypass scan Bypass Normal
00000110 HIGHZ Control boundary to high impedance Bypass Modified test
10000111 CLAMP Control boundary to 1/0 Bypass Test
10001000 BYPASS ‡ Bypass scan Bypass Normal
00001001 RUNT Boundary-run test Bypass Test
00001010 READBN Boundary read Boundary scan Normal
10001011 READBT Boundary read Boundary scan Test
00001100 CELLTST Boundary self test Boundary scan Normal
10001101 TOPHIP Boundary toggle outputs Bypass Test
10001110 SCANCN Boundary-control register scan Boundary control Normal
00001111 SCANCT Boundary-control register scan Boundary control Test
† Bit 7 is used to maintain even parity in the 8-bit instruction. of the BSR). When a given output enable is active (logic 0), the associated I/O pins operate in the output mode. Otherwise, the I/O pins operate in the input mode. The device operates in the test mode. scan path. The device operates in the normal mode. associated with I/O pins in the output mode. The device operates in the normal mode.
3.3-V ABT SCAN TEST DEVICE WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS669 – JULY 1996 13POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 bypass scan This instruction conforms to the IEEE Standard 1149.1-1990 BYPASS instruction. The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device operates in the normal mode. control boundary to high impedance This instruction conforms to the IEEE Standard 1149.1a-1993 HIGHZ instruction. The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device operates in a modified test mode in which all device I/O pins are placed in the high-impedance state, the device input pins remain operational, and the normal on-chip logic function is performed. control boundary to 1/0 This instruction conforms to the IEEE Standard 1149.1a-1993 CLAMP instruction. The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. Data in the I/O BSCs for pins in the output mode is applied to the device I/O pins. The device operates in the test mode. boundary-run test The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device operates in the test mode. The test operation specified in the BCR is executed during Run-Test/Idle. The five test operations decoded by the BCR are: sample inputs/toggle outputs (TOPSIP), PRPG, PSA, simultaneous PSA and PRPG (PSA/PRPG), and simultaneous PSA and binary count up (PSA/COUNT). boundary read The BSR is selected in the scan path. The value in the BSR remains unchanged during Capture-DR. This instruction is useful for inspecting data after a PSA operation. boundary self test The BSR is selected in the scan path. All BSCs capture the inverse of their current values during Capture-DR. In this way, the contents of the shadow latches can be read out to verify the integrity of both shift-register and shadow-latch elements of the BSR. The device operates in the normal mode. boundary toggle outputs The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. Data in the shift-register elements of the selected output-mode BSCs is toggled on each rising edge of TCK in Run-Test/Idle and is then updated in the shadow latches and thereby applied to the associated device I/O pins on each falling edge of TCK in Run-Test/Idle. Data in the input-mode BSCs remains constant. Data appearing at the device input or I/O pins is not captured in the input-mode BSCs. The device operates in the test mode. boundary-control-register scan The BCR is selected in the scan path. The value in the BCR remains unchanged during Capture-DR. This operation must be performed before a boundary-run test operation to specify which test operation is to be executed.
3.3-V ABT SCAN TEST DEVICE WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS669 – JULY 1996
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boundary-control-register opcode description The BCR opcodes are decoded from BCR bits 2–0, as shown in Table 4. The selected test operation is performed while the RUNT instruction is executed in the Run-Test/Idle state. The following descriptions detail the operation of each BCR instruction and illustrate the associated PSA and PRPG algorithms. Table 4. Boundary-Control Register Opcodes X00 Sample inputs/toggle outputs (TOPSIP) X01 Pseudo-random pattern generation/36-bit mode (PRPG) X10 Parallel-signature analysis/36-bit mode (PSA)
011 Simultaneous PSA and PRPG/18-bit mode (PSA/PRPG)
111 Simultaneous PSA and binary count up/18-bit mode (PSA/COUNT)
While the control input BSCs (bits 47–36) are not included in the toggle, PSA, PRPG, or COUNT algorithms, the output-enable BSCs (bits 47–44 of the BSR) control the drive state (active or high impedance) of the selected device output pins. These BCR instructions are only valid when both bytes of the device are operating in one direction of data flow (i.e., 1OEAB ≠ 1OEBA and 2OEAB ≠ 2OEBA ) and in the same direction of data flow (i.e., 1OEAB = 2OEAB and 1OEBA = 2OEBA ). Otherwise, the bypass instruction is operated. sample inputs/toggle outputs (TOPSIP) Data appearing at the selected device input-mode I/O pins is captured in the shift-register elements of the associated BSCs on each rising edge of TCK. Data in the shift-register elements of the selected output-mode BSCs is toggled on each rising edge of TCK, updated in the shadow latches, and applied to the associated device I/O pins on each falling edge of TCK.
patterns are generated. An initial seed value should be scanned into the BSR before performing this operation. A seed value of all zeroes does not produce additional patterns. Figure 5. 36-Bit PRPG Configuration (1OEAB = 2OEAB = 0, 1OEBA = 2OEBA = 1)
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Figure 6. 36-Bit PRPG Configuration (1OEAB = 2OEAB = 1, 1OEBA = 2OEBA = 0)
seed value should be scanned into the BSR before performing this operation. Figure 7. 36-Bit PSA Configuration (1OEAB = 2OEAB = 0, 1OEBA = 2OEBA = 1)
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Figure 8. 36-Bit PSA Configuration (1OEAB = 2OEAB = 1, 1OEBA = 2OEBA = 0)
performing this operation. A seed value of all zeroes does not produce additional patterns. Figure 9. 18-Bit PSA/PRPG Configuration (1OEAB = 2OEAB = 0, 1OEBA = 2OEBA = 1)
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Figure 10. 18-Bit PSA/PRPG Configuration (1OEAB = 2OEAB = 1, 1OEBA = 2OEBA = 0)
Figure 11. 18-Bit PSA/COUNT Configuration (1OEAB = 2OEAB = 0, 1OEBA = 2OEBA = 1)
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Figure 12. 18-Bit PSA/COUNT Configuration (1OEAB = 2OEAB = 1, 1OEBA = 2OEBA = 0)
by changing the value of TMS on the falling edge of TCK and then applying a rising edge to TCK. operation of the test circuitry during each TCK cycle. Table 5. Explanation of Timing Example
2 Run-Test/Idle
3 Select-DR-Scan
4 Select-IR-Scan
on the rising edge of TCK as the TAP controller advances to the next state. TCK cycle. The last bit of the instruction is shifted as the TAP controller advances from Shift-IR to Exit1-IR. 14 Exit1-IR TDO becomes inactive (goes to the high-impedance state) on the falling edge of TCK. 15 Update-IR The IR is updated with the new instruction (BYPASS) on the falling edge of TCK.
16 Select-DR-Scan
on the rising edge of TCK as the TAP controller advances to the next state. 19–20 Shift-DR The binary value 101 is shifted in via TDI, while the binary value 010 is shifted out via TDO. 21 Exit1-DR TDO becomes inactive (goes to the high-impedance state) on the falling edge of TCK. 22 Update-DR The selected data register is updated with the new data on the falling edge of TCK.
23 Select-DR-Scan
24 Select-IR-Scan
25 Test-Logic-Reset Test operation completed
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3 State (TDO) or Don’t Care (TDI)
Figure 13. Timing Example implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings can be exceeded if the input and output clamp-current ratings are observed.
- This current only flows when the output is in the high state and VO > VCC .
3.3-V ABT SCAN TEST DEVICE WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS669 – JULY 1996 25POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT VIK VCC = 2.7 V, II = –18 mA –1.2 V VCC = MIN to MAX‡, IOH = –100 mA VCC –0.2 VOH VCC = 2.7 V, IOH = –3 mA 2.4 VVOH VCC =3V IOH = –8 mA 2.4 V VCC = 3 V IOH = –24 mA 2 VCC =27V IOL = 100 mA 0.2 VCC = 2.7 V IOL = 24 mA 0.5 VOL IOL = 16 mA 0.4 V VCC = 3 V IOL = 32 mA 0.5 IOL = 48 mA 0.55 CLK LE TCK VCC = 3.6 V, VI = VCC or GND ±1 CLK , LE, TCK VCC = 0 or MAX‡, VI = 5.5 V 10 VI = 5.5 V 50 II OE, TDI, TMS VCC = 3.6 V VI = VCC 1 mAII VI = 0 –25 –100 mA VI = 5.5 V 20 A or B ports§ VCC = 3.6 V VI = VCC 1 VI = 0 –5 II(h ld)¶ Ao rB ports VCC =3V VI = 0.8 V 75 500 mAII(hold)¶ A or B ports VCC = 3 V VI = 2 V –75 –500 mA IOZH TDO VCC = 3.6 V, VO = 3 V 50 mA IOZL TDO VCC = 3.6 V, VO = 0.5 V –50 mA IOZPU TDO VCC = 0 to 1.5 V, VO = 0.5 V or 3 V ±50 mA IOZPD TDO VCC = 1.5 V to 0, VO = 0.5 V or 3 V ± 50 mA VCC = 3.6 V, Outputs high 0.7 3 ICC VCC = 3.6 V, IO = 0, Outputs low 21 30 mA VI = VCC or GND Outputs disabled 0.7 3 DICC # VCC = 3 V to 3.6 V, One input at VCC – 0.6 V, Other inputs at VCC or GND 0.2 mA C i VI = 3 V or 0 4 pF C io VO = 3 V or 0 11 pF C o VO = 3 V or 0 8 pF † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. § Unused pins at VCC or GND ¶ The parameter II(hold) includes the off-state output leakage current. # This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
3.3-V ABT SCAN TEST DEVICE WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS669 – JULY 1996
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timing requirements over recommended operating free-air temperature range (unless otherwise noted) (normal mode) (see Figure 14)123 VCC = 3.3 V ± 0.3 V VCC = 2.7 V UNIT MIN MAX MIN MAX fclock Clock frequency CLKAB or CLKBA 0 90 0 80 MHz t Pulse duration CLKAB or CLKBA high or low 6.5 6.7 nstw Pulse duration LEAB or LEBA high 2.4 2.4 ns A before CLKAB↑ or B before CLKBA↑ 3.6 4 tsu Setup time A before LEAB↓ or B before LEBA↓ CLK high 1.2 0.6 ns A before LEAB ↓ or B before LEBA ↓ CLK low 1.4 1.5 th Hold time A after CLKAB↑ or B after CLKBA↑ 1.2 0.8 nsth Hold time A after LEAB↓ or B after LEBA↓ 4.9 5.4 ns timing requirements over recommended operating free-air temperature range (unless otherwise noted) (test mode) (see Figure 14) VCC = 3.3 V ± 0.3 V VCC = 2.7 V UNIT MIN MAX MIN MAX fclock Clock frequency TCK 0 50 0 40 MHz tw Pulse duration TCK high or low 12 14 ns A, B, CLK, LE, or OE before TCK↑ 8 9 tsu Setup time TDI before TCK↑ 3.5 4.5 ns TMS before TCK↑ 3 4 A, B, CLK, LE, or OE after TCK↑ 1.7 1.1 th Hold time TDI after TCK↑ 1.5 0.8 ns TMS after TCK↑ 1.5 0.6 td Delay time Power up to TCK↑ 50* 50* ns tr Rise time VCC power up 1* 1* ms * On products compliant to MIL-PRF-38535, this parameter is not production tested.
3.3-V ABT SCAN TEST DEVICE WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS669 – JULY 1996 27POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (normal mode) (see Figure 14)123 PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 3.3 V ± 0.3 V VCC = 2.7 V UNIT(INPUT) (OUTPUT) MIN MAX MIN MAX fmax CLKAB or CLKBA 90 80 MHz tPLH Ao rB Bo rA 1.5 6.8 8.4 ns tPHL A or B B or A 1.5 6.8 8.4 ns tPLH CLKAB or CLKBA Bo rA 2 9 10 ns tPHL CLKAB or CLKBA B or A 2 8.5 9.4 ns tPLH LEAB or LEBA Bo rA 2.5 10.8 12.5 ns tPHL LEAB or LEBA B or A 2.5 8.6 9.4 ns tPZH OEAB or OEBA Bo rA 2 10.5 11.5 ns tPZL OEAB or OEBA B or A 2 11 12 ns tPHZ OEAB or OEBA Bo rA 3 10.8 11.5 ns tPLZ OEAB or OEBA B or A 2.5 9.9 10.6 ns switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (test mode) (see Figure 14) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 3.3 V ± 0.3 V VCC = 2.7 V UNIT(INPUT) (OUTPUT) MIN MAX MIN MAX fmax TCK 50 40 MHz tPLH TCK ↓ Ao rB 3 18 20 ns tPHL TCK ↓ A or B 3 18 20 ns tPLH TCK ↓ TDO 2 6.6 9 ns tPHL TCK ↓ TDO 2.5 8 9 ns tPZH TCK ↓ Ao rB 5 20 23 ns tPZL TCK ↓ A or B 5 20 23 ns tPZH TCK ↓ TDO 1.5 6.7 8 ns tPZL TCK ↓ TDO 2 7 8.5 ns tPHZ TCK ↓ Ao rB 4 22 24 ns tPLZ TCK ↓ A or B 4 21 23 ns tPHZ TCK ↓ TDO 2.5 8.5 10 ns tPLZ TCK ↓ TDO 2 8 9.5 ns
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NOTES: A. C L includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 W , tr ≤ 2.5 ns, tf≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 14. Load Circuit and Voltage Waveforms
Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) SNJ54LVT18502HV OBSOLETE CFP HV 68 TBD Call TI Call TI (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54LVT18502 :
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